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| author | Tingting Meng <tingting.meng@altera.com> | 2025-03-10 15:29:41 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:40 +0800 |
| commit | 1f8d5085e985884ae1c82254d6e1af231f9d9e8b (patch) | |
| tree | de57a8d915b89f720629a5b9217421dec98a694a /tools/u_boot_pylib/test_util.py | |
| parent | 3d54b52addc0c8c58a7f9aa97c6c145d773a1e0e (diff) | |
arm: socfpga: agilex5: Add MMU mapping region
MMU mapping regions were added for the second and third DDR memory banks.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions