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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-04-03 10:52:51 +0300 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-04-12 11:12:06 +0300 |
| commit | 69dffab9416c45f0341675aafd2c84e11df2d749 (patch) | |
| tree | a8f4d35d7c003628e126238c719042065db7a749 /tools/u_boot_pylib/test_util.py | |
| parent | 9ee12daa591b8adefa8ae221295a85e2ee467742 (diff) | |
ARM: tegra114: clock: avoid touching DISP clocks on init
The clock initialization routine sets the DISP* clock parent to PLLC,
resulting in DC failure in the case when PLLD was previously configured.
This issue disrupts chainloading and to prevent failures caused by DISP*
clock parent conflicts, clock initialization should not modify DISP*. The
DC driver handles DISP* configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions