diff options
58 files changed, 1798 insertions, 185 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 61a5336b2d..94dcb7df2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1148,6 +1148,7 @@ Chong Huang <chuang@ucrobotics.com> Macpaul Lin <macpaul@andestech.com> ADP-AG101 N1213 (AG101 SoC) + ADP-AG101P N1213 (AG101P XC5 FPGA) ######################################################################### # End of MAINTAINERS list # diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index 45221ee78a..190342062a 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -41,7 +41,7 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { *(.data*) } . = ALIGN(4); diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index a6f1c93494..7b52b989bc 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -26,4 +26,18 @@ extern unsigned int __machine_arch_type; # define machine_is_adpag101() (0) #endif +#define MACH_TYPE_ADPAG101P 1 + +#ifdef CONFIG_ARCH_ADPAG101P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG101P +# endif +# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P) +#else +# define machine_is_adpag101p() (1) +#endif + #endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a09eb91406..253bf08b6a 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -103,6 +103,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 puts("Work-around for Erratum NMG_LBC103 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG ETSEC129 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 0a4ce538f3..b9a8193759 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -317,7 +317,6 @@ int cpu_init_r(void) volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; - uint l2srbar; u32 l2siz_field; svr = get_svr(); @@ -385,8 +384,8 @@ int cpu_init_r(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); - l2srbar = l2cache->l2srbar0; #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) + u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 4ef3c9a8a5..091af7c95a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -71,7 +71,7 @@ void cpu_init_early_f(void) #endif #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - u32 *l2srbar, *dst, *src; + u32 *dst, *src; void (*setup_ifc_sram)(void); #endif @@ -137,7 +137,7 @@ void cpu_init_early_f(void) dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; for (i = 0; i < 1024; i++) - *l2srbar++ = *src++; + *dst++ = *src++; setup_ifc_sram(); diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 89ed5b47fc..4b52dad56c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -495,7 +495,6 @@ void fsl_serdes_init(void) int cfg; serdes_corenet_t *srds_regs; int lane, bank, idx; - enum srds_prtcl lane_prtcl; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -507,6 +506,7 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -516,6 +516,7 @@ void fsl_serdes_init(void) */ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#endif /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -617,7 +618,10 @@ void fsl_serdes_init(void) } } +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl; + idx = serdes_get_lane_idx(lane); lane_prtcl = serdes_get_prtcl(cfg, lane); @@ -729,6 +733,7 @@ void fsl_serdes_init(void) #endif } +#endif #ifdef DEBUG puts("\n"); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5e0d78d006..7bd5cc0b0f 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -319,6 +319,55 @@ l2_disabled: #endif /* CONFIG_MPC8569 */ /* + * Search for the TLB that covers the code we're executing, and shrink it + * so that it covers only this 4K page. That will ensure that any other + * TLB we create won't interfere with it. We assume that the TLB exists, + * which is why we don't check the Valid bit of MAS1. + * + * This is necessary, for example, when booting from the on-chip ROM, + * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. + * If we don't shrink this TLB now, then we'll accidentally delete it + * in "purge_old_ccsr_tlb" below. + */ + bl nexti /* Find our address */ +nexti: mflr r1 /* R1 = our PC */ + li r2, 0 + mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ + isync + msync + tlbsx 0, r1 /* This must succeed */ + + /* Set the size of the TLB to 4KB */ + mfspr r3, MAS1 + li r2, 0xF00 + andc r3, r3, r2 /* Clear the TSIZE bits */ + ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l + mtspr MAS1, r3 + + /* + * Set the base address of the TLB to our PC. We assume that + * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. + */ + lis r3, MAS2_EPN@h + ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ + + and r1, r1, r3 /* Our PC, rounded down to the nearest page */ + + mfspr r2, MAS2 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS2, r2 /* Set the EPN to our PC base address */ + + mfspr r2, MAS3 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS3, r2 /* Set the RPN to our PC base address */ + + isync + msync + tlbwe + +/* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit * system, where we want to move CCSR to near the top of 36-bit address space. @@ -352,6 +401,8 @@ purge_old_ccsr_tlb: li r1, 0 mtspr MAS6, r1 /* Search the current address space and PID */ + isync + msync tlbsx 0, r8 mfspr r1, MAS1 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ @@ -359,6 +410,8 @@ purge_old_ccsr_tlb: rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ mtspr MAS1, r1 + isync + msync tlbwe 1: @@ -387,7 +440,7 @@ create_ccsr_new_tlb: tlbwe /* - * Create a TLB for the old location of CCSR. Register R9 is reserved + * Create a TLB for the current location of CCSR. Register R9 is reserved * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: @@ -407,6 +460,33 @@ create_ccsr_old_tlb: msync tlbwe + /* + * We have a TLB for what we think is the current (old) CCSR. Let's + * verify that, otherwise we won't be able to move it. + * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only + * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. + */ +verify_old_ccsr: + lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l +#ifdef CONFIG_FSL_CORENET + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ + slwi r1, r1, 12 +#endif + + cmpl 0, r0, r1 + + /* + * If the value we read from CCSRBARL is not what we expect, then + * enter an infinite loop. This will at least allow a debugger to + * halt execution and examine TLBs, etc. There's no point in going + * on. + */ +infinite_debug_loop: + bne infinite_debug_loop + #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) @@ -446,7 +526,7 @@ create_temp_law: */ read_old_ccsrbar: lwz r0, 0(r9) /* CCSRBARH */ - lwz r0, 4(r9) /* CCSRBARH */ + lwz r0, 4(r9) /* CCSRBARL */ isync /* diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 01a3561fa0..929f6a607e 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -172,7 +172,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, void disable_tlb(u8 esel) { - u32 _mas0, _mas1, _mas2, _mas3, _mas7; + u32 _mas0, _mas1, _mas2, _mas3; free_tlb_cam(esel); @@ -180,14 +180,13 @@ void disable_tlb(u8 esel) _mas1 = 0; _mas2 = 0; _mas3 = 0; - _mas7 = 0; mtspr(MAS0, _mas0); mtspr(MAS1, _mas1); mtspr(MAS2, _mas2); mtspr(MAS3, _mas3); #ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); + mtspr(MAS7, 0); #endif asm volatile("isync;msync;tlbwe;isync"); @@ -252,16 +251,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) unsigned int tlb_size; unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; + unsigned int max_cam; u64 size, memsize = (u64)memsize_in_meg << 20; #ifdef CONFIG_SYS_PPC_DDR_WIMGE wimge = CONFIG_SYS_PPC_DDR_WIMGE; #endif size = min(memsize, CONFIG_MAX_MEM_MAPPED); - - /* Convert (4^max) kB to (2^max) bytes */ - max_cam = max_cam * 2 + 10; + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; + } else { + /* Convert (2^max) kB to (2^max) bytes */ + max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10; + } for (i = 0; size && i < 8; i++) { int ram_tlb_index = find_free_tlbcam(); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 15cd375ae3..2067d53ad2 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -672,7 +672,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, rcw_en = 1; ap_en = popts->ap_en; } else { - rcw_en = 0; ap_en = 0; } @@ -702,9 +701,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) -#ifdef CONFIG_FSL_DDR3 | ((rcw_en & 0x1) << 2) -#endif | ((md_en & 0x1) << 0) ); debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); @@ -745,7 +742,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_FSL_DDR3 if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < 4; i++) { + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; else @@ -944,7 +941,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < 4; i++) { + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) rtt = popts->rtt_override_value; else diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 4dc748b951..00ec57be1f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -483,7 +483,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) const struct dynamic_odt *pdodt = odt_unknown; +#endif ulong ddr_freq; /* @@ -493,6 +495,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) /* Chip select options. */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { switch (pdimm[0].n_ranks) { @@ -546,6 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, break; } } +#endif /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 112c603532..d07ae1b4fe 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -87,13 +87,12 @@ void ft_fixup_num_cores(void *blob) { #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ #ifdef CONFIG_HAS_FSL_DR_USB -static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type) +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type, int start_offset) { const char *compat = "fsl-usb2-dr"; const char *prop_mode = "dr_mode"; const char *prop_type = "phy_type"; - static int start_offset = -1; int node_offset; int err; @@ -102,7 +101,7 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, if (node_offset < 0) { printf("WARNING: could not find compatible node %s: %s.\n", compat, fdt_strerror(node_offset)); - return; + return -1; } if (mode) { @@ -121,16 +120,18 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, prop_type, compat, fdt_strerror(err)); } - start_offset = node_offset; + return node_offset; } void fdt_fixup_dr_usb(void *blob, bd_t *bd) { const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "umti" }; + const char *phys[] = { "ulpi", "utmi" }; const char *mode = NULL; const char *phy_type = NULL; char usb1_defined = 0; + int usb_mode_off = -1; + int usb_phy_off = -1; char str[5]; int i, j; @@ -153,11 +154,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } if (mode_idx >= 0) - fdt_fixup_usb_mode_phy_type(blob, - modes[mode_idx], NULL); + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + modes[mode_idx], NULL, usb_mode_off); if (phy_idx >= 0) - fdt_fixup_usb_mode_phy_type(blob, - NULL, phys[phy_idx]); + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, phys[phy_idx], usb_phy_off); if (!strcmp(str, "usb1")) usb1_defined = 1; if (mode_idx < 0 && phy_idx < 0) @@ -165,11 +166,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } if (!usb1_defined) { + int usb_off = -1; mode = getenv("usb_dr_mode"); phy_type = getenv("usb_phy_type"); if (!mode && !phy_type) return; - fdt_fixup_usb_mode_phy_type(blob, mode, phy_type); + fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off); } } #endif /* CONFIG_HAS_FSL_DR_USB */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index d78962ff87..587576bacf 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -107,7 +107,7 @@ void init_early_memctl_regs(void) void upmconfig(uint upm, uint *table, uint size) { fsl_lbc_t *lbc = LBC_BASE_ADDR; - int i, mdr, mad, old_mad = 0; + int i, mad, old_mad = 0; u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK); u32 msel = BR_UPMx_TO_MSEL(upm); u32 *mxmr = &lbc->mamr + upm; @@ -138,7 +138,7 @@ void upmconfig(uint upm, uint *table, uint size) for (i = 0; i < size; i++) { out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i); out_be32(&lbc->mdr, table[i]); - mdr = in_be32(&lbc->mdr); + (void)in_be32(&lbc->mdr); *dummy = 0; do { mad = in_be32(mxmr) & MxMR_MAD_MSK; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c3d6ba9e99..981d639796 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 +#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index ef5076b24d..209103e3ce 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -392,17 +392,17 @@ extern void print_bats(void); */ #define MAS0_TLBSEL_MSK 0x30000000 -#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) #define MAS0_ESEL_MSK 0x0FFF0000 -#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) +#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) & 0x00000FFF) #define MAS1_VALID 0x80000000 #define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) +#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) #define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) -#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10))) +#define MAS1_TSIZE(x) (((x) << 8) & 0x00000F00) +#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10)) #define MAS2_EPN 0xFFFFF000 #define MAS2_X0 0x00000040 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 1b96b84dcb..4e32639821 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -513,7 +513,13 @@ #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ +#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ +#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ +#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ +#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ diff --git a/board/AndesTech/adp-ag101p/Makefile b/board/AndesTech/adp-ag101p/Makefile new file mode 100644 index 0000000000..03c3ff41e8 --- /dev/null +++ b/board/AndesTech/adp-ag101p/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := adp-ag101p.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c new file mode 100644 index 0000000000..8dd20430d4 --- /dev/null +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <faraday/ftsdc010.h> +#include <faraday/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ + +int board_init(void) +{ + /* + * refer to BOOT_PARAMETER_PA_BASE within + * "linux/arch/nds32/include/asm/misc_spec.h" + */ + gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + + ftsmc020_init(); /* initialize Flash */ + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size((void *)sdram_base, expected_size); + + gd->ram_size = actual_size; + + if (expected_size != actual_size) { + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + } + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ftmac100_initialize(bd); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else { + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + ftsdc010_mmc_init(0); + return 0; +} diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 6f221aff26..8a09f99cc4 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -28,13 +28,12 @@ #if defined(CONFIG_OF_BOARD_SETUP) static void cds_pci_fixup(void *blob) { - int node, tmp[2]; + int node; const char *path; int len, slot, i; u32 *map = NULL; node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { path = fdt_getprop(blob, node, "pci0", NULL); if (path) { diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 89d8810f74..6acbc361a3 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -31,12 +31,81 @@ #include "pixis.h" #endif +/* define for SYS CLK or CLK1Frequency */ +#define TTL 1 +#define CLK2 0 +#define CRYSTAL 0 +#define MAX_VDW (511 + 8) +#define MAX_RDW (127 + 2) +#define MIN_VDW (4 + 8) +#define MIN_RDW (1 + 2) +#define NUM_OD_SETTING 8 +/* + * These defines cover the industrial temperature range part, + * for commercial, change below to 400000 and 55000, respectively + */ +#define MAX_VCO 360000 +#define MIN_VCO 60000 + /* decode S[0-2] to Output Divider (OD) */ static u8 ics307_s_to_od[] = { 10, 2, 8, 4, 5, 7, 3, 6 }; /* + * Find one solution to generate required frequency for SYSCLK + * out_freq: KHz, required frequency to the SYSCLK + * the result will be retuned with component RDW, VDW, OD, TTL, + * CLK2 and crystal + */ +unsigned long ics307_sysclk_calculator(unsigned long out_freq) +{ + const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; + unsigned long tmp_out, diff, result = 0; + int found = 0; + + for (odp = 0; odp < NUM_OD_SETTING; odp++) { + od = ics307_s_to_od[odp]; + if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) + continue; + for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { + /* Calculate the VDW */ + vdw = out_freq * 1000 * od * rdw / (input_freq * 2); + if (vdw > MAX_VDW) + vdw = MAX_VDW; + if (vdw < MIN_VDW) + continue; + /* Calculate the temp out frequency */ + tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); + diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); + /* + * calculate the percent, the precision is 1/1000 + * If greater than 1/1000, continue + * otherwise, we think the solution is we required + */ + if (diff * 1000 / out_freq > 1) + continue; + else { + s_vdw = vdw; + s_rdw = rdw; + s_odp = odp; + found = 1; + break; + } + } + } + + if (found) + result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | + CLK2 << 19 | TTL << 21 | CRYSTAL << 22; + + debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, + ics307_s_to_od[s_odp]); + return result; +} + +/* * Calculate frequency being generated by ICS307-02 clock chip based upon * the control bytes being programmed into it. */ diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h index db3dbc41f7..37579124bc 100644 --- a/board/freescale/common/ics307_clk.h +++ b/board/freescale/common/ics307_clk.h @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,8 +23,10 @@ #define __ICS_CLK_H_ 1 #ifndef __ASSEMBLY__ + extern unsigned long get_board_sys_clk(void); extern unsigned long get_board_ddr_clk(void); +extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); #endif #endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 765f0359bf..276ae3c5cf 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -156,9 +156,29 @@ static void pixis_dump_regs(void) } #endif +void pixis_sysclk_set(unsigned long sysclk) +{ + unsigned long freq_word; + u8 sclk0, sclk1, sclk2; + + freq_word = ics307_sysclk_calculator(sysclk); + sclk2 = freq_word & 0xff; + sclk1 = (freq_word >> 8) & 0xff; + sclk0 = (freq_word >> 16) & 0xff; + + /* set SYSCLK enable bit */ + PIXIS_WRITE(vcfgen0, 0x01); + + /* SYSCLK to required frequency */ + PIXIS_WRITE(sclk[0], sclk0); + PIXIS_WRITE(sclk[1], sclk1); + PIXIS_WRITE(sclk[2], sclk2); +} + int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int i; + unsigned long sysclk; char *p_altbank = NULL; #ifdef DEBUG char *p_dump = NULL; @@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) continue; } #endif + if (strcmp(argv[i], "sysclk") == 0) { + sysclk = simple_strtoul(argv[i + 1], NULL, 0); + i += 1; + pixis_sysclk_set(sysclk); + continue; + } unknown_param = argv[i]; } @@ -219,4 +245,5 @@ U_BOOT_CMD( #ifdef DEBUG "pixis_reset dump - display the PIXIS registers\n" #endif + "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n" ); diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index a35b5cfe3e..8d07061c36 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr) { int i, j; int mulconst; - int intarr_len, no_dec = 0; + int no_dec = 0; unsigned long intval = 0, decval = 0; char intarr[3], decarr[3]; @@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr) i++; } - /* Assign length of integer part to intarr_len. */ - intarr_len = i; intarr[i] = '\0'; if (no_dec) { diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a7a5e13af7..962f380383 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 7ff00d1460..1f00c14530 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; int i; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; @@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis) SLOT5, /* 17 - Bank 3:D */ }; - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index a8d57cddde..e5563f7c75 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,6 +33,9 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h> +#include <fsl_mdio.h> +#include <netdev.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -81,12 +84,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -115,7 +116,6 @@ void lbc_sdram_init(void) uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; uint lsdmr_common; puts("LBC SDRAM: "); @@ -137,7 +137,6 @@ void lbc_sdram_init(void) /* * MPC8548 uses "new" 15-16 style addressing. */ - cpu_board_rev = get_cpu_board_revision(); lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516; @@ -287,7 +286,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } -int last_stage_init(void) +void configure_rgmii(void) { unsigned short temp; @@ -295,29 +294,77 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 18); - miiphy_read(CONFIG_TSEC1_NAME, + miiphy_read(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, &temp); temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, temp); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 3); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, 0x8000); } - return 0; + return; } +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif +#ifdef CONFIG_TSEC4 + /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 4); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + configure_rgmii(); + + return pci_eth_init(bis); +} +#endif #if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 225c5d8d07..6e3945eddb 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -147,12 +147,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -302,6 +300,7 @@ pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); + i2c_set_bus_num(orig_i2c_bus); } #ifdef CONFIG_PCI diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 89557d221f..d119c6517f 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -303,12 +303,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 575bdb55ab..6d605139fc 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_NAND_SPL /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 03e9da1940..b9e66f7fa7 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 864b3ce8fb..cfbae69119 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) /* Delete eLBC node as it is muxed with USB2 controller */ diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5ff6ea6aa1..79689199c1 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -25,15 +25,17 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifndef CONFIG_NAND_SPL SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#endif + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4671128afd..a60c5a20a9 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_qe_pins(blob); #endif #endif + +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif } #endif diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 0a1dfa7cc6..4b0d577e2c 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e1a3ea36e9..26095a5455 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -77,12 +77,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index c5fe92e061..98bc7df4c8 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -348,7 +348,7 @@ phys_size_t fixed_sdram(void) void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; + int node; #ifdef CONFIG_PCI const char *path; #endif @@ -356,7 +356,6 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { #ifdef CONFIG_PCI path = fdt_getprop(blob, node, "pci0", NULL); diff --git a/boards.cfg b/boards.cfg index 58bbc621c0..c83d8616e2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -348,6 +348,7 @@ vct_platinumavc_onenand_small mips mips32 vct microna qi_lb60 mips xburst qi_lb60 qi nios2-generic nios2 nios2 nios2-generic altera adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101 +adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101 PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 diff --git a/common/fdt_support.c b/common/fdt_support.c index bdda64d2d7..593f16c162 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -49,8 +49,8 @@ DECLARE_GLOBAL_DATA_PTR; * Convenience function to find a node and return it's property or a * default value if it doesn't exist. */ -u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop, - const u32 dflt) +u32 fdt_getprop_u32_default(const void *fdt, const char *path, + const char *prop, const u32 dflt) { const u32 *val; int off; @@ -61,7 +61,7 @@ u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop, val = fdt_getprop(fdt, off, prop, NULL); if (val) - return *val; + return fdt32_to_cpu(*val); else return dflt; } @@ -372,7 +372,7 @@ static int get_cells_len(void *blob, char *nr_cells_name) const u32 *cell; cell = fdt_getprop(blob, 0, nr_cells_name, NULL); - if (cell && *cell == 2) + if (cell && fdt32_to_cpu(*cell) == 2) return 8; return 4; diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 258be0a908..5b017a910c 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -225,7 +225,7 @@ unsigned int get_i2c_clock(int bus) void i2c_init(int speed, int slaveadd) { - struct fsl_i2c *dev; + const struct fsl_i2c *dev; unsigned int temp; int bus_num, i; diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index ed296ee026..e6467a2d18 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -111,7 +111,6 @@ static int do_command(struct mmc *dev, struct mmc_cmd *cmd) static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize) { u32 *tempbuff = dest; - int i; u64 xfercount = blkcount * blksize; struct mmc_host *host = dev->priv; u32 status, status_err; @@ -121,31 +120,6 @@ static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize) status = readl(&host->base->status); status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_RXOVERR); - while (!status_err && - (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32))) { - if (status & SDI_STA_RXFIFOBR) { - for (i = 0; i < SDI_FIFO_BURST_SIZE; i++) - *(tempbuff + i) = readl(&host->base->fifo); - tempbuff += SDI_FIFO_BURST_SIZE; - xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32); - } - status = readl(&host->base->status); - status_err = status & - (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_RXOVERR); - } - - if (status & SDI_STA_DTIMEOUT) { - printf("Read data timed out, xfercount: %llu, status: 0x%08X\n", - xfercount, status); - return -ETIMEDOUT; - } else if (status & SDI_STA_DCRCFAIL) { - printf("Read data blk CRC error: 0x%x\n", status); - return -EILSEQ; - } else if (status & SDI_STA_RXOVERR) { - printf("Read data RX overflow error\n"); - return -EIO; - } - while ((!status_err) && (xfercount >= sizeof(u32))) { if (status & SDI_STA_RXDAVL) { *(tempbuff) = readl(&host->base->fifo); diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index 78b11900ed..ccf48bbb17 100644 --- a/drivers/mmc/tegra2_mmc.c +++ b/drivers/mmc/tegra2_mmc.c @@ -81,7 +81,8 @@ static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) * 11 = Selects 64-bit Address ADMA2 */ ctrl = readb(&host->reg->hostctl); - ctrl &= ~(3 << 3); /* SDMA */ + ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; + ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; writeb(ctrl, &host->reg->hostctl); /* We do not handle DMA boundaries, so set it to max (512 KiB) */ @@ -103,43 +104,36 @@ static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) * ENBLKCNT[1] : Block Count Enable * ENDMA[0] : DMA Enable */ - mode = (1 << 1) | (1 << 0); + mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | + TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); + if (data->blocks > 1) - mode |= (1 << 5); + mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; + if (data->flags & MMC_DATA_READ) - mode |= (1 << 4); + mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; writew(mode, &host->reg->trnmod); } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) +static int mmc_wait_inhibit(struct mmc_host *host, + struct mmc_cmd *cmd, + struct mmc_data *data, + unsigned int timeout) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; - int flags, i; - unsigned int timeout; - unsigned int mask; - unsigned int retry = 0x100000; - debug(" mmc_send_cmd called\n"); - - /* Wait max 10 ms */ - timeout = 10; - /* * PRNSTS - * CMDINHDAT[1] : Command Inhibit (DAT) - * CMDINHCMD[0] : Command Inhibit (CMD) + * CMDINHDAT[1] : Command Inhibit (DAT) + * CMDINHCMD[0] : Command Inhibit (CMD) */ - mask = (1 << 0); - if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY)) - mask |= (1 << 1); + unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; /* * We shouldn't wait for data inhibit for stop commands, even * though they might use busy signaling */ - if (data) - mask &= ~(1 << 1); + if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) + mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; while (readl(&host->reg->prnsts) & mask) { if (timeout == 0) { @@ -150,6 +144,24 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, udelay(1000); } + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + int flags, i; + int result; + unsigned int mask; + unsigned int retry = 0x100000; + debug(" mmc_send_cmd called\n"); + + result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); + + if (result < 0) + return result; + if (data) mmc_prepare_data(host, data); @@ -175,20 +187,20 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, * 11 = Length 48 Check busy after response */ if (!(cmd->resp_type & MMC_RSP_PRESENT)) - flags = 0; + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; else if (cmd->resp_type & MMC_RSP_136) - flags = (1 << 0); + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; else if (cmd->resp_type & MMC_RSP_BUSY) - flags = (3 << 0); + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; else - flags = (2 << 0); + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; if (cmd->resp_type & MMC_RSP_CRC) - flags |= (1 << 3); + flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; if (cmd->resp_type & MMC_RSP_OPCODE) - flags |= (1 << 4); + flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; if (data) - flags |= (1 << 5); + flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; debug("cmd: %d\n", cmd->cmdidx); @@ -197,7 +209,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, for (i = 0; i < retry; i++) { mask = readl(&host->reg->norintsts); /* Command Complete */ - if (mask & (1 << 0)) { + if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { if (!data) writel(mask, &host->reg->norintsts); break; @@ -209,11 +221,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return TIMEOUT; } - if (mask & (1 << 16)) { + if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { /* Timeout Error */ debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); return TIMEOUT; - } else if (mask & (1 << 15)) { + } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { /* Error Interrupt */ debug("error: %08x cmd %d\n", mask, cmd->cmdidx); return -1; @@ -256,23 +268,44 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } if (data) { + unsigned long start = get_timer(0); + while (1) { mask = readl(&host->reg->norintsts); - if (mask & (1 << 15)) { + if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { /* Error Interrupt */ writel(mask, &host->reg->norintsts); printf("%s: error during transfer: 0x%08x\n", __func__, mask); return -1; - } else if (mask & (1 << 3)) { - /* DMA Interrupt */ + } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { + /* + * DMA Interrupt, restart the transfer where + * it was interrupted. + */ + unsigned int address = readl(&host->reg->sysad); + debug("DMA end\n"); - break; - } else if (mask & (1 << 1)) { + writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, + &host->reg->norintsts); + writel(address, &host->reg->sysad); + } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { /* Transfer Complete */ debug("r/w is done\n"); break; + } else if (get_timer(start) > 2000UL) { + writel(mask, &host->reg->norintsts); + printf("%s: MMC Timeout\n" + " Interrupt status 0x%08x\n" + " Interrupt status enable 0x%08x\n" + " Interrupt signal enable 0x%08x\n" + " Present status 0x%08x\n", + __func__, mask, + readl(&host->reg->norintstsen), + readl(&host->reg->norintsigen), + readl(&host->reg->prnsts)); + return -1; } } writel(mask, &host->reg->norintsts); @@ -310,12 +343,14 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) * ENINTCLK[0] : Internal Clock Enable */ div >>= 1; - clk = (div << 8) | (1 << 0); + clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | + TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); writew(clk, &host->reg->clkcon); /* Wait max 10 ms */ timeout = 10; - while (!(readw(&host->reg->clkcon) & (1 << 1))) { + while (!(readw(&host->reg->clkcon) & + TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { if (timeout == 0) { printf("%s: timeout error\n", __func__); return; @@ -324,7 +359,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) udelay(1000); } - clk |= (1 << 2); + clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; writew(clk, &host->reg->clkcon); debug("mmc_change_clock: clkcon = %08X\n", clk); @@ -375,7 +410,7 @@ static void mmc_reset(struct mmc_host *host) * 1 = reset * 0 = work */ - writeb((1 << 0), &host->reg->swrst); + writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); host->clock = 0; @@ -383,7 +418,7 @@ static void mmc_reset(struct mmc_host *host) timeout = 100; /* hw clears the bit when it's done */ - while (readb(&host->reg->swrst) & (1 << 0)) { + while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { if (timeout == 0) { printf("%s: timeout error\n", __func__); return; @@ -413,12 +448,17 @@ static int mmc_core_init(struct mmc *mmc) * NORMAL Interrupt Status Enable Register init * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable + * [3] ENSTADMAINT : DMA boundary interrupt * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable * [0] ENSTACMDCMPLT : Command Complete Status Enable */ mask = readl(&host->reg->norintstsen); mask &= ~(0xffff); - mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0); + mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | + TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | + TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | + TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | + TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); writel(mask, &host->reg->norintstsen); /* @@ -427,7 +467,7 @@ static int mmc_core_init(struct mmc *mmc) */ mask = readl(&host->reg->norintsigen); mask &= ~(0xffff); - mask |= (1 << 1); + mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; writel(mask, &host->reg->norintsigen); return 0; diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h index 28698e0fc0..671583c422 100644 --- a/drivers/mmc/tegra2_mmc.h +++ b/drivers/mmc/tegra2_mmc.h @@ -68,6 +68,55 @@ struct tegra2_mmc { unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ }; +#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) + +#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) +#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) +#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) + +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) + +#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) +#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) +#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) + +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) + +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) +#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) + +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) + +#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) + +#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) +#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) + +#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) + +#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) + struct mmc_host { struct tegra2_mmc *reg; unsigned int version; /* SDHCI spec. version */ diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 23ef14baf4..846c37249b 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -395,7 +395,6 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512; - u32 n; u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); @@ -405,7 +404,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) printf("\nMMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - n = mmc->block_dev.block_read(dev, blk, cnt, addr); + (void)mmc->block_dev.block_read(dev, blk, cnt, addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 78ffc95c53..160bc0597d 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -19,6 +19,7 @@ #include <tsec.h> #include <fsl_mdio.h> #include <asm/errno.h> +#include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +44,9 @@ static RTXBD rtx __attribute__ ((aligned(8))); #error "rtx must be 64-bit aligned" #endif +static int tsec_send(struct eth_device *dev, + volatile void *packet, int length); + /* Default initializations for TSEC controllers. */ static struct tsec_info_struct tsec_info[] = { @@ -236,6 +240,87 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +/* + * When MACCFG1[Rx_EN] is enabled during system boot as part + * of the eTSEC port initialization sequence, + * the eTSEC Rx logic may not be properly initialized. + */ +void redundant_init(struct eth_device *dev) +{ + struct tsec_private *priv = dev->priv; + tsec_t *regs = priv->regs; + uint t, count = 0; + int fail = 1; + static const u8 pkt[] = { + 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, + 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, + 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, + 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, + 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, + 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, + 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, + 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72}; + + /* Enable promiscuous mode */ + setbits_be32(®s->rctrl, 0x8); + /* Enable loopback mode */ + setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); + /* Enable transmit and receive */ + setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + + do { + tsec_send(dev, (void *)pkt, sizeof(pkt)); + + /* Wait for buffer to be received */ + for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { + if (t >= 10 * TOUT_LOOP) { + printf("%s: tsec: rx error\n", dev->name); + break; + } + } + + if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) + fail = 0; + + rtx.rxbd[rxIdx].length = 0; + rtx.rxbd[rxIdx].status = + RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rxIdx = (rxIdx + 1) % PKTBUFSRX; + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + if (fail) { + printf("loopback recv packet error!\n"); + clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); + udelay(1000); + setbits_be32(®s->maccfg1, MACCFG1_RX_EN); + } + } while ((count++ < 4) && (fail == 1)); + + if (fail) + panic("eTSEC init fail!\n"); + /* Disable promiscuous mode */ + clrbits_be32(®s->rctrl, 0x8); + /* Disable loopback mode */ + clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); +} +#endif + /* Set up the buffers and their descriptors, and bring up the * interface */ @@ -248,6 +333,9 @@ static void startup_tsec(struct eth_device *dev) /* reset the indices to zero */ rxIdx = 0; txIdx = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + uint svr; +#endif /* Point to the buffer descriptors */ out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); @@ -269,6 +357,11 @@ static void startup_tsec(struct eth_device *dev) } rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + redundant_init(dev); +#endif /* Enable Transmit and Receive */ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 1ecb1379a5..3e46e3515f 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -264,13 +264,10 @@ static int uec_open(uec_private_t *uec, comm_dir_e mode) static int uec_stop(uec_private_t *uec, comm_dir_e mode) { - ucc_fast_private_t *uccf; - if (!uec || !uec->uccf) { printf("%s: No handle passed.\n", __FUNCTION__); return -EINVAL; } - uccf = uec->uccf; /* check if the UCC number is in range. */ if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { @@ -325,7 +322,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec, phy_interface_t if_mode, int speed) { phy_interface_t enet_if_mode; - uec_info_t *uec_info; uec_t *uec_regs; u32 upsmr; u32 maccfg2; @@ -335,7 +331,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec, return -EINVAL; } - uec_info = uec->uec_info; uec_regs = uec->uec_regs; enet_if_mode = if_mode; @@ -516,12 +511,10 @@ bus_fail: static void adjust_link(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; - uec_t *uec_regs; struct uec_mii_info *mii_info = uec->mii_info; extern void change_phy_interface_mode(struct eth_device *dev, phy_interface_t mode, int speed); - uec_regs = uec->uec_regs; if (mii_info->link) { /* Now we make sure that we can be in full duplex mode. diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 5a65d92719..b2d294ee88 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -40,11 +40,13 @@ int ehci_hcd_init(void) { struct usb_ehci *ehci; - char usb_phy[5]; const char *phy_type = NULL; size_t len; +#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY + char usb_phy[5]; usb_phy[0] = '\0'; +#endif ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h new file mode 100644 index 0000000000..b4dbd71133 --- /dev/null +++ b/include/andestech/andes_pcu.h @@ -0,0 +1,367 @@ +/* + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Andes Power Control Unit + */ +#ifndef __ANDES_PCU_H +#define __ANDES_PCU_H + +#ifndef __ASSEMBLY__ + +struct pcs { + unsigned int cr; /* PCSx Configuration (clock scaling) */ + unsigned int parm; /* PCSx Parameter*/ + unsigned int stat1; /* PCSx Status 1 */ + unsigned int stat2; /* PCSx Stusts 2 */ + unsigned int pdd; /* PCSx PDD */ +}; + +struct andes_pcu { + unsigned int rev; /* 0x00 - PCU Revision */ + unsigned int spinfo; /* 0x04 - Scratch Pad Info */ + unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ + unsigned int soc_id; /* 0x10 - SoC ID */ + unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ + unsigned int soc_apb; /* 0x18 - SoC APB configuration */ + unsigned int rsvd2; /* 0x1C */ + unsigned int dcsrcr0; /* 0x20 - Driving Capability + and Slew Rate Control 0 */ + unsigned int dcsrcr1; /* 0x24 - Driving Capability + and Slew Rate Control 1 */ + unsigned int dcsrcr2; /* 0x28 - Driving Capability + and Slew Rate Control 2 */ + unsigned int rsvd3; /* 0x2C */ + unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ + unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ + unsigned int dmaes; /* 0x38 - DMA Engine Selection */ + unsigned int rsvd4; /* 0x3C */ + unsigned int oscc; /* 0x40 - OSC Control */ + unsigned int pwmcd; /* 0x44 - PWM Clock divider */ + unsigned int socmisc; /* 0x48 - SoC Misc. */ + unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ + unsigned int bsmcr; /* 0x80 - BSM Controrl */ + unsigned int bsmst; /* 0x84 - BSM Status */ + unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ + unsigned int west; /* 0x8C - Wakeup Event Status */ + unsigned int rsttiming; /* 0x90 - Reset Timing */ + unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ + unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ + struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ + unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ + struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ + unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ + struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ + unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ + struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ + unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ + struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ + unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ + struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ + unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ + struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ + unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ + struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ + unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ + struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ + unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ + unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager + Scratch Pad Memory 0 */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * PCU Revision Register (ro) + */ +#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) +#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) + +/* + * Scratch Pad Info Register (ro) + */ +#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) +#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) + +/* + * SoC ID Register (ro) + */ +#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) +#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) +#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) + +/* + * SoC AHB Configuration Register (ro) + */ +#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) +#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) +#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) +#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) +#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) +#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) +#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) +#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) +#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) +#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) +#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) +#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) +#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) +#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) +#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) +#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) +#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) +#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) +#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) +#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) + +/* + * SoC APB Configuration Register (ro) + */ +#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) +#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) +#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) +#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) +#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) +#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) +#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) +#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) +#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) +#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) +#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) +#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) +#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) + +/* + * Driving Capability and Slew Rate Control Register 0 (rw) + */ +#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) +#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) +#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) +#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) +#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) + +/* + * Driving Capability and Slew Rate Control Register 1 (rw) + */ +#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) + +/* + * Driving Capability and Slew Rate Control Register 2 (rw) + */ +#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) +#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) +#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) +#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) +#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) +#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) +#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) +#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) + +/* + * Multi-function Port Setting Register 0 (rw) + */ +#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) +#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) +#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) +#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) +#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) +#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) +#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) + +/* + * Multi-function Port Setting Register 1 (rw) + */ +#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) +#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) +#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) +#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) +#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) +#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) +#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) +#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) +#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) +#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) +#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) +#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) +#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) +#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) +#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) +#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) + +/* + * DMA Engine Selection Register (rw) + */ +#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) +#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) +#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) +#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) +#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) +#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) +#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) +#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) + +/* + * OSC Control Register (rw) + */ +#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) +#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) +#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) +#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) +#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) +#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) + +/* + * PWM Clock Divider Register (rw) + */ +#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) + +/* + * SoC Misc. Register (rw) + */ +#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) +#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) +#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) +#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) +#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) +#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) +#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) +#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) +#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) +#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) +#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) +#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) +#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) +#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) +#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) +#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) +#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) +#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) +#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) +#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) +#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) +#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) +#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) +#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) +#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) +#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) +#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) +#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) +#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) +#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) + +/* + * BSM Control Register (rw) + */ +#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) +#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) +#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) +#define ANDES_PCU_BSMCR_IE(x) ((x) << 31) + +/* + * BSM Status Register + */ +#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) +#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) +#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) + +/* + * Wakeup Event Sensitivity Register (rw) + */ +#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) + +/* + * Wakeup Event Status Register (ro) + */ +#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) + +/* + * Reset Timing Register + */ +#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) +#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) +#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) +#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) + +/* + * PCU Interrupt Status Register + */ +#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) +#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) +#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) +#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) +#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) +#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) +#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) +#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) +#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) +#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) + +/* + * PCSx Configuration Register + */ +#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) +#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) +#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) +#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ + +/* + * PCSx Parameter Register (rw) + */ +#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) +#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) +#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) + +/* + * PCSx Status Register 1 + */ +#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) +#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) + +/* + * PCSx Status Register 2 + */ +#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) +#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) + +/* + * PCSx PDD Register + * This is reserved for PCS(1-7) + */ +#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) +#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) +#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) +#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) + +#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) +#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) +#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) +#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) +#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) +#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) +#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) +#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) +#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) + +#endif /* __ANDES_PCU_H */ diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h index 903c7a7759..1db7cec209 100644 --- a/include/config_phylib_all_drivers.h +++ b/include/config_phylib_all_drivers.h @@ -22,6 +22,7 @@ #define CONFIG_PHY_REALTEK #define CONFIG_PHY_NATSEMI #define CONFIG_PHY_LXT +#define CONFIG_PHY_ATHEROS #ifdef CONFIG_PHYLIB_10G #define CONFIG_PHY_TERANETICS diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d4e3ef5c2c..16db98fe57 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -131,7 +131,7 @@ #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a99f8d592a..1a6ba692ab 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -464,6 +464,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC +#define CONFIG_PHY_MARVELL + #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 19d32718fa..ab27b9895a 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -108,7 +108,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index ffee8fc8b0..d7910e1c73 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -115,7 +115,7 @@ #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 0077060984..1158fec436 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -173,7 +173,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* * Serial Port diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 883d44e371..00fa74d6f7 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -151,7 +151,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h new file mode 100644 index 0000000000..ffc70a630b --- /dev/null +++ b/include/configs/adp-ag101p.h @@ -0,0 +1,383 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/ag101.h> + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_ADP_AG101P + +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_MEM_REMAP +#endif + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x03200000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#endif + +/* + * Timer + */ + +/* + * According to the discussion in u-boot mailing list before, + * CONFIG_SYS_HZ at 1000 is mandatory. + */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK_FREQ 39062500 +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif + +#ifdef CONFIG_FTRTC010_EXTCLK +#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +/* + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/* + * Real Time Clock Divider + * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) + */ +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (4*OSC_5MHZ) +#define RTC_DIV_COUNT (0.5) /* Why?? */ + +/* + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Ethernet + */ +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/* + * SD (MMC) controller + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FTSDC010 +#define CONFIG_FTSDC010_NUMBER 1 +#define CONFIG_CMD_FAT + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Size of malloc() pool + */ +/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * size in bytes reserved for initial data + */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * AHB Controller configuration + */ +#define CONFIG_FTAHBC020S + +#ifdef CONFIG_FTAHBC020S +#include <faraday/ftahbc020s.h> + +/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 + +/* + * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, + * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote + * in C language. + */ +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ + (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ + FTAHBC020S_SLAVE_BSR_SIZE(0xb)) +#endif + +/* + * Watchdog + */ +#define CONFIG_FTWDT010_WATCHDOG + +/* + * PMU Power controller configuration + */ +#define CONFIG_PMU +#define CONFIG_FTPMU010_POWER + +#ifdef CONFIG_FTPMU010_POWER +#include <faraday/ftpmu010.h> +#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E +#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ + FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ + FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ + FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ + FTPMU010_SDRAMHTC_CKE_DCSR | \ + FTPMU010_SDRAMHTC_DQM_DCSR | \ + FTPMU010_SDRAMHTC_SDCLK_DCSR) +#endif + +/* + * SDRAM controller configuration + */ +#define CONFIG_FTSDMC021 + +#ifdef CONFIG_FTSDMC021 +#include <faraday/ftsdmc021.h> + +#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ + FTSDMC021_TP1_TRP(1) | \ + FTSDMC021_TP1_TRCD(1) | \ + FTSDMC021_TP1_TRF(3) | \ + FTSDMC021_TP1_TWR(1) | \ + FTSDMC021_TP1_TCL(2)) + +#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ + FTSDMC021_TP2_INI_REFT(8) | \ + FTSDMC021_TP2_REF_INTV(0x180)) + +/* + * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, + * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in + * C language. + */ +#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ + FTSDMC021_CR1_DSZ(3) | \ + FTSDMC021_CR1_MBW(2) | \ + FTSDMC021_CR1_BNKSIZE(6)) + +#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ + FTSDMC021_CR2_IREF | \ + FTSDMC021_CR2_ISMR) + +#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE +#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK0_BASE) + +#endif + +/* + * Physical Memory Map + */ +#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#if defined(CONFIG_MEM_REMAP) +#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ +#endif +#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ +#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ +#endif + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +#ifdef CONFIG_MEM_REMAP +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ + GENERATED_GBL_DATA_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) +#endif /* CONFIG_MEM_REMAP */ + +/* + * Load address and memory test area should agree with + * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x300000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) + +/* + * Static memory controller configuration + */ +#define CONFIG_FTSMC020 + +#ifdef CONFIG_FTSMC020 +#include <faraday/ftsmc020.h> + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ +#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(1) | \ + FTSMC020_TPR_CTW(1) | \ + FTSMC020_TPR_ATI(1) | \ + FTSMC020_TPR_AT2(1) | \ + FTSMC020_TPR_WTC(1) | \ + FTSMC020_TPR_AHT(1) | \ + FTSMC020_TPR_TRNA(1)) +#endif + +/* + * FLASH on ADP_AG101P is connected to BANK0 + * Just disalbe the other BANK to avoid detection error. + */ +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (0x00) +#define FTSMC020_BANK1_TIMING (0x00) +#endif /* CONFIG_FTSMC020 */ + +/* + * FLASH and environment organization + */ +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* support JEDEC */ + +/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define PHYS_FLASH_1 0x80400000 /* BANK 1 */ +#else /* !CONFIG_SKIP_LOWLEVEL_INIT */ +#ifdef CONFIG_MEM_REMAP +#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ +#else +#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ +#endif /* CONFIG_MEM_REMAP */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) +#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) +#define CONFIG_ENV_SIZE 8192 +#define CONFIG_ENV_OVERWRITE + +#endif /* __CONFIG_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index bcfb034840..5a69902f89 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -221,7 +221,7 @@ /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k SPL code*/ -#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/fdt_support.h b/include/fdt_support.h index c7b4605f06..cef3c6509d 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -28,8 +28,8 @@ #include <fdt.h> -u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop, - const u32 dflt); +u32 fdt_getprop_u32_default(const void *fdt, const char *path, + const char *prop, const u32 dflt); int fdt_chosen(void *fdt, int force); int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force); void do_fixup_by_path(void *fdt, const char *path, const char *prop, diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h new file mode 100644 index 0000000000..a33b122fcb --- /dev/null +++ b/include/synopsys/dwcddr21mctl.h @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller + */ +#ifndef __DWCDDR21MCTL_H +#define __DWCDDR21MCTL_H + +#ifndef __ASSEMBLY__ +struct dwcddr21mctl { + unsigned int ccr; /* Controller Configuration */ + unsigned int dcr; /* DRAM Configuration */ + unsigned int iocr; /* I/O Configuration */ + unsigned int csr; /* Controller Status */ + unsigned int drr; /* DRAM refresh */ + unsigned int tpr0; /* SDRAM Timing Parameters 0 */ + unsigned int tpr1; /* SDRAM Timing Parameters 1 */ + unsigned int tpr2; /* SDRAM Timing Parameters 2 */ + unsigned int gdllcr; /* Global DLL Control */ + unsigned int dllcr[10]; /* DLL Control */ + unsigned int rslr[4]; /* Rank System Lantency */ + unsigned int rdgr[4]; /* Rank DQS Gating */ + unsigned int dqtr[9]; /* DQ Timing */ + unsigned int dqstr; /* DQS Timing */ + unsigned int dqsbtr; /* DQS_b Timing */ + unsigned int odtcr; /* ODT Configuration */ + unsigned int dtr[2]; /* Data Training */ + unsigned int dtar; /* Data Training Address */ + unsigned int rsved[82]; /* Reserved */ + unsigned int mr; /* Mode Register */ + unsigned int emr; /* Extended Mode Register */ + unsigned int emr2; /* Extended Mode Register 2 */ + unsigned int emr3; /* Extended Mode Register 3 */ + unsigned int hpcr[32]; /* Host Port Configurarion */ + unsigned int pqcr[8]; /* Priority Queue Configuration */ + unsigned int mmgcr; /* Memory Manager General Config */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * Control Configuration Register + */ +#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) +#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) +#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) +#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) +#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) +#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) +#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) +#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) +#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) +#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) +#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28) +#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) +#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) +#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) + +/* + * DRAM Configuration Register + */ +#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) +#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1) +#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) +#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10) +#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12) +#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13) +#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25) +#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27) +#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31) + +/* + * I/O Configuration Register + */ +#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4) +#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8) +#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26) +#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29) +#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30) +#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31) + +/* + * Controller Status Register + */ +#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0) +#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18) +#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19) +#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20) +#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21) +#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22) + +/* + * DRAM Refresh Register + */ +#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0) +#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8) +#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24) +#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31) + +/* + * SDRAM Timing Parameters Register 0 + */ +#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2) +#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5) +#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8) +#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12) +#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16) +#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21) +#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25) +#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31) + +/* + * SDRAM Timing Parameters Register 1 + */ +#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2) +#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3) +#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12) +#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14) +#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23) +#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27) +#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31) + +/* + * SDRAM Timing Parameters Register 2 + */ +#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0) +#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10) +#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15) + +/* + * Global DLL Control Register + */ +#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2) +#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5) +#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9) +#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11) +#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12) +#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20) +#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29) + +/* + * DLL Control Register 0-9 + */ +#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12) +#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14) +#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18) +#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19) +#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31) + +/* + * Rank System Lantency Register + */ +#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12) +#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15) +#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18) +#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21) +#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24) + +/* + * Rank DQS Gating Register + */ +#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2) +#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4) +#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6) +#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8) +#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10) +#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12) +#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14) +#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16) + +/* + * DQ Timing Register + */ +#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4) +#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8) +#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12) +#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16) +#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20) +#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24) +#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28) + +/* + * DQS Timing Register + */ +#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12) +#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15) +#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18) +#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21) +#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24) + +/* + * DQS_b (DQSBTR) Timing Register + */ +#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12) +#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15) +#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18) +#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21) +#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24) + +/* + * ODT Configuration Register + */ +#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4) +#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8) +#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12) +#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16) +#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20) +#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24) +#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28) + +/* + * Data Training Register + */ +#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */ +#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */ +#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */ +#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */ + +#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */ +#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */ +#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */ +#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */ + +/* + * Data Training Address Register + */ +#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0) +#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12) +#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28) + +/* + * Mode Register + */ +#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_MR_BT(x) ((x) << 3) +#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4) +#define DWCDDR21MCTL_MR_TM(x) ((x) << 7) +#define DWCDDR21MCTL_MR_DR(x) ((x) << 8) +#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_MR_PD(x) ((x) << 12) + +/* + * Extended Mode register + */ +#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0) +#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1) +#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2) +#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6) +#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7) +#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10) +#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11) +#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12) + +#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x) +#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x) + +#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0)) +#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1)) +#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0)) +#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1)) + +/* + * Extended Mode register 2 + */ +#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3) +#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7) + +/* + * Extended Mode register 3: [15:0] reserved for JEDEC. + */ + +/* + * Host port Configuration register 0-31 + */ +#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0) + +/* + * Priority Queue Configuration register 0-7 + */ +#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8) +#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10) +#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12) +#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20) +#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25) +#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28) + +/* + * Memory Manager General Configuration register + */ +#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0) + +#endif /* __DWCDDR21MCTL_H */ |