diff options
| -rw-r--r-- | CHANGELOG | 26 | ||||
| -rw-r--r-- | board/xpedite1k/config.mk | 4 | ||||
| -rw-r--r-- | board/xpedite1k/xpedite1k.c | 27 | ||||
| -rw-r--r-- | cpu/mpc5xxx/pci_mpc5200.c | 2 | ||||
| -rw-r--r-- | cpu/mpc5xxx/start.S | 2 | ||||
| -rw-r--r-- | cpu/mpc8260/pci.c | 371 | ||||
| -rw-r--r-- | cpu/mpc8260/traps.c | 42 | ||||
| -rw-r--r-- | cpu/ppc4xx/405gp_pci.c | 33 | ||||
| -rw-r--r-- | cpu/ppc4xx/440gx_enet.c | 46 | ||||
| -rw-r--r-- | drivers/inca-ip_sw.c | 4 | ||||
| -rw-r--r-- | drivers/pci_auto.c | 68 | ||||
| -rw-r--r-- | drivers/pci_indirect.c | 13 | ||||
| -rw-r--r-- | include/asm-ppc/immap_8260.h | 144 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 938 | ||||
| -rw-r--r-- | include/asm-ppc/u-boot.h | 4 | ||||
| -rw-r--r-- | include/bmp_logo.h | 2 | ||||
| -rw-r--r-- | include/configs/XPEDITE1K.h | 4 |
17 files changed, 975 insertions, 755 deletions
diff --git a/CHANGELOG b/CHANGELOG index 4c285c365d3..63f5eb856c0 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,32 @@ Changes for U-Boot 1.0.2: ====================================================================== +* Patch by Travis Sawyer, 09 Feb 2004: + o 440GX: + - Fix PCI Indirect access for type 1 config cycles with ppc440. + - Add phymode for 440 enet + - fix pci pre init + o XPedite1K: + - Change board_pre_init to board_early_init_f + - Add user flash to bus controller setup + - Fix pci pre init + - Fix is_pci_host to check GPIO for monarch bit + - Force xpedite1k to pci conventional mode (via #define option) + +* Patch by Brad Kemp, 4 Feb 2004: + - handle the machine check that is generated during the PCI scans + on 82xx processors. + - define the registers used in the IMMR by the PCI subsystem. + +* Patch by Pierre Aubert, 03 Feb 2004: + cpu/mpc5xxx/start.S: copy MBAR into SPR311 + +* Patch by Jeff Angielski, 03 Feb 2004: + Fix copy & paste error in cpu/mpc8260/pci.c + +* Patch by Reinhard Meyer, 24 Jan 2004: + Fix typo in cpu/mpc5xxx/pci_mpc5200.c + * Add Auto-MDIX support for INCA-IP * Some code cleanup diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk index c0f0da84eed..e42b273a41b 100644 --- a/board/xpedite1k/config.mk +++ b/board/xpedite1k/config.mk @@ -22,11 +22,9 @@ # # -# esd ADCIOP boards +# XES XPedite1000 PPC440GX # -#TEXT_BASE = 0xFFFE0000 - ifeq ($(ramsym),1) TEXT_BASE = 0x07FD0000 else diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index c025c85db84..d6b30b94466 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -32,7 +32,7 @@ long int fixed_sdram (void); -int board_pre_init (void) +int board_early_init_f(void) { unsigned long sdrreg; /* TBS: Setup the GPIO access for the user LEDs */ @@ -51,6 +51,8 @@ int board_pre_init (void) /* set the bus controller */ mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ + mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */ + mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */ /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -217,17 +219,18 @@ long int fixed_sdram (void) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; - - /*--------------------------------------------------------------------------+ - * TBS: - * The xpedite1k is a PrPMC board, however for our purposes it is the host - *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if( (strap & 0x00100000) == 0 ){ - printf("PCI: CPC0_STRP1[PAE] not set.\n"); - return 0; + /* See if we're supposed to setup the pci */ + mfsdr(sdr_sdstp1, strap); + if ((strap & 0x00010000) == 0) { + return (0); } +#if defined(CFG_PCI_FORCE_PCI_CONV) + /* Setup System Device Register PCIX0_XCR */ + mfsdr(sdr_xcr, strap); + strap &= 0x0f000000; + mtsdr(sdr_xcr, strap); +#endif return 1; } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ @@ -292,9 +295,7 @@ void pci_target_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { - /* The ebony board is always configured as host. */ - /* TBS: The xpedite1k is not necessarily the host, however for our purposes, it is. */ - return(1); + return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0); } #endif /* defined(CONFIG_PCI) */ diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c index 0c2114a818c..94c157f6e88 100644 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -115,7 +115,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose) /* Map MBAR to PCI space */ *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1; + *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1; /* Map RAM to PCI space */ *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 26811e11ad7..6f0b269b46c 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -145,6 +145,8 @@ lowboot_reentry: lis r3, CFG_MBAR@h ori r3, r3, CFG_MBAR@l #if defined(CONFIG_MPC5200) + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 rlwinm r3, r3, 16, 16, 31 #endif #if defined(CONFIG_MGT5100) diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index b3a89f53fef..dc077ed1d5d 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -28,28 +28,28 @@ #include <pci.h> #include <mpc8260.h> #include <asm/m8260_pci.h> - +#include <asm/io.h> /* - * Local->PCI map (from CPU) controlled by + * Local->PCI map (from CPU) controlled by * MPC826x master window * - * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 - * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 + * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 + * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 * - * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) - * PCI Mem with prefetch + * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) + * PCI Mem with prefetch * - * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) - * PCI Mem w/o prefetch + * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) + * PCI Mem w/o prefetch * - * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) - * 32-bit PCI IO + * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) + * 32-bit PCI IO * * PCI->Local map (from PCI) - * MPC826x slave window controlled by + * MPC826x slave window controlled by * - * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) - * MPC826x local memory + * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) + * MPC826x local memory */ /* @@ -58,13 +58,13 @@ */ #ifndef CFG_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ #else #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL #endif #ifndef CFG_PCI_SLV_MEM_BUS -#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ #else #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS #endif @@ -85,28 +85,28 @@ /* PCIBR0 */ #ifndef CFG_PCI_MSTR0_LOCAL -#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ +#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ #else #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL #endif #ifndef CFG_PCIMSK0_MASK -#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ +#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ #else #define PCIMSK0_MASK CFG_PCIMSK0_MASK #endif /* PCIBR1 */ #ifndef CFG_PCI_MSTR1_LOCAL -#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ +#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ #else #define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL #endif #ifndef CFG_PCIMSK1_MASK -#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ +#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ #else -#define PCIMSK1_MASK CFG_PCIMSK1_MASK +#define PCIMSK1_MASK CFG_PCIMSK1_MASK #endif /* @@ -116,13 +116,13 @@ */ #ifndef CFG_PCI_MSTR_MEM_LOCAL -#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ #else #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL #endif #ifndef CFG_PCI_MSTR_MEM_BUS -#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ #else #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS #endif @@ -134,7 +134,7 @@ #endif #ifndef CFG_PCI_MSTR_MEM_SIZE -#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ +#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ #else #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE #endif @@ -152,13 +152,13 @@ */ #ifndef CFG_PCI_MSTR_MEMIO_LOCAL -#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ +#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ #else #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL #endif #ifndef CFG_PCI_MSTR_MEMIO_BUS -#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ +#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ #else #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS #endif @@ -170,13 +170,13 @@ #endif #ifndef CFG_PCI_MSTR_MEMIO_SIZE -#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ +#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ #else #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE #endif #ifndef CFG_POCMR1_MASK_ATTRIB -#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) +#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) #else #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB #endif @@ -188,13 +188,13 @@ */ #ifndef CFG_PCI_MSTR_IO_LOCAL -#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ +#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ #else #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL #endif #ifndef CFG_PCI_MSTR_IO_BUS -#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ +#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ #else #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS #endif @@ -206,13 +206,13 @@ #endif #ifndef CFG_PCI_MSTR_IO_SIZE -#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ +#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ #else #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE #endif #ifndef CFG_POCMR2_MASK_ATTRIB -#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) +#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) #else #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB #endif @@ -223,193 +223,198 @@ #define PCI_CLASS_BRIDGE_CTLR 0x06 -static inline void pci_outl(u32 addr, u32 data) +static inline void pci_outl (u32 addr, u32 data) { - *(volatile u32 *) addr = cpu_to_le32(data); + *(volatile u32 *) addr = cpu_to_le32 (data); } -void pci_mpc8250_init(struct pci_controller *hose) +void pci_mpc8250_init (struct pci_controller *hose) { #ifdef CONFIG_MPC8266ADS - DECLARE_GLOBAL_DATA_PTR; + DECLARE_GLOBAL_DATA_PTR; #endif - u16 tempShort; - u32 immr_addr = CFG_IMMR; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - pci_dev_t host_devno = PCI_BDF(0, 0, 0); + u16 tempShort; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + pci_dev_t host_devno = PCI_BDF (0, 0, 0); - pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG, - CFG_IMMR + PCI_CFG_DATA_REG); + pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, + CFG_IMMR + PCI_CFG_DATA_REG); - /* - * Setting required to enable local bus for PCI (SIUMCR [LBPC]). - */ + /* + * Setting required to enable local bus for PCI (SIUMCR [LBPC]). + */ #ifdef CONFIG_MPC8266ADS - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; + immap->im_siu_conf.sc_siumcr = + (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) + | SIUMCR_LBPC01; #else - /* - * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), - * and local bus for PCI (SIUMCR [LBPC]). - */ - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_LBPC11 & + /* + * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), + * and local bus for PCI (SIUMCR [LBPC]). + */ + immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & + ~SIUMCR_LBPC11 & ~SIUMCR_CS10PC11 & - ~SIUMCR_LBPC11) | - SIUMCR_LBPC01 | - SIUMCR_CS10PC01 | - SIUMCR_LBPC01; + ~SIUMCR_LBPC11) | + SIUMCR_LBPC01 | + SIUMCR_CS10PC01 | + SIUMCR_APPC10; #endif - /* Make PCI lowest priority */ - /* Each 4 bits is a device bus request and the MS 4bits - is highest priority */ - /* Bus 4bit value - --- ---------- - CPM high 0b0000 - CPM middle 0b0001 - CPM low 0b0010 - PCI reguest 0b0011 - Reserved 0b0100 - Reserved 0b0101 - Internal Core 0b0110 - External Master 1 0b0111 - External Master 2 0b1000 - External Master 3 0b1001 - The rest are reserved */ - immap->im_siu_conf.sc_ppc_alrh = 0x61207893; - - /* Park bus on core while modifying PCI Bus accesses */ - immap->im_siu_conf.sc_ppc_acr = 0x6; - - /* - * Set up master windows that allow the CPU to access PCI space. These - * windows are set up using the two SIU PCIBR registers. - */ - *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK; - *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) = - PCI_MSTR0_LOCAL | PCIBR_ENABLE; + /* Make PCI lowest priority */ + /* Each 4 bits is a device bus request and the MS 4bits + is highest priority */ + /* Bus 4bit value + --- ---------- + CPM high 0b0000 + CPM middle 0b0001 + CPM low 0b0010 + PCI reguest 0b0011 + Reserved 0b0100 + Reserved 0b0101 + Internal Core 0b0110 + External Master 1 0b0111 + External Master 2 0b1000 + External Master 3 0b1001 + The rest are reserved */ + immap->im_siu_conf.sc_ppc_alrh = 0x61207893; + + /* Park bus on core while modifying PCI Bus accesses */ + immap->im_siu_conf.sc_ppc_acr = 0x6; + + /* + * Set up master windows that allow the CPU to access PCI space. These + * windows are set up using the two SIU PCIBR registers. + */ + immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; + immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; #ifdef CONFIG_MPC8266ADS - *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK; - *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) = - PCI_MSTR1_LOCAL | PCIBR_ENABLE; + immap->im_memctl.memc_pcimsk0 = PCIMSK1_MASK; + immap->im_memctl.memc_pcibr0 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; #endif - /* Release PCI RST (by default the PCI RST signal is held low) */ - pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN); + /* Release PCI RST (by default the PCI RST signal is held low) */ + immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); - /* give it some time */ - { + /* give it some time */ + { #ifdef CONFIG_MPC8266ADS /* Give the PCI cards more time to initialize before query - This might be good for other boards also - */ - int i; - for (i = 0; i < 1000; ++i) + This might be good for other boards also + */ + int i; + + for (i = 0; i < 1000; ++i) #endif - udelay(1000); - } - - /* - * Set up master window that allows the CPU to access PCI Memory (prefetch) - * space. This window is set up using the first set of Outbound ATU registers. - */ - pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12); /* PCI base */ - pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ - pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI Memory (non-prefetch) - * space. This window is set up using the second set of Outbound ATU registers. - */ - pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ - pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ - pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI IO space. This window - * is set up using the third set of Outbound ATU registers. - */ - pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12); /* PCI base */ - pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12); /* Local base */ - pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12); /* Local base */ - pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12); /* PCI base */ - pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB); /* Size & attribute */ - - /* See above for description - puts PCI request as highest priority */ - immap->im_siu_conf.sc_ppc_alrh = 0x03124567; - - /* Park the bus on the PCI */ - immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; - - /* Host mode - specify the bridge as a host-PCI bridge */ - - pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE, - PCI_CLASS_BRIDGE_CTLR); - - /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ - pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort); - pci_hose_write_config_word(hose, host_devno, PCI_COMMAND, - tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + udelay (1000); + } + + /* + * Set up master window that allows the CPU to access PCI Memory (prefetch) + * space. This window is set up using the first set of Outbound ATU registers. + */ + immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ + immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ + immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ + + /* + * Set up master window that allows the CPU to access PCI Memory (non-prefetch) + * space. This window is set up using the second set of Outbound ATU registers. + */ + immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ + immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ + immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ + + /* + * Set up master window that allows the CPU to access PCI IO space. This window + * is set up using the third set of Outbound ATU registers. + */ + immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ + immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ + immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ + + /* + * Set up slave window that allows PCI masters to access MPC826x local memory. + * This window is set up using the first set of Inbound ATU registers + */ + immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ + immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ + immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ + + /* See above for description - puts PCI request as highest priority */ + immap->im_siu_conf.sc_ppc_alrh = 0x03124567; + + /* Park the bus on the PCI */ + immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; + + /* Host mode - specify the bridge as a host-PCI bridge */ + + pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, + PCI_CLASS_BRIDGE_CTLR); + + /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ + pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); + pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, + tempShort | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); -#ifdef CONFIG_MPC8266ADS /* do some bridge init, should be done on all 8260 based bridges */ - pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08); - pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8); -#endif + pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, + 0x08); + pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, + 0xF8); - hose->first_busno = 0; - hose->last_busno = 0xff; + hose->first_busno = 0; + hose->last_busno = 0xff; - /* System memory space */ + /* System memory space */ #ifdef CONFIG_MPC8266ADS - pci_set_region(hose->regions + 0, - PCI_SLV_MEM_BUS, - PCI_SLV_MEM_LOCAL, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); + pci_set_region (hose->regions + 0, + PCI_SLV_MEM_BUS, + PCI_SLV_MEM_LOCAL, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); #else - pci_set_region(hose->regions + 0, - CFG_SDRAM_BASE, - CFG_SDRAM_BASE, - 0x4000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); + pci_set_region (hose->regions + 0, + CFG_SDRAM_BASE, + CFG_SDRAM_BASE, + 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); #endif - /* PCI memory space */ + /* PCI memory space */ #ifdef CONFIG_MPC8266ADS - pci_set_region(hose->regions + 1, - PCI_MSTR_MEMIO_BUS, - PCI_MSTR_MEMIO_LOCAL, - PCI_MSTR_MEMIO_SIZE, - PCI_REGION_MEM); + pci_set_region (hose->regions + 1, + PCI_MSTR_MEMIO_BUS, + PCI_MSTR_MEMIO_LOCAL, + PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); #else - pci_set_region(hose->regions + 1, - PCI_MSTR_MEM_BUS, - PCI_MSTR_MEM_LOCAL, - PCI_MSTR_MEM_SIZE, - PCI_REGION_MEM); + pci_set_region (hose->regions + 1, + PCI_MSTR_MEM_BUS, + PCI_MSTR_MEM_LOCAL, + PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); #endif - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - PCI_MSTR_IO_BUS, - PCI_MSTR_IO_LOCAL, - PCI_MSTR_IO_SIZE, - PCI_REGION_IO); + /* PCI I/O space */ + pci_set_region (hose->regions + 2, + PCI_MSTR_IO_BUS, + PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); + + hose->region_count = 3; + + pci_register_hose (hose); + /* Mask off master abort machine checks */ + immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); + eieio (); + + hose->last_busno = pci_hose_scan (hose); - hose->region_count = 3; - pci_register_hose(hose); + /* clear the error in the error status register */ + immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); - hose->last_busno = pci_hose_scan(hose); + /* unmask master abort machine checks */ + immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); } -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index a7f6f7e1a78..deab8082971 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -35,6 +35,7 @@ #include <common.h> #include <command.h> #include <asm/processor.h> +#include <asm/m8260_pci.h> #if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; @@ -86,14 +87,12 @@ void show_regs(struct pt_regs * regs) printf("\n"); for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { + if ((i % 8) == 0) { printf("GPR%02d: ", i); } printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { + if ((i % 8) == 7) { printf("\n"); } } @@ -108,6 +107,24 @@ _exception(int signr, struct pt_regs *regs) panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } +#ifdef CONFIG_PCI +void dump_pci (void) +{ + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + printf ("PCI: err status %x err mask %x err ctrl %x\n", + le32_to_cpu (immap->im_pci.pci_esr), + le32_to_cpu (immap->im_pci.pci_emr), + le32_to_cpu (immap->im_pci.pci_ecr)); + printf (" error address %x error data %x ctrl %x\n", + le32_to_cpu (immap->im_pci.pci_eacr), + le32_to_cpu (immap->im_pci.pci_edcr), + le32_to_cpu (immap->im_pci.pci_eccr)); + +} +#endif + void MachineCheckException(struct pt_regs *regs) { @@ -117,6 +134,17 @@ MachineCheckException(struct pt_regs *regs) * when a device is not present. Catch it and return to * the PCI exception handler. */ +#ifdef CONFIG_PCI + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifdef DEBUG + dump_pci(); +#endif + /* clear the error in the error status register */ + if(immap->im_pci.pci_esr && cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { + immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); + return; + } +#endif if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; return; @@ -130,8 +158,7 @@ MachineCheckException(struct pt_regs *regs) printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); printf("regs %p ",regs); - switch( regs->msr & 0x0000F000) - { + switch( regs->msr & 0x0000F000) { case (1<<12) : printf("Machine check signal - probably due to mm fault\n" "with mmu off\n"); @@ -150,6 +177,9 @@ MachineCheckException(struct pt_regs *regs) } show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); +#ifdef CONFIG_PCI + dump_pci(); +#endif panic("machine check"); } diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index d3f6b237945..c9e2e9c628f 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -411,15 +411,23 @@ void pci_440_init (struct pci_controller *hose) /*--------------------------------------------------------------------------+ * The PCI initialization sequence enable bit must be set ... if not abort - * pci setup since updating the bit requires chip reset. + * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if( (strap & 0x00040000) == 0 ){ - printf("PCI: CPC0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } - +#if defined (CONFIG_440_GX) + mfsdr(sdr_sdstp1,strap); + if ( (strap & 0x00010000) == 0 ){ + printf("PCI: SDR0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#else + strap = mfdcr(cpc0_strp1); + if( (strap & 0x00040000) == 0 ){ + printf("PCI: CPC0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif /*--------------------------------------------------------------------------+ * PCI controller init *--------------------------------------------------------------------------*/ @@ -463,8 +471,13 @@ void pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#if defined(CONFIG_440_GX) + out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#else + out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#endif /*--------------------------------------------------------------------------+ * PCI master init: default is one 256MB region for PCI memory: diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c index 617a174381a..45020856dfc 100644 --- a/cpu/ppc4xx/440gx_enet.c +++ b/cpu/ppc4xx/440gx_enet.c @@ -116,6 +116,10 @@ #undef INFO_440_ENET +#define BI_PHYMODE_NONE 0 +#define BI_PHYMODE_ZMII 1 +#define BI_PHYMODE_RGMII 2 + /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ @@ -316,11 +320,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) break; } + bis->bi_phynum[devnum] = reg; + /* Reset the phy */ miiphy_reset (reg); /* Start/Restart autonegotiation */ -/* miiphy_write(reg, PHY_BMCR, 0x9340); */ phy_setup_aneg (reg); udelay (1000); @@ -579,13 +584,6 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), (interrupt_handler_t *) enetInt, dev); } -#if 0 /* done by irq_install_handler */ - /* set up interrupt handler */ - /* setup interrupt controller to take interrupts from the MAL & - EMAC */ - mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */ - mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF); -#endif mtmsr (msr); /* enable interrupts again */ @@ -1027,33 +1025,49 @@ int ppc_440x_eth_initialize (bd_t * bis) pfc1 &= ~(0x01e00000); pfc1 |= 0x01200000; mtsdr (sdr_pfc1, pfc1); + /* set phy num and mode */ + bis->bi_phynum[0] = CONFIG_PHY_ADDR; + bis->bi_phynum[1] = CONFIG_PHY1_ADDR; + bis->bi_phynum[2] = CONFIG_PHY2_ADDR; + bis->bi_phynum[3] = CONFIG_PHY3_ADDR; + bis->bi_phymode[0] = 0; + bis->bi_phymode[1] = 0; + bis->bi_phymode[2] = 2; + bis->bi_phymode[3] = 2; for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) { /* See if we can actually bring up the interface, otherwise, skip it */ switch (eth_num) { case 0: - if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) + if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; case 1: - if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == - 0) + if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; case 2: - if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == - 0) + if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; case 3: - if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == - 0) + if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; default: - if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) + if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; } diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c index 42edca880f7..c76b34495ca 100644 --- a/drivers/inca-ip_sw.c +++ b/drivers/inca-ip_sw.c @@ -69,7 +69,7 @@ /************************ Auto MDIX settings ************************/ #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR -#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL +#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 @@ -173,7 +173,7 @@ int inca_switch_initialize(bd_t * bis) inca_dma_init(); inca_init_switch_chip(); - + inca_amdix(); sprintf(dev->name, "INCA-IP Switch"); diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 3965f137170..3f26886e8b3 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -46,16 +46,14 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned { unsigned long addr; - if (!res) - { + if (!res) { DEBUGF("No resource"); goto error; } addr = ((res->bus_lower - 1) | (size - 1)) + 1; - if (addr - res->bus_start + size > res->size) - { + if (addr - res->bus_start + size > res->size) { DEBUGF("No room in resource"); goto error; } @@ -90,8 +88,7 @@ void pciauto_setup_device(struct pci_controller *hose, pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; - for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) - { + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { /* Tickle the BAR and get the response */ pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); pci_hose_read_config_dword(hose, dev, bar, &bar_response); @@ -103,15 +100,12 @@ void pciauto_setup_device(struct pci_controller *hose, found_mem64 = 0; /* Check the BAR type and set our address mask */ - if (bar_response & PCI_BASE_ADDRESS_SPACE) - { + if (bar_response & PCI_BASE_ADDRESS_SPACE) { bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; bar_res = io; DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); - } - else - { + } else { if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) found_mem64 = 1; @@ -122,8 +116,7 @@ void pciauto_setup_device(struct pci_controller *hose, DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size); } - if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) - { + if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { /* Write it out and update our limit */ pci_hose_write_config_dword(hose, dev, bar, bar_value); @@ -132,8 +125,7 @@ void pciauto_setup_device(struct pci_controller *hose, * upper 32 bits of the bar and force it to locate * in the lower 4GB of memory. */ - if (found_mem64) - { + if (found_mem64) { bar += 4; pci_hose_write_config_dword(hose, dev, bar, 0x00000000); } @@ -163,12 +155,10 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, /* Configure bus number registers */ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); - /* TBS: passed in sub_bus is correct, removed the +1 */ pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); - if (pci_mem) - { + if (pci_mem) { /* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_mem, 0x100000); @@ -179,8 +169,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, cmdstat |= PCI_COMMAND_MEMORY; } - if (pci_io) - { + if (pci_io) { /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); @@ -209,8 +198,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose, /* Configure bus number registers */ pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); - if (pci_mem) - { + if (pci_mem) { /* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_mem, 0x100000); @@ -218,8 +206,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose, (pci_mem->bus_lower-1) >> 16); } - if (pci_io) - { + if (pci_io) { /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); @@ -240,10 +227,8 @@ void pciauto_config_init(struct pci_controller *hose) hose->pci_io = hose->pci_mem = NULL; - for (i=0; i<hose->region_count; i++) - { - switch(hose->regions[i].flags) - { + for (i=0; i<hose->region_count; i++) { + switch(hose->regions[i].flags) { case PCI_REGION_IO: if (!hose->pci_io || hose->pci_io->size < hose->regions[i].size) @@ -258,8 +243,7 @@ void pciauto_config_init(struct pci_controller *hose) } - if (hose->pci_mem) - { + if (hose->pci_mem) { pciauto_region_init(hose->pci_mem); DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n", @@ -267,8 +251,7 @@ void pciauto_config_init(struct pci_controller *hose) hose->pci_mem->bus_start + hose->pci_mem->size - 1); } - if (hose->pci_io) - { + if (hose->pci_io) { pciauto_region_init(hose->pci_io); DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n", @@ -289,23 +272,22 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); - switch(class) - { + switch(class) { case PCI_CLASS_BRIDGE_PCI: hose->current_busno++; pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io); DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); - /* TBS: Passing in current_busno allows for sibling P2P bridges */ + /* Passing in current_busno allows for sibling P2P bridges */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); /* - * TBS: need to figure out if this is a subordinate bridge on the bus + * need to figure out if this is a subordinate bridge on the bus * to be able to properly set the pri/sec/sub bridge registers. */ n = pci_hose_scan_bus(hose, hose->current_busno); - /* TBS: figure out the deepest we've gone for this leg */ + /* figure out the deepest we've gone for this leg */ sub_bus = max(n, sub_bus); pciauto_postscan_setup_bridge(hose, dev, sub_bus); @@ -314,11 +296,10 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) case PCI_CLASS_STORAGE_IDE: pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); - if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) - { - DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); - return sub_bus; - } + if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { + DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); + return sub_bus; + } pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); break; @@ -327,8 +308,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) /* just do a minimal setup of the bridge, let the OS take care of the rest */ pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io); - DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", - PCI_DEV(dev)); + DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); hose->current_busno++; break; diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c index 7dc17a7a3a0..0368681351a 100644 --- a/drivers/pci_indirect.c +++ b/drivers/pci_indirect.c @@ -43,6 +43,19 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ } +#elif defined(CONFIG_440_GX) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + if (PCI_BUS(dev) > 0) \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \ + else \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} #else #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ diff --git a/include/asm-ppc/immap_8260.h b/include/asm-ppc/immap_8260.h index c61cc4f536a..407cf49956c 100644 --- a/include/asm-ppc/immap_8260.h +++ b/include/asm-ppc/immap_8260.h @@ -1,18 +1,17 @@ - /* * MPC8260 Internal Memory Map * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) * - * The Internal Memory Map of the 8260. I don't know how generic + * The Internal Memory Map of the 8260. I don't know how generic * this will be, as I don't have any knowledge of the subsequent - * parts at this time. I copied this from the 8xx_immap.h. + * parts at this time. I copied this from the 8xx_immap.h. */ #ifndef __IMMAP_82XX__ #define __IMMAP_82XX__ /* System configuration registers. */ -typedef struct sys_conf { +typedef struct sys_conf { uint sc_siumcr; uint sc_sypcr; char res1[6]; @@ -89,7 +88,12 @@ typedef struct mem_ctlr { u_char memc_lsrt; char res9[3]; uint memc_immr; - char res10[84]; + uint memc_pcibr0; + uint memc_pcibr1; + char res10[16]; + uint memc_pcimsk0; + uint memc_pcimsk1; + char res11[52]; } memctl8260_t; /* System Integration Timers. @@ -107,9 +111,136 @@ typedef struct sys_int_timers { uint sit_pitc; uint sit_pitr; char res6[94]; - char res7[2390]; + char res7[390]; } sit8260_t; +/* PCI + */ +typedef struct pci_config { + uint pci_omisr; + uint pci_ominr; + char res1[8]; + uint pci_ifqpr; + uint pci_ofqpr; + char res2[8]; + uint pci_imr0; + uint pci_imr1; + uint pci_omr0; + uint pci_omr1; + uint pci_odr; + char res3[4]; + uint pci_idr; + char res4[20]; + uint pci_imisr; + uint pci_imimr; + char res5[24]; + uint pci_ifhpr; + uint pci_iftpr; + char res6[8]; + uint pci_iphpr; + uint pci_iptpr; + char res7[8]; + uint pci_ofhpr; + uint pci_oftpr; + char res8[8]; + uint pci_ophpr; + uint pci_optpr; + char res9[12]; + uint pci_mucr; + char res10[8]; + uint pci_qbar; + char res11[12]; + uint pci_dmamr0; + uint pci_dmasr0; + uint pci_dmacdar0; + char res12[4]; + uint pci_dmasar0; + char res13[4]; + uint pci_dmadar0; + char res14[4]; + uint pci_dmabcr0; + uint pci_dmandar0; + char res15[88]; + uint pci_dmamr1; + uint pci_dmasr1; + uint pci_dmacdar1; + char res16[4]; + uint pci_dmasar1; + char res17[4]; + uint pci_dmadar1; + char res18[4]; + uint pci_dmabcr1; + uint pci_dmandar1; + char res19[88]; + uint pci_dmamr2; + uint pci_dmasr2; + uint pci_dmacdar2; + char res20[4]; + uint pci_dmasar2; + char res21[4]; + uint pci_dmadar2; + char res22[4]; + uint pci_dmabcr2; + uint pci_dmandar2; + char res23[88]; + uint pci_dmamr3; + uint pci_dmasr3; + uint pci_dmacdar3; + char res24[4]; + uint pci_dmasar3; + char res25[4]; + uint pci_dmadar3; + char res26[4]; + uint pci_dmabcr3; + uint pci_dmandar3; + char res27[344]; + uint pci_potar0; + char res28[4]; + uint pci_pobar0; + char res29[4]; + uint pci_pocmr0; + char res30[4]; + uint pci_potar1; + char res31[4]; + uint pci_pobar1; + char res32[4]; + uint pci_pocmr1; + char res33[4]; + uint pci_potar2; + char res34[4]; + uint pci_pobar2; + char res35[4]; + uint pci_pocmr2; + char res36[52]; + uint pci_ptcr; + uint pci_gpcr; + uint pci_gcr; + uint pci_esr; + uint pci_emr; + uint pci_ecr; + uint pci_eacr; + char res37[4]; + uint pci_edcr; + char res38[4]; + uint pci_eccr; + char res39[44]; + uint pci_pitar1; + char res40[4]; + uint pci_pibar1; + char res41[4]; + uint pci_picmr1; + char res42[4]; + uint pci_pitar0; + char res43[4]; + uint pci_pibar0; + char res44[4]; + uint pci_picmr0; + char res45[4]; + uint pci_cfg_addr; + uint pci_cfg_data; + uint pci_int_ack; + char res46[756]; +}pci8260_t; #define PISCR_PIRQ_MASK ((ushort)0xff00) #define PISCR_PS ((ushort)0x0080) #define PISCR_PIE ((ushort)0x0004) @@ -375,6 +506,7 @@ typedef struct immap { sysconf8260_t im_siu_conf; /* SIU Configuration */ memctl8260_t im_memctl; /* Memory Controller */ sit8260_t im_sit; /* System Integration Timers */ + pci8260_t im_pci; /* PCI Configuration */ intctl8260_t im_intctl; /* Interrupt Controller */ car8260_t im_clkrst; /* Clocks and reset */ iop8260_t im_ioport; /* IO Port control/status */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index ac4ab479734..f036b682859 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -92,293 +92,294 @@ /* Special Purpose Registers (SPRNs)*/ -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ #ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #else #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ #endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #ifndef CONFIG_BOOKE #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #else #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ #endif /* CONFIG_BOOKE */ #ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ #endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ #ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ #else #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ #endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ -#define SPRN_EAR 0x11A /* External Address Register */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ #else #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ #endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<15) /* Instruction Cache Enable */ -#define HID0_DCE (1<<14) /* Data Cache Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<12) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ -#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ -#define HID0_DCI HID0_DCFI +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<15) /* Instruction Cache Enable */ +#define HID0_DCE (1<<14) /* Data Cache Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<12) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ +#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ +#define HID0_DCI HID0_DCFI #define HID0_SPD (1<<9) /* Speculative disable */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ -#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ +#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ #define HID0_ABE (1<<3) /* Address Broadcast Enable */ -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ -#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ -#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE -#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ -#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ #else #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ #endif /* CONFIG_BOOKE */ -#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ -#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ -#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ -#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ -#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ -#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ -#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ -#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ -#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ -#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ -#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ -#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ -#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ -#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ -#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ -#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ -#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ -#define ICCR_NOCACHE 0 /* Noncacheable */ -#define ICCR_CACHE 1 /* Cacheable */ -#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ -#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ -#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ -#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ -#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ -#define SPRN_LR 0x008 /* Link Register */ -#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ -#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ -#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ -#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ -#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ -#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ +#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ +#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ +#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ +#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ +#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ +#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ +#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ +#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ +#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ +#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ +#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ +#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ +#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ +#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ +#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ +#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ +#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define ICCR_NOCACHE 0 /* Noncacheable */ +#define ICCR_CACHE 1 /* Cacheable */ +#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ +#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ +#define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MBAR 0x137 /* System memory base address */ +#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ +#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ +#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ +#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ +#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ #ifndef CONFIG_BOOKE -#define SPRN_PID 0x3B1 /* Process ID */ -#define SPRN_PIR 0x3FF /* Processor Identification Register */ +#define SPRN_PID 0x3B1 /* Process ID */ +#define SPRN_PIR 0x3FF /* Processor Identification Register */ #else #define SPRN_PID 0x030 /* Book E Process ID */ #define SPRN_PIR 0x11E /* Book E Processor Identification Register */ #endif /* CONFIG_BOOKE */ -#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ -#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ -#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ -#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ -#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ -#define SPRN_PVR 0x11F /* Processor Version Register */ -#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ -#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ -#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ -#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ -#define SGR_NORMAL 0 -#define SGR_GUARDED 1 -#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ -#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ -#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ -#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ -#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ -#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ -#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ -#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ -#define SPRN_TBHI 0x3DC /* Time Base High */ -#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ -#define SPRN_TBLO 0x3DD /* Time Base Low */ -#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ -#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */ -#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */ -#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */ -#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */ +#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ +#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ +#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ +#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PVR 0x11F /* Processor Version Register */ +#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ +#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ +#define SGR_NORMAL 0 +#define SGR_GUARDED 1 +#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ +#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ +#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ +#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ +#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ +#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_TBHI 0x3DC /* Time Base High */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ +#define SPRN_TBLO 0x3DD /* Time Base Low */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ +#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */ +#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */ +#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */ +#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */ #ifndef CONFIG_BOOKE -#define SPRN_TCR 0x3DA /* Timer Control Register */ +#define SPRN_TCR 0x3DA /* Timer Control Register */ #else #define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ -#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ -#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ -#define THRM1_TIN (1<<0) -#define THRM1_TIV (1<<1) -#define THRM1_THRES (0x7f<<2) -#define THRM1_TID (1<<29) -#define THRM1_TIE (1<<30) -#define THRM1_V (1<<31) -#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ -#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ -#define THRM3_E (1<<31) +#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +#define THRM1_TIN (1<<0) +#define THRM1_TIV (1<<1) +#define THRM1_THRES (0x7f<<2) +#define THRM1_TID (1<<29) +#define THRM1_TIE (1<<30) +#define THRM1_V (1<<31) +#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ +#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ +#define THRM3_E (1<<31) #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ #ifndef CONFIG_BOOKE -#define SPRN_TSR 0x3D8 /* Timer Status Register */ +#define SPRN_TSR 0x3D8 /* Timer Status Register */ #else #define SPRN_TSR 0x150 /* Book E Timer Status Register */ #endif /* CONFIG_BOOKE */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ -#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ -#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ -#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ -#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ -#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ -#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ -#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ -#define SPRN_XER 0x001 /* Fixed Point Exception Register */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ /* Book E definitions */ #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ #define SPRN_CSRR0 0x03A /* Critical SRR0 */ #define SPRN_CSRR1 0x03B /* Critical SRR0 */ -#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ -#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ -#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ -#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ -#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ -#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ -#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ -#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ -#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ -#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ -#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ @@ -406,7 +407,7 @@ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ -#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ @@ -433,127 +434,128 @@ /* Short-hand versions for a number of the above SPRNs */ -#define CTR SPRN_CTR /* Counter Register */ -#define DAR SPRN_DAR /* Data Address Register */ -#define DABR SPRN_DABR /* Data Address Breakpoint Register */ -#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ -#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ -#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ -#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ -#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ -#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ -#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ -#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ -#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ -#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ -#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ -#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ -#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ -#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ -#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ -#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ -#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ -#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ -#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ -#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ -#define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ -#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ -#define ESR SPRN_ESR /* Exception Syndrome Register */ -#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ -#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ -#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ -#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ -#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ -#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ -#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ -#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ -#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ -#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ -#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ -#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ -#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ -#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ -#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ -#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ -#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ -#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ -#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ -#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ -#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ -#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ -#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ -#define LR SPRN_LR +#define CTR SPRN_CTR /* Counter Register */ +#define DAR SPRN_DAR /* Data Address Register */ +#define DABR SPRN_DABR /* Data Address Breakpoint Register */ +#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ +#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ +#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ +#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ +#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ +#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ +#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ +#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ +#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ +#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ +#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ +#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ +#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ +#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ +#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ +#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ +#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ +#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ +#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ +#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ +#define DBSR SPRN_DBSR /* Debug Status Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ +#define EAR SPRN_EAR /* External Address Register */ +#define ESR SPRN_ESR /* Exception Syndrome Register */ +#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ +#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ +#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ +#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ +#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ +#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ +#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ +#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ +#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ +#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ +#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ +#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ +#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ +#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ +#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ +#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ +#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ +#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ +#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ +#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ +#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define LR SPRN_LR +#define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_E500) #define PIR SPRN_PIR #endif -#define PVR SPRN_PVR /* Processor Version */ -#define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ -#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ -#define SPR1 SPRN_SPRG1 -#define SPR2 SPRN_SPRG2 -#define SPR3 SPRN_SPRG3 -#define SPRG0 SPRN_SPRG0 -#define SPRG1 SPRN_SPRG1 -#define SPRG2 SPRN_SPRG2 -#define SPRG3 SPRN_SPRG3 -#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ -#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ -#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ -#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ -#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ -#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ -#define TCR SPRN_TCR /* Timer Control Register */ -#define TSR SPRN_TSR /* Timer Status Register */ +#define PVR SPRN_PVR /* Processor Version */ +#define RPA SPRN_RPA /* Required Physical Address Register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ +#define SPR1 SPRN_SPRG1 +#define SPR2 SPRN_SPRG2 +#define SPR3 SPRN_SPRG3 +#define SPRG0 SPRN_SPRG0 +#define SPRG1 SPRN_SPRG1 +#define SPRG2 SPRN_SPRG2 +#define SPRG3 SPRN_SPRG3 +#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ +#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ +#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ +#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ +#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ +#define TCR SPRN_TCR /* Timer Control Register */ +#define TSR SPRN_TSR /* Timer Status Register */ #define ICTC 1019 -#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ -#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ -#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ -#define XER SPRN_XER - -#define DECAR SPRN_DECAR -#define CSRR0 SPRN_CSRR0 -#define CSRR1 SPRN_CSRR1 -#define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 -#define SPRG4R SPRN_SPRG4R -#define SPRG5R SPRN_SPRG5R -#define SPRG6R SPRN_SPRG6R -#define SPRG7R SPRN_SPRG7R -#define SPRG4W SPRN_SPRG4W -#define SPRG5W SPRN_SPRG5W -#define SPRG6W SPRN_SPRG6W -#define SPRG7W SPRN_SPRG7W +#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ +#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ +#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ +#define XER SPRN_XER + +#define DECAR SPRN_DECAR +#define CSRR0 SPRN_CSRR0 +#define CSRR1 SPRN_CSRR1 +#define IVPR SPRN_IVPR +#define USPRG0 SPRN_USPRG0 +#define SPRG4R SPRN_SPRG4R +#define SPRG5R SPRN_SPRG5R +#define SPRG6R SPRN_SPRG6R +#define SPRG7R SPRN_SPRG7R +#define SPRG4W SPRN_SPRG4W +#define SPRG5W SPRN_SPRG5W +#define SPRG6W SPRN_SPRG6W +#define SPRG7W SPRN_SPRG7W #define DEAR SPRN_DEAR -#define DBCR2 SPRN_DBCR2 -#define IAC3 SPRN_IAC3 -#define IAC4 SPRN_IAC4 -#define DVC1 SPRN_DVC1 -#define DVC2 SPRN_DVC2 -#define IVOR0 SPRN_IVOR0 -#define IVOR1 SPRN_IVOR1 -#define IVOR2 SPRN_IVOR2 -#define IVOR3 SPRN_IVOR3 -#define IVOR4 SPRN_IVOR4 -#define IVOR5 SPRN_IVOR5 -#define IVOR6 SPRN_IVOR6 -#define IVOR7 SPRN_IVOR7 -#define IVOR8 SPRN_IVOR8 -#define IVOR9 SPRN_IVOR9 -#define IVOR10 SPRN_IVOR10 -#define IVOR11 SPRN_IVOR11 -#define IVOR12 SPRN_IVOR12 -#define IVOR13 SPRN_IVOR13 -#define IVOR14 SPRN_IVOR14 -#define IVOR15 SPRN_IVOR15 +#define DBCR2 SPRN_DBCR2 +#define IAC3 SPRN_IAC3 +#define IAC4 SPRN_IAC4 +#define DVC1 SPRN_DVC1 +#define DVC2 SPRN_DVC2 +#define IVOR0 SPRN_IVOR0 +#define IVOR1 SPRN_IVOR1 +#define IVOR2 SPRN_IVOR2 +#define IVOR3 SPRN_IVOR3 +#define IVOR4 SPRN_IVOR4 +#define IVOR5 SPRN_IVOR5 +#define IVOR6 SPRN_IVOR6 +#define IVOR7 SPRN_IVOR7 +#define IVOR8 SPRN_IVOR8 +#define IVOR9 SPRN_IVOR9 +#define IVOR10 SPRN_IVOR10 +#define IVOR11 SPRN_IVOR11 +#define IVOR12 SPRN_IVOR12 +#define IVOR13 SPRN_IVOR13 +#define IVOR14 SPRN_IVOR14 +#define IVOR15 SPRN_IVOR15 #define IVOR32 SPRN_IVOR32 #define IVOR33 SPRN_IVOR33 #define IVOR34 SPRN_IVOR34 @@ -578,135 +580,135 @@ /* Device Control Registers */ -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ -#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ -#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ -#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ -#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ -#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ -#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ -#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ -#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ -#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ -#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ -#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ -#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ -#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ -#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ -#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ -#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ -#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ -#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ -#define DCRN_DMASR 0x0E0 /* DMA Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 +#define DCRN_BEAR 0x090 /* Bus Error Address Register */ +#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 +#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ +#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ +#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ +#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ +#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ +#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ +#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ +#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ +#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ +#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ +#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ +#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ +#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ +#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ +#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ +#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ +#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ +#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ +#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ +#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ +#define DCRN_DMASR 0x0E0 /* DMA Status Register */ +#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ +#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ +#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 /* Processor Version Register */ /* Processor Version Register (PVR) field extraction */ -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ /* * IBM has further subdivided the standard PowerPC 16-bit version and * revision subfields of the PVR for the PowerPC 403s into the following: */ -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ /* Processor Version Numbers */ -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_405EP_RB 0x51210950 -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_405EP_RB 0x51210950 +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P #define PVR_7400 0x000C0000 #define PVR_7410 0x800C0000 #define PVR_7450 0x80000000 @@ -719,12 +721,12 @@ * differentiated by the version number in the Communication Processor * Module (CPM). */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 /* * PowerQUICC II family processors report different PVR values depending diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index a53efe50f71..c73b53f1f77 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -104,6 +104,10 @@ typedef struct bd_info { #if defined(CONFIG_NX823) unsigned char bi_sernum[8]; #endif +#if defined(CONFIG_440_GX) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ +#endif } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/include/bmp_logo.h b/include/bmp_logo.h index 265f744d0e3..9c924b8592d 100644 --- a/include/bmp_logo.h +++ b/include/bmp_logo.h @@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = { 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, - 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, + 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, }; unsigned char bmp_logo_bitmap[] = { diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 845449cc637..8bdd293261e 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -37,7 +37,7 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #define CONFIG_440_GX 1 /* 440 GX */ -#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ @@ -235,7 +235,7 @@ extern void out32(unsigned int, unsigned long); #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - +#define CFG_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is |