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-rw-r--r--arch/x86/cpu/coreboot/Kconfig20
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c9
-rw-r--r--arch/x86/dts/Makefile1
-rw-r--r--arch/x86/dts/coreboot.dts41
-rw-r--r--board/coreboot/coreboot/Kconfig28
-rw-r--r--board/coreboot/coreboot/Makefile2
-rw-r--r--board/coreboot/coreboot/coreboot.c17
-rw-r--r--board/coreboot/coreboot/start.S (renamed from board/coreboot/coreboot/coreboot_start.S)0
-rw-r--r--configs/coreboot_defconfig18
-rw-r--r--doc/README.x8615
-rw-r--r--include/configs/coreboot.h32
11 files changed, 116 insertions, 67 deletions
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 392c2589450..93f61f2fa4f 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -3,26 +3,26 @@ if TARGET_COREBOOT
config SYS_COREBOOT
bool
default y
+ imply SYS_NS16550
+ imply SCSI
+ imply SCSI_AHCI
imply AHCI_PCI
- imply E1000
- imply ICH_SPI
imply MMC
imply MMC_PCI
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
- imply SCSI
- imply SCSI_AHCI
- imply SPI_FLASH
- imply SYS_NS16550
imply USB
imply USB_EHCI_HCD
imply USB_XHCI_HCD
+ imply USB_STORAGE
+ imply USB_KEYBOARD
imply VIDEO_COREBOOT
+ imply E1000
+ imply ETH_DESIGNWARE
+ imply PCH_GBE
+ imply RTL8169
imply CMD_CBFS
imply FS_CBFS
-
-config CBMEM_CONSOLE
- bool
- default y
+ imply CBMEM_CONSOLE
endif
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 69025c1537b..a6fd3a849a2 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fdtdec.h>
+#include <usb.h>
#include <asm/io.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
@@ -75,12 +76,10 @@ int last_stage_init(void)
if (gd->flags & GD_FLG_COLD_BOOT)
timestamp_add_to_bootstage();
- board_final_cleanup();
+ /* start usb so that usb keyboard can be used as input device */
+ usb_init();
- return 0;
-}
+ board_final_cleanup();
-int misc_init_r(void)
-{
return 0;
}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 37e4fdc7601..c62540fe74c 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
conga-qeval20-qa3-e3845.dtb \
+ coreboot.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
dfi-bt700-q7x-151.dtb \
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
new file mode 100644
index 00000000000..a94f7818331
--- /dev/null
+++ b/arch/x86/dts/coreboot.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Generic coreboot payload device tree for x86 targets
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "coreboot x86 payload";
+ compatible = "coreboot,x86-payload";
+
+ aliases {
+ serial0 = &serial;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ pci {
+ compatible = "pci-x86";
+ u-boot,dm-pre-reloc;
+ };
+
+ coreboot-fb {
+ compatible = "coreboot-fb";
+ };
+};
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index cfa1d50ee45..5bd6465d989 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -9,35 +9,15 @@ config SYS_VENDOR
config SYS_SOC
default "coreboot"
+config SYS_CONFIG_NAME
+ default "coreboot"
+
config SYS_TEXT_BASE
default 0x01110000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- imply SPI_FLASH_ATMEL
- imply SPI_FLASH_EON
- imply SPI_FLASH_GIGADEVICE
- imply SPI_FLASH_MACRONIX
- imply SPI_FLASH_SPANSION
- imply SPI_FLASH_STMICRO
- imply SPI_FLASH_SST
- imply SPI_FLASH_WINBOND
-
-comment "coreboot-specific options"
-
-config SYS_CONFIG_NAME
- string "Board configuration file"
- default "qemu-x86"
- help
- This option selects the board configuration file in include/configs/
- directory to be used to build U-Boot for coreboot.
-
-config DEFAULT_DEVICE_TREE
- string "Board Device Tree Source (dts) file"
- default "qemu-x86_i440fx"
- help
- This option selects the board Device Tree Source (dts) file in
- arch/x86/dts/ directory to be used to build U-Boot for coreboot.
+ select BOARD_EARLY_INIT_R
config SYS_CAR_ADDR
hex "Board specific Cache-As-RAM (CAR) address"
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
index ea0f3ee1ae0..8db7cc62f30 100644
--- a/board/coreboot/coreboot/Makefile
+++ b/board/coreboot/coreboot/Makefile
@@ -10,4 +10,4 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-obj-y += coreboot_start.o
+obj-y += start.o coreboot.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
new file mode 100644
index 00000000000..ed5606d4a44
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+
+int board_early_init_r(void)
+{
+ /*
+ * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+ * can be discovered by their drivers
+ */
+ pci_init();
+
+ return 0;
+}
diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/start.S
index aa702622d48..aa702622d48 100644
--- a/board/coreboot/coreboot/coreboot_start.S
+++ b/board/coreboot/coreboot/start.S
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 114ac6115ea..ad0b35f2046 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -4,28 +4,25 @@ CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_FIT_SIGNATURE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
+CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
-CONFIG_CMD_TPM=y
-CONFIG_CMD_TPM_TEST=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -34,11 +31,8 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="coreboot"
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPI=y
-CONFIG_TPM_TIS_LPC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
+# CONFIG_PCI_PNP is not set
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_TPM=y
diff --git a/doc/README.x86 b/doc/README.x86
index 9162ea17d82..6015ca40115 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -47,21 +47,6 @@ on other architectures, like below:
$ make coreboot_defconfig
$ make all
-Note this default configuration will build a U-Boot payload for the QEMU board.
-To build a coreboot payload against another board, you can change the build
-configuration during the 'make menuconfig' process.
-
-x86 architecture --->
- ...
- (qemu-x86) Board configuration file
- (qemu-x86_i440fx) Board Device Tree Source (dts) file
- (0x01920000) Board specific Cache-As-RAM (CAR) address
- (0x4000) Board specific Cache-As-RAM (CAR) size
-
-Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
-to point to a new board. You can also change the Cache-As-RAM (CAR) related
-settings here if the default values do not fit your new board.
-
Build Instructions for U-Boot as main bootloader
------------------------------------------------
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
new file mode 100644
index 00000000000..1cf5c037e85
--- /dev/null
+++ b/include/configs/coreboot.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+/* ATA/IDE support */
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 4
+#define CONFIG_SYS_ATA_BASE_ADDR 0
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_ALT_OFFSET 0
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
+#define CONFIG_ATAPI
+
+#endif /* __CONFIG_H */