diff options
125 files changed, 4866 insertions, 846 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f8041..0c6ce2bfd4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -152,10 +152,6 @@ Dave Ellis <DGE@sixnetio.com> SXNI855T MPC8xx -Fred Fan <fanyefeng@gmail.com> - - mx51evk i.MX51 - Thomas Frieden <ThomasF@hyperion-entertainment.com> AmigaOneG3SE MPC7xx @@ -549,6 +545,7 @@ Stefano Babic <sbabic@denx.de> polaris xscale trizepsiv xscale + mx51evk i.MX51 Dirk Behme <dirk.behme@gmail.com> @@ -806,6 +803,10 @@ Prafulla Wadaskar <prafulla@marvell.com> rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Matthias Weisser <weisserm@arcor.de> + + jadecpu ARM926EJS (MB86R01 SoC) + Richard Woodruff <r-woodruff2@ti.com> omap2420h4 ARM1136EJS @@ -579,6 +579,7 @@ LIST_ARM9=" \ edminiv2 \ guruplug \ imx27lite \ + jadecpu \ lpd7a400 \ magnesium \ mv88f6281gtw_ge \ @@ -253,6 +253,13 @@ ifeq ($(SOC),omap4) LIBS += $(CPUDIR)/omap-common/libomap-common.a endif +ifeq ($(SOC),s5pc1xx) +LIBS += $(CPUDIR)/s5p-common/libs5p-common.a +endif +ifeq ($(SOC),s5pc2xx) +LIBS += $(CPUDIR)/s5p-common/libs5p-common.a +endif + LIBS := $(addprefix $(obj),$(LIBS)) .PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE) @@ -1883,7 +1890,7 @@ CPUAT91_RAM_config \ CPUAT91_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a cpuat91 arm arm920t cpuat91 eukrea at91rm9200 + @$(MKCONFIG) -n $@ -a cpuat91 arm arm920t cpuat91 eukrea at91 ######################################################################### ## ARM926EJ-S Systems diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index 4f467be91c2..def3980b634 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91_EFLASH) += eflash.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 77d49ab1c76..87b04426b9b 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -28,12 +28,27 @@ #include <asm/arch/gpio.h> #include <asm/arch/io.h> +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + void at91_serial0_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */ writel(1 << AT91SAM9260_ID_US0, &pmc->pcer); } @@ -42,7 +57,7 @@ void at91_serial1_hw_init(void) at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */ writel(1 << AT91SAM9260_ID_US1, &pmc->pcer); } @@ -51,7 +66,7 @@ void at91_serial2_hw_init(void) at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */ writel(1 << AT91SAM9260_ID_US2, &pmc->pcer); } @@ -59,7 +74,7 @@ void at91_serial3_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ writel(1 << AT91_ID_SYS, &pmc->pcer); } @@ -88,9 +103,9 @@ void at91_spi0_hw_init(unsigned long cs_mask) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer); @@ -125,9 +140,9 @@ void at91_spi1_hw_init(unsigned long cs_mask) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */ /* Enable clock */ writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer); @@ -194,3 +209,24 @@ void at91_macb_hw_init(void) #endif } #endif + +#if defined(CONFIG_ATMEL_MCI) || defined(CONFIG_GENERIC_ATMEL_MCI) +void at91_mci_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */ +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */ + at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */ + at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */ + at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */ + at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */ +#endif +} +#endif + diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c new file mode 100644 index 00000000000..2e851dbd2c8 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -0,0 +1,271 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * this driver supports the enhanced embedded flash in the Atmel + * AT91SAM9XE devices with the following geometry: + * + * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages) + * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages) + * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages) + * (the exact geometry is read from the flash at runtime, so any + * future devices should already be covered) + * + * Regions can be write/erase protected. + * Whole (!) pages can be individually written with erase on the fly. + * Writing partial pages will corrupt the rest of the page. + * + * The flash is presented to u-boot with each region being a sector, + * having the following effects: + * Each sector can be hardware protected (protect on/off). + * Each page in a sector can be rewritten anytime. + * Since pages are erased when written, the "erase" does nothing. + * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected + * by u-Boot commands. + * + * Note: Redundant environment will not work in this flash since + * it does use partial page writes. Make sure the environent spans + * whole pages! + */ + +/* + * optional TODOs (nice to have features): + * + * make the driver coexist with other NOR flash drivers + * (use an index into flash_info[], requires work + * in those other drivers, too) + * Make the erase command fill the sectors with 0xff + * (if the flashes grow larger in the future and + * someone puts a jffs2 into them) + * do a read-modify-write for partially programmed pages + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_eefc.h> +#include <asm/arch/at91_dbu.h> + +/* checks to detect configuration errors */ +#if CONFIG_SYS_MAX_FLASH_BANKS!=1 +#error eflash: this driver can only handle 1 bank +#endif + +/* global structure */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static u32 pagesize; + +unsigned long flash_init (void) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + at91_dbu_t *dbu = (at91_dbu_t *) 0xfffff200; + u32 id, size, nplanes, planesize, nlocks; + u32 addr, i, tmp=0; + + debug("eflash: init\n"); + + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* check if its an AT91ARM9XE SoC */ + if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { + puts("eflash: not an AT91SAM9XE\n"); + return 0; + } + + /* now query the eflash for its structure */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + id = readl(&eefc->frr); /* word 0 */ + size = readl(&eefc->frr); /* word 1 */ + pagesize = readl(&eefc->frr); /* word 2 */ + nplanes = readl(&eefc->frr); /* word 3 */ + planesize = readl(&eefc->frr); /* word 4 */ + debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n", + id, size, pagesize, nplanes, planesize); + for (i=1; i<nplanes; i++) { + tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */ + }; + nlocks = readl(&eefc->frr); /* word 4+nplanes */ + debug("nlocks=%u\n", nlocks); + /* since we are going to use the lock regions as sectors, check count */ + if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) { + printf("eflash: number of lock regions(%u) "\ + "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n", + nlocks); + nlocks = CONFIG_SYS_MAX_FLASH_SECT; + } + flash_info[0].size = size; + flash_info[0].sector_count = nlocks; + flash_info[0].flash_id = id; + + addr = AT91SAM9XE_FLASH_BASE; + for (i=0; i<nlocks; i++) { + tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ + flash_info[0].start[i] = addr; + flash_info[0].protect[i] = 0; + addr += tmp; + }; + + /* now read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; i<flash_info[0].sector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + flash_info[0].protect[i] = (tmp >> (i%32)) & 1; +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (i < CONFIG_EFLASH_PROTSECTORS) + flash_info[0].protect[i] = 1; +#endif + } + + return size; +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + puts("AT91SAM9XE embedded flash\n Size: "); + print_size(info->size, " in "); + printf("%d Sectors\n", info->sector_count); + + printf(" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +int flash_real_protect (flash_info_t *info, long sector, int prot) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + u32 pagenum = (info->start[sector]-AT91SAM9XE_FLASH_BASE)/pagesize; + u32 i, tmp=0; + + debug("protect sector=%ld prot=%d\n", sector, prot); + +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (sector < CONFIG_EFLASH_PROTSECTORS) { + if (!prot) { + printf("eflash: sector %lu cannot be unprotected\n", + sector); + } + return 1; /* return anyway, caller does not care for result */ + } +#endif + if (prot) { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } else { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* now re-read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; i<info->sector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + info->protect[i] = (tmp >> (i%32)) & 1; + } + return 0; +} + +static u32 erase_write_page (u32 pagenum) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + + debug("erase+write page=%u\n", pagenum); + + /* give erase and write page command */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* return status */ + return readl(&eefc->fsr) + & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE); +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + debug("erase first=%d last=%d\n", s_first, s_last); + puts("this flash does not need and support erasing!\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + u32 pagenum; + u32 *src32, *dst32; + u32 i; + + debug("write src=%08lx addr=%08lx cnt=%lx\n", + (ulong)src, addr, cnt); + + /* REQUIRE addr to be on a page start, abort if not */ + if (addr % pagesize) { + printf ("eflash: start %08lx is not on page start\n"\ + " write aborted\n", addr); + return 1; + } + + /* now start copying data */ + pagenum = (addr-AT91SAM9XE_FLASH_BASE)/pagesize; + src32 = (u32 *) src; + dst32 = (u32 *) addr; + while (cnt > 0) { + i = pagesize / 4; + /* fill page buffer */ + while (i--) + *dst32++ = *src32++; + /* write page */ + if (erase_write_page(pagenum)) + return 1; + pagenum++; + if (cnt > pagesize) + cnt -= pagesize; + else + cnt = 0; + } + return 0; +} + diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index 1b67e77887f..d2569d8baea 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -27,18 +27,19 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/io.h> -/* - * Reset the cpu by setting up the watchdog timer and let him time out. - */ +/* Reset the cpu by telling the reset controller to do so */ void reset_cpu(ulong ignored) { at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; - /* this is the way Linux does it */ - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST, - &rstc->cr); - - while (1); - /* Never reached */ + writel(AT91_RSTC_KEY + | AT91_RSTC_CR_PROCRST /* Processor Reset */ + | AT91_RSTC_CR_PERRST /* Peripheral Reset */ +#ifdef CONFIG_AT91RESET_EXTRST + | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ +#endif + , &rstc->cr); + /* never reached */ + while (1) + ; } diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index d21eebfb4eb..8efc34bcf12 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -138,8 +138,5 @@ ulong get_timer(ulong base) */ ulong get_tbclk(void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return timer_freq; } diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index c63e8641f21..82c978bd93e 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -81,7 +81,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1; - for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; } diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile new file mode 100644 index 00000000000..ce3e5a5a5ac --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = clock.o reset.o timer.o +SOBJS = + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c new file mode 100644 index 00000000000..70c8c8b04a2 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * Get the peripheral bus frequency depending on pll pin settings + */ +ulong get_bus_freq(ulong dummy) +{ + struct mb86r0x_crg * crg = (struct mb86r0x_crg *) + MB86R0x_CRG_BASE; + uint32_t pllmode; + + pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; + + if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) + return 40000000; + + return 41164767; +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c new file mode 100644 index 00000000000..e7f0f6788bb --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * Reset the cpu by setting software reset request bit + */ +void reset_cpu(ulong ignored) +{ + struct mb86r0x_crg * crg = (struct mb86r0x_crg *) + MB86R0x_CRG_BASE; + + writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); + while (1) + /* NOP */; + /* Never reached */ +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c new file mode 100644 index 00000000000..9175b71d16a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2010 + * Matthias Weisser, Graf-Syteco <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <div64.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) + +static unsigned long long timestamp; +static ulong lastdec; + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ; + do_div(usec, 1000000); + + return usec; +} + +/* nothing really to do with interrupts, just starts up a counter. */ +int timer_init(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + ulong ctrl = readl(&timer->control); + + writel(TIMER_LOAD_VAL, &timer->load); + + ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | + MB86R0x_TIMER_SIZE_32; + + writel(ctrl, &timer->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + ulong now = readl(&timer->value); + + if (now <= lastdec) { + /* normal mode (non roll) */ + /* move stamp forward with absolut diff ticks */ + timestamp += lastdec - now; + } else { + /* we have rollover of incrementer */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + return timestamp; +} + +void reset_timer_masked(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + + /* capture current value time */ + lastdec = readl(&timer->value); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = usec_to_tick(usec); + tmp = get_ticks(); /* get current timestamp */ + + while ((get_ticks() - tmp) < tmo) /* loop till event */ + /*NOP*/; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = TIMER_FREQ; + return tbclk; +} diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 3740e33e9d8..260f88b46e0 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -61,7 +61,7 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1; - for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; } diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 3a4a304e45b..caee7263b15 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)libomap-common.a SOBJS := reset.o + COBJS := timer.o +COBJS += syslib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S index a53c4081958..838b1221ee2 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.S +++ b/arch/arm/cpu/armv7/omap-common/reset.S @@ -27,10 +27,12 @@ reset_cpu: ldr r1, rstctl @ get addr for global reset @ reg - mov r3, #0x2 @ full reset pll + mpu + ldr r3, rstbit @ sw reset bit str r3, [r1] @ force reset mov r0, r0 _loop_forever: b _loop_forever rstctl: .word PRM_RSTCTRL +rstbit: + .word PRM_RSTCTRL_RESET diff --git a/arch/arm/cpu/armv7/omap3/syslib.c b/arch/arm/cpu/armv7/omap-common/syslib.c index 9ced495c8d0..f9ed9a307b7 100644 --- a/arch/arm/cpu/armv7/omap3/syslib.c +++ b/arch/arm/cpu/armv7/omap-common/syslib.c @@ -23,8 +23,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> #include <asm/arch/sys_proto.h> /************************************************************ diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 79ae26706e7..95526d6893d 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -32,7 +32,6 @@ COBJS += board.o COBJS += clock.o COBJS += gpio.o COBJS += mem.o -COBJS += syslib.o COBJS += sys_info.o COBJS-$(CONFIG_EMIF4) += emif4.o diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 69e56f55c5b..6c2a132b63b 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -120,41 +120,6 @@ void secureworld_exit() } /****************************************************************************** - * Routine: setup_auxcr() - * Description: Write to AuxCR desired value using SMI. - * general use. - *****************************************************************************/ -void setup_auxcr() -{ - unsigned long i; - volatile unsigned int j; - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - /* Enabling ASA */ - __asm__ __volatile__("orr r0, r0, #0x10"); - /* Enable L1NEON */ - __asm__ __volatile__("orr r0, r0, #1 << 5"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */ - __asm__ __volatile__("mov r12, #0x2"); - __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2"); - __asm__ __volatile__("orr r0, r0, #1 << 27"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); -} - -/****************************************************************************** * Routine: try_unlock_sram() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index 4b65ac58a57..24e950f38cd 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -43,6 +43,7 @@ .global invalidate_dcache .global l2_cache_enable .global l2_cache_disable +.global setup_auxcr /* * invalidate_dcache() @@ -128,64 +129,56 @@ finished_inval: ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} - -l2_cache_enable: - stmfd r13!, {r0, r1, r2, lr} - @ ES2 onwards we can disable/enable L2 ourselves +l2_cache_set: + stmfd r13!, {r4 - r6, lr} + mov r5, r0 bl get_cpu_rev - cmp r0, #CPU_3XX_ES20 - blt l2_cache_disable_EARLIER_THAN_ES2 - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - b l2_cache_enable_END -l2_cache_enable_EARLIER_THAN_ES2: - @ Save r0, r12 and restore them after usage - mov r3, ip - str r3, [sp, #4] - mov r3, r0 - @ + mov r4, r0 + bl get_cpu_family + @ ES2 onwards we can disable/enable L2 ourselves + cmp r0, #CPU_OMAP34XX + cmpeq r4, #CPU_3XX_ES10 + mrc 15, 0, r0, cr1, cr0, 1 + bic r0, r0, #2 + orr r0, r0, r5, lsl #1 + mcreq 15, 0, r0, cr1, cr0, 1 @ GP Device ROM code API usage here @ r12 = AUXCR Write function and r0 value - @ mov ip, #3 - mrc 15, 0, r0, cr1, cr0, 1 - orr r0, r0, #2 - @ SMI instruction to call ROM Code API - .word 0xe1600070 - mov r0, r3 - mov ip, r3 - str r3, [sp, #4] -l2_cache_enable_END: - ldmfd r13!, {r1, r2, r3, pc} + @ SMCNE instruction to call ROM Code API + .word 0x11600070 + ldmfd r13!, {r4 - r6, pc} +l2_cache_enable: + mov r0, #1 + b l2_cache_set l2_cache_disable: - stmfd r13!, {r0, r1, r2, lr} - @ ES2 onwards we can disable/enable L2 ourselves - bl get_cpu_rev - cmp r0, #CPU_3XX_ES20 - blt l2_cache_disable_EARLIER_THAN_ES2 - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - b l2_cache_disable_END -l2_cache_disable_EARLIER_THAN_ES2: - @ Save r0, r12 and restore them after usage - mov r3, ip - str r3, [sp, #4] - mov r3, r0 - @ - @ GP Device ROM code API usage here - @ r12 = AUXCR Write function and r0 value - @ - mov ip, #3 - mrc 15, 0, r0, cr1, cr0, 1 - bic r0, r0, #2 - @ SMI instruction to call ROM Code API - .word 0xe1600070 - mov r0, r3 - mov ip, r3 - str r3, [sp, #4] -l2_cache_disable_END: - ldmfd r13!, {r1, r2, r3, pc} + mov r0, #0 + b l2_cache_set + +/****************************************************************************** + * Routine: setup_auxcr() + * Description: Write to AuxCR desired value using SMI. + * general use. + *****************************************************************************/ +setup_auxcr: + mrc p15, 0, r0, c0, c0, 0 @ read main ID register + and r2, r0, #0x00f00000 @ variant + and r3, r0, #0x0000000f @ revision + orr r1, r3, r2, lsr #20-4 @ combine variant and revision + mov r12, #0x3 + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x10 @ Enable ASA + @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround) + cmp r1, #0x21 + orrlt r0, r0, #1 << 5 + .word 0xE1600070 @ SMC + mov r12, #0x2 + mrc p15, 1, r0, c9, c0, 2 + @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround) + cmp r1, #0x21 + orrlt r0, r0, #1 << 27 + .word 0xE1600070 @ SMC + bx lr + diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 6330c9e5da4..2238c52e3be 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -50,12 +50,7 @@ u32 get_osc_clk_speed(void) if (val & SYSCLKDIV_2) cdiv = 2; - else if (val & SYSCLKDIV_1) - cdiv = 1; else - /* - * Should never reach here! (Assume divider as 1) - */ cdiv = 1; /* enable timer2 */ @@ -89,11 +84,7 @@ u32 get_osc_clk_speed(void) while (readl(&s32k_base->s32k_cr) < (start + 20)) ; cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */ - - if (cdiv == 2) - { - cdiff *= 2; - } + cdiff *= cdiv; /* based on number of ticks assign speed */ if (cdiff > 19000) @@ -135,65 +126,22 @@ void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) } } -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) +/* + * OMAP34XX/35XX specific functions + */ + +static void dpll3_init_34xx(u32 sil_index, u32 clk_index) { + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_core_dpll_param(); void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; - u32 osc_clk = 0, sys_clkin_sel; - u32 clk_index, sil_index = 0; - struct prm *prm_base = (struct prm *)PRM_BASE; - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *dpll_param_p; - - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); xip_safe = is_running_in_sram(); - /* - * Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - /* set input crystal speed */ - sr32(&prm_base->clksel, 0, 3, sys_clkin_sel); + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - /* input clock divider */ - sr32(&prm_base->clksrc_ctrl, 6, 2, 2); - clk_index = sys_clkin_sel / 2; - } else { - /* input clock divider */ - sr32(&prm_base->clksrc_ctrl, 6, 2, 1); - clk_index = sys_clkin_sel; - } - - /* - * The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if (get_cpu_rev()) - sil_index = 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; if (xip_safe) { /* * CORE DPLL @@ -208,34 +156,38 @@ void prcm_init(void) * work. write another value and then default value. */ - /* m3x2 */ - sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1); - /* m3x2 */ + /* CM_CLKSEL1_EMU[DIV_DPLL3] */ + sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ; sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); - /* Set M2 */ - sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2); - /* Set M */ - sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m); - /* Set N */ - sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n); - /* 96M Src */ + + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); + + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); + + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); + + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ sr32(&prcm_base->clksel1_pll, 6, 1, 0); - /* ssi */ + + /* SSI */ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); - /* fsusb */ + /* FSUSB */ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); - /* l4 */ + /* L4 */ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); - /* l3 */ + /* L3 */ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); - /* gfx */ - sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); - /* reset mgr */ + /* GFX */ + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + /* RESET MGR */ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); - /* FREQSEL */ - sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel); - /* lock mode */ - sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); + /* LOCK MODE */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); @@ -244,102 +196,405 @@ void prcm_init(void) * if running from flash, jump to small relocated code * area in SRAM. */ + f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + + SRAM_VECT_CODE); + p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); - sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&p0, 4, 4, ptr->fsel); p1 = readl(&prcm_base->clksel1_pll); - sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */ - sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */ - sr32(&p1, 6, 1, 0); /* set source for 96M */ + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&p1, 27, 5, ptr->m2); + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&p1, 16, 11, ptr->m); + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&p1, 8, 7, ptr->n); + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + sr32(&p1, 6, 1, 0); p2 = readl(&prcm_base->clksel_core); - sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */ + /* SSI */ + sr32(&p2, 8, 4, CORE_SSI_DIV); + /* FSUSB */ + sr32(&p2, 4, 2, CORE_FUSB_DIV); + /* L4 */ + sr32(&p2, 2, 2, CORE_L4_DIV); + /* L3 */ + sr32(&p2, 0, 2, CORE_L3_DIV); p3 = (u32)&prcm_base->idlest_ckgen; (*f_lock_pll) (p0, p1, p2, p3); } +} - /* PER DPLL */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); - wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); - - /* Getting the base address to PER DPLL param table */ - - /* Set N */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); +static void dpll4_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_per_dpll_param(); /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; + ptr = ptr + clk_index; + + /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* * Errata 1.50 Workaround for OMAP3 ES1.0 only * If using default divisors, write default divisor + 1 * and then the actual divisor value */ - sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */ - sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */ - sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */ - sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */ - sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */ - sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */ - sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */ - sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */ - sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */ - sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */ + /* M6 */ + sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1)); + sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); + /* M5 */ + sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1)); + sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); + /* M4 */ + sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1)); + sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); + /* M3 */ + sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1)); + sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); + /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ + sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1)); + sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2); /* Workaround end */ - sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */ - sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */ - sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */ + /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */ + sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m); + + /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ + sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n); + + /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */ + sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel); + + /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); +} - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); +static void mpu_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; /* MPU DPLL (unlocked already) */ - /* Set M2 */ - sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2); - /* Set M */ - sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m); - /* Set N */ - sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n); - /* FREQSEL */ - sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel); - /* lock mode */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); - wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* IVA DPLL (set to 12*20=240MHz) */ + /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ + sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2); + + /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m); + + /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ + sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n); + + /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */ + sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel); +} + +static void iva_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_iva_dpll_param(); + + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; + + /* IVA DPLL */ + /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ + sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); + wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); + + /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ + sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2); + + /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ + sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m); + + /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ + sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n); + + /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */ + sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel); + + /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ + sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); +} + +/* + * OMAP3630 specific functions + */ + +static void dpll3_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); + void (*f_lock_pll) (u32, u32, u32, u32); + int xip_safe, p0, p1, p2, p3; + + xip_safe = is_running_in_sram(); + + /* Moving it to the right sysclk base */ + ptr += clk_index; + + if (xip_safe) { + /* CORE DPLL */ + + /* Select relock bypass: CM_CLKEN_PLL[0:2] */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, + LDELAY); + + /* CM_CLKSEL1_EMU[DIV_DPLL3] */ + sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); + + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); + + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); + + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); + + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + sr32(&prcm_base->clksel1_pll, 6, 1, 0); + + /* SSI */ + sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); + /* FSUSB */ + sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); + /* L4 */ + sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); + /* L3 */ + sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); + /* GFX */ + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + /* RESET MGR */ + sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); + /* LOCK MODE */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + + wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, + LDELAY); + } else if (is_running_in_flash()) { + /* + * if running from flash, jump to small relocated code + * area in SRAM. + */ + f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + + SRAM_VECT_CODE); + + p0 = readl(&prcm_base->clken_pll); + sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&p0, 4, 4, ptr->fsel); + + p1 = readl(&prcm_base->clksel1_pll); + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&p1, 27, 5, ptr->m2); + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&p1, 16, 11, ptr->m); + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&p1, 8, 7, ptr->n); + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + sr32(&p1, 6, 1, 0); + + p2 = readl(&prcm_base->clksel_core); + /* SSI */ + sr32(&p2, 8, 4, CORE_SSI_DIV); + /* FSUSB */ + sr32(&p2, 4, 2, CORE_FUSB_DIV); + /* L4 */ + sr32(&p2, 2, 2, CORE_L4_DIV); + /* L3 */ + sr32(&p2, 0, 2, CORE_L3_DIV); + + p3 = (u32)&prcm_base->idlest_ckgen; + + (*f_lock_pll) (p0, p1, p2, p3); + } +} + +static void dpll4_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct dpll_per_36x_param *ptr; + + ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr += clk_index; + + /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); + + /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */ + sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6); + + /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ + sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5); + + /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ + sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4); + + /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */ + sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3); + + /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ + sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2); + + /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */ + sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m); + + /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ + sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n); + + /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */ + sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div); + + /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); + wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); +} + +static void mpu_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param(); + + /* Moving to the right sysclk */ + ptr += clk_index; + + /* MPU DPLL (unlocked already */ + + /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ + sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2); + + /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m); + + /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ + sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n); +} + +static void iva_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param(); + + /* Moving to the right sysclk */ + ptr += clk_index; + + /* IVA DPLL */ + /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); - /* set M2 */ - sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2); - /* set M */ - sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m); - /* set N */ - sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n); - /* FREQSEL */ - sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel); - /* lock mode */ + + /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ + sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2); + + /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ + sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m); + + /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ + sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n); + + /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk = 0, sys_clkin_sel; + u32 clk_index, sil_index = 0; + struct prm *prm_base = (struct prm *)PRM_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* + * Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + /* set input crystal speed */ + sr32(&prm_base->clksel, 0, 3, sys_clkin_sel); + + /* If the input clock is greater than 19.2M always divide/2 */ + if (sys_clkin_sel > 2) { + /* input clock divider */ + sr32(&prm_base->clksrc_ctrl, 6, 2, 2); + clk_index = sys_clkin_sel / 2; + } else { + /* input clock divider */ + sr32(&prm_base->clksrc_ctrl, 6, 2, 1); + clk_index = sys_clkin_sel; + } + + if (get_cpu_family() == CPU_OMAP36XX) { + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, + LDELAY); + + dpll3_init_36xx(0, clk_index); + dpll4_init_36xx(0, clk_index); + iva_init_36xx(0, clk_index); + mpu_init_36xx(0, clk_index); + + /* Lock MPU DPLL to set frequency */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, + LDELAY); + } else { + /* + * The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + if (((get_cpu_family() == CPU_OMAP34XX) + && (get_cpu_rev() >= CPU_3XX_ES20)) || + (get_cpu_family() == CPU_AM35XX)) + sil_index = 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, + LDELAY); + + dpll3_init_34xx(sil_index, clk_index); + dpll4_init_34xx(sil_index, clk_index); + iva_init_34xx(sil_index, clk_index); + mpu_init_34xx(sil_index, clk_index); + + /* Lock MPU DPLL to set frequency */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, + LDELAY); + } /* Set up GPTimers to sys_clk source only */ sr32(&prcm_base->clksel_per, 0, 8, 0xff); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 73063ec8e66..91c6dbcc092 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -359,3 +359,72 @@ per_dpll_param: get_per_dpll_param: adr r0, per_dpll_param mov pc, lr + +/* + * Tables for 36XX/37XX devices + * + */ +mpu_36x_dpll_param: +/* 12MHz */ +.word 50, 0, 0, 1 +/* 13MHz */ +.word 600, 12, 0, 1 +/* 19.2MHz */ +.word 125, 3, 0, 1 +/* 26MHz */ +.word 300, 12, 0, 1 +/* 38.4MHz */ +.word 125, 7, 0, 1 + +iva_36x_dpll_param: +/* 12MHz */ +.word 130, 2, 0, 1 +/* 13MHz */ +.word 20, 0, 0, 1 +/* 19.2MHz */ +.word 325, 11, 0, 1 +/* 26MHz */ +.word 10, 0, 0, 1 +/* 38.4MHz */ +.word 325, 23, 0, 1 + +core_36x_dpll_param: +/* 12MHz */ +.word 100, 2, 0, 1 +/* 13MHz */ +.word 400, 12, 0, 1 +/* 19.2MHz */ +.word 375, 17, 0, 1 +/* 26MHz */ +.word 200, 12, 0, 1 +/* 38.4MHz */ +.word 375, 35, 0, 1 + +per_36x_dpll_param: +/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ +.word 12000, 360, 4, 9, 16, 5, 4, 3, 1 +.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 +.word 19200, 360, 7, 9, 16, 5, 4, 3, 1 +.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 +.word 38400, 360, 15, 9, 16, 5, 4, 3, 1 + +.globl get_36x_mpu_dpll_param +get_36x_mpu_dpll_param: + adr r0, mpu_36x_dpll_param + mov pc, lr + +.globl get_36x_iva_dpll_param +get_36x_iva_dpll_param: + adr r0, iva_36x_dpll_param + mov pc, lr + +.globl get_36x_core_dpll_param +get_36x_core_dpll_param: + adr r0, core_36x_dpll_param + mov pc, lr + +.globl get_36x_per_dpll_param +get_36x_per_dpll_param: + adr r0, per_36x_dpll_param + mov pc, lr + diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 96fd990c71c..8905224439b 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -107,18 +107,12 @@ u32 get_sdr_cs_offset(u32 cs) /* * do_sdrc_init - * - Initialize the SDRAM for use. - * - Sets up SDRC timings for CS0 * - code called once in C-Stack only context for CS0 and a possible 2nd * time depending on memory configuration from stack+global context */ void do_sdrc_init(u32 cs, u32 early) { - struct sdrc_actim *sdrc_actim_base; - - if (cs) - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - else - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; if (early) { /* reset sdrc controller */ @@ -138,24 +132,29 @@ void do_sdrc_init(u32 cs, u32 early) sdelay(0x20000); } - writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | - RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | - DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); - writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); - writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); - - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - /* - * CAS latency 3, Write Burst = Read Burst, Serial Mode, - * Burst length = 4 + * SDRC timings are set up by x-load or config header + * We don't need to redo them here. + * Older x-loads configure only CS0 + * configure CS1 to handle this ommission */ - writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); + if (cs) { + sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + writel(readl(&sdrc_base->cs[CS0].mcfg), + &sdrc_base->cs[CS1].mcfg); + writel(readl(&sdrc_base->cs[CS0].rfr_ctrl), + &sdrc_base->cs[CS1].rfr_ctrl); + writel(readl(&sdrc_actim_base0->ctrla), + &sdrc_actim_base1->ctrla); + writel(readl(&sdrc_actim_base0->ctrlb), + &sdrc_actim_base1->ctrlb); + } + /* + * Test ram in this bank + * Disable if bad or not present + */ if (!mem_ok(cs)) writel(0, &sdrc_base->cs[cs].mcfg); } diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 1df4401d492..549ac19189d 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -38,7 +38,10 @@ static char *rev_s[CPU_3XX_MAX_REV] = { "2.0", "2.1", "3.0", - "3.1"}; + "3.1", + "UNKNOWN", + "UNKNOWN", + "3.1.2"}; /***************************************************************** * dieid_num_r(void) - read and set die ID @@ -75,32 +78,81 @@ u32 get_cpu_type(void) } /****************************************** - * get_cpu_rev(void) - extract version info + * get_cpu_id(void) - extract cpu id + * returns 0 for ES1.0, cpuid otherwise ******************************************/ -u32 get_cpu_rev(void) +u32 get_cpu_id(void) { - u32 cpuid = 0; struct ctrl_id *id_base; + u32 cpuid = 0; /* * On ES1.0 the IDCODE register is not exposed on L4 * so using CPU ID to differentiate between ES1.0 and > ES1.0. */ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) - return CPU_3XX_ES10; - else { + if ((cpuid & 0xf) == 0x0) { + return 0; + } else { /* Decode the IDs on > ES1.0 */ id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE; - cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf; + cpuid = readl(&id_base->idcode); + } - /* Some early ES2.0 seem to report ID 0, fix this */ - if(cpuid == 0) - cpuid = CPU_3XX_ES20; + return cpuid; +} - return cpuid; +/****************************************** + * get_cpu_family(void) - extract cpu info + ******************************************/ +u32 get_cpu_family(void) +{ + u16 hawkeye; + u32 cpu_family; + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_OMAP34XX; + + hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; + switch (hawkeye) { + case HAWKEYE_OMAP34XX: + cpu_family = CPU_OMAP34XX; + break; + case HAWKEYE_AM35XX: + cpu_family = CPU_AM35XX; + break; + case HAWKEYE_OMAP36XX: + cpu_family = CPU_OMAP36XX; + break; + default: + cpu_family = CPU_OMAP34XX; } + + return cpu_family; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_3XX_ES10; + else + return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; +} + +/***************************************************************** + * get_sku_id(void) - read sku_id to get info on max clock rate + *****************************************************************/ +u32 get_sku_id(void) +{ + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; + return readl(&id_base->sku_id) & SKUID_CLK_MASK; } /*************************************************************************** @@ -213,24 +265,66 @@ u32 get_device_type(void) */ int print_cpuinfo (void) { - char *cpu_s, *sec_s; + char *cpu_family_s, *cpu_s, *sec_s, *max_clk; + + switch (get_cpu_family()) { + case CPU_OMAP34XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3503: + cpu_s = "3503"; + break; + case OMAP3515: + cpu_s = "3515"; + break; + case OMAP3525: + cpu_s = "3525"; + break; + case OMAP3530: + cpu_s = "3530"; + break; + default: + cpu_s = "35XX"; + break; + } + if ((get_cpu_rev() >= CPU_3XX_ES31) && + (get_sku_id() == SKUID_CLK_720MHZ)) + max_clk = "720 mHz"; + else + max_clk = "600 mHz"; - switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; break; - case OMAP3515: - cpu_s = "3515"; + case CPU_AM35XX: + cpu_family_s = "AM"; + switch (get_cpu_type()) { + case AM3505: + cpu_s = "3505"; + break; + case AM3517: + cpu_s = "3517"; + break; + default: + cpu_s = "35XX"; + break; + } + max_clk = "600 Mhz"; break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; + case CPU_OMAP36XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3730: + cpu_s = "3630/3730"; + break; + default: + cpu_s = "36XX/37XX"; + break; + } + max_clk = "1 Ghz"; break; default: + cpu_family_s = "OMAP"; cpu_s = "35XX"; - break; + max_clk = "600 Mhz"; } switch (get_device_type()) { @@ -250,8 +344,9 @@ int print_cpuinfo (void) sec_s = "?"; } - printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n", - cpu_s, sec_s, rev_s[get_cpu_rev()]); + printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s[get_cpu_rev()], max_clk); return 0; } diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile new file mode 100644 index 00000000000..37371f6fda6 --- /dev/null +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2009 Samsung Electronics +# Minkyu Kang <mk7.kang@samsung.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libs5p-common.a + +COBJS-y += cpu_info.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index f16c0ff1307..2f6c7085546 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -25,15 +25,14 @@ #include <asm/arch/clk.h> /* Default is s5pc100 */ -unsigned int s5pc1xx_cpu_id = 0xC100; +unsigned int s5p_cpu_id = 0xC100; #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { - s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID); - s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12); + s5p_set_cpu_id(); - s5pc1xx_clock_init(); + s5p_clock_init(); return 0; } @@ -41,7 +40,7 @@ int arch_cpu_init(void) u32 get_device_type(void) { - return s5pc1xx_cpu_id; + return s5p_cpu_id; } #ifdef CONFIG_DISPLAY_CPUINFO @@ -50,7 +49,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU:\tS5P%X@%sMHz\n", - s5pc1xx_cpu_id, strmhz(buf, get_arm_clk())); + s5p_cpu_id, strmhz(buf, get_arm_clk())); return 0; } diff --git a/arch/arm/cpu/armv7/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index c5df5c5ab53..04906503e6e 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -44,23 +44,20 @@ static unsigned long long timestamp; /* Monotonic incrementing timer */ static unsigned long lastdec; /* Last decremneter snapshot */ /* macro to read the 16 bit timer */ -static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void) +static inline struct s5p_timer *s5p_get_base_timer(void) { - if (cpu_is_s5pc110()) - return (struct s5pc1xx_timer *)S5PC110_TIMER_BASE; - else - return (struct s5pc1xx_timer *)S5PC100_TIMER_BASE; + return (struct s5p_timer *)samsung_get_base_timer(); } int timer_init(void) { - struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + struct s5p_timer *const timer = s5p_get_base_timer(); u32 val; /* * @ PWM Timer 4 * Timer Freq(HZ) = - * PCLK / { (prescaler_value + 1) * (divider_value) } + * PWM_CLK / { (prescaler_value + 1) * (divider_value) } */ /* set prescaler : 16 */ @@ -71,7 +68,7 @@ int timer_init(void) if (count_value == 0) { /* reset initial value */ /* count_value = 2085937.5(HZ) (per 1 sec)*/ - count_value = get_pclk() / ((PRESCALER_1 + 1) * + count_value = get_pwm_clk() / ((PRESCALER_1 + 1) * (MUX_DIV_2 + 1)); /* count_value / 100 = 20859.375(HZ) (per 10 msec) */ @@ -83,13 +80,13 @@ int timer_init(void) lastdec = count_value; val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) | - S5PC1XX_TCON4_AUTO_RELOAD; + TCON4_AUTO_RELOAD; /* auto reload & manual update */ - writel(val | S5PC1XX_TCON4_UPDATE, &timer->tcon); + writel(val | TCON4_UPDATE, &timer->tcon); /* start PWM timer 4 */ - writel(val | S5PC1XX_TCON4_START, &timer->tcon); + writel(val | TCON4_START, &timer->tcon); timestamp = 0; @@ -154,7 +151,7 @@ void __udelay(unsigned long usec) void reset_timer_masked(void) { - struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + struct s5p_timer *const timer = s5p_get_base_timer(); /* reset time */ lastdec = readl(&timer->tcnto4); @@ -163,7 +160,7 @@ void reset_timer_masked(void) unsigned long get_timer_masked(void) { - struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + struct s5p_timer *const timer = s5p_get_base_timer(); unsigned long now = readl(&timer->tcnto4); if (lastdec >= now) diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile index 3785593d25a..263945f4e77 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Makefile +++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile @@ -32,9 +32,7 @@ SOBJS = cache.o SOBJS += reset.o COBJS += clock.o -COBJS += cpu_info.o COBJS += sromc.o -COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c index 19619f92cd9..98a27e551db 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c +++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c @@ -38,14 +38,16 @@ #define CONFIG_SYS_CLK_FREQ_C110 24000000 #endif -unsigned long (*get_pclk)(void); +unsigned long (*get_uart_clk)(int dev_index); +unsigned long (*get_pwm_clk)(void); unsigned long (*get_arm_clk)(void); unsigned long (*get_pll_clk)(int); /* s5pc110: return pll clock frequency */ static unsigned long s5pc100_get_pll_clk(int pllreg) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, mask, fout; unsigned int freq; @@ -95,7 +97,8 @@ static unsigned long s5pc100_get_pll_clk(int pllreg) /* s5pc100: return pll clock frequency */ static unsigned long s5pc110_get_pll_clk(int pllreg) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, mask, fout; unsigned int freq; @@ -151,7 +154,8 @@ static unsigned long s5pc110_get_pll_clk(int pllreg) /* s5pc110: return ARM clock frequency */ static unsigned long s5pc110_get_arm_clk(void) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll, armclk; unsigned int apll_ratio; @@ -170,7 +174,8 @@ static unsigned long s5pc110_get_arm_clk(void) /* s5pc100: return ARM clock frequency */ static unsigned long s5pc100_get_arm_clk(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll, armclk; unsigned int apll_ratio, arm_ratio; @@ -191,7 +196,8 @@ static unsigned long s5pc100_get_arm_clk(void) /* s5pc100: return HCLKD0 frequency */ static unsigned long get_hclk(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long hclkd0; uint div, d0_bus_ratio; @@ -207,7 +213,8 @@ static unsigned long get_hclk(void) /* s5pc100: return PCLKD1 frequency */ static unsigned long get_pclkd1(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long d1_bus, pclkd1; uint div, d1_bus_ratio, pclkd1_ratio; @@ -227,7 +234,8 @@ static unsigned long get_pclkd1(void) /* s5pc110: return HCLKs frequency */ static unsigned long get_hclk_sys(int dom) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long hclk; unsigned int div; unsigned int offset; @@ -255,7 +263,8 @@ static unsigned long get_hclk_sys(int dom) /* s5pc110: return PCLKs frequency */ static unsigned long get_pclk_sys(int dom) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long pclk; unsigned int div; unsigned int offset; @@ -289,15 +298,33 @@ static unsigned long s5pc100_get_pclk(void) return get_pclkd1(); } -void s5pc1xx_clock_init(void) +/* s5pc1xx: return uart clock frequency */ +static unsigned long s5pc1xx_get_uart_clk(int dev_index) +{ + if (cpu_is_s5pc110()) + return s5pc110_get_pclk(); + else + return s5pc100_get_pclk(); +} + +/* s5pc1xx: return pwm clock frequency */ +static unsigned long s5pc1xx_get_pwm_clk(void) +{ + if (cpu_is_s5pc110()) + return s5pc110_get_pclk(); + else + return s5pc100_get_pclk(); +} + +void s5p_clock_init(void) { if (cpu_is_s5pc110()) { get_pll_clk = s5pc110_get_pll_clk; get_arm_clk = s5pc110_get_arm_clk; - get_pclk = s5pc110_get_pclk; } else { get_pll_clk = s5pc100_get_pll_clk; get_arm_clk = s5pc100_get_arm_clk; - get_pclk = s5pc100_get_pclk; } + get_uart_clk = s5pc1xx_get_uart_clk; + get_pwm_clk = s5pc1xx_get_pwm_clk; } diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S index 7f6ff9c35f2..70fa146cf38 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S @@ -28,7 +28,7 @@ .globl reset_cpu reset_cpu: - ldr r1, =S5PC1XX_PRO_ID + ldr r1, =S5PC100_PRO_ID ldr r2, [r1] ldr r4, =0x00010000 and r4, r2, r4 diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c index 380be81be5e..044d12298db 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c +++ b/arch/arm/cpu/armv7/s5pc1xx/sromc.c @@ -35,12 +35,8 @@ void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) { u32 tmp; - struct s5pc1xx_smc *srom; - - if (cpu_is_s5pc100()) - srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; - else - srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; + struct s5pc1xx_smc *srom = + (struct s5pc1xx_smc *)samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 01840eede41..0067190a20e 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -27,6 +27,7 @@ void at91_can_hw_init(void); void at91_macb_hw_init(void); +void at91_mci_hw_init(void); void at91_serial_hw_init(void); void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h new file mode 100644 index 00000000000..34292935359 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_dbu.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * Debug Unit + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBU_H +#define AT91_DBU_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_dbu { + u32 cr; /* Control Register WO */ + u32 mr; /* Mode Register RW */ + u32 ier; /* Interrupt Enable Register WO */ + u32 idr; /* Interrupt Disable Register WO */ + u32 imr; /* Interrupt Mask Register RO */ + u32 sr; /* Status Register RO */ + u32 rhr; /* Receive Holding Register RO */ + u32 thr; /* Transmit Holding Register WO */ + u32 brgr; /* Baud Rate Generator Register RW */ + u32 res1[7];/* 0x0024 - 0x003C Reserved */ + u32 cidr; /* Chip ID Register RO */ + u32 exid; /* Chip ID Extension Register RO */ + u32 fnr; /* Force NTRST Register RW */ +} at91_dbu_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_DBU_CID_ARCH_MASK 0x0ff00000 +#define AT91_DBU_CID_ARCH_9xx 0x01900000 +#define AT91_DBU_CID_ARCH_9XExx 0x02900000 + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/include/asm/arch-at91/at91_eefc.h new file mode 100644 index 00000000000..d45b3deca48 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_eefc.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * Enhanced Embedded Flash Controller + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_EEFC_H +#define AT91_EEFC_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_eefc { + u32 fmr; /* Flash Mode Register RW */ + u32 fcr; /* Flash Command Register WO */ + u32 fsr; /* Flash Status Register RO */ + u32 frr; /* Flash Result Register RO */ +} at91_eefc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_EEFC_FMR_FWS_MASK 0x00000f00 +#define AT91_EEFC_FMR_FRDY_BIT 0x00000001 + +#define AT91_EEFC_FCR_KEY 0x5a000000 +#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 +#define AT91_EEFC_FCR_FARG_SHIFT 8 +#define AT91_EEFC_FCR_FCMD_GETD 0x0 +#define AT91_EEFC_FCR_FCMD_WP 0x1 +#define AT91_EEFC_FCR_FCMD_WPL 0x2 +#define AT91_EEFC_FCR_FCMD_EWP 0x3 +#define AT91_EEFC_FCR_FCMD_EWPL 0x4 +#define AT91_EEFC_FCR_FCMD_EA 0x5 +#define AT91_EEFC_FCR_FCMD_SLB 0x8 +#define AT91_EEFC_FCR_FCMD_CLB 0x9 +#define AT91_EEFC_FCR_FCMD_GLB 0xA +#define AT91_EEFC_FCR_FCMD_SGPB 0xB +#define AT91_EEFC_FCR_FCMD_CGPB 0xC +#define AT91_EEFC_FCR_FCMD_GGPB 0xD + +#define AT91_EEFC_FSR_FRDY 1 +#define AT91_EEFC_FSR_FCMDE 2 +#define AT91_EEFC_FSR_FLOCKE 4 + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/include/asm/arch-at91/at91_gpbr.h new file mode 100644 index 00000000000..cf1d790dd9d --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_gpbr.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * General Purpose Backup Registers + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_GPBR_H +#define AT91_GPBR_H + +/* + * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile + * 32 Bit registers (buffered by the Vbu power). + * + * Please consider carefully before using this resource for tasks + * that do not really need nonvolatile registers. Maybe you can + * store information in EEPROM or FLASH instead. + * + * However, if you use a GPBR please document its use here and + * reference the define in your code! + * + * known typical uses of the GPBRs: + * GPBR[0]: offset for RTT timekeeping (u-boot, kernel) + * GPBR[1]: unused + * GPBR[2]: unused + * GPBR[3]: bootcount (u-boot) + */ +#define AT91_GPBR_INDEX_TIMEOFF 0 +#define AT91_GPBR_INDEX_BOOTCOUNT 3 + +#ifndef __ASSEMBLY__ + +typedef struct at91_gpbr { + u32 reg[4]; +} at91_gpbr_t; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h index 5615a0206ca..61aca79418a 100644 --- a/arch/arm/include/asm/arch-at91/at91_pit.h +++ b/arch/arm/include/asm/arch-at91/at91_pit.h @@ -25,7 +25,7 @@ typedef struct at91_pit { #define AT91_PIT_MR_IEN 0x02000000 #define AT91_PIT_MR_EN 0x01000000 -#define AT91_PIT_MR_PIV_MASK (x & 0x000fffff) +#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff) #define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) #ifdef CONFIG_AT91_LEGACY diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/include/asm/arch-at91/at91_rtt.h new file mode 100644 index 00000000000..e0253ef8214 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_rtt.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * Real-time Timer + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_RTT_H +#define AT91_RTT_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_rtt { + u32 mr; /* Mode Register RW 0x00008000 */ + u32 ar; /* Alarm Register RW 0xFFFFFFFF */ + u32 vr; /* Value Register RO 0x00000000 */ + u32 sr; /* Status Register RO 0x00000000 */ +} at91_rtt_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_RTT_MR_RTPRES 0x0000ffff +#define AT91_RTT_MR_ALMIEN 0x00010000 +#define AT91_RTT_RTTINCIEN 0x00020000 +#define AT91_RTT_RTTRST 0x00040000 + +#define AT91_RTT_SR_ALMS 0x00000001 +#define AT91_RTT_SR_RTTINC 0x00000002 + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index ec043180369..cb34a94a3b3 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -59,7 +59,15 @@ #define AT91_RTT_BASE 0xfffffd20 #define AT91_PIT_BASE 0xfffffd30 #define AT91_WDT_BASE 0xfffffd40 -#define AT91_GPR_BASE 0xfffffd50 +/* + * The AT91SAM9XE has the GPBRs at a different address than + * the AT91SAM9260/9G20. + */ +#ifdef CONFIG_AT91SAM9XE +# define AT91_GPR_BASE 0xfffffd60 +#else +# define AT91_GPR_BASE 0xfffffd50 +#endif #ifdef CONFIG_AT91_LEGACY @@ -140,10 +148,12 @@ /* * Cpu Name */ -#if defined(CONFIG_AT91SAM9260) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" +#if defined(CONFIG_AT91SAM9XE) +# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9XE" +#elif defined(CONFIG_AT91SAM9260) +# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" #elif defined(CONFIG_AT91SAM9G20) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" +# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" #endif #endif diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index f642dd99585..457e6c9b2b5 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 4ddb3155d7c..9f732a738e2 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -20,6 +20,7 @@ #include <asm/arch-at91/at91rm9200.h> #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #include <asm/arch/at91sam9260.h> +#define AT91_BASE_MCI AT91SAM9260_BASE_MCI #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h new file mode 100644 index 00000000000..0bc5279137b --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef ASM_OFFSETS_H +#define ASM_OFFSETS_H + +/* + * Offset definitions for DDR controller + */ +#define DDR2_DRIC 0x00 +#define DDR2_DRIC1 0x02 +#define DDR2_DRIC2 0x04 +#define DDR2_DRCA 0x06 +#define DDR2_DRCM 0x08 +#define DDR2_DRCST1 0x0a +#define DDR2_DRCST2 0x0c +#define DDR2_DRCR 0x0e +#define DDR2_DRCF 0x20 +#define DDR2_DRASR 0x30 +#define DDR2_DRIMS 0x50 +#define DDR2_DROS 0x60 +#define DDR2_DRIBSODT1 0x64 +#define DDR2_DROABA 0x70 +#define DDR2_DROBS 0x84 + +/* + * Offset definitions Chip Control Module + */ +#define CCNT_CDCRC 0xec + +/* + * Offset definitions clock reset generator + */ +#define CRG_CRPR 0x00 +#define CRG_CRHA 0x18 +#define CRG_CRPA 0x1c +#define CRG_CRPB 0x20 +#define CRG_CRHB 0x24 +#define CRG_CRAM 0x28 + +/* + * Offset definitions External bus interface + */ +#define MEMC_MCFMODE0 0x00 +#define MEMC_MCFMODE2 0x08 +#define MEMC_MCFMODE4 0x10 +#define MEMC_MCFTIM0 0x20 +#define MEMC_MCFTIM2 0x28 +#define MEMC_MCFTIM4 0x30 +#define MEMC_MCFAREA0 0x40 +#define MEMC_MCFAREA2 0x48 +#define MEMC_MCFAREA4 0x50 + +#endif /* ASM_OFFSETS_H */ diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h new file mode 100644 index 00000000000..d1e57c03497 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/mb86r0x.h> + +#endif diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h new file mode 100644 index 00000000000..36a28b7af33 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h @@ -0,0 +1,573 @@ +/* + * (C) Copyright 2007 + * + * mb86r0x definitions + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MB86R0X_H +#define MB86R0X_H + +#ifndef __ASSEMBLY__ + +/* GPIO registers */ +struct mb86r0x_gpio { + uint32_t gpdr0; + uint32_t gpdr1; + uint32_t gpdr2; + uint32_t res; + uint32_t gpddr0; + uint32_t gpddr1; + uint32_t gpddr2; +}; + +/* PWM registers */ +struct mb86r0x_pwm { + uint32_t bcr; + uint32_t tpr; + uint32_t pr; + uint32_t dr; + uint32_t cr; + uint32_t sr; + uint32_t ccr; + uint32_t ir; +}; + +/* The mb86r0x chip control (CCNT) register set. */ +struct mb86r0x_ccnt { + uint32_t ccid; + uint32_t csrst; + uint32_t pad0[2]; + uint32_t cist; + uint32_t cistm; + uint32_t cgpio_ist; + uint32_t cgpio_istm; + uint32_t cgpio_ip; + uint32_t cgpio_im; + uint32_t caxi_bw; + uint32_t caxi_ps; + uint32_t cmux_md; + uint32_t cex_pin_st; + uint32_t cmlb; + uint32_t pad1[1]; + uint32_t cusb; + uint32_t pad2[41]; + uint32_t cbsc; + uint32_t cdcrc; + uint32_t cmsr0; + uint32_t cmsr1; + uint32_t pad3[2]; +}; + +/* The mb86r0x clock reset generator */ +struct mb86r0x_crg { + uint32_t crpr; + uint32_t pad0; + uint32_t crwr; + uint32_t crsr; + uint32_t crda; + uint32_t crdb; + uint32_t crha; + uint32_t crpa; + uint32_t crpb; + uint32_t crhb; + uint32_t cram; +}; + +/* The mb86r0x timer */ +struct mb86r0x_timer { + uint32_t load; + uint32_t value; + uint32_t control; + uint32_t intclr; + uint32_t ris; + uint32_t mis; + uint32_t bgload; +}; + +/* mb86r0x gdc display controller */ +struct mb86r0x_gdc_dsp { + /* Display settings */ + uint32_t dcm0; + uint16_t pad00; + uint16_t htp; + uint16_t hdp; + uint16_t hdb; + uint16_t hsp; + uint8_t hsw; + uint8_t vsw; + uint16_t pad01; + uint16_t vtr; + uint16_t vsp; + uint16_t vdp; + uint16_t wx; + uint16_t wy; + uint16_t ww; + uint16_t wh; + + /* Layer 0 */ + uint32_t l0m; + uint32_t l0oa; + uint32_t l0da; + uint16_t l0dx; + uint16_t l0dy; + + /* Layer 1 */ + uint32_t l1m; + uint32_t cbda0; + uint32_t cbda1; + uint32_t pad02; + + /* Layer 2 */ + uint32_t l2m; + uint32_t l2oa0; + uint32_t l2da0; + uint32_t l2oa1; + uint32_t l2da1; + uint16_t l2dx; + uint16_t l2dy; + + /* Layer 3 */ + uint32_t l3m; + uint32_t l3oa0; + uint32_t l3da0; + uint32_t l3oa1; + uint32_t l3da1; + uint16_t l3dx; + uint16_t l3dy; + + /* Layer 4 */ + uint32_t l4m; + uint32_t l4oa0; + uint32_t l4da0; + uint32_t l4oa1; + uint32_t l4da1; + uint16_t l4dx; + uint16_t l4dy; + + /* Layer 5 */ + uint32_t l5m; + uint32_t l5oa0; + uint32_t l5da0; + uint32_t l5oa1; + uint32_t l5da1; + uint16_t l5dx; + uint16_t l5dy; + + /* Cursor */ + uint16_t cutc; + uint8_t cpm; + uint8_t csize; + uint32_t cuoa0; + uint16_t cux0; + uint16_t cuy0; + uint32_t cuoa1; + uint16_t cux1; + uint16_t cuy1; + + /* Layer blending */ + uint32_t l0bld; + uint32_t pad03; + uint32_t l0tc; + uint16_t l3tc; + uint16_t l2tc; + uint32_t pad04[15]; + + /* Display settings */ + uint32_t dcm1; + uint32_t dcm2; + uint32_t dcm3; + uint32_t pad05; + + /* Layer 0 extended */ + uint32_t l0em; + uint16_t l0wx; + uint16_t l0wy; + uint16_t l0ww; + uint16_t l0wh; + uint32_t pad06; + + /* Layer 1 extended */ + uint32_t l1em; + uint16_t l1wx; + uint16_t l1wy; + uint16_t l1ww; + uint16_t l1wh; + uint32_t pad07; + + /* Layer 2 extended */ + uint32_t l2em; + uint16_t l2wx; + uint16_t l2wy; + uint16_t l2ww; + uint16_t l2wh; + uint32_t pad08; + + /* Layer 3 extended */ + uint32_t l3em; + uint16_t l3wx; + uint16_t l3wy; + uint16_t l3ww; + uint16_t l3wh; + uint32_t pad09; + + /* Layer 4 extended */ + uint32_t l4em; + uint16_t l4wx; + uint16_t l4wy; + uint16_t l4ww; + uint16_t l4wh; + uint32_t pad10; + + /* Layer 5 extended */ + uint32_t l5em; + uint16_t l5wx; + uint16_t l5wy; + uint16_t l5ww; + uint16_t l5wh; + uint32_t pad11; + + /* Multi screen control */ + uint32_t msc; + uint32_t pad12[3]; + uint32_t dls; + uint32_t dbgc; + + /* Layer blending */ + uint32_t l1bld; + uint32_t l2bld; + uint32_t l3bld; + uint32_t l4bld; + uint32_t l5bld; + uint32_t pad13; + + /* Extended transparency control */ + uint32_t l0etc; + uint32_t l1etc; + uint32_t l2etc; + uint32_t l3etc; + uint32_t l4etc; + uint32_t l5etc; + uint32_t pad14[10]; + + /* YUV coefficients */ + uint32_t l1ycr0; + uint32_t l1ycr1; + uint32_t l1ycg0; + uint32_t l1ycg1; + uint32_t l1ycb0; + uint32_t l1ycb1; + uint32_t pad15[130]; + + /* Layer palletes */ + uint32_t l0pal[256]; + uint32_t l1pal[256]; + uint32_t pad16[256]; + uint32_t l2pal[256]; + uint32_t l3pal[256]; + uint32_t pad17[256]; + + /* PWM settings */ + uint32_t vpwmm; + uint16_t vpwms; + uint16_t vpwme; + uint32_t vpwmc; + uint32_t pad18[253]; +}; + +/* mb86r0x gdc capture controller */ +struct mb86r0x_gdc_cap { + uint32_t vcm; + uint32_t csc; + uint32_t vcs; + uint32_t pad01; + + uint32_t cbm; + uint32_t cboa; + uint32_t cbla; + uint16_t cihstr; + uint16_t civstr; + uint16_t cihend; + uint16_t civend; + uint32_t pad02; + + uint32_t chp; + uint32_t cvp; + uint32_t pad03[4]; + + uint32_t clpf; + uint32_t pad04; + uint32_t cmss; + uint32_t cmds; + uint32_t pad05[12]; + + uint32_t rgbhc; + uint32_t rgbhen; + uint32_t rgbven; + uint32_t pad06; + uint32_t rgbs; + uint32_t pad07[11]; + + uint32_t rgbcmy; + uint32_t rgbcmcb; + uint32_t rgbcmcr; + uint32_t rgbcmb; + uint32_t pad08[12 + 1984]; +}; + +/* mb86r0x gdc draw */ +struct mb86r0x_gdc_draw { + uint32_t ys; + uint32_t xs; + uint32_t dxdy; + uint32_t xus; + uint32_t dxudy; + uint32_t xls; + uint32_t dxldy; + uint32_t usn; + uint32_t lsn; + uint32_t pad01[7]; + uint32_t rs; + uint32_t drdx; + uint32_t drdy; + uint32_t gs; + uint32_t dgdx; + uint32_t dgdy; + uint32_t bs; + uint32_t dbdx; + uint32_t dbdy; + uint32_t pad02[7]; + uint32_t zs; + uint32_t dzdx; + uint32_t dzdy; + uint32_t pad03[13]; + uint32_t ss; + uint32_t dsdx; + uint32_t dsdy; + uint32_t ts; + uint32_t dtdx; + uint32_t dtdy; + uint32_t qs; + uint32_t dqdx; + uint32_t dqdy; + uint32_t pad04[23]; + uint32_t lpn; + uint32_t lxs; + uint32_t lxde; + uint32_t lys; + uint32_t lyde; + uint32_t lzs; + uint32_t lzde; + uint32_t pad05[13]; + uint32_t pxdc; + uint32_t pydc; + uint32_t pzdc; + uint32_t pad06[25]; + uint32_t rxs; + uint32_t rys; + uint32_t rsizex; + uint32_t rsizey; + uint32_t pad07[12]; + uint32_t saddr; + uint32_t sstride; + uint32_t srx; + uint32_t sry; + uint32_t daddr; + uint32_t dstride; + uint32_t drx; + uint32_t dry; + uint32_t brsizex; + uint32_t brsizey; + uint32_t tcolor; + uint32_t pad08[93]; + uint32_t blpo; + uint32_t pad09[7]; + uint32_t ctr; + uint32_t ifsr; + uint32_t ifcnt; + uint32_t sst; + uint32_t ds; + uint32_t pst; + uint32_t est; + uint32_t pad10; + uint32_t mdr0; + uint32_t mdr1; + uint32_t mdr2; + uint32_t mdr3; + uint32_t mdr4; + uint32_t pad14[2]; + uint32_t mdr7; + uint32_t fbr; + uint32_t xres; + uint32_t zbr; + uint32_t tbr; + uint32_t pfbr; + uint32_t cxmin; + uint32_t cxmax; + uint32_t cymin; + uint32_t cymax; + uint32_t txs; + uint32_t tis; + uint32_t toa; + uint32_t sho; + uint32_t abr; + uint32_t pad15[2]; + uint32_t fc; + uint32_t bc; + uint32_t alf; + uint32_t blp; + uint32_t pad16; + uint32_t tbc; + uint32_t pad11[42]; + uint32_t lx0dc; + uint32_t ly0dc; + uint32_t lx1dc; + uint32_t ly1dc; + uint32_t pad12[12]; + uint32_t x0dc; + uint32_t y0dc; + uint32_t x1dc; + uint32_t y1dc; + uint32_t x2dc; + uint32_t y2dc; + uint32_t pad13[666]; +}; + +/* mb86r0x gdc geometry engine */ +struct mb86r0x_gdc_geom { + uint32_t gctr; + uint32_t pad00[15]; + uint32_t gmdr0; + uint32_t gmdr1; + uint32_t gmdr2; + uint32_t pad01[237]; + uint32_t dfifog; + uint32_t pad02[767]; +}; + +/* mb86r0x gdc */ +struct mb86r0x_gdc { + uint32_t pad00[2]; + uint32_t lts; + uint32_t pad01; + uint32_t lsta; + uint32_t pad02[3]; + uint32_t ist; + uint32_t imask; + uint32_t pad03[6]; + uint32_t lsa; + uint32_t lco; + uint32_t lreq; + + uint32_t pad04[16*1024 - 19]; + struct mb86r0x_gdc_dsp dsp0; + struct mb86r0x_gdc_dsp dsp1; + uint32_t pad05[4*1024 - 2]; + uint32_t vccc; + uint32_t vcsr; + struct mb86r0x_gdc_cap cap0; + struct mb86r0x_gdc_cap cap1; + uint32_t pad06[4*1024]; + uint32_t texture_base[16*1024]; + struct mb86r0x_gdc_draw draw; + uint32_t pad07[7*1024]; + struct mb86r0x_gdc_geom geom; + uint32_t pad08[7*1024]; +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Physical Address Defines + */ +#define MB86R0x_DDR2_BASE 0xf3000000 +#define MB86R0x_GDC_BASE 0xf1fc0000 +#define MB86R0x_CCNT_BASE 0xfff42000 +#define MB86R0x_CAN0_BASE 0xfff54000 +#define MB86R0x_CAN1_BASE 0xfff55000 +#define MB86R0x_I2C0_BASE 0xfff56000 +#define MB86R0x_I2C1_BASE 0xfff57000 +#define MB86R0x_EHCI_BASE 0xfff80000 +#define MB86R0x_OHCI_BASE 0xfff81000 +#define MB86R0x_IRC1_BASE 0xfffb0000 +#define MB86R0x_MEMC_BASE 0xfffc0000 +#define MB86R0x_TIMER_BASE 0xfffe0000 +#define MB86R0x_UART0_BASE 0xfffe1000 +#define MB86R0x_UART1_BASE 0xfffe2000 +#define MB86R0x_IRCE_BASE 0xfffe4000 +#define MB86R0x_CRG_BASE 0xfffe7000 +#define MB86R0x_IRC0_BASE 0xfffe8000 +#define MB86R0x_GPIO_BASE 0xfffe9000 +#define MB86R0x_PWM0_BASE 0xfff41000 +#define MB86R0x_PWM1_BASE 0xfff41100 + +#define MB86R0x_CRSR_SWRSTREQ (1 << 1) + +/* + * Timer register bits + */ +#define MB86R0x_TIMER_ENABLE (1 << 7) +#define MB86R0x_TIMER_MODE_MSK (1 << 6) +#define MB86R0x_TIMER_MODE_FR (0 << 6) +#define MB86R0x_TIMER_MODE_PD (1 << 6) + +#define MB86R0x_TIMER_INT_EN (1 << 5) +#define MB86R0x_TIMER_PRS_MSK (3 << 2) +#define MB86R0x_TIMER_PRS_4S (1 << 2) +#define MB86R0x_TIMER_PRS_8S (1 << 3) +#define MB86R0x_TIMER_SIZE_32 (1 << 1) +#define MB86R0x_TIMER_ONE_SHT (1 << 0) + +/* + * Clock reset generator bits + */ +#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) +#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) +/* + * DDR2 controller bits + */ +#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) +#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) +#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) +#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ + MB86R0x_DDR2_DRCI_CKEN | \ + MB86R0x_DDR2_DRCI_DRCMD) +#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ + MB86R0x_DDR2_DRCI_CKEN) +#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN +#endif /* MB86R0X_H */ diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h index 71a0cb6ae49..40f80baf61c 100644 --- a/arch/arm/include/asm/arch-omap3/clocks.h +++ b/arch/arm/include/asm/arch-omap3/clocks.h @@ -51,12 +51,29 @@ typedef struct { unsigned int m2; } dpll_param; +struct dpll_per_36x_param { + unsigned int sys_clk; + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m2div; +}; + /* Following functions are exported from lowlevel_init.S */ extern dpll_param *get_mpu_dpll_param(void); extern dpll_param *get_iva_dpll_param(void); extern dpll_param *get_core_dpll_param(void); extern dpll_param *get_per_dpll_param(void); +extern dpll_param *get_36x_mpu_dpll_param(void); +extern dpll_param *get_36x_iva_dpll_param(void); +extern dpll_param *get_36x_core_dpll_param(void); +extern dpll_param *get_36x_per_dpll_param(void); + extern void *_end_vect, *_start; #endif diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index 661407b564e..30ef690fa2a 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -282,4 +282,31 @@ #define PER_FSEL_38P4 0x07 #define PER_M2_38P4 0x09 +/* 36XX PER DPLL */ + +#define PER_36XX_M_12 0x1B0 +#define PER_36XX_N_12 0x05 +#define PER_36XX_FSEL_12 0x07 +#define PER_36XX_M2_12 0x09 + +#define PER_36XX_M_13 0x360 +#define PER_36XX_N_13 0x0C +#define PER_36XX_FSEL_13 0x03 +#define PER_36XX_M2_13 0x09 + +#define PER_36XX_M_19P2 0x1C2 +#define PER_36XX_N_19P2 0x09 +#define PER_36XX_FSEL_19P2 0x07 +#define PER_36XX_M2_19P2 0x09 + +#define PER_36XX_M_26 0x1B0 +#define PER_36XX_N_26 0x0C +#define PER_36XX_FSEL_26 0x07 +#define PER_36XX_M2_26 0x09 + +#define PER_36XX_M_38P4 0x1C2 +#define PER_36XX_N_38P4 0x13 +#define PER_36XX_FSEL_38P4 0x07 +#define PER_36XX_M2_38P4 0x09 + #endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 390b0079451..962d6d40aa8 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -60,19 +60,14 @@ struct ctrl { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ -/* cpu type */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct ctrl_id { u8 res1[0x4]; u32 idcode; /* 0x04 */ u32 prod_id; /* 0x08 */ - u8 res2[0x0C]; + u32 sku_id; /* 0x0c */ + u8 res2[0x08]; u32 die_id_0; /* 0x18 */ u32 die_id_1; /* 0x1C */ u32 die_id_2; /* 0x20 */ @@ -89,6 +84,11 @@ struct ctrl_id { #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 +/* device speed */ +#define SKUID_CLK_MASK 0xf +#define SKUID_CLK_600MHZ 0x0 +#define SKUID_CLK_720MHZ 0x8 + #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) @@ -419,6 +419,7 @@ struct prm { }; #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL 0x48307250 +#define PRM_RSTCTRL_RESET 0x04 #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 12815f694f4..3957c796f22 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -176,11 +176,41 @@ struct gpio { #define CPU_3XX_ES21 2 #define CPU_3XX_ES30 3 #define CPU_3XX_ES31 4 -#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) +#define CPU_3XX_ES312 7 +#define CPU_3XX_MAX_REV 8 #define CPU_3XX_ID_SHIFT 28 #define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ +/* + * Hawkeye values + */ +#define HAWKEYE_OMAP34XX 0xb7ae +#define HAWKEYE_AM35XX 0xb868 +#define HAWKEYE_OMAP36XX 0xb891 + +#define HAWKEYE_SHIFT 12 + +/* + * Define CPU families + */ +#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ +#define CPU_AM35XX 0x3500 /* AM35xx devices */ +#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ + +/* + * Control status register values corresponding to cpu variants + */ +#define OMAP3503 0x5c00 +#define OMAP3515 0x1c00 +#define OMAP3525 0x4c00 +#define OMAP3530 0x0c00 + +#define AM3505 0x5c00 +#define AM3517 0x1c00 + +#define OMAP3730 0x0c00 + #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index db7b42aed10..4a28ba1c4ae 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -41,7 +41,9 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, void watchdog_init(void); void set_muxconf_regs(void); +u32 get_cpu_family(void); u32 get_cpu_rev(void); +u32 get_sku_id(void); u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 79ff22cf316..d0c808d1217 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -88,6 +88,7 @@ #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) #define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ad0c640dfd8..4813e9e21d9 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -33,6 +33,9 @@ void watchdog_init(void); u32 get_device_type(void); void invalidate_dcache(u32); void set_muxconf_regs(void); +void sr32(void *, u32, u32, u32); +u32 wait_on_value(u32, u32, void *, u32); +void sdelay(unsigned long); extern const struct omap_sysinfo sysinfo; diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 80717f8a579..6ce02a92125 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -76,7 +76,7 @@ enum orion5x_cpu_attrib { /* * Device Address MAP BAR values -/* + * * All addresses and sizes not defined by board code * will be given default values here. */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h index 3e59abe78c6..3488eb7c157 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ b/arch/arm/include/asm/arch-s5pc1xx/clk.h @@ -29,10 +29,11 @@ #define HPLL 3 #define VPLL 4 -void s5pc1xx_clock_init(void); +void s5p_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); extern unsigned long (*get_arm_clk)(void); -extern unsigned long (*get_pclk)(void); +extern unsigned long (*get_pwm_clk)(void); +extern unsigned long (*get_uart_clk)(int dev_index); #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index b3af8cc782a..e74959fe222 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -25,9 +25,9 @@ #define S5PC1XX_ADDR_BASE 0xE0000000 -#define S5PC1XX_CLOCK_BASE 0xE0100000 - /* S5PC100 */ +#define S5PC100_PRO_ID 0xE0000000 +#define S5PC100_CLOCK_BASE 0xE0100000 #define S5PC100_GPIO_BASE 0xE0300000 #define S5PC100_VIC0_BASE 0xE4000000 #define S5PC100_VIC1_BASE 0xE4100000 @@ -41,6 +41,8 @@ #define S5PC100_MMC_BASE 0xED800000 /* S5PC110 */ +#define S5PC110_PRO_ID 0xE0000000 +#define S5PC110_CLOCK_BASE 0xE0100000 #define S5PC110_GPIO_BASE 0xE0200000 #define S5PC110_PWMTIMER_BASE 0xE2500000 #define S5PC110_WATCHDOG_BASE 0xE2700000 @@ -54,21 +56,44 @@ #define S5PC110_VIC2_BASE 0xF2200000 #define S5PC110_VIC3_BASE 0xF2300000 -/* Chip ID */ -#define S5PC1XX_PRO_ID 0xE0000000 - #ifndef __ASSEMBLY__ +#include <asm/io.h> /* CPU detection macros */ -extern unsigned int s5pc1xx_cpu_id; +extern unsigned int s5p_cpu_id; + +static inline void s5p_set_cpu_id(void) +{ + s5p_cpu_id = readl(S5PC100_PRO_ID); + s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); +} #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ - return s5pc1xx_cpu_id == id ? 1 : 0; \ + return s5p_cpu_id == id ? 1 : 0; \ } IS_SAMSUNG_TYPE(s5pc100, 0xc100) IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +#define SAMSUNG_BASE(device, base) \ +static inline unsigned int samsung_get_base_##device(void) \ +{ \ + if (cpu_is_s5pc100()) \ + return S5PC100_##base; \ + else if (cpu_is_s5pc110()) \ + return S5PC110_##base; \ + else \ + return 0; \ +} + +SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(gpio, GPIO_BASE) +SAMSUNG_BASE(pro_id, PRO_ID) +SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(sromc, SROMC_BASE) +SAMSUNG_BASE(timer, PWMTIMER_BASE) +SAMSUNG_BASE(uart, UART_BASE) #endif #endif /* _S5PC1XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 9a7faed319e..2df33a607c0 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -33,96 +33,96 @@ struct s5p_gpio_bank { }; struct s5pc100_gpio { - struct s5p_gpio_bank gpio_a0; - struct s5p_gpio_bank gpio_a1; - struct s5p_gpio_bank gpio_b; - struct s5p_gpio_bank gpio_c; - struct s5p_gpio_bank gpio_d; - struct s5p_gpio_bank gpio_e0; - struct s5p_gpio_bank gpio_e1; - struct s5p_gpio_bank gpio_f0; - struct s5p_gpio_bank gpio_f1; - struct s5p_gpio_bank gpio_f2; - struct s5p_gpio_bank gpio_f3; - struct s5p_gpio_bank gpio_g0; - struct s5p_gpio_bank gpio_g1; - struct s5p_gpio_bank gpio_g2; - struct s5p_gpio_bank gpio_g3; - struct s5p_gpio_bank gpio_i; - struct s5p_gpio_bank gpio_j0; - struct s5p_gpio_bank gpio_j1; - struct s5p_gpio_bank gpio_j2; - struct s5p_gpio_bank gpio_j3; - struct s5p_gpio_bank gpio_j4; - struct s5p_gpio_bank gpio_k0; - struct s5p_gpio_bank gpio_k1; - struct s5p_gpio_bank gpio_k2; - struct s5p_gpio_bank gpio_k3; - struct s5p_gpio_bank gpio_l0; - struct s5p_gpio_bank gpio_l1; - struct s5p_gpio_bank gpio_l2; - struct s5p_gpio_bank gpio_l3; - struct s5p_gpio_bank gpio_l4; - struct s5p_gpio_bank gpio_h0; - struct s5p_gpio_bank gpio_h1; - struct s5p_gpio_bank gpio_h2; - struct s5p_gpio_bank gpio_h3; + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c; + struct s5p_gpio_bank d; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank l3; + struct s5p_gpio_bank l4; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; }; struct s5pc110_gpio { - struct s5p_gpio_bank gpio_a0; - struct s5p_gpio_bank gpio_a1; - struct s5p_gpio_bank gpio_b; - struct s5p_gpio_bank gpio_c0; - struct s5p_gpio_bank gpio_c1; - struct s5p_gpio_bank gpio_d0; - struct s5p_gpio_bank gpio_d1; - struct s5p_gpio_bank gpio_e0; - struct s5p_gpio_bank gpio_e1; - struct s5p_gpio_bank gpio_f0; - struct s5p_gpio_bank gpio_f1; - struct s5p_gpio_bank gpio_f2; - struct s5p_gpio_bank gpio_f3; - struct s5p_gpio_bank gpio_g0; - struct s5p_gpio_bank gpio_g1; - struct s5p_gpio_bank gpio_g2; - struct s5p_gpio_bank gpio_g3; - struct s5p_gpio_bank gpio_i; - struct s5p_gpio_bank gpio_j0; - struct s5p_gpio_bank gpio_j1; - struct s5p_gpio_bank gpio_j2; - struct s5p_gpio_bank gpio_j3; - struct s5p_gpio_bank gpio_j4; - struct s5p_gpio_bank gpio_mp0_1; - struct s5p_gpio_bank gpio_mp0_2; - struct s5p_gpio_bank gpio_mp0_3; - struct s5p_gpio_bank gpio_mp0_4; - struct s5p_gpio_bank gpio_mp0_5; - struct s5p_gpio_bank gpio_mp0_6; - struct s5p_gpio_bank gpio_mp0_7; - struct s5p_gpio_bank gpio_mp1_0; - struct s5p_gpio_bank gpio_mp1_1; - struct s5p_gpio_bank gpio_mp1_2; - struct s5p_gpio_bank gpio_mp1_3; - struct s5p_gpio_bank gpio_mp1_4; - struct s5p_gpio_bank gpio_mp1_5; - struct s5p_gpio_bank gpio_mp1_6; - struct s5p_gpio_bank gpio_mp1_7; - struct s5p_gpio_bank gpio_mp1_8; - struct s5p_gpio_bank gpio_mp2_0; - struct s5p_gpio_bank gpio_mp2_1; - struct s5p_gpio_bank gpio_mp2_2; - struct s5p_gpio_bank gpio_mp2_3; - struct s5p_gpio_bank gpio_mp2_4; - struct s5p_gpio_bank gpio_mp2_5; - struct s5p_gpio_bank gpio_mp2_6; - struct s5p_gpio_bank gpio_mp2_7; - struct s5p_gpio_bank gpio_mp2_8; + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank mp0_1; + struct s5p_gpio_bank mp0_2; + struct s5p_gpio_bank mp0_3; + struct s5p_gpio_bank mp0_4; + struct s5p_gpio_bank mp0_5; + struct s5p_gpio_bank mp0_6; + struct s5p_gpio_bank mp0_7; + struct s5p_gpio_bank mp1_0; + struct s5p_gpio_bank mp1_1; + struct s5p_gpio_bank mp1_2; + struct s5p_gpio_bank mp1_3; + struct s5p_gpio_bank mp1_4; + struct s5p_gpio_bank mp1_5; + struct s5p_gpio_bank mp1_6; + struct s5p_gpio_bank mp1_7; + struct s5p_gpio_bank mp1_8; + struct s5p_gpio_bank mp2_0; + struct s5p_gpio_bank mp2_1; + struct s5p_gpio_bank mp2_2; + struct s5p_gpio_bank mp2_3; + struct s5p_gpio_bank mp2_4; + struct s5p_gpio_bank mp2_5; + struct s5p_gpio_bank mp2_6; + struct s5p_gpio_bank mp2_7; + struct s5p_gpio_bank mp2_8; struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank gpio_h0; - struct s5p_gpio_bank gpio_h1; - struct s5p_gpio_bank gpio_h2; - struct s5p_gpio_bank gpio_h3; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; }; /* functions */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index ac560c27046..68c59d13e34 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -56,7 +56,7 @@ struct s5p_mmc { unsigned int control4; unsigned char res4[0x6e]; unsigned short hcver; - unsigned char res5[0xFFF00]; + unsigned char res5[0xFFF02]; }; struct mmc_host { diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h index e02a8d8fb3a..0369968d4a9 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/include/asm/arch-s5pc1xx/pwm.h @@ -22,19 +22,15 @@ #ifndef __ASM_ARM_ARCH_PWM_H_ #define __ASM_ARM_ARCH_PWM_H_ -/* PWM timer addressing */ -#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE -#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE - /* Interval mode(Auto Reload) of PWM Timer 4 */ -#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) +#define TCON4_AUTO_RELOAD (1 << 22) /* Update TCNTB4 */ -#define S5PC1XX_TCON4_UPDATE (1 << 21) +#define TCON4_UPDATE (1 << 21) /* start bit of PWM Timer 4 */ -#define S5PC1XX_TCON4_START (1 << 20) +#define TCON4_START (1 << 20) #ifndef __ASSEMBLY__ -struct s5pc1xx_timer { +struct s5p_timer { unsigned int tcfg0; unsigned int tcfg1; unsigned int tcon; diff --git a/arch/avr32/cpu/at32ap700x/Makefile b/arch/avr32/cpu/at32ap700x/Makefile index 46e6ef661a4..30ea92590dc 100644 --- a/arch/avr32/cpu/at32ap700x/Makefile +++ b/arch/avr32/cpu/at32ap700x/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).a -COBJS := portmux.o clk.o +COBJS := portmux.o clk.o mmu.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/avr32/cpu/at32ap700x/mmu.c b/arch/avr32/cpu/at32ap700x/mmu.c new file mode 100644 index 00000000000..c3a1b93679d --- /dev/null +++ b/arch/avr32/cpu/at32ap700x/mmu.c @@ -0,0 +1,78 @@ +#include <common.h> +#include <asm/arch/mmu.h> +#include <asm/sysreg.h> + +void mmu_init_r(unsigned long dest_addr) +{ + uintptr_t vmr_table_addr; + + /* Round monitor address down to the nearest page boundary */ + dest_addr &= PAGE_ADDR_MASK; + + /* Initialize TLB entry 0 to cover the monitor, and lock it */ + sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V)); + sysreg_write(TLBELO, dest_addr | MMU_VMR_CACHE_WRBACK); + sysreg_write(MMUCR, SYSREG_BF(DRP, 0) | SYSREG_BF(DLA, 1) + | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M)); + __builtin_tlbw(); + + /* + * Calculate the address of the VM range table in a PC-relative + * manner to make sure we hit the SDRAM and not the flash. + */ + vmr_table_addr = (uintptr_t)&mmu_vmr_table; + sysreg_write(PTBR, vmr_table_addr); + printf("VMR table @ 0x%08x\n", vmr_table_addr); + + /* Enable paging */ + sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1) + | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E)); +} + +int mmu_handle_tlb_miss(void) +{ + const struct mmu_vm_range *vmr_table; + const struct mmu_vm_range *vmr; + unsigned int fault_pgno; + int first, last; + + fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT; + vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR); + + /* Do a binary search through the VM ranges */ + first = 0; + last = CONFIG_SYS_NR_VM_REGIONS; + while (first < last) { + unsigned int start; + int middle; + + /* Pick the entry in the middle of the remaining range */ + middle = (first + last) >> 1; + vmr = &vmr_table[middle]; + start = vmr->virt_pgno; + + /* Do the bisection thing */ + if (fault_pgno < start) { + last = middle; + } else if (fault_pgno >= (start + vmr->nr_pages)) { + first = middle + 1; + } else { + /* Got it; let's slam it into the TLB */ + uint32_t tlbelo; + + tlbelo = vmr->phys & ~PAGE_ADDR_MASK; + tlbelo |= fault_pgno << PAGE_SHIFT; + sysreg_write(TLBELO, tlbelo); + __builtin_tlbw(); + + /* Zero means success */ + return 0; + } + } + + /* + * Didn't find any matching entries. Return a nonzero value to + * indicate that this should be treated as a fatal exception. + */ + return -1; +} diff --git a/arch/avr32/cpu/exception.c b/arch/avr32/cpu/exception.c index dc9c3002a49..b21ef1f928d 100644 --- a/arch/avr32/cpu/exception.c +++ b/arch/avr32/cpu/exception.c @@ -59,7 +59,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) { unsigned int mode; - printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc); + printf("\n *** Unhandled exception %u at PC=0x%08lx [%08lx]\n", + ecr, regs->pc, regs->pc - gd->reloc_off); switch (ecr) { case ECR_BUS_ERROR_WRITE: diff --git a/arch/avr32/cpu/start.S b/arch/avr32/cpu/start.S index 99c9e06cb83..06bf4c692d8 100644 --- a/arch/avr32/cpu/start.S +++ b/arch/avr32/cpu/start.S @@ -82,12 +82,19 @@ _evba: .org 0x44 rjmp unknown_exception /* DTLB Modified */ - .org 0x50 - rjmp unknown_exception /* ITLB Miss */ - .org 0x60 - rjmp unknown_exception /* DTLB Miss (read) */ - .org 0x70 - rjmp unknown_exception /* DTLB Miss (write) */ + .org 0x50 /* ITLB Miss */ + pushm r8-r12,lr + rjmp 1f + .org 0x60 /* DTLB Miss (read) */ + pushm r8-r12,lr + rjmp 1f + .org 0x70 /* DTLB Miss (write) */ + pushm r8-r12,lr +1: mov r12, sp + rcall mmu_handle_tlb_miss + popm r8-r12,lr + brne unknown_exception + rete .size _evba, . - _evba diff --git a/arch/avr32/include/asm/arch-at32ap700x/addrspace.h b/arch/avr32/include/asm/arch-at32ap700x/addrspace.h index 409eee35363..4edc1bd7017 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/addrspace.h +++ b/arch/avr32/include/asm/arch-at32ap700x/addrspace.h @@ -75,10 +75,7 @@ static inline void * phys_to_virt(unsigned long address) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - if (flags == MAP_WRBACK) - return (void *)P1SEGADDR(paddr); - else - return (void *)P2SEGADDR(paddr); + return (void *)paddr; } #endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/mmu.h b/arch/avr32/include/asm/arch-at32ap700x/mmu.h new file mode 100644 index 00000000000..fcd9a056092 --- /dev/null +++ b/arch/avr32/include/asm/arch-at32ap700x/mmu.h @@ -0,0 +1,66 @@ +/* + * In order to deal with the hardcoded u-boot requirement that virtual + * addresses are always mapped 1:1 with physical addresses, we implement + * a small virtual memory manager so that we can use the MMU hardware in + * order to get the caching properties right. + * + * A few pages (or possibly just one) are locked in the TLB permanently + * in order to avoid recursive TLB misses, but most pages are faulted in + * on demand. + */ +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +#include <asm/sysreg.h> + +#define PAGE_SHIFT 20 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1)) + +#define MMU_VMR_CACHE_NONE \ + (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D)) +#define MMU_VMR_CACHE_WBUF \ + (MMU_VMR_CACHE_NONE | SYSREG_BIT(B)) +#define MMU_VMR_CACHE_WRTHRU \ + (MMU_VMR_CACHE_NONE | SYSREG_BIT(TLBELO_C) | SYSREG_BIT(W)) +#define MMU_VMR_CACHE_WRBACK \ + (MMU_VMR_CACHE_WBUF | SYSREG_BIT(TLBELO_C)) + +/* + * This structure is used in our "page table". Instead of the usual + * x86-inspired radix tree, we let each entry cover an arbitrary-sized + * virtual address range and store them in a binary search tree. This is + * somewhat slower, but should use significantly less RAM, and we + * shouldn't get many TLB misses when using 1 MB pages anyway. + * + * With 1 MB pages, we need 12 bits to store the page number. In + * addition, we stick an Invalid bit in the high bit of virt_pgno (if + * set, it cannot possibly match any faulting page), and all the bits + * that need to be written to TLBELO in phys_pgno. + */ +struct mmu_vm_range { + uint16_t virt_pgno; + uint16_t nr_pages; + uint32_t phys; +}; + +/* + * An array of mmu_vm_range objects describing all pageable addresses. + * The array is sorted by virt_pgno so that the TLB miss exception + * handler can do a binary search to find the correct entry. + */ +extern struct mmu_vm_range mmu_vmr_table[]; + +/* + * Initialize the MMU. This will set up a fixed TLB entry for the static + * u-boot image at dest_addr and enable paging. + */ +void mmu_init_r(unsigned long dest_addr); + +/* + * Handle a TLB miss exception. This function is called directly from + * the exception vector table written in assembly. + */ +int mmu_handle_tlb_miss(void); + +#endif /* __ASM_ARCH_MMU_H */ diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 9e741d22e2c..aa589bb4b00 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -33,6 +33,7 @@ #include <asm/initcalls.h> #include <asm/sections.h> +#include <asm/arch/mmu.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -265,6 +266,9 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) gd->flags |= GD_FLG_RELOC; gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; + /* Enable the MMU so that we can keep u-boot simple */ + mmu_init_r(dest_addr); + board_early_init_r(); monitor_flash_len = _edata - _text; diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 004d8daa900..49bc03e3ec1 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -26,11 +26,26 @@ #include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> #include <asm/arch/portmux.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + static const struct sdram_config sdram_config = { .data_bits = SDRAM_DATA_16BIT, .row_bits = 13, @@ -75,13 +90,11 @@ phys_size_t initdram(int board_type) unsigned long actual_size; void *sdram_base; - sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + sdram_base = uncached(EBI_SDRAM_BASE); expected_size = sdram_init(sdram_base, &sdram_config); actual_size = get_ram_size(sdram_base, expected_size); - unmap_physmem(sdram_base, EBI_SDRAM_SIZE); - if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index c36cb5717be..8b1e1b57d78 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -25,11 +25,26 @@ #include <asm/sdram.h> #include <asm/arch/clk.h> #include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> #include <asm/arch/portmux.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + static const struct sdram_config sdram_config = { #if defined(CONFIG_ATSTK1006) /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */ @@ -97,13 +112,11 @@ phys_size_t initdram(int board_type) unsigned long actual_size; void *sdram_base; - sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + sdram_base = uncached(EBI_SDRAM_BASE); expected_size = sdram_init(sdram_base, &sdram_config); actual_size = get_ram_size(sdram_base, expected_size); - unmap_physmem(sdram_base, EBI_SDRAM_SIZE); - if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index 8af680fe914..b0eca939b7f 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -24,10 +24,25 @@ #include <asm/sdram.h> #include <asm/arch/clk.h> #include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> #include <asm/arch/portmux.h> DECLARE_GLOBAL_DATA_PTR; +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + static const struct sdram_config sdram_config = { /* MT48LC4M32B2P-6 (16 MB) */ .data_bits = SDRAM_DATA_32BIT, @@ -68,13 +83,11 @@ phys_size_t initdram(int board_type) unsigned long actual_size; void *sdram_base; - sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + sdram_base = uncached(EBI_SDRAM_BASE); expected_size = sdram_init(sdram_base, &sdram_config); actual_size = get_ram_size(sdram_base, expected_size); - unmap_physmem(sdram_base, EBI_SDRAM_SIZE); - if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 694bd743588..41fa3e1567a 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009 + * (C) Copyright 2009-2010 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -28,13 +28,13 @@ #include <common.h> #include <asm/arch/at91sam9263.h> -#include <asm/arch/at91sam9_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <netdev.h> @@ -52,10 +52,10 @@ int get_hw_rev(void) if (hw_rev >= 0) return hw_rev; - hw_rev = at91_get_gpio_value(AT91_PIN_PB19); - hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; if (hw_rev == 15) hw_rev = 0; @@ -67,44 +67,44 @@ int get_hw_rev(void) static void meesc_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | -#endif - AT91_SMC_TDF_(2)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -117,26 +117,27 @@ static void meesc_macb_hw_init(void) */ static void meesc_ethercat_hw_init(void) { + at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + /* Configure SMC EBI1_CS0 for EtherCAT */ - at91_sys_write(AT91_SMC1_SETUP(0), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC1_PULSE(0), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9)); - at91_sys_write(AT91_SMC1_CYCLE(0), - AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5)); + writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), + &smc1->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | + AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), + &smc1->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), + &smc1->cs[0].cycle); /* * Configure behavior at external wait signal, byte-select mode, 16 bit * data bus width, none data float wait states and TDF optimization */ - at91_sys_write(AT91_SMC1_MODE(0), - AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | - AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | - AT91_SMC_TDFMODE); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | + AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | + AT91_SMC_MODE_TDF, &smc1->cs[0].mode); /* Configure RDY/BSY */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ + at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ } int dram_init(void) @@ -150,7 +151,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); #endif return rc; } @@ -175,7 +176,7 @@ int checkboard(void) gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; puts("Board: EtherCAN/2 Gateway"); /* switch on LED1D */ - at91_set_gpio_output(AT91_PIN_PB12, 1); + at91_set_pio_output(AT91_PIO_PORTB, 12, 1); break; default: /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ @@ -222,8 +223,9 @@ u32 get_board_rev(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - char *str; - char buf[32]; + char *str; + char buf[32]; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* * Normally the processor clock has a divisor of 2. @@ -231,10 +233,9 @@ int misc_init_r(void) * Check the user has set environment mdiv to 4 to change the divisor. */ if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { - at91_sys_write(AT91_PMC_MCKR, - (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) | - AT91SAM9_PMC_MDIV_4); - at91_clock_init(0); + writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | + AT91SAM9_PMC_MDIV_4, &pmc->mckr); + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); serial_setbrg(); /* Notify the user that the clock is not default */ printf("Setting master clock to %s MHz\n", @@ -247,10 +248,14 @@ int misc_init_r(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Peripheral Clock Enable Register */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE); + writel(1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE | + 1 << AT91SAM9263_ID_UHP, + &pmc->pcer); /* initialize ET1100 Controller */ meesc_ethercat_hw_init(); @@ -271,5 +276,8 @@ int board_init(void) #ifdef CONFIG_AT91_CAN at91_can_hw_init(); #endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif return 0; } diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index 0017962d420..cd4d42c6b79 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Eukrea Electromatique <www.eukrea.com> + * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com> * Eric Benard <eric@eukrea.com> * based on at91rm9200dk.c which is : * (C) Copyright 2002 @@ -27,13 +27,11 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/io.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <ks8721.h> -#endif +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_pmc.h> DECLARE_GLOBAL_DATA_PTR; @@ -61,31 +59,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_DRIVER_ETHER) -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = ks8721_initphy; - p_phyops->IsPhyConnected = ks8721_isphyconnected; - p_phyops->GetLinkSpeed = ks8721_getlinkspeed; - p_phyops->AutoNegotiate = ks8721_autonegotiate; -} - -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ #ifdef CONFIG_DRIVER_AT91EMAC - int board_eth_init(bd_t *bis) { int rc = 0; @@ -93,3 +67,20 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +#ifdef CONFIG_SOFT_I2C +void i2c_init_board(void) +{ + u32 pin; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + writel(1 << AT91_ID_PIOA, &pmc->pcer); + pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); +} +#endif diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index cc0f1371218..470adba7948 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -27,12 +27,32 @@ #include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> #include <asm/arch/portmux.h> #include <atmel_lcdc.h> #include <lcd.h> #include "../../../arch/avr32/cpu/hsmc3.h" +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT, + .phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + #if defined(CONFIG_LCD) /* 480x272x16 @ 72 Hz */ vidinfo_t panel_info = { @@ -153,13 +173,11 @@ phys_size_t initdram(int board_type) unsigned long actual_size; void *sdram_base; - sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + sdram_base = uncached(EBI_SDRAM_BASE); expected_size = sdram_init(sdram_base, &sdram_config); actual_size = get_ram_size(sdram_base, expected_size); - unmap_physmem(sdram_base, EBI_SDRAM_SIZE); - if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index 8b3e22cd9ec..78f4fd405ea 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -30,10 +30,25 @@ #include <asm/arch/clk.h> #include <asm/arch/hmatrix.h> #include <asm/arch/memory-map.h> +#include <asm/arch/mmu.h> #include <asm/arch/portmux.h> DECLARE_GLOBAL_DATA_PTR; +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + static const struct sdram_config sdram_config = { .data_bits = SDRAM_DATA_32BIT, .row_bits = 13, @@ -80,13 +95,11 @@ phys_size_t initdram(int board_type) unsigned long actual_size; void *sdram_base; - sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + sdram_base = uncached(EBI_SDRAM_BASE); expected_size = sdram_init(sdram_base, &sdram_config); actual_size = get_ram_size(sdram_base, expected_size); - unmap_physmem(sdram_base, EBI_SDRAM_SIZE); - if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); diff --git a/board/overo/overo.c b/board/overo/overo.c index e85be7d5e6c..1b67f1f5024 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -43,6 +43,17 @@ static void setup_net_chip(void); #endif +/* GPMC definitions for LAN9221 chips on Tobi expansion boards */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + /* * Routine: board_init * Description: Early hardware init. @@ -61,6 +72,70 @@ int board_init(void) } /* + * Routine: get_board_revision + * Description: Returns the board revision + */ +int get_board_revision(void) +{ + int revision; + + if (!omap_request_gpio(112) && + !omap_request_gpio(113) && + !omap_request_gpio(115)) { + + omap_set_gpio_direction(112, 1); + omap_set_gpio_direction(113, 1); + omap_set_gpio_direction(115, 1); + + revision = omap_get_gpio_datain(115) << 2 | + omap_get_gpio_datain(113) << 1 | + omap_get_gpio_datain(112); + + omap_free_gpio(112); + omap_free_gpio(113); + omap_free_gpio(115); + } else { + printf("Error: unable to acquire board revision GPIOs\n"); + revision = -1; + } + + return revision; +} + +/* + * Routine: get_sdio2_config + * Description: Return information about the wifi module connection + * Returns 0 if the module connects though a level translator + * Returns 1 if the module connects directly + */ +int get_sdio2_config(void) +{ + int sdio_direct; + + if (!omap_request_gpio(130) && !omap_request_gpio(139)) { + + omap_set_gpio_direction(130, 0); + omap_set_gpio_direction(139, 1); + + sdio_direct = 1; + omap_set_gpio_dataout(130, 0); + if (omap_get_gpio_datain(139) == 0) { + omap_set_gpio_dataout(130, 1); + if (omap_get_gpio_datain(139) == 1) + sdio_direct = 0; + } + + omap_free_gpio(130); + omap_free_gpio(139); + } else { + printf("Error: unable to acquire sdio2 clk GPIOs\n"); + sdio_direct = -1; + } + + return sdio_direct; +} + +/* * Routine: misc_init_r * Description: Configure board specific parts */ @@ -73,6 +148,21 @@ int misc_init_r(void) setup_net_chip(); #endif + printf("Board revision: %d\n", get_board_revision()); + + switch (get_sdio2_config()) { + case 0: + printf("Tranceiver detected on mmc2\n"); + MUX_OVERO_SDIO2_TRANSCEIVER(); + break; + case 1: + printf("Direct connection on mmc2\n"); + MUX_OVERO_SDIO2_DIRECT(); + break; + default: + printf("Unable to detect mmc2 connection type\n"); + } + dieid_num_r(); return 0; @@ -99,14 +189,13 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - /* Configure GPMC registers */ - writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); - writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); - writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); - writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); - writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); - writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); - writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + /* first lan chip */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, + GPMC_SIZE_16M); + + /* second lan chip */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000, + GPMC_SIZE_16M); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/board/overo/overo.h b/board/overo/overo.h index 18735232a15..33a92e4e126 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -138,7 +138,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ /* - SMSC911X_NRES*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ /*DSS*/\ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ @@ -189,18 +189,18 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ /* - PEN_DOWN*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ /*Audio Interface */\ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ /*Expansion card */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ @@ -211,7 +211,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ /*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ @@ -220,7 +220,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ /*Bluetooth*/\ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ @@ -301,7 +301,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ @@ -387,5 +387,36 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ +#define MUX_OVERO_SDIO2_DIRECT() \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/ + +#define MUX_OVERO_SDIO2_TRANSCEIVER() \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/ #endif diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 060d5d17c90..43367291132 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -67,7 +67,7 @@ int board_mmc_init(bd_t *bis) int i; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - gpio_direction_output(&s5pc110_gpio->gpio_j2, 7, 1); + gpio_direction_output(&s5pc110_gpio->j2, 7, 1); /* * MMC0 GPIO @@ -80,11 +80,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPG0[0:6] special function 2 */ - gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2); + gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE); + gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4X); + gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); } return s5p_mmc_init(0); diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 4b729927f42..62737aba1ab 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -51,7 +51,7 @@ lowlevel_init: ldr r7, =S5PC100_GPIO_BASE ldr r8, =S5PC100_GPIO_BASE /* Read CPU ID */ - ldr r2, =S5PC1XX_PRO_ID + ldr r2, =S5PC110_PRO_ID ldr r0, [r2] mov r1, #0x00010000 and r0, r0, r1 @@ -377,7 +377,7 @@ lockloop: * void system_clock_init(void) */ system_clock_init: - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Check S5PC100 */ cmp r7, r8 @@ -437,7 +437,7 @@ system_clock_init: ldr r1, =0x3ff03ff str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 32572c51da9..30d0d06a440 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -131,7 +131,7 @@ wakeup_reset: * void system_clock_init(void) */ system_clock_init: - ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x00011110 diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index c25869e5c40..501855edd38 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -35,7 +35,8 @@ void onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); struct samsung_onenand *onenand; int value; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index fb466c6ece4..31e8d9e0ec3 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -38,10 +38,10 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile new file mode 100644 index 00000000000..87d2234ca38 --- /dev/null +++ b/board/syteco/jadecpu/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += jadecpu.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk new file mode 100644 index 00000000000..c661f0b8afd --- /dev/null +++ b/board/syteco/jadecpu/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x46000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c new file mode 100644 index 00000000000..04d2f9d5a66 --- /dev/null +++ b/board/syteco/jadecpu/jadecpu.c @@ -0,0 +1,170 @@ +/* + * (c) 2010 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/mb86r0x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) + MB86R0x_CCNT_BASE; + + /* We select mode 0 for group 2 and mode 1 for group 4 */ + writel(0x00000010, &ccnt->cmux_md); + + gd->flags = 0; + gd->bd->bi_arch_number = MACH_TYPE_JADECPU; + gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; + + icache_enable(); + + return 0; +} + +static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, + unsigned long pwm_base) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; + const char *e; + + writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); + + e = getenv(pwm_opts); + if (e != NULL) { + const char *s; + uint32_t freq, init; + + freq = 0; + init = 0; + + s = strchr(e, 'f'); + if (s != NULL) + freq = simple_strtol(s + 2, NULL, 0); + + s = strchr(e, 'i'); + if (s != NULL) + init = simple_strtol(s + 2, NULL, 0); + + if (freq > 0) { + writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, + &pwm->bcr); + writel(1002, &pwm->tpr); + writel(1, &pwm->pr); + writel(init * 10 + 1, &pwm->dr); + writel(1, &pwm->cr); + writel(1, &pwm->sr); + } + } +} + +int board_late_init(void) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + uint32_t in_word; + +#ifdef CONFIG_VIDEO_MB86R0xGDC + /* Check if we have valid display settings and turn on power if so */ + /* Display 0 */ + if (getenv("gs_dsp_0_param") || getenv("videomode")) + setup_display_power((1 << 3), "gs_dsp_0_pwm", + MB86R0x_PWM0_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); + + /* Display 1 */ + if (getenv("gs_dsp_1_param") || getenv("videomode1")) + setup_display_power((1 << 4), "gs_dsp_1_pwm", + MB86R0x_PWM1_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); +#endif /* CONFIG_VIDEO_MB86R0xGDC */ + + /* 5V enable */ + writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); + writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); + + /* We have special boot options if told by GPIOs */ + in_word = readl(&gpio->gpdr1); + + if ((in_word & 0xC0) == 0xC0) { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + setenv("preboot", "run gs_slow_boot"); + } else if ((in_word & 0xC0) != 0) { + setenv("stdout", "vga"); + setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;" + "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;" + "bootelf 0x40000000; bootelf 0x10080000"); + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + if (getenv("gs_devel")) { + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("gs_bootcmd", "bootelf 0x10080000"); + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +/* + * DRAM configuration + */ +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S new file mode 100644 index 00000000000..5ad4dceb924 --- /dev/null +++ b/board/syteco/jadecpu/lowlevel_init.S @@ -0,0 +1,265 @@ +/* + * Board specific setup info + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, <philippe.robin@arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/mb86r0x.h> +#include <asm/arch/asm-offsets.h> + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: +/* + * Initialize Clock Reset Generator (CRG) + */ + + ldr r0, =MB86R0x_CRG_BASE + + /* Not change the initial value that is set by external pin.*/ +WAIT_PLL: + ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ + tst r2, #MB86R0x_CRG_CRPR_PLLRDY + beq WAIT_PLL + + /* Set clock gate control */ + ldr r1, =CONFIG_SYS_CRG_CRHA_INIT + str r1, [r0, #CRG_CRHA] + ldr r1, =CONFIG_SYS_CRG_CRPA_INIT + str r1, [r0, #CRG_CRPA] + ldr r1, =CONFIG_SYS_CRG_CRPB_INIT + str r1, [r0, #CRG_CRPB] + ldr r1, =CONFIG_SYS_CRG_CRHB_INIT + str r1, [r0, #CRG_CRHB] + ldr r1, =CONFIG_SYS_CRG_CRAM_INIT + str r1, [r0, #CRG_CRAM] + +/* + * Initialize External Bus Interface + */ + ldr r0, =MB86R0x_MEMC_BASE + + ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT + str r1, [r0, #MEMC_MCFMODE0] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT + str r1, [r0, #MEMC_MCFMODE2] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT + str r1, [r0, #MEMC_MCFMODE4] + + ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT + str r1, [r0, #MEMC_MCFTIM0] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT + str r1, [r0, #MEMC_MCFTIM2] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT + str r1, [r0, #MEMC_MCFTIM4] + + ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT + str r1, [r0, #MEMC_MCFAREA0] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT + str r1, [r0, #MEMC_MCFAREA2] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT + str r1, [r0, #MEMC_MCFAREA4] + +/* + * Initialize DDR2 Controller + */ + + /* Wait for PLL LOCK up time or more */ + wait_timer 20 + + /* + * (2) Initialize DDRIF + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT + strh r1, [r0, #DDR2_DRIMS] + + /* + * (3) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (4) IRESET/IUSRRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 + str r1, [r0, #CCNT_CDCRC] + + /* + * (5) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (6) IDLLRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 + str r1, [r0, #CCNT_CDCRC] + + /* + * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) + */ + wait_timer 33536 + + /* + * (9) MCKE ON + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT + strh r1, [r0, #DDR2_DRCA] + ldr r1, =MB86R0x_DDR2_DRCI_INIT + strh r1, [r0, #DDR2_DRIC] + + /* + * (10) Initialize SDRAM + */ + + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 67 /* 400ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 18 /* 105ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 /* MRS to OCD: 200clock */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT + strh r1, [r0, #DDR2_DRCM] + + ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT + strh r1, [r0, #DDR2_DRCST1] + + ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT + strh r1, [r0, #DDR2_DRCST2] + + ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT + strh r1, [r0, #DDR2_DRCR] + + ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT + strh r1, [r0, #DDR2_DRCF] + + ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT + strh r1, [r0, #DDR2_DRASR] + + /* + * (11) ODT setting + */ + ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT + strh r1, [r0, #DDR2_DROBS] + ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT + strh r1, [r0, #DDR2_DROABA] + ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT + strh r1, [r0, #DDR2_DRIBSODT1] + + /* + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode + */ + ldr r1, =CONFIG_SYS_DDR2_DROS_INIT + strh r1, [r0, #DDR2_DROS] + ldr r1, =MB86R0x_DDR2_DRCI_NORMAL + strh r1, [r0, #DDR2_DRIC] + + mov pc, lr diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 3b4c9e73b57..4647908052c 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -38,8 +38,6 @@ #include <asm/mach-types.h> #include "beagle.h" -static int beagle_revision_c; - /* * Routine: board_init * Description: Early hardware init. @@ -58,43 +56,41 @@ int board_init(void) } /* - * Routine: beagle_get_revision - * Description: Return the revision of the BeagleBoard this code is running on. - * If it is a revision Ax/Bx board, this function returns 0, - * on a revision C board you will get a 1. + * Routine: get_board_revision + * Description: Detect if we are running on a Beagle revision Ax/Bx, + * C1/2/3, C4 or xM. This can be done by reading + * the level of GPIO173, GPIO172 and GPIO171. This should + * result in + * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx + * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 + * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 + * GPIO173, GPIO172, GPIO171: 0 0 0 => xM */ -int beagle_get_revision(void) +int get_board_revision(void) { - return beagle_revision_c; -} + int revision; -/* - * Routine: beagle_identify - * Description: Detect if we are running on a Beagle revision Ax/Bx or - * Cx. This can be done by GPIO_171. If this is low, we are - * running on a revision C board. - */ -void beagle_identify(void) -{ - beagle_revision_c = 0; - if (!omap_request_gpio(171)) { - unsigned int val; + if (!omap_request_gpio(171) && + !omap_request_gpio(172) && + !omap_request_gpio(173)) { omap_set_gpio_direction(171, 1); - val = omap_get_gpio_datain(171); - omap_free_gpio(171); + omap_set_gpio_direction(172, 1); + omap_set_gpio_direction(173, 1); - if (val) - beagle_revision_c = 0; - else - beagle_revision_c = 1; + revision = omap_get_gpio_datain(173) << 2 | + omap_get_gpio_datain(172) << 1 | + omap_get_gpio_datain(171); + + omap_free_gpio(171); + omap_free_gpio(172); + omap_free_gpio(173); + } else { + printf("Error: unable to acquire board revision GPIOs\n"); + revision = -1; } - printf("Board revision "); - if (beagle_revision_c) - printf("C\n"); - else - printf("Ax/Bx\n"); + return revision; } /* @@ -106,6 +102,44 @@ int misc_init_r(void) struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + switch (get_board_revision()) { + case REVISION_AXBX: + printf("Beagle Rev Ax/Bx\n"); + setenv("beaglerev", "AxBx"); + setenv("mpurate", "600"); + break; + case REVISION_CX: + printf("Beagle Rev C1/C2/C3\n"); + setenv("beaglerev", "Cx"); + setenv("mpurate", "600"); + MUX_BEAGLE_C(); + break; + case REVISION_C4: + printf("Beagle Rev C4\n"); + setenv("beaglerev", "C4"); + setenv("mpurate", "720"); + MUX_BEAGLE_C(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; + case REVISION_XM: + printf("Beagle xM Rev A\n"); + setenv("beaglerev", "xMA"); + setenv("mpurate", "1000"); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; + default: + printf("Beagle unknown 0x%02x\n", get_board_revision()); + } + twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); @@ -120,8 +154,6 @@ int misc_init_r(void) writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); - beagle_identify(); - dieid_num_r(); return 0; @@ -136,8 +168,4 @@ int misc_init_r(void) void set_muxconf_regs(void) { MUX_BEAGLE(); - - if (beagle_revision_c) { - MUX_BEAGLE_C(); - } } diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index 7fe6275e379..d86033772b8 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -33,7 +33,11 @@ const omap3_sysinfo sysinfo = { #endif }; -#define BOARD_REVISION_MASK (0x1 << 11) +/* BeagleBoard revisions */ +#define REVISION_AXBX 0x7 +#define REVISION_CX 0x6 +#define REVISION_C4 0x5 +#define REVISION_XM 0x0 /* * IEN - Input Enable @@ -264,7 +268,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ @@ -374,11 +378,37 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ #define MUX_BEAGLE_C() \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ +#define MUX_BEAGLE_XM() \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ + MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ + MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ + MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ + MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ + MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ + #endif diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda.h index 8f6a6b1a6b8..877ae5f9598 100644 --- a/board/ti/panda/panda.h +++ b/board/ti/panda/panda.h @@ -237,28 +237,28 @@ const struct pad_conf_entry core_padconf_array[] = { }; const struct pad_conf_entry wkup_padconf_array[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ - {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ - {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ + {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ + {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ }; #endif diff --git a/boards.cfg b/boards.cfg index 69c68979354..05ddb8c69d4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -43,6 +43,7 @@ meesc arm arm926ejs - esd at91 otc570 arm arm926ejs - esd at91 pm9261 arm arm926ejs - ronetix at91 pm9263 arm arm926ejs - ronetix at91 +jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood mx51evk arm armv7 mx51evk freescale mx51 diff --git a/common/serial.c b/common/serial.c index fceabfa1e7e..1345c08aefd 100644 --- a/common/serial.c +++ b/common/serial.c @@ -40,9 +40,9 @@ struct serial_device *__default_serial_console (void) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \ - || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ - || defined(CONFIG_SYS_SC520) + || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ + || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ + || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; @@ -78,7 +78,7 @@ struct serial_device *__default_serial_console (void) #else #error "CONFIG_SERIAL? missing." #endif -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) #if defined(CONFIG_SERIAL0) return &s5p_serial0_device; #elif defined(CONFIG_SERIAL1) @@ -162,7 +162,7 @@ void serial_initialize (void) serial_register(&s3c24xx_serial1_device); serial_register(&s3c24xx_serial2_device); #endif -#if defined(CONFIG_S5PC1XX) +#if defined(CONFIG_S5P) serial_register(&s5p_serial0_device); serial_register(&s5p_serial1_device); serial_register(&s5p_serial2_device); diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci new file mode 100644 index 00000000000..18b1bdf7e5d --- /dev/null +++ b/doc/README.atmel_mci @@ -0,0 +1,86 @@ +How to use SD/MMC cards with Atmel SoCs having MCI hardware +----------------------------------------------------------- +2010-08-16 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> + +This is a new approach to use Atmel MCI hardware with the +general MMC framework. Therefore it benefits from that +framework's abilities to handle SDHC Cards and the ability +to write blocks. + +- AT91SAM9XE512 (tested, will definitely work with XE128 and XE256) +- AT91SAM9260 (not tested, but MCI is to AT91SAM9XE) +- AT91SAM9G20 (not tested, should work) + +It should work with all other ATMEL devices that have MCI, +including AVR32. + +The generic driver does NOT assign port pins to the MCI block +nor does it start the MCI clock. This has to be handled in a +board/SoC specific manner before the driver is initialized: + +example: this is added to at91sam9260_devices.c: + +#if defined(CONFIG_ATMEL_MCI) || defined(CONFIG_GENERIC_ATMEL_MCI) +void at91_mci_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCCK */ +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* MCCDB */ + at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* MCDB0 */ + at91_set_b_periph(AT91_PIO_PORTA, 5, PUP); /* MCDB1 */ + at91_set_b_periph(AT91_PIO_PORTA, 4, PUP); /* MCDB2 */ + at91_set_b_periph(AT91_PIO_PORTA, 3, PUP); /* MCDB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCDA3 */ +#endif +} +#endif + +the board specific file need added: +... +#ifdef CONFIG_GENERIC_ATMEL_MCI +# include <mmc.h> +#endif +... +#ifdef CONFIG_GENERIC_ATMEL_MCI +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_mci_hw_init(); + + /* This calls the atmel_mci_init in gen_atmel_mci.c */ + return atmel_mci_init((void *)AT91_BASE_MCI); +} + +/* this is a weak define that we are overriding */ +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + /* + * the only currently existing use of this function + * (fsl_esdhc.c) suggests this function must return + * *cs = TRUE if a card is NOT detected -> in most + * cases the value of the pin when the detect switch + * closes to GND + */ + *cd = at91_get_gpio_value (CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; + return 0; +} + +#endif + +and the board definition files needs: + +/* SD/MMC card */ +#define CONFIG_MMC 1 +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_GENERIC_ATMEL_MCI 1 +#define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */ +#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 +#define CONFIG_CMD_MMC 1 + diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 528ca2e99af..07d395d898f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,7 +29,7 @@ COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o -COBJS-$(CONFIG_S5PC1XX) += s5p_gpio.o +COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 8dfd8a32ba6..6603d74294b 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -25,12 +25,13 @@ include $(TOPDIR)/config.mk LIB := $(obj)libmmc.a -COBJS-$(CONFIG_GENERIC_MMC) += mmc.o COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o -COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o +COBJS-$(CONFIG_GENERIC_MMC) += mmc.o +COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o +COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o diff --git a/drivers/mmc/atmel_mci.h b/drivers/mmc/atmel_mci.h index 5b4f5c99b6d..823a77d91b3 100644 --- a/drivers/mmc/atmel_mci.h +++ b/drivers/mmc/atmel_mci.h @@ -22,7 +22,45 @@ #ifndef __CPU_AT32AP_ATMEL_MCI_H__ #define __CPU_AT32AP_ATMEL_MCI_H__ -/* Atmel MultiMedia Card Interface (MCI) registers */ +#ifndef __ASSEMBLY__ + +/* + * Structure for struct SoC access. + * Names starting with '_' are fillers. + */ +typedef struct atmel_mci { + /* reg Offset */ + u32 cr; /* 0x00 */ + u32 mr; /* 0x04 */ + u32 dtor; /* 0x08 */ + u32 sdcr; /* 0x0c */ + u32 argr; /* 0x10 */ + u32 cmdr; /* 0x14 */ + u32 _18; /* 0x18 */ + u32 _1c; /* 0x1c */ + u32 rspr; /* 0x20 */ + u32 rspr1; /* 0x24 */ + u32 rspr2; /* 0x28 */ + u32 rspr3; /* 0x2c */ + u32 rdr; /* 0x30 */ + u32 tdr; /* 0x34 */ + u32 _38; /* 0x38 */ + u32 _3c; /* 0x3c */ + u32 sr; /* 0x40 */ + u32 ier; /* 0x44 */ + u32 idr; /* 0x48 */ + u32 imr; /* 0x4c */ +} atmel_mci_t; + +#endif /* __ASSEMBLY__ */ + +/* + * NOTICE: Use of registers offsets is depreciated. + * These defines will be removed once the old driver + * is taken out of commision. + * + * Atmel MultiMedia Card Interface (MCI) registers + */ #define MMCI_CR 0x0000 #define MMCI_MR 0x0004 #define MMCI_DTOR 0x0008 @@ -192,7 +230,13 @@ << MMCI_##name##_OFFSET)) \ | MMCI_BF(name,value)) -/* Register access macros */ +/* + * NOTICE: Use of registers offsets is depreciated. + * These defines will be removed once the old driver + * is taken out of commision. + * + * Register access macros + */ #define mmci_readl(reg) \ readl((void *)MMCI_BASE + MMCI_##reg) #define mmci_writel(reg,value) \ diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c new file mode 100644 index 00000000000..fa4df9943a7 --- /dev/null +++ b/drivers/mmc/gen_atmel_mci.c @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2010 + * Rob Emanuele <rob@emanuele.us> + * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de> + * + * Original Driver: + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mmc.h> +#include <part.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/byteorder.h> +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> +#include "atmel_mci.h" + +#ifndef CONFIG_SYS_MMC_CLK_OD +# define CONFIG_SYS_MMC_CLK_OD 150000 +#endif + +#define MMC_DEFAULT_BLKLEN 512 + +#if defined(CONFIG_ATMEL_MCI_PORTB) +# define MCI_BUS 1 +#else +# define MCI_BUS 0 +#endif + +static int initialized = 0; + +/* + * Print command and status: + * + * - always when DEBUG is defined + * - on command errors + */ +static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) +{ + printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n", + cmdr, cmdr&0x3F, arg, status, msg); +} + +/* Setup for MCI Clock and Block Size */ +static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) +{ + atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + u32 bus_hz = get_mci_clk_rate(); + u32 clkdiv = 255; + + debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n", + bus_hz, hz, blklen); + if (hz > 0) { + /* find lowest clkdiv yielding a rate <= than requested */ + for (clkdiv=0; clkdiv<255; clkdiv++) { + if ((bus_hz / (clkdiv+1) / 2) <= hz) + break; + } + } + printf("mci: setting clock %u Hz, block size %u\n", + (bus_hz / (clkdiv+1)) / 2, blklen); + + blklen &= 0xfffc; + /* On some platforms RDPROOF and WRPROOF are ignored */ + writel((MMCI_BF(CLKDIV, clkdiv) + | MMCI_BF(BLKLEN, blklen) + | MMCI_BIT(RDPROOF) + | MMCI_BIT(WRPROOF)), &mci->mr); + initialized = 1; +} + +/* Return the CMDR with flags for a given command and data packet */ +static u32 mci_encode_cmd( + struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags) +{ + u32 cmdr = 0; + + /* Default Flags for Errors */ + *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) | + MMCI_BIT(RINDE) | MMCI_BIT(RTOE)); + + /* Default Flags for the Command */ + cmdr |= MMCI_BIT(MAXLAT); + + if (data) { + cmdr |= MMCI_BF(TRCMD, 1); + if (data->blocks > 1) + cmdr |= MMCI_BF(TRTYP, 1); + if (data->flags & MMC_DATA_READ) + cmdr |= MMCI_BIT(TRDIR); + } + + if (cmd->resp_type & MMC_RSP_CRC) + *error_flags |= MMCI_BIT(RCRCE); + if (cmd->resp_type & MMC_RSP_136) + cmdr |= MMCI_BF(RSPTYP, 2); + else if (cmd->resp_type & MMC_RSP_BUSY) + cmdr |= MMCI_BF(RSPTYP, 3); + else if (cmd->resp_type & MMC_RSP_PRESENT) + cmdr |= MMCI_BF(RSPTYP, 1); + + return cmdr | MMCI_BF(CMDNB, cmd->cmdidx); +} + +/* Entered into function pointer in mci_send_cmd */ +static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags) +{ + u32 status; + + do { + status = readl(&mci->sr); + if (status & (error_flags | MMCI_BIT(OVRE))) + goto io_fail; + } while (!(status & MMCI_BIT(RXRDY))); + + if (status & MMCI_BIT(RXRDY)) { + *data = readl(&mci->rdr); + status = 0; + } +io_fail: + return status; +} + +/* Entered into function pointer in mci_send_cmd */ +static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags) +{ + u32 status; + + do { + status = readl(&mci->sr); + if (status & (error_flags | MMCI_BIT(UNRE))) + goto io_fail; + } while (!(status & MMCI_BIT(TXRDY))); + + if (status & MMCI_BIT(TXRDY)) { + writel(*data, &mci->tdr); + status = 0; + } +io_fail: + return status; +} + +/* + * Entered into mmc structure during driver init + * + * Sends a command out on the bus and deals with the block data. + * Takes the mmc pointer, a command pointer, and an optional data pointer. + */ +static int +mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + u32 cmdr; + u32 error_flags = 0; + u32 status; + + if (!initialized) { + puts ("MCI not initialized!\n"); + return COMM_ERR; + } + + /* Figure out the transfer arguments */ + cmdr = mci_encode_cmd(cmd, data, &error_flags); + + /* Send the command */ + writel(cmd->cmdarg, &mci->argr); + writel(cmdr, &mci->cmdr); + +#ifdef DEBUG + dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG"); +#endif + + /* Wait for the command to complete */ + while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY))); + + if (status & error_flags) { + dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed"); + return COMM_ERR; + } + + /* Copy the response to the response buffer */ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mci->rspr); + cmd->response[1] = readl(&mci->rspr1); + cmd->response[2] = readl(&mci->rspr2); + cmd->response[3] = readl(&mci->rspr3); + } else + cmd->response[0] = readl(&mci->rspr); + + /* transfer all of the blocks */ + if (data) { + u32 word_count, block_count; + u32* ioptr; + u32 sys_blocksize, dummy, i; + u32 (*mci_data_op) + (atmel_mci_t *mci, u32* data, u32 error_flags); + + if (data->flags & MMC_DATA_READ) { + mci_data_op = mci_data_read; + sys_blocksize = mmc->read_bl_len; + ioptr = (u32*)data->dest; + } else { + mci_data_op = mci_data_write; + sys_blocksize = mmc->write_bl_len; + ioptr = (u32*)data->src; + } + + status = 0; + for (block_count = 0; + block_count < data->blocks && !status; + block_count++) { + word_count = 0; + do { + status = mci_data_op(mci, ioptr, error_flags); + word_count++; + ioptr++; + } while (!status && word_count < (data->blocksize/4)); +#ifdef DEBUG + if (data->flags & MMC_DATA_READ) + { + printf("Read Data:\n"); + print_buffer(0, data->dest, 1, + word_count*4, 0); + } +#endif +#ifdef DEBUG + if (!status && word_count < (sys_blocksize / 4)) + printf("filling rest of block...\n"); +#endif + /* fill the rest of a full block */ + while (!status && word_count < (sys_blocksize / 4)) { + status = mci_data_op(mci, &dummy, + error_flags); + word_count++; + } + if (status) { + dump_cmd(cmdr, cmd->cmdarg, status, + "Data Transfer Failed"); + return COMM_ERR; + } + } + + /* Wait for Transfer End */ + i = 0; + do { + status = readl(&mci->sr); + + if (status & error_flags) { + dump_cmd(cmdr, cmd->cmdarg, status, + "DTIP Wait Failed"); + return COMM_ERR; + } + i++; + } while ((status & MMCI_BIT(DTIP)) && i < 10000); + if (status & MMCI_BIT(DTIP)) { + dump_cmd(cmdr, cmd->cmdarg, status, + "XFER DTIP never unset, ignoring"); + } + } + + return 0; +} + +/* Entered into mmc structure during driver init */ +static void mci_set_ios(struct mmc *mmc) +{ + atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + int busw = (mmc->bus_width == 4) ? 1 : 0; + + /* Set the clock speed */ + mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); + + /* + * set the bus width and select slot for this interface + * there is no capability for multiple slots on the same interface yet + * Bitfield SCDBUS needs to be expanded to 2 bits for 8-bit buses + */ + writel(MMCI_BF(SCDBUS, busw) | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); +} + +/* Entered into mmc structure during driver init */ +static int mci_init(struct mmc *mmc) +{ + atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + + /* Initialize controller */ + writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ + writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */ + writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */ + + /* Initial Time-outs */ + writel(0x5f, &mci->dtor); + /* Disable Interrupts */ + writel(~0UL, &mci->idr); + + /* Set default clocks and blocklen */ + mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + + return 0; +} + +/* + * This is the only exported function + * + * Call it with the MCI register base address + */ +int atmel_mci_init(void *regs) +{ + struct mmc *mmc = malloc(sizeof(struct mmc)); + + if (!mmc) + return -1; + strcpy(mmc->name, "mci"); + mmc->priv = regs; + mmc->send_cmd = mci_send_cmd; + mmc->set_ios = mci_set_ios; + mmc->init = mci_init; + + /* need to be able to pass these in on a board by board basis */ + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->host_caps = MMC_MODE_4BIT; + /* + * min and max frequencies determined by + * max and min of clock divider + */ + mmc->f_min = get_mci_clk_rate() / (2*256); + mmc->f_max = get_mci_clk_rate() / (2*1); + + mmc_register(mmc); + + return 0; +} diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 9506cca2181..15d41e55bd1 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -33,7 +33,7 @@ #include "omap3_mmc.h" -const unsigned short mmc_transspeed_val[15][4] = { +static const unsigned short mmc_transspeed_val[15][4] = { {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, @@ -51,7 +51,7 @@ const unsigned short mmc_transspeed_val[15][4] = { {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} }; -mmc_card_data cur_card_data; +static mmc_card_data cur_card_data; static block_dev_desc_t mmc_blk_dev; static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE; @@ -80,7 +80,7 @@ block_dev_desc_t *mmc_get_dev(int dev) return (block_dev_desc_t *) &mmc_blk_dev; } -unsigned char mmc_board_init(void) +static unsigned char mmc_board_init(void) { #if defined(CONFIG_TWL4030_POWER) twl4030_power_mmc_init(); @@ -114,7 +114,7 @@ unsigned char mmc_board_init(void) return 1; } -void mmc_init_stream(void) +static void mmc_init_stream(void) { writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); @@ -129,7 +129,7 @@ void mmc_init_stream(void) writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } -unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) +static unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) { unsigned int val; @@ -158,7 +158,7 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) return 1; } -unsigned char mmc_init_setup(void) +static unsigned char mmc_init_setup(void) { unsigned int reg_val; @@ -192,7 +192,7 @@ unsigned char mmc_init_setup(void) return 1; } -unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, +static unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, unsigned int *response) { unsigned int mmc_stat; @@ -228,7 +228,7 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, return 1; } -unsigned char mmc_read_data(unsigned int *output_buf) +static unsigned char mmc_read_data(unsigned int *output_buf) { unsigned int mmc_stat; unsigned int read_count = 0; @@ -269,7 +269,7 @@ unsigned char mmc_read_data(unsigned int *output_buf) return 1; } -unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) +static unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) { unsigned char err; unsigned int argument = 0; @@ -380,7 +380,7 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) return 1; } -unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, +static unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, mmc_csd_reg_t *cur_csd) { mmc_extended_csd_reg_t ext_csd; @@ -434,45 +434,48 @@ unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, return 1; } -unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, - mmc_card_data *mmc_c, - unsigned long *output_buf) +static unsigned long mmc_bread(int dev_num, unsigned long blknr, + lbaint_t blkcnt, void *dst) { unsigned char err; unsigned int argument; unsigned int resp[4]; - unsigned int num_sec_val = - (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + unsigned int *output_buf = dst; unsigned int sec_inc_val; + lbaint_t i; - if (num_sec_val == 0) - return 1; + if (blkcnt == 0) + return 0; - if (mmc_c->mode == SECTOR_MODE) { - argument = start_sec; + if (cur_card_data.mode == SECTOR_MODE) { + argument = blknr; sec_inc_val = 1; } else { - argument = start_sec * MMCSD_SECTOR_SIZE; + argument = blknr * MMCSD_SECTOR_SIZE; sec_inc_val = MMCSD_SECTOR_SIZE; } - while (num_sec_val) { + for (i = 0; i < blkcnt; i++) { err = mmc_send_cmd(MMC_CMD17, argument, resp); - if (err != 1) - return err; + if (err != 1) { + printf("mmc: CMD17 failed, status = %08x\n", err); + break; + } - err = mmc_read_data((unsigned int *) output_buf); - if (err != 1) - return err; + err = mmc_read_data(output_buf); + if (err != 1) { + printf("mmc: read failed, status = %08x\n", err); + break; + } output_buf += (MMCSD_SECTOR_SIZE / 4); argument += sec_inc_val; - num_sec_val--; } - return 1; + + return i; } -unsigned char configure_mmc(mmc_card_data *mmc_card_cur) +static unsigned char configure_mmc(mmc_card_data *mmc_card_cur) { unsigned char ret_val; unsigned int argument; @@ -541,13 +544,6 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur) return 1; } -unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, - void *dst) -{ - omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, - (unsigned long *) dst); - return 1; -} int mmc_legacy_init(int dev) { diff --git a/drivers/mmc/omap3_mmc.h b/drivers/mmc/omap3_mmc.h index cbb3dc3a3a6..e4d263c8776 100644 --- a/drivers/mmc/omap3_mmc.h +++ b/drivers/mmc/omap3_mmc.h @@ -230,13 +230,4 @@ typedef union { mmc_csd_reg_t Card_CSD; } mmc_resp_t; -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - #endif /* MMC_H */ diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index 669b1d0d2f9..1fd425cbb67 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -23,12 +23,6 @@ #include <asm/io.h> #include <asm/arch/mmc.h> -#ifdef DEBUG_S5P_HSMMC -#define dbg(x...) printf(x) -#else -#define dbg(x...) do { } while (0) -#endif - /* support 4 mmc hosts */ struct mmc mmc_dev[4]; struct mmc_host mmc_host[4]; @@ -36,18 +30,14 @@ struct mmc_host mmc_host[4]; static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index) { unsigned long offset = dev_index * sizeof(struct s5p_mmc); - - if (cpu_is_s5pc100()) - return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset); - else - return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset); + return (struct s5p_mmc *)(samsung_get_base_mmc() + offset); } static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) { unsigned char ctrl; - dbg("data->dest: %08x\n", (u32)data->dest); + debug("data->dest: %08x\n", (u32)data->dest); writel((u32)data->dest, &host->reg->sysad); /* * DMASEL[4:3] @@ -128,7 +118,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) mmc_prepare_data(host, data); - dbg("cmd->arg: %08x\n", cmd->cmdarg); + debug("cmd->arg: %08x\n", cmd->cmdarg); writel(cmd->cmdarg, &host->reg->argument); if (data) @@ -165,7 +155,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) flags |= (1 << 5); - dbg("cmd: %d\n", cmd->cmdidx); + debug("cmd: %d\n", cmd->cmdidx); writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); @@ -186,11 +176,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (mask & (1 << 16)) { /* Timeout Error */ - dbg("timeout: %08x cmd %d\n", mask, cmd->cmdidx); + debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); return TIMEOUT; } else if (mask & (1 << 15)) { /* Error Interrupt */ - dbg("error: %08x cmd %d\n", mask, cmd->cmdidx); + debug("error: %08x cmd %d\n", mask, cmd->cmdidx); return -1; } @@ -206,7 +196,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, cmd->response[i] |= readb(offset - 1); } - dbg("cmd->resp[%d]: %08x\n", + debug("cmd->resp[%d]: %08x\n", i, cmd->response[i]); } } else if (cmd->resp_type & MMC_RSP_BUSY) { @@ -223,10 +213,10 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } cmd->response[0] = readl(&host->reg->rspreg0); - dbg("cmd->resp[0]: %08x\n", cmd->response[0]); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); } else { cmd->response[0] = readl(&host->reg->rspreg0); - dbg("cmd->resp[0]: %08x\n", cmd->response[0]); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); } } @@ -242,11 +232,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return -1; } else if (mask & (1 << 3)) { /* DMA Interrupt */ - dbg("DMA end\n"); + debug("DMA end\n"); break; } else if (mask & (1 << 1)) { /* Transfer Complete */ - dbg("r/w is done\n"); + debug("r/w is done\n"); break; } } @@ -288,7 +278,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) div = 2; else div = 1; - dbg("div: %d\n", div); + debug("div: %d\n", div); div >>= 1; /* @@ -325,7 +315,7 @@ static void mmc_set_ios(struct mmc *mmc) unsigned char ctrl; unsigned long val; - dbg("set_ios: bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); + debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); /* * SELCLKPADDS[17:16] diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9a88a..7d178468adb 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,9 +2653,12 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } if (!type) { - printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" - " 0x%02x, Chip ID: 0x%02x\n", __func__, - *maf_id, dev_id); + /* supress warning if there is no nand */ + if (*maf_id != 0x00 && *maf_id != 0xff && + dev_id != 0x00 && dev_id != 0xff) + printk(KERN_INFO "%s: unknown NAND device: " + "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", + __func__, *maf_id, dev_id); return ERR_PTR(-ENODEV); } diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c index f2be687639b..20b49124d5a 100644 --- a/drivers/mtd/onenand/samsung.c +++ b/drivers/mtd/onenand/samsung.c @@ -67,7 +67,7 @@ do { \ #define MAP_01 (0x1 << 24) #define MAP_10 (0x2 << 24) #define MAP_11 (0x3 << 24) -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) #define MAP_00 (0x0 << 26) #define MAP_01 (0x1 << 26) #define MAP_10 (0x2 << 26) @@ -121,7 +121,7 @@ static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) { return (fba << 12) | (fpa << 6) | (fsa << 4); } -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) { return (fba << 13) | (fpa << 7) | (fsa << 5); @@ -614,7 +614,7 @@ void s3c_onenand_init(struct mtd_info *mtd) #if defined(CONFIG_S3C64XX) onenand->base = (void *)0x70100000; onenand->ahb_addr = (void *)0x20000000; -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) onenand->base = (void *)0xE7100000; onenand->ahb_addr = (void *)0xB0000000; #endif diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index eb066cb58df..1a5408959e1 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -59,57 +59,48 @@ void twl4030_power_reset_init(void) } } - /* - * Power Init + * Set Device Group and Voltage */ -#define DEV_GRP_P1 0x20 -#define VAUX3_VSEL_28 0x03 -#define DEV_GRP_ALL 0xE0 -#define VPLL2_VSEL_18 0x05 -#define VDAC_VSEL_18 0x03 +void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, + u8 dev_grp, u8 dev_grp_sel) +{ + /* Select the Device Group */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel, + dev_grp); + + /* Select the Voltage */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val, + vsel_reg); +} void twl4030_power_init(void) { - unsigned char byte; - /* set VAUX3 to 2.8V */ - byte = DEV_GRP_P1; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VAUX3_DEV_GRP); - byte = VAUX3_VSEL_28; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VAUX3_DEDICATED); + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED, + TWL4030_PM_RECEIVER_VAUX3_VSEL_28, + TWL4030_PM_RECEIVER_VAUX3_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); /* set VPLL2 to 1.8V */ - byte = DEV_GRP_ALL; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VPLL2_DEV_GRP); - byte = VPLL2_VSEL_18; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VPLL2_DEDICATED); + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED, + TWL4030_PM_RECEIVER_VPLL2_VSEL_18, + TWL4030_PM_RECEIVER_VPLL2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_ALL); /* set VDAC to 1.8V */ - byte = DEV_GRP_P1; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VDAC_DEV_GRP); - byte = VDAC_VSEL_18; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VDAC_DEDICATED); + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED, + TWL4030_PM_RECEIVER_VDAC_VSEL_18, + TWL4030_PM_RECEIVER_VDAC_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); } -#define VMMC1_VSEL_30 0x02 - void twl4030_power_mmc_init(void) { - unsigned char byte; - - byte = DEV_GRP_P1; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VMMC1_DEV_GRP); - - /* 3 Volts */ - byte = VMMC1_VSEL_30; - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte, - TWL4030_PM_RECEIVER_VMMC1_DEDICATED); + /* Set VMMC1 to 3 Volts */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED, + TWL4030_PM_RECEIVER_VMMC1_VSEL_30, + TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); } + diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 772a49a9021..98734db77f6 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)librtc.a +COBJS-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o COBJS-y += date.o COBJS-$(CONFIG_RTC_DS12887) += ds12887.o diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c new file mode 100644 index 00000000000..de8e30d0d7c --- /dev/null +++ b/drivers/rtc/at91sam9_rtt.c @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the internal Real-time Timer + * of AT91SAM9260 and compatibles. + * Compatible with the LinuX rtc driver workaround: + * The RTT cannot be written to, but only reset. + * The actual time is the sum of RTT and one of + * the four GPBR registers. + * + * The at91sam9260 has 4 GPBR (0-3). + * For their typical use see at91_gpbr.h ! + * + * make sure u-boot and kernel use the same GPBR ! + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <asm/errno.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_rtt.h> +#include <asm/arch/at91_gpbr.h> + +#if defined(CONFIG_CMD_DATE) + +int rtc_get (struct rtc_time *tmp) +{ + at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + ulong tim; + ulong tim2; + ulong off; + + do { + tim = readl(&rtt->vr); + tim2 = readl(&rtt->vr); + } while (tim!=tim2); + off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); + /* off==0 means time is invalid, but we ignore that */ + to_tm (tim+off, tmp); + return 0; +} + +int rtc_set (struct rtc_time *tmp) +{ + at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + ulong tim; + + tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* clear alarm, set prescaler to 32768, clear counter */ + writel(32768+AT91_RTT_RTTRST, &rtt->mr); + writel(~0, &rtt->ar); + writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); + /* wait for counter clear to happen, takes less than a 1/32768th second */ + while (readl(&rtt->vr) != 0) + ; + return 0; +} + +void rtc_reset (void) +{ + at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + + /* clear alarm, set prescaler to 32768, clear counter */ + writel(32768+AT91_RTT_RTTRST, &rtt->mr); + writel(~0, &rtt->ar); + writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); + /* wait for counter clear to happen, takes less than a 1/32768th second */ + while (readl(&rtt->vr) != 0) + ; +} + +#endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c731bfb594f..6d45a8ef554 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -36,7 +36,7 @@ COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o -COBJS-$(CONFIG_S5PC1XX) += serial_s5p.o +COBJS-$(CONFIG_S5P) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index e0d4e8004dd..77096643f1f 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -30,11 +30,7 @@ static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { u32 offset = dev_index * sizeof(struct s5p_uart); - - if (cpu_is_s5pc100()) - return (struct s5p_uart *)(S5PC100_UART_BASE + offset); - else - return (struct s5p_uart *)(S5PC110_UART_BASE + offset); + return (struct s5p_uart *)(samsung_get_base_uart() + offset); } /* @@ -67,11 +63,11 @@ void serial_setbrg_dev(const int dev_index) { DECLARE_GLOBAL_DATA_PTR; struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - u32 pclk = get_pclk(); + u32 uclk = get_uart_clk(dev_index); u32 baudrate = gd->baudrate; u32 val; - val = pclk / baudrate; + val = uclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); writew(udivslot[val % 16], &uart->udivslot); diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 317c0b41b6f..d0de9319684 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -43,7 +43,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, u32 csrx; void *regs; - if (cs > 3 || !spi_cs_is_valid(bus, cs)) + if (!spi_cs_is_valid(bus, cs)) return NULL; switch (bus) { @@ -168,8 +168,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * somewhat quirky, and it doesn't really buy us much anyway * in the context of U-Boot. */ - if (flags & SPI_XFER_BEGIN) + if (flags & SPI_XFER_BEGIN) { spi_cs_activate(slave); + /* + * sometimes the RDR is not empty when we get here, + * in theory that should not happen, but it DOES happen. + * Read it here to be on the safe side. + * That also clears the OVRES flag. Required if the + * following loop exits due to OVRES! + */ + spi_readl(as, RDR); + } for (len_tx = 0, len_rx = 0; len_rx < len; ) { status = spi_readl(as, SR); diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 7d84fc71a6e..4be82e73960 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_AMBA) += amba.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o +COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_SED156X) += sed156x.o diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c new file mode 100644 index 00000000000..3bdc1db61d6 --- /dev/null +++ b/drivers/video/mb86r0xgdc.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic + * controller. + */ + +#include <common.h> + +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice mb86r0x; + +static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, + u32 *videomem) +{ + struct ctfb_res_modes var_mode; + u32 dcm1, dcm2, dcm3; + u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; + u8 hsw, vsw; + u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; + u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; + unsigned long div; + int bpp; + u32 i; + + bpp = video_get_params(&var_mode, modestr); + + if (bpp == 0) { + var_mode.xres = 640; + var_mode.yres = 480; + var_mode.pixclock = 39721; /* 25MHz */ + var_mode.left_margin = 48; + var_mode.right_margin = 16; + var_mode.upper_margin = 33; + var_mode.lower_margin = 10; + var_mode.hsync_len = 96; + var_mode.vsync_len = 2; + var_mode.sync = 0; + var_mode.vmode = 0; + bpp = 15; + } + + /* Fill memory with white */ + for (i = 0; i < var_mode.xres * var_mode.yres / 2; i++) + *videomem++ = 0xFFFFFFFF; + + mb86r0x.winSizeX = var_mode.xres; + mb86r0x.winSizeY = var_mode.yres; + + /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ + div = 660000 / (1000000000L / var_mode.pixclock); + if (div > 64) + div = 64; + if (0 == div) + div = 1; + + dcm1 = (div - 1) << 8; + dcm2 = 0x00000000; + if (var_mode.sync & FB_SYNC_CLK_INV) + dcm3 = 0x00000100; + else + dcm3 = 0x00000000; + + htp = var_mode.left_margin + var_mode.xres + + var_mode.hsync_len + var_mode.right_margin; + hdp = var_mode.xres; + hdb = var_mode.xres; + hsp = var_mode.xres + var_mode.right_margin; + hsw = var_mode.hsync_len; + + vsw = var_mode.vsync_len; + vtr = var_mode.upper_margin + var_mode.yres + + var_mode.vsync_len + var_mode.lower_margin; + vsp = var_mode.yres + var_mode.lower_margin; + vdp = var_mode.yres; + + l2m = ((var_mode.yres - 1) << (0)) | + (((var_mode.xres * 2) / 64) << (16)) | + ((1) << (31)); + + l2em = (1 << 0) | (1 << 1); + + l2oa0 = mb86r0x.frameAdrs; + l2da0 = mb86r0x.frameAdrs; + l2oa1 = mb86r0x.frameAdrs; + l2da1 = mb86r0x.frameAdrs; + l2dx = 0; + l2dy = 0; + l2wx = 0; + l2wy = 0; + l2ww = var_mode.xres; + l2wh = var_mode.yres - 1; + + writel(dcm1, &dsp->dcm1); + writel(dcm2, &dsp->dcm2); + writel(dcm3, &dsp->dcm3); + + writew(htp, &dsp->htp); + writew(hdp, &dsp->hdp); + writew(hdb, &dsp->hdb); + writew(hsp, &dsp->hsp); + writeb(hsw, &dsp->hsw); + + writeb(vsw, &dsp->vsw); + writew(vtr, &dsp->vtr); + writew(vsp, &dsp->vsp); + writew(vdp, &dsp->vdp); + + writel(l2m, &dsp->l2m); + writel(l2em, &dsp->l2em); + writel(l2oa0, &dsp->l2oa0); + writel(l2da0, &dsp->l2da0); + writel(l2oa1, &dsp->l2oa1); + writel(l2da1, &dsp->l2da1); + writew(l2dx, &dsp->l2dx); + writew(l2dy, &dsp->l2dy); + writew(l2wx, &dsp->l2wx); + writew(l2wy, &dsp->l2wy); + writew(l2ww, &dsp->l2ww); + writew(l2wh, &dsp->l2wh); + + writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); +} + +void *video_hw_init(void) +{ + struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; + GraphicDevice *pGD = &mb86r0x; + char *s; + u32 *vid; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + vid = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) + dsp_init(&gdc->dsp0, s, vid); + + s = getenv("videomode1"); + if (s != NULL) + dsp_init(&gdc->dsp1, s, vid); + + return pGD; +} diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 4ed5514d302..83056b6fd0c 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -49,6 +49,9 @@ #define CONFIG_SYS_CLKDIV_PBA 2 #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index b258f2df439..6416d170919 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -73,6 +73,9 @@ */ #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 2ef255274f4..a4d9b0b9083 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -73,6 +73,9 @@ */ #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 195be82095f..06bb5da8a3f 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -73,6 +73,9 @@ */ #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index f93118edbc4..d3cbee6b634 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -73,6 +73,9 @@ */ #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 049298cfa36..9ef4523de42 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -1,5 +1,5 @@ /* - * CPUAT91 by (C) Copyright 2006 Eric Benard + * CPUAT91 by (C) Copyright 2006-2010 Eric Benard * eric@eukrea.com * * Configuration settings for the CPUAT91 board. @@ -23,15 +23,12 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY +#ifndef _CONFIG_CPUAT91_H +#define _CONFIG_CPUAT91_H #ifdef CONFIG_CPUAT91_RAM #define CONFIG_SKIP_LOWLEVEL_INIT 1 #define CONFIG_SKIP_RELOCATE_UBOOT 1 -#define CONFIG_CPUAT91 1 #else #define CONFIG_BOOTDELAY 1 #endif @@ -43,6 +40,7 @@ #define CONFIG_ARM920T 1 #define CONFIG_AT91RM9200 1 +#define CONFIG_CPUAT91 1 #undef CONFIG_USE_IRQ #define USE_920T_MMU 1 @@ -89,16 +87,36 @@ #undef CONFIG_USART0 #undef CONFIG_USART1 -#define CONFIG_HARD_I2C 1 +#undef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C 1 +#define AT91_PIN_SDA (1<<25) +#define AT91_PIN_SCL (1<<26) + +#define CONFIG_SYS_I2C_INIT_BOARD 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); +#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); +#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) +#define I2C_SDA(bit) \ + if (bit) \ + writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ + else \ + writel(AT91_PMX_AA_TWD, &pio->pioa.codr); +#define I2C_SCL(bit) \ + if (bit) \ + writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ + else \ + writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) -#if defined(CONFIG_HARD_I2C) -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#endif #define CONFIG_BOOTP_BOOTFILESIZE 1 #define CONFIG_BOOTP_BOOTPATH 1 @@ -117,10 +135,8 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NFS -#if defined(CONFIG_HARD_I2C) #define CONFIG_CMD_EEPROM 1 #define CONFIG_CMD_I2C 1 -#endif #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 @@ -148,6 +164,7 @@ #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #if defined(CONFIG_CMD_USB) #define CONFIG_USB_OHCI_NEW 1 @@ -206,7 +223,7 @@ "mtdparts=physmap-flash.0:" \ "128k(u-boot)ro," \ "128k(u-boot-env)," \ - "1408k(kernel)," \ + "1792k(kernel)," \ "-(rootfs)" #define CONFIG_BOOTARGS \ @@ -221,13 +238,13 @@ "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \ "10000000 ${filesize}\0" \ "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \ - "1019ffff; erase 10040000 1019ffff; cp.b 21000000 " \ + "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \ "10040000 ${filesize}\0" \ "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \ - "101a0000 10ffffff; erase 101a0000 10ffffff; cp.b " \ - "21000000 101A0000 ${filesize}\0" \ + "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \ + "21000000 10200000 ${filesize}\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "flashboot=run ramargs;bootm 10040000\0" \ "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ "bootm 21000000\0" -#endif /* __CONFIG_H */ +#endif /* _CONFIG_CPUAT91_H */ diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 739ff0d6271..1c381c76b85 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -70,6 +70,9 @@ */ #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 0c70af57425..8ca04ea4809 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -47,6 +47,9 @@ #define CONFIG_SYS_CLKDIV_PBA 2 #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h new file mode 100644 index 00000000000..29c534c4a9f --- /dev/null +++ b/include/configs/jadecpu.h @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * Configuation settings for the jadecpu board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MB86R0x +#define CONFIG_MB86R0x_IOCLK get_bus_freq(0) +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=mw.l 0x40000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ + "bootelf 0x40000000\0" \ + "" + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define BOARD_LATE_INIT 1 + +/* + * Compressions + */ +#define CONFIG_LZO + +/* + * Hardware drivers + */ + +/* + * Serial + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ +#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ +#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ +#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ + +#define CONFIG_CONS_INDEX 4 + +/* + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x02000000 +#define CONFIG_SMC911X_16_BIT + +/* + * Video + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB86R0xGDC +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) +#define VIDEO_FB_16BPP_WORD_SWAP +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG + +#define CONFIG_CMD_BMP 1 +#define CONFIG_CMD_CAN 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_ELF 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_USB 1 + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* USB */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "jade> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_PREBOOT "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" +#define CONFIG_AUTOBOOT_STOP_STR "stopgs" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +/* + * Clock reset generator init + */ +#define CONFIG_SYS_CRG_CRHA_INIT 0xffff +#define CONFIG_SYS_CRG_CRPA_INIT 0xffff +#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe +#define CONFIG_SYS_CRG_CRHB_INIT 0xffff +#define CONFIG_SYS_CRG_CRAM_INIT 0xffef + +/* + * Memory controller settings + */ +#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ +#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ +#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ +#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 +#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 +#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 +#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ +#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ +#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ + +/* + * DDR2 controller init settings + */ +#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 +#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 +#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 +#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f +#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 +#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ +#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 +#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 +#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 +#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 +#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 +#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 +#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 +#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 +#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F +#define CONFIG_SYS_DDR2_DROS_INIT 0x0001 + +/* + * DRAM init sequence + */ + +/* PALL Command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 +#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 + +/* EMR(2) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 +#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 + +/* EMR(3) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 +#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 + +/* EMR(1) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 +#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 + +/* MRS command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 +#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 + +/* PALL command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 +#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 + +/* REF command 1 */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f +#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 + +/* MRS command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 +#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 + +/* EMR(1) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 +#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 + +/* EMR(1) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 +#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index e085f4a47c5..dbb25314399 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009 + * (C) Copyright 2009-2010 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -31,13 +31,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* Common stuff */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_MEESC 1 /* Board is esd MEESC */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ @@ -85,11 +84,11 @@ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_USB #define CONFIG_CMD_PING 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 /* LED */ #define CONFIG_AT91_LED 1 @@ -121,9 +120,9 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 - +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ @@ -133,6 +132,17 @@ #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 36488b32cd2..6ed9e75bb46 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -51,6 +51,9 @@ #define CONFIG_SYS_CLKDIV_PBA 2 #define CONFIG_SYS_CLKDIV_PBB 1 +/* Reserve VM regions for SDRAM, NOR flash and FRAM */ +#define CONFIG_SYS_NR_VM_REGIONS 3 + /* * The PLLOPT register controls the PLL like this: * icp = PLLOPT<2> diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ae5a7919d87..71553f9a08c 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -158,6 +158,7 @@ /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ @@ -183,6 +184,7 @@ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ "console=ttyS2,115200n8\0" \ + "mpurate=500\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -191,6 +193,7 @@ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapfb.debug=y " \ @@ -198,6 +201,7 @@ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapfb.debug=y " \ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 3a3b389614c..a0e0f248b21 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -129,6 +129,7 @@ /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ @@ -153,6 +154,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ + "mpurate=500\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -161,6 +163,7 @@ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapfb.debug=y " \ @@ -168,6 +171,7 @@ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapfb.debug=y " \ diff --git a/include/configs/otc570.h b/include/configs/otc570.h index fb0f576f456..4a1cedec0fe 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -35,6 +35,7 @@ #define CONFIG_OTC570 1 /* Board is esd OTC570 */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index c8ea8fda82b..dc01ceb7b26 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -30,7 +30,7 @@ /* High Level Configuration Options */ #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 76a47c4456f..595d1740013 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -34,7 +34,7 @@ */ #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC100 1 /* which is in a S5PC100 */ #define CONFIG_SMDKC100 1 /* working with SMDKC100 */ diff --git a/include/mmc.h b/include/mmc.h index fcb237e81e4..9f94f423fbf 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -179,6 +179,16 @@ struct mmc_cid { char pnm[7]; }; +/* + * WARNING! + * + * This structure is used by atmel_mci.c only. + * It works for the AVR32 architecture but NOT + * for ARM/AT91 architectures. + * Its use is highly depreciated. + * After the atmel_mci.c driver for AVR32 has + * been replaced this structure will be removed. + */ struct mmc_csd { u8 csd_structure:2, @@ -275,7 +285,10 @@ int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); int board_mmc_getcd(u8 *cd, struct mmc *mmc); -#ifndef CONFIG_GENERIC_MMC +#ifdef CONFIG_GENERIC_MMC +int atmel_mci_init(void *regs); +#else int mmc_legacy_init(int verbose); #endif + #endif /* _MMC_H_ */ diff --git a/include/serial.h b/include/serial.h index 6513d8eeef9..15ab73c13d9 100644 --- a/include/serial.h +++ b/include/serial.h @@ -25,9 +25,9 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ - defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ - defined(CONFIG_SYS_SC520) + defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ + defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ + defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) @@ -52,7 +52,7 @@ extern struct serial_device s3c24xx_serial1_device; extern struct serial_device s3c24xx_serial2_device; #endif -#if defined(CONFIG_S5PC1XX) +#if defined(CONFIG_S5P) extern struct serial_device s5p_serial0_device; extern struct serial_device s5p_serial1_device; extern struct serial_device s5p_serial2_device; diff --git a/include/twl4030.h b/include/twl4030.h index 2b2f5ae6cde..930c285c26f 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -304,6 +304,17 @@ #define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0 #define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1 +/* Voltage Selection in PM Receiver Module */ +#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05 +#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03 +#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05 +#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 +#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 + +/* Device Selection in PM Receiver Module */ +#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20 +#define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0 + /* LED */ #define TWL4030_LED_LEDEN 0xEE #define TWL4030_LED_LEDEN_LEDAON (1 << 0) @@ -500,6 +511,9 @@ static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) /* For hardware resetting */ void twl4030_power_reset_init(void); +/* For setting device group and voltage */ +void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, + u8 dev_grp, u8 dev_grp_sel); /* For initializing power device */ void twl4030_power_init(void); /* For initializing mmc power */ diff --git a/tools/Makefile b/tools/Makefile index 749d9942309..b2e73b2ccc5 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -118,6 +118,9 @@ endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif +ifeq ($(VENDOR),syteco) +LOGO_BMP= logos/syteco.bmp +endif # now $(obj) is defined HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp Binary files differnew file mode 100644 index 00000000000..9a994fe3e38 --- /dev/null +++ b/tools/logos/syteco.bmp |
