diff options
40 files changed, 7559 insertions, 221 deletions
diff --git a/CHANGELOG b/CHANGELOG index cd057958fbb..7cc395603d3 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,15 @@ Changes for U-Boot 1.1.1: ====================================================================== +* Patches by Pantelis Antoniou, 30 Mar 2004: + - add auto-complete support to the U-Boot CLI + - add support for NETTA and NETPHONE boards; fix NETVIA board + +* Patch by Yuli Barcohen, 28 Mar 2004: + - Add support for MPC8272 family including MPC8247/8248/8271/8272 + - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) + - Change configuration method for MPC8260ADS family + * add startup code to clear the BSS of standalone applications * Fix if / elif handling bug in HUSH shell @@ -28,12 +28,18 @@ D: ERIC Support N: Pantelis Antoniou E: panto@intracom.gr -D: NETVIA board support, ARTOS support. +D: NETVIA & NETPHONE board support, ARTOS support. N: Pierre Aubert E: <p.aubert@staubli.com> D: Support for RPXClassic board +N: Yuli Barcohen +E: yuli@arabellasw.com +D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards. +D: Support for Zephyr Engineering ZPC.1900 board. +W: http://www.arabellasw.com + N: Jerry van Baren E: <vanbaren@cideas.com> D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. diff --git a/MAINTAINERS b/MAINTAINERS index 0a1b55a4b19..635aea3005c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27,6 +27,7 @@ Pantelis Antoniou <panto@intracom.gr> Yuli Barcohen <yuli@arabellasw.com> + MPC8260ADS MPC826x/MPC827x/MPC8280 ZPC1900 MPC8265 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> @@ -285,7 +286,6 @@ Unknown / orphaned boards: MOUSSE MPC824x - MPC8260ADS MPC8260 RPXsuper MPC8260 rsdproto MPC8260 @@ -48,7 +48,7 @@ LIST_8xx=" \ RPXClassic RPXlite RRvision SM850 \ SPD823TS svm_sc8xx SXNI855T TOP860 \ TQM823L TQM823L_LCD TQM850L TQM855L \ - TQM860L v37 \ + TQM860L v37 NETTA NETPHONE \ " ######################################################################### @@ -85,10 +85,10 @@ LIST_824x=" \ LIST_8260=" \ atc cogent_mpc8260 CPU86 ep8260 \ gw8260 hymod IPHASE4539 MPC8260ADS \ - MPC8266ADS PM826 PM828 ppmc8260 \ - RPXsuper rsdproto sacsng sbc8260 \ - SCM TQM8260_AC TQM8260_AD TQM8260_AE \ - ZPC1900 \ + MPC8266ADS MPC8272ADS PM826 PM828 \ + ppmc8260 PQ2FADS RPXsuper rsdproto \ + sacsng sbc8260 SCM TQM8260_AC \ + TQM8260_AD TQM8260_AE ZPC1900 \ " ######################################################################### @@ -398,6 +398,22 @@ NETVIA_config: unconfig } @./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia +NETPHONE_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx netphone + +xtract_NETTA = $(subst _ISDN,,$(subst _config,,$1)) + +NETTA_ISDN_config \ +NETTA_config: unconfig + @ >include/config.h + @[ -z "$(findstring NETTA_config,$@)" ] || \ + { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \ + } + @[ -z "$(findstring NETTA_ISDN_config,$@)" ] || \ + { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \ + } + @./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta + NX823_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx nx823 @@ -752,8 +768,23 @@ hymod_config: unconfig IPHASE4539_config: unconfig @./mkconfig $(@:_config=) ppc mpc8260 iphase4539 -MPC8260ADS_config: unconfig - @./mkconfig $(@:_config=) ppc mpc8260 mpc8260ads +MPC8260ADS_config \ +MPC8260ADS_33MHz_config \ +MPC8260ADS_40MHz_config \ +MPC8272ADS_config \ +PQ2FADS_config \ +PQ2FADS-VR_config \ +PQ2FADS-ZU_config \ +PQ2FADS-ZU_66MHz_config \ + : unconfig + $(if $(findstring PQ2FADS,$@), \ + @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \ + @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h) + $(if $(findstring MHz,$@), \ + @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \ + $(if $(findstring VR,$@), \ + @echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h)) + @./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads MPC8266ADS_config: unconfig @./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads @@ -280,7 +280,8 @@ The following options need to be configured: CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900, CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850, CONFIG_QS823, CONFIG_QS860T, CONFIG_DB64360, - CONFIG_DB64460, CONFIG_DUET_ADS + CONFIG_DB64460, CONFIG_DUET_ADS CONFIG_NETTA + CONFIG_NETPHONE ARM based boards: ----------------- @@ -320,7 +321,7 @@ The following options need to be configured: CFG_8260ADS - original MPC8260ADS CFG_8266ADS - MPC8266ADS CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR - + CFG_8272ADS - MPC8272ADS - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of @@ -1231,6 +1232,10 @@ The following options need to be configured: default value of 5 is used. - Command Interpreter: + CFG_AUTO_COMPLETE + + Enable auto completion of commands using TAB. + CFG_HUSH_PARSER Define this variable to enable the "hush" shell (from diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c index 67a75230ed1..fea9173cdd9 100644 --- a/board/mpc8260ads/mpc8260ads.c +++ b/board/mpc8260ads/mpc8260ads.c @@ -9,7 +9,7 @@ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com * Added support for the 16M dram simm on the 8260ads boards * - * (C) Copyright 2003 Arabella Software Ltd. + * (C) Copyright 2003-2004 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. * @@ -47,121 +47,137 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) + const iop_conf_t iop_conf_tab[4][32] = { /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */ + /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ }, /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ }, /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ +#if CONFIG_ADSTYPE == CFG_8272ADS + /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ + /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ +#else + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ +#if CONFIG_ADSTYPE == CFG_8272ADS + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ +#else + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ }, /* Port D */ { /* conf ppar psor pdir podr pdat */ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ @@ -198,19 +214,25 @@ void reset_phy (void) { vu_long *bcsr = (vu_long *)CFG_BCSR; - /* reset the FEC port */ - bcsr[1] &= ~FETH1_RST; + /* Reset the PHY */ +#if CFG_PHY_ADDR == 0 + bcsr[1] &= ~(FETHIEN1 | FETH1_RST); udelay(2); bcsr[1] |= FETH1_RST; +#else + bcsr[3] &= ~(FETHIEN2 | FETH2_RST); + udelay(2); + bcsr[3] |= FETH2_RST; +#endif /* CFG_PHY_ADDR == 0 */ udelay(1000); #ifdef CONFIG_MII -#if CONFIG_ADSTYPE == CFG_PQ2FADS +#if CONFIG_ADSTYPE >= CFG_PQ2FADS /* * Do not bypass Rx/Tx (de)scrambler (fix configuration error) * Enable autonegotiation. */ - miiphy_write(0, 16, 0x610); - miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write(CFG_PHY_ADDR, 16, 0x610); + miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); #else /* * Ethernet PHY is configured (by means of configuration pins) @@ -218,9 +240,9 @@ void reset_phy (void) * to advertise all capabilities, including 100Mb/s, and * restart autonegotiation. */ - miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */ - miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */ - miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */ + miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */ + miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #endif /* CONFIG_MII */ } @@ -229,7 +251,12 @@ int board_early_init_f (void) { vu_long *bcsr = (vu_long *)CFG_BCSR; - bcsr[1] = ~FETHIEN1 & ~RS232EN_1; +#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1) + bcsr[1] &= ~RS232EN_1; +#endif +#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1) + bcsr[1] &= ~RS232EN_2; +#endif #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */ #if CONFIG_ADSTYPE == CFG_PQ2FADS @@ -252,8 +279,10 @@ int board_early_init_f (void) long int initdram (int board_type) { -#if CONFIG_ADSTYPE == CFG_PQ2FADS +#if CONFIG_ADSTYPE == CFG_PQ2FADS long int msize = 32; +#elif CONFIG_ADSTYPE == CFG_8272ADS + long int msize = 64; #else long int msize = 16; #endif @@ -470,6 +499,8 @@ int checkboard (void) puts ("Board: Motorola MPC8266ADS\n"); #elif CONFIG_ADSTYPE == CFG_PQ2FADS puts ("Board: Motorola PQ2FADS-ZU\n"); +#elif CONFIG_ADSTYPE == CFG_8272ADS + puts ("Board: Motorola MPC8272ADS\n"); #else puts ("Board: unknown\n"); #endif diff --git a/board/netphone/Makefile b/board/netphone/Makefile new file mode 100644 index 00000000000..b3c1797e226 --- /dev/null +++ b/board/netphone/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o phone_console.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netphone/config.mk b/board/netphone/config.mk new file mode 100644 index 00000000000..8497ebc812b --- /dev/null +++ b/board/netphone/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# netVia Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/netphone/flash.c b/board/netphone/flash.c new file mode 100644 index 00000000000..a1c87f51310 --- /dev/null +++ b/board/netphone/flash.c @@ -0,0 +1,506 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_byte(flash_info_t * info, ulong dest, uchar data); +static void flash_get_offsets(ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_MX: + printf("MXIC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + short i; + uchar mid; + uchar pid; + vu_char *caddr = (vu_char *) addr; + ulong base = (ulong) addr; + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + mid = caddr[0]; + switch (mid) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (MX_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_MX; + break; + case (STM_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + pid = caddr[1]; /* device ID */ + switch (pid) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + + case (STM_ID_M29W040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf(" "); + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *) info->start[0]; + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0xF0; + + udelay(20000); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *) (info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer(0); + last = start; + addr = (vu_char *) (info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_char *) info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte(flash_info_t * info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c new file mode 100644 index 00000000000..f80ec66d966 --- /dev/null +++ b/board/netphone/netphone.c @@ -0,0 +1,620 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#include <common.h> +#include <miiphy.h> +#include <sed156x.h> + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#endif + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Intracom NetPhone\n"); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define A10_AAAA 0x00000000 +#define A10_AAA0 0x00200000 +#define A10_AAA1 0x00300000 +#define A10_000A 0x00800000 +#define A10_0000 0x00A00000 +#define A10_0001 0x00B00000 +#define A10_111A 0x00C00000 +#define A10_1110 0x00E00000 +#define A10_1111 0x00F00000 + +#define RAS_0000 0x00000000 +#define RAS_0001 0x00040000 +#define RAS_1110 0x00080000 +#define RAS_1111 0x000C0000 + +#define CAS_0000 0x00000000 +#define CAS_0001 0x00010000 +#define CAS_1110 0x00020000 +#define CAS_1111 0x00030000 + +#define WE_0000 0x00000000 +#define WE_0001 0x00004000 +#define WE_1110 0x00008000 +#define WE_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 8 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + + upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + { + u32 d1, d2; + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + +#if 0 + printf("check 0\n"); + check_ram(( 0 << 20), (2 << 20)); + printf("check 16\n"); + check_ram((16 << 20), (2 << 20)); + printf("check 32\n"); + check_ram((32 << 20), (2 << 20)); + printf("check 48\n"); + check_ram((48 << 20), (2 << 20)); +#endif + + if (size == 0) { + printf("SIZE is zero: LOOP on 0\n"); + for (;;) { + *(volatile u32 *)0 = 0; + (void)*(volatile u32 *)0; + } + } + + return size; +} + +/* ------------------------------------------------------------------------- */ + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + udelay(10000); + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + miiphy_read(phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK 0 +#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) +#define PA_SP_MASK 0 +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK _B(28) +#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) +#define PB_SP_MASK (_BR(22, 25)) +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) +#define PB_SP_DIRVAL 0 + +#define PC_GP_INMASK _BW(12) +#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) +#define PC_SP_MASK 0 +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL (_BW(10) | _BW(11)) +#define PC_SP_DIRVAL 0 + +#define PE_GP_INMASK _B(31) +#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) +#define PE_SP_MASK 0 +#define PE_ODR_VAL 0 +#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) +#define PE_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* NAND chip select */ + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + + /* DSP chip select */ + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + + /* External register chip select */ + memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); + memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); + + memctl->memc_br5 &= ~BR_V; + memctl->memc_br6 &= ~BR_V; + memctl->memc_br7 &= ~BR_V; + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + cpm->cp_pedat = PE_GP_OUTVAL; + cpm->cp_peodr = PE_ODR_VAL; + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; + cpm->cp_pepar = PE_SP_MASK; + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <linux/mtd/nand.h> + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen; + + totlen = nand_probe(CFG_NAND_BASE); + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + +static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ + +/* called from timer interrupt every 1/CFG_HZ sec */ +void board_show_activity(ulong timestamp) +{ + if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) + --left_to_poll; +} + +extern void phone_console_do_poll(void); + +static void do_poll(void) +{ + unsigned int base; + + while (left_to_poll <= 0) { + phone_console_do_poll(); + base = left_to_poll + PHONE_CONSOLE_POLL_HZ; + do { + left_to_poll = base; + } while (base != left_to_poll); + } +} + +/* called when looping */ +void show_activity(int arg) +{ + do_poll(); +} + +#endif + +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + /* printf("overwrite_console called\n"); */ + return 0; +} +#endif + +extern int drv_phone_init(void); +extern int drv_phone_use_me(void); + +int misc_init_r(void) +{ + return drv_phone_init(); +} + +int last_stage_init(void) +{ + int i; + + reset_phys(); + + /* check in order to enable the local console */ + left_to_poll = PHONE_CONSOLE_POLL_HZ; + i = CFG_HZ * 2; + while (i > 0) { + + if (tstc()) { + getc(); + break; + } + + do_poll(); + + if (drv_phone_use_me()) { + console_assign(stdin, "phone"); + console_assign(stdout, "phone"); + console_assign(stderr, "phone"); + setenv("bootdelay", "-1"); + break; + } + + udelay(1000000 / CFG_HZ); + i--; + left_to_poll--; + } + left_to_poll = PHONE_CONSOLE_POLL_HZ; + + return 0; +} diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c new file mode 100644 index 00000000000..0a7e6079722 --- /dev/null +++ b/board/netphone/phone_console.c @@ -0,0 +1,1122 @@ +/* + * (C) Copyright 2004 Intracom S.A. + * Pantelis Antoniou <panto@intracom.gr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * phone_console.c + * + * A phone based console + * + * Virtual display of 80x24 characters. + * The actual display is much smaller and panned to show the virtual one. + * Input is made by a numeric keypad utilizing the input method of + * mobile phones. Sorry no T9 lexicons... + * + */ + +#include <common.h> + +#include <version.h> +#include <linux/types.h> +#include <devices.h> + +#include <sed156x.h> + +/*************************************************************************************************/ + +#define ROWS 24 +#define COLS 80 + +#define REFRESH_HZ (CFG_HZ/50) /* refresh every 20ms */ +#define BLINK_HZ (CFG_HZ/2) /* cursor blink every 500ms */ + +/*************************************************************************************************/ + +#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat +#define DISPLAY_BACKLIT_MASK 0x0010 + +/*************************************************************************************************/ + +#define KP_STABLE_HZ (CFG_HZ/100) /* stable for 10ms */ +#define KP_REPEAT_DELAY_HZ (CFG_HZ/4) /* delay before repeat 250ms */ +#define KP_REPEAT_HZ (CFG_HZ/20) /* repeat every 50ms */ +#define KP_FORCE_DELAY_HZ (CFG_HZ/2) /* key was force pressed */ +#define KP_IDLE_DELAY_HZ (CFG_HZ/2) /* key was released and idle */ + +#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_RXD_MASK 0x0008 + +#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_TXD_MASK 0x0004 + +#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_CLK_MASK 0x0001 + +#define KP_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) +#define KP_CS_MASK 0x00000010 + +#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK) + +#define KP_SPI_TXD(x) \ + do { \ + if (x) \ + KP_SPI_TXD_PORT |= KP_SPI_TXD_MASK; \ + else \ + KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \ + } while(0) + +#define KP_SPI_CLK(x) \ + do { \ + if (x) \ + KP_SPI_CLK_PORT |= KP_SPI_CLK_MASK; \ + else \ + KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \ + } while(0) + +#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK) + +#define KP_SPI_BIT_DELAY() /* no delay */ + +#define KP_CS(x) \ + do { \ + if (x) \ + KP_CS_PORT |= KP_CS_MASK; \ + else \ + KP_CS_PORT &= ~KP_CS_MASK; \ + } while(0) + +#define KP_ROWS 7 +#define KP_COLS 4 + +#define KP_ROWS_MASK ((1 << KP_ROWS) - 1) +#define KP_COLS_MASK ((1 << KP_COLS) - 1) + +#define SCAN 0 +#define SCAN_FILTER 1 +#define SCAN_COL 2 +#define SCAN_COL_FILTER 3 +#define PRESSED 4 + +#define KP_F1 0 /* leftmost dot (tab) */ +#define KP_F2 1 /* middle left dot */ +#define KP_F3 2 /* up */ +#define KP_F4 3 /* middle right dot */ +#define KP_F5 4 /* rightmost dot */ +#define KP_F6 5 /* C */ +#define KP_F7 6 /* left */ +#define KP_F8 7 /* down */ +#define KP_F9 8 /* right */ +#define KP_F10 9 /* enter */ +#define KP_F11 10 /* R */ +#define KP_F12 11 /* save */ +#define KP_F13 12 /* redial */ +#define KP_F14 13 /* speaker */ +#define KP_F15 14 /* unused */ +#define KP_F16 15 /* unused */ + +#define KP_RELEASE -1 /* key depressed */ +#define KP_FORCE -2 /* key was pressed for more than force hz */ +#define KP_IDLE -3 /* key was released and idle */ + +#define KP_1 '1' +#define KP_2 '2' +#define KP_3 '3' +#define KP_4 '4' +#define KP_5 '5' +#define KP_6 '6' +#define KP_7 '7' +#define KP_8 '8' +#define KP_9 '9' +#define KP_0 '0' +#define KP_STAR '*' +#define KP_HASH '#' + +/*************************************************************************************************/ + +static int curs_disabled; +static int curs_col, curs_row; +static int disp_col, disp_row; + +static int width, height; + +/* the simulated vty buffer */ +static char vty_buf[ROWS * COLS]; +static char last_visible_buf[ROWS * COLS]; /* worst case */ +static char *last_visible_curs_ptr; +static int last_visible_curs_rev; +static int blinked_state; +static int last_input_mode; +static int refresh_time; +static int blink_time; +static char last_fast_punct; +static int last_tab_indicator = -1; + +/*************************************************************************************************/ + +#define IM_SMALL 0 +#define IM_CAPITAL 1 +#define IM_NUMBER 2 + +static int input_mode; +static char fast_punct; +static int tab_indicator; +static const char *fast_punct_list = ",.:;*"; + +static const char *input_mode_txt[] = { "abc", "ABC", "123" }; + +static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|"; +static const char *whspace = " 0\n"; +/* per mode character select (for 2-9) */ +static const char *digits_sel[2][8] = { + { /* small */ + "abc2", /* 2 */ + "def3", /* 3 */ + "ghi4", /* 4 */ + "jkl5", /* 5 */ + "mno6", /* 6 */ + "pqrs7", /* 7 */ + "tuv8", /* 8 */ + "wxyz9", /* 9 */ + }, { /* capital */ + "ABC2", /* 2 */ + "DEF3", /* 3 */ + "GHI4", /* 4 */ + "JKL5", /* 5 */ + "MNO6", /* 6 */ + "PQRS7", /* 7 */ + "TUV8", /* 8 */ + "WXYZ9", /* 9 */ + } +}; + +/*****************************************************************************/ + +static void update(void); +static void ensure_visible(int col, int row, int dx, int dy); + +static void console_init(void) +{ + curs_disabled = 0; + curs_col = 0; + curs_row = 0; + + disp_col = 0; + disp_row = 0; + + input_mode = IM_SMALL; + fast_punct = ','; + last_fast_punct = '\0'; + refresh_time = REFRESH_HZ; + blink_time = BLINK_HZ; + + tab_indicator = 1; + + memset(vty_buf, ' ', sizeof(vty_buf)); + + memset(last_visible_buf, ' ', sizeof(last_visible_buf)); + last_visible_curs_ptr = NULL; + last_input_mode = -1; + last_visible_curs_rev = 0; + + blinked_state = 0; + + sed156x_init(); + width = sed156x_text_width; + height = sed156x_text_height - 1; +} + +/*****************************************************************************/ + +void phone_putc(const char c); + +/*****************************************************************************/ + +static int queued_char = -1; +static int enabled = 0; + +/*****************************************************************************/ + +/* flush buffers */ +int phone_start(void) +{ + console_init(); + + update(); + sed156x_sync(); + + enabled = 1; + queued_char = 'U' - '@'; + + /* backlit on */ + DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK; + + return 0; +} + +int phone_stop(void) +{ + enabled = 0; + + sed156x_clear(); + sed156x_sync(); + + /* backlit off */ + DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK; + + return 0; +} + +void phone_puts(const char *s) +{ + int count = strlen(s); + + while (count--) + phone_putc(*s++); +} + +int phone_tstc(void) +{ + return queued_char >= 0 ? 1 : 0; +} + +int phone_getc(void) +{ + int r; + + if (queued_char < 0) + return -1; + + r = queued_char; + queued_char = -1; + + return r; +} + +/*****************************************************************************/ + +int drv_phone_init(void) +{ + device_t console_dev; + char *penv; + + /* + * Force console i/o to serial ? + */ + if ((penv = getenv("console")) != NULL && strcmp(penv, "serial") == 0) + return 0; + + console_init(); + + memset(&console_dev, 0, sizeof(console_dev)); + strcpy(console_dev.name, "phone"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + console_dev.start = phone_start; + console_dev.stop = phone_stop; + console_dev.putc = phone_putc; /* 'putc' function */ + console_dev.puts = phone_puts; /* 'puts' function */ + console_dev.tstc = phone_tstc; /* 'tstc' function */ + console_dev.getc = phone_getc; /* 'getc' function */ + + if (device_register(&console_dev) == 0) + return 1; + + return 0; +} + +static int use_me; + +int drv_phone_use_me(void) +{ + return use_me; +} + +static void kp_do_poll(void); + +void phone_console_do_poll(void) +{ + int i, x, y; + + kp_do_poll(); + + if (enabled) { + /* do the blink */ + blink_time -= PHONE_CONSOLE_POLL_HZ; + if (blink_time <= 0) { + blink_time += BLINK_HZ; + if (last_visible_curs_ptr) { + i = last_visible_curs_ptr - last_visible_buf; + x = i % width; y = i / width; + sed156x_reverse_at(x, y, 1); + last_visible_curs_rev ^= 1; + } + } + + /* do the refresh */ + refresh_time -= PHONE_CONSOLE_POLL_HZ; + if (refresh_time <= 0) { + refresh_time += REFRESH_HZ; + sed156x_sync(); + } + } + +} + +static int last_scancode = -1; +static int forced_scancode = 0; +static int input_state = -1; +static int input_scancode = -1; +static int input_selected_char = -1; +static char input_covered_char; + +static void putchar_at_cursor(char c) +{ + vty_buf[curs_row * COLS + curs_col] = c; + ensure_visible(curs_col, curs_row, 1, 1); +} + +static char getchar_at_cursor(void) +{ + return vty_buf[curs_row * COLS + curs_col]; +} + +static void queue_input_char(char c) +{ + if (c <= 0) + return; + + queued_char = c; +} + +static void terminate_input(void) +{ + if (input_state < 0) + return; + + if (input_selected_char >= 0) + queue_input_char(input_selected_char); + + input_state = -1; + input_selected_char = -1; + putchar_at_cursor(input_covered_char); + + curs_disabled = 0; + blink_time = BLINK_HZ; + update(); +} + +static void handle_enabled_scancode(int scancode) +{ + char c; + int new_disp_col, new_disp_row; + const char *sel; + + + switch (scancode) { + + /* key was released */ + case KP_RELEASE: + forced_scancode = 0; + break; + + /* key was forced */ + case KP_FORCE: + + switch (last_scancode) { + case '#': + if (input_mode == IM_NUMBER) { + input_mode = IM_CAPITAL; + /* queue backspace to erase # */ + queue_input_char('\b'); + } else { + input_mode = IM_NUMBER; + fast_punct = '*'; + } + update(); + break; + + case '0': case '1': + case '2': case '3': case '4': case '5': + case '6': case '7': case '8': case '9': + + if (input_state < 0) + break; + + input_selected_char = last_scancode; + putchar_at_cursor((char)input_selected_char); + terminate_input(); + + break; + + default: + break; + } + + break; + + /* release and idle */ + case KP_IDLE: + input_scancode = -1; + if (input_state < 0) + break; + terminate_input(); + break; + + /* change input mode */ + case '#': + if (last_scancode == '#') /* no repeat */ + break; + + if (input_mode == IM_NUMBER) { + input_scancode = scancode; + input_state = 0; + input_selected_char = scancode; + input_covered_char = getchar_at_cursor(); + putchar_at_cursor((char)input_selected_char); + terminate_input(); + break; + } + + if (input_mode == IM_SMALL) + input_mode = IM_CAPITAL; + else + input_mode = IM_SMALL; + + update(); + break; + + case '*': + /* no repeat */ + if (last_scancode == scancode) + break; + + if (input_state >= 0) + terminate_input(); + + input_scancode = fast_punct; + input_state = 0; + input_selected_char = input_scancode; + input_covered_char = getchar_at_cursor(); + putchar_at_cursor((char)input_selected_char); + terminate_input(); + + break; + + case '0': case '1': + case '2': case '3': case '4': case '5': + case '6': case '7': case '8': case '9': + + /* no repeat */ + if (last_scancode == scancode) + break; + + if (input_mode == IM_NUMBER) { + input_scancode = scancode; + input_state = 0; + input_selected_char = scancode; + input_covered_char = getchar_at_cursor(); + putchar_at_cursor((char)input_selected_char); + terminate_input(); + break; + } + + if (input_state >= 0 && input_scancode != scancode) + terminate_input(); + + if (input_state < 0) { + curs_disabled = 1; + input_scancode = scancode; + input_state = 0; + input_covered_char = getchar_at_cursor(); + } else + input_state++; + + if (scancode == '0') + sel = whspace; + else if (scancode == '1') + sel = punct; + else + sel = digits_sel[input_mode][scancode - '2']; + c = *(sel + input_state); + if (c == '\0') { + input_state = 0; + c = *sel; + } + + input_selected_char = (int)c; + putchar_at_cursor((char)input_selected_char); + update(); + + break; + + /* move visible display */ + case KP_F3: case KP_F8: case KP_F7: case KP_F9: + + new_disp_col = disp_col; + new_disp_row = disp_row; + + switch (scancode) { + /* up */ + case KP_F3: + if (new_disp_row <= 0) + break; + new_disp_row--; + break; + + /* down */ + case KP_F8: + if (new_disp_row >= ROWS - height) + break; + new_disp_row++; + break; + + /* left */ + case KP_F7: + if (new_disp_col <= 0) + break; + new_disp_col--; + break; + + /* right */ + case KP_F9: + if (new_disp_col >= COLS - width) + break; + new_disp_col++; + break; + } + + /* no change? */ + if (disp_col == new_disp_col && disp_row == new_disp_row) + break; + + disp_col = new_disp_col; + disp_row = new_disp_row; + update(); + + break; + + case KP_F6: /* backspace */ + /* inputing something; no backspace sent, just cancel input */ + if (input_state >= 0) { + input_selected_char = -1; /* cancel */ + terminate_input(); + break; + } + queue_input_char('\b'); + break; + + case KP_F10: /* enter */ + /* inputing something; first cancel input */ + if (input_state >= 0) + terminate_input(); + queue_input_char('\r'); + break; + + case KP_F11: /* R -> Ctrl-C (abort) */ + if (input_state >= 0) + terminate_input(); + queue_input_char('C' - 'Q'); /* ctrl-c */ + break; + + case KP_F5: /* F% -> Ctrl-U (clear line) */ + if (input_state >= 0) + terminate_input(); + queue_input_char('U' - 'Q'); /* ctrl-c */ + break; + + + case KP_F1: /* tab */ + /* inputing something; first cancel input */ + if (input_state >= 0) + terminate_input(); + queue_input_char('\t'); + break; + + case KP_F2: /* change fast punct */ + sel = strchr(fast_punct_list, fast_punct); + if (sel == NULL) + sel = &fast_punct_list[0]; + sel++; + if (*sel == '\0') + sel = &fast_punct_list[0]; + fast_punct = *sel; + update(); + break; + + + } + + if (scancode != KP_FORCE && scancode != KP_IDLE) /* don't record forced or idle scancode */ + last_scancode = scancode; +} + +static void scancode_action(int scancode) +{ +#if 0 + if (scancode == KP_RELEASE) + printf(" RELEASE\n"); + else if (scancode == KP_FORCE) + printf(" FORCE\n"); + else if (scancode == KP_IDLE) + printf(" IDLE\n"); + else if (scancode < 32) + printf(" F%d", scancode + 1); + else + printf(" %c", (char)scancode); + printf("\n"); +#endif + + if (enabled) { + handle_enabled_scancode(scancode); + return; + } + + if (scancode == KP_FORCE && last_scancode == '*') + use_me = 1; + + last_scancode = scancode; +} + +/**************************************************************************************/ + +/* update the display; make sure to update only the differences */ +static void update(void) +{ + int i; + char *s, *e, *t, *r, *b, *cp; + + if (input_mode != last_input_mode) + sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3); + + if (tab_indicator != last_tab_indicator) + sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2); + + if (fast_punct != last_fast_punct) + sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1); + + if (curs_disabled || + curs_col < disp_col || curs_col >= (disp_col + width) || + curs_row < disp_row || curs_row >= (disp_row + height)) { + cp = NULL; + } else + cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col); + + + /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */ + + /* clear previous cursor */ + if (last_visible_curs_ptr && last_visible_curs_rev == 0) { + i = last_visible_curs_ptr - last_visible_buf; + sed156x_reverse_at(i % width, i / width, 1); + } + + b = vty_buf + disp_row * COLS + disp_col; + t = last_visible_buf; + for (i = 0; i < height; i++) { + s = b; + e = b + width; + /* update only the differences */ + do { + while (s < e && *s == *t) { + s++; + t++; + } + if (s == e) /* no more */ + break; + + /* find run */ + r = s; + while (s < e && *s != *t) + *t++ = *s++; + + /* and update */ + sed156x_output_at(r - b, i, r, s - r); + + } while (s < e); + + b += COLS; + } + + /* set cursor */ + if (cp) { + last_visible_curs_ptr = cp; + i = last_visible_curs_ptr - last_visible_buf; + sed156x_reverse_at(i % width, i / width, 1); + last_visible_curs_rev = 0; + } else { + last_visible_curs_ptr = NULL; + } + + last_input_mode = input_mode; + last_fast_punct = fast_punct; + last_tab_indicator = tab_indicator; +} + +/* ensure visibility; the trick is to minimize the screen movement */ +static void ensure_visible(int col, int row, int dx, int dy) +{ + int x1, y1, x2, y2, a1, b1, a2, b2; + + /* clamp visible region */ + if (col < 0) { + dx -= col; + col = 0; + if (dx <= 0) + dx = 1; + } + + if (row < 0) { + dy -= row; + row = 0; + if (dy <= 0) + dy = 1; + } + + if (col + dx > COLS) + dx = COLS - col; + + if (row + dy > ROWS) + dy = ROWS - row; + + + /* move to easier to use vars */ + x1 = disp_col; y1 = disp_row; + x2 = x1 + width; y2 = y1 + height; + a1 = col; b1 = row; + a2 = a1 + dx; b2 = b1 + dy; + + /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ + + if (a2 > x2) { + /* move to the right */ + x2 = a2; + x1 = x2 - width; + if (x1 < 0) { + x1 = 0; + x2 = width; + } + } else if (a1 < x1) { + /* move to the left */ + x1 = a1; + x2 = x1 + width; + if (x2 > COLS) { + x2 = COLS; + x1 = x2 - width; + } + } + + if (b2 > y2) { + /* move down */ + y2 = b2; + y1 = y2 - height; + if (y1 < 0) { + y1 = 0; + y2 = height; + } + } else if (b1 < y1) { + /* move up */ + y1 = b1; + y2 = y1 + width; + if (y2 > ROWS) { + y2 = ROWS; + y1 = y2 - height; + } + } + + /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ + + /* no movement? */ + if (disp_col == x1 && disp_row == y1) + return; + + disp_col = x1; + disp_row = y1; +} + +/**************************************************************************************/ + +static void newline(void) +{ + curs_col = 0; + if (curs_row + 1 < ROWS) + curs_row++; + else { + memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1)); + memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS); + } +} + +void phone_putc(const char c) +{ + int i; + + if (input_mode != -1) { + input_selected_char = -1; + terminate_input(); + } + + curs_disabled = 1; + update(); + + blink_time = BLINK_HZ; + + switch (c) { + case 13: /* ignore */ + break; + + case '\n': /* next line */ + newline(); + ensure_visible(curs_col, curs_row, 1, 1); + break; + + case 9: /* tab 8 */ + /* move to tab */ + i = curs_col; + i |= 0x0008; + i &= ~0x0007; + + if (i < COLS) + curs_col = i; + else + newline(); + + ensure_visible(curs_col, curs_row, 1, 1); + break; + + case 8: /* backspace */ + if (curs_col <= 0) + break; + curs_col--; + + /* make sure that we see a couple of characters before */ + if (curs_col > 4) + ensure_visible(curs_col - 4, curs_row, 4, 1); + else + ensure_visible(curs_col, curs_row, 1, 1); + + break; + + default: /* draw the char */ + putchar_at_cursor(c); + + /* + * check for newline + */ + if (curs_col + 1 < COLS) + curs_col++; + else + newline(); + + ensure_visible(curs_col, curs_row, 1, 1); + + break; + } + + curs_disabled = 0; + blink_time = BLINK_HZ; + update(); +} + +/**************************************************************************************/ + +static inline unsigned int kp_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + KP_SPI_TXD(val & 0x80); + val <<= 1; + KP_SPI_CLK_TOGGLE(); + KP_SPI_BIT_DELAY(); + rx <<= 1; + if (KP_SPI_RXD()) + rx |= 1; + KP_SPI_CLK_TOGGLE(); + KP_SPI_BIT_DELAY(); + } + + return rx; +} + +unsigned int kp_data_transfer(unsigned int val) +{ + KP_SPI_CLK(1); + KP_CS(0); + val = kp_transfer(val); + KP_CS(1); + + return val; +} + +unsigned int kp_get_col_mask(unsigned int row_mask) +{ + unsigned int val, col_mask; + + val = 0x80 | (row_mask & 0x7F); + (void)kp_data_transfer(val); + col_mask = kp_data_transfer(val) & 0x0F; + + /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */ + return col_mask; +} + +/**************************************************************************************/ + +static const int kp_scancodes[KP_ROWS * KP_COLS] = { + KP_F1, KP_F3, KP_F4, KP_F2, + KP_F6, KP_F8, KP_F9, KP_F7, + KP_1, KP_3, KP_F11, KP_2, + KP_4, KP_6, KP_F12, KP_5, + KP_7, KP_9, KP_F13, KP_8, + KP_STAR, KP_HASH, KP_F14, KP_0, + KP_F5, KP_F15, KP_F16, KP_F10, +}; + +static const int kp_repeats[KP_ROWS * KP_COLS] = { + 0, 1, 0, 0, + 0, 1, 1, 1, + 1, 1, 0, 1, + 1, 1, 0, 1, + 1, 1, 0, 1, + 1, 1, 0, 1, + 0, 0, 0, 1, +}; + +static int kp_state = SCAN; +static int kp_last_col_mask; +static int kp_cur_row, kp_cur_col; +static int kp_scancode; +static int kp_stable; +static int kp_repeat; +static int kp_repeat_time; +static int kp_force_time; +static int kp_idle_time; + +static void kp_do_poll(void) +{ + unsigned int col_mask; + int col; + + switch (kp_state) { + case SCAN: + if (kp_idle_time > 0) { + kp_idle_time -= PHONE_CONSOLE_POLL_HZ; + if (kp_idle_time <= 0) + scancode_action(KP_IDLE); + } + + col_mask = kp_get_col_mask(KP_ROWS_MASK); + if (col_mask == KP_COLS_MASK) + break; /* nothing */ + kp_last_col_mask = col_mask; + kp_stable = 0; + kp_state = SCAN_FILTER; + break; + + case SCAN_FILTER: + col_mask = kp_get_col_mask(KP_ROWS_MASK); + if (col_mask != kp_last_col_mask) { + kp_state = SCAN; + break; + } + + kp_stable += PHONE_CONSOLE_POLL_HZ; + if (kp_stable < KP_STABLE_HZ) + break; + + kp_cur_row = 0; + kp_stable = 0; + kp_state = SCAN_COL; + + (void)kp_get_col_mask(1 << kp_cur_row); + break; + + case SCAN_COL: + col_mask = kp_get_col_mask(1 << kp_cur_row); + if (col_mask == KP_COLS_MASK) { + if (++kp_cur_row >= KP_ROWS) { + kp_state = SCAN; + break; + } + kp_get_col_mask(1 << kp_cur_row); + break; + } + kp_last_col_mask = col_mask; + kp_stable = 0; + kp_state = SCAN_COL_FILTER; + break; + + case SCAN_COL_FILTER: + col_mask = kp_get_col_mask(1 << kp_cur_row); + if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) { + kp_state = SCAN; + break; + } + + kp_stable += PHONE_CONSOLE_POLL_HZ; + if (kp_stable < KP_STABLE_HZ) + break; + + for (col = 0; col < KP_COLS; col++) + if ((col_mask & (1 << col)) == 0) + break; + kp_cur_col = col; + kp_state = PRESSED; + kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col]; + kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col]; + + if (kp_repeat) + kp_repeat_time = KP_REPEAT_DELAY_HZ; + kp_force_time = KP_FORCE_DELAY_HZ; + + scancode_action(kp_scancode); + + break; + + case PRESSED: + col_mask = kp_get_col_mask(1 << kp_cur_row); + if (col_mask != kp_last_col_mask) { + kp_state = SCAN; + scancode_action(KP_RELEASE); + kp_idle_time = KP_IDLE_DELAY_HZ; + break; + } + + if (kp_repeat) { + kp_repeat_time -= PHONE_CONSOLE_POLL_HZ; + if (kp_repeat_time <= 0) { + kp_repeat_time += KP_REPEAT_HZ; + scancode_action(kp_scancode); + } + } + + if (kp_force_time > 0) { + kp_force_time -= PHONE_CONSOLE_POLL_HZ; + if (kp_force_time <= 0) + scancode_action(KP_FORCE); + } + + break; + } +} diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds new file mode 100644 index 00000000000..c3dac0ef4a5 --- /dev/null +++ b/board/netphone/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug new file mode 100644 index 00000000000..21b7e6aabc0 --- /dev/null +++ b/board/netphone/u-boot.lds.debug @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netta/Makefile b/board/netta/Makefile new file mode 100644 index 00000000000..c89e4c58f13 --- /dev/null +++ b/board/netta/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o dsp.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netta/config.mk b/board/netta/config.mk new file mode 100644 index 00000000000..8497ebc812b --- /dev/null +++ b/board/netta/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# netVia Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/netta/dsp.c b/board/netta/dsp.c new file mode 100644 index 00000000000..2bea3adeae3 --- /dev/null +++ b/board/netta/dsp.c @@ -0,0 +1,1031 @@ +/* + * Intracom TI6711 DSP + */ + +#include <common.h> +#include <post.h> + +#include "mpc8xx.h" + +struct ram_range { + u32 start; + u32 size; +}; + +static const struct ram_range int_ram[] = { + { 0x00000000U, 0x00010000U }, +}; + +static const struct ram_range ext_ram[] = { + { 0x80000000U, 0x00100000U }, +}; + +static const struct ram_range ranges[] = { + { 0x00000000U, 0x00010000U }, + { 0x80000000U, 0x00100000U }, +}; + +/*******************************************************************************************************/ + +static inline int addr_in_int_ram(u32 addr) +{ + int i; + + for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++) + if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size) + return 1; + + return 0; +} + +static inline int addr_in_ext_ram(u32 addr) +{ + int i; + + for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++) + if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size) + return 1; + + return 0; +} + +/*******************************************************************************************************/ + +#define DSP_HPIC 0x0 +#define DSP_HPIA 0x4 +#define DSP_HPID1 0x8 +#define DSP_HPID2 0xC + +static u32 dummy_delay; +static volatile u32 *ti6711_delay = &dummy_delay; + +static inline void dsp_go_slow(void) +{ + volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; + + memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX; + memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX; + + ti6711_delay = (u32 *)DUMMY_BASE; +} + +static inline void dsp_go_fast(void) +{ + volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; + + memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK; + memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; + + ti6711_delay = &dummy_delay; +} + +/*******************************************************************************************************/ + +static inline void dsp_delay(void) +{ + /* perform ti6711_delay chip select read to have a small delay */ + (void) *(volatile u32 *)ti6711_delay; +} + +static inline u16 dsp_read_hpic(void) +{ + return *((volatile u16 *)DSP_BASE); +} + +static inline void dsp_write_hpic(u16 val) +{ + *((volatile u16 *)DSP_BASE) = val; +} + +static inline void dsp_reset(void) +{ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); + udelay(250); + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); + udelay(250); +} + +static inline void dsp_init_hpic(void) +{ + int i; + volatile u16 *p; + + dsp_go_slow(); + + i = 0; + while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { + dsp_delay(); + i++; + } + dsp_delay(); + + /* write control register */ + p = (volatile u16 *)DSP_BASE; + p[0] = 0x0000; + dsp_delay(); + p[1] = 0x0000; + dsp_delay(); + + dsp_go_fast(); +} + +static inline void dsp_wait_hrdy(void) +{ + int i; + + i = 0; + while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { + dsp_delay(); + i++; + } +} + +static inline u32 dsp_read_hpic_word(u32 addr) +{ + u32 val; + volatile u16 *p; + + p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); + + val = ((u32) p[0] << 16); + dsp_delay(); + + val |= p[1]; + dsp_delay(); + + return val; +} + +static inline u16 dsp_read_hpic_hi_hword(u32 addr) +{ + return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr); +} + +static inline u16 dsp_read_hpic_lo_hword(u32 addr) +{ + return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2); +} + +static inline void dsp_write_hpic_word(u32 addr, u32 val) +{ + volatile u16 *p; + + p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); + p[0] = (u16)(val >> 16); + dsp_delay(); + + p[1] = (u16)val; + dsp_delay(); +} + +static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h) +{ + *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h; +} + +static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l) +{ + *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l; +} + +/********************************************************************/ + +static inline void c62_write_word(u32 addr, u32 val) +{ + dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); + dsp_delay(); + dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); + dsp_delay(); + + dsp_wait_hrdy(); + dsp_delay(); + + dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16)); + dsp_delay(); + + dsp_wait_hrdy(); + dsp_delay(); + + dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val); + dsp_delay(); +} + +static u32 c62_read_word(u32 addr) +{ + u32 val; + + dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); + dsp_delay(); + dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); + dsp_delay(); + + /* FETCH */ + dsp_write_hpic(0x10); + dsp_delay(); + + dsp_wait_hrdy(); + dsp_delay(); + + val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16; + dsp_delay(); + + dsp_wait_hrdy(); + dsp_delay(); + + val |= dsp_read_hpic_lo_hword(DSP_HPID2); + dsp_delay(); + + return val; +} + +static inline void c62_read(u32 addr, u32 *buffer, int numdata) +{ + int i; + + if (numdata <= 0) + return; + + for (i = 0; i < numdata; i++) { + *buffer++ = c62_read_word(addr); + addr += 4; + } +} + +static inline u32 c62_checksum(u32 addr, int numdata) +{ + int i; + u32 chksum; + + chksum = 0; + for (i = 0; i < numdata; i++) { + chksum += c62_read_word(addr); + addr += 4; + } + + return chksum; +} + +static inline void c62_write(u32 addr, const u32 *buffer, int numdata) +{ + int i; + + if (numdata <= 0) + return; + + for (i = 0; i < numdata; i++) { + c62_write_word(addr, *buffer++); + addr += 4; + } +} + +static inline int c62_write_word_validated(u32 addr, u32 val) +{ + c62_write_word(addr, val); + return c62_read_word(addr) == val ? 0 : -1; +} + +static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata) +{ + int i, r; + + if (numdata <= 0) + return 0; + + for (i = 0; i < numdata; i++) { + r = c62_write_word_validated(addr, *buffer++); + if (r < 0) + return r; + addr += 4; + } + return 0; +} + +/***********************************************************************************************************/ + +static const u8 bootstrap_rbin[5084] = { + 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, + 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 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0x0f, 0xff, 0xfa, 0x90, + 0x00, 0x00, 0x80, 0x00, 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, + 0x01, 0x80, 0x00, 0xf8, 0x01, 0x90, 0x02, 0xf4, 0x02, 0x60, 0x80, 0x2a, + 0x02, 0x00, 0xdb, 0xeb, 0x02, 0x00, 0x04, 0x28, 0x02, 0x10, 0x02, 0xf4, + 0x02, 0x00, 0x22, 0x66, 0x02, 0x60, 0x88, 0x28, 0x02, 0x00, 0xdb, 0xe8, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, 0x02, 0x80, 0x42, 0x66, + 0x02, 0x60, 0x8a, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0xc2, 0x66, 0x02, 0x60, 0x92, 0x28, + 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, + 0x02, 0x80, 0x62, 0x66, 0x02, 0x60, 0x8c, 0x2a, 0x02, 0x00, 0xdb, 0xea, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x82, 0x66, + 0x02, 0x60, 0x8e, 0x28, 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x10, 0x02, 0x76, 0x00, 0x00, 0xa2, 0x64, 0x02, 0x60, 0x90, 0x2a, + 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x02, 0xf4, + 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x01, 0x90, 0x02, 0xf4, + 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, 0x00, 0x00, 0x00, 0xa8, + 0x00, 0x10, 0x02, 0xf4, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19, 0x2a, 0x2a, + 0x02, 0x84, 0x20, 0xfb, 0x02, 0x00, 0x00, 0x6a, 0x02, 0x90, 0x02, 0xf6, + 0x02, 0x98, 0xe0, 0x2a, 0x02, 0x19, 0x2c, 0x2a, 0x02, 0x00, 0x00, 0x6b, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a, + 0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa, + 0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68, + 0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12, + 0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65, + 0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79, + 0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59, + 0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64, + 0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78, + 0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a, + 0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41, + 0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4, + 0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa, + 0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, + 0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6, + 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, + 0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static int load_bootstrap(void) +{ + const u8 *s = bootstrap_rbin; + u32 l = sizeof(bootstrap_rbin); + const u8 *data, *hdr, *h; + u32 chksum, chksum2; + int i, j, rangenr; + u32 start, length; + + if (l < 12) { + printf("bootstrap image corrupted. (too short header)\n"); + return -1; + } + + chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7]; + rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11]; + s += 12; l -= 12; + + hdr = s; + s += 8 * rangenr; l -= 8 * rangenr; + data = s; + + /* validate bootstrap image */ + h = hdr; s = data; chksum2 = 0; + for (i = 0; i < rangenr; i++) { + start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; + length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; + h += 8; + + /* too short */ + if (l < length) { + printf("bootstrap image corrupted. (too short data)\n"); + return -1; + } + l -= length; + + j = (int)length / 4; + while (j-- > 0) { + chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3]; + s += 4; + } + } + + /* checksum must match */ + if (chksum != chksum2) { + printf("bootstrap image corrupted. (checksum error)\n"); + return -1; + } + + /* nothing must be left */ + if (l != 0) { + printf("bootstrap image corrupted. (garbage at the end)\n"); + return -1; + } + + /* write the image */ + h = hdr; + s = data; + for (i = 0; i < rangenr; i++) { + start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; + length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; + h += 8; + c62_write(start, (u32 *)s, length / 4); + s += length; + } + + /* and now validate checksum */ + h = hdr; + s = data; + chksum2 = 0; + for (i = 0; i < rangenr; i++) { + start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; + length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; + h += 8; + chksum2 += c62_checksum(start, length / 4); + s += length; + } + + /* checksum must match */ + if (chksum != chksum2) { + printf("bootstrap in DSP memory is corrupted\n"); + return -1; + } + + return 0; +} + +struct host_init { + u32 master_mode; + struct { + u8 port_id; + u8 slot_id; + } ch_serial_map[32]; + u32 clk_divider[2]; + /* pll */ + u32 initmode; + u32 pllm; + u32 div[4]; + u32 oscdiv1; + u32 unused[10]; +}; + +const struct host_init hi_default = { + .master_mode = +#if !defined(CONFIG_NETTA_ISDN) + -1, +#else + 0, +#endif + + .ch_serial_map = { + [ 0] = { .port_id = 2, .slot_id = 16 }, + [ 1] = { .port_id = 2, .slot_id = 17 }, + [ 2] = { .port_id = 2, .slot_id = 18 }, + [ 3] = { .port_id = 2, .slot_id = 19 }, + [ 4] = { .port_id = 2, .slot_id = 20 }, + [ 5] = { .port_id = 2, .slot_id = 21 }, + [ 6] = { .port_id = 2, .slot_id = 22 }, + [ 7] = { .port_id = 2, .slot_id = 23 }, + [ 8] = { .port_id = 2, .slot_id = 24 }, + [ 9] = { .port_id = 2, .slot_id = 25 }, + [10] = { .port_id = 2, .slot_id = 26 }, + [11] = { .port_id = 2, .slot_id = 27 }, + [12] = { .port_id = 2, .slot_id = 28 }, + [13] = { .port_id = 2, .slot_id = 29 }, + [14] = { .port_id = 2, .slot_id = 30 }, + [15] = { .port_id = 2, .slot_id = 31 }, + }, + + /* + dsp_clk(xin, pllm) = xin * pllm + serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1) + */ + + .clk_divider = { + [0] = 47, /* must be 2048Hz */ + [1] = 47, + }, + + .initmode = 1, + .pllm = +#if !defined(CONFIG_NETTA_ISDN) + 8, /* for =~ 25MHz 8 */ +#else + 4, +#endif + .div = { + [0] = 0x8000, + [1] = 0x8000, /* for =~ 25MHz 0x8000 */ + [2] = 0x8001, /* for =~ 25MHz 0x8001 */ + [3] = 0x8001, /* for =~ 25MHz 0x8001 */ + }, + + .oscdiv1 = 0, +}; + +static void hi_write(const struct host_init *hi) +{ + u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)]; + u32 *s; + u32 chksum; + int i; + + memset(hi_buf, 0, sizeof(hi_buf)); + + s = hi_buf; + s++; + *s++ = hi->master_mode; + for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++) + *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) | + ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id; + + for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++) + *s++ = hi->clk_divider[i]; + + *s++ = hi->initmode; + *s++ = hi->pllm; + for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++) + *s++ = hi->div[i]; + *s++ = hi->oscdiv1; + + chksum = 0; + for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++) + chksum += hi_buf[i]; + hi_buf[0] = -chksum; + + c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0])); +} + +static void run_bootstrap(void) +{ + dsp_go_slow(); + + hi_write(&hi_default); + + /* signal interrupt */ + dsp_write_hpic(0x0002); + dsp_delay(); + + dsp_go_fast(); +} + +/***********************************************************************************************************/ + +int board_post_dsp(int flags) +{ + u32 ramS, ramE; + u32 data, data2; + int i, j, k, r; + + dsp_reset(); + dsp_init_hpic(); + dsp_go_slow(); + + data = 0x11223344; + dsp_write_hpic_word(DSP_HPIA, data); + data2 = dsp_read_hpic_word(DSP_HPIA); + if (data2 != 0x11223344) { + printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); + goto err; + } + + data = 0xFFEEDDCC; + dsp_write_hpic_word(DSP_HPIA, data); + data2 = dsp_read_hpic_word(DSP_HPIA); + if (data2 != 0xFFEEDDCC) { + printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); + goto err; + } + + r = load_bootstrap(); + if (r < 0) { + printf("BOOTSTRAP: ** ERROR ** failed to load\n"); + goto err; + } + + run_bootstrap(); + + dsp_go_fast(); + + printf(" "); + + /* test RAMs */ + for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) { + + ramS = ranges[k].start; + ramE = ranges[k].start + ranges[k].size; + + for (j = 0; j < 3; j++) { + + printf("\b\b\b\bR%d.%d", k, j); + + for (i = ramS; i < ramE; i += 4) { + + data = 0; + switch (j) { + case 0: data = 0xAA55AA55; break; + case 1: data = 0x55AA55AA; break; + case 2: data = (u32)i; break; + } + + c62_write_word(i, data); + data2 = c62_read_word(i); + if (data != data2) { + printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2); + goto err; + } + } + } + } + + printf("\b\b\b\b \b\b\b\bOK\n"); + + /* XXX assume that this works */ + load_bootstrap(); + run_bootstrap(); + dsp_go_fast(); + + return 0; + +err: + return -1; +} + +int board_dsp_reset(void) +{ + int r; + + dsp_reset(); + dsp_init_hpic(); + dsp_go_slow(); + r = load_bootstrap(); + if (r < 0) + return r; + + run_bootstrap(); + dsp_go_fast(); + + return 0; +} diff --git a/board/netta/flash.c b/board/netta/flash.c new file mode 100644 index 00000000000..ca3e061c279 --- /dev/null +++ b/board/netta/flash.c @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_byte(flash_info_t * info, ulong dest, uchar data); +static void flash_get_offsets(ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_MX: + printf("MXIC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + short i; + uchar mid; + uchar pid; + vu_char *caddr = (vu_char *) addr; + ulong base = (ulong) addr; + + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + mid = caddr[0]; + switch (mid) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (MX_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_MX; + break; + case (STM_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + pid = caddr[1]; /* device ID */ + switch (pid) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + + case (STM_ID_M29W040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf(" "); + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *) info->start[0]; + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0xF0; + + udelay(20000); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *) (info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer(0); + last = start; + addr = (vu_char *) (info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (vu_char *) info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte(flash_info_t * info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/netta/netta.c b/board/netta/netta.c new file mode 100644 index 00000000000..afb3fe18332 --- /dev/null +++ b/board/netta/netta.c @@ -0,0 +1,575 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#include <common.h> +#include <miiphy.h> + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#endif + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Intracom NETTA" +#if defined(CONFIG_NETTA_ISDN) + " with ISDN support" +#endif + "\n" + ); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define A10_AAAA 0x00000000 +#define A10_AAA0 0x00200000 +#define A10_AAA1 0x00300000 +#define A10_000A 0x00800000 +#define A10_0000 0x00A00000 +#define A10_0001 0x00B00000 +#define A10_111A 0x00C00000 +#define A10_1110 0x00E00000 +#define A10_1111 0x00F00000 + +#define RAS_0000 0x00000000 +#define RAS_0001 0x00040000 +#define RAS_1110 0x00080000 +#define RAS_1111 0x000C0000 + +#define CAS_0000 0x00000000 +#define CAS_0001 0x00010000 +#define CAS_1110 0x00020000 +#define CAS_1111 0x00030000 + +#define WE_0000 0x00000000 +#define WE_0001 0x00004000 +#define WE_1110 0x00008000 +#define WE_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 8 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + + upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + { + u32 d1, d2; + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + +#if 0 + printf("check 0\n"); + check_ram(( 0 << 20), (2 << 20)); + printf("check 16\n"); + check_ram((16 << 20), (2 << 20)); + printf("check 32\n"); + check_ram((32 << 20), (2 << 20)); + printf("check 48\n"); + check_ram((48 << 20), (2 << 20)); +#endif + + if (size == 0) { + printf("SIZE is zero: LOOP on 0\n"); + for (;;) { + *(volatile u32 *)0 = 0; + (void)*(volatile u32 *)0; + } + } + + return size; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r(void) +{ + return(0); +} + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + miiphy_read(phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +extern int board_dsp_reset(void); + +int last_stage_init(void) +{ + int r; + + reset_phys(); + r = board_dsp_reset(); + if (r < 0) + printf("*** WARNING *** DSP reset failed (run diagnostics)\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11)) +#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15)) +#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5)) +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK (_B(28) | _B(31)) +#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 30)) +#define PB_SP_MASK (_BR(22, 25)) +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_SP_DIRVAL 0 + +#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) +#define PC_GP_OUTMASK (_BW(6) | _BW(12)) +#define PC_SP_MASK (_BW(4) | _BW(8)) +#define PC_SOVAL 0 +#define PC_INTVAL _BW(7) +#define PC_GP_OUTVAL (_BW(6) | _BW(12)) +#define PC_SP_DIRVAL 0 + +#define PD_GP_INMASK 0 +#define PD_GP_OUTMASK _BWR(3, 15) +#define PD_SP_MASK 0 +#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) +#define PD_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* CS1: NAND chip select */ + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + + /* CS2: DSP */ + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); + memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + + /* CS4: External register chip select */ + memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); + memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); + + /* CS5: dummy for accurate delay */ + memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2); + memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + ioport->iop_pddat = PD_GP_OUTVAL; + ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; + ioport->iop_pdpar = PD_SP_MASK; + + ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <linux/mtd/nand.h> + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen = nand_probe(CFG_NAND_BASE); + + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) + +int pcmcia_init(void) +{ + return 0; +} + +#endif + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds new file mode 100644 index 00000000000..c3dac0ef4a5 --- /dev/null +++ b/board/netta/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug new file mode 100644 index 00000000000..21b7e6aabc0 --- /dev/null +++ b/board/netta/u-boot.lds.debug @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index 963f98f10ca..b7e57bfaf94 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -2607,6 +2607,370 @@ static int identify (volatile uchar *p) #endif /* CONFIG_IDE_8xx_PCCARD */ /* -------------------------------------------------------------------- */ +/* NETTA board by Intracom S.A. */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_NETTA) + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +#define PCMCIA_BOARD_MSG "NETTA" + +static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; + +static void cfg_vppd(int no) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) + return; + + mask = vppd_masks[no]; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_vppd(int no, int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) + return; + + mask = vppd_masks[no]; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; + +static void cfg_vccd(int no) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) + return; + + mask = vccd_masks[no]; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_vccd(int no, int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) + return; + + mask = vccd_masks[no]; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static const unsigned short oc_mask = _BW(8); + +static void cfg_oc(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask = oc_mask; + + immap->im_ioport.iop_pcdir &= ~mask; + immap->im_ioport.iop_pcso &= ~mask; + immap->im_ioport.iop_pcint &= ~mask; + immap->im_ioport.iop_pcpar &= ~mask; +} + +static int get_oc(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask = oc_mask; + int what; + + what = !!(immap->im_ioport.iop_pcdat & mask);; + return what; +} + +static const unsigned short shdn_mask = _BW(12); + +static void cfg_shdn(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + mask = shdn_mask; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_shdn(int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + mask = shdn_mask; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static void cfg_ports (void); + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + if ((pipr & mask) == mask) { + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ + puts (" 5.0V card found: "); + } else { + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ + puts (" 3.3V card found: "); + } + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if (!get_oc()) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* All voltages off / Hi-Z */ + set_vppd(0, 1); set_vppd(1, 1); + set_vccd(0, 1); set_vccd(1, 1); + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + ushort sreg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + sreg = immap->im_ioport.iop_pcdat; + set_vppd(0, 1); set_vppd(1, 1); + + switch(vcc) { + case 0: + break; /* Switch off */ + + case 33: + set_vccd(0, 1); set_vccd(1, 0); + break; + + case 50: + set_vccd(0, 0); set_vccd(1, 1); + break; + + default: + goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +static void cfg_ports (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + + cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ + cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ + cfg_shdn(); + cfg_oc(); + + /* + * Configure Port A for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + set_vppd(0, 1); set_vppd(1, 1); + set_vccd(0, 0); set_vccd(1, 0); + set_shdn(1); + + udelay(100000); +} + +#endif /* NETTA */ + + +/* -------------------------------------------------------------------- */ #endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */ diff --git a/common/command.c b/common/command.c index dfec9c138a7..df5d3e9bca5 100644 --- a/common/command.c +++ b/common/command.c @@ -217,3 +217,285 @@ cmd_tbl_t *find_cmd (const char *cmd) return NULL; /* not found or ambiguous command */ } + +#ifdef CONFIG_AUTO_COMPLETE + +int var_complete(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) +{ + static char tmp_buf[512]; + int space; + + space = last_char == '\0' || last_char == ' ' || last_char == '\t'; + + if (space && argc == 1) + return env_complete("", maxv, cmdv, sizeof(tmp_buf), tmp_buf); + + if (!space && argc == 2) + return env_complete(argv[1], maxv, cmdv, sizeof(tmp_buf), tmp_buf); + + return 0; +} + +static void install_auto_complete_handler(const char *cmd, + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[])) +{ + cmd_tbl_t *cmdtp; + + cmdtp = find_cmd(cmd); + if (cmdtp == NULL) + return; + + cmdtp->complete = complete; +} + +void install_auto_complete(void) +{ + install_auto_complete_handler("printenv", var_complete); + install_auto_complete_handler("setenv", var_complete); +#if (CONFIG_COMMANDS & CFG_CMD_RUN) + install_auto_complete_handler("run", var_complete); +#endif +} + +/*************************************************************************************/ + +static int complete_cmdv(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) +{ + cmd_tbl_t *cmdtp; + const char *p; + int len, clen; + int n_found = 0; + const char *cmd; + + /* sanity? */ + if (maxv < 2) + return -2; + + cmdv[0] = NULL; + + if (argc == 0) { + /* output full list of commands */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + if (n_found >= maxv - 2) { + cmdv[n_found++] = "..."; + break; + } + cmdv[n_found++] = cmdtp->name; + } + cmdv[n_found] = NULL; + return n_found; + } + + /* more than one arg or one but the start of the next */ + if (argc > 1 || (last_char == '\0' || last_char == ' ' || last_char == '\t')) { + cmdtp = find_cmd(argv[0]); + if (cmdtp == NULL || cmdtp->complete == NULL) { + cmdv[0] = NULL; + return 0; + } + return (*cmdtp->complete)(argc, argv, last_char, maxv, cmdv); + } + + cmd = argv[0]; + /* + * Some commands allow length modifiers (like "cp.b"); + * compare command name only until first dot. + */ + p = strchr(cmd, '.'); + if (p == NULL) + len = strlen(cmd); + else + len = p - cmd; + + /* return the partial matches */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + + clen = strlen(cmdtp->name); + if (clen < len) + continue; + + if (memcmp(cmd, cmdtp->name, len) != 0) + continue; + + /* too many! */ + if (n_found >= maxv - 2) { + cmdv[n_found++] = "..."; + break; + } + + cmdv[n_found++] = cmdtp->name; + } + + cmdv[n_found] = NULL; + return n_found; +} + +static int make_argv(char *s, int argvsz, char *argv[]) +{ + int argc = 0; + + /* split into argv */ + while (argc < argvsz - 1) { + + /* skip any white space */ + while ((*s == ' ') || (*s == '\t')) + ++s; + + if (*s == '\0') /* end of s, no more args */ + break; + + argv[argc++] = s; /* begin of argument string */ + + /* find end of string */ + while (*s && (*s != ' ') && (*s != '\t')) + ++s; + + if (*s == '\0') /* end of s, no more args */ + break; + + *s++ = '\0'; /* terminate current arg */ + } + argv[argc] = NULL; + + return argc; +} + +static void print_argv(const char *banner, const char *leader, const char *sep, int linemax, char *argv[]) +{ + int ll = leader != NULL ? strlen(leader) : 0; + int sl = sep != NULL ? strlen(sep) : 0; + int len, i; + + if (banner) { + puts("\n"); + puts(banner); + } + + i = linemax; /* force leader and newline */ + while (*argv != NULL) { + len = strlen(*argv) + sl; + if (i + len >= linemax) { + puts("\n"); + if (leader) + puts(leader); + i = ll - sl; + } else if (sep) + puts(sep); + puts(*argv++); + i += len; + } + printf("\n"); +} + +static int find_common_prefix(char *argv[]) +{ + int i, len; + char *anchor, *s, *t; + + if (*argv == NULL) + return 0; + + /* begin with max */ + anchor = *argv++; + len = strlen(anchor); + while ((t = *argv++) != NULL) { + s = anchor; + for (i = 0; i < len; i++, t++, s++) { + if (*t != *s) + break; + } + len = s - anchor; + } + return len; +} + +static char tmp_buf[CFG_CBSIZE]; /* copy of console I/O buffer */ + +int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) +{ + int n = *np, col = *colp; + char *argv[CFG_MAXARGS + 1]; /* NULL terminated */ + char *cmdv[20]; + char *s, *t; + const char *sep; + int i, j, k, len, seplen, argc; + int cnt; + char last_char; + + if (strcmp(prompt, CFG_PROMPT) != 0) + return 0; /* not in normal console */ + + cnt = strlen(buf); + if (cnt >= 1) + last_char = buf[cnt - 1]; + else + last_char = '\0'; + + /* copy to secondary buffer which will be affected */ + strcpy(tmp_buf, buf); + + /* separate into argv */ + argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv); + + /* do the completion and return the possible completions */ + i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv); + + /* no match; bell and out */ + if (i == 0) { + if (argc > 1) /* allow tab for non command */ + return 0; + putc('\a'); + return 1; + } + + s = NULL; + len = 0; + sep = NULL; + seplen = 0; + if (i == 1) { /* one match; perfect */ + k = strlen(argv[argc - 1]); + s = cmdv[0] + k; + len = strlen(s); + sep = " "; + seplen = 1; + } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */ + k = strlen(argv[argc - 1]); + j -= k; + if (j > 0) { + s = cmdv[0] + k; + len = j; + } + } + + if (s != NULL) { + k = len + seplen; + /* make sure it fits */ + if (n + k >= CFG_CBSIZE - 2) { + putc('\a'); + return 1; + } + + t = buf + cnt; + for (i = 0; i < len; i++) + *t++ = *s++; + if (sep != NULL) + for (i = 0; i < seplen; i++) + *t++ = sep[i]; + *t = '\0'; + n += k; + col += k; + puts(t - k); + if (sep == NULL) + putc('\a'); + *np = n; + *colp = col; + } else { + print_argv(NULL, " ", " ", 78, cmdv); + + puts(prompt); + puts(buf); + } + return 1; +} + +#endif diff --git a/common/env_common.c b/common/env_common.c index e7ee4991f88..d46f24f603a 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -260,3 +260,44 @@ void env_relocate (void) disable_nvram(); #endif } + +#ifdef CONFIG_AUTO_COMPLETE +int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) +{ + int i, nxt, len, vallen, found; + const char *lval, *rval; + + found = 0; + cmdv[0] = NULL; + + len = strlen(var); + /* now iterate over the variables and select those that match */ + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) + ; + + lval = env_get_addr(i); + rval = strchr(lval, '='); + if (rval != NULL) { + vallen = rval - lval; + rval++; + } else + vallen = strlen(lval); + + if (len > 0 && (vallen < len || memcmp(lval, var, len) != 0)) + continue; + + if (found >= maxv - 2 || bufsz < vallen + 1) { + cmdv[found++] = "..."; + break; + } + cmdv[found++] = buf; + memcpy(buf, lval, vallen); buf += vallen; bufsz -= vallen; + *buf++ = '\0'; bufsz--; + } + + cmdv[found] = NULL; + return found; +} +#endif diff --git a/common/main.c b/common/main.c index 156e4bc3d8a..7ce9b75f907 100644 --- a/common/main.c +++ b/common/main.c @@ -365,6 +365,10 @@ void main_loop (void) u_boot_hush_start (); #endif +#ifdef CONFIG_AUTO_COMPLETE + install_auto_complete(); +#endif + #ifdef CONFIG_PREBOOT if ((p = getenv ("preboot")) != NULL) { # ifdef CONFIG_AUTOBOOT_KEYED @@ -608,6 +612,14 @@ int readline (const char *const prompt) */ if (n < CFG_CBSIZE-2) { if (c == '\t') { /* expand TABs */ +#ifdef CONFIG_AUTO_COMPLETE + /* if auto completion triggered just continue */ + *p = '\0'; + if (cmd_auto_complete(prompt, console_buffer, &n, &col)) { + p = console_buffer + n; /* reset */ + continue; + } +#endif puts (tab_seq+(col&07)); col += 8 - (col&07); } else { diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 2a1c0e13fe6..8adf950f980 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -36,7 +36,7 @@ * added 8260 masks by * Marius Groeger <mag@sysgo.de> * - * added HiP7 (8270/8275/8280) processors support by + * added HiP7 (824x/827x/8280) processors support by * Yuli Barcohen <yuli@arabellasw.com> */ @@ -129,6 +129,10 @@ int checkcpu (void) case 0x0A01: puts ("0.1 1K49M"); break; + case 0x0C00: + case 0x0D00: + printf ("0.0 0K50M"); + break; default: printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); break; diff --git a/fs/reiserfs/reiserfs.c b/fs/reiserfs/reiserfs.c index ef4baf70a40..31c25ebc7b1 100644 --- a/fs/reiserfs/reiserfs.c +++ b/fs/reiserfs/reiserfs.c @@ -75,19 +75,19 @@ static void sd_print_item (struct item_head * ih, char * item) time_t ttime; if (stat_data_v1 (ih)) { - struct stat_data_v1 * sd = (struct stat_data_v1 *)item; - ttime = sd_v1_mtime(sd); - ctime_r(&ttime, filetime); - printf ("%-10s %4hd %6d %6d %9d %24.24s", - bb_mode_string(sd_v1_mode(sd)), sd_v1_nlink(sd),sd_v1_uid(sd), sd_v1_gid(sd), - sd_v1_size(sd), filetime); + struct stat_data_v1 * sd = (struct stat_data_v1 *)item; + ttime = sd_v1_mtime(sd); + ctime_r(&ttime, filetime); + printf ("%-10s %4hd %6d %6d %9d %24.24s", + bb_mode_string(sd_v1_mode(sd)), sd_v1_nlink(sd),sd_v1_uid(sd), sd_v1_gid(sd), + sd_v1_size(sd), filetime); } else { struct stat_data * sd = (struct stat_data *)item; - ttime = sd_v2_mtime(sd); - ctime_r(&ttime, filetime); - printf ("%-10s %4d %6d %6d %9d %24.24s", - bb_mode_string(sd_v2_mode(sd)), sd_v2_nlink(sd),sd_v2_uid(sd),sd_v2_gid(sd), - (__u32) sd_v2_size(sd), filetime); + ttime = sd_v2_mtime(sd); + ctime_r(&ttime, filetime); + printf ("%-10s %4d %6d %6d %9d %24.24s", + bb_mode_string(sd_v2_mode(sd)), sd_v2_nlink(sd),sd_v2_uid(sd),sd_v2_gid(sd), + (__u32) sd_v2_size(sd), filetime); } } @@ -95,7 +95,7 @@ static int journal_read (int block, int len, char *buffer) { return reiserfs_devread ((INFO->journal_block + block) << INFO->blocksize_shift, - 0, len, buffer); + 0, len, buffer); } /* Read a block from ReiserFS file system, taking the journal into @@ -247,7 +247,7 @@ journal_init (void) *journal_table++ = desc.j_len; for (i = 0; i < __le32_to_cpu(desc.j_len) && i < JOURNAL_TRANS_HALF; i++) { - /* both are in the little endian format */ + /* both are in the little endian format */ *journal_table++ = desc.j_realblock[i]; #ifdef REISERDEBUG printf ("block %d is in journal %d.\n", @@ -287,7 +287,7 @@ reiserfs_mount (unsigned part_length) if (part_length < superblock + (sizeof (super) >> SECTOR_BITS) || ! reiserfs_devread (superblock, 0, sizeof (struct reiserfs_super_block), - (char *) &super) + (char *) &super) || (substring (REISER3FS_SUPER_MAGIC_STRING, super.s_magic) > 0 && substring (REISER2FS_SUPER_MAGIC_STRING, super.s_magic) > 0 && substring (REISERFS_SUPER_MAGIC_STRING, super.s_magic) > 0) @@ -299,7 +299,7 @@ reiserfs_mount (unsigned part_length) superblock = REISERFS_OLD_DISK_OFFSET_IN_BYTES >> SECTOR_BITS; if (part_length < superblock + (sizeof (super) >> SECTOR_BITS) || ! reiserfs_devread (superblock, 0, sizeof (struct reiserfs_super_block), - (char *) &super)) + (char *) &super)) return 0; if (substring (REISER2FS_SUPER_MAGIC_STRING, super.s_magic) > 0 @@ -664,7 +664,7 @@ reiserfs_read (char *buf, unsigned len) * directly without using block_read */ reiserfs_devread (blocknr << INFO->blocksize_shift, - blk_offset, to_read, buf); + blk_offset, to_read, buf); update_buf_len: len -= to_read; buf += to_read; @@ -717,15 +717,15 @@ reiserfs_dir (char *dirname) #ifdef REISERDEBUG printf ("sd_mode=%x sd_size=%d\n", - stat_data_v1(INFO->current_ih) ? sd_v1_mode((struct stat_data_v1 *) INFO->current_item) : - sd_v2_mode((struct stat_data *) (INFO->current_item)), - stat_data_v1(INFO->current_ih) ? sd_v1_size((struct stat_data_v1 *) INFO->current_item) : - sd_v2_size((struct stat_data *) INFO->current_item) - ); + stat_data_v1(INFO->current_ih) ? sd_v1_mode((struct stat_data_v1 *) INFO->current_item) : + sd_v2_mode((struct stat_data *) (INFO->current_item)), + stat_data_v1(INFO->current_ih) ? sd_v1_size((struct stat_data_v1 *) INFO->current_item) : + sd_v2_size((struct stat_data *) INFO->current_item) + ); #endif /* REISERDEBUG */ mode = stat_data_v1(INFO->current_ih) ? - sd_v1_mode((struct stat_data_v1 *) INFO->current_item) : + sd_v1_mode((struct stat_data_v1 *) INFO->current_item) : sd_v2_mode((struct stat_data *) INFO->current_item); /* If we've got a symbolic link, then chase it. */ @@ -740,8 +740,8 @@ reiserfs_dir (char *dirname) /* Get the symlink size. */ filemax = stat_data_v1(INFO->current_ih) ? - sd_v1_size((struct stat_data_v1 *) INFO->current_item) : - sd_v2_size((struct stat_data *) INFO->current_item); + sd_v1_size((struct stat_data_v1 *) INFO->current_item) : + sd_v2_size((struct stat_data *) INFO->current_item); /* Find out how long our remaining name is. */ len = 0; @@ -760,7 +760,7 @@ reiserfs_dir (char *dirname) INFO->fileinfo.k_dir_id = dir_id; INFO->fileinfo.k_objectid = objectid; - filepos = 0; + filepos = 0; if (! next_key () || reiserfs_read (linkbuf, filemax) != filemax) { @@ -804,8 +804,8 @@ reiserfs_dir (char *dirname) filepos = 0; filemax = stat_data_v1(INFO->current_ih) ? - sd_v1_size((struct stat_data_v1 *) INFO->current_item) : - sd_v2_size((struct stat_data *) INFO->current_item); + sd_v1_size((struct stat_data_v1 *) INFO->current_item) : + sd_v2_size((struct stat_data *) INFO->current_item); #if 0 /* If this is a new stat data and size is > 4GB set filemax to * maximum @@ -879,22 +879,22 @@ reiserfs_dir (char *dirname) if (cmp <= 0) { char fn[PATH_MAX]; - struct fsys_reiser_info info_save; + struct fsys_reiser_info info_save; if (print_possibilities > 0) print_possibilities = -print_possibilities; *name_end = 0; strcpy(fn, filename); - *name_end = tmp; + *name_end = tmp; /* If NAME is "." or "..", do not count it. */ - if (strcmp (fn, ".") != 0 && strcmp (fn, "..") != 0) { - memcpy(&info_save, INFO, sizeof(struct fsys_reiser_info)); - search_stat (deh_dir_id(de_head), deh_objectid(de_head)); - sd_print_item(INFO->current_ih, INFO->current_item); - printf(" %s\n", fn); - search_stat (dir_id, objectid); - memcpy(INFO, &info_save, sizeof(struct fsys_reiser_info)); + if (strcmp (fn, ".") != 0 && strcmp (fn, "..") != 0) { + memcpy(&info_save, INFO, sizeof(struct fsys_reiser_info)); + search_stat (deh_dir_id(de_head), deh_objectid(de_head)); + sd_print_item(INFO->current_ih, INFO->current_item); + printf(" %s\n", fn); + search_stat (dir_id, objectid); + memcpy(INFO, &info_save, sizeof(struct fsys_reiser_info)); } } } diff --git a/fs/reiserfs/reiserfs_private.h b/fs/reiserfs/reiserfs_private.h index 2bdb5e7e3f3..d0197cb804e 100644 --- a/fs/reiserfs/reiserfs_private.h +++ b/fs/reiserfs/reiserfs_private.h @@ -157,13 +157,13 @@ struct offset_v2 { */ #if defined(__LITTLE_ENDIAN_BITFIELD) - /* little endian version */ - __u64 k_offset:60; - __u64 k_type: 4; + /* little endian version */ + __u64 k_offset:60; + __u64 k_type: 4; #elif defined(__BIG_ENDIAN_BITFIELD) - /* big endian version */ - __u64 k_type: 4; - __u64 k_offset:60; + /* big endian version */ + __u64 k_type: 4; + __u64 k_offset:60; #else #error "__LITTLE_ENDIAN_BITFIELD or __BIG_ENDIAN_BITFIELD must be defined" #endif @@ -368,7 +368,7 @@ struct reiserfs_de_head __u32 deh_dir_id; /* objectid of the parent directory of the object, that is referenced by directory entry */ __u32 deh_objectid;/* objectid of the object, that is referenced by - directory entry */ + directory entry */ __u16 deh_location;/* offset of name in the whole item */ __u16 deh_state; /* whether 1) entry contains stat data (for future), and 2) whether entry is hidden diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index f3846cd4205..2a9774ade83 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -83,9 +83,14 @@ * downloading RAM microcode. */ #define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) #define CPM_DP_NOSPACE ((uint)0x7fffffff) +#ifndef CONFIG_MPC8272_FAMILY +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) +#else /* 8247/48/71/72 */ +#define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) +#endif /* !CONFIG_MPC8272_FAMILY */ /* The number of pages of host memory we allocate for CPM. This is * done early in kernel initialization to get physically contiguous diff --git a/include/command.h b/include/command.h index b8c42e1c930..a2936ad8b3e 100644 --- a/include/command.h +++ b/include/command.h @@ -46,6 +46,10 @@ struct cmd_tbl_s { #ifdef CFG_LONGHELP char *help; /* Help message (long) */ #endif +#ifdef CONFIG_AUTO_COMPLETE + /* do auto completion on the arguments */ + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]); +#endif }; typedef struct cmd_tbl_s cmd_tbl_t; @@ -57,6 +61,11 @@ extern cmd_tbl_t __u_boot_cmd_end; /* common/command.c */ cmd_tbl_t *find_cmd(const char *cmd); +#ifdef CONFIG_AUTO_COMPLETE +extern void install_auto_complete(void); +extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); +#endif + /* * Monitor Command * diff --git a/include/common.h b/include/common.h index acdcf697372..9645ef489c8 100644 --- a/include/common.h +++ b/include/common.h @@ -64,6 +64,15 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_5xx) #include <asm/5xx_immap.h> #elif defined(CONFIG_8260) +#if defined(CONFIG_MPC8247) \ + || defined(CONFIG_MPC8248) \ + || defined(CONFIG_MPC8271) \ + || defined(CONFIG_MPC8272) +#define CONFIG_MPC8272_FAMILY 1 +#endif +#if defined(CONFIG_MPC8272_FAMILY) +#define CONFIG_MPC8260 1 +#endif #include <asm/immap_8260.h> #endif #ifdef CONFIG_MPC85xx @@ -196,6 +205,10 @@ void setenv (char *, char *); # include <asm/u-boot-i386.h> #endif /* CONFIG_I386 */ +#ifdef CONFIG_AUTO_COMPLETE +int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); +#endif + void pci_init (void); void pci_init_board(void); void pciinfo (int, int); diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index b0e9e447496..ce6e59173f4 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -232,7 +232,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 -/* +/* * Define CONFIG_FEC_10MBIT to force FEC at 10Mb */ /* #define CONFIG_FEC_10MBIT 1 */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index efc7a613fcc..7bd0d8e88d1 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -7,10 +7,11 @@ * Note: my board is a PILOT rev. * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. * - * (C) Copyright 2003 Arabella Software Ltd. + * (C) Copyright 2003-2004 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. + * Ported to MPC8272ADS board. * * See file CREDITS for list of people who contributed to this * project. @@ -39,18 +40,24 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ +#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ /* ADS flavours */ #define CFG_8260ADS 1 /* MPC8260ADS */ #define CFG_8266ADS 2 /* MPC8266ADS */ #define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */ +#define CFG_8272ADS 4 /* MPC8272ADS */ #ifndef CONFIG_ADSTYPE #define CONFIG_ADSTYPE CFG_8260ADS #endif /* CONFIG_ADSTYPE */ +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_MPC8272 1 +#else +#define CONFIG_MPC8260 1 +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ /* allow serial and ethaddr to be overwritten */ @@ -92,42 +99,60 @@ #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#if (CONFIG_ETHER_INDEX == 2) -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Full duplex - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#if CONFIG_ETHER_INDEX == 1 + +# define CFG_PHY_ADDR 0 +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) +# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) + +#elif CONFIG_ETHER_INDEX == 2 + +#if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ +# define CFG_PHY_ADDR 3 +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) +#else /* RxCLK is CLK13, TxCLK is CLK14 */ +# define CFG_PHY_ADDR 0 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + +# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) #endif /* CONFIG_ETHER_INDEX */ +#define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */ +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */ + #define CONFIG_MII /* MII PHY management */ #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ /* * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_MDIO_PIN 0x00002000 /* PC18 */ +#define CFG_MDC_PIN 0x00001000 /* PC19 */ +#else +#define CFG_MDIO_PIN 0x00400000 /* PC9 */ +#define CFG_MDC_PIN 0x00200000 /* PC10 */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN #define MIIDELAY udelay(1) #endif /* CONFIG_ETHER_ON_FCC */ -#if CONFIG_ADSTYPE == CFG_PQ2FADS -#undef CONFIG_SPD_EEPROM /* On PQ2FADS-ZU, SDRAM is soldered */ +#if CONFIG_ADSTYPE >= CFG_PQ2FADS +#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */ #else #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ @@ -136,21 +161,21 @@ #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) #define CONFIG_SPD_ADDR 0x50 #endif -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ +#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ #ifndef CONFIG_SDRAM_PBI #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN -#if CONFIG_ADSTYPE == CFG_PQ2FADS +#if CONFIG_ADSTYPE >= CFG_PQ2FADS #define CONFIG_8260_CLKIN 100000000 /* in Hz */ #else #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif #endif -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 38400 #define CFG_EXCLUDE CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ @@ -176,7 +201,7 @@ CFG_CMD_USB | \ CFG_CMD_VFD -#if CONFIG_ADSTYPE == CFG_PQ2FADS +#if CONFIG_ADSTYPE >= CFG_PQ2FADS #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_CMD_SDRAM | \ CFG_CMD_I2C | \ @@ -184,14 +209,14 @@ #else #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_EXCLUDE ) ) -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ +#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock2" #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ @@ -256,12 +281,12 @@ #define RS232EN_2 0x01000001 #define FETHIEN1 0x08000008 #define FETH1_RST 0x04000004 -#define FETHIEN2 0x01000000 +#define FETHIEN2 0x10000000 #define FETH2_RST 0x08000000 #define BCSR_PCI_MODE 0x01000000 #define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -273,7 +298,6 @@ ( HRCW_BMS | HRCW_APPC10 ) |\ ( HRCW_MODCK_H0101 ) \ ) - /* no slaves */ #define CFG_HRCW_SLAVE1 0 #define CFG_HRCW_SLAVE2 0 @@ -336,8 +360,8 @@ #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 -#if CONFIG_ADSTYPE == CFG_8266ADS -#undef CFG_LSDRAM_BASE /* No local bus SDRAM on MPC8266ADS */ +#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS) +#undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */ #endif /* CONFIG_ADSTYPE == CFG_8266ADS */ #if CONFIG_ADSTYPE == CFG_PQ2FADS @@ -347,6 +371,11 @@ #define CFG_LSDMR 0x828737A3 #define CFG_LSRT 0x13 #define CFG_MPTPR 0x2800 +#elif CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_OR2 0xFC002CC0 +#define CFG_PSDMR 0x834E24A3 +#define CFG_PSRT 0x13 +#define CFG_MPTPR 0x2800 #else #define CFG_OR2 0xFF000CA0 #define CFG_PSDMR 0x016EB452 diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h new file mode 100644 index 00000000000..6dd12fe4441 --- /dev/null +++ b/include/configs/NETPHONE.h @@ -0,0 +1,694 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ +#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +/* #define CONFIG_XIN 10000000 */ +#define CONFIG_XIN 50000000 +#define MPC8XX_HZ 120000000 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +#define CONFIG_AUTOSCRIPT +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY +#define CONFIG_MII 1 +#define CONFIG_RMII 1 /* use RMII interface */ + +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY_NORXERR 1 + +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 4 +#define CONFIG_FEC2_PHY_NORXERR 1 + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_CDP \ + ) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 25000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 40000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 75000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif + +#elif CONFIG_XIN == 50000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 50MHz +#endif + +#else + +#error unsupported XIN freq +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3 and OR3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_MAMR_PTA 234 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ARTOS /* include ARTOS support */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/****************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define NAND_SIZE 0x00010000 /* 64K */ +#define ER_SIZE 0x00010000 /* 64K */ + +#define DSP_BASE 0xF1000000 +#define NAND_BASE 0xF1010000 +#define ER_BASE 0xF1020000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 + +#define CFG_MAX_NAND_DEVICE 1 + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ + } while(0) + +#define NAND_WAIT_READY(nand) \ + do { \ + while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ + ; \ + } while (0) + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +/*****************************************************************************/ + +#define STATUS_LED_BIT 0x00000008 /* bit 28 */ +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifndef __ASSEMBLY__ + +/* LEDs */ + +/* led_id_t is unsigned int mask */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \ + else \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ + } while(0) + +#define __led_init(msk, st) __led_set(msk, st) + +#endif + +/*********************************************************************************************************** + + Pin definitions: + + +------+----------------+--------+------------------------------------------------------------ + | # | Name | Type | Comment + +------+----------------+--------+------------------------------------------------------------ + | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select + | PA7 | DSP_INT | Output | DSP interrupt + | PA10 | DSP_RESET | Output | DSP reset + | PA14 | USBOE | Output | USB (1) + | PA15 | USBRXD | Output | USB (1) + | PB19 | BT_RTS | Output | Bluetooth (0) + | PB23 | BT_CTS | Output | Bluetooth (0) + | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select + | PB27 | SPICS_DISP | Output | Display chip select + | PB28 | SPI_RXD_3V | Input | SPI Data Rx + | PB29 | SPI_TXD | Output | SPI Data Tx + | PB30 | SPI_CLK | Output | SPI Clock + | PC10 | DISPA0 | Output | Display A0 + | PC11 | BACKLIGHT | Output | Display backlit + | PC12 | SPI2RXD | Input | 2nd SPI RXD + | PC13 | SPI2TXD | Output | 2nd SPI TXD + | PC15 | SPI2CLK | Output | 2nd SPI CLK + | PE17 | F_ALE | Output | NAND F_ALE + | PE18 | F_CLE | Output | NAND F_CLE + | PE20 | F_CE | Output | NAND F_CE + | PE24 | SPICS_SCOUT | Output | Codec chip select + | PE27 | SPICS_ER | Output | External serial register CS + | PE28 | LEDIO1 | Output | LED + | PE29 | LEDIO2 | Output | LED hook for A (TA2) + | PE30 | LEDIO3 | Output | LED hook for A (TA2) + | PE31 | F_RY_BY | Input | NAND F_RY_BY + +------+----------------+--------+--------------------------------------------------- + + Chip selects: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | CS0 | CS0 | Boot flash + | CS1 | CS_FLASH | NAND flash + | CS2 | CS_DSP | DSP + | CS3 | DCS_DRAM | DRAM + +------+----------------+------------------------------------------------------------ + + Interrupts: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IRQ1 | IRQ_DSP | DSP interrupt + | IRQ3 | S_INTER | DUSLIC ??? + | IRQ4 | F_RY_BY | NAND + | IRQ7 | IRQ_MAX | MAX 3100 interrupt + +------+----------------+------------------------------------------------------------ + + Interrupts on PCMCIA pins: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface + | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface + | IP_A2| RMII1_MDINT | PHY interrupt for #1 + | IP_A3| RMII2_MDINT | PHY interrupt for #2 + +------+----------------+------------------------------------------------------------ + +*************************************************************************************************/ + +#define CONFIG_SED156X 1 /* use SED156X */ +#define CONFIG_SED156X_PG12864Q 1 /* type of display used */ + +/* serial interfacing macros */ + +#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_SPI_RXD_MASK 0x00000008 + +#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_SPI_TXD_MASK 0x00000004 + +#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_SPI_CLK_MASK 0x00000002 + +#define SED156X_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_CS_MASK 0x00000010 + +#define SED156X_A0_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define SED156X_A0_MASK 0x0020 + +/*************************************************************************************************/ + +#define CFG_CONSOLE_IS_IN_ENV 1 +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CFG_CONSOLE_ENV_OVERWRITE 1 + +/*************************************************************************************************/ + +/* use board specific hardware */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_SHOW_ACTIVITY + +/*************************************************************************************************/ + +/* phone console configuration */ + +#define PHONE_CONSOLE_POLL_HZ (CFG_HZ/200) /* poll every 5ms */ + +/*************************************************************************************************/ + +#define CONFIG_CDP_DEVICE_ID 20 +#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ +#define CONFIG_CDP_PORT_ID "eth%d" +#define CONFIG_CDP_CAPABILITIES 0x00000010 +#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__ +#define CONFIG_CDP_PLATFORM "Intracom NetPhone" +#define CONFIG_CDP_TRIGGER 0x20020001 +#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ +#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ + +/*************************************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 + +/*************************************************************************************************/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h new file mode 100644 index 00000000000..76e9cb4c1e0 --- /dev/null +++ b/include/configs/NETTA.h @@ -0,0 +1,745 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ +#define CONFIG_NETTA 1 /* ...on a NetTA board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +/* #define CONFIG_XIN 10000000 */ +#define CONFIG_XIN 50000000 +#define MPC8XX_HZ 120000000 +/* #define MPC8XX_HZ 100000000 */ +/* #define MPC8XX_HZ 50000000 */ +/* #define MPC8XX_HZ 80000000 */ + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY /* do not discover phys */ +#define CONFIG_MII 1 +#define CONFIG_RMII 1 /* use RMII interface */ + +#if defined(CONFIG_NETTA_ISDN) +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY_NORXERR 1 +#undef CONFIG_ETHER_ON_FEC2 +#else +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY_NORXERR 1 +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ +#define CONFIG_FEC2_PHY_NORXERR 1 +#endif + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_DSP ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_PCMCIA | CFG_CMD_IDE | CFG_CMD_FAT | \ + CFG_CMD_DIAG | \ + CFG_CMD_CDP \ + ) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 25000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 40000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 75000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif + +#elif CONFIG_XIN == 50000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 80000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 50MHz +#endif + +#else + +#error unsupported XIN freq +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL001 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3 and OR3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#if MPC8XX_HZ == 120000000 +#define CFG_MAMR_PTA 234 +#elif MPC8XX_HZ == 100000000 +#define CFG_MAMR_PTA 195 +#elif MPC8XX_HZ == 80000000 +#define CFG_MAMR_PTA 156 +#elif MPC8XX_HZ == 50000000 +#define CFG_MAMR_PTA 98 +#else +#error Unknown frequency +#endif + + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ARTOS /* include ARTOS support */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/*********************************************************************************************************** + + Pin definitions: + + +------+----------------+--------+------------------------------------------------------------ + | # | Name | Type | Comment + +------+----------------+--------+------------------------------------------------------------ + | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK + | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) + | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA + | PA7 | DCL1_3V | Periph | IDL1 PCM clock + | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx + | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx + | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA + | PA12 | P_SHDN | Output | TPS2211A PCMCIA + | PA13 | ETH_LOOP | Output | CISCO Loopback remote power + | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) + | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA + | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA + | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board + | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) + | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. + | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC + | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC + | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) + | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom + | PB21 | LEDIO | Output | Led mode indication for PHY + | PB22 | UART_CTS | Input | UART CTS + | PB23 | UART_RTS | Output | UART RTS + | PB24 | UART_RX | Periph | UART Data Rx + | PB25 | UART_TX | Periph | UART Data Tx + | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) + | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) + | PB28 | SPI_RXD_3V | Input | SPI Data Rx + | PB29 | SPI_TXD | Output | SPI Data Tx + | PB30 | SPI_CLK | Output | SPI Clock + | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 + | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) + | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) + | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) + | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) + | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) + | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) + | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) + | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) + | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) + | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) + | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) + | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. + | PD3 | F_ALE | Output | NAND + | PD4 | F_CLE | Output | NAND + | PD5 | F_CE | Output | NAND + | PD6 | DSP_INT | Output | DSP debug interrupt + | PD7 | DSP_RESET | Output | DSP reset + | PD8 | RMII_MDC | Periph | MII mgt clock + | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 + | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 + | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 + | PD12 | FSC2 | Periph | IDL2 frame sync + | PD13 | DGRANT2 | Input | D channel grant from S #2 + | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 + | PD15 | TP700 | Output | Testpoint for software debugging + | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data + | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data + | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for + | | DCL2 | Periph | NetRoute: PCM clock #2 + | PE17 | TP703 | Output | Testpoint for software debugging + | PE18 | DGRANT1 | Input | D channel grant from S #1 + | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable + | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 + | PE20 | FSC1 | Periph | IDL1 frame sync + | PE21 | RMII2-RXD0 | Periph | FEC2 receive data + | PE22 | RMII2-RXD1 | Periph | FEC2 receive data + | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC + | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) + | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) + | PE26 | RMII2-RXDV | Periph | FEC2 valid + | PE27 | DREQ2 | Output | D channel request for S #2. + | PE28 | FPGA_DONE | Input | FPGA done signal + | PE29 | FPGA_INIT | Output | FPGA init signal + | PE30 | UDOUT2_3V | Input | IDL2 PCM input + | PE31 | | | Free + +------+----------------+--------+--------------------------------------------------- + + Chip selects: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | CS0 | CS0 | Boot flash + | CS1 | CS_FLASH | NAND flash + | CS2 | CS_DSP | DSP + | CS3 | DCS_DRAM | DRAM + | CS4 | CS_ER1 | External output register + +------+----------------+------------------------------------------------------------ + + Interrupts: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IRQ1 | UINTER_3V | S interupt chips interrupt (common) + | IRQ3 | IRQ_DSP | DSP interrupt + | IRQ4 | IRQ_DSP1 | Extra DSP interrupt + +------+----------------+------------------------------------------------------------ + +*************************************************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define NAND_SIZE 0x00010000 /* 64K */ +#define ER_SIZE 0x00010000 /* 64K */ +#define DUMMY_SIZE 0x00010000 /* 64K */ + +#define DSP_BASE 0xF1000000 +#define NAND_BASE 0xF1010000 +#define ER_BASE 0xF1020000 +#define DUMMY_BASE 0xF1FF0000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 + +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_NO_RB + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \ + } while(0) + +#ifndef NAND_NO_RB +#define NAND_WAIT_READY(nand) \ + do { \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \ + WATCHDOG_RESET(); \ + } \ + } while (0) +#else +#define NAND_WAIT_READY(nand) udelay(12) +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +/*****************************************************************************/ + +#if 1 +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#endif + +/*************************************************************************************************/ + +#define CONFIG_CDP_DEVICE_ID 20 +#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ +#define CONFIG_CDP_PORT_ID "eth%d" +#define CONFIG_CDP_CAPABILITIES 0x00000010 +#define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__ +#define CONFIG_CDP_PLATFORM "Intracom NetTA" +#define CONFIG_CDP_TRIGGER 0x20020001 +#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ +#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ + +/*************************************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 + +/*************************************************************************************************/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 46505b6fd37..8f93a49c082 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -36,7 +36,6 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_NETVIA 1 /* ...on a NetVia board */ -#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */ #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ @@ -49,14 +48,8 @@ #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#ifdef CONFIG_NETVIA_PLL_CLOCK -/* XXX make sure that you calculate these two correctly */ -#define CFG_GCLK_MF 1350 -#define CONFIG_8xx_GCLK_FREQ 44236800 -#else -#define CFG_GCLK_MF 1 -#define CONFIG_8xx_GCLK_FREQ 50000000 -#endif +#define CONFIG_XIN 10000000 +#define CONFIG_8xx_GCLK_FREQ 80000000 #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -253,22 +246,34 @@ * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * - */ - -#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */ + #define SCCR_MASK SCCR_EBDF11 + +#if CONFIG_8xx_GCLK_FREQ == 50000000 + +#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) #define CFG_SCCR (SCCR_TBS | \ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) +#elif CONFIG_8xx_GCLK_FREQ == 80000000 + +#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) + +#endif + /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- @@ -520,6 +525,6 @@ static inline void __led_set(led_id_t mask, int state) #endif -/****************************************************************/ +/*************************************************************************************************/ #endif /* __CONFIG_H */ diff --git a/include/mpc8260.h b/include/mpc8260.h index c93370c4d0e..ff52a7b38b3 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -34,8 +34,12 @@ #define CPU_ID_STR "MPC8255" #endif #ifndef CPU_ID_STR +#if defined(CONFIG_MPC8272_FAMILY) +#define CPU_ID_STR "MPC8272" +#else #define CPU_ID_STR "MPC8260" #endif +#endif /* !CPU_ID_STR */ /*----------------------------------------------------------------------- * Exception offsets (PowerPC standard) diff --git a/include/pcmcia.h b/include/pcmcia.h index 3080be3b006..af56e6d1b78 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -64,6 +64,8 @@ # define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ # define CONFIG_PCMCIA_SLOT_A +#elif defined(CONFIG_NETTA) +# define CONFIG_PCMCIA_SLOT_A #else # error "PCMCIA Slot not configured" #endif diff --git a/include/status_led.h b/include/status_led.h index 441b0c23187..cad287d43f2 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -333,6 +333,9 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ +/***** NetPhone ********************************************************/ +#elif defined(CONFIG_NETPHONE) +/* XXX empty just to avoid the error */ /************************************************************************/ #else # error Status LED configuration missing diff --git a/lib_ppc/board.c b/lib_ppc/board.c index de5adb4c3c9..998c25cc9ff 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -93,7 +93,7 @@ extern flash_info_t flash_info[]; #if defined(CFG_ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN #elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ - (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ + (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ defined(CFG_ENV_IS_IN_NVRAM) #define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) #else |