diff options
| -rw-r--r-- | Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/Kconfig | 34 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/lib/bootm.c | 31 | ||||
| -rw-r--r-- | board/sunxi/Kconfig | 2 | ||||
| -rw-r--r-- | include/configs/arndale.h | 2 | ||||
| -rw-r--r-- | include/configs/sun7i.h | 2 | ||||
| -rw-r--r-- | include/configs/vexpress_ca15_tc2.h | 2 |
9 files changed, 76 insertions, 11 deletions
@@ -58,6 +58,14 @@ config CC_OPTIMIZE_FOR_SIZE endmenu # General setup +menuconfig EXPERT + bool "Configure standard U-Boot features (expert users)" + help + This option allows certain base U-Boot options and settings + to be disabled or tweaked. This is for specialized + environments which can tolerate a "non-standard" U-Boot. + Only use this if you really know what you are doing. + menu "Boot images" config SPL_BUILD diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5241cb473b7..b9ac59e1a4a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -415,6 +415,8 @@ config TARGET_INTEGRATORCP_CM946ES config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT config TARGET_VEXPRESS_CA5X2 bool "Support vexpress_ca5x2" @@ -826,6 +828,8 @@ source "arch/arm/cpu/arm926ejs/versatile/Kconfig" source "arch/arm/cpu/armv7/zynq/Kconfig" +source "arch/arm/cpu/armv7/Kconfig" + source "board/aristainetos/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig new file mode 100644 index 00000000000..61e7c824594 --- /dev/null +++ b/arch/arm/cpu/armv7/Kconfig @@ -0,0 +1,34 @@ +if CPU_V7 + +config CPU_V7_HAS_NONSEC + bool + +config CPU_V7_HAS_VIRT + bool + +config ARMV7_NONSEC + boolean "Enable support for booting in non-secure mode" if EXPERT + depends on CPU_V7_HAS_NONSEC + default y + ---help--- + Say Y here to enable support for booting in non-secure / SVC mode. + +config ARMV7_BOOT_SEC_DEFAULT + boolean "Boot in secure mode by default" if EXPERT + depends on ARMV7_NONSEC + default n + ---help--- + Say Y here to boot in secure mode by default even if non-secure mode + is supported. This option is useful to boot kernels which do not + suppport booting in non-secure mode. Only set this if you need it. + This can be overriden at run-time by setting the bootm_boot_mode env. + variable to "sec" or "nonsec". + +config ARMV7_VIRT + boolean "Enable support for hardware virtualization" if EXPERT + depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC + default y + ---help--- + Say Y here to boot in hypervisor (HYP) mode when booting non-secure. + +endif diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 090be9383fc..e9a102ce3c0 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -26,6 +26,8 @@ config TARGET_ODROID config TARGET_ARNDALE bool "Exynos5250 Arndale board" + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 4949d573af8..a7f7c679976 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -237,6 +237,26 @@ static void boot_prep_linux(bootm_headers_t *images) } } +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +static bool boot_nonsec(void) +{ + char *s = getenv("bootm_boot_mode"); +#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT + bool nonsec = false; +#else + bool nonsec = true; +#endif + + if (s && !strcmp(s, "sec")) + nonsec = false; + + if (s && !strcmp(s, "nonsec")) + nonsec = true; + + return nonsec; +} +#endif + /* Subcommand: GO */ static void boot_jump_linux(bootm_headers_t *images, int flag) { @@ -285,12 +305,13 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) if (!fake) { #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) - armv7_init_nonsec(); - secure_ram_addr(_do_nonsec_entry)(kernel_entry, - 0, machid, r2); -#else - kernel_entry(0, machid, r2); + if (boot_nonsec()) { + armv7_init_nonsec(); + secure_ram_addr(_do_nonsec_entry)(kernel_entry, + 0, machid, r2); + } else #endif + kernel_entry(0, machid, r2); } #endif } diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index c3f865d2983..7555896f740 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -21,6 +21,8 @@ config MACH_SUN6I config MACH_SUN7I bool "sun7i (Allwinner A20)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL config MACH_SUN8I diff --git a/include/configs/arndale.h b/include/configs/arndale.h index f9ee40fa7ee..aa6b631c5d4 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -60,6 +60,4 @@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 -#define CONFIG_ARMV7_VIRT - #endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index ea407903229..36295876fd8 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -22,8 +22,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#define CONFIG_ARMV7_VIRT 1 -#define CONFIG_ARMV7_NONSEC 1 #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 982f4a75ef6..b43afa29387 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -18,6 +18,4 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR -#define CONFIG_ARMV7_VIRT - #endif |