diff options
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 93 |
1 files changed, 78 insertions, 15 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 9d05f83cbc4..5944dd2813b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -128,13 +128,20 @@ static void mxs_mem_init_clock(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; +#if defined(CONFIG_MX23) + /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ + const unsigned char divider = 33; +#elif defined(CONFIG_MX28) + /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ + const unsigned char divider = 21; +#endif /* Gate EMI clock */ writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); - /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ - writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), + /* Set fractional divider for ref_emi */ + writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); /* Ungate EMI clock */ @@ -217,10 +224,60 @@ uint32_t mxs_mem_get_size(void) return sz; } -void mxs_mem_init(void) +#ifdef CONFIG_MX23 +static void mx23_mem_setup_vddmem(void) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + + writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | + POWER_VDDMEMCTRL_ENABLE_ILIMIT | + POWER_VDDMEMCTRL_ENABLE_LINREG | + POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, + &power_regs->hw_power_vddmemctrl); + + early_delay(10000); + + writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | + POWER_VDDMEMCTRL_ENABLE_LINREG, + &power_regs->hw_power_vddmemctrl); +} + +static void mx23_mem_init(void) +{ + mx23_mem_setup_vddmem(); + + /* + * Configure the DRAM registers + */ + + /* Clear START and SREFRESH bit from DRAM_CTL8 */ + clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); + + initialize_dram_values(); + + /* Set START bit in DRAM_CTL16 */ + setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); + + clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); + early_delay(20000); + + /* Adjust EMI port priority. */ + clrsetbits_le32(0x80020000, 0x1f << 16, 0x8); + early_delay(20000); + + setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); + setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); + + /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ + while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) + ; +} +#endif + +#ifdef CONFIG_MX28 +static void mx28_mem_init(void) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct mxs_pinctrl_regs *pinctrl_regs = (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; @@ -228,16 +285,6 @@ void mxs_mem_init(void) writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); - /* Power up PLL0 */ - writel(CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - - early_delay(11000); - - mxs_mem_init_clock(); - - mxs_mem_setup_vdda(); - /* * Configure the DRAM registers */ @@ -256,6 +303,22 @@ void mxs_mem_init(void) /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) ; +} +#endif + +void mxs_mem_init(void) +{ + early_delay(11000); + + mxs_mem_init_clock(); + + mxs_mem_setup_vdda(); + +#if defined(CONFIG_MX23) + mx23_mem_init(); +#elif defined(CONFIG_MX28) + mx28_mem_init(); +#endif early_delay(10000); |