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-rw-r--r--README3
-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/mx6/Kconfig42
-rw-r--r--arch/arm/imx-common/Kconfig2
-rw-r--r--board/prodrive/alpr/nand.c16
-rw-r--r--board/seco/Kconfig63
-rw-r--r--board/seco/common/Makefile2
-rw-r--r--board/seco/common/mx6.c138
-rw-r--r--board/seco/common/mx6.h9
-rw-r--r--board/seco/mx6quq7/MAINTAINERS6
-rw-r--r--board/seco/mx6quq7/Makefile7
-rw-r--r--board/seco/mx6quq7/mx6quq7-2g.cfg173
-rw-r--r--board/seco/mx6quq7/mx6quq7.c162
-rw-r--r--board/socrates/nand.c25
-rw-r--r--common/cmd_nand.c27
-rw-r--r--configs/mx6dlsabresd_defconfig2
-rw-r--r--configs/mx6slevk_defconfig4
-rw-r--r--configs/mx6slevk_spinor_defconfig4
-rw-r--r--configs/secomx6quq7_defconfig7
-rw-r--r--doc/README.nand12
-rw-r--r--drivers/dfu/dfu_nand.c2
-rw-r--r--drivers/mtd/nand/davinci_nand.c12
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c38
-rw-r--r--drivers/mtd/nand/fsl_ifc_nand.c38
-rw-r--r--drivers/mtd/nand/fsl_upm.c18
-rw-r--r--drivers/mtd/nand/mpc5121_nfc.c26
-rw-r--r--drivers/mtd/nand/mxc_nand.c33
-rw-r--r--drivers/mtd/nand/mxs_nand.c4
-rw-r--r--drivers/mtd/nand/nand_base.c65
-rw-r--r--drivers/mtd/nand/nand_util.c156
-rw-r--r--drivers/mtd/nand/ndfc.c18
-rw-r--r--drivers/mtd/nand/vf610_nfc.c28
-rw-r--r--drivers/spi/cf_qspi.c2
-rw-r--r--drivers/spi/cf_spi.c31
-rw-r--r--drivers/spi/davinci_spi.c3
-rw-r--r--drivers/spi/designware_spi.c4
-rw-r--r--drivers/spi/ftssp010_spi.c4
-rw-r--r--drivers/spi/ti_qspi.c7
-rw-r--r--drivers/watchdog/imx_watchdog.c3
-rw-r--r--include/configs/B4860QDS.h1
-rw-r--r--include/configs/BSC9131RDB.h1
-rw-r--r--include/configs/BSC9132QDS.h1
-rw-r--r--include/configs/C29XPCIE.h1
-rw-r--r--include/configs/M54418TWR.h1
-rw-r--r--include/configs/MPC8313ERDB.h1
-rw-r--r--include/configs/MPC8315ERDB.h1
-rw-r--r--include/configs/MPC837XEMDS.h1
-rw-r--r--include/configs/MPC8536DS.h1
-rw-r--r--include/configs/MPC8569MDS.h1
-rw-r--r--include/configs/MPC8572DS.h1
-rw-r--r--include/configs/P1010RDB.h1
-rw-r--r--include/configs/P1022DS.h1
-rw-r--r--include/configs/P1023RDB.h1
-rw-r--r--include/configs/P2041RDB.h1
-rw-r--r--include/configs/T102xQDS.h1
-rw-r--r--include/configs/T102xRDB.h1
-rw-r--r--include/configs/T1040QDS.h1
-rw-r--r--include/configs/T104xRDB.h1
-rw-r--r--include/configs/T208xQDS.h1
-rw-r--r--include/configs/T208xRDB.h1
-rw-r--r--include/configs/T4240QDS.h1
-rw-r--r--include/configs/T4240RDB.h1
-rw-r--r--include/configs/VCMA9.h1
-rw-r--r--include/configs/corenet_ds.h1
-rw-r--r--include/configs/dra7xx_evm.h1
-rw-r--r--include/configs/ethernut5.h1
-rw-r--r--include/configs/ids8313.h1
-rw-r--r--include/configs/km/kmp204x-common.h1
-rw-r--r--include/configs/ls1021aqds.h1
-rw-r--r--include/configs/ls2085a_common.h1
-rw-r--r--include/configs/mx6slevk.h7
-rw-r--r--include/configs/p1_p2_rdb_pc.h1
-rw-r--r--include/configs/secomx6quq7.h166
-rw-r--r--include/configs/ve8313.h1
-rw-r--r--include/configs/xpedite537x.h1
-rw-r--r--include/configs/xpedite550x.h1
-rw-r--r--include/linux/mtd/nand.h5
-rw-r--r--include/nand.h35
78 files changed, 966 insertions, 486 deletions
diff --git a/README b/README
index 5d57eb924ff..b7c2a170686 100644
--- a/README
+++ b/README
@@ -3483,9 +3483,6 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
- CONFIG_MTD_NAND_VERIFY_WRITE
- verify if the written data is correct reread.
-
- UBI support
CONFIG_CMD_UBI
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9292e9878df..80b0d34190f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -428,6 +428,10 @@ config ARCH_KEYSTONE
select CPU_V7
select SUPPORT_SPL
+config ARCH_MX6
+ bool "Freescale MX6"
+ select CPU_V7
+
config TARGET_M53EVK
bool "Support m53evk"
select CPU_V7
@@ -730,6 +734,8 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/cpu/armv7/mx6/Kconfig"
+
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/cpu/armv7/omap3/Kconfig"
@@ -756,6 +762,8 @@ source "arch/arm/cpu/armv7/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
+source "arch/arm/imx-common/Kconfig"
+
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
new file mode 100644
index 00000000000..076ba520c66
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -0,0 +1,42 @@
+if ARCH_MX6
+
+config MX6
+ bool
+ default y
+
+config MX6D
+ bool
+
+config MX6DL
+ bool
+
+config MX6Q
+ bool
+
+config MX6QDL
+ bool
+
+config MX6S
+ bool
+
+config MX6SL
+ bool
+
+config MX6SX
+ bool
+
+choice
+ prompt "MX6 board select"
+
+config TARGET_SECOMX6
+ bool "Support secomx6 boards"
+ select CPU_V7
+
+endchoice
+
+config SYS_SOC
+ default "mx6"
+
+source "board/seco/Kconfig"
+
+endif
diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
new file mode 100644
index 00000000000..37b375249d4
--- /dev/null
+++ b/arch/arm/imx-common/Kconfig
@@ -0,0 +1,2 @@
+config IMX_CONFIG
+ string
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 5427de56342..ca40cea9ad1 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -93,19 +93,6 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
}
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- if (buf[i] != readb(&(alpr_ndfc->data)))
- return i;
-
- return 0;
-}
-#endif
-
static int alpr_nand_dev_ready(struct mtd_info *mtd)
{
/*
@@ -130,9 +117,6 @@ int board_nand_init(struct nand_chip *nand)
nand->read_byte = alpr_nand_read_byte;
nand->write_buf = alpr_nand_write_buf;
nand->read_buf = alpr_nand_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = alpr_nand_verify_buf;
-#endif
nand->dev_ready = alpr_nand_dev_ready;
return 0;
diff --git a/board/seco/Kconfig b/board/seco/Kconfig
new file mode 100644
index 00000000000..dcb1ac81e02
--- /dev/null
+++ b/board/seco/Kconfig
@@ -0,0 +1,63 @@
+if TARGET_SECOMX6
+
+choice
+ prompt "SECO i.MX6 Board variant"
+
+config SECOMX6_Q7
+ bool "Q7"
+
+config SECOMX6_UQ7
+ bool "uQ7"
+
+config SECOMX6_USBC
+ bool "uSBC"
+
+endchoice
+
+choice
+ prompt "SECO i.MX6 SoC variant"
+
+config SECOMX6Q
+ bool "i.MX6Q"
+ select MX6Q
+
+config SECOMX6DL
+ bool "i.MX6DL"
+ select MX6DL
+
+config SECOMX6S
+ bool "i.MX6S"
+ select MX6S
+
+endchoice
+
+choice
+ prompt "DDR size"
+
+config SECOMX6_512MB
+ bool "512MB"
+
+config SECOMX6_1GB
+ bool "1GB"
+
+config SECOMX6_2GB
+ bool "2GB"
+
+config SECOMX6_4GB
+ bool "4GB"
+
+endchoice
+
+config IMX_CONFIG
+ default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB
+
+config SYS_BOARD
+ default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q
+
+config SYS_VENDOR
+ default "seco"
+
+config SYS_CONFIG_NAME
+ default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q
+
+endif
diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile
new file mode 100644
index 00000000000..9e37ebbb92c
--- /dev/null
+++ b/board/seco/common/Makefile
@@ -0,0 +1,2 @@
+
+obj-$(CONFIG_TARGET_SECOMX6) += mx6.o
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
new file mode 100644
index 00000000000..2f14f59f3c1
--- /dev/null
+++ b/board/seco/common/mx6.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 ECA Sinters
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <i2c.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void seco_mx6_setup_uart_iomux(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+void seco_mx6_setup_enet_iomux(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+int seco_mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+ return 0;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void seco_mx6_setup_usdhc_iomux(int id)
+{
+ switch (id) {
+ case 3:
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+ ARRAY_SIZE(usdhc3_pads));
+ break;
+
+ case 4:
+ imx_iomux_v3_setup_multiple_pads(usdhc4_pads,
+ ARRAY_SIZE(usdhc4_pads));
+ break;
+
+ default:
+ printf("Warning: invalid usdhc id (%d)\n", id);
+ break;
+ }
+}
diff --git a/board/seco/common/mx6.h b/board/seco/common/mx6.h
new file mode 100644
index 00000000000..a05db673e28
--- /dev/null
+++ b/board/seco/common/mx6.h
@@ -0,0 +1,9 @@
+#ifndef __SECO_COMMON_MX6_H
+#define __SECO_COMMON_MX6_H
+
+void seco_mx6_setup_uart_iomux(void);
+void seco_mx6_setup_enet_iomux(void);
+int seco_mx6_rgmii_rework(struct phy_device *phydev);
+void seco_mx6_setup_usdhc_iomux(int id);
+
+#endif /* __SECO_COMMON_MX6_H */
diff --git a/board/seco/mx6quq7/MAINTAINERS b/board/seco/mx6quq7/MAINTAINERS
new file mode 100644
index 00000000000..60fd4caab8f
--- /dev/null
+++ b/board/seco/mx6quq7/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6QUQ7 BOARD
+M: Boris Brezillon <boris.brezillon@free-electrons.com>
+S: Maintained
+F: board/seco/mx6quq7/
+F: include/configs/secomx6quq7.h
+F: configs/secomx6quq7_defconfig
diff --git a/board/seco/mx6quq7/Makefile b/board/seco/mx6quq7/Makefile
new file mode 100644
index 00000000000..bbf1d681905
--- /dev/null
+++ b/board/seco/mx6quq7/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 ECA Sinters
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6quq7.o
diff --git a/board/seco/mx6quq7/mx6quq7-2g.cfg b/board/seco/mx6quq7/mx6quq7-2g.cfg
new file mode 100644
index 00000000000..159120edd6c
--- /dev/null
+++ b/board/seco/mx6quq7/mx6quq7-2g.cfg
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2013 Seco USA Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* DATA STROBE */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
+
+/* DATA */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
+/* ADDRESS */
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
+
+/* CONTROL */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
+
+/* CLOCK */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
+
+/*
+ * DDR3 SETTINGS
+ * Read Data Bit Delay
+ */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+
+/* Write Leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+
+/* DQS gating, read delay, write delay calibration values */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
+
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
+
+/* write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
+
+/* Complete calibration by forced measurement: */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/*
+ * MMDC init:
+ * in DDR3, 64-bit mode, only MMDC0 is init
+ */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+
+/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+
+/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+
+/* Initialize DDR3 on CS_0 and CS_1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+
+/* P0 01c */
+/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+
+/*ZQ - Calibrationi */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
new file mode 100644
index 00000000000..ea1d4b8e497
--- /dev/null
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 ECA Sinters
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <i2c.h>
+
+#include "../common/mx6.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ seco_mx6_setup_uart_iomux();
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ seco_mx6_rgmii_rework(phydev);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret = 0;
+
+ seco_mx6_setup_enet_iomux();
+
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return -ENOMEM;
+
+ /* scan phy 4,5,6,7 */
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ free(bus);
+ return -ENOMEM;
+ }
+
+ printf("using phy at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ free(phydev);
+ free(bus);
+ printf("FEC MXC: %s:failed\n", __func__);
+ }
+#endif
+
+ return ret;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ u32 index = 0;
+ int ret;
+
+ /*
+ * Following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 eMMC on Board
+ * mmc1 Ext SD
+ */
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ seco_mx6_setup_usdhc_iomux(3);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ break;
+ case 1:
+ seco_mx6_setup_usdhc_iomux(4);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+
+ default:
+ printf("Warning: %d exceed maximum number of SD ports %d\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+
+ gpio_direction_output(IMX_GPIO_NR(2, 4), 0);
+
+ /* Set Low */
+ gpio_set_value(IMX_GPIO_NR(2, 4), 0);
+ udelay(1000);
+
+ /* Set High */
+ gpio_set_value(IMX_GPIO_NR(2, 4), 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: SECO uQ7\n");
+
+ return 0;
+}
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 73944780bfe..15e6ea69446 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -18,9 +18,6 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
static u_char sc_nand_read_byte(struct mtd_info *mtd);
static u16 sc_nand_read_word(struct mtd_info *mtd);
static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
-#endif
static int sc_nand_device_ready(struct mtd_info *mtdinfo);
#define FPGA_NAND_CMD_MASK (0x7 << 28)
@@ -102,25 +99,6 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
}
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/**
- * sc_nand_verify_buf - Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- */
-static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- if (buf[i] != sc_nand_read_byte(mtd));
- return -EFAULT;
- }
- return 0;
-}
-#endif
-
/**
* sc_nand_device_ready - Check the NAND device is ready for next command.
* @mtd: MTD device structure
@@ -178,9 +156,6 @@ int board_nand_init(struct nand_chip *nand)
nand->read_word = sc_nand_read_word;
nand->write_buf = sc_nand_write_buf;
nand->read_buf = sc_nand_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = sc_nand_verify_buf;
-#endif
return 0;
}
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 7f962dcb25a..17fa7ea6bd0 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -419,10 +419,13 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
.mode = MTD_OPS_RAW
};
- if (read)
+ if (read) {
ret = mtd_read_oob(nand, off, &ops);
- else
+ } else {
ret = mtd_write_oob(nand, off, &ops);
+ if (!ret)
+ ret = nand_verify_page_oob(nand, &ops, off);
+ }
if (ret) {
printf("%s: error at offset %llx, ret %d\n",
@@ -690,7 +693,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
else
ret = nand_write_skip_bad(nand, off, &rwsize,
NULL, maxsize,
- (u_char *)addr, 0);
+ (u_char *)addr,
+ WITH_WR_VERIFY);
#ifdef CONFIG_CMD_NAND_TRIMFFS
} else if (!strcmp(s, ".trimffs")) {
if (read) {
@@ -699,17 +703,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
maxsize, (u_char *)addr,
- WITH_DROP_FFS);
-#endif
-#ifdef CONFIG_CMD_NAND_YAFFS
- } else if (!strcmp(s, ".yaffs")) {
- if (read) {
- printf("Unknown nand command suffix '%s'.\n", s);
- return 1;
- }
- ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
- maxsize, (u_char *)addr,
- WITH_YAFFS_OOB);
+ WITH_DROP_FFS | WITH_WR_VERIFY);
#endif
} else if (!strcmp(s, ".oob")) {
/* out-of-band data */
@@ -853,11 +847,6 @@ static char nand_help_text[] =
" 'addr', skipping bad blocks and dropping any pages at the end\n"
" of eraseblocks that contain only 0xFF\n"
#endif
-#ifdef CONFIG_CMD_NAND_YAFFS
- "nand write.yaffs - addr off|partition size\n"
- " write 'size' bytes starting at offset 'off' with yaffs format\n"
- " from memory address 'addr', skipping bad blocks.\n"
-#endif
"nand erase[.spread] [clean] off size - erase 'size' bytes "
"from offset 'off'\n"
" With '.spread', erase enough for given file size, otherwise,\n"
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 6adfd55708d..cde0d705a56 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -1,5 +1,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
CONFIG_ARM=y
CONFIG_TARGET_MX6SABRESD=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_DM=y
CONFIG_DM_THERMAL=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index fb8c4decfdd..c6b3108d752 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -1,3 +1,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
CONFIG_ARM=y
CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 93efe730149..454cb400b56 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -1,3 +1,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
CONFIG_ARM=y
CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
new file mode 100644
index 00000000000..dcd681dfb74
--- /dev/null
+++ b/configs/secomx6quq7_defconfig
@@ -0,0 +1,7 @@
+CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_SECOMX6=y
+CONFIG_SECOMX6_UQ7=y
+CONFIG_SECOMX6Q=y
+CONFIG_SECOMX6_2GB=y
diff --git a/doc/README.nand b/doc/README.nand
index dee0e00a617..46d7edd179f 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -99,12 +99,6 @@ Configuration Options:
CONFIG_CMD_NAND_TORTURE
Enables the torture command (see description of this command below).
- CONFIG_MTD_NAND_ECC_JFFS2
- Define this if you want the Error Correction Code information in
- the out-of-band data to be formatted to match the JFFS2 file system.
- CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
- someone to implement.
-
CONFIG_SYS_MAX_NAND_DEVICE
The maximum number of NAND devices you want to support.
@@ -312,12 +306,6 @@ Platform specific options
NOTE:
=====
-The current NAND implementation is based on what is in recent
-Linux kernels. The old legacy implementation has been removed.
-
-If you have board code which used CONFIG_NAND_LEGACY, you'll need
-to convert to the current NAND interface for it to continue to work.
-
The Disk On Chip driver is currently broken and has been for some time.
There is a driver in drivers/mtd/nand, taken from Linux, that works with
the current NAND system but has not yet been adapted to the u-boot
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index f9ee18999ab..a9754922e8d 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -64,7 +64,7 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
return ret;
/* then write */
ret = nand_write_skip_bad(nand, start, &count, &actual,
- lim, buf, 0);
+ lim, buf, WITH_WR_VERIFY);
}
if (ret != 0) {
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 41689b5165d..a3970745c95 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -405,18 +405,6 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
goto err;
}
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
- /* Send command to read back the data */
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
-
- if (chip->verify_buf(mtd, buf, mtd->writesize)) {
- ret = -EIO;
- goto err;
- }
-
- /* Make sure the next page prog is preceded by a status read */
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
-#endif
err:
/* restore ECC layout */
if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 3372b642125..e85832d319d 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -561,41 +561,6 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
len, avail);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/*
- * Verify buffer against the FCM Controller Data Buffer
- */
-static int fsl_elbc_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- int i;
-
- if (len < 0) {
- printf("write_buf of %d bytes", len);
- return -EINVAL;
- }
-
- if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
- printf("verify_buf beyond end of buffer "
- "(%d requested, %u available)\n",
- len, ctrl->read_bytes - ctrl->index);
-
- ctrl->index = ctrl->read_bytes;
- return -EINVAL;
- }
-
- for (i = 0; i < len; i++)
- if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
- break;
-
- ctrl->index += len;
- return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
-}
-#endif
-
/* This function is called after Program and Erase Operations to
* check for success or failure.
*/
@@ -727,9 +692,6 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
nand->read_byte = fsl_elbc_read_byte;
nand->write_buf = fsl_elbc_write_buf;
nand->read_buf = fsl_elbc_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = fsl_elbc_verify_buf;
-#endif
nand->select_chip = fsl_elbc_select_chip;
nand->cmdfunc = fsl_elbc_cmdfunc;
nand->waitfunc = fsl_elbc_wait;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index b283eaea345..7903eebd537 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -683,41 +683,6 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
__func__, len, avail);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/*
- * Verify buffer against the IFC Controller Data Buffer
- */
-static int fsl_ifc_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
- struct fsl_ifc_ctrl *ctrl = priv->ctrl;
- int i;
-
- if (len < 0) {
- printf("%s of %d bytes", __func__, len);
- return -EINVAL;
- }
-
- if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
- printf("%s beyond end of buffer "
- "(%d requested, %u available)\n",
- __func__, len, ctrl->read_bytes - ctrl->index);
-
- ctrl->index = ctrl->read_bytes;
- return -EINVAL;
- }
-
- for (i = 0; i < len; i++)
- if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
- break;
-
- ctrl->index += len;
- return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
-}
-#endif
-
/* This function is called after Program and Erase Operations to
* check for success or failure.
*/
@@ -940,9 +905,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
nand->write_buf = fsl_ifc_write_buf;
nand->read_buf = fsl_ifc_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = fsl_ifc_verify_buf;
-#endif
nand->select_chip = fsl_ifc_select_chip;
nand->cmdfunc = fsl_ifc_cmdfunc;
nand->waitfunc = fsl_ifc_wait;
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 65ce98ad5e3..5426c321141 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -153,21 +153,6 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
buf[i] = in_8(chip->IO_ADDR_R);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++) {
- if (buf[i] != in_8(chip->IO_ADDR_R))
- return -EFAULT;
- }
-
- return 0;
-}
-#endif
-
static int nand_dev_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
@@ -193,9 +178,6 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
chip->read_byte = upm_nand_read_byte;
chip->read_buf = upm_nand_read_buf;
chip->write_buf = upm_nand_write_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- chip->verify_buf = upm_nand_verify_buf;
-#endif
if (fun->dev_ready)
chip->dev_ready = nand_dev_ready;
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 7233bfc1279..e621c3665e5 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -459,29 +459,6 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/* Compare buffer with NAND flash */
-static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
- const u_char * buf, int len)
-{
- u_char tmp[256];
- uint bsize;
-
- while (len) {
- bsize = min(len, 256);
- mpc5121_nfc_read_buf(mtd, tmp, bsize);
-
- if (memcmp(buf, tmp, bsize))
- return 1;
-
- buf += bsize;
- len -= bsize;
- }
-
- return 0;
-}
-#endif
-
/* Read byte from NFC buffers */
static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
{
@@ -609,9 +586,6 @@ int board_nand_init(struct nand_chip *chip)
chip->read_word = mpc5121_nfc_read_word;
chip->read_buf = mpc5121_nfc_read_buf;
chip->write_buf = mpc5121_nfc_write_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- chip->verify_buf = mpc5121_nfc_verify_buf;
-#endif
chip->select_chip = mpc5121_nfc_select_chip;
chip->bbt_options = NAND_BBT_USE_FLASH;
chip->ecc.mode = NAND_ECC_SOFT;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 2e5b5b9bf98..f12b07e7adc 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -949,34 +949,6 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
host->col_addr = col;
}
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/*
- * Used by the upper layer to verify the data in NAND Flash
- * with the data in the buf.
- */
-static int mxc_nand_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- u_char tmp[256];
- uint bsize;
-
- while (len) {
- bsize = min(len, 256);
- mxc_nand_read_buf(mtd, tmp, bsize);
-
- if (memcmp(buf, tmp, bsize))
- return 1;
-
- buf += bsize;
- len -= bsize;
- }
-
- return 0;
-}
-#endif
-#endif
-
/*
* This function is used by upper layer for select and
* deselect of the NAND chip
@@ -1207,11 +1179,6 @@ int board_nand_init(struct nand_chip *this)
this->read_word = mxc_nand_read_word;
this->write_buf = mxc_nand_write_buf;
this->read_buf = mxc_nand_read_buf;
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- this->verify_buf = mxc_nand_verify_buf;
-#endif
-#endif
host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
#ifdef MXC_NFC_V3_2
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7a064ab1bf9..2d2b938633c 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -453,7 +453,7 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
d->cmd.data =
MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
- MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+ MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
d->cmd.address = 0;
@@ -510,7 +510,7 @@ static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
d->cmd.data =
MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
- (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
(length << MXS_DMA_DESC_BYTES_OFFSET);
d->cmd.address = (dma_addr_t)nand_info->data_buf;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 6db6566e733..c0e381ad2d1 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -361,51 +361,6 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
ioread8_rep(chip->IO_ADDR_R, buf, len);
}
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/**
- * nand_verify_buf - [DEFAULT] Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- *
- * Default verify function for 8bit buswidth.
- */
-static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++)
- if (buf[i] != readb(chip->IO_ADDR_R))
- return -EFAULT;
- return 0;
-}
-
-/**
- * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- *
- * Default verify function for 16bit buswidth.
- */
-static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
- u16 *p = (u16 *) buf;
- len >>= 1;
-
- for (i = 0; i < len; i++)
- if (p[i] != readw(chip->IO_ADDR_R))
- return -EFAULT;
-
- return 0;
-}
-#endif
-#endif
-
/**
* nand_write_buf16 - [DEFAULT] write buffer to chip
* @mtd: MTD device structure
@@ -2435,20 +2390,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
status = chip->waitfunc(mtd, chip);
}
-
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- /* Send command to read back the data */
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
-
- if (chip->verify_buf(mtd, buf, mtd->writesize))
- return -EIO;
-
- /* Make sure the next page prog is preceded by a status read */
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
-#endif
-#endif
-
return 0;
}
@@ -3139,12 +3080,6 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
if (!chip->scan_bbt)
chip->scan_bbt = nand_default_bbt;
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- if (!chip->verify_buf)
- chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
-#endif
-#endif
if (!chip->controller) {
chip->controller = &chip->hwcontrol;
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index afdd160d816..12dd26a33fa 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -464,6 +464,87 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
#endif
/**
+ * nand_verify_page_oob:
+ *
+ * Verify a page of NAND flash, including the OOB.
+ * Reads page of NAND and verifies the contents and OOB against the
+ * values in ops.
+ *
+ * @param nand NAND device
+ * @param ops MTD operations, including data to verify
+ * @param ofs offset in flash
+ * @return 0 in case of success
+ */
+int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
+{
+ int rval;
+ struct mtd_oob_ops vops;
+ size_t verlen = nand->writesize + nand->oobsize;
+
+ memcpy(&vops, ops, sizeof(vops));
+
+ vops.datbuf = malloc(verlen);
+
+ if (!vops.datbuf)
+ return -ENOMEM;
+
+ vops.oobbuf = vops.datbuf + nand->writesize;
+
+ rval = mtd_read_oob(nand, ofs, &vops);
+ if (!rval)
+ rval = memcmp(ops->datbuf, vops.datbuf, vops.len);
+ if (!rval)
+ rval = memcmp(ops->oobbuf, vops.oobbuf, vops.ooblen);
+
+ free(vops.datbuf);
+
+ return rval ? -EIO : 0;
+}
+
+/**
+ * nand_verify:
+ *
+ * Verify a region of NAND flash.
+ * Reads NAND in page-sized chunks and verifies the contents against
+ * the contents of a buffer. The offset into the NAND must be
+ * page-aligned, and the function doesn't handle skipping bad blocks.
+ *
+ * @param nand NAND device
+ * @param ofs offset in flash
+ * @param len buffer length
+ * @param buf buffer to read from
+ * @return 0 in case of success
+ */
+int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
+{
+ int rval = 0;
+ size_t verofs;
+ size_t verlen = nand->writesize;
+ uint8_t *verbuf = malloc(verlen);
+
+ if (!verbuf)
+ return -ENOMEM;
+
+ /* Read the NAND back in page-size groups to limit malloc size */
+ for (verofs = ofs; verofs < ofs + len;
+ verofs += verlen, buf += verlen) {
+ verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs));
+ rval = nand_read(nand, verofs, &verlen, verbuf);
+ if (!rval || (rval == -EUCLEAN))
+ rval = memcmp(buf, verbuf, verlen);
+
+ if (rval)
+ break;
+ }
+
+ free(verbuf);
+
+ return rval ? -EIO : 0;
+}
+
+
+
+/**
* nand_write_skip_bad:
*
* Write image to NAND flash.
@@ -499,24 +580,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
if (actual)
*actual = 0;
-#ifdef CONFIG_CMD_NAND_YAFFS
- if (flags & WITH_YAFFS_OOB) {
- if (flags & ~WITH_YAFFS_OOB)
- return -EINVAL;
-
- int pages;
- pages = nand->erasesize / nand->writesize;
- blocksize = (pages * nand->oobsize) + nand->erasesize;
- if (*length % (nand->writesize + nand->oobsize)) {
- printf("Attempt to write incomplete page"
- " in yaffs mode\n");
- return -EINVAL;
- }
- } else
-#endif
- {
- blocksize = nand->erasesize;
- }
+ blocksize = nand->erasesize;
/*
* nand_write() handles unaligned, partial page writes.
@@ -554,6 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
if (!need_skip && !(flags & WITH_DROP_FFS)) {
rval = nand_write(nand, offset, length, buffer);
+
+ if ((flags & WITH_WR_VERIFY) && !rval)
+ rval = nand_verify(nand, offset, *length, buffer);
+
if (rval == 0)
return 0;
@@ -581,48 +649,22 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
else
write_size = blocksize - block_offset;
-#ifdef CONFIG_CMD_NAND_YAFFS
- if (flags & WITH_YAFFS_OOB) {
- int page, pages;
- size_t pagesize = nand->writesize;
- size_t pagesize_oob = pagesize + nand->oobsize;
- struct mtd_oob_ops ops;
-
- ops.len = pagesize;
- ops.ooblen = nand->oobsize;
- ops.mode = MTD_OPS_AUTO_OOB;
- ops.ooboffs = 0;
-
- pages = write_size / pagesize_oob;
- for (page = 0; page < pages; page++) {
- WATCHDOG_RESET();
-
- ops.datbuf = p_buffer;
- ops.oobbuf = ops.datbuf + pagesize;
-
- rval = mtd_write_oob(nand, offset, &ops);
- if (rval != 0)
- break;
-
- offset += pagesize;
- p_buffer += pagesize_oob;
- }
- }
- else
-#endif
- {
- truncated_write_size = write_size;
+ truncated_write_size = write_size;
#ifdef CONFIG_CMD_NAND_TRIMFFS
- if (flags & WITH_DROP_FFS)
- truncated_write_size = drop_ffs(nand, p_buffer,
- &write_size);
+ if (flags & WITH_DROP_FFS)
+ truncated_write_size = drop_ffs(nand, p_buffer,
+ &write_size);
#endif
- rval = nand_write(nand, offset, &truncated_write_size,
- p_buffer);
- offset += write_size;
- p_buffer += write_size;
- }
+ rval = nand_write(nand, offset, &truncated_write_size,
+ p_buffer);
+
+ if ((flags & WITH_WR_VERIFY) && !rval)
+ rval = nand_verify(nand, offset,
+ truncated_write_size, p_buffer);
+
+ offset += write_size;
+ p_buffer += write_size;
if (rval != 0) {
printf("NAND write to offset %llx failed %d\n",
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 265959502d8..8a68cb0a67a 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -118,21 +118,6 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
out_be32((u32 *)(base + NDFC_DATA), *p++);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (; len > 0; len -= 4)
- if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
- return -1;
-
- return 0;
-}
-#endif
-
/*
* Read a byte from the NDFC.
*/
@@ -207,9 +192,6 @@ int board_nand_init(struct nand_chip *nand)
#endif
nand->write_buf = ndfc_write_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = ndfc_verify_buf;
-#endif
nand->read_byte = ndfc_read_byte;
chip++;
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 928d58b3a73..d98dd28800e 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -146,6 +146,7 @@ struct vf610_nfc {
void __iomem *regs;
uint column;
int spareonly;
+ int page_sz;
int page;
/* Status and ID are in alternate locations. */
int alt_buf;
@@ -329,6 +330,11 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
ROW_ADDR_SHIFT, page);
}
+static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
+{
+ __raw_writel(size, regbase + NFC_SECTOR_SIZE);
+}
+
/* Send command to NAND chip */
static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
int column, int page)
@@ -342,12 +348,14 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
switch (command) {
case NAND_CMD_PAGEPROG:
nfc->page = -1;
+ vf610_nfc_transfer_size(nfc->regs, nfc->page_sz);
vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
command, PROGRAM_PAGE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_RESET:
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
break;
/*
@@ -363,14 +371,15 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
if (nfc->page == page)
return;
nfc->page = page;
+ vf610_nfc_transfer_size(nfc->regs, nfc->page_sz);
vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_ERASE1:
- if (nfc->page == page)
- nfc->page = -1;
+ nfc->page = -1;
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_commands(nfc->regs, command,
NAND_CMD_ERASE2, ERASE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
@@ -378,11 +387,13 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
case NAND_CMD_READID:
nfc->alt_buf = ALT_BUF_ID;
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
break;
case NAND_CMD_STATUS:
nfc->alt_buf = ALT_BUF_STAT;
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_command(nfc->regs, command,
STATUS_READ_CMD_CODE);
break;
@@ -580,7 +591,6 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
struct nand_chip *chip;
struct vf610_nfc *nfc;
int err = 0;
- int page_sz;
struct vf610_nfc_config cfg = {
.hardware_ecc = 1,
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
@@ -634,9 +644,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
chip->bbt_td = &bbt_main_descr;
chip->bbt_md = &bbt_mirror_descr;
- page_sz = PAGE_2K + OOB_64;
- page_sz += cfg.width == 16 ? 1 : 0;
- vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+ nfc->page_sz = PAGE_2K + OOB_64;
+ nfc->page_sz += cfg.width == 16 ? 1 : 0;
/* Set configuration register. */
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
@@ -665,16 +674,15 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
chip->ecc.mode = NAND_ECC_SOFT; /* default */
- page_sz = mtd->writesize + mtd->oobsize;
+ nfc->page_sz = mtd->writesize + mtd->oobsize;
/* Single buffer only, max 256 OOB minus ECC status */
- if (page_sz > PAGE_2K + 256 - 8) {
+ if (nfc->page_sz > PAGE_2K + 256 - 8) {
dev_err(nfc->dev, "Unsupported flash size\n");
err = -ENXIO;
goto error;
}
- page_sz += cfg.width == 16 ? 1 : 0;
- vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+ nfc->page_sz += cfg.width == 16 ? 1 : 0;
if (cfg.hardware_ecc) {
if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c
index 6b8563366b8..834c5bd259d 100644
--- a/drivers/spi/cf_qspi.c
+++ b/drivers/spi/cf_qspi.c
@@ -20,7 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
#define clamp(x, low, high) (min(max(low, x), high))
-#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s)
+#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
struct cf_qspi_slave {
struct spi_slave slave; /* Specific bus:cs ID for each device */
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 879a809cba4..6ce11012e89 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -20,13 +20,6 @@ struct cf_spi_slave {
int charbit;
};
-int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
- void *din, ulong flags);
-struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode);
-void cfspi_init(void);
-void cfspi_tx(u32 ctrl, u16 data);
-u16 cfspi_rx(void);
-
extern void cfspi_port_conf(void);
extern int cfspi_claim_bus(uint bus, uint cs);
extern void cfspi_release_bus(uint bus, uint cs);
@@ -46,7 +39,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_MODE_MOD 0x00200000
#define SPI_DBLRATE 0x00100000
-void cfspi_init(void)
+static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct cf_spi_slave, slave);
+}
+
+static void cfspi_init(void)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
@@ -84,7 +82,7 @@ void cfspi_init(void)
#endif
}
-void cfspi_tx(u32 ctrl, u16 data)
+static void cfspi_tx(u32 ctrl, u16 data)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
@@ -93,7 +91,7 @@ void cfspi_tx(u32 ctrl, u16 data)
dspi->tfr = (ctrl | data);
}
-u16 cfspi_rx(void)
+static u16 cfspi_rx(void)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
@@ -102,10 +100,10 @@ u16 cfspi_rx(void)
return (dspi->rfr & 0xFFFF);
}
-int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
- void *din, ulong flags)
+static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
+ void *din, ulong flags)
{
- struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave;
+ struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
static u32 ctrl = 0;
@@ -176,7 +174,8 @@ int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
return 0;
}
-struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode)
+static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
+ uint mode)
{
/*
* bit definition for mode:
@@ -326,7 +325,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
void spi_free_slave(struct spi_slave *slave)
{
- free(slave);
+ struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+
+ free(cfslave);
}
int spi_claim_bus(struct spi_slave *slave)
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0ec5b9d8592..bf18362baaf 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -32,9 +32,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (!ds)
return NULL;
- ds->slave.bus = bus;
- ds->slave.cs = cs;
-
switch (bus) {
case SPI0_BUS:
ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 2624844d528..8f5c0fc8029 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv)
if (!priv->fifo_len) {
u32 fifo;
- for (fifo = 2; fifo <= 256; fifo++) {
+ for (fifo = 1; fifo < 256; fifo++) {
dw_writew(priv, DW_SPI_TXFLTR, fifo);
if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
break;
}
- priv->fifo_len = (fifo == 2) ? 0 : fifo - 1;
+ priv->fifo_len = (fifo == 1) ? 0 : fifo;
dw_writew(priv, DW_SPI_TXFLTR, 0);
}
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
index 267e4d83bd0..c7d64804780 100644
--- a/drivers/spi/ftssp010_spi.c
+++ b/drivers/spi/ftssp010_spi.c
@@ -431,7 +431,9 @@ free_out:
void spi_free_slave(struct spi_slave *slave)
{
- free(slave);
+ struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+
+ free(chip);
}
int spi_claim_bus(struct spi_slave *slave)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 857b60455a9..3356c0f072e 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -109,10 +109,17 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
slave->op_mode_rx = 8;
#endif
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+ memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+ QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS);
+#else
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS;
+#endif
writel(memval, &qslave->base->setup0);
}
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index d5993b4d26d..1d18d4b269f 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -20,7 +20,6 @@ struct watchdog_regs {
#define WCR_WDE 0x04 /* WDOG enable */
#define WCR_WDT 0x08
#define WCR_SRS 0x10
-#define WCR_WDW 0x80
#define SET_WCR_WT(x) (x << 8)
#ifdef CONFIG_IMX_WATCHDOG
@@ -47,7 +46,7 @@ void hw_watchdog_init(void)
#endif
timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
- WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
+ SET_WCR_WT(timeout), &wdog->wcr);
hw_watchdog_reset();
}
#endif
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 838a0b18c38..dca1ca5abda 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -391,7 +391,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 6aaaaa43f0f..047ed8b1bb3 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -198,7 +198,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 59a8d1b5d17..ceee0e4d49d 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -320,7 +320,6 @@ combinations. this should be removed later
/* NAND */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index e24b9233687..7c45c3617ae 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -234,7 +234,6 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index be1750f6278..3a6e9811d51 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -53,7 +53,6 @@
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_NAND_YAFFS
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index d9a19c3694a..9cea76ae9b9 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -272,7 +272,6 @@
"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 1384f360bdf..fbf38c88d9f 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -245,7 +245,6 @@
"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 85f5c40edef..521904daad6 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -283,7 +283,6 @@
* NAND Flash on the Local Bus
*/
#define CONFIG_CMD_NAND 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_FSL_ELBC 1
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 27221648e42..dc09b1f8704 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -308,7 +308,6 @@
CONFIG_SYS_NAND_BASE + 0x80000, \
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 4da247c51ae..e624c717ffa 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -194,7 +194,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 0b07876e780..5e7bc49dcf4 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -303,7 +303,6 @@
CONFIG_SYS_NAND_BASE + 0x80000,\
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index cd6a39c6571..ccf3ce3bac9 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -444,7 +444,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#if defined(CONFIG_P1010RDB_PA)
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 437111070da..795e3b5e186 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -290,7 +290,6 @@
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index a8b7817a8ef..d65c461fda5 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -136,7 +136,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index d8d30bb2805..f99da6562aa 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -251,7 +251,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 3f02cede320..2927043df49 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -398,7 +398,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index bd40d6ac93c..84e8336a724 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -379,7 +379,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 92f5f56718c..faf8c9dc7ec 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -308,7 +308,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 52633181ad4..6cc95ef2d10 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -341,7 +341,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index ff6d2c1d37e..046aa48baa1 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -357,7 +357,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index db6b42ea0f1..faaf22c9bf3 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -328,7 +328,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index dd7d52f293a..cfe6557caa1 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -281,7 +281,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index b644a6ce8be..c1ad35a018b 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -467,7 +467,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 94078f54819..6aee6db3f38 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -62,7 +62,6 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_YAFFS
#define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 225ffdd0a5b..8e27ae4b728 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -248,7 +248,6 @@
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index dee2b11056e..8fe0e6c16ae 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -77,6 +77,7 @@
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+#define CONFIG_QSPI_QUAD_SUPPORT
/*
* Default to using SPI for environment, etc.
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index ce61a1621c0..b79000e706a 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -153,7 +153,6 @@
/* JFFS2 */
#ifdef CONFIG_CMD_JFFS2
-#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_NAND
#endif
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 2384864eb02..c1ca56c692e 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -214,7 +214,6 @@
#define CONFIG_SYS_NAND_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 949b3dadb38..b70b5b19f5c 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -167,7 +167,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 3dc4da391b3..5de416d117b 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -251,7 +251,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index f80efedeb2f..e0435cc0a7a 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -191,7 +191,6 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 21c654b6b12..dad49f96df4 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -249,4 +249,11 @@
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
#endif
+#define CONFIG_IMX6_THERMAL
+
+#define CONFIG_CMD_FUSE
+#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
+#define CONFIG_MXC_OCOTP
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5f27c2a41a8..a5f97176ce7 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -494,7 +494,6 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#if defined(CONFIG_P1020RDB_PD)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
new file mode 100644
index 00000000000..46ffb7a31c9
--- /dev/null
+++ b/include/configs/secomx6quq7.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2013 Seco S.r.l
+ *
+ * Configuration settings for the Seco Boards.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_BOARD_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \
+ "ip_server=10.0.0.1\0" \
+ "nfs_path=/targetfs \0" \
+ "memory=mem=1024M\0" \
+ "bootdev=mmc dev 0; ext2load mmc 0:1\0" \
+ "root=root=/dev/mmcblk0p1\0" \
+ "option=rootwait rw fixrtc rootflags=barrier=1\0" \
+ "cpu_freq=arm_freq=996\0" \
+ "setbootargs=setenv bootargs console=ttymxc1,115200 ${root}" \
+ " ${option} ${memory} ${cpu_freq}\0" \
+ "setbootargs_nfs=setenv bootargs console=ttymxc1,115200" \
+ " root=/dev/nfs nfsroot=${ip_server}:${nfs_path}" \
+ " nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp" \
+ " ${memory} ${cpu_freq}\0" \
+ "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \
+ "bootcmd=run setbootargs; run setbootdev; run boot_dev;" \
+ " bootm 0x10800000\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+ #define CONFIG_ENV_OFFSET (6 * 128 * 1024)
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index bce94b3fdc6..107f01a07ec 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -186,7 +186,6 @@
*/
#define CONFIG_SYS_NAND_BASE 0x61000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index d6b61435006..988a2e8bfeb 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -131,7 +131,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
#define CONFIG_NAND_FSL_ELBC
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 4536b94e916..ac3f4f1c84a 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -122,7 +122,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
#define CONFIG_NAND_FSL_ELBC
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8438490fe42..bc927ecc599 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -678,11 +678,6 @@ struct nand_chip {
void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
-#endif
-#endif
void (*select_chip)(struct mtd_info *mtd, int chip);
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
diff --git a/include/nand.h b/include/nand.h
index 15e31ab538b..d2a53ab856e 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -82,34 +82,8 @@ static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
* declarations from nand_util.c
****************************************************************************/
-struct nand_write_options {
- u_char *buffer; /* memory block containing image to write */
- ulong length; /* number of bytes to write */
- ulong offset; /* start address in NAND */
- int quiet; /* don't display progress messages */
- int autoplace; /* if true use auto oob layout */
- int forcejffs2; /* force jffs2 oob layout */
- int forceyaffs; /* force yaffs oob layout */
- int noecc; /* write without ecc */
- int writeoob; /* image contains oob data */
- int pad; /* pad to page size */
- int blockalign; /* 1|2|4 set multiple of eraseblocks
- * to align to */
-};
-
-typedef struct nand_write_options nand_write_options_t;
typedef struct mtd_oob_ops mtd_oob_ops_t;
-struct nand_read_options {
- u_char *buffer; /* memory block in which read image is written*/
- ulong length; /* number of bytes to read */
- ulong offset; /* start address in NAND */
- int quiet; /* don't display progress messages */
- int readoob; /* put oob data in image */
-};
-
-typedef struct nand_read_options nand_read_options_t;
-
struct nand_erase_options {
loff_t length; /* number of bytes to erase */
loff_t offset; /* first address in NAND to erase */
@@ -130,15 +104,16 @@ typedef struct nand_erase_options nand_erase_options_t;
int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
size_t *actual, loff_t lim, u_char *buffer);
-#define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag
- * is a 'mode' meaning it cannot be mixed with
- * other flags */
-#define WITH_DROP_FFS (1 << 1) /* drop trailing all-0xff pages */
+#define WITH_DROP_FFS (1 << 0) /* drop trailing all-0xff pages */
+#define WITH_WR_VERIFY (1 << 1) /* verify data was written correctly */
int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
size_t *actual, loff_t lim, u_char *buffer, int flags);
int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
int nand_torture(nand_info_t *nand, loff_t offset);
+int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops,
+ loff_t ofs);
+int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf);
#define NAND_LOCK_STATUS_TIGHT 0x01
#define NAND_LOCK_STATUS_UNLOCK 0x04