diff options
-rw-r--r-- | arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi | 4 | ||||
-rw-r--r-- | board/toradex/smarc-imx95/spl.c | 42 | ||||
-rw-r--r-- | board/toradex/verdin-imx95/spl.c | 50 |
3 files changed, 96 insertions, 0 deletions
diff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi index 19f21eb8417..97f321defa7 100644 --- a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi @@ -46,6 +46,10 @@ bootph-pre-ram; }; +&pinctrl_ctrl_sleep_moci { + bootph-pre-ram; +}; + &pinctrl_io_exp_int { bootph-pre-ram; }; diff --git a/board/toradex/smarc-imx95/spl.c b/board/toradex/smarc-imx95/spl.c index fe29b792eb2..cd161c77301 100644 --- a/board/toradex/smarc-imx95/spl.c +++ b/board/toradex/smarc-imx95/spl.c @@ -25,6 +25,24 @@ DECLARE_GLOBAL_DATA_PTR; #define EC_I2C_BUS 3 +#define GPIO1_PCNS_ADDR (GPIO1_BASE_ADDR + 0x10) +#define GPIO1_ICNS_ADDR (GPIO1_BASE_ADDR + 0x14) +#define GPIO1_PCNP_ADDR (GPIO1_BASE_ADDR + 0x18) +#define GPIO1_ICNP_ADDR (GPIO1_BASE_ADDR + 0x1C) + +/* Defines to encode the GPIO1 access protection */ +#define GPIO_PCNS_I2C_GP_CK (0x4UL) +#define GPIO_PCNS_I2C_GP_DAT (0x8UL) +#define GPIO_PCNS_PMIC_RTC_IRQ_N (0x400UL) +#define GPIO_PCNS_EC_MCU_INT (0x800UL) +#define GPIO_PCNS_CTRL_IO_EXP_INT_B (0x4000UL) + +#define GPIO_PCNP_I2C_GP_CK (0x4UL) +#define GPIO_PCNP_I2C_GP_DAT (0x8UL) +#define GPIO_PCNP_PMIC_RTC_IRQ_N (0x400UL) +#define GPIO_PCNP_EC_MCU_INT (0x800UL) +#define GPIO_PCNP_CTRL_IO_EXP_INT_B (0x4000UL) + int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -43,6 +61,28 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) } } +void spl_board_prepare_for_boot(void) +{ + /* + * Configure non-secure, non-privileged access to + * GPIO1 registers and interrupts + */ + writel(GPIO_PCNS_I2C_GP_CK | + GPIO_PCNS_I2C_GP_DAT | + GPIO_PCNS_PMIC_RTC_IRQ_N | + GPIO_PCNS_EC_MCU_INT | + GPIO_PCNS_CTRL_IO_EXP_INT_B, + GPIO1_PCNS_ADDR); + writel(0x1, GPIO1_ICNS_ADDR); + writel(GPIO_PCNP_I2C_GP_CK | + GPIO_PCNP_I2C_GP_DAT | + GPIO_PCNP_PMIC_RTC_IRQ_N | + GPIO_PCNP_EC_MCU_INT | + GPIO_PCNP_CTRL_IO_EXP_INT_B, + GPIO1_PCNP_ADDR); + writel(0x1, GPIO1_ICNP_ADDR); +} + static void ec_boot_notify(void) { struct udevice *bus; @@ -113,6 +153,8 @@ void board_init_f(ulong dummy) printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); + disable_smmuv3(); + /* Set ARM CPU freq to max rate */ clock_init_late(); diff --git a/board/toradex/verdin-imx95/spl.c b/board/toradex/verdin-imx95/spl.c index 76d07f4e49b..abb2a94cd6d 100644 --- a/board/toradex/verdin-imx95/spl.c +++ b/board/toradex/verdin-imx95/spl.c @@ -23,6 +23,28 @@ DECLARE_GLOBAL_DATA_PTR; +#define GPIO1_PCNS_ADDR (GPIO1_BASE_ADDR + 0x10) +#define GPIO1_ICNS_ADDR (GPIO1_BASE_ADDR + 0x14) +#define GPIO1_PCNP_ADDR (GPIO1_BASE_ADDR + 0x18) +#define GPIO1_ICNP_ADDR (GPIO1_BASE_ADDR + 0x1C) + +/* Defines to encode the GPIO1 access protection */ +#define GPIO_PCNS_CTRL_I2C_SCL (0x4UL) +#define GPIO_PCNS_CTRL_I2C_SDA (0x8UL) +#define GPIO_PCNS_CTRL_WAKE1_MICO_N (0x400UL) +#define GPIO_PCNS_PMIC_EN_WIFI (0x800UL) +#define GPIO_PCNS_ETH_2_RGMII_INT_N (0x1000UL) +#define GPIO_PCNS_IO_EXP_INT_N (0x2000UL) +#define GPIO_PCNS_CTRL_SLEEP_MOCI_N (0x4000UL) + +#define GPIO_PCNP_CTRL_I2C_SCL (0x4UL) +#define GPIO_PCNP_CTRL_I2C_SDA (0x8UL) +#define GPIO_PCNP_CTRL_WAKE1_MICO_N (0x400UL) +#define GPIO_PCNP_PMIC_EN_WIFI (0x800UL) +#define GPIO_PCNP_ETH_2_RGMII_INT_N (0x1000UL) +#define GPIO_PCNP_IO_EXP_INT_N (0x2000UL) +#define GPIO_PCNP_CTRL_SLEEP_MOCI_N (0x4000UL) + int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -50,6 +72,32 @@ void spl_board_init(void) printf("Fail to start RNG: %d\n", ret); } +void spl_board_prepare_for_boot(void) +{ + /* + * Configure non-secure, non-privileged access to + * GPIO1 registers and interrupts + */ + writel(GPIO_PCNS_CTRL_I2C_SCL | + GPIO_PCNS_CTRL_I2C_SDA | + GPIO_PCNS_CTRL_WAKE1_MICO_N | + GPIO_PCNS_PMIC_EN_WIFI | + GPIO_PCNS_ETH_2_RGMII_INT_N | + GPIO_PCNS_IO_EXP_INT_N | + GPIO_PCNS_CTRL_SLEEP_MOCI_N, + GPIO1_PCNS_ADDR); + writel(0x1, GPIO1_ICNS_ADDR); + writel(GPIO_PCNP_CTRL_I2C_SCL | + GPIO_PCNP_CTRL_I2C_SDA | + GPIO_PCNP_CTRL_WAKE1_MICO_N | + GPIO_PCNP_PMIC_EN_WIFI | + GPIO_PCNP_ETH_2_RGMII_INT_N | + GPIO_PCNP_IO_EXP_INT_N | + GPIO_PCNP_CTRL_SLEEP_MOCI_N, + GPIO1_PCNP_ADDR); + writel(0x1, GPIO1_ICNP_ADDR); +} + void board_init_f(ulong dummy) { u32 state = 0; @@ -80,6 +128,8 @@ void board_init_f(ulong dummy) printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); + disable_smmuv3(); + /* Set ARM CPU freq to max rate */ clock_init_late(); |