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-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c2
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c2
-rw-r--r--board/sbc8548/sbc8548.c2
-rw-r--r--board/sbc8641d/sbc8641d.c4
-rw-r--r--cpu/mpc85xx/mp.c6
-rw-r--r--cpu/mpc85xx/release.S3
-rw-r--r--cpu/mpc85xx/spd_sdram.c4
-rw-r--r--cpu/mpc86xx/spd_sdram.c4
-rw-r--r--fs/jffs2/jffs2_1pass.c4
-rw-r--r--include/asm-ppc/immap_85xx.h6
-rw-r--r--include/asm-ppc/immap_86xx.h4
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/lwmon5.h2
-rw-r--r--include/configs/sbc8641d.h2
-rw-r--r--lib_ppc/cache.c3
-rw-r--r--post/board/lwmon/Makefile4
-rw-r--r--post/board/lwmon5/sysmon.c57
-rw-r--r--post/board/lwmon5/watchdog.c5
-rw-r--r--post/board/netta/Makefile4
-rw-r--r--post/cpu/mpc8xx/Makefile5
-rw-r--r--tools/.gitignore1
21 files changed, 81 insertions, 45 deletions
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index d9a740ee0d..3a855b5903 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -192,7 +192,7 @@ long int fixed_sdram(void)
ddr->cs0_bnds = 0x0000001f;
ddr->cs0_config = 0x80010202;
- ddr->ext_refrec = 0x00000000;
+ ddr->timing_cfg_3 = 0x00000000;
ddr->timing_cfg_0 = 0x00260802;
ddr->timing_cfg_1 = 0x3935d322;
ddr->timing_cfg_2 = 0x14904cc8;
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 31e7d67d04..bb1f927b95 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -130,7 +130,7 @@ fixed_sdram(void)
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 8a6ced3864..46496da60b 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -299,7 +299,7 @@ long int fixed_sdram (void)
ddr->cs1_config = 0x80010101;
ddr->cs2_config = 0x00000000;
ddr->cs3_config = 0x00000000;
- ddr->ext_refrec = 0x00000000;
+ ddr->timing_cfg_3 = 0x00000000;
ddr->timing_cfg_0 = 0x00220802;
ddr->timing_cfg_1 = 0x38377322;
ddr->timing_cfg_2 = 0x0fa044C7;
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index b3dd9c8657..519f332784 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -135,7 +135,7 @@ long int fixed_sdram (void)
ddr->cs1_config = CFG_DDR_CS1_CONFIG;
ddr->cs2_config = CFG_DDR_CS2_CONFIG;
ddr->cs3_config = CFG_DDR_CS3_CONFIG;
- ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
@@ -166,7 +166,7 @@ long int fixed_sdram (void)
ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
- ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
+ ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH;
ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index e733f7b00a..a527cf3047 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -103,6 +103,10 @@ int cpu_release(int nr, int argc, char *argv[])
}
table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
+
+ /* ensure all table updates complete before final address write */
+ eieio();
+
table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
return 0;
@@ -153,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg)
/* wait for everyone */
while (timeout) {
int i;
- for (i = 1; i < CONFIG_NR_CPUS; i++) {
+ for (i = 0; i < CONFIG_NR_CPUS; i++) {
if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
cpu_up_mask |= (1 << i);
};
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 3b7366ff69..a47edaea62 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -114,6 +114,7 @@ __secondary_start_page:
lwz r4,ENTRY_ADDR_LOWER(r10)
andi. r11,r4,1
bne 2b
+ isync
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
@@ -169,7 +170,7 @@ __secondary_start_page:
mtspr SPRN_SRR1,r13
rfi
- .align 3
+ .align L1_CACHE_SHIFT
.globl __spin_table
__spin_table:
.space CONFIG_NR_CPUS*ENTRY_SIZE
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 435458a189..e3a824999c 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -610,8 +610,8 @@ spd_sdram(void)
/*
* Sneak in some Extended Refresh Recovery.
*/
- ddr->ext_refrec = (trfc_high << 16);
- debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+ ddr->timing_cfg_3 = (trfc_high << 16);
+ debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
ddr->timing_cfg_1 =
(0
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 60a7818989..8485841a45 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
/*
* Sneak in some Extended Refresh Recovery.
*/
- ddr->ext_refrec = (trfc_high << 16);
- debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+ ddr->timing_cfg_3 = (trfc_high << 16);
+ debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
ddr->timing_cfg_1 =
(0
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index 69f53eabcf..a3304384f2 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -185,11 +185,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
{
struct mtdids *id = current_part->dev->id;
u32 bytes_read = 0;
-#if defined(CFG_NAND_LEGACY)
size_t retlen;
-#else
- ulong retlen;
-#endif
int cpy_bytes;
while (bytes_read < size) {
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index dc6e278ff4..2d07625464 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -92,7 +92,7 @@ typedef struct ccsr_ddr {
uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
char res5[48];
- uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+ uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -106,8 +106,8 @@ typedef struct ccsr_ddr {
char res6[4];
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
char res7[20];
- uint init_address; /* 0x2148 - DDR training initialization address */
- uint init_ext_address; /* 0x214C - DDR training initialization extended address */
+ uint init_addr; /* 0x2148 - DDR training initialization address */
+ uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
char res8_1[16];
uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 7526061d5a..0b78c94f7c 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -109,7 +109,7 @@ typedef struct ccsr_ddr {
uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
char res7[104];
- uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
+ uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -126,7 +126,7 @@ typedef struct ccsr_ddr {
uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
uint init_addr; /* 0x2148 - DDR training initialzation address */
- uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */
+ uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */
char res10[2728];
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 9e70198e42..585411c4e2 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -114,7 +114,7 @@
#if 0 /* TODO */
#define CFG_DDR_CS0_BNDS 0x0000000F
#define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH 0x00000000
+#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_TIMING_0 0x00260802
#define CFG_DDR_TIMING_1 0x3935d322
#define CFG_DDR_TIMING_2 0x14904cc8
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 690584a786..1f669aa8f6 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -91,9 +91,9 @@
/* Additional registers for watchdog timer post test */
-#define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2)
#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
+#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR
#define CFG_WATCHDOG_MAGIC 0x12480000
#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
#define CFG_DSPIC_TEST_MASK 0x00000001
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 18cedff929..20da73e0fa 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -136,7 +136,7 @@
#define CFG_DDR_CS1_CONFIG 0x00000000
#define CFG_DDR_CS2_CONFIG 0x00000000
#define CFG_DDR_CS3_CONFIG 0x00000000
- #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_TIMING_0 0x00220802
#define CFG_DDR_TIMING_1 0x38377322
#define CFG_DDR_TIMING_2 0x002040c7
diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c
index 27e1a823c6..5bfb220707 100644
--- a/lib_ppc/cache.c
+++ b/lib_ppc/cache.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/cache.h>
+#include <watchdog.h>
void flush_cache (ulong start_addr, ulong size)
{
@@ -35,6 +36,7 @@ void flush_cache (ulong start_addr, ulong size)
addr < end_addr;
addr += CFG_CACHELINE_SIZE) {
asm ("dcbst 0,%0": :"r" (addr));
+ WATCHDOG_RESET();
}
asm ("sync"); /* Wait for all dcbst to complete on bus */
@@ -42,6 +44,7 @@ void flush_cache (ulong start_addr, ulong size)
addr < end_addr;
addr += CFG_CACHELINE_SIZE) {
asm ("icbi 0,%0": :"r" (addr));
+ WATCHDOG_RESET();
}
}
asm ("sync"); /* Always flush prefetch queue in any case */
diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile
index 899b0dc1f3..d2932bed13 100644
--- a/post/board/lwmon/Makefile
+++ b/post/board/lwmon/Makefile
@@ -20,10 +20,10 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
+include $(OBJTREE)/include/autoconf.mk
LIB = libpostlwmon.a
-COBJS = sysmon.o
+COBJS-$(CONFIG_HAS_POST) += sysmon.o
include $(TOPDIR)/post/rules.mk
diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c
index 02d5f6f32a..9a37b2e836 100644
--- a/post/board/lwmon5/sysmon.c
+++ b/post/board/lwmon5/sysmon.c
@@ -32,9 +32,9 @@
* The test passes when all the following voltages and temperatures
* are within allowed ranges:
*
- * Temperature -40 .. +85 C
- * +5V +4.75 .. +5.25 V
- * +5V standby +4.75 .. +5.25 V
+ * Temperature -40 .. +90 C
+ * +5V +4.50 .. +5.50 V
+ * +5V standby +3.50 .. +5.50 V
*
* LCD backlight is not enabled if temperature values are not within
* allowed ranges (-30 .. + 80). The brightness of backlite can be
@@ -60,6 +60,21 @@ extern int dspic_read(ushort reg);
#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off)
+#define REG_TEMPERATURE 0x12BC
+#define REG_VOLTAGE_5V 0x12CA
+#define REG_VOLTAGE_5V_STANDBY 0x12C6
+
+#define TEMPERATURE_MIN (-40) /* degr. C */
+#define TEMPERATURE_MAX (+90) /* degr. C */
+#define TEMPERATURE_DISPLAY_MIN (-35) /* degr. C */
+#define TEMPERATURE_DISPLAY_MAX (+85) /* degr. C */
+
+#define VOLTAGE_5V_MIN (+4500) /* mV */
+#define VOLTAGE_5V_MAX (+5500) /* mV */
+
+#define VOLTAGE_5V_STANDBY_MIN (+3500) /* mV */
+#define VOLTAGE_5V_STANDBY_MAX (+5500) /* mV */
+
typedef struct sysmon_s sysmon_t;
typedef struct sysmon_table_s sysmon_table_t;
@@ -107,17 +122,31 @@ struct sysmon_table_s
static sysmon_table_t sysmon_table[] =
{
- {"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
- 1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0,
- 0x8000-30, 0x8000+80, 0, 0x12BC},
-
- {"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
- 100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0,
- 0x8000+4750, 0x8000+5250, 0, 0x12CA},
-
- {"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
- 100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0,
- 0x8000+4750, 0x8000+5250, 0, 0x12C6},
+ {
+ "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
+ 1, 1, -32768, 32767, 0xFFFF,
+ 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
+ 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
+ REG_TEMPERATURE
+ },
+
+ {
+ "+ 5 V", "V", &sysmon_dspic, NULL, NULL,
+ 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
+ 100, 1000, 0, 0xFFFF, 0xFFFF,
+ VOLTAGE_5V_MIN, VOLTAGE_5V_MAX, 0,
+ VOLTAGE_5V_MIN, VOLTAGE_5V_MAX, 0,
+ REG_VOLTAGE_5V
+ },
+
+ {
+ "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
+ 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
+ 100, 1000, 0, 0xFFFF, 0xFFFF,
+ VOLTAGE_5V_STANDBY_MIN, VOLTAGE_5V_STANDBY_MAX, 0,
+ VOLTAGE_5V_STANDBY_MIN, VOLTAGE_5V_STANDBY_MAX, 0,
+ REG_VOLTAGE_5V_STANDBY
+ },
};
static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c
index 16c01bee43..1246278a58 100644
--- a/post/board/lwmon5/watchdog.c
+++ b/post/board/lwmon5/watchdog.c
@@ -52,8 +52,9 @@ static void watchdog_magic_write(uint value)
int sysmon1_post_test(int flags)
{
- if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS)) {
- /* 3.1. GPIO62 is low
+ if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS) == 0) {
+ /*
+ * 3.1. GPIO62 is low
* Assuming system voltage failure.
*/
post_log("Abnormal voltage detected (GPIO62)\n");
diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile
index 60c7790ace..8a8578f439 100644
--- a/post/board/netta/Makefile
+++ b/post/board/netta/Makefile
@@ -20,10 +20,10 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
+include $(OBJTREE)/include/autoconf.mk
LIB = libpostnetta.a
-COBJS = codec.o dsp.o
+COBJS-$(CONFIG_HAS_POST) += codec.o dsp.o
include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile
index f871cbab64..162924f6b2 100644
--- a/post/cpu/mpc8xx/Makefile
+++ b/post/cpu/mpc8xx/Makefile
@@ -20,10 +20,11 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
+include $(OBJTREE)/include/autoconf.mk
LIB = libpostmpc8xx.a
-AOBJS = cache_8xx.o
-COBJS = cache.o ether.o spr.o uart.o usb.o watchdog.o
+AOBJS-$(CONFIG_HAS_POST) += cache_8xx.o
+COBJS-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o
include $(TOPDIR)/post/rules.mk
diff --git a/tools/.gitignore b/tools/.gitignore
index 979f2dac0d..df3500d965 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -15,3 +15,4 @@
/fdt_strerror.c
/fdt_wip.c
/libfdt_internal.h
+/zlib.h
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-27 19:26:39 +0000