diff options
| -rw-r--r-- | MAINTAINERS | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc8260/ether_fcc.c | 2 | ||||
| -rw-r--r-- | board/sbc8240/Makefile | 44 | ||||
| -rw-r--r-- | board/sbc8240/README | 140 | ||||
| -rw-r--r-- | board/sbc8240/flash.c | 638 | ||||
| -rw-r--r-- | board/sbc8240/sbc8240.c | 111 | ||||
| -rw-r--r-- | board/sbc8260/Makefile | 50 | ||||
| -rw-r--r-- | board/sbc8260/flash.c | 392 | ||||
| -rw-r--r-- | board/sbc8260/sbc8260.c | 289 | ||||
| -rw-r--r-- | boards.cfg | 2 | ||||
| -rw-r--r-- | include/configs/RPXsuper.h | 2 | ||||
| -rw-r--r-- | include/configs/gw8260.h | 2 | ||||
| -rw-r--r-- | include/configs/sacsng.h | 4 | ||||
| -rw-r--r-- | include/configs/sbc8240.h | 364 | ||||
| -rw-r--r-- | include/configs/sbc8260.h | 1080 | ||||
| -rw-r--r-- | include/status_led.h | 3 |
16 files changed, 4 insertions, 3123 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 6ebcc3152d8..3ab38fa9845 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -134,10 +134,6 @@ Wolfgang Denk <wd@denx.de> PCIPPC2 MPC750 PCIPPC6 MPC750 -Jon Diekema <jon.diekema@smiths-aerospace.com> - - sbc8260 MPC8260 - Alex Dubov <oakad@yahoo.com> mpq101 MPC8548 diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index c82958db1b6..b05f5762e53 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -687,7 +687,7 @@ eth_loopback_test (void) immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; -#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng) +#elif defined(CONFIG_SACSng) /* * Attention: this is board-specific * 1, FCC2 diff --git a/board/sbc8240/Makefile b/board/sbc8240/Makefile deleted file mode 100644 index 12e4aa6880e..00000000000 --- a/board/sbc8240/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sbc8240/README b/board/sbc8240/README deleted file mode 100644 index 71595b4bffb..00000000000 --- a/board/sbc8240/README +++ /dev/null @@ -1,140 +0,0 @@ -The supported features of the SBC8240/8245 board are: - 8240 or 8245 processor - 66MHz & 100MHz bus speed - Decrementer timer - 1 UART channel (Console channel) - 8240 Interrupt Controller - 8240 PCI bridge - 8240 Memory Controller - SDRAM (16, 64 MB Memory DIMM) - FLASH 512K On board - FLASH 4MB On board - - -Memory Map from CPU point of view: - - Start Size Access to - ----------------------------------------------------- - 0x00000000 64MB SDRAM DIMM - 0xFF000000 4MB On Board FLASH - 0xFFF00000 512K On Board FLASH or SRAM (Configured by jumper) - 0xFFE00000 8K EEPROM - 0xFFE80000 8Bit LED - 0xFFF80000 8Bit UART - - -Setting the board Jumpers & Switches: - - In order to get the board running with the default configuration the - jumpers need to be set as follows: - - General Jumpers: - ____________________________________________ - | Jumpers | Jumpers | Jumpers | - |-------------|--------------|---------------| - |JP1 1-2 | JP14 1-2 | JP27 1-2 | - |JP5 Open | JP15 1-2 | JP28 2-3 | - |JP8 1-2 | JP16 1-2 | JP33 Open | - |JP9 1-2 | JP17 1-2 | JP37 Close | - |JP10 1-2 | JP18 1-2 | | - |JP11 2-3 | JP19 1-2 | | - |JP12 1-2 | JP20 1-2 | | - |JP13 1-2 | JP25 Open | | - |_____________|______________|_______________| - - Bus speed Jumpers: - _________________________ - | 100MHz Bus | 66 MHz Bus | - |------------|------------| - | JP2 1-2 | JP2 1-2 | - | JP3 1-2 | JP3 2-3 | - | JP4 1-2 | JP4 2-3 | - | JP6 1-2 | JP6 2-3 | - | JP7 1-2 | JP7 1-2 | - |____________|____________| - - -U-Boot 1.1.2 (Jun 24 2004 - 17:01:04) - -CPU: MPC8240 Revision 1.1 at 247.500 MHz: 16 kB I-Cache 16 kB D-Cache -Board: sbc8240 Revision 255 Local Bus at 99 MHz -DRAM: 64 MB -FLASH: 512 kB - 00 11 8086 1229 0200 00 -In: serial -Out: serial -Err: serial -Net: i82559#0 - -Welcome to U-Boot for the sbc8240 - -Type ? or help to get on-line help - -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=version;echo;tftpboot $loadaddr $loadfile;bootvx -bootdelay=5 -baudrate=9600 -ethaddr=DE:AD:BE:EF:01:01 -ipaddr=192.168.193.102 -preboot=echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type "? or help" to get on-line help;echo -netmask=255.255.255.248 -clocks_in_mhz=1 -bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei -ipaddr=192.168.193.102 -loadfile=vxWorks.st -loadaddr=0x01000000 -net_load=tftpboot $loadaddr $loadfile -serverip=192.168.193.99 -ethact=i82559#0 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 631/16380 bytes -=> boot - -U-Boot 1.1.2 (Jun 24 2004 - 17:01:04) - -Using i82559#0 device -TFTP from server 192.168.193.99; our IP address is 192.168.193.102 -Filename 'vxWorks.st'. -Load address: 0x1000000 -Loading: ################################################################# - ################################################################# - ############################################################## -done -Bytes transferred = 979927 (ef3d7 hex) -## Ethernet MAC address not copied to NV RAM -Loading .text @ 0x00100000 (758848 bytes) -Loading .data @ 0x001b9440 (79904 bytes) -Clearing .bss @ 0x001ccc60 (20288 bytes) -## Using bootline (@ 0x4200): $fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei -## Starting vxWorks at 0x00100000 ... - -Adding 2845 symbols for standalone. - - - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]] ]]]] ]]]]]]]]]] ]] ]]]] (R) - ] ]]]]]]]]] ]]]]]] ]]]]]]]] ]] ]]]] - ]] ]]]]]]] ]]]]]]]] ]]]]]] ] ]] ]]]] - ]]] ]]]]] ] ]]] ] ]]]] ]]] ]]]]]]]]] ]]]] ]] ]]]] ]] ]]]]] - ]]]] ]]] ]] ] ]]] ]] ]]]]] ]]]]]] ]] ]]]]]]] ]]]] ]] ]]]] - ]]]]] ] ]]]] ]]]]] ]]]]]]]] ]]]] ]] ]]]] ]]]]]]] ]]]] - ]]]]]] ]]]]] ]]]]]] ] ]]]]] ]]]] ]] ]]]] ]]]]]]]] ]]]] - ]]]]]]] ]]]]] ] ]]]]]] ] ]]] ]]]] ]] ]]]] ]]]] ]]]] ]]]] - ]]]]]]]] ]]]]] ]]] ]]]]]]] ] ]]]]]]] ]]]] ]]]] ]]]] ]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]] Development System - ]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]] VxWorks version 5.5.1 - ]]]]]]]]]]]]]]]]]]]]]]]]]] KERNEL: WIND version 2.6 - ]]]]]]]]]]]]]]]]]]]]]]]]] Copyright Wind River Systems, Inc., 1984-2003 - - CPU: MPC8240 -- Wind River BSP. SBC8240 Board. Processor #0. - Memory Size: 0x2000000. BSP version 1.2/28. - --> diff --git a/board/sbc8240/flash.c b/board/sbc8240/flash.c deleted file mode 100644 index a095753a41f..00000000000 --- a/board/sbc8240/flash.c +++ /dev/null @@ -1,638 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> - -#if CONFIG_SYS_MAX_FLASH_BANKS != 1 -#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (FLASH_WORD_SIZE) AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE) SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay (1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - - DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c deleted file mode 100644 index 01abe26a421..00000000000 --- a/board/sbc8240/sbc8240.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <pci.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define BOARD_REV_REG 0xFE80002B - -int checkboard (void) -{ - char revision = *(volatile char *)(BOARD_REV_REG); - char buf[32]; - - puts ("Board: sbc8240 "); - printf("Revision %d ", revision); - printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); - - return 0; -} - -phys_size_t initdram(int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CONFIG_SYS_LED_BASE - *((unsigned char *) (CONFIG_SYS_LED_BASE)) = 0xFF; -#endif /* CONFIG_SYS_LED_BASE */ - - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/sbc8260/Makefile b/board/sbc8260/Makefile deleted file mode 100644 index f1d86fc173d..00000000000 --- a/board/sbc8260/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sbc8260.o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c deleted file mode 100644 index 645c67f4309..00000000000 --- a/board/sbc8260/flash.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger <mgroeger@sysgo.de> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD 29F080B devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor, devid; - ulong base = (ulong)addr; - -/* printf("addr = %08lx\n", (unsigned long)addr); */ - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0] = 0xf0f0f0f0; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - udelay (1000); - - vendor = addr[0]; -/* printf("vendor = %08lx\n", vendor); */ - if (vendor != 0x01010101) { - info->size = 0; - goto out; - } - - devid = addr[1]; -/* printf("devid = %08lx\n", devid); */ - - if ((devid & 0xff) == AMD_ID_F080B) { - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; - /* we have 16 sectors with 64KB each x 4 */ - info->sector_count = 16; - info->size = 4 * info->sector_count * 64*1024; - } - else { - info->size = 0; - goto out; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* reset command */ - addr = (vu_long *)info->start[0]; - -out: - addr[0] = 0xf0f0f0f0; - - return info->size; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c deleted file mode 100644 index 33ce1a4ee34..00000000000 --- a/board/sbc8260/sbc8260.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2001 - * Advent Networks, Inc. <http://www.adventnetworks.com> - * Jay Monkman <jtm@smoothsmoothie.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 0, 0, 1, 0, 0 }, /* PB17 */ - /* PB16 */ { 1, 0, 0, 1, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 0, 0, 1, 0, 0 }, /* PB15 */ - /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* PB14 */ - /* PB13 */ { 1, 0, 0, 1, 0, 0 }, /* PB13 */ - /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* PB12 */ - /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* PB11 */ - /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* PB10 */ - /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* PB8 */ - /* PB7 */ { 1, 0, 0, 1, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 0, 0, 1, 0, 0 }, /* PB6 */ - /* PB5 */ { 1, 0, 0, 1, 0, 0 }, /* PB5 */ - /* PB4 */ { 1, 0, 0, 1, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 1, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 1, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 1, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 1, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: EST SBC8260\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - ulong psdmr = CONFIG_SYS_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* return total ram size */ - return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CONFIG_SYS_LED_BASE - uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1); - uchar ss; - uchar tmp[64]; - int res; - - if ((ds != 0) && (ds != 0xff)) { - res = getenv_f("ethaddr", tmp, sizeof (tmp)); - if (res > 0) { - ss = ((ds >> 4) & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[15] = ss; - - ss = (ds & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[16] = ss; - - tmp[17] = '\0'; - setenv ("ethaddr", tmp); - /* set the led to show the address */ - *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds; - } - } -#endif /* CONFIG_SYS_LED_BASE */ - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ diff --git a/boards.cfg b/boards.cfg index 0af96f54c68..e5cb91b4cc6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -417,7 +417,6 @@ OXC powerpc mpc824x oxc PN62 powerpc mpc824x pn62 Sandpoint8240 powerpc mpc824x sandpoint Sandpoint8245 powerpc mpc824x sandpoint -sbc8240 powerpc mpc824x utx8245 powerpc mpc824x debris powerpc mpc824x - etin kvme080 powerpc mpc824x - etin @@ -457,7 +456,6 @@ Rattler8248 powerpc mpc8260 rattler - RPXsuper powerpc mpc8260 rpxsuper rsdproto powerpc mpc8260 sacsng powerpc mpc8260 -sbc8260 powerpc mpc8260 ZPC1900 powerpc mpc8260 zpc1900 MPC8260ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS MPC8260ADS_33MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 5c19bd36e4f..9d97f2fd378 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -35,7 +35,7 @@ #undef CONFIG_SYS_SBC_BOOT_LOW /* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk + * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE. * The main FLASH is whichever is connected to *CS0. U-Boot expects * this to be the SIMM. */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 35e6944d548..93d688581fa 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -85,7 +85,7 @@ #define CONFIG_SYS_SBC_BOOT_LOW 1 /* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk + * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE. * The main FLASH is whichever is connected to *CS0. U-Boot expects * this to be the SIMM. */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 32e0444a2fb..914767ac1b4 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -10,8 +10,7 @@ * Advent Networks, Inc. <http://www.adventnetworks.com> * Jay Monkman <jtm@smoothsmoothie.com> * - * Configuration settings for the WindRiver SBC8260 board. - * See http://www.windriver.com/products/html/sbc8260.html + * Configuration settings for the SACSng 8260 board. * * See file CREDITS for list of people who contributed to this * project. @@ -547,7 +546,6 @@ *****************************************************************************/ #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ #define CONFIG_SACSng 1 /* munged for the SACSng */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h deleted file mode 100644 index 2267677d2eb..00000000000 --- a/include/configs/sbc8240.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Configuration settings for the sbc8240 board. - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_WRSBC8240 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \ - "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \ - "tn=sbc8240 o=fei \0" \ - "env_startaddr=FFF70000\0" \ - "env_endaddr=FFF7FFFF\0" \ - "loadfile=vxWorks.st\0" \ - "loadaddr=0x01000000\0" \ - "net_load=tftpboot $loadaddr $loadfile\0" \ - "uboot_startaddr=FFF00000\0" \ - "uboot_endaddr=FFF3FFFF\0" \ - "update=tftp $loadaddr /u-boot.bin;" \ - "protect off $uboot_startaddr $uboot_endaddr;" \ - "era $uboot_startaddr $uboot_endaddr;" \ - "cp.b $loadaddr $uboot_startaddr $filesize;" \ - "protect on $uboot_startaddr $uboot_endaddr\0" \ - "zapenv=protect off $env_startaddr $env_endaddr;" \ - "era $env_startaddr $env_endaddr;" \ - "protect on $env_startaddr $env_endaddr\0" - -#define CONFIG_BOOTDELAY 5 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_ENV_OVERWRITE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ -#define CONFIG_IPADDR 192.168.193.102 -#define CONFIG_NETMASK 255.255.255.248 -#define CONFIG_SERVERIP 192.168.193.99 - -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define STATUS_LED_BIT 0x00000001 -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ -/* LEDs */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile char *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile char *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ - else \ - *((volatile char *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_LED_BASE 0xFFE80000 - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 3686400 - -#define CONFIG_SYS_NS16550_COM1 0xFFF80000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CONFIG_SYS_HZ 1000 -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 7 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_REFINT 430 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 192 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFF70000 -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* we need Plug 'n Play */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_TULIP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h deleted file mode 100644 index 0d83337254a..00000000000 --- a/include/configs/sbc8260.h +++ /dev/null @@ -1,1080 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen <Murray.Jensen@cmst.csiro.au> - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2001 - * Advent Networks, Inc. <http://www.adventnetworks.com> - * Jay Monkman <jtm@smoothsmoothie.com> - * - * Configuration settings for the WindRiver SBC8260 board. - * See http://www.windriver.com/products/html/sbc8260.html - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Enable debug prints */ -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x1 0x5 33 100 133 Open Close Open - * 0x1 0x6 33 100 166 Open Open Close - * 0x1 0x7 33 100 200 Open Open Open - * - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 4 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH1_SIZE 2 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0xa0000000 - - -/* - * SBC8260 with 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x00F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x00F5 FFB0 Board Info Data - * 0x00F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x00FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - -/* - * SBC8260 with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* - * Select SPI support configuration - */ -#undef CONFIG_SPI /* Disable SPI driver */ - -/* - * Select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SOFT_I2C -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT 1 - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address - * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx) - * http://standards.ieee.org/regauth/oui/index.shtml - */ -#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb - -/* - * Define this to set the last octet of the ethernet address from the - * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7 - * switch and the LEDs are backwards with respect to each other. DS7 - * is on the board edge side of both the LED strip and the DS0-DS7 - * switch. - */ -#undef CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#undef CONFIG_AUTOBOOT_KEYED -#ifdef CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds, press \" \" to stop\n", bootdelay -# define CONFIG_AUTOBOOT_STOP_STR " " -# undef CONFIG_AUTOBOOT_DELAY_STR -# define DEBUG_BOOTKEYS 0 -#endif - -/* Define this to contain any number of null terminated strings that - * will be part of the default enviroment compiled into the boot image. - * - * Variable Usage - * -------------- ------------------------------------------------------- - * serverip server IP address - * ipaddr my IP address - * reprog Reload flash with a new copy of U-Boot - * zapenv Erase the environment area in flash - * root-on-initrd Set the bootcmd variable to allow booting of an initial - * ram disk. - * root-on-nfs Set the bootcmd variable to allow booting of a NFS - * mounted root filesystem. - * boot-hook Convenient stub to do something useful before the - * bootm command is executed. - * - * Example usage of root-on-initrd and root-on-nfs : - * - * Note: The lines have been wrapped to improved its readability. - * - * => printenv bootcmd - * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=${serverip}:${rootpath} - * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm - * - * => run root-on-initrd - * => printenv bootcmd - * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw - * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm - * - * => run root-on-nfs - * => printenv bootcmd - * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=${serverip}:${rootpath} - * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm - * - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serverip=192.168.123.205\0" \ - "ipaddr=192.168.123.213\0" \ - "reprog="\ - "bootp;" \ - "tftpboot 0x140000 /bdi2000/u-boot.bin;" \ - "protect off 1:0;" \ - "erase 1:0;" \ - "cp.b 140000 40000000 ${filesize};" \ - "protect on 1:0\0" \ - "zapenv="\ - "protect off 1:1;" \ - "erase 1:1;" \ - "protect on 1:1\0" \ - "root-on-initrd="\ - "setenv bootcmd "\ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm\0" \ - "root-on-nfs="\ - "setenv bootcmd "\ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm\0" \ - "boot-hook=echo\0" - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " - -#undef CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) - * of an image is printed by image commands like bootm or iminfo. - */ -#define CONFIG_TIMESTAMP - -/* If this variable is defined, an environment variable named "ver" - * is created by U-Boot showing the U-Boot version. - */ -#define CONFIG_VERSION_VARIABLE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM - -#undef CONFIG_CMD_KGDB - -#if defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_CMD_MII -#endif - - -#undef CONFIG_WATCHDOG /* disable the watchdog */ - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ - -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP |\ - SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) * - * 1 60x GPCM 32 bit FLASH (SIMM - Unused) - * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) - * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused) - * 4 Local SDRAM 32 bit SDRAM (on board - 4MB) - * 5 60x GPCM 8 bit EEPROM (8KB) - * 6 60x GPCM 8 bit FLASH (on board - 2MB) * - * 7 60x GPCM 8 bit LEDs, switches - * - * (*) This configuration requires the SBC8260 be configured - * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to - * the on board FLASH. In other words, JP24 should have - * pins 1 and 2 jumpered and pins 3 and 4 jumpered. - * - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F080B parts. - * - * Note: For the 4 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 4 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - * - * 16MB DIMM: P/N - * 64MB DIMM: P/N 1W-8864X8-4-P1-EST - * - * Note: *CS3 is unused for this DIMM - */ - -/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 16 MB DIMM, the OR2 is configured as follows: - * - * - 16 MB - * - 2 internal banks per device - * - Row start address bit is A9 with PSDMR[PBI] = 0 - * - 11 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 16) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_2 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_11) -#endif - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* Address that the DIMM SPD memory lives at. - */ -#define SDRAM_SPD_ADDR 0x54 - -#if (CONFIG_SYS_SDRAM0_SIZE == 16) -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A16-A18 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A16_A18 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif - -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif - -/* - * Shoot for approximately 1MHz on the prescaler. - */ -#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000)) -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 -#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000)) -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#else -#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif -#define CONFIG_SYS_PSRT 14 - - -/* Bank 4 - On board SDRAM - * - * This is not implemented yet. - */ - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - On board FLASH - * - * This expects the on board FLASH SIMM to be connected to *CS6 - * It consists of 1 AM29F016A part. - */ -#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) - -/* BR6 is configured as follows: - * - * - Base address of 0x60000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows: - * - * - 2 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ - -/*----------------------------------------------------------------------- - * BR7 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR7 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 7 - LEDs and switches - * - * LEDs are at 0x00001 (write only) - * switches are at 0x00001 (read only) - */ -#ifdef CONFIG_SYS_LED_BASE - -/* BR7 is configured as follows: - * - * - Base address of 0xA0000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR7 is configured as follows: - * - * - 1 byte - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 15 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* CONFIG_SYS_LED_BASE */ -#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index 59143296c39..c85c206772b 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -308,9 +308,6 @@ void status_led_set (int led, int state); /***** STx XTc ********************************************************/ #elif defined(CONFIG_STXXTC) /* XXX empty just to avoid the error */ -/***** sbc8240 ********************************************************/ -#elif defined(CONFIG_WRSBC8240) -/* XXX empty just to avoid the error */ /************************************************************************/ #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ |