diff options
| -rw-r--r-- | CHANGELOG | 14 | ||||
| -rw-r--r-- | CREDITS | 6 | ||||
| -rw-r--r-- | MAINTAINERS | 10 | ||||
| -rw-r--r-- | MAKEALL | 32 | ||||
| -rw-r--r-- | Makefile | 15 | ||||
| -rw-r--r-- | README | 2 | ||||
| -rw-r--r-- | board/atc/Makefile | 40 | ||||
| -rw-r--r-- | board/atc/atc.c | 366 | ||||
| -rw-r--r-- | board/atc/config.mk | 43 | ||||
| -rw-r--r-- | board/atc/flash.c | 665 | ||||
| -rw-r--r-- | board/atc/u-boot.lds | 118 | ||||
| -rw-r--r-- | board/gen860t/README | 25 | ||||
| -rw-r--r-- | board/gen860t/gen860t.c | 22 | ||||
| -rw-r--r-- | board/gen860t/ioport.c | 69 | ||||
| -rw-r--r-- | board/gen860t/u-boot-flashenv.lds | 132 | ||||
| -rw-r--r-- | board/gen860t/u-boot.lds | 11 | ||||
| -rw-r--r-- | common/main.c | 2 | ||||
| -rw-r--r-- | cpu/mpc8260/Makefile | 2 | ||||
| -rw-r--r-- | cpu/mpc8260/spi.c | 435 | ||||
| -rw-r--r-- | cpu/mpc8xx/lcd.c | 12 | ||||
| -rw-r--r-- | include/asm-ppc/cpm_8260.h | 13 | ||||
| -rw-r--r-- | include/common.h | 2 | ||||
| -rw-r--r-- | include/configs/GEN860T.h | 119 | ||||
| -rw-r--r-- | include/configs/TQM8260.h | 36 | ||||
| -rw-r--r-- | include/configs/atc.h | 442 | ||||
| -rw-r--r-- | include/status_led.h | 16 | ||||
| -rw-r--r-- | lib_ppc/board.c | 4 |
27 files changed, 2526 insertions, 127 deletions
diff --git a/CHANGELOG b/CHANGELOG index b597d596934..09ad4f6f126 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,20 @@ Changes since U-Boot 0.3.1: ====================================================================== +* Add support for Promess ATC board + +* Patch by Keith Outwater, 28 Apr 2003: + - Miscellaneous corrections and additions to GEN860T board specific code. + - Added GEN860_SC variant to GEN860T. + - Miscellaneous corrections to GEN860T documentation. + - Correct duplicate entry in U-Boot CREDITS file. + - Add GEN860T_SC entry in MAINTAINERS file. + - Update CREDITS file with GEN860T_SC info. + +* Update Smiths Aerospace addresses in MAINTAINERS file + +* Fix error handling in hush's version of "run" command + * LWMON extensions: - Splashscreen support - modem support @@ -213,12 +213,8 @@ D: Initial support for SSV-DNP1110, SMC91111 driver W: www.elinos.com N: Keith Outwater -E: Keith_Outwater@mvis.com -D: Support for GEN860T board - -N: Keith Outwater E: keith_outwater@mvis.com -D: Support for generic/custom MPC860T board (GEN860T) +D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC) N: Frank Panno E: fpanno@delphintech.com diff --git a/MAINTAINERS b/MAINTAINERS index 332e4137563..7942a0289a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28,7 +28,7 @@ Pantelis Antoniou <panto@intracom.gr> NETVIA MPC8xx -Jerry Van Baren <vanbaren_gerald@si.com> +Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> sacsng MPC8260 @@ -80,6 +80,11 @@ Wolfgang Denk <wd@denx.de> CU824 MPC8240 Sandpoint8240 MPC8240 + ATC MPC8250 + PM825 MPC8250 + + TQM8255 MPC8255 + CPU86 MPC8260 PM826 MPC8260 TQM8260 MPC8260 @@ -87,7 +92,7 @@ Wolfgang Denk <wd@denx.de> PCIPPC2 MPC750 PCIPPC6 MPC750 -Jon Diekema <diekema_jon@si.com> +Jon Diekema <jon.diekema@smiths-aerospace.com> sbc8260 MPC8260 @@ -160,6 +165,7 @@ Scott McNutt <smcnutt@artesyncp.com> Keith Outwater <Keith_Outwater@mvis.com> GEN860T MPC860T + GEN860T_SC MPC860T Frank Panno <fpanno@delphintech.com> @@ -26,16 +26,17 @@ LIST_8xx=" \ ADS860 AMX860 c2mon CCM \ cogent_mpc8xx ESTEEM192E ETX094 ELPT860 \ FADS823 FADS850SAR FADS860T FLAGADM \ - FPS850L GEN860T GENIETV GTH \ - hermes IAD210 ICU862_100MHz IP860 \ - IVML24 IVML24_128 IVML24_256 IVMS8 \ - IVMS8_128 IVMS8_256 KUP4K LANTEC \ - lwmon MBX MBX860T MHPC \ - MVS1 NETVIA NX823 pcu_e \ - R360MPI RPXClassic RPXlite RRvision \ - SM850 SPD823TS svm_sc8xx SXNI855T \ - TOP860 TQM823L TQM823L_LCD TQM850L \ - TQM855L TQM860L TTTech v37 \ + FPS850L GEN860T GEN860T_SC GENIETV \ + GTH hermes IAD210 ICU862_100MHz \ + IP860 IVML24 IVML24_128 IVML24_256 \ + IVMS8 IVMS8_128 IVMS8_256 KUP4K \ + LANTEC lwmon MBX MBX860T \ + MHPC MVS1 NETVIA NX823 \ + pcu_e R360MPI RPXClassic RPXlite \ + RRvision SM850 SPD823TS svm_sc8xx \ + SXNI855T TOP860 TQM823L TQM823L_LCD \ + TQM850L TQM855L TQM860L TTTech \ + v37 \ " ######################################################################### @@ -62,14 +63,15 @@ LIST_824x=" \ " ######################################################################### -## MPC8260 Systems +## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### LIST_8260=" \ - cogent_mpc8260 CPU86 ep8260 gw8260 \ - hymod IPHASE4539 MPC8260ADS MPC8266ADS \ - PM826 ppmc8260 RPXsuper rsdproto \ - sacsng sbc8260 SCM TQM8260 \ + ATC cogent_mpc8260 CPU86 ep8260 \ + gw8260 hymod IPHASE4539 MPC8260ADS \ + MPC8266ADS PM826 ppmc8260 RPXsuper \ + rsdproto sacsng sbc8260 SCM \ + TQM8260 \ " ######################################################################### @@ -212,8 +212,16 @@ FADS860T_config: unconfig FLAGADM_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx flagadm +xtract_GEN860T = $(subst _SC,,$(subst _config,,$1)) + +GEN860T_SC_config \ GEN860T_config: unconfig - @./mkconfig $(@:_config=) ppc mpc8xx gen860t + @ >include/config.h + @[ -z "$(findstring _SC,$@)" ] || \ + { echo "#define CONFIG_SC" >>include/config.h ; \ + echo "With reduced H/W feature set (SC)..." ; \ + } + @./mkconfig -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t GENIETV_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx genietv @@ -575,11 +583,13 @@ sbc8260_config: unconfig SCM_config: unconfig @./mkconfig $(@:_config=) ppc mpc8260 SCM siemens +TQM8255_config \ TQM8260_config \ TQM8260_L2_config \ TQM8255_266MHz_config \ TQM8260_266MHz_config \ TQM8260_L2_266MHz_config \ +TQM8255_300MHz_config \ TQM8260_300MHz_config: unconfig @ >include/config.h @if [ "$(findstring _L2_,$@)" ] ; then \ @@ -601,6 +611,9 @@ TQM8260_300MHz_config: unconfig { echo "#define CONFIG_MPC8255" >>include/config.h ; } @./mkconfig -a TQM8260 ppc mpc8260 tqm8260 +atc_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 atc + ######################################################################### ## 74xx/7xx Systems ######################################################################### @@ -180,7 +180,7 @@ Directory Hierarchy: Files specific to EVB64260 boards - board/fads Files specific to FADS boards - board/flagadm Files specific to FLAGADM boards -- board/gen860t Files specific to GEN860T boards +- board/gen860t Files specific to GEN860T and GEN860T_SC boards - board/genietv Files specific to GENIETV boards - board/gth Files specific to GTH boards - board/hermes Files specific to HERMES boards diff --git a/board/atc/Makefile b/board/atc/Makefile new file mode 100644 index 00000000000..35b84288da6 --- /dev/null +++ b/board/atc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c new file mode 100644 index 00000000000..3547f41f93b --- /dev/null +++ b/board/atc/atc.c @@ -0,0 +1,366 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ + /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ + /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ +#if 1 + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ +#else + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ +#endif + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ + /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ +#if 0 + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ +#else + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */ +#endif + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ +#if 0 + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ +#else + /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */ +#endif + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + printf ("Board: ATC\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + ulong cnt, val; + volatile ulong *addr; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + int i; + ulong save[32]; /* to make test non-destructive */ + ulong maxsize; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + /* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + i = 0; + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *) base; + save[i] = *addr; + *addr = 0; + + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + /* Write the actual size to ORx + */ + *orx_ptr = orx | ~(cnt * sizeof (long) - 1); + return (cnt * sizeof (long)); + } + } + return (maxsize); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + long psize; + + psize = 8 * 1024 * 1024; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } + +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/atc/config.mk b/board/atc/config.mk new file mode 100644 index 00000000000..8fc82f3f8b4 --- /dev/null +++ b/board/atc/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ATC boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_atc.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# + +ifeq ($(CONFIG_BOOT_ROM),y) + TEXT_BASE := 0xFF800000 + PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM +else + TEXT_BASE := 0xFF000000 +endif + +# RAM version +#TEXT_BASE := 0x100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/atc/flash.c b/board/atc/flash.c new file mode 100644 index 00000000000..4bcf2ee7f34 --- /dev/null +++ b/board/atc/flash.c @@ -0,0 +1,665 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { +#if 0 + ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; +#else + ulong flashbase = CFG_FLASH_BASE; +#endif + + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", + i, flash_info[i].size); + } + + size += flash_info[i].size; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (uniform sector type) */ + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = base + (i * sect_size); + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base < info->start[0] + info->size) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(1000000);//psl + //psl switch (addr[1] & 0xff) { + switch (addr[0] & 0xff) {//psl + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + //psl if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { + if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + + return (res); +} diff --git a/board/atc/u-boot.lds b/board/atc/u-boot.lds new file mode 100644 index 00000000000..5df4cdb321c --- /dev/null +++ b/board/atc/u-boot.lds @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/gen860t/README b/board/gen860t/README index 761ceed302a..7c03f93650f 100644 --- a/board/gen860t/README +++ b/board/gen860t/README @@ -1,8 +1,7 @@ - This directory contains board specific code for a generic MPC860T based embedded computer, called 'GEN860T'. The design is generic in the sense that common, readily available components are used and that the architecture of the -system is i(relatively) straightforward: +system is relatively straightforward: One eight bit wide boot (FLASH) memory 32 bit main memory using SDRAM @@ -23,14 +22,14 @@ hearing from you, especially if you discover bugs or find ways to improve the quality of this U-Boot port. Here are the salient features of the system: -Clock : 33 Mhz oscillator -Processor core frequency : 66 Mhz if in 1:2:1 mode; can also run 1:1 -Bus frequency : 33 Mhz +Clock : 33.3 Mhz oscillator +Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 +Bus frequency : 33.3 Mhz Main memory: Type : SDRAM Width : 32 bits - Size : 64 megabytes + Size : 64 mibibytes Chip : Two Micron MT48LC16M16A2TG-7E CS : MPC860T CS1*/UPMA UPMA CONNECTIONS: @@ -42,7 +41,7 @@ Main memory: Boot memory: Type : FLASH Width : 8 bits - Size : 16 megabytes + Size : 16 mibibytes Chip : One Intel 28F128J3A (StrataFlash) CS : MPC860T CS0*/GPCM (this is the "boot" chip select) @@ -56,7 +55,7 @@ EEPROM memory: Filesystem memory: Type : NAND FLASH (Toshiba) Width : 8 bits (i.e. interface to DOC is 8 bits) - Size : 32 megabytes + Size : 32 mibibytes Chip : One DiskOnCHip Millenium Plus (DOC 2000+) CS : MPC860T CS2*/GPCM @@ -92,6 +91,12 @@ Miscellaneous: Mil-Std 1553 databus interface on CS5*/GPCM. Audio sounder (beeper) with digital volume control connected to SPKROUT. +SC variant: + A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. + The 'SC' variant only provides support for the Virtex FPGA, SDRAM main + memory, EEPROM and flash memory. The system clock frequency is reduced + to 24 MHz. + Issues: The DOC 2000+ returns 0x40 as its device ID when probed using the method desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver @@ -105,11 +110,11 @@ Status: in MTD for this device. I wish I had known this sooner :( The GEN860T board specific files and configuration is based on the work -of others who have contributed to U-Boot. The copright and license notices +of others who have contributed to U-Boot. The copyright and license notices of these authors have been retained wherever their code has been reused. All new code to support the GEN860T board is: - (C) Copyright 2001-2002 + (C) Copyright 2001-2003 Keith Outwater (keith_outwater@mvis.com) and the following license applies: diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index 16a3262c4b5..094eeef037e 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -271,18 +271,12 @@ misc_init_r (void) int last_stage_init(void) { +#if !defined(CONFIG_SC) unsigned char buf[256]; int i; /* - * Set LEDs here since status LED init code has already run - */ - status_led_set(STATUS_LED_BIT1, STATUS_LED_ON); - status_led_set(STATUS_LED_BIT3, STATUS_LED_ON); - - /* - * Turn the beeper volume all the way down in case this is a warm - * boot. + * Turn the beeper volume all the way down in case this is a warm boot. */ set_beeper_volume(-64); init_beeper(); @@ -294,6 +288,18 @@ last_stage_init(void) if (i > 0) { do_beeper(buf); } +#endif return 0; } + +/* + * Stub to make POST code happy. Can't self-poweroff, so just hang. + */ +void +board_poweroff(void) +{ + puts("### Please power off the board ###\n"); + while (1); +} + /* vim: set ts=4 sw=4 tw=78 : */ diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c index 5d6524dbd38..7b3ebd44905 100644 --- a/board/gen860t/ioport.c +++ b/board/gen860t/ioport.c @@ -42,8 +42,9 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* * Port A configuration - * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High + * Pin Signal Type Active Initial state + * PA7 fpgaProgramLowOut Out Low High + * PA1 fpgaCoreVoltageFailLow In Low N/A */ { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ @@ -62,22 +63,32 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ +#else /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ }, /* + * Port B configuration * Pin Signal Type Active Initial state * PB14 docBusyLowIn In Low X * PB15 gpio1Sig Out High Low * PB16 fpgaDoneBi In High X - * PB17 swBitOkLowOut Out Low Low + * PB17 swBitOkLowOut Out Low High * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) * PB22 fpgaInitLowBi In Low X * PB23 batteryOkSig In High X - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + * PB31 pulseCatcherClr Out High 0 + */ + { /* conf ppar psor pdir podr pdat pint function */ +#if !defined(CONFIG_SC) + /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#else + /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ +#endif /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ @@ -85,19 +96,32 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ +#else + /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ +#else + /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ +#endif /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 0, 0, 1, 0, 0, 0 }, /* swBitOkLow */ + /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ +#if !defined(CONFIG_SC) /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ - }, +#else + /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ +#endif + }, /* + * Port C configuration * Pin Signal Type Active Initial state * PC4 i2cBus1EnSig Out High High * PC5 i2cBus2EnSig Out High High @@ -108,29 +132,48 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { * PC12 systemBitOkIn In High X * PC15 selfDreqLow In Low X */ - { /* conf ppar psor pdir podr pdat pint function */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ +#else + /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ +#if !defined(CONFIG_SC) /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ +#else + /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ +#else + /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ +#if !defined(CONFIG_SC) /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ +#else + /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ + /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, + }, - /* Port D configuration */ - { /* conf ppar psor pdir podr pdat pint function */ + /* + * Port D configuration + */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ @@ -149,7 +192,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - } + } }; /* diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds new file mode 100644 index 00000000000..8b1ce1a1b48 --- /dev/null +++ b/board/gen860t/u-boot-flashenv.lds @@ -0,0 +1,132 @@ +/* + * Linker command file for the GEN860T board when the environment is + * stored in flash memory. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* + * Read-only sections, merged into text segment: + */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* + * Read-write section, merged into data segment: + */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data: + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); + + .ppcenv: + { + . = env_offset; + common/environment.o + } +} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index 1b53c723d50..b67faa63d00 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -56,15 +56,6 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset; - common/environment.o(.text) */ - *(.text) *(.fixup) *(.got1) @@ -128,8 +119,6 @@ SECTIONS *(.bss) *(COMMON) } - _end = . ; PROVIDE (end = .); } - diff --git a/common/main.c b/common/main.c index 33d871771bd..fe4ebb4f662 100644 --- a/common/main.c +++ b/common/main.c @@ -880,7 +880,7 @@ int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; #else if (parse_string_outer(arg, - FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) == 0) + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0) return 1; #endif } diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile index 22d323e21dc..81f74eca8a2 100644 --- a/cpu/mpc8260/Makefile +++ b/cpu/mpc8260/Makefile @@ -28,7 +28,7 @@ LIB = lib$(CPU).a START = start.o kgdb.o OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \ - bedbug_603e.o status_led.o pci.o + bedbug_603e.o status_led.o pci.o spi.o all: .depend $(START) $(LIB) diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c new file mode 100644 index 00000000000..6a2dc8f29bf --- /dev/null +++ b/cpu/mpc8260/spi.c @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2001 Navin Boppuri / Prashant Patel + * <nboppuri@trinetcommunication.com>, + * <pmpatel@trinetcommunication.com> + * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de> + * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8260 CPM SPI interface. + * + * Parts of this code are probably not portable and/or specific to + * the board which I used for the tests. Please send fixes/complaints + * to wd@denx.de + * + */ + +#include <common.h> +#include <asm/cpm_8260.h> +#include <linux/ctype.h> +#include <malloc.h> +#include <post.h> +#include <net.h> + +#if defined(CONFIG_SPI) + +/* Warning: + * You cannot enable DEBUG for early system initalization, i. e. when + * this driver is used to read environment parameters like "baudrate" + * from EEPROM which are used to initialize the serial port which is + * needed to print the debug messages... + */ +#undef DEBUG + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + +/* --------------------------------------------------------------- + * Offset for initial SPI buffers in DPRAM: + * We need a 520 byte scratch DPRAM area to use at an early stage. + * It is used between the two initialization calls (spi_init_f() + * and spi_init_r()). + * The value 0x2000 makes it far enough from the start of the data + * area (as well as from the stack pointer). + * --------------------------------------------------------------- */ +#ifndef CFG_SPI_INIT_OFFSET +#define CFG_SPI_INIT_OFFSET 0x2000 +#endif + +#define CPM_SPI_BASE 0x100 + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) + +#endif /* DEBUG */ + +/* ------------------- + * Function prototypes + * ------------------- */ +void spi_init (void); + +ssize_t spi_read (uchar *, int, uchar *, int); +ssize_t spi_write (uchar *, int, uchar *, int); +ssize_t spi_xfer (size_t); + +/* ------------------- + * Variables + * ------------------- */ + +#define MAX_BUFFER 0x104 + +/* ---------------------------------------------------------------------- + * Initially we place the RX and TX buffers at a fixed location in DPRAM! + * ---------------------------------------------------------------------- */ +static uchar *rxbuf = + (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase + [CFG_SPI_INIT_OFFSET]; +static uchar *txbuf = + (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase + [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; + +/* ************************************************************************** + * + * Function: spi_init_f + * + * Description: Init SPI-Controller (ROM part) + * + * return: --- + * + * *********************************************************************** */ +void spi_init_f (void) +{ + unsigned int dpaddr; + + volatile spi_t *spi; + volatile immap_t *immr; + volatile cpm8260_t *cp; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8260_t *) &immr->im_cpm; + + *(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI; + spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; + +/* 1 */ + /* ------------------------------------------------ + * Initialize Port D SPI pins + * (we are only in Master Mode !) + * ------------------------------------------------ */ + + /* -------------------------------------------- + * GPIO or per. Function + * PPARD[16] = 1 [0x00008000] (SPIMISO) + * PPARD[17] = 1 [0x00004000] (SPIMOSI) + * PPARD[18] = 1 [0x00002000] (SPICLK) + * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM) + * -------------------------------------------- */ + immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */ + immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */ + + /* ---------------------------------------------- + * In/Out or per. Function 0/1 + * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO + * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI + * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK + * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM + * ---------------------------------------------- */ + immr->im_ioport.iop_pdird &= ~0x0000E000; + immr->im_ioport.iop_pdird |= 0x00080000; + + /* ---------------------------------------------- + * special option reg. + * PSORD[16] = 1 [0x00008000] -> SPIMISO + * PSORD[17] = 1 [0x00004000] -> SPIMOSI + * PSORD[18] = 1 [0x00002000] -> SPICLK + * ---------------------------------------------- */ + immr->im_ioport.iop_psord |= 0x0000E000; + + /* Initialize the parameter ram. + * We need to make sure many things are initialized to zero + */ + spi->spi_rstate = 0; + spi->spi_rdp = 0; + spi->spi_rbptr = 0; + spi->spi_rbc = 0; + spi->spi_rxtmp = 0; + spi->spi_tstate = 0; + spi->spi_tdp = 0; + spi->spi_tbptr = 0; + spi->spi_tbc = 0; + spi->spi_txtmp = 0; + + /* Allocate space for one transmit and one receive buffer + * descriptor in the DP ram + */ +#ifdef CFG_ALLOC_DPRAM + dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8); +#else + dpaddr = CPM_SPI_BASE; +#endif + +/* 3 */ + /* Set up the SPI parameters in the parameter ram */ + spi->spi_rbase = dpaddr; + spi->spi_tbase = dpaddr + sizeof (cbd_t); + + /***********IMPORTANT******************/ + + /* + * Setting transmit and receive buffer descriptor pointers + * initially to rbase and tbase. Only the microcode patches + * documentation talks about initializing this pointer. This + * is missing from the sample I2C driver. If you dont + * initialize these pointers, the kernel hangs. + */ + spi->spi_rbptr = spi->spi_rbase; + spi->spi_tbptr = spi->spi_tbase; + +/* 4 */ + /* Init SPI Tx + Rx Parameters */ + while (cp->cp_cpcr & CPM_CR_FLG) + ; + cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + while (cp->cp_cpcr & CPM_CR_FLG) + ; + +/* 6 */ + /* Set to big endian. */ + spi->spi_tfcr = CPMFCR_EB; + spi->spi_rfcr = CPMFCR_EB; + +/* 7 */ + /* Set maximum receive size. */ + spi->spi_mrblr = MAX_BUFFER; + +/* 8 + 9 */ + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; + rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; + + tbdf->cbd_sc &= ~BD_SC_READY; + rbdf->cbd_sc &= ~BD_SC_EMPTY; + + /* Set the bd's rx and tx buffer address pointers */ + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + +/* 10 + 11 */ + immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ + immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ + + + return; +} + +/* ************************************************************************** + * + * Function: spi_init_r + * + * Description: Init SPI-Controller (RAM part) - + * The malloc engine is ready and we can move our buffers to + * normal RAM + * + * return: --- + * + * *********************************************************************** */ +void spi_init_r (void) +{ + volatile spi_t *spi; + volatile immap_t *immr; + volatile cpm8260_t *cp; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8260_t *) &immr->im_cpm; + + spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; + + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; + rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; + + /* Allocate memory for RX and TX buffers */ + rxbuf = (uchar *) malloc (MAX_BUFFER); + txbuf = (uchar *) malloc (MAX_BUFFER); + + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + + return; +} + +/**************************************************************************** + * Function: spi_write + **************************************************************************** */ +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + *txbuf = SPI_EEPROM_WREN; /* write enable */ + spi_xfer(1); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ + memcpy(alen + txbuf, buffer, len); + spi_xfer(alen + len); + /* ignore received data */ + for (i = 0; i < 1000; i++) { + *txbuf = SPI_EEPROM_RDSR; /* read status */ + txbuf[1] = 0; + spi_xfer(2); + if (!(rxbuf[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + + return len; +} + +/**************************************************************************** + * Function: spi_read + **************************************************************************** */ +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_READ; /* READ memory array */ + + /* + * There is a bug in 860T (?) that cuts the last byte of input + * if we're reading into DPRAM. The solution we choose here is + * to always read len+1 bytes (we have one extra byte at the + * end of the buffer). + */ + spi_xfer(alen + len + 1); + memcpy(buffer, alen + rxbuf, len); + + return len; +} + +/**************************************************************************** + * Function: spi_xfer + **************************************************************************** */ +ssize_t spi_xfer (size_t count) +{ + volatile immap_t *immr; + volatile cpm8260_t *cp; + volatile spi_t *spi; + cbd_t *tbdf, *rbdf; + int tm; + + DPRINT (("*** spi_xfer entered ***\n")); + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8260_t *) &immr->im_cpm; + + spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; + + tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; + rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; + + /* Board-specific: Set CS for device (ATC EEPROM) */ + immr->im_ioport.iop_pdatd &= ~0x00080000; + + /* Setting tx bd status and data length */ + tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; + tbdf->cbd_datlen = count; + + DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", + tbdf->cbd_datlen)); + + /* Setting rx bd status and data length */ + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + rbdf->cbd_datlen = 0; /* rx length has no significance */ + + immr->im_spi.spi_spmode = SPMODE_REV | + SPMODE_MSTR | + SPMODE_EN | + SPMODE_LEN(8) | /* 8 Bits per char */ + SPMODE_PM(0x8) ; /* medium speed */ + immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ + immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ + + /* start spi transfer */ + DPRINT (("*** spi_xfer: Performing transfer ...\n")); + immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */ + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * -------------------------------- */ + for (tm=0; tm<1000; ++tm) { + if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */ + DPRINT (("*** spi_xfer: Tx buffer empty\n")); + break; + } + if ((tbdf->cbd_sc & BD_SC_READY) == 0) { + DPRINT (("*** spi_xfer: Tx BD done\n")); + break; + } + udelay (1000); + } + if (tm >= 1000) { + printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); + } + DPRINT (("*** spi_xfer: ... transfer ended\n")); + +#ifdef DEBUG + printf ("\nspi_xfer: txbuf after xfer\n"); + memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ + printf ("spi_xfer: rxbuf after xfer\n"); + memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ + printf ("\n"); +#endif + + /* Clear CS for device */ + immr->im_ioport.iop_pdatd |= 0x00080000; + + return count; +} +#endif /* CONFIG_SPI */ diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c index 3d3b039abc4..0db5348650f 100644 --- a/cpu/mpc8xx/lcd.c +++ b/cpu/mpc8xx/lcd.c @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> +#include <watchdog.h> #include <version.h> #include <stdarg.h> #include <lcdvideo.h> @@ -1059,6 +1060,8 @@ static void bitmap_plot (int x, int y) /* Leave room for default color map */ cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); + WATCHDOG_RESET(); + /* Set color map */ for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) { ushort colreg = bmp_logo_palette[i]; @@ -1071,11 +1074,15 @@ static void bitmap_plot (int x, int y) bmap = &bmp_logo_bitmap[0]; fb = (char *)(lcd_base + y * lcd_line_length + x); + WATCHDOG_RESET(); + for (i=0; i<BMP_LOGO_HEIGHT; ++i) { memcpy (fb, bmap, BMP_LOGO_WIDTH); bmap += BMP_LOGO_WIDTH; fb += panel_info.vl_col; } + + WATCHDOG_RESET(); } #endif /* CONFIG_LCD_LOGO */ @@ -1098,6 +1105,8 @@ int lcd_display_bitmap(ulong bmp_image) unsigned colors,bpix; unsigned long compression; + WATCHDOG_RESET(); + if (!((bmp->header.signature[0]=='B') && (bmp->header.signature[1]=='M'))) { printf ("Error: no valid bmp image at %lx\n", bmp_image); @@ -1149,6 +1158,8 @@ int lcd_display_bitmap(ulong bmp_image) #endif *cmap-- = colreg; } + + WATCHDOG_RESET(); } padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); @@ -1163,6 +1174,7 @@ int lcd_display_bitmap(ulong bmp_image) (((height>=panel_info.vl_row) ? panel_info.vl_row : height)-1) * lcd_line_length); for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); for (j = 0; j < width ; j++) *(fb++)=255-*(bmap++); bmap += (width - padded_line); diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index bf2e2a2cb62..5c70603f485 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -170,7 +170,7 @@ typedef struct cpm_buf_desc { */ #define PROFF_SMC1 (0) #define PROFF_SMC2 (64) - +#define PROFF_SPI ((16*1024) - 128) /* Define enough so I can at least use the serial port as a UART. */ @@ -737,6 +737,17 @@ typedef struct spi { #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) #define SPMODE_PM(x) ((x) &0xF) +/* SPI Event/Mask register. +*/ +#define SPI_EMASK 0x37 /* Event Mask */ +#define SPI_MME 0x20 /* Multi-Master Error */ +#define SPI_TXE 0x10 /* Transmit Error */ +#define SPI_BSY 0x04 /* Busy */ +#define SPI_TXB 0x02 /* Tx Buffer Empty */ +#define SPI_RXB 0x01 /* RX Buffer full/closed */ + +#define SPI_STR 0x80 /* SPCOM: Start transmit */ + #define SPI_EB ((u_char)0x10) /* big endian byte order */ #define BD_IIC_START ((ushort)0x0400) diff --git a/include/common.h b/include/common.h index 509675410e5..2ff1c8c35a8 100644 --- a/include/common.h +++ b/include/common.h @@ -198,7 +198,7 @@ extern void pic_write (uchar reg, uchar val); # define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR #endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */ -#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM) +#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM) || defined(CONFIG_ATC) extern void spi_init_f (void); extern void spi_init_r (void); extern ssize_t spi_read (uchar *, int, uchar *, int); diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 29e4807ea2a..47a87862c2a 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -38,14 +38,22 @@ /* * Identify the board */ -#define CONFIG_IDENT_STRING " GEN860T" +#if !defined(CONFIG_SC) +#define CONFIG_IDENT_STRING " B2" +#else +#define CONFIG_IDENT_STRING " SC" +#endif /* * Don't depend on the RTC clock to determine clock frequency - * the 860's internal rtc uses a 32.768 KHz clock which is * generated by the DS1337 - and the DS1337 clock can be turned off. */ -#define CONFIG_8xx_GCLK_FREQ 66600000 +#if !defined(CONFIG_SC) +#define CONFIG_8xx_GCLK_FREQ 66600000 +#else +#define CONFIG_8xx_GCLK_FREQ 48000000 +#endif /* * The RS-232 console port is on SMC1 @@ -143,7 +151,7 @@ * environment so that we can autoscript the full default environment. */ #define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.200 +#define CONFIG_SERVERIP 10.0.4.201 #define CONFIG_IPADDR 10.0.4.111 /* @@ -156,17 +164,20 @@ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ #define CFG_ENV_EEPROM_SIZE (32 * 1024) -#undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C - /* - * Configure software I2C support (taken from IP860 BSP). - * The I2C bus is connected to the GEN860T's 'dedicated' I2C - * pins, i.e. PB26 and PB27 + * Enable I2C and select the hardware/software driver */ +#define CONFIG_HARD_I2C 1 /* CPM based I2C */ +#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ + +#ifdef CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100000 /* clock speed in Hz */ +#define CFG_I2C_SLAVE 0xFE /* I2C slave address */ +#endif + +#ifdef CONFIG_SOFT_I2C #define PB_SCL 0x00000020 /* PB 26 */ #define PB_SDA 0x00000010 /* PB 27 */ - #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) @@ -176,15 +187,14 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 100000 /* clock speed in Hz */ -#define CFG_I2C_SLAVE 0xFE /* I2C slave address */ +#endif /* * Allow environment overwrites by anyone */ #define CONFIG_ENV_OVERWRITE +#if !defined(CONFIG_SC) /* * The MPC860's internal RTC is horribly broken in rev D masks. Three * internal MPC860T circuit nodes were inadvertently left floating; this @@ -193,35 +203,55 @@ * reasonable battery can keep that kind RTC running during powerdown for any * length of time, so we use an external RTC on the I2C bus instead. */ -#undef CONFIG_RTC_MPC8xx #define CONFIG_RTC_DS1337 -#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_I2C_RTC_ADDR 0x68 +#else /* - * Allow partial commands to be matched to uniqueness. + * No external RTC on SC variant, so we're stuck with the internal one. */ -#define CFG_MATCH_PARTIAL_CMD +#define CONFIG_RTC_MPC8xx +#endif + +/* + * Power On Self Test support + */ +#define CONFIG_POST ( CFG_POST_CACHE | \ + CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_SPR ) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 +#endif /* * List of available monitor commands. Use the system default list * plus add some of the "non-standard" commands back in. * See ./cmd_confdefs.h */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ +#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ CFG_CMD_I2C | \ - CFG_CMD_DOC | \ CFG_CMD_EEPROM | \ CFG_CMD_REGINFO | \ CFG_CMD_IMMAP | \ CFG_CMD_ELF | \ CFG_CMD_DATE | \ - CFG_CMD_DATE | \ CFG_CMD_FPGA | \ CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) + CFG_CMD_BEDBUG | \ + CFG_CMD_POST_DIAG ) + +#if !defined(CONFIG_SC) +#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) +#else +#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS +#endif /* * There is no IDE/PCMCIA hardware support on the board. @@ -258,7 +288,12 @@ * Verbose help from command monitor. */ #define CFG_LONGHELP -#define CFG_PROMPT "gen860t> " +#if !defined(CONFIG_SC) +#define CFG_PROMPT "B2> " +#else +#define CFG_PROMPT "SC> " +#endif + /* * Use the "hush" command parser @@ -393,15 +428,9 @@ /* * Reserve memory for U-Boot. */ -#define CFG_MAX_U_BOOT_SECT 3 - -#if defined(DEBUG) -#define CFG_MONITOR_LEN (512 * 1024) -#else -#define CFG_MONITOR_LEN (256 * 1024) -#endif - -#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MAX_UBOOT_SECTS 4 +#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE) +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* * Select environment placement. NOTE that u-boot.lds must @@ -414,8 +443,14 @@ #define CFG_ENV_SIZE (2 * 1024) #define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024)) #else -#define CFG_ENV_SIZE (4 * 1024) -#define CFG_ENV_OFFSET (CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE) +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE + +/* + * This ultimately gets passed right into the linker script, so we have to + * use a number :( + */ +#define CFG_ENV_OFFSET 0x060000 #endif /* @@ -439,7 +474,7 @@ #endif /*------------------------------------------------------------------------ - * SYPCR - System Protection Control UM 11-9 + * SYPCR - System Protection Control UM 11-9 * ----------------------------------------------------------------------- * SYPCR can only be written once after reset! * @@ -523,6 +558,7 @@ */ #define SCCR_MASK SCCR_EBDF11 +#if !defined(CONFIG_SC) #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ SCCR_COM00 | /* full strength CLKOUT */ \ SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ @@ -530,6 +566,17 @@ SCCR_DFNL000 | \ SCCR_DFNH000 \ ) +#else +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ + SCCR_DFNL000 | \ + SCCR_DFNH000 | \ + SCCR_RTDIV | \ + SCCR_RTSEL \ + ) +#endif /*----------------------------------------------------------------------- * DER - Debug Enable Register UM 37-46 @@ -695,10 +742,12 @@ /* * Disk On Chip (millenium) configuration */ +#if !defined(CONFIG_SC) #define CFG_MAX_DOC_DEVICE 1 #undef CFG_DOC_SUPPORT_2000 #define CFG_DOC_SUPPORT_MILLENNIUM #undef CFG_DOC_PASSIVE_PROBE +#endif /* * FEC interrupt assignment diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 86281dd5fbe..1ea9a5e162e 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -203,11 +203,15 @@ /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifndef CONFIG_300MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 83333000 /* in Hz */ -#endif +#ifdef CONFIG_MPC8255 +# define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#else /* !CONFIG_MPC8255 */ +# ifndef CONFIG_300MHz +# define CONFIG_8260_CLKIN 66666666 /* in Hz */ +# else +# define CONFIG_8260_CLKIN 83333000 /* in Hz */ +# endif +#endif /* CONFIG_MPC8255 */ #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) #define CONFIG_BAUDRATE 230400 @@ -311,15 +315,19 @@ * defines for the various registers affected by the HRCW e.g. changing * HRCW_DPPCxx requires you to also change CFG_SIUMCR. */ -#if defined(CONFIG_266MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0111) -#elif defined(CONFIG_300MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0110) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) -#endif +#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) + +#ifdef CONFIG_MPC8255 +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +#else /* ! MPC8255 */ +# if defined(CONFIG_266MHz) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +# elif defined(CONFIG_300MHz) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) +# else +# define CFG_HRCW_MASTER (__HRCW__ALL__) +# endif +#endif /* CONFIG_MPC8255 */ /* no slaves so just fill with zeros */ #define CFG_HRCW_SLAVE1 0 diff --git a/include/configs/atc.h b/include/configs/atc.h new file mode 100644 index 00000000000..ca6b740aafc --- /dev/null +++ b/include/configs/atc.h @@ -0,0 +1,442 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_ATC 1 /* ...on a ATC board */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ + +#define CONFIG_BAUDRATE 115200 + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_ON_FCC + +#define CONFIG_NET_MULTI +#define CONFIG_ETHER_ON_FCC2 + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#define CONFIG_ETHER_ON_FCC3 + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the local Bus (see 28-13) + * - Enable Half Duplex in FSMR + */ +# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 64000000 /* in Hz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ + +#define CONFIG_PREBOOT \ + "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\ + "bootm" + +/*----------------------------------------------------------------------- + * Miscellaneous configuration options + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ + +#define CFG_ALLOC_DPRAM + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SPI + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash configuration + */ + +#define CFG_BOOTROM_BASE 0xFF800000 +#define CFG_BOOTROM_SIZE 0x00080000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x00800000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CONFIG_FLASH_16BIT + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ + HRCW_BPS10 | HRCW_DPPC10 |\ + HRCW_APPC10) + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#if 1 +/* environment is in Flash */ +#define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) +# define CFG_ENV_SIZE 0x10000 +# define CFG_ENV_SECT_SIZE 0x10000 +#else +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#endif +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ + HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\ + SIUMCR_CS10PC00|SIUMCR_BCTLC10) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +#define CFG_MIN_AM_MASK 0xC0000000 +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescaler Register 10-18 + *----------------------------------------------------------------------- + */ +#define CFG_MPTPR 0x1F00 + +/*----------------------------------------------------------------------- + * PSRT - Refresh Timer Register 10-16 + *----------------------------------------------------------------------- + */ +#define CFG_PSRT 0x0f + +/*----------------------------------------------------------------------- + * PSRT - SDRAM Mode Register 10-10 + *----------------------------------------------------------------------- + */ + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A10 |\ + ORxS_NUMR_11) + +#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A16_A18 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit Boot ROM + * 1 60x GPCM 64 bit FLASH + * 2 60x SDRAM 64 bit SDRAM + * + */ + +#define CFG_MRS_OFFS 0x00000000 + +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + + +/* Bank 2 - 60x bus SDRAM + */ +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2_8COL + +#define CFG_PSDMR CFG_PSDMR_8COL +#endif /* CFG_RAMBOOT */ + +#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index 773573d479c..0d5a56ebc64 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -97,20 +97,20 @@ void status_led_set (int led, int state); # define STATUS_LED_DAT im_ioport.iop_padat # define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */ -# define STATUS_LED_PERIOD (CFG_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING +# define STATUS_LED_PERIOD (CFG_HZ / 4) +# define STATUS_LED_STATE STATUS_LED_OFF # define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */ -# define STATUS_LED_PERIOD1 (CFG_HZ / 2) +# define STATUS_LED_PERIOD1 (CFG_HZ / 8) # define STATUS_LED_STATE1 STATUS_LED_BLINKING # define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */ -# define STATUS_LED_PERIOD2 (CFG_HZ / 2) -# define STATUS_LED_STATE2 STATUS_LED_BLINKING +# define STATUS_LED_PERIOD2 (CFG_HZ / 4) +# define STATUS_LED_STATE2 STATUS_LED_OFF # define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */ -# define STATUS_LED_PERIOD3 (CFG_HZ / 2) -# define STATUS_LED_STATE3 STATUS_LED_BLINKING +# define STATUS_LED_PERIOD3 (CFG_HZ / 4) +# define STATUS_LED_STATE3 STATUS_LED_OFF # define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ -# define STATUS_LED_BOOT 0 /* Boot status on LED 1 */ +# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */ /***** IVMS8 **********************************************************/ #elif defined(CONFIG_IVMS8) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 4b1edeec0d2..923f70e9ef6 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -50,8 +50,10 @@ #include <cmd_bedbug.h> #endif #ifdef CFG_ALLOC_DPRAM +#if !defined(CONFIG_8260) #include <commproc.h> #endif +#endif #include <version.h> #if defined(CONFIG_BAB7xx) #include <w83c553f.h> @@ -277,8 +279,10 @@ init_fnc_t *init_sequence[] = { get_clocks, /* get CPU and bus clocks (etc.) */ init_timebase, #ifdef CFG_ALLOC_DPRAM +#if !defined(CONFIG_8260) dpram_init, #endif +#endif #if defined(CONFIG_BOARD_POSTCLK_INIT) board_postclk_init, #endif |