diff options
164 files changed, 6485 insertions, 7799 deletions
@@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc6 +EXTRAVERSION = NAME = # *DOCUMENTATION* diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 2e71ff2dc97..b4126c61df1 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -46,3 +46,5 @@ obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o + +obj-$(CONFIG_SYSINFO_SMBIOS) += sysinfo.o diff --git a/arch/arm/cpu/armv8/sysinfo.c b/arch/arm/cpu/armv8/sysinfo.c new file mode 100644 index 00000000000..850142da37d --- /dev/null +++ b/arch/arm/cpu/armv8/sysinfo.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Linaro Limited + * Author: Raymond Mao <raymond.mao@linaro.org> + */ +#include <dm.h> +#include <smbios_plat.h> +#include <stdio.h> +#include <sysinfo.h> + +union ccsidr_el1 { + struct { + u64 linesize:3; + u64 associativity:10; + u64 numsets:15; + u64 unknown:4; + u64 reserved:32; + } no_ccidx; + struct { + u64 linesize:3; + u64 associativity:21; + u64 reserved1:8; + u64 numsets:24; + u64 reserved2:8; + } ccidx_aarch64; + struct { + u64 linesize:3; + u64 associativity:21; + u64 reserved:8; + u64 unallocated:32; + } ccidx_aarch32; + u64 data; +}; + +union midr_el1 { + struct { + u64 revision:4; + u64 partnum:12; + u64 architecture:4; + u64 variant:4; + u64 implementer:8; + u64 reserved:32; + } fields; + u64 data; +}; + +enum { + CACHE_NONE, + CACHE_INST_ONLY, + CACHE_DATA_ONLY, + CACHE_INST_WITH_DATA, + CACHE_UNIFIED, +}; + +enum { + CACHE_ASSOC_DIRECT_MAPPED = 1, + CACHE_ASSOC_2WAY = 2, + CACHE_ASSOC_4WAY = 4, + CACHE_ASSOC_8WAY = 8, + CACHE_ASSOC_16WAY = 16, + CACHE_ASSOC_12WAY = 12, + CACHE_ASSOC_24WAY = 24, + CACHE_ASSOC_32WAY = 32, + CACHE_ASSOC_48WAY = 48, + CACHE_ASSOC_64WAY = 64, + CACHE_ASSOC_20WAY = 20, +}; + +enum { + VENDOR_RESERVED = 0, + VENDOR_ARM = 0x41, + VENDOR_BROADCOM = 0x42, + VENDOR_CAVIUM = 0x43, + VENDOR_DEC = 0x44, + VENDOR_FUJITSU = 0x46, + VENDOR_INFINEON = 0x49, + VENDOR_FREESCALE = 0x4d, + VENDOR_NVIDIA = 0x4e, + VENDOR_AMCC = 0x50, + VENDOR_QUALCOMM = 0x51, + VENDOR_MARVELL = 0x56, + VENDOR_INTEL = 0x69, + VENDOR_AMPERE = 0xc0, +}; + +/* + * TODO: + * To support ARMv8.3, we need to read "CCIDX, bits [23:20]" from + * ID_AA64MMFR2_EL1 to get the format of CCSIDR_EL1: + * + * 0b0000 - 32-bit format implemented for all levels of the CCSIDR_EL1. + * 0b0001 - 64-bit format implemented for all levels of the CCSIDR_EL1. + * + * Here we assume to use CCSIDR_EL1 in no CCIDX layout: + * NumSets, bits [27:13]: (Number of sets in cache) - 1 + * Associativity, bits [12:3]: (Associativity of cache) - 1 + * LineSize, bits [2:0]: (Log2(Number of bytes in cache line)) - 4 + */ +int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo) +{ + u64 clidr_el1; + u32 csselr_el1; + u32 num_sets; + union ccsidr_el1 creg; + int cache_type; + + sysinfo_cache_info_default(cinfo); + + /* Read CLIDR_EL1 */ + asm volatile("mrs %0, clidr_el1" : "=r" (clidr_el1)); + debug("CLIDR_EL1: 0x%llx\n", clidr_el1); + + cache_type = (clidr_el1 >> (3 * level)) & 0x7; + if (cache_type == CACHE_NONE) /* level does not exist */ + return -1; + + switch (cache_type) { + case CACHE_INST_ONLY: + cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_INST; + break; + case CACHE_DATA_ONLY: + cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_DATA; + break; + case CACHE_UNIFIED: + cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED; + break; + case CACHE_INST_WITH_DATA: + cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_OTHER; + break; + default: + cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN; + break; + } + + /* Select cache level */ + csselr_el1 = (level << 1); + asm volatile("msr csselr_el1, %0" : : "r" (csselr_el1)); + + /* Read CCSIDR_EL1 */ + asm volatile("mrs %0, ccsidr_el1" : "=r" (creg.data)); + debug("CCSIDR_EL1 (Level %d): 0x%llx\n", level + 1, creg.data); + + /* Extract cache size and associativity */ + cinfo->line_size = 1 << (creg.no_ccidx.linesize + 4); + + /* Map the associativity value */ + switch (creg.no_ccidx.associativity + 1) { + case CACHE_ASSOC_DIRECT_MAPPED: + cinfo->associativity = SMBIOS_CACHE_ASSOC_DMAPPED; + break; + case CACHE_ASSOC_2WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_2WAY; + break; + case CACHE_ASSOC_4WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_4WAY; + break; + case CACHE_ASSOC_8WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_8WAY; + break; + case CACHE_ASSOC_16WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_16WAY; + break; + case CACHE_ASSOC_12WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_12WAY; + break; + case CACHE_ASSOC_24WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_24WAY; + break; + case CACHE_ASSOC_32WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_32WAY; + break; + case CACHE_ASSOC_48WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_48WAY; + break; + case CACHE_ASSOC_64WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_64WAY; + break; + case CACHE_ASSOC_20WAY: + cinfo->associativity = SMBIOS_CACHE_ASSOC_20WAY; + break; + default: + cinfo->associativity = SMBIOS_CACHE_ASSOC_UNKNOWN; + break; + } + + num_sets = creg.no_ccidx.numsets + 1; + /* Size in KB */ + cinfo->max_size = (cinfo->associativity * num_sets * cinfo->line_size) / + 1024; + + debug("L%d Cache:\n", level + 1); + debug("Number of bytes in cache line:%u\n", cinfo->line_size); + debug("Associativity of cache:%u\n", cinfo->associativity); + debug("Number of sets in cache:%u\n", num_sets); + debug("Cache size in KB:%u\n", cinfo->max_size); + + cinfo->inst_size = cinfo->max_size; + + /* + * Below fields with common values are placed under DT smbios node + * socket-design, config + * Other fields are typically specific to the implementation of the ARM + * processor by the silicon vendor: + * supp_sram_type, curr_sram_type, speed, err_corr_type + */ + + return 0; +} + +int sysinfo_get_processor_info(struct processor_info *pinfo) +{ + u64 mpidr, core_count; + union midr_el1 midr; + + /* Read the MIDR_EL1 register */ + asm volatile("mrs %0, MIDR_EL1" : "=r"(midr.data)); + /* Read the MPIDR_EL1 register */ + asm volatile("mrs %0, MPIDR_EL1" : "=r"(mpidr)); + + debug("MIDR: 0x%016llx\n", midr.data); + debug("MPIDR: 0x%016llx\n", mpidr); + debug("CPU Implementer: 0x%02x\n", midr.fields.implementer); + + switch (midr.fields.implementer) { + case VENDOR_ARM: + pinfo->manufacturer = "ARM Limited"; + break; + case VENDOR_BROADCOM: + pinfo->manufacturer = "Broadcom Corporation"; + break; + case VENDOR_CAVIUM: + pinfo->manufacturer = "Cavium Inc"; + break; + case VENDOR_DEC: + pinfo->manufacturer = "Digital Equipment Corporation"; + break; + case VENDOR_FUJITSU: + pinfo->manufacturer = "Fujitsu Ltd"; + break; + case VENDOR_INFINEON: + pinfo->manufacturer = "Infineon Technologies AG"; + break; + case VENDOR_FREESCALE: + pinfo->manufacturer = "Freescale Semiconductor Inc"; + break; + case VENDOR_NVIDIA: + pinfo->manufacturer = "NVIDIA Corporation"; + break; + case VENDOR_AMCC: + pinfo->manufacturer = + "Applied Micro Circuits Corporation"; + break; + case VENDOR_QUALCOMM: + pinfo->manufacturer = "Qualcomm Inc"; + break; + case VENDOR_MARVELL: + pinfo->manufacturer = "Marvell International Ltd"; + break; + case VENDOR_INTEL: + pinfo->manufacturer = "Intel Corporation"; + break; + case VENDOR_AMPERE: + pinfo->manufacturer = "Ampere Computing"; + break; + default: + pinfo->manufacturer = "Unknown"; + break; + } + debug("CPU part number: 0x%x\n", midr.fields.partnum); + debug("CPU revision: 0x%x\n", midr.fields.revision); + debug("CPU architecture: 0x%x\n", midr.fields.architecture); + debug("CPU variant: 0x%x\n", midr.fields.variant); + + /* Extract number of cores */ + core_count = (mpidr >> 0) & 0xFF; + pinfo->core_count = core_count + 1; + debug("CPU Core Count: %d\n", pinfo->core_count); + + pinfo->core_enabled = pinfo->core_count; + pinfo->characteristics = SMBIOS_PROCESSOR_64BIT | + SMBIOS_PROCESSOR_ARM64_SOCID; + if (pinfo->core_count > 1) + pinfo->characteristics |= SMBIOS_PROCESSOR_MULTICORE; + + /* + * Below fields with common values are placed under DT smbios node + * version, processor-type, processor-status, upgrade, family2, + * socket-design, serial, asset-tag, part-number + */ + + return 0; +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 23b537a2fcb..aef0425c967 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -55,27 +55,17 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb -dtb-$(CONFIG_ROCKCHIP_RK3066) += \ - rk3066a-mk808.dtb - dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb -dtb-$(CONFIG_ROCKCHIP_RK3188) += \ - rk3188-radxarock.dtb - dtb-$(CONFIG_ROCKCHIP_RK322X) += \ rk3229-evb.dtb dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ - rk3288-firefly.dtb \ - rk3288-miqi.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ rk3288-rock-pi-n8.dtb \ - rk3288-tinker.dtb \ - rk3288-tinker-s.dtb \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ diff --git a/arch/arm/dts/qemu-arm64.dts b/arch/arm/dts/qemu-arm64.dts index 096b3910728..95fcf53ed74 100644 --- a/arch/arm/dts/qemu-arm64.dts +++ b/arch/arm/dts/qemu-arm64.dts @@ -7,5 +7,9 @@ /dts-v1/; +#if defined(CONFIG_SYSINFO_SMBIOS) && !defined(QFW_SMBIOS) +#include "smbios_generic.dtsi" +#endif + / { }; diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts deleted file mode 100644 index 06790f05b39..00000000000 --- a/arch/arm/dts/rk3066a-mk808.dts +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Paweł Jarosz <paweljarosz3691@gmail.com> - */ - -/dts-v1/; -#include <dt-bindings/input/input.h> -#include "rk3066a.dtsi" - -/ { - model = "Rikomagic MK808"; - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@60000000 { - reg = <0x60000000 0x40000000>; - device_type = "memory"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <2500000>; - poll-interval = <100>; - - button-recovery { - label = "recovery"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue_led: led-0 { - label = "mk808:blue:power"; - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "default-on"; - }; - }; - - hdmi_con { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vcc_2v5: vcc-2v5 { - compatible = "regulator-fixed"; - regulator-name = "vcc_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&host_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&otg_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_wifi: sdio-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wifi_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_in_vop1 { - status = "disabled"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - non-removable; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_wifi>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&nfc { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - nand@0 { - reg = <0>; - label = "rk-nand"; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-step-size = <1024>; - nand-ecc-strength = <40>; - nand-is-boot-medium; - rockchip,boot-blks = <8>; - rockchip,boot-ecc-strength = <24>; - }; -}; - -&pinctrl { - usb-host { - host_drv: host-drv { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb-otg { - otg_drv: otg-drv { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - wifi_pwr: wifi-pwr { - rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_2v5>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vop0 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 06f405ca2c5..d99db7853b5 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -3,26 +3,6 @@ #include "rockchip-u-boot.dtsi" #include "rk3xxx-u-boot.dtsi" -&gpio0 { - gpio-ranges = <&pinctrl 0 0 32>; -}; - -&gpio1 { - gpio-ranges = <&pinctrl 0 32 32>; -}; - -&gpio2 { - gpio-ranges = <&pinctrl 0 64 32>; -}; - -&gpio3 { - gpio-ranges = <&pinctrl 0 96 32>; -}; - -&gpio4 { - gpio-ranges = <&pinctrl 0 128 32>; -}; - &gpio6 { status = "disabled"; }; diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi deleted file mode 100644 index de9915d946f..00000000000 --- a/arch/arm/dts/rk3066a.dtsi +++ /dev/null @@ -1,880 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3066a-cru.h> -#include <dt-bindings/power/rk3066-power.h> -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3066a"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - operating-points = - /* kHz uV */ - <1416000 1300000>, - <1200000 1175000>, - <1008000 1125000>, - <816000 1125000>, - <600000 1100000>, - <504000 1100000>, - <312000 1075000>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010c000 0x19c>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_LCDC0>, - <&cru DCLK_LCDC0>, - <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, - <&cru SRST_LCDC0_AHB>, - <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop0_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop0>; - }; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010e000 0x19c>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, - <&cru SRST_LCDC1_AHB>, - <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop1_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop1>; - }; - }; - }; - - hdmi: hdmi@10116000 { - compatible = "rockchip,rk3066-hdmi"; - reg = <0x10116000 0x2000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HDMI>; - clock-names = "hclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; - power-domains = <&power RK3066_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vop0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop0_out_hdmi>; - }; - - hdmi_in_vop1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vop1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - i2s0: i2s@10118000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x10118000 0x2000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 4>, <&dmac1_s 5>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@1011a000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@1011c000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011c000 0x2000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 9>, <&dmac1_s 10>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <400000000>, <594000000>, - <300000000>, <150000000>, - <75000000>, <300000000>, - <150000000>, <75000000>; - }; - - timer2: timer@2000e000 { - compatible = "snps,dw-apb-timer"; - reg = <0x2000e000 0x100>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3066a-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - timer0: timer@20038000 { - compatible = "snps,dw-apb-timer"; - reg = <0x20038000 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer1: timer@2003a000 { - compatible = "snps,dw-apb-timer"; - reg = <0x2003a000 0x100>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - tsadc: tsadc@20060000 { - compatible = "rockchip,rk3066-tsadc"; - reg = <0x20060000 0x100>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "saradc", "apb_pclk"; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - resets = <&cru SRST_TSADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg-pull-default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ - <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ - <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ - <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ - <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ - <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ - <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ - <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ - <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, - <2 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, - <2 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, - <3 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, - <3 RK_PA3 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, - <1 RK_PB1 1 &pcfg_pull_default>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, - <3 RK_PD4 1 &pcfg_pull_default>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, - <3 RK_PB3 1 &pcfg_pull_default>, - <3 RK_PB4 1 &pcfg_pull_default>, - <3 RK_PB5 1 &pcfg_pull_default>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, - <3 RK_PC2 1 &pcfg_pull_default>, - <3 RK_PC3 1 &pcfg_pull_default>, - <3 RK_PC4 1 &pcfg_pull_default>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, - <0 RK_PB0 1 &pcfg_pull_default>, - <0 RK_PB1 1 &pcfg_pull_default>, - <0 RK_PB2 1 &pcfg_pull_default>, - <0 RK_PB3 1 &pcfg_pull_default>, - <0 RK_PB4 1 &pcfg_pull_default>, - <0 RK_PB5 1 &pcfg_pull_default>, - <0 RK_PB6 1 &pcfg_pull_default>, - <0 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, - <0 RK_PC1 1 &pcfg_pull_default>, - <0 RK_PC2 1 &pcfg_pull_default>, - <0 RK_PC3 1 &pcfg_pull_default>, - <0 RK_PC4 1 &pcfg_pull_default>, - <0 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - i2s2 { - i2s2_bus: i2s2-bus { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, - <0 RK_PD1 1 &pcfg_pull_default>, - <0 RK_PD2 1 &pcfg_pull_default>, - <0 RK_PD3 1 &pcfg_pull_default>, - <0 RK_PD4 1 &pcfg_pull_default>, - <0 RK_PD5 1 &pcfg_pull_default>; - }; - }; - }; -}; - -&gpu { - compatible = "rockchip,rk3066-mali", "arm,mali-400"; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3066_PD_GPU>; -}; - -&grf { - compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; - - usbphy: usbphy { - compatible = "rockchip,rk3066a-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@188 { - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&mmc0 { - clock-frequency = <50000000>; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - max-frequency = <50000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; -}; - -&mmc1 { - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; -}; - -&emmc { - dmas = <&dmac2 4>; - dma-names = "rx-tx"; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3066-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3066_PD_VIO { - reg = <RK3066_PD_VIO>; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF1>, - <&cru ACLK_CIF1>, - <&cru HCLK_CIF1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru HCLK_HDMI>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_cif1>, - <&qos_ipp>, - <&qos_rga>; - #power-domain-cells = <0>; - }; - - power-domain@RK3066_PD_VIDEO { - reg = <RK3066_PD_VIDEO>; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3066_PD_GPU { - reg = <RK3066_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 0>, <&dmac1_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 2>, <&dmac1_s 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 8>, <&dmac2 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&vpu { - power-domains = <&power RK3066_PD_VIDEO>; -}; - -&wdt { - compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; -}; - -&emac { - compatible = "rockchip,rk3066-emac"; -}; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts deleted file mode 100644 index 118deacd38c..00000000000 --- a/arch/arm/dts/rk3188-radxarock.dts +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - */ - -/dts-v1/; -#include <dt-bindings/input/input.h> -#include "rk3188.dtsi" - -/ { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; - - aliases { - mmc0 = &mmc0; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green_led: led-0 { - label = "rock:green:user1"; - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue_led: led-1 { - label = "rock:blue:user2"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep_led: led-2 { - label = "rock:red:power"; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&emac { - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&gpu { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - system-power-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&act8846_dvs0_ctl>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_hdmi: REG6 { - regulator-name = "VDD_HDMI"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vcc18: REG7 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_rmii: REG9 { - regulator-name = "VCC_RMII"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC18_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28: REG12 { - regulator-name = "VCC_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lan8720a { - phy_int: phy-int { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd0 { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 176f9e65c26..8f2849dda24 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -6,25 +6,8 @@ #include "rockchip-u-boot.dtsi" #include "rk3xxx-u-boot.dtsi" -&global_timer { - status = "okay"; -}; - &gpio0 { compatible = "rockchip,gpio-bank"; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -&gpio1 { - gpio-ranges = <&pinctrl 0 32 32>; -}; - -&gpio2 { - gpio-ranges = <&pinctrl 0 64 32>; -}; - -&gpio3 { - gpio-ranges = <&pinctrl 0 96 32>; }; &pmu { diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi deleted file mode 100644 index 44b54af0bbf..00000000000 --- a/arch/arm/dts/rk3188.dtsi +++ /dev/null @@ -1,815 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3188-cru.h> -#include <dt-bindings/power/rk3188-power.h> -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE1>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE2>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE3>; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <875000>; - clock-latency-ns = <40000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <925000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <975000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1075000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1150000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1250000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010c000 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010e000 0x1000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - timer3: timer@2000e000 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x2000e000 0x20>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; - clock-names = "pclk", "timer"; - }; - - timer6: timer@200380a0 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x200380a0 0x20>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; - clock-names = "pclk", "timer"; - }; - - i2s0: i2s@1011a000 { - compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: sound@1011e000 { - compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; - reg = <0x1011e000 0x2000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1_s 8>; - dma-names = "tx"; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3188-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ - <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ - <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ - <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ - <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ - <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ - <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ - <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, - <3 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, - <1 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, - <3 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, - <1 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - lcdc1 { - lcdc1_dclk: lcdc1-dclk { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; - }; - - lcdc1_den: lcdc1-den { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; - }; - - lcdc1_hsync: lcdc1-hsync { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; - }; - - lcdc1_vsync: lcdc1-vsync { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; - }; - - lcdc1_rgb24: lcdc1-rgb24 { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, - <2 RK_PA1 1 &pcfg_pull_none>, - <2 RK_PA2 1 &pcfg_pull_none>, - <2 RK_PA3 1 &pcfg_pull_none>, - <2 RK_PA4 1 &pcfg_pull_none>, - <2 RK_PA5 1 &pcfg_pull_none>, - <2 RK_PA6 1 &pcfg_pull_none>, - <2 RK_PA7 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB1 1 &pcfg_pull_none>, - <2 RK_PB2 1 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC2 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none>, - <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>, - <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, - <1 RK_PA1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, - <1 RK_PB1 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>, - <3 RK_PA6 1 &pcfg_pull_none>, - <3 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, - <3 RK_PC2 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, - <1 RK_PC1 1 &pcfg_pull_none>, - <1 RK_PC2 1 &pcfg_pull_none>, - <1 RK_PC3 1 &pcfg_pull_none>, - <1 RK_PC4 1 &pcfg_pull_none>, - <1 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; - }; - }; - }; -}; - -&emac { - compatible = "rockchip,rk3188-emac"; -}; - -&global_timer { - interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; -}; - -&local_timer { - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; -}; - -&gpu { - compatible = "rockchip,rk3188-mali", "arm,mali-400"; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3188_PD_GPU>; -}; - -&grf { - compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; - - io_domains: io-domains { - compatible = "rockchip,rk3188-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3188-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@11c { - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - }; -}; - -&i2c0 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3188-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3188_PD_VIO { - reg = <RK3188_PD_VIO>; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_ipp>, - <&qos_rga>; - #power-domain-cells = <0>; - }; - - power-domain@RK3188_PD_VIDEO { - reg = <RK3188_PD_VIDEO>; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3188_PD_GPU { - reg = <RK3188_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&vpu { - compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; - power-domains = <&power RK3188_PD_VIDEO>; -}; - -&wdt { - compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; -}; diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 644198a4a2f..b7d13bcb860 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -6,21 +6,8 @@ #include "rk3288-u-boot.dtsi" / { - config { - bootph-all; - u-boot,boot-led = "firefly:green:power"; - }; - - leds { - bootph-all; - - work { - bootph-all; - }; - - power { - bootph-all; - }; + chosen { + stdout-path = "serial2:115200n8"; }; }; @@ -36,46 +23,100 @@ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; -&pinctrl { - bootph-all; +&emmc { + bootph-pre-ram; + bootph-some-ram; }; -&uart2 { - bootph-all; +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; }; -&sdmmc { - bootph-all; +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; }; -&emmc { - bootph-all; +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_pwr { + bootph-pre-ram; + bootph-some-ram; +}; + +&gmac { + snps,reset-delays-us = <0 10000 80000>; +}; + +&gpio7 { + /delete-property/ bootph-all; + bootph-pre-ram; }; -&gpio3 { +&pcfg_pull_none { bootph-all; }; -&gpio8 { +&pcfg_pull_none_12ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up { bootph-all; }; &pcfg_pull_up_drv_12ma { bootph-pre-ram; + bootph-some-ram; +}; + +&power_led { + default-state = "on"; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_bus4 { bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cd { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_pwr { bootph-pre-ram; }; + +&uart2 { + bootph-all; +}; + +&uart2_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts deleted file mode 100644 index 72982efdf6d..00000000000 --- a/arch/arm/dts/rk3288-firefly.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288"; - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&ir { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi deleted file mode 100644 index 0824b19ee64..00000000000 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> - */ - -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - button@0 { - gpio-key,wakeup = <1>; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = <116>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led>; - }; - - power { - gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; - label = "firefly:green:power"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led: power-led { - rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led: work-led { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vcc_18>; - status = "disabled"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 43cb48bd032..e5c7e761c46 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -4,15 +4,6 @@ */ #include "rk3288-u-boot.dtsi" -/ { - leds { - bootph-all; - - work { - bootph-all; - }; - }; -}; &dmc { rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa @@ -25,34 +16,96 @@ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; -&pinctrl { - bootph-all; +&emmc { + bootph-pre-ram; + bootph-some-ram; }; -&uart2 { - bootph-all; +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; }; -&sdmmc { +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_pwr { + bootph-pre-ram; + bootph-some-ram; +}; + +&gmac { + snps,reset-delays-us = <0 10000 80000>; +}; + +&gpio7 { + /delete-property/ bootph-all; + bootph-pre-ram; +}; + +&pcfg_pull_none { bootph-all; }; -&emmc { +&pcfg_pull_none_12ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up { bootph-all; }; +&pcfg_pull_up_drv_12ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; +}; + &sdmmc_bus4 { bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cd { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_pwr { bootph-pre-ram; }; + +&uart2 { + bootph-all; +}; + +&uart2_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts deleted file mode 100644 index 4a2f249e1b1..00000000000 --- a/arch/arm/dts/rk3288-miqi.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-miqi.dtsi" - -/ { - model = "mqmaker MiQi"; - compatible = "mqmaker,miqi", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; -}; diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi deleted file mode 100644 index c56e1109e3a..00000000000 --- a/arch/arm/dts/rk3288-miqi.dtsi +++ /dev/null @@ -1,417 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> - */ - -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - label = "miqi:green:user"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - leds { - led_ctl: led-ctl { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - vbus-supply = <&vcc_host>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi index b4c5483146a..614d47ce180 100644 --- a/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi @@ -15,20 +15,25 @@ &emmc { bootph-pre-ram; + bootph-some-ram; }; -&emmc_clk { +&emmc_bus8 { bootph-pre-ram; + bootph-some-ram; }; -&emmc_cmd { +&emmc_clk { bootph-pre-ram; + bootph-some-ram; }; -&emmc_pwr { +&emmc_cmd { bootph-pre-ram; + bootph-some-ram; }; -&emmc_bus8 { +&emmc_pwr { bootph-pre-ram; + bootph-some-ram; }; diff --git a/arch/arm/dts/rk3288-tinker-s.dts b/arch/arm/dts/rk3288-tinker-s.dts deleted file mode 100644 index cc7ac5f8811..00000000000 --- a/arch/arm/dts/rk3288-tinker-s.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "rk3288-tinker.dtsi" - -/ { - model = "Rockchip RK3288 Asus Tinker Board S"; - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - max-frequency = <150000000>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 0cf1b696d16..a6f6f14df93 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -6,7 +6,6 @@ #include "rk3288-u-boot.dtsi" &dmc { - bootph-all; rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 @@ -17,6 +16,14 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; +&gmac { + snps,reset-delays-us = <0 10000 80000>; +}; + +&gpio7 { + /delete-property/ bootph-all; +}; + &i2c2 { m24c08@50 { compatible = "at,24c08", "i2c-eeprom"; @@ -24,62 +31,54 @@ }; }; -&pinctrl { - bootph-all; -}; - -&uart2 { - bootph-all; -}; - -&uart2_xfer { +&pcfg_pull_none { bootph-all; }; -&sdmmc { - bootph-pre-ram; -}; - -&gpio7 { - bootph-pre-ram; -}; - -&vcc_sd { - bootph-pre-ram; -}; - &pcfg_pull_none_drv_8ma { bootph-pre-ram; + bootph-some-ram; }; -&pcfg_pull_up_drv_8ma { - bootph-pre-ram; +&pcfg_pull_up { + bootph-all; }; -&pcfg_pull_none { +&pcfg_pull_up_drv_8ma { bootph-pre-ram; + bootph-some-ram; }; -&pcfg_pull_up { +&sdmmc { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_bus4 { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { bootph-pre-ram; + bootph-some-ram; }; -&sdmmc_pwr { +&uart2 { + bootph-all; +}; + +&uart2_xfer { + bootph-pre-sram; bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts deleted file mode 100644 index 8b1848c310e..00000000000 --- a/arch/arm/dts/rk3288-tinker.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-tinker.dtsi" - -/ { - model = "Tinker-RK3288"; - compatible = "rockchip,rk3288-tinker", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&pinctrl { - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&usb_host1 { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-tinker.dtsi b/arch/arm/dts/rk3288-tinker.dtsi deleted file mode 100644 index 62b4beb2510..00000000000 --- a/arch/arm/dts/rk3288-tinker.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/input/input.h> -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - button@0 { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = <KEY_POWER>; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - pwr-led { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - act-led { - gpios=<&gpio2 3 GPIO_ACTIVE_LOW>; - linux,default-trigger="mmc0"; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from - * vcc_io directly. Those boards won't be able to power cycle SD cards - * but it shouldn't hurt to toggle this pin there anyway. - */ - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - supports-sd; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc33_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc18_ldo1>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc18_ldo1: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_ldo1"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_mipi: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_mipi"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_codec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc33_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - headset: nau8825@1a { - compatible = "nuvoton,nau8825"; - #sound-dai-cells = <0>; - reg = <0x1a>; - interrupt-parent = <&gpio6>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - nuvoton,jkdet-enable = <1>; - nuvoton,jkdet-pull-enable = <1>; - nuvoton,jkdet-pull-up = <0>; - nuvoton,jkdet-polarity = <1>; - nuvoton,vref-impedance = <2>; - nuvoton,micbias-voltage = <6>; - nuvoton,sar-threshold-num = <4>; - nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>; - nuvoton,sar-hysteresis = <0>; - nuvoton,sar-voltage = <6>; - nuvoton,sar-compare-time = <0>; - nuvoton,sar-sampling-time = <0>; - nuvoton,short-key-debounce = <3>; - nuvoton,jack-insert-debounce = <7>; - nuvoton,jack-eject-debounce = <7>; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S0_OUT>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc18_ldo1>; - status ="okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status= "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on EVB board so bump up to 8ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pwr_3g: pwr-3g { - rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index a43d320ade7..2205caabc51 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,15 +7,6 @@ / { aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; mmc0 = &emmc; mmc1 = &sdmmc; mmc2 = &sdio0; @@ -128,11 +119,11 @@ }; &vopb { - bootph-all; + bootph-some-ram; }; &vopl { - bootph-all; + bootph-some-ram; }; &xin24m { diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi deleted file mode 100644 index ead343dc3df..00000000000 --- a/arch/arm/dts/rk3288.dtsi +++ /dev/null @@ -1,2035 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3288-cru.h> -#include <dt-bindings/power/rk3288-power.h> -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "rockchip,rk3288"; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - arm-pmu { - compatible = "arm,cortex-a12-pmu"; - interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - rockchip,pmu = <&pmu>; - - cpu0: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x500>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu1: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x501>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu2: cpu@502 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x502>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu3: cpu@503 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x503>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - }; - - cpu_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-126000000 { - opp-hz = /bits/ 64 <126000000>; - opp-microvolt = <900000>; - }; - opp-216000000 { - opp-hz = /bits/ 64 <216000000>; - opp-microvolt = <900000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <900000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - }; - opp-696000000 { - opp-hz = /bits/ 64 <696000000>; - opp-microvolt = <950000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1050000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1200000>; - }; - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1300000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * The rk3288 cannot use the memory area above 0xfe000000 - * for dma operations for some reason. While there is - * probably a better solution available somewhere, we - * haven't found it yet and while devices with 2GB of ram - * are not affected, this issue prevents 4GB from booting. - * So to make these devices at least bootable, block - * this area for the time being until the real solution - * is found. - */ - dma-unusable@fe000000 { - reg = <0x0 0xfe000000 0x0 0x1000000>; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - }; - - timer: timer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff810000 0x0 0x20>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - sdmmc: mmc@ff0c0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0xff0c0000 0x0 0x4000>; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio0: mmc@ff0d0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0xff0d0000 0x0 0x4000>; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio1: mmc@ff0e0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, - <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0xff0e0000 0x0 0x4000>; - resets = <&cru SRST_SDIO1>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@ff0f0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0xff0f0000 0x0 0x4000>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 11>, <&dmac_peri 12>; - dma-names = "tx", "rx"; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - reg = <0x0 0xff110000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 13>, <&dmac_peri 14>; - dma-names = "tx", "rx"; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - reg = <0x0 0xff120000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff130000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 15>, <&dmac_peri 16>; - dma-names = "tx", "rx"; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - reg = <0x0 0xff130000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff140000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 1>, <&dmac_peri 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 3>, <&dmac_peri 4>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 7>, <&dmac_peri 8>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff1c0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1c0000 0x0 0x100>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 9>, <&dmac_peri 10>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - reserve_thermal: reserve-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - }; - - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 2>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - gmac: ethernet@ff290000 { - compatible = "rockchip,rk3288-gmac"; - reg = <0x0 0xff290000 0x0 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - resets = <&cru SRST_MAC>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USBHOST0>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ - usb_host0_ohci: usb@ff520000 { - compatible = "generic-ohci"; - reg = <0x0 0xff520000 0x0 0x100>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USBHOST0>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1: usb@ff540000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff540000 0x0 0x40000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USBHOST1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy2>; - phy-names = "usb2-phy"; - snps,reset-phy-on-wake; - status = "disabled"; - }; - - usb_otg: usb@ff580000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_hsic: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HSIC>; - status = "disabled"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff660000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff660000 0x0 0x1000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - bus_intmem: sram@ff700000 { - compatible = "mmio-sram"; - reg = <0x0 0xff700000 0x0 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xff700000 0x18000>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - pmu_sram: sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0x0 0xff720000 0x0 0x1000>; - }; - - pmu: power-management@ff730000 { - compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff730000 0x0 0x100>; - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - - /* - * Note: Although SCLK_* are the working clocks - * of device without including on the NOC, needed for - * synchronous reset. - * - * The clocks on the which NOC: - * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. - * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. - * ACLK_RGA is on ACLK_RGA_NIU. - * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. - * - * Which clock are device clocks: - * clocks devices - * *_IEP IEP:Image Enhancement Processor - * *_ISP ISP:Image Signal Processing - * *_VIP VIP:Video Input Processor - * *_VOP* VOP:Visual Output Processor - * *_RGA RGA - * *_EDP* EDP - * *_LVDS_* LVDS - * *_HDMI HDMI - * *_MIPI_* MIPI - */ - power-domain@RK3288_PD_VIO { - reg = <RK3288_PD_VIO>; - clocks = <&cru ACLK_IEP>, - <&cru ACLK_ISP>, - <&cru ACLK_RGA>, - <&cru ACLK_VIP>, - <&cru ACLK_VOP0>, - <&cru ACLK_VOP1>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru HCLK_IEP>, - <&cru HCLK_ISP>, - <&cru HCLK_RGA>, - <&cru HCLK_VIP>, - <&cru HCLK_VOP0>, - <&cru HCLK_VOP1>, - <&cru PCLK_EDP_CTRL>, - <&cru PCLK_HDMI_CTRL>, - <&cru PCLK_LVDS_PHY>, - <&cru PCLK_MIPI_CSI>, - <&cru PCLK_MIPI_DSI0>, - <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_EDP_24M>, - <&cru SCLK_EDP>, - <&cru SCLK_ISP_JPE>, - <&cru SCLK_ISP>, - <&cru SCLK_RGA>; - pm_qos = <&qos_vio0_iep>, - <&qos_vio1_vop>, - <&qos_vio1_isp_w0>, - <&qos_vio1_isp_w1>, - <&qos_vio0_vop>, - <&qos_vio0_vip>, - <&qos_vio2_rga_r>, - <&qos_vio2_rga_w>, - <&qos_vio1_isp_r>; - #power-domain-cells = <0>; - }; - - /* - * Note: The following 3 are HEVC(H.265) clocks, - * and on the ACLK_HEVC_NIU (NOC). - */ - power-domain@RK3288_PD_HEVC { - reg = <RK3288_PD_HEVC>; - clocks = <&cru ACLK_HEVC>, - <&cru SCLK_HEVC_CABAC>, - <&cru SCLK_HEVC_CORE>; - pm_qos = <&qos_hevc_r>, - <&qos_hevc_w>; - #power-domain-cells = <0>; - }; - - /* - * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC - * (video endecoder & decoder) clocks that on the - * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). - */ - power-domain@RK3288_PD_VIDEO { - reg = <RK3288_PD_VIDEO>; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_video>; - #power-domain-cells = <0>; - }; - - /* - * Note: ACLK_GPU is the GPU clock, - * and on the ACLK_GPU_NIU (NOC). - */ - power-domain@RK3288_PD_GPU { - reg = <RK3288_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu_r>, - <&qos_gpu_w>; - #power-domain-cells = <0>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x94>; - mode-normal = <BOOT_NORMAL>; - mode-recovery = <BOOT_RECOVERY>; - mode-bootloader = <BOOT_FASTBOOT>; - mode-loader = <BOOT_BL_DOWNLOAD>; - }; - }; - - sgrf: syscon@ff740000 { - compatible = "rockchip,rk3288-sgrf", "syscon"; - reg = <0x0 0xff740000 0x0 0x1000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3288-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, - <500000000>, <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x1000>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - status = "disabled"; - }; - - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBOTG_PHY>; - reset-names = "phy-reset"; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST0_PHY>; - reset-names = "phy-reset"; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST1_PHY>; - reset-names = "phy-reset"; - }; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; - reg = <0x0 0xff800000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - spdif: sound@ff8b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff8b0000 0x0 0x10000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2s: i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x10000>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - crypto: crypto@ff8a0000 { - compatible = "rockchip,rk3288-crypto"; - reg = <0x0 0xff8a0000 0x0 0x4000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - }; - - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x40>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - rockchip,disable-mmu-reset; - status = "disabled"; - }; - - rga: rga@ff920000 { - compatible = "rockchip,rk3288-rga"; - reg = <0x0 0xff920000 0x0 0x180>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; - reset-names = "core", "axi", "ahb"; - }; - - vopb: vop@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopb>; - }; - - vopb_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff940000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopl>; - }; - - vopl_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff940300 0x0 0x100>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_dsi: dsi@ff960000 { - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x4000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - - mipi_out: port@1 { - reg = <1>; - }; - }; - }; - - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0x0 0xff96c000 0x0 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - - lvds_out: port@1 { - reg = <1>; - }; - }; - }; - - edp: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0x0 0xff970000 0x0 0x4000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&edp_phy>; - phy-names = "dp"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_EDP>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - - edp_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0x0 0xff980000 0x0 0x20000>; - reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "cec"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - vpu_mmu: iommu@ff9a0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760"; - reg = <0x0 0xffa30000 0x0 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3288_PD_GPU>; - status = "disabled"; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <950000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1100000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1250000>; - }; - }; - - qos_gpu_r: qos@ffaa0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xffb20000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; - reg = <0x0 0xffb40000 0x0 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - cpu_id: cpu-id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3288-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff750000 0x0 0x100>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7a0000 0x0 0x100>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff7b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7b0000 0x0 0x100>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@ff7c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7c0000 0x0 0x100>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO5>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@ff7d0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7d0000 0x0 0x100>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@ff7e0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7e0000 0x0 0x100>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO7>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@ff7f0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7f0000 0x0 0x100>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO8>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hdmi { - hdmi_cec_c0: hdmi-cec-c0 { - rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; - }; - - hdmi_cec_c7: hdmi-cec-c7 { - rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; - }; - - hdmi_ddc: hdmi-ddc { - rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - - hdmi_ddc_unwedge: hdmi-ddc-unwedge { - rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - suspend { - global_pwroff: global-pwroff { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; - }; - - ddr0_retention: ddr0-retention { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; - }; - - ddr1_retention: ddr1-retention { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, - <8 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, - <6 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, - <7 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, - <7 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, - <6 RK_PA1 1 &pcfg_pull_none>, - <6 RK_PA2 1 &pcfg_pull_none>, - <6 RK_PA3 1 &pcfg_pull_none>, - <6 RK_PA4 1 &pcfg_pull_none>, - <6 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_ctl: lcdc-ctl { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>, - <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, - <6 RK_PC1 1 &pcfg_pull_up>, - <6 RK_PC2 1 &pcfg_pull_up>, - <6 RK_PC3 1 &pcfg_pull_up>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, - <4 RK_PC5 1 &pcfg_pull_up>, - <4 RK_PC6 1 &pcfg_pull_up>, - <4 RK_PC7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; - }; - }; - - sdio1 { - sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; - }; - - sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, - <3 RK_PD1 4 &pcfg_pull_up>, - <3 RK_PD2 4 &pcfg_pull_up>, - <3 RK_PD3 4 &pcfg_pull_up>; - }; - - sdio1_cd: sdio1-cd { - rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; - }; - - sdio1_wp: sdio1-wp { - rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; - }; - - sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; - }; - - sdio1_int: sdio1-int { - rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; - }; - - sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; - }; - - sdio1_clk: sdio1-clk { - rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; - }; - - sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>, - <3 RK_PA4 2 &pcfg_pull_up>, - <3 RK_PA5 2 &pcfg_pull_up>, - <3 RK_PA6 2 &pcfg_pull_up>, - <3 RK_PA7 2 &pcfg_pull_up>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; - }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_cs1: spi2-cs1 { - rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; - }; - spi2_clk: spi2-clk { - rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, - <4 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, - <5 RK_PB1 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, - <7 RK_PC7 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, - <7 RK_PB0 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, - <5 RK_PB6 3 &pcfg_pull_none>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD2 3 &pcfg_pull_none>, - <3 RK_PD3 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none_12ma>, - <3 RK_PD5 3 &pcfg_pull_none_12ma>, - <3 RK_PD0 3 &pcfg_pull_none_12ma>, - <3 RK_PD1 3 &pcfg_pull_none_12ma>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA6 3 &pcfg_pull_none>, - <4 RK_PB1 3 &pcfg_pull_none_12ma>, - <4 RK_PA4 3 &pcfg_pull_none_12ma>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none>, - <3 RK_PD5 3 &pcfg_pull_none>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA4 3 &pcfg_pull_none>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA2 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 6bdc892bd91..5517176aa4a 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -11,7 +11,7 @@ }; config { - u-boot,spl-payload-offset = <0x40000>; + u-boot,spl-payload-offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; }; }; @@ -29,11 +29,35 @@ rockchip,panel = <&edp_panel>; }; +&emmc_phy { + /delete-property/ bootph-pre-ram; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&pp1500_ap_io { + bootph-pre-ram; +}; + &pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; +&pp1500_en { + bootph-pre-ram; +}; + +&pp3000 { + bootph-pre-ram; +}; + +&pp3000_en { + bootph-pre-ram; +}; + &ppvar_bigcpu_pwm { regulator-init-microvolt = <900000>; }; @@ -80,7 +104,8 @@ &spi1 { spi_flash: flash@0 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index aecf7dbe383..883d399a06a 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { + config { + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -36,6 +40,10 @@ bootph-pre-ram; }; +&gpio1 { + bootph-pre-ram; +}; + &spi1 { flash@0 { bootph-pre-ram; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 43b67991fe5..cd84269dab4 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { + config { + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + smbios { compatible = "u-boot,sysinfo-smbios"; smbios { @@ -32,6 +36,10 @@ bootph-pre-ram; }; +&gpio1 { + bootph-pre-ram; +}; + &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 2bec139d833..70f35b6c197 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -39,11 +39,21 @@ mkimage { args = "-n rk3399 -T rkspi"; + multiple-data-files; +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + }; +#endif u-boot-spl { }; }; - u-boot-img { - offset = <0x40000>; + fit { + type = "blob"; + filename = "u-boot.itb"; + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; }; u-boot { offset = <0x300000>; diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi new file mode 100644 index 00000000000..b66e5015d60 --- /dev/null +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rk356x-u-boot.dtsi" + +&vcc5v0_usb { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +}; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 0a0943b462a..24a976cf7e2 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -87,6 +87,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; diff --git a/arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi new file mode 100644 index 00000000000..b18f958c8a2 --- /dev/null +++ b/arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-nanopc-t6-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi new file mode 100644 index 00000000000..1dc574c2f21 --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +#include "rk3588s-u-boot.dtsi" + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 09d8b311cec..8880d162b11 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -69,6 +69,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_down { bootph-all; }; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi deleted file mode 100644 index cb4e42ede56..00000000000 --- a/arch/arm/dts/rk3xxx.dtsi +++ /dev/null @@ -1,488 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &emac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - spi0 = &spi0; - spi1 = &spi1; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - clock-output-names = "xin24m"; - }; - - gpu: gpu@10090000 { - compatible = "arm,mali-400"; - reg = <0x10090000 0x10000>; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - assigned-clocks = <&cru ACLK_GPU>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_GPU>; - status = "disabled"; - }; - - vpu: video-codec@10104000 { - compatible = "rockchip,rk3066-vpu"; - reg = <0x10104000 0x800>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, - <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; - clock-names = "aclk_vdpu", "hclk_vdpu", - "aclk_vepu", "hclk_vepu"; - }; - - L2: cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - global_timer: global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; - clocks = <&cru CORE_PERI>; - status = "disabled"; - /* The clock source and the sched_clock provided by the arm_global_timer - * on Rockchip rk3066a/rk3188 are quite unstable because their rates - * depend on the CPU frequency. - * Keep the arm_global_timer disabled in order to have the - * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default. - */ - }; - - local_timer: local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; - clocks = <&cru CORE_PERI>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - status = "disabled"; - }; - - qos_gpu: qos@1012d000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_lcdc0: qos@1012f000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f000 0x20>; - }; - - qos_cif0: qos@1012f080 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f080 0x20>; - }; - - qos_ipp: qos@1012f100 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f100 0x20>; - }; - - qos_lcdc1: qos@1012f180 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f180 0x20>; - }; - - qos_cif1: qos@1012f200 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f200 0x20>; - }; - - qos_rga: qos@1012f280 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f280 0x20>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy1>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - emac: ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x3c>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - - rockchip,grf = <&grf>; - - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref"; - max-speed = <100>; - phy-mode = "rmii"; - - status = "disabled"; - }; - - mmc0: mmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - mmc1: mmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x1021c000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 4>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - nfc: nand-controller@10500000 { - compatible = "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_NANDC0>; - clock-names = "ahb"; - status = "disabled"; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = <BOOT_NORMAL>; - mode-recovery = <BOOT_RECOVERY>; - mode-bootloader = <BOOT_FASTBOOT>; - mode-loader = <BOOT_BL_DOWNLOAD>; - }; - }; - - grf: grf@20008000 { - compatible = "syscon", "simple-mfd"; - reg = <0x20008000 0x200>; - }; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@2002d000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - status = "disabled"; - }; - - i2c1: i2c@2002f000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002f000 0x1000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C1>; - clock-names = "i2c"; - - status = "disabled"; - }; - - pwm0: pwm@20030000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030000 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - pwm1: pwm@20030010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030010 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - wdt: watchdog@2004c000 { - compatible = "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - i2c2: i2c@20056000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x20056000 0x1000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C2>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c3: i2c@2005a000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C3>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c4: i2c@2005e000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C4>; - clock-names = "i2c"; - - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - status = "disabled"; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@20070000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x20070000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 10>, <&dmac2 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi1: spi@20074000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x20074000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; -}; diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi new file mode 100644 index 00000000000..fc168317c9e --- /dev/null +++ b/arch/arm/dts/smbios_generic.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Default SMBIOS information for Arm64 platforms + * + * Copyright (c) 2024 Linaro Limited + * Author: Raymond Mao <raymond.mao@linaro.org> + */ +#include <config.h> +#include <smbios_def.h> + +/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + + smbios { + system { + manufacturer = CONFIG_SYS_VENDOR; + product = CONFIG_SYS_BOARD; + version = ""; + serial = ""; + wakeup-type = <SMBIOS_WAKEUP_TYPE_UNKNOWN>; + sku = ""; + family = "armv8"; + }; + + baseboard { + manufacturer = CONFIG_SYS_VENDOR; + product = CONFIG_SYS_BOARD; + version = ""; + serial = ""; + asset-tag = ""; + chassis-location = ""; + feature-flags = <SMBIOS_BOARD_FEAT_HOST_BOARD>; + board-type = <SMBIOS_BOARD_TYPE_MOTHERBOARD>; + }; + + chassis { + manufacturer = CONFIG_SYS_VENDOR; + version = ""; + serial = ""; + asset-tag = ""; + chassis-type = <SMBIOS_ENCLOSURE_DESKTOP>; + bootup-state = <SMBIOS_STATE_SAFE>; + power-supply-state = <SMBIOS_STATE_SAFE>; + thermal-state = <SMBIOS_STATE_SAFE>; + security-status = <SMBIOS_SECURITY_NONE>; + oem-defined = <SMBIOS_ENCLOSURE_OEM_UND>; + height = <SMBIOS_ENCLOSURE_HEIGHT_UND>; + number-of-power-cords = <SMBIOS_POWCORD_NUM_UND>; + }; + + processor { + version = ""; + processor-type = <SMBIOS_PROCESSOR_TYPE_CENTRAL>; + processor-status = <SMBIOS_PROCESSOR_STATUS_ENABLED>; + upgrade = <SMBIOS_PROCESSOR_UPGRADE_NONE>; + family = <SMBIOS_PROCESSOR_FAMILY_EXT>; + family2 = <SMBIOS_PROCESSOR_FAMILY_ARMV8>; + socket-design = ""; + serial = ""; + asset-tag = ""; + part-number = ""; + }; + + cache { + l1-cache { + socket-design = ""; + config = <(SMBIOS_CACHE_LEVEL_1 | + SMBIOS_CACHE_ENABLED | + SMBIOS_CACHE_OP_WB)>; + }; + + l2-cache { + socket-design = ""; + config = <(SMBIOS_CACHE_LEVEL_2 | + SMBIOS_CACHE_ENABLED | + SMBIOS_CACHE_OP_WB)>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 60d1b1acf9a..385fed8a852 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -10,39 +10,44 @@ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { - pss_ref_clk: pss_ref_clk { + pss_ref_clk: pss-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; + clock-output-names = "pss_ref_clk"; }; - video_clk: video_clk { + video_clk: video-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "video_clk"; }; - pss_alt_ref_clk: pss_alt_ref_clk { + pss_alt_ref_clk: pss-alt-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; + clock-output-names = "pss_alt_ref_clk"; }; - gt_crx_ref_clk: gt_crx_ref_clk { + gt_crx_ref_clk: gt-crx-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; + clock-output-names = "gt_crx_ref_clk"; }; - aux_ref_clk: aux_ref_clk { + aux_ref_clk: aux-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "aux_ref_clk"; }; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 4e0587fd441..6e2d9542012 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -494,6 +494,7 @@ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; + label = "eeprom_cc"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ @@ -509,6 +510,7 @@ /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; + label = "eeprom_ebm"; reg = <0x52>; }; }; @@ -520,6 +522,7 @@ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; + label = "eeprom_fmc1"; reg = <0x50>; }; }; @@ -531,6 +534,7 @@ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; + label = "eeprom_fmc2"; reg = <0x50>; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index c4f70581695..6f5856017bf 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -175,6 +175,7 @@ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; + label = "eeprom_cc"; reg = <0x54>; /* & 0x5c */ bootph-all; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 620f5185cc4..70acd3eb88b 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -90,20 +90,6 @@ }; }; - ams { - compatible = "iio-hwmon"; - io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, - <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, - <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, - <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, - <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, - <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, - <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, - <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, - <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, - <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; - }; - pwm-fan { compatible = "pwm-fan"; status = "okay"; @@ -111,6 +97,10 @@ }; }; +&ams { + status = "okay"; +}; + &modepin_gpio { label = "modepin"; }; @@ -369,10 +359,6 @@ "", "", "", ""; /* 170 - 173 */ }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index c9051360931..3542844e697 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -593,10 +593,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index dd63d22f45e..955810ae717 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -1065,10 +1065,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 31effbf27a8..64d822255ec 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -527,10 +527,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 999b2431bdf..3e883d717c2 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -539,10 +539,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 70ca5e6379f..0e0436ecce8 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -18,6 +18,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "xlnx,zynqmp"; @@ -36,6 +37,7 @@ #size-cells = <0>; cpu0: cpu@0 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -46,6 +48,7 @@ }; cpu1: cpu@1 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -56,6 +59,7 @@ }; cpu2: cpu@2 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -66,6 +70,7 @@ }; cpu3: cpu@3 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -388,6 +393,102 @@ }; }; + ams: ams { + compatible = "iio-hwmon"; + status = "disabled"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, + <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, + <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, + <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, + <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, + <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, + <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; + }; + + + tsens_apu: thermal-sensor-apu { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&xilinx_ams 7>; + io-channel-names = "sensor-channel"; + }; + + tsens_rpu: thermal-sensor-rpu { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&xilinx_ams 8>; + io-channel-names = "sensor-channel"; + }; + + tsens_pl: thermal-sensor-pl { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&xilinx_ams 20>; + io-channel-names = "sensor-channel"; + }; + + thermal-zones { + apu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tsens_apu>; + + trips { + apu_passive: passive { + temperature = <93000>; + hysteresis = <3500>; + type = "passive"; + }; + + apu_critical: critical { + temperature = <96500>; + hysteresis = <3500>; + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&apu_passive>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + rpu-thermal { + polling-delay = <10000>; + thermal-sensors = <&tsens_rpu>; + + trips { + critical { + temperature = <96500>; + hysteresis = <3500>; + type = "critical"; + }; + }; + }; + + pl-thermal { + polling-delay = <10000>; + thermal-sensors = <&tsens_pl>; + + trips { + critical { + temperature = <96500>; + hysteresis = <3500>; + type = "critical"; + }; + }; + }; + }; + amba: axi { compatible = "simple-bus"; bootph-all; @@ -1153,7 +1254,6 @@ xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; - status = "disabled"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xffa50000 0x0 0x800>; diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index dad484813fa..afce8a44af3 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -346,7 +346,7 @@ enum { ACLK_VOP_LOW_ROOT_SEL_100M, ACLK_VOP_LOW_ROOT_SEL_24M, ACLK_VOP_ROOT_SEL_SHIFT = 5, - ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT, + ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, ACLK_VOP_ROOT_SEL_GPLL = 0, ACLK_VOP_ROOT_SEL_CPLL, ACLK_VOP_ROOT_SEL_AUPLL, diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..4dbb589aab8 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,13 @@ * Copyright 2018 NXP */ -#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A57 0xD07 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_CORTEX_A76 0xD0B +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) static inline unsigned int read_midr(void) { @@ -18,9 +20,17 @@ static inline unsigned int read_midr(void) return val; } -#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) -#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) -#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) +#define is_cortex_a(__n) \ + static inline int is_cortex_a##__n(void) \ + { \ + unsigned int midr = read_midr(); \ + midr &= MIDR_PARTNUM_MASK; \ + midr >>= MIDR_PARTNUM_SHIFT; \ + return midr == MIDR_PARTNUM_CORTEX_A##__n; \ + } + +is_cortex_a(35) +is_cortex_a(53) +is_cortex_a(57) +is_cortex_a(72) +is_cortex_a(76) diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 5c0d3ee6869..78153c97a58 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -171,6 +171,25 @@ void board_init_f(ulong dummy) debug("am62a_init: %s done\n", __func__); } +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_EMMC: + return MMCSD_MODE_EMMCBOOT; + case BOOT_DEVICE_MMC: + if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) + return MMCSD_MODE_RAW; + default: + return MMCSD_MODE_FS; + } +} + u32 spl_boot_device(void) { return get_boot_device(); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 269c219a6f8..4d3157b2edd 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -48,6 +48,7 @@ config ROCKCHIP_RK3066 select TPL select TPL_ROCKCHIP_BACK_TO_BROM select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SERIAL @@ -84,6 +85,7 @@ config ROCKCHIP_RK3188 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM select SPL_ROCKCHIP_BACK_TO_BROM select BOARD_LATE_INIT + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD help diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 69a5614b449..e563bf455e6 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -75,7 +75,7 @@ config TARGET_FENNEC_RK3288 config TARGET_FIREFLY_RK3288 bool "Firefly-RK3288" select BOARD_LATE_INIT - select SPL_BOARD_INIT if SPL + select ROCKCHIP_COMMON_STACK_ADDR select TPL help Firefly is a RK3288-based development board with 2 USB ports, @@ -86,6 +86,8 @@ config TARGET_FIREFLY_RK3288 config TARGET_MIQI_RK3288 bool "MiQi-RK3288" select BOARD_LATE_INIT + select ROCKCHIP_COMMON_STACK_ADDR + select TPL help MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0 ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It @@ -132,6 +134,7 @@ config TARGET_ROCK2 config TARGET_TINKER_RK3288 bool "Tinker-RK3288" select BOARD_LATE_INIT + select ROCKCHIP_COMMON_STACK_ADDR select TPL help Tinker is a RK3288-based development board with 2 USB ports, HDMI, @@ -160,7 +163,7 @@ config SYS_SOC default "rk3288" config SYS_MALLOC_F_LEN - default 0x2000 + default 0x2000 if !SPL_SHARES_INIT_SP_ADDR config SPL_DRIVERS_MISC default y @@ -177,6 +180,9 @@ config SPL_SERIAL config TPL_STACK default 0xff718000 +config TPL_SYS_MALLOC_F_LEN + default 0x2000 + config TPL_TEXT_BASE default 0xff704000 diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index c6b1a35f47e..03d97e1d746 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -216,3 +216,19 @@ int arch_cpu_init(void) return 0; } #endif + +#define RK3308_GRF_CHIP_ID 0xFF000800 + +int checkboard(void) +{ + u32 chip_id = readl(RK3308_GRF_CHIP_ID); + + if (chip_id == 0x3308) + printf("SoC: RK3308B\n"); + else if (chip_id == 0x3308c) + printf("SoC: RK3308B-S\n"); + else + printf("SoC: RK3308\n"); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 04a84e2f6a0..500cfcd87af 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -146,15 +146,6 @@ config SYS_SOC config ROCKCHIP_COMMON_STACK_ADDR default y -config SYS_MALLOC_F_LEN - default 0x4000 if !SPL_SHARES_INIT_SP_ADDR - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" @@ -164,9 +155,6 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000 -config SPL_STACK_R_ADDR - default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR - if BOOTCOUNT_LIMIT config BOOTCOUNT_BOOTLIMIT diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 0c28241c603..1ce43c6f0d4 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -7,7 +7,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <spl_gpio.h> #include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -16,6 +15,7 @@ #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/gpio.h> #include <linux/bitops.h> #include <linux/printk.h> #include <power/regulator.h> @@ -133,27 +133,6 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - - if (IS_ENABLED(CONFIG_XPL_BUILD) && - (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || - IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { - rk_setreg(&grf->io_vsel, 1 << 0); - - /* - * Let's enable these power rails here, we are already running - * the SPI-Flash-based code. - */ - spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), - GPIO_PULL_NORMAL); - - spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), - GPIO_PULL_NORMAL); - } - /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index c9a32287e92..c2b96902d2d 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -3,7 +3,10 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + #include <dm.h> +#include <misc.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3568.h> @@ -139,3 +142,61 @@ int arch_cpu_init(void) #endif return 0; } + +#define RK3568_OTP_CPU_CODE_OFFSET 0x02 +#define RK3568_OTP_SPECIFICATION_OFFSET 0x07 +#define RK3568_OTP_PERFORMANCE_OFFSET 0x22 + +int checkboard(void) +{ + u8 cpu_code[2], specification, package, performance; + struct udevice *dev; + char suffix[3]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x66 or 0x35 0x68 */ + ret = misc_read(dev, RK3568_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0x2 for RK3568B2 and 0xA for RK3568J */ + ret = misc_read(dev, RK3568_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + /* package: likely SoC variant revision, 0x2 for RK3568B2 */ + package = specification >> 5; + specification &= 0x1f; + + /* performance: used to identify RK3566T SoC variant */ + ret = misc_read(dev, RK3568_OTP_PERFORMANCE_OFFSET, &performance, 1); + if (ret < 0) { + log_debug("Could not read performance, ret=%d\n", ret); + return 0; + } + if (performance & 0x0f) + specification = 0x14; /* T-variant */ + + /* for RK3568J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + /* for RK3568B2 i.e. '0' + 0x2 = '2' */ + suffix[1] = package > 1 ? '0' + package : '\0'; + suffix[2] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index b5a0e624a53..155b8f00ca2 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -74,6 +74,28 @@ config TARGET_JAGUAR_RK3588 - fan controller (AMC6821 emulation) * 80-pin Mezzanine connector +config TARGET_KHADAS_EDGE2_RK3588 + bool "Khadas Edge2 RK3588 board" + select BOARD_LATE_INIT + help + Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer) + by Khadas. + + There are tree variants depending on the DRAM size : 8G and 16G. + + Specification: + + Rockchip RK3588S SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MP4 GPU + 3x MIPI CSI 4x lanes + 2x MIPI-DSI DPHY 4x lanes + 32/64GB eMMC + 1x USB 2.0, 1x USB 3.0, 2x USB-Type-C + 1x HDMI 2.1 output, 1x DP 1.4 output + USB PD over USB Type-C + config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" select BOARD_LATE_INIT @@ -260,6 +282,26 @@ config TARGET_ROCK_5_ITX_RK3588 Front-panel connectors for audio and case-power, -leds Powered by either 12V, ATX power-supply or PoE +config TARGET_ROCK_5C_RK3588S + bool "Radxa ROCK 5C RK3588S2 board" + select BOARD_LATE_INIT + help + Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer. + + Specification: + + Quad A76 and Quad A55 CPU + 6 TOPS NPU + up to 32GB LPDDR4x RAM + eMMC / SPI flash connector + Micro SD Card slot + Gigabit ethernet port (supports PoE with add-on PoE HAT) + WiFi6 / BT5.4 + 1x USB 3.0 Type-A HOST port + 1x USB 3.0 Type-A OTG port + 2x USB 2.0 Type-A HOST port + 1x USB Type-C 5V power port + config TARGET_SIGE7_RK3588 bool "ArmSoM Sige7 RK3588 board" select BOARD_LATE_INIT @@ -393,11 +435,13 @@ source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" +source "board/khadas/khadas-edge2-rk3588s/Kconfig" source "board/pine64/quartzpro64-rk3588/Kconfig" source "board/turing/turing-rk1-rk3588/Kconfig" source "board/radxa/rock5a-rk3588s/Kconfig" source "board/radxa/rock5b-rk3588/Kconfig" source "board/radxa/rock-5-itx-rk3588/Kconfig" +source "board/radxa/rock-5c-rk3588s/Kconfig" source "board/rockchip/evb_rk3588/Kconfig" source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2dac2a5b80..c1dce3ee370 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -4,6 +4,10 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <misc.h> #include <spl.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -178,3 +182,51 @@ int arch_cpu_init(void) return 0; } #endif + +#define RK3588_OTP_CPU_CODE_OFFSET 0x02 +#define RK3588_OTP_SPECIFICATION_OFFSET 0x06 + +int checkboard(void) +{ + u8 cpu_code[2], specification, package; + struct udevice *dev; + char suffix[3]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */ + ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3588J and 0x13 for RK3588S */ + ret = misc_read(dev, RK3588_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + /* package: likely SoC variant revision, 0x2 for RK3588S2 */ + package = specification >> 5; + specification &= 0x1f; + + /* for RK3588J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + /* for RK3588S2 i.e. '0' + 0x2 = '2' */ + suffix[1] = package > 1 ? '0' + package : '\0'; + suffix[2] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 8ee25e4c316..3aa218545bb 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -349,7 +349,7 @@ static int do_zynqmp_reboot(struct cmd_tbl *cmdtp, int flag, multiboot = hextoul(argv[2], NULL); - ret = zynqmp_mmio_write(0xFFCA0010, 0xfff, multiboot); + ret = zynqmp_mmio_write((ulong)&csu_base->multi_boot, 0xfff, multiboot); if (ret != 0) { printf("Failed: mmio write\n"); return ret; diff --git a/board/firefly/firefly-rk3288/MAINTAINERS b/board/firefly/firefly-rk3288/MAINTAINERS index 42db0bd5e1f..174027e770b 100644 --- a/board/firefly/firefly-rk3288/MAINTAINERS +++ b/board/firefly/firefly-rk3288/MAINTAINERS @@ -1,6 +1,7 @@ FIREFLY M: Simon Glass <sjg@chromium.org> S: Maintained +F: arch/arm/dts/rk3288-firefly-u-boot.dtsi F: board/firefly/firefly-rk3288 F: include/configs/firefly-rk3288.h F: configs/firefly-rk3288_defconfig diff --git a/board/firefly/firefly-rk3288/Makefile b/board/firefly/firefly-rk3288/Makefile deleted file mode 100644 index 671684597d2..00000000000 --- a/board/firefly/firefly-rk3288/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2015 Google, Inc -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += firefly-rk3288.o diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c deleted file mode 100644 index c65ce5890e5..00000000000 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <hang.h> -#include <led.h> -#include <log.h> -#include <asm/global_data.h> -#include <dm/ofnode.h> - -#ifdef CONFIG_XPL_BUILD -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = ofnode_conf_read_str("u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_state(dev, LEDST_ON); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } -} -#endif diff --git a/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS index 63ff6fafc8d..27853188e59 100644 --- a/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS +++ b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS @@ -5,5 +5,4 @@ S: Maintained F: board/friendlyelec/nanopc-t6-rk3588 F: include/configs/nanopc-t6-rk3588.h F: configs/nanopc-t6-rk3588_defconfig -F: arch/arm/dts/rk3588-nanopc-t6.dts -F: arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi +F: arch/arm/dts/rk3588-nanopc-t6* diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 8b635ef71ac..d2c5aaacf66 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -6,6 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ +#include <asm/armv8/cpu.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/processor.h> @@ -66,12 +67,7 @@ int board_init(void) void reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); else writel(RST_CA57_CODE, RST_CA57RESCNT); diff --git a/board/khadas/khadas-edge2-rk3588s/Kconfig b/board/khadas/khadas-edge2-rk3588s/Kconfig new file mode 100644 index 00000000000..dd7b6cd8054 --- /dev/null +++ b/board/khadas/khadas-edge2-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KHADAS_EDGE2_RK3588 + +config SYS_BOARD + default "khadas-edge2-rk3588s" + +config SYS_VENDOR + default "khadas" + +config SYS_CONFIG_NAME + default "khadas-edge2-rk3588s" + +endif diff --git a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..3f16923b0f2 --- /dev/null +++ b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS @@ -0,0 +1,6 @@ +KHADAS-EDGE2-RK3588S +M: Jacobe Zang <jacobe.zang@wesion.com> +S: Maintained +F: configs/khadas-edge2-rk3588s_defconfig +F: include/configs/khadas-edge2-rk3588s.h +F: dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
\ No newline at end of file diff --git a/board/mqmaker/miqi_rk3288/MAINTAINERS b/board/mqmaker/miqi_rk3288/MAINTAINERS index 1cb5f790fe7..d7e55b02fe3 100644 --- a/board/mqmaker/miqi_rk3288/MAINTAINERS +++ b/board/mqmaker/miqi_rk3288/MAINTAINERS @@ -1,7 +1,6 @@ MIQI M: Jernej Skrabec <jernej.skrabec@siol.net> S: Maintained -F: arch/arm/dts/rk3288-miqi.dts F: arch/arm/dts/rk3288-miqi-u-boot.dtsi F: board/mqmaker/miqi_rk3288 F: include/configs/miqi_rk3288.h diff --git a/board/radxa/rock-5c-rk3588s/Kconfig b/board/radxa/rock-5c-rk3588s/Kconfig new file mode 100644 index 00000000000..ec964bdcb93 --- /dev/null +++ b/board/radxa/rock-5c-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROCK_5C_RK3588S + +config SYS_BOARD + default "rock-5c-rk3588s" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock-5c-rk3588s" + +endif diff --git a/board/radxa/rock-5c-rk3588s/MAINTAINERS b/board/radxa/rock-5c-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..17183c739d6 --- /dev/null +++ b/board/radxa/rock-5c-rk3588s/MAINTAINERS @@ -0,0 +1,7 @@ +ROCK-5C-RK3588S +M: FUKAUMI Naoki <naoki@radxa.com> +S: Maintained +F: arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi +F: board/radxa/rock-5c-rk3588s/ +F: configs/rock-5c-rk3588s_defconfig +F: include/configs/rock-5c-rk3588s.h diff --git a/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c index fd827467b30..856b434df36 100644 --- a/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c +++ b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c @@ -52,6 +52,8 @@ void rockchip_capsule_update_board_setup(void) fw_images[0].fw_name = u"ROCKPI4C-IDBLOADER"; fw_images[1].fw_name = u"ROCKPI4C-UBOOT"; + } else { + update_info.num_images = 0; } } #endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */ diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/rcar-common/gen3-common.c index 4291e1d5bcb..004feca6180 100644 --- a/board/renesas/rcar-common/gen3-common.c +++ b/board/renesas/rcar-common/gen3-common.c @@ -7,6 +7,7 @@ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ +#include <asm/armv8/cpu.h> #include <dm.h> #include <fdt_support.h> #include <hang.h> @@ -50,14 +51,9 @@ int fdtdec_board_setup(const void *fdt_blob) void __weak reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) + else if (is_cortex_a57()) writel(RST_CA57_CODE, RST_CA57RESCNT); else hang(); diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 588134ecb27..b2780401a39 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -28,6 +28,13 @@ F: configs/lubancat-2-rk3568_defconfig F: arch/arm/dts/rk3568-lubancat-2.dts F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +NANOPI-R3S +M: Tianling Shen <cnsztl@gmail.com> +R: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/nanopi-r3s-rk3566_defconfig +F: arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi + NANOPI-R5C M: Tianling Shen <cnsztl@gmail.com> R: Jonas Karlman <jonas@kwiboo.se> diff --git a/board/rockchip/tinker_rk3288/MAINTAINERS b/board/rockchip/tinker_rk3288/MAINTAINERS index 3869d5dc853..ab1ce72a77b 100644 --- a/board/rockchip/tinker_rk3288/MAINTAINERS +++ b/board/rockchip/tinker_rk3288/MAINTAINERS @@ -1,10 +1,7 @@ TINKER-RK3288 M: Lin Huang <hl@rock-chips.com> +R: Jonas Karlman <jonas@kwiboo.se> S: Maintained -F: arch/arm/dts/rk3288-tinker.dts -F: arch/arm/dts/rk3288-tinker.dtsi -F: arch/arm/dts/rk3288-tinker-s.dts -F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi F: arch/arm/dts/rk3288-tinker-u-boot.dtsi F: board/rockchip/tinker_rk3288 F: include/configs/tinker_rk3288.h @@ -12,7 +9,9 @@ F: configs/tinker-rk3288_defconfig TINKER-S-RK3288 M: Michael Trimarchi <michael@amarulasolutions.com> +R: Jonas Karlman <jonas@kwiboo.se> S: Maintained +F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi F: board/rockchip/tinker_rk3288 F: include/configs/tinker_rk3288.h F: configs/tinker-s-rk3288_defconfig diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index e966e9f201a..dfd553d1aa5 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -22,7 +22,7 @@ static int get_ethaddr_from_eeprom(u8 *addr) return i2c_eeprom_read(dev, 0, addr, 6); } -int rk3288_board_late_init(void) +int rockchip_early_misc_init_r(void) { u8 ethaddr[6]; diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index fd5c6ced795..b4483d00ad1 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -6,6 +6,7 @@ #include <command.h> #include <cpu_func.h> +#include <dfu.h> #include <env.h> #include <fdtdec.h> #include <init.h> @@ -14,6 +15,7 @@ #include <malloc.h> #include <memalign.h> #include <mmc.h> +#include <mtd.h> #include <time.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -35,9 +37,36 @@ static xilinx_desc versalpl = { }; #endif +static u8 versal_get_bootmode(void) +{ + u8 bootmode; + u32 reg = 0; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + +static u32 versal_multi_boot(void) +{ + u8 bootmode = versal_get_bootmode(); + + /* Mostly workaround for QEMU CI pipeline */ + if (bootmode == JTAG_MODE) + return 0; + + return readl(0xF1110004); +} + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); + printf("Multiboot:\t%d\n", versal_multi_boot()); #if defined(CONFIG_FPGA_VERSALPL) fpga_init(); @@ -113,21 +142,6 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, return ret; } -static u8 versal_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - reg = readl(&crp_base->boot_mode_usr); - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static int boot_targets_setup(void) { u8 bootmode; @@ -346,9 +360,35 @@ enum env_location env_get_location(enum env_operation op, int prio) #define DFU_ALT_BUF_LEN SZ_1K +static void mtd_found_part(u32 *base, u32 *size) +{ + struct mtd_info *part, *mtd; + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (!IS_ERR_OR_NULL(mtd)) { + list_for_each_entry(part, &mtd->partitions, node) { + debug("0x%012llx-0x%012llx : \"%s\"\n", + part->offset, part->offset + part->size, + part->name); + + if (*base >= part->offset && + *base < part->offset + part->size) { + debug("Found my partition: %d/%s\n", + part->index, part->name); + *base = part->offset; + *size = part->size; + break; + } + } + } +} + void set_dfu_alt_info(char *interface, char *devstr) { int bootseq = 0, len = 0; + u32 multiboot = versal_multi_boot(); u32 bootmode = versal_get_bootmode(); ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); @@ -358,6 +398,8 @@ void set_dfu_alt_info(char *interface, char *devstr) memset(buf, 0, sizeof(buf)); + multiboot = env_get_hex("multiboot", multiboot); + switch (bootmode) { case EMMC_MODE: case SD_MODE: @@ -368,9 +410,28 @@ void set_dfu_alt_info(char *interface, char *devstr) len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", bootseq); + if (multiboot) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "%04d", multiboot); + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", bootseq); break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + case OSPI_MODE: + { + u32 base = multiboot * SZ_32K; + u32 size = 0x1500000; + u32 limit = size; + + mtd_found_part(&base, &limit); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw 0x%x 0x%x", + base, limit); + } + break; default: return; } diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c index e5598807e8c..f8d7c8466f6 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c @@ -465,7 +465,7 @@ static unsigned long psu_peripherals_pre_init_data(void) static unsigned long psu_peripherals_init_data(void) { - psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index ff3a0924de7..b0c2ac6f2e8 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -62,14 +62,8 @@ bootmenu_0=eMMC Boot=run som_mmc_boot bootmenu_1=SD Boot=run som_cc_boot bootmenu_delay=5 -usb_hub_init=mw 1000 0056 && sleep 1 && i2c write 1000 2d aa 2 -s - -# usb hub init -kv260_setup=i2c dev 1 && run usb_hub_init -# usb hub init -kr260_setup=i2c dev 1 && run usb_hub_init; i2c dev 2 && run usb_hub_init; -# usb hub init with enabling PM nodes for ... -kd240_setup=i2c dev 1 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw node 47 +# Enabling PM nodes for uart0 and can0 +kd240_setup=zynqmp pmufw node 33; zynqmp pmufw node 47 tpm_setup=tpm autostart; tpm_reset=echo "!!! For TPM reset a full power cycle or pressing the POR_B button is required !!!"; @@ -79,7 +73,7 @@ tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi board_setup=\ rtc dev 0; \ zynqmp mmio_write 0xFFCA0010 0xfff 0; \ -if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\ -if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\ +if test ${card1_name} = SCK-KV-G; then run tpm_kv260; fi;\ +if test ${card1_name} = SCK-KR-G; then run tpm_reset; fi;\ if test ${card1_name} = SCK-KD-G; then run kd240_setup; run tpm_kd240; fi;\ run tpm_setup diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 2392027d40b..49efeec3681 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -321,7 +321,7 @@ int fdt_kaslrseed(void *fdt, bool overwrite) * board_fdt_chosen_bootargs - boards may override this function to use * alternative kernel command line arguments */ -__weak char *board_fdt_chosen_bootargs(void) +__weak const char *board_fdt_chosen_bootargs(const struct fdt_property *fdt_ba) { return env_get("bootargs"); } @@ -331,7 +331,7 @@ int fdt_chosen(void *fdt) struct abuf buf = {}; int nodeoffset; int err; - char *str; /* used to set string properties */ + const char *str; /* used to set string properties */ err = fdt_check_header(fdt); if (err < 0) { @@ -364,7 +364,8 @@ int fdt_chosen(void *fdt) } } - str = board_fdt_chosen_bootargs(); + str = board_fdt_chosen_bootargs(fdt_get_property(fdt, nodeoffset, + "bootargs", NULL)); if (str) { err = fdt_setprop(fdt, nodeoffset, "bootargs", str, diff --git a/cmd/Kconfig b/cmd/Kconfig index 93efeaec6f4..4c4ad9d9979 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1453,6 +1453,12 @@ config CMD_OPTEE_RPMB in the Replay Protection Memory Block partition in eMMC by using Persistent Objects in OPTEE +config CMD_OPTEE + bool "Enable OP-TEE commands" + depends on OPTEE + help + OP-TEE commands support. + config CMD_MTD bool "mtd" depends on MTD diff --git a/cmd/Makefile b/cmd/Makefile index 1e6d3128c8c..bf322201c64 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -119,6 +119,7 @@ obj-$(CONFIG_CMD_PAUSE) += pause.o obj-$(CONFIG_CMD_SLEEP) += sleep.o obj-$(CONFIG_CMD_MMC) += mmc.o obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o +obj-$(CONFIG_CMD_OPTEE) += optee.o obj-$(CONFIG_CMD_MP) += mp.o obj-$(CONFIG_CMD_MTD) += mtd.o obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o diff --git a/cmd/optee.c b/cmd/optee.c new file mode 100644 index 00000000000..d0d37293986 --- /dev/null +++ b/cmd/optee.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2024, Advanced Micro Devices, Inc. + */ +#include <command.h> +#include <errno.h> +#include <tee.h> +#include <vsprintf.h> + +#define TA_HELLO_WORLD_CMD_INC_VALUE 0 +/* This needs to match the UUID of the Hello World TA. */ +#define TA_HELLO_WORLD_UUID \ + { 0x8aaaf200, 0x2450, 0x11e4, \ + { 0xab, 0xe2, 0x00, 0x02, 0xa5, 0xd5, 0xc5, 0x1b} } + +static int hello_world_ta(unsigned int value) +{ + const struct tee_optee_ta_uuid uuid = TA_HELLO_WORLD_UUID; + struct tee_open_session_arg session_arg; + struct udevice *tee = NULL; + struct tee_invoke_arg arg; + struct tee_param param[2]; + int rc; + + tee = tee_find_device(tee, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&session_arg, 0, sizeof(session_arg)); + tee_optee_ta_uuid_to_octets(session_arg.uuid, &uuid); + rc = tee_open_session(tee, &session_arg, 0, NULL); + if (rc) { + printf("tee_open_session(): failed(%d)\n", rc); + return rc; + } + + arg.func = TA_HELLO_WORLD_CMD_INC_VALUE; + arg.session = session_arg.session; + + param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT; + param[0].u.value.a = value; + + printf("Value before: 0x%x\n", (int)param[0].u.value.a); + printf("Calling TA\n"); + tee_invoke_func(tee, &arg, 1, param); + + printf("Value after: 0x%x\n", (int)param[0].u.value.a); + return tee_close_session(tee, session_arg.session); +} + +static int do_optee_hello_world_ta(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret, value = 0; + + if (strcmp(argv[1], NULL)) + value = hextoul(argv[1], NULL); + + ret = hello_world_ta(value); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_LONGHELP(optee, + "hello [<value>] Invoke the OP-TEE 'Hello World' TA\n"); + +U_BOOT_CMD_WITH_SUBCMDS(optee, "OP-TEE commands", optee_help_text, + U_BOOT_SUBCMD_MKENT(hello, 2, 1, do_optee_hello_world_ta)); diff --git a/cmd/smbios.c b/cmd/smbios.c index d3bd8b12a67..562dd7959be 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -14,16 +14,109 @@ DECLARE_GLOBAL_DATA_PTR; -static const char * const wakeup_type_strings[] = { - "Reserved", /* 0x00 */ - "Other", /* 0x01 */ - "Unknown", /* 0x02 */ - "APM Timer", /* 0x03 */ - "Modem Ring", /* 0x04 */ - "Lan Remote", /* 0x05 */ - "Power Switch", /* 0x06 */ - "PCI PME#", /* 0x07 */ - "AC Power Restored", /* 0x08 */ +static const struct str_lookup_table wakeup_type_strings[] = { + { SMBIOS_WAKEUP_TYPE_RESERVED, "Reserved" }, + { SMBIOS_WAKEUP_TYPE_OTHER, "Other" }, + { SMBIOS_WAKEUP_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_WAKEUP_TYPE_APM_TIMER, "APM Timer" }, + { SMBIOS_WAKEUP_TYPE_MODEM_RING, "Modem Ring" }, + { SMBIOS_WAKEUP_TYPE_LAN_REMOTE, "Lan Remote" }, + { SMBIOS_WAKEUP_TYPE_POWER_SWITCH, "Power Switch" }, + { SMBIOS_WAKEUP_TYPE_PCI_PME, "PCI PME#" }, + { SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED, "AC Power Restored" }, +}; + +static const struct str_lookup_table boardtype_strings[] = { + { SMBIOS_BOARD_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_BOARD_TYPE_OTHER, "Other" }, + { SMBIOS_BOARD_TYPE_SERVER_BLADE, "Server Blade" }, + { SMBIOS_BOARD_TYPE_CON_SWITCH, "Connectivity Switch" }, + { SMBIOS_BOARD_TYPE_SM_MODULE, "System Management Module" }, + { SMBIOS_BOARD_TYPE_PROCESSOR_MODULE, "Processor Module" }, + { SMBIOS_BOARD_TYPE_IO_MODULE, "I/O Module" }, + { SMBIOS_BOARD_TYPE_MEM_MODULE, "Memory Module" }, + { SMBIOS_BOARD_TYPE_DAUGHTER_BOARD, "Daughter board" }, + { SMBIOS_BOARD_TYPE_MOTHERBOARD, "Motherboard" }, + { SMBIOS_BOARD_TYPE_PROC_MEM_MODULE, "Processor/Memory Module" }, + { SMBIOS_BOARD_TYPE_PROC_IO_MODULE, "Processor/IO Module" }, + { SMBIOS_BOARD_TYPE_INTERCON, "Interconnect board" }, +}; + +static const struct str_lookup_table chassis_state_strings[] = { + { SMBIOS_STATE_OTHER, "Other" }, + { SMBIOS_STATE_UNKNOWN, "Unknown" }, + { SMBIOS_STATE_SAFE, "Safe" }, + { SMBIOS_STATE_WARNING, "Warning" }, + { SMBIOS_STATE_CRITICAL, "Critical" }, + { SMBIOS_STATE_NONRECOVERABLE, "Non-recoverable" }, +}; + +static const struct str_lookup_table chassis_security_strings[] = { + { SMBIOS_SECURITY_OTHER, "Other" }, + { SMBIOS_SECURITY_UNKNOWN, "Unknown" }, + { SMBIOS_SECURITY_NONE, "None" }, + { SMBIOS_SECURITY_EXTINT_LOCK, "External interface locked out" }, + { SMBIOS_SECURITY_EXTINT_EN, "External interface enabled" }, +}; + +static const struct str_lookup_table processor_type_strings[] = { + { SMBIOS_PROCESSOR_TYPE_OTHER, "Other" }, + { SMBIOS_PROCESSOR_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_PROCESSOR_TYPE_CENTRAL, "Central Processor" }, + { SMBIOS_PROCESSOR_TYPE_MATH, "Math Processor" }, + { SMBIOS_PROCESSOR_TYPE_DSP, "DSP Processor" }, + { SMBIOS_PROCESSOR_TYPE_VIDEO, "Video Processor" }, +}; + +static const struct str_lookup_table processor_family_strings[] = { + { SMBIOS_PROCESSOR_FAMILY_OTHER, "Other" }, + { SMBIOS_PROCESSOR_FAMILY_UNKNOWN, "Unknown" }, + { SMBIOS_PROCESSOR_FAMILY_RSVD, "Reserved" }, + { SMBIOS_PROCESSOR_FAMILY_ARMV7, "ARMv7" }, + { SMBIOS_PROCESSOR_FAMILY_ARMV8, "ARMv8" }, + { SMBIOS_PROCESSOR_FAMILY_RV32, "RISC-V RV32" }, + { SMBIOS_PROCESSOR_FAMILY_RV64, "RISC-V RV64" }, +}; + +static const struct str_lookup_table processor_upgrade_strings[] = { + { SMBIOS_PROCESSOR_UPGRADE_OTHER, "Other" }, + { SMBIOS_PROCESSOR_UPGRADE_UNKNOWN, "Unknown" }, + { SMBIOS_PROCESSOR_UPGRADE_NONE, "None" }, +}; + +static const struct str_lookup_table err_corr_type_strings[] = { + { SMBIOS_CACHE_ERRCORR_OTHER, "Other" }, + { SMBIOS_CACHE_ERRCORR_UNKNOWN, "Unknown" }, + { SMBIOS_CACHE_ERRCORR_NONE, "None" }, + { SMBIOS_CACHE_ERRCORR_PARITY, "Parity" }, + { SMBIOS_CACHE_ERRCORR_SBITECC, "Single-bit ECC" }, + { SMBIOS_CACHE_ERRCORR_MBITECC, "Multi-bit ECC" }, +}; + +static const struct str_lookup_table sys_cache_type_strings[] = { + { SMBIOS_CACHE_SYSCACHE_TYPE_OTHER, "Other" }, + { SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_CACHE_SYSCACHE_TYPE_INST, "Instruction" }, + { SMBIOS_CACHE_SYSCACHE_TYPE_DATA, "Data" }, + { SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED, "Unified" }, +}; + +static const struct str_lookup_table associativity_strings[] = { + { SMBIOS_CACHE_ASSOC_OTHER, "Other" }, + { SMBIOS_CACHE_ASSOC_UNKNOWN, "Unknown" }, + { SMBIOS_CACHE_ASSOC_DMAPPED, "Direct Mapped" }, + { SMBIOS_CACHE_ASSOC_2WAY, "2-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_4WAY, "4-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_FULLY, "Fully Associative" }, + { SMBIOS_CACHE_ASSOC_8WAY, "8-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_16WAY, "16-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_12WAY, "12-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_24WAY, "24-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_32WAY, "32-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_48WAY, "48-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_64WAY, "64-way Set-Associative" }, + { SMBIOS_CACHE_ASSOC_20WAY, "20-way Set-Associative" }, + }; /** @@ -37,7 +130,7 @@ static const char *smbios_get_string(void *table, int index) { const char *str = (char *)table + ((struct smbios_header *)table)->length; - static const char fallback[] = "Not Specified"; + static const char fallback[] = ""; if (!index) return fallback; @@ -79,17 +172,53 @@ static void smbios_print_generic(struct smbios_header *table) } } -void smbios_print_str(const char *label, void *table, u8 index) +static void smbios_print_str(const char *label, void *table, u8 index) { printf("\t%s: %s\n", label, smbios_get_string(table, index)); } -const char *smbios_wakeup_type_str(u8 wakeup_type) +static void smbios_print_lookup_str(const struct str_lookup_table *table, + u16 index, u16 array_size, + const char *prefix) +{ + int i; + const char *str = NULL; + + for (i = 0; i < array_size; i++) { + if ((table + i)->idx == index) + str = (table + i)->str; + } + + if (str) + printf("\t%s: %s\n", prefix, str); + else + printf("\t%s: [%04x]\n", prefix, index); +} + +static void smbios_print_type0(struct smbios_type0 *table) { - if (wakeup_type >= ARRAY_SIZE(wakeup_type_strings)) - /* Values over 0x08 are reserved. */ - wakeup_type = 0; - return wakeup_type_strings[wakeup_type]; + printf("BIOS Information\n"); + smbios_print_str("Vendor", table, table->vendor); + smbios_print_str("BIOS Version", table, table->bios_ver); + /* Keep table->bios_start_segment as 0 for UEFI-based systems */ + smbios_print_str("BIOS Release Date", table, table->bios_release_date); + printf("\tBIOS ROM Size: 0x%02x\n", table->bios_rom_size); + printf("\tBIOS Characteristics: 0x%016llx\n", + table->bios_characteristics); + printf("\tBIOS Characteristics Extension Byte 1: 0x%02x\n", + table->bios_characteristics_ext1); + printf("\tBIOS Characteristics Extension Byte 2: 0x%02x\n", + table->bios_characteristics_ext2); + printf("\tSystem BIOS Major Release: 0x%02x\n", + table->bios_major_release); + printf("\tSystem BIOS Minor Release: 0x%02x\n", + table->bios_minor_release); + printf("\tEmbedded Controller Firmware Major Release: 0x%02x\n", + table->ec_major_release); + printf("\tEmbedded Controller Firmware Minor Release: 0x%02x\n", + table->ec_minor_release); + printf("\tExtended BIOS ROM Size: 0x%04x\n", + table->extended_bios_rom_size); } static void smbios_print_type1(struct smbios_type1 *table) @@ -99,12 +228,14 @@ static void smbios_print_type1(struct smbios_type1 *table) smbios_print_str("Product Name", table, table->product_name); smbios_print_str("Version", table, table->version); smbios_print_str("Serial Number", table, table->serial_number); - if (table->length >= 0x19) { + if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V21) { printf("\tUUID: %pUl\n", table->uuid); - printf("\tWake-up Type: %s\n", - smbios_wakeup_type_str(table->wakeup_type)); + smbios_print_lookup_str(wakeup_type_strings, + table->wakeup_type, + ARRAY_SIZE(wakeup_type_strings), + "Wake-up Type"); } - if (table->length >= 0x1b) { + if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V24) { smbios_print_str("SKU Number", table, table->sku_number); smbios_print_str("Family", table, table->family); } @@ -112,25 +243,166 @@ static void smbios_print_type1(struct smbios_type1 *table) static void smbios_print_type2(struct smbios_type2 *table) { - u16 *handle; + int i; + u8 *addr = (u8 *)table + offsetof(struct smbios_type2, eos); - printf("Base Board Information\n"); + printf("Baseboard Information\n"); smbios_print_str("Manufacturer", table, table->manufacturer); smbios_print_str("Product Name", table, table->product_name); smbios_print_str("Version", table, table->version); smbios_print_str("Serial Number", table, table->serial_number); smbios_print_str("Asset Tag", table, table->asset_tag_number); - printf("\tFeature Flags: 0x%04x\n", table->feature_flags); + printf("\tFeature Flags: 0x%02x\n", table->feature_flags); smbios_print_str("Chassis Location", table, table->chassis_location); printf("\tChassis Handle: 0x%04x\n", table->chassis_handle); - smbios_print_str("Board Type", table, table->board_type); - printf("\tContained Object Handles: "); - handle = (void *)table->eos; - for (int i = 0; i < table->number_contained_objects; ++i) - printf("0x%04x ", handle[i]); + smbios_print_lookup_str(boardtype_strings, + table->board_type, + ARRAY_SIZE(boardtype_strings), + "Board Type"); + printf("\tNumber of Contained Object Handles: 0x%02x\n", + table->number_contained_objects); + if (!table->number_contained_objects) + return; + + printf("\tContained Object Handles:\n"); + for (i = 0; i < table->number_contained_objects; i++) { + printf("\t\tObject[%03d]:\n", i); + if (CONFIG_IS_ENABLED(HEXDUMP)) + print_hex_dump("\t\t", DUMP_PREFIX_OFFSET, 16, 1, addr, + sizeof(u16), false); + addr += sizeof(u16); + } printf("\n"); } +static void smbios_print_type3(struct smbios_type3 *table) +{ + int i; + u8 *addr = (u8 *)table + offsetof(struct smbios_type3, sku_number); + + printf("Baseboard Information\n"); + smbios_print_str("Manufacturer", table, table->manufacturer); + printf("\tType: 0x%02x\n", table->chassis_type); + smbios_print_str("Version", table, table->version); + smbios_print_str("Serial Number", table, table->serial_number); + smbios_print_str("Asset Tag", table, table->asset_tag_number); + smbios_print_lookup_str(chassis_state_strings, + table->bootup_state, + ARRAY_SIZE(chassis_state_strings), + "Boot-up State"); + smbios_print_lookup_str(chassis_state_strings, + table->power_supply_state, + ARRAY_SIZE(chassis_state_strings), + "Power Supply State"); + smbios_print_lookup_str(chassis_state_strings, + table->thermal_state, + ARRAY_SIZE(chassis_state_strings), + "Thermal State"); + smbios_print_lookup_str(chassis_security_strings, + table->security_status, + ARRAY_SIZE(chassis_security_strings), + "Security Status"); + printf("\tOEM-defined: 0x%08x\n", table->oem_defined); + printf("\tHeight: 0x%02x\n", table->height); + printf("\tNumber of Power Cords: 0x%02x\n", + table->number_of_power_cords); + printf("\tContained Element Count: 0x%02x\n", table->element_count); + printf("\tContained Element Record Length: 0x%02x\n", + table->element_record_length); + if (table->element_count) { + printf("\tContained Elements:\n"); + for (i = 0; i < table->element_count; i++) { + printf("\t\tElement[%03d]:\n", i); + if (CONFIG_IS_ENABLED(HEXDUMP)) + print_hex_dump("\t\t", DUMP_PREFIX_OFFSET, 16, + 1, addr, + table->element_record_length, + false); + printf("\t\tContained Element Type: 0x%02x\n", *addr); + printf("\t\tContained Element Minimum: 0x%02x\n", + *(addr + 1)); + printf("\t\tContained Element Maximum: 0x%02x\n", + *(addr + 2)); + addr += table->element_record_length; + } + } + smbios_print_str("SKU Number", table, *addr); +} + +static void smbios_print_type4(struct smbios_type4 *table) +{ + printf("Processor Information:\n"); + smbios_print_str("Socket Designation", table, table->socket_design); + smbios_print_lookup_str(processor_type_strings, + table->processor_type, + ARRAY_SIZE(processor_type_strings), + "Processor Type"); + smbios_print_lookup_str(processor_family_strings, + table->processor_family, + ARRAY_SIZE(processor_family_strings), + "Processor Family"); + smbios_print_str("Processor Manufacturer", table, + table->processor_manufacturer); + printf("\tProcessor ID word 0: 0x%08x\n", table->processor_id[0]); + printf("\tProcessor ID word 1: 0x%08x\n", table->processor_id[1]); + smbios_print_str("Processor Version", table, table->processor_version); + printf("\tVoltage: 0x%02x\n", table->voltage); + printf("\tExternal Clock: 0x%04x\n", table->external_clock); + printf("\tMax Speed: 0x%04x\n", table->max_speed); + printf("\tCurrent Speed: 0x%04x\n", table->current_speed); + printf("\tStatus: 0x%02x\n", table->status); + smbios_print_lookup_str(processor_upgrade_strings, + table->processor_upgrade, + ARRAY_SIZE(processor_upgrade_strings), + "Processor Upgrade"); + printf("\tL1 Cache Handle: 0x%04x\n", table->l1_cache_handle); + printf("\tL2 Cache Handle: 0x%04x\n", table->l2_cache_handle); + printf("\tL3 Cache Handle: 0x%04x\n", table->l3_cache_handle); + smbios_print_str("Serial Number", table, table->serial_number); + smbios_print_str("Asset Tag", table, table->asset_tag); + smbios_print_str("Part Number", table, table->part_number); + printf("\tCore Count: 0x%02x\n", table->core_count); + printf("\tCore Enabled: 0x%02x\n", table->core_enabled); + printf("\tThread Count: 0x%02x\n", table->thread_count); + printf("\tProcessor Characteristics: 0x%04x\n", + table->processor_characteristics); + smbios_print_lookup_str(processor_family_strings, + table->processor_family2, + ARRAY_SIZE(processor_family_strings), + "Processor Family 2"); + printf("\tCore Count 2: 0x%04x\n", table->core_count2); + printf("\tCore Enabled 2: 0x%04x\n", table->core_enabled2); + printf("\tThread Count 2: 0x%04x\n", table->thread_count2); + printf("\tThread Enabled: 0x%04x\n", table->thread_enabled); +} + +static void smbios_print_type7(struct smbios_type7 *table) +{ + printf("Cache Information:\n"); + smbios_print_str("Socket Designation", table, + table->socket_design); + printf("\tCache Configuration: 0x%04x\n", table->config.data); + printf("\tMaximum Cache Size: 0x%04x\n", table->max_size.data); + printf("\tInstalled Size: 0x%04x\n", table->inst_size.data); + printf("\tSupported SRAM Type: 0x%04x\n", table->supp_sram_type.data); + printf("\tCurrent SRAM Type: 0x%04x\n", table->curr_sram_type.data); + printf("\tCache Speed: 0x%02x\n", table->speed); + smbios_print_lookup_str(err_corr_type_strings, + table->err_corr_type, + ARRAY_SIZE(err_corr_type_strings), + "Error Correction Type"); + smbios_print_lookup_str(sys_cache_type_strings, + table->sys_cache_type, + ARRAY_SIZE(sys_cache_type_strings), + "System Cache Type"); + smbios_print_lookup_str(associativity_strings, + table->associativity, + ARRAY_SIZE(associativity_strings), + "Associativity"); + printf("\tMaximum Cache Size 2: 0x%08x\n", table->max_size2.data); + printf("\tInstalled Cache Size 2: 0x%08x\n", table->inst_size2.data); +} + static void smbios_print_type127(struct smbios_type127 *table) { printf("End Of Table\n"); @@ -192,13 +464,25 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc, pos->handle, pos->type, pos->length, (unsigned long long)map_to_sysmem(pos)); switch (pos->type) { - case 1: + case SMBIOS_BIOS_INFORMATION: + smbios_print_type0((struct smbios_type0 *)pos); + break; + case SMBIOS_SYSTEM_INFORMATION: smbios_print_type1((struct smbios_type1 *)pos); break; - case 2: + case SMBIOS_BOARD_INFORMATION: smbios_print_type2((struct smbios_type2 *)pos); break; - case 127: + case SMBIOS_SYSTEM_ENCLOSURE: + smbios_print_type3((struct smbios_type3 *)pos); + break; + case SMBIOS_PROCESSOR_INFORMATION: + smbios_print_type4((struct smbios_type4 *)pos); + break; + case SMBIOS_CACHE_INFORMATION: + smbios_print_type7((struct smbios_type7 *)pos); + break; + case SMBIOS_END_OF_TABLE: smbios_print_type127((struct smbios_type127 *)pos); break; default: diff --git a/common/board_f.c b/common/board_f.c index 54c48d42ee9..6c5c3bfab48 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -815,21 +815,26 @@ static int initf_bootstage(void) static int initf_dm(void) { -#if defined(CONFIG_DM) && CONFIG_IS_ENABLED(SYS_MALLOC_F) int ret; + if (!CONFIG_IS_ENABLED(SYS_MALLOC_F)) + return 0; + bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f"); ret = dm_init_and_scan(true); bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F); if (ret) return ret; + ret = dm_autoprobe(); + if (ret) + return ret; + if (IS_ENABLED(CONFIG_TIMER_EARLY)) { ret = dm_timer_init(); if (ret) return ret; } -#endif return 0; } diff --git a/common/board_r.c b/common/board_r.c index f63c6aed4d5..179259b00de 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -250,7 +250,7 @@ static int initr_dm(void) if (ret) return ret; - return 0; + return dm_autoprobe(); } #endif diff --git a/common/spl/spl.c b/common/spl/spl.c index ad31a2f8b6c..02269fff93c 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -500,6 +500,10 @@ static int spl_common_init(bool setup_malloc) debug("dm_init_and_scan() returned error %d\n", ret); return ret; } + + ret = dm_autoprobe(); + if (ret) + return ret; } return 0; diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 107d6c6becf..bf6e9639901 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -1,12 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_AM62A7=y CONFIG_TARGET_AM62A7_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-sk" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -31,11 +33,14 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_REMOTEPROC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -55,10 +60,21 @@ CONFIG_CLK_TI_SCI=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y -# CONFIG_GPIO is not set -# CONFIG_I2C is not set +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -72,6 +88,12 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_REMOTEPROC_TI_K3_DSP=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index ec712b14492..274cd20e1c1 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -8,7 +8,6 @@ CONFIG_TARGET_AM62A7_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk" CONFIG_DM_RESET=y @@ -63,9 +62,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y -CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y @@ -88,6 +85,7 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index a0eaa128f47..9df90e05d36 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -10,7 +10,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" CONFIG_DM_RESET=y @@ -67,9 +66,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y -CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 2509a91cf62..c77e09db156 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_AM625=y @@ -8,6 +9,7 @@ CONFIG_TARGET_AM625_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk" CONFIG_SPL_TEXT_BASE=0x80080000 @@ -40,7 +42,9 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y @@ -74,9 +78,21 @@ CONFIG_DFU_SF=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -97,6 +113,12 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index c7fc9d124c7..0ceac16dd20 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -11,7 +11,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm" @@ -84,9 +83,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index eb63f060c1b..2750fa2cc27 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -74,5 +74,6 @@ CONFIG_PL01X_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index decac2e1935..5e67de3bd85 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,28 +1,16 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -30,22 +18,22 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -60,7 +48,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -76,6 +64,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y @@ -85,6 +74,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 0fb73049738..b4f7e61ad0d 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_TEXT_BASE=0x1110000 CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x3d00 +CONFIG_BLOBLIST_SIZE_RELOC=0x30000 CONFIG_NR_DRAM_BANKS=8 CONFIG_MAX_CPUS=8 CONFIG_SPL_DM_SPI=y @@ -44,8 +45,8 @@ CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set -CONFIG_BLOBLIST_ADDR=0x100000 -CONFIG_BLOBLIST_SIZE=0x30000 +CONFIG_BLOBLIST_ADDR=0xfef10000 +CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 5bbea6c42a8..0be6e4462dd 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -1,29 +1,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_KEVIN=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -31,22 +19,22 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -61,7 +49,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -77,6 +65,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y @@ -86,6 +75,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 00f23174210..d8a671b7a8a 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -4,20 +4,13 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-firefly" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_SIZE_LIMIT=0x40000 @@ -25,13 +18,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-firefly.dtb" +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -47,10 +42,12 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -63,17 +60,22 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y @@ -96,4 +98,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge2-rk3588s_defconfig b/configs/khadas-edge2-rk3588s_defconfig new file mode 100644 index 00000000000..208c72ca425 --- /dev/null +++ b/configs/khadas-edge2-rk3588s_defconfig @@ -0,0 +1,215 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-khadas-edge2" +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_KHADAS_EDGE2_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-khadas-edge2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_AB=y +CONFIG_SYS_PROMPT="kedge2# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_SPI=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_MMC=y +# CONFIG_DM_SPI_FLASH=y +CONFIG_MMC=y +# CONFIG_MMC_SPI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x07000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEY=y +CONFIG_RK8XX_PWRKEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +# CONFIG_NAND=y +# CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_FUEL_GAUGE=y +CONFIG_POWER_FG_CW201X=y +CONFIG_POWER_FG_CW221X=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_DM_POWER_DELIVERY=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_HUSB311=y +CONFIG_TYPEC_FUSB302=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_REGULATOR_RK806=y +CONFIG_CHARGER_BQ25700=y +CONFIG_CHARGER_BQ25890=y +CONFIG_CHARGER_SC8551=y +CONFIG_CHARGER_SGM41542=y +CONFIG_DM_CHARGE_DISPLAY=y +CONFIG_CHARGE_ANIMATION=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RAMDISK=y +CONFIG_RAMDISK_RO=y +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_MAXIM_MAX96745=y +CONFIG_DRM_MAXIM_MAX96755F=y +CONFIG_DRM_PANEL_ROHM_BU18RL82=y +CONFIG_DRM_PANEL_MAXIM_MAX96752F=y +CONFIG_DRM_ROHM_BU18XL82=y +CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_DW_DP=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_XBC=y +CONFIG_LZ4=y +CONFIG_LZMA=y +CONFIG_ERRNO_STR=y +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 420a8bd1e79..166468fd4e7 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -1,37 +1,31 @@ CONFIG_ARM=y CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00000000 +CONFIG_TEXT_BASE=0x01000000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-miqi" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_MIQI_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_TEXT_BASE=0xff704000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-miqi.dtb" +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -47,10 +41,12 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -61,8 +57,13 @@ CONFIG_SPL_CLK=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y @@ -71,6 +72,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y @@ -93,4 +95,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 12a37054b4d..e47d0b594f3 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -14,7 +14,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3066a-mk808" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3066=y # CONFIG_ROCKCHIP_STIMER is not set @@ -35,7 +35,7 @@ CONFIG_SPL_PAYLOAD="u-boot.bin" CONFIG_DEBUG_UART=y CONFIG_SD_BOOT=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3066a-mk808.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig new file mode 100644 index 00000000000..870613f690a --- /dev/null +++ b/configs/nanopi-r3s-rk3566_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 06ac6fed3bc..0c7107c1f41 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -61,6 +61,8 @@ CONFIG_PCIE_ECAM_GENERIC=y CONFIG_SCSI=y CONFIG_DEBUG_UART_PL011=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y @@ -70,3 +72,4 @@ CONFIG_USB_EHCI_PCI=y CONFIG_SEMIHOSTING=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y +CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig new file mode 100644 index 00000000000..59f9f25edcb --- /dev/null +++ b/configs/rock-5c-rk3588s_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5c" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ROCK_5C_RK3588S=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index d7f11310cba..9c05bf45146 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3188-radxarock" CONFIG_ROCKCHIP_RK3188=y # CONFIG_ROCKCHIP_STIMER is not set CONFIG_TARGET_ROCK=y @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3188-radxarock.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x7800 diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 08b7e2784e9..75322073285 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -20,8 +20,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -39,7 +37,6 @@ CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y -CONFIG_CMD_BOOTSTAGE=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 42dbef9c2c3..bc5379d4343 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -4,21 +4,12 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_SIZE_LIMIT=0x4b000 @@ -26,15 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker.dtb" +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -43,6 +34,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -50,10 +42,13 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -65,19 +60,20 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y @@ -95,8 +91,11 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index e62a03e066c..f0c8cc5bbc1 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -4,21 +4,12 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker-s" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x800000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_SIZE_LIMIT=0x4b000 @@ -26,15 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker-s.dtb" +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -51,10 +42,13 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -66,19 +60,20 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y @@ -102,4 +97,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 4d23b353409..529815afe16 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -78,4 +78,5 @@ CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index 8453be5a590..818c62c6959 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -76,4 +76,5 @@ CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index c8f166c1221..fb757c1067d 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -83,6 +83,7 @@ CONFIG_CLK_VERSAL=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 8fb66f7cb08..a68bd522f90 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -197,6 +197,7 @@ CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 9d785413a8e..7667e67a05a 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y # CONFIG_BINMAN_FDT is not set CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 09f487acf0d..b13079cdf70 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -110,7 +110,7 @@ CONFIG_CMD_UBI=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_BOARD=y -CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-dlc21-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-vpk120-revA zynqmp-vp-x-a2785-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-rev1.1 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-rev1.0 zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-zcu670-revA zynqmp-zcu670-revB" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index cd84df1e290..6a5e1dd5d95 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -92,6 +92,7 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index 1eda769c752..b48afb27938 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -243,7 +243,7 @@ board_init_r(), as per the rules, and DRAM is available then. SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper. This includes a pointer to the HOB list as well as DRAM information. See struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR, -normally 100000. +normally fef10000. SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent boots. Be warned that SPL can take 30 seconds without this cache! This is a diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9bab86d2347..1407080f1f4 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: * rk3566 - Anbernic RGxx3 (anbernic-rgxx3-rk3566) + - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566) - Hardkernel ODROID-M1S (odroid-m1s-rk3566) - Pine64 PineTab2 (pinetab2-rk3566) - Pine64 Quartz64-A Board (quartz64-a-rk3566) @@ -137,10 +138,12 @@ List of mainline supported Rockchip boards: - Generic RK3588S/RK3588 (generic-rk3588) - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) + - Khadas Edge2 (khadas-edge2-rk3588s) - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) + - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index db15f945d3b..cba4fd066ab 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -40,10 +40,10 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin + export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf + export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt - ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL" + ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index 46112544c82..4586b8d8b5a 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -47,11 +47,11 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin + export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf + export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt - ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL" + ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst index 8c2c81d7ac9..92f638a0204 100644 --- a/doc/develop/driver-model/design.rst +++ b/doc/develop/driver-model/design.rst @@ -842,6 +842,23 @@ steps (see device_probe()): cause the uclass to do some housekeeping to record the device as activated and 'known' by the uclass. +For some platforms, certain devices must be probed to get the platform into +a working state. To help with this, drivers marked with DM_FLAG_PROBE_AFTER_BIND +will be probed immediately after all devices are bound. For now, this happens in +SPL, before relocation and after relocation. See the call to ``dm_autoprobe()`` +for where this is done. + +The auto-probe feature is tricky because it bypasses the normal ordering of +probing. General, if device A (e.g. video) needs device B (e.g. clock), then +A's probe() method uses ``clk_get_by_index()`` and B is probed before A. But +A is only probed when it is used. Therefore care should be taken when using +auto-probe, limiting it to devices which truly are essential, such as power +domains or critical clocks. + +See here for more discussion of this feature: + +:Link: https://patchwork.ozlabs.org/project/uboot/patch/20240626235717.272219-1-marex@denx.de/ + Running stage ^^^^^^^^^^^^^ diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 449d0375a1b..859ae3b1974 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -51,13 +51,15 @@ Examples:: Current Status -------------- -* U-Boot v2024.10 was released on Mon 07 October 2024. +* U-Boot v2025.01 was released on Mon 06 January 2025. -* The Merge Window for the next release (v2025.01) is **closed**. +* The Merge Window for the next release (v2025.04) is **open** until the -rc1 + release on Mon 27 January 2025. -* The next branch is now **open**. +* The next branch is now **closed** until the -rc2 release on Mon 10 February + 2025. -* Release "v2025.01" is scheduled for 06 January 2025. +* Release "v2025.04" is scheduled for 07 April 2025. Future Releases --------------- @@ -65,31 +67,29 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -For the next scheduled release, release candidates were made on:: +.. For the next scheduled release, release candidates were made on:: -* U-Boot v2025.01-rc1 was released on Mon 28 October 2024. +.. * U-Boot v2025.04-rc1 was released on Mon 27 January 2025. -* U-Boot v2025.01-rc2 was released on Mon 11 November 2024. +.. * U-Boot v2025.04-rc2 was released on Mon 10 February 2025. -* U-Boot v2025.01-rc3 was released on Mon 25 November 2024. +.. * U-Boot v2025.04-rc3 was released on Mon 24 February 2025. -* U-Boot v2025.01-rc4 was released on Mon 09 December 2024. +.. * U-Boot v2025.04-rc4 was released on Mon 10 March 2025. -* U-Boot v2025.01-rc5 was released on Mon 23 December 2024. - -* U-Boot v2025.01-rc6 was released on Mon 30 December 2024. +.. * U-Boot v2025.04-rc5 was released on Mon 24 March 2025. Please note that the following dates are planned only and may be deviated from as needed. -* "v2025.01": end of MW = Mon, Oct 21, 2024; release = Mon, Jan 06, 2025 - * "v2025.04": end of MW = Mon, Jan 27, 2025; release = Mon, Apr 07, 2025 * "v2025.07": end of MW = Mon, Apr 21, 2025; release = Mon, Jul 07, 2025 * "v2025.10": end of MW = Mon, Jul 21, 2025; release = Mon, Oct 06, 2025 +* "v2026.01": end of MW = Mon, Oct 20, 2025; release = Mon, Jan 05, 2026 + Previous Releases ----------------- @@ -97,6 +97,8 @@ Note: these statistics are generated by our fork of `gitdm <https://source.denx.de/u-boot/gitdm>`_, which was originally created by Jonathan Corbet. +* :doc:`statistics/u-boot-stats-v2025.01` which was released on 06 January 2025. + * :doc:`statistics/u-boot-stats-v2024.10` which was released on 07 October 2024. * :doc:`statistics/u-boot-stats-v2024.07` which was released on 01 July 2024. diff --git a/doc/develop/statistics/u-boot-stats-v2025.01.rst b/doc/develop/statistics/u-boot-stats-v2025.01.rst new file mode 100644 index 00000000000..668ccffba0b --- /dev/null +++ b/doc/develop/statistics/u-boot-stats-v2025.01.rst @@ -0,0 +1,907 @@ +:orphan: + +Release Statistics for U-Boot v2025.01 +====================================== + +* Processed 1768 changesets from 205 developers + +* 27 employers found + +* A total of 1040983 lines added, 82958 removed (delta 958025) + +.. table:: Developers with the most changesets + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 352 (19.9%) + Marek Vasut 114 (6.4%) + Heinrich Schuchardt 88 (5.0%) + Christian Marangi 68 (3.8%) + Sughosh Ganu 56 (3.2%) + Jerome Forissier 51 (2.9%) + Caleb Connolly 46 (2.6%) + Sam Protsenko 42 (2.4%) + Neil Armstrong 40 (2.3%) + Patrick Rudolph 34 (1.9%) + Tom Rini 33 (1.9%) + Michal Simek 32 (1.8%) + Ilias Apalodimas 29 (1.6%) + Rasmus Villemoes 29 (1.6%) + Raymond Mao 28 (1.6%) + Peng Fan 25 (1.4%) + Jonas Karlman 24 (1.4%) + Venkatesh Yadav Abbarapu 23 (1.3%) + Oliver Gaskell 21 (1.2%) + Fabio Estevam 19 (1.1%) + Heiko Stuebner 17 (1.0%) + Ye Li 16 (0.9%) + Svyatoslav Ryhel 15 (0.8%) + Paul Kocialkowski 15 (0.8%) + Richard Weinberger 14 (0.8%) + Chia-Wei Wang 12 (0.7%) + Takahiro Kuwano 12 (0.7%) + Daniel Schultz 12 (0.7%) + Zixun LI 11 (0.6%) + Paul Barker 10 (0.6%) + Anatolij Gustschin 10 (0.6%) + Manorit Chawdhry 9 (0.5%) + Patrice Chotard 9 (0.5%) + Padmarao Begari 9 (0.5%) + Romain Naour 9 (0.5%) + Bhupesh Sharma 9 (0.5%) + Chris Packham 8 (0.5%) + Andy Shevchenko 8 (0.5%) + Wadim Egorov 8 (0.5%) + Bastien Curutchet 8 (0.5%) + Hanyuan Zhao 8 (0.5%) + Chris Morgan 8 (0.5%) + Tim Harvey 8 (0.5%) + Quentin Schulz 7 (0.4%) + Andrew Goodbody 7 (0.4%) + Mattijs Korpershoek 6 (0.3%) + William Zhang 6 (0.3%) + Janne Grunau 6 (0.3%) + Jan Kiszka 6 (0.3%) + Dmitry Rokosov 6 (0.3%) + Sebastian Reichel 6 (0.3%) + Kishon Vijay Abraham I 6 (0.3%) + Jonathan Humphreys 5 (0.3%) + Patrick Delaunay 5 (0.3%) + Michael Walle 5 (0.3%) + Yuri Zaporozhets 5 (0.3%) + Linus Walleij 5 (0.3%) + Julius Lehmann 5 (0.3%) + Boyan Karatotev 5 (0.3%) + Baocheng Su 5 (0.3%) + Prasad Kummari 5 (0.3%) + Jim Liu 5 (0.3%) + Jacky Chou 5 (0.3%) + Philip Oberfichtner 5 (0.3%) + Andy Yan 4 (0.2%) + Siddharth Vadapalli 4 (0.2%) + david regan 4 (0.2%) + Ion Agorria 4 (0.2%) + Andrejs Cainikovs 4 (0.2%) + Billy Tsai 4 (0.2%) + Marcin Juszkiewicz 4 (0.2%) + Jesse Taube 4 (0.2%) + Alexander Kochetkov 4 (0.2%) + Chintan Vankar 4 (0.2%) + Martyn Welch 4 (0.2%) + Jernej Skrabec 4 (0.2%) + John Watts 4 (0.2%) + Sean Anderson 4 (0.2%) + Kongyang Liu 4 (0.2%) + Prasanth Babu Mantena 3 (0.2%) + J. Neuschäfer 3 (0.2%) + E Shattow 3 (0.2%) + Nicolas Belin 3 (0.2%) + Udit Kumar 3 (0.2%) + Leo Yan 3 (0.2%) + Love Kumar 3 (0.2%) + Weijie Gao 3 (0.2%) + Erik Schumacher 3 (0.2%) + Conor Dooley 3 (0.2%) + LekKit 3 (0.2%) + Maksim Kiselev 3 (0.2%) + Maximilian Brune 3 (0.2%) + FUKAUMI Naoki 3 (0.2%) + Hiago De Franco 3 (0.2%) + Devarsh Thakkar 3 (0.2%) + Joy Zou 3 (0.2%) + Andre Przywara 3 (0.2%) + Tomas Paukrt 3 (0.2%) + Arseniy Krasnov 3 (0.2%) + Andreas Schwab 2 (0.1%) + Tony Dinh 2 (0.1%) + Khoa Hoang 2 (0.1%) + Nam Cao 2 (0.1%) + Javier Tia 2 (0.1%) + Lad Prabhakar 2 (0.1%) + Ian Ray 2 (0.1%) + Paul Geurts 2 (0.1%) + Moritz Fischer 2 (0.1%) + Gilles Talis 2 (0.1%) + Vaishnav Achath 2 (0.1%) + Mayuresh Chitale 2 (0.1%) + Frank Sae 2 (0.1%) + Alex Shumsky 2 (0.1%) + John Vicky Vykuntapu 2 (0.1%) + Miquel Raynal 2 (0.1%) + Santhosh Kumar K 2 (0.1%) + Brian Ruley 2 (0.1%) + Ashok Reddy Soma 2 (0.1%) + Daniel Palmer 2 (0.1%) + Matthias Pritschet 2 (0.1%) + Dario Binacchi 2 (0.1%) + Vignesh Raghavendra 2 (0.1%) + Benjamin Hahn 2 (0.1%) + Yashwanth Varakala 2 (0.1%) + Yasuharu Shibata 2 (0.1%) + Mikhail Kshevetskiy 2 (0.1%) + Geert Uytterhoeven 1 (0.1%) + Ronald Wahl 1 (0.1%) + Francois Berder 1 (0.1%) + Wei Ming Chen 1 (0.1%) + Leonard Anderweit 1 (0.1%) + Johan Jonker 1 (0.1%) + Roger Quadros 1 (0.1%) + Peter Robinson 1 (0.1%) + Vincent Stehlé 1 (0.1%) + Evgeny Bachinin 1 (0.1%) + Mark Kettenis 1 (0.1%) + Dominik Wernberger 1 (0.1%) + Joel Stanley 1 (0.1%) + Ben Horgan 1 (0.1%) + Holger Brunck 1 (0.1%) + Dominique Martinet 1 (0.1%) + Francesco Dolcini 1 (0.1%) + Heiko Schocher 1 (0.1%) + Vasileios Amoiridis 1 (0.1%) + Peter Korsgaard 1 (0.1%) + Loic Poulain 1 (0.1%) + Saeed Nowshadi 1 (0.1%) + Sergey Bostandzhyan 1 (0.1%) + Chris Paterson 1 (0.1%) + Benjamin SzÅ‘ke 1 (0.1%) + mason1920 1 (0.1%) + Uwe Kleine-König 1 (0.1%) + Nick Hu 1 (0.1%) + Henrik Grimler 1 (0.1%) + Baruch Siach 1 (0.1%) + Markus Volk 1 (0.1%) + Tudor Ambarus 1 (0.1%) + Jonas Jelonek 1 (0.1%) + Alexander Dahl 1 (0.1%) + Anton Blanchard 1 (0.1%) + Li Hua Qian 1 (0.1%) + Daniel Semkowicz 1 (0.1%) + Lukasz Czechowski 1 (0.1%) + Paul Alvin 1 (0.1%) + Philip Balister 1 (0.1%) + Han Xu 1 (0.1%) + Dmitry Dunaev 1 (0.1%) + Guillaume La Roque 1 (0.1%) + Eva Kurchatova 1 (0.1%) + Dmitrii Merkurev 1 (0.1%) + Ken Kurematsu 1 (0.1%) + Ray Chang 1 (0.1%) + Bhavya Kapoor 1 (0.1%) + Parth Pancholi 1 (0.1%) + Eugen Hristev 1 (0.1%) + Godfrey Mwangi 1 (0.1%) + Callum Parsey 1 (0.1%) + Jonas Schwöbel 1 (0.1%) + Sidharth Prabukumar 1 (0.1%) + Chris Webb 1 (0.1%) + Ying-Chun Liu (PaulLiu) 1 (0.1%) + Vitor Soares 1 (0.1%) + Arturo Buzarra 1 (0.1%) + Joakim Tjernlund 1 (0.1%) + Vitaliy Vasylskyy 1 (0.1%) + Jacky Bai 1 (0.1%) + Frank Li 1 (0.1%) + Stanley Chu 1 (0.1%) + Francis Laniel 1 (0.1%) + John Keeping 1 (0.1%) + Keerthy 1 (0.1%) + Kuan Lim Lee 1 (0.1%) + Rogerio Guerra Borin 1 (0.1%) + Mathieu Othacehe 1 (0.1%) + Franco Venturi 1 (0.1%) + Maxim Moskalets 1 (0.1%) + Derald D. Woods 1 (0.1%) + MD Danish Anwar 1 (0.1%) + Andrew Davis 1 (0.1%) + Primoz Fiser 1 (0.1%) + Lukasz Majewski 1 (0.1%) + Jianfeng A Zhu 1 (0.1%) + Ravi Minnikanti 1 (0.1%) + Michael Polyntsov 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most changed lines + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 929361 (86.0%) + Simon Glass 18229 (1.7%) + Marek Vasut 12581 (1.2%) + Chia-Wei Wang 12218 (1.1%) + Peng Fan 9088 (0.8%) + Caleb Connolly 6163 (0.6%) + Christian Marangi 5779 (0.5%) + Sebastian Reichel 5023 (0.5%) + Vitaliy Vasylskyy 4735 (0.4%) + Fabio Estevam 4727 (0.4%) + Jerome Forissier 4086 (0.4%) + Patrick Rudolph 4001 (0.4%) + Bhupesh Sharma 3827 (0.4%) + Andrew Davis 3676 (0.3%) + Andre Przywara 3267 (0.3%) + Raymond Mao 3040 (0.3%) + Gilles Talis 2897 (0.3%) + Vaishnav Achath 2852 (0.3%) + david regan 2790 (0.3%) + Paul Barker 2574 (0.2%) + Sughosh Ganu 2518 (0.2%) + Kongyang Liu 2406 (0.2%) + Jonas Karlman 2194 (0.2%) + Oliver Gaskell 1930 (0.2%) + Venkatesh Yadav Abbarapu 1762 (0.2%) + Svyatoslav Ryhel 1540 (0.1%) + Jan Kiszka 1362 (0.1%) + Neil Armstrong 1225 (0.1%) + Sam Protsenko 1078 (0.1%) + Marcin Juszkiewicz 1045 (0.1%) + Heinrich Schuchardt 1022 (0.1%) + Conor Dooley 890 (0.1%) + Michal Simek 881 (0.1%) + Siddharth Vadapalli 879 (0.1%) + Heiko Stuebner 803 (0.1%) + Jim Liu 772 (0.1%) + Love Kumar 707 (0.1%) + Derald D. Woods 695 (0.1%) + Philip Oberfichtner 645 (0.1%) + Andy Yan 614 (0.1%) + Ilias Apalodimas 580 (0.1%) + Billy Tsai 563 (0.1%) + Julius Lehmann 561 (0.1%) + Frank Sae 499 (0.0%) + Chris Packham 485 (0.0%) + Janne Grunau 473 (0.0%) + Johan Jonker 469 (0.0%) + Alexander Kochetkov 457 (0.0%) + Chris Morgan 425 (0.0%) + Ye Li 413 (0.0%) + Bastien Curutchet 385 (0.0%) + Dmitry Rokosov 376 (0.0%) + Kuan Lim Lee 375 (0.0%) + Maximilian Brune 334 (0.0%) + Linus Walleij 328 (0.0%) + Manorit Chawdhry 302 (0.0%) + Rasmus Villemoes 297 (0.0%) + Martyn Welch 292 (0.0%) + Zixun LI 269 (0.0%) + Romain Naour 229 (0.0%) + Lad Prabhakar 215 (0.0%) + Richard Weinberger 212 (0.0%) + Paul Kocialkowski 209 (0.0%) + Chintan Vankar 202 (0.0%) + Keerthy 191 (0.0%) + Wadim Egorov 188 (0.0%) + Santhosh Kumar K 173 (0.0%) + Tim Harvey 168 (0.0%) + Anatolij Gustschin 155 (0.0%) + Prasad Kummari 154 (0.0%) + Hanyuan Zhao 147 (0.0%) + William Zhang 147 (0.0%) + Mayuresh Chitale 139 (0.0%) + Quentin Schulz 133 (0.0%) + Dmitrii Merkurev 124 (0.0%) + FUKAUMI Naoki 117 (0.0%) + Padmarao Begari 116 (0.0%) + Lukasz Czechowski 112 (0.0%) + Mathieu Othacehe 110 (0.0%) + Andrew Goodbody 106 (0.0%) + Francis Laniel 98 (0.0%) + Takahiro Kuwano 96 (0.0%) + Boyan Karatotev 94 (0.0%) + Jacky Chou 90 (0.0%) + Andy Shevchenko 87 (0.0%) + Baocheng Su 86 (0.0%) + Ashok Reddy Soma 83 (0.0%) + Mattijs Korpershoek 82 (0.0%) + Kishon Vijay Abraham I 80 (0.0%) + Daniel Schultz 73 (0.0%) + Jernej Skrabec 72 (0.0%) + Arseniy Krasnov 72 (0.0%) + Guillaume La Roque 71 (0.0%) + Benjamin Hahn 62 (0.0%) + Vasileios Amoiridis 58 (0.0%) + Udit Kumar 56 (0.0%) + Paul Alvin 54 (0.0%) + Leo Yan 53 (0.0%) + Paul Geurts 53 (0.0%) + Ion Agorria 51 (0.0%) + Patrick Delaunay 50 (0.0%) + Brian Ruley 49 (0.0%) + Maksim Kiselev 48 (0.0%) + Matthias Pritschet 47 (0.0%) + J. Neuschäfer 46 (0.0%) + Javier Tia 45 (0.0%) + Jesse Taube 41 (0.0%) + Joy Zou 41 (0.0%) + Tony Dinh 40 (0.0%) + Ravi Minnikanti 39 (0.0%) + Sean Anderson 38 (0.0%) + Prasanth Babu Mantena 37 (0.0%) + Khoa Hoang 37 (0.0%) + Parth Pancholi 36 (0.0%) + Yasuharu Shibata 35 (0.0%) + Dmitry Dunaev 35 (0.0%) + Weijie Gao 34 (0.0%) + Sergey Bostandzhyan 32 (0.0%) + Arturo Buzarra 32 (0.0%) + Patrice Chotard 30 (0.0%) + Jonathan Humphreys 30 (0.0%) + Erik Schumacher 30 (0.0%) + Alex Shumsky 30 (0.0%) + Nick Hu 30 (0.0%) + Tomas Paukrt 27 (0.0%) + Devarsh Thakkar 24 (0.0%) + Michael Polyntsov 24 (0.0%) + Callum Parsey 23 (0.0%) + Yuri Zaporozhets 22 (0.0%) + Hiago De Franco 21 (0.0%) + Chris Webb 21 (0.0%) + Francois Berder 20 (0.0%) + John Watts 19 (0.0%) + Nicolas Belin 19 (0.0%) + Daniel Palmer 19 (0.0%) + Michael Walle 18 (0.0%) + Bhavya Kapoor 18 (0.0%) + Jonas Schwöbel 18 (0.0%) + Stanley Chu 18 (0.0%) + Benjamin SzÅ‘ke 17 (0.0%) + John Keeping 17 (0.0%) + Ian Ray 14 (0.0%) + John Vicky Vykuntapu 13 (0.0%) + Peter Korsgaard 13 (0.0%) + MD Danish Anwar 13 (0.0%) + Vignesh Raghavendra 12 (0.0%) + Andrejs Cainikovs 11 (0.0%) + Li Hua Qian 10 (0.0%) + Moritz Fischer 9 (0.0%) + Evgeny Bachinin 9 (0.0%) + Loic Poulain 9 (0.0%) + Joakim Tjernlund 9 (0.0%) + Miquel Raynal 8 (0.0%) + Lukasz Majewski 8 (0.0%) + Jianfeng A Zhu 8 (0.0%) + Nam Cao 7 (0.0%) + Holger Brunck 7 (0.0%) + Heiko Schocher 7 (0.0%) + Andreas Schwab 6 (0.0%) + Geert Uytterhoeven 6 (0.0%) + Anton Blanchard 6 (0.0%) + Jacky Bai 6 (0.0%) + E Shattow 5 (0.0%) + Ray Chang 5 (0.0%) + LekKit 4 (0.0%) + Yashwanth Varakala 4 (0.0%) + Peter Robinson 4 (0.0%) + Maxim Moskalets 4 (0.0%) + Ronald Wahl 3 (0.0%) + Uwe Kleine-König 3 (0.0%) + Markus Volk 3 (0.0%) + Eugen Hristev 3 (0.0%) + Godfrey Mwangi 3 (0.0%) + Dario Binacchi 2 (0.0%) + Mikhail Kshevetskiy 2 (0.0%) + Wei Ming Chen 2 (0.0%) + Leonard Anderweit 2 (0.0%) + Dominik Wernberger 2 (0.0%) + Joel Stanley 2 (0.0%) + Saeed Nowshadi 2 (0.0%) + Henrik Grimler 2 (0.0%) + Eva Kurchatova 2 (0.0%) + Frank Li 2 (0.0%) + Rogerio Guerra Borin 2 (0.0%) + Roger Quadros 1 (0.0%) + Vincent Stehlé 1 (0.0%) + Mark Kettenis 1 (0.0%) + Ben Horgan 1 (0.0%) + Dominique Martinet 1 (0.0%) + Francesco Dolcini 1 (0.0%) + Chris Paterson 1 (0.0%) + mason1920 1 (0.0%) + Baruch Siach 1 (0.0%) + Tudor Ambarus 1 (0.0%) + Jonas Jelonek 1 (0.0%) + Alexander Dahl 1 (0.0%) + Daniel Semkowicz 1 (0.0%) + Philip Balister 1 (0.0%) + Han Xu 1 (0.0%) + Ken Kurematsu 1 (0.0%) + Sidharth Prabukumar 1 (0.0%) + Ying-Chun Liu (PaulLiu) 1 (0.0%) + Vitor Soares 1 (0.0%) + Franco Venturi 1 (0.0%) + Primoz Fiser 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most lines removed + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Marek Vasut 6902 (8.3%) + Andrew Davis 3578 (4.3%) + Andre Przywara 3255 (3.9%) + david regan 2650 (3.2%) + Paul Barker 2432 (2.9%) + Fabio Estevam 2002 (2.4%) + Caleb Connolly 1697 (2.0%) + Jan Kiszka 1189 (1.4%) + Conor Dooley 758 (0.9%) + Derald D. Woods 693 (0.8%) + Johan Jonker 469 (0.6%) + Lad Prabhakar 182 (0.2%) + Paul Kocialkowski 134 (0.2%) + Andy Shevchenko 44 (0.1%) + Tony Dinh 18 (0.0%) + Manorit Chawdhry 13 (0.0%) + Maximilian Brune 8 (0.0%) + Holger Brunck 7 (0.0%) + Jacky Bai 6 (0.0%) + Anatolij Gustschin 5 (0.0%) + Li Hua Qian 5 (0.0%) + Miquel Raynal 3 (0.0%) + E Shattow 3 (0.0%) + Geert Uytterhoeven 2 (0.0%) + Maxim Moskalets 2 (0.0%) + Uwe Kleine-König 2 (0.0%) + Hiago De Franco 1 (0.0%) + Anton Blanchard 1 (0.0%) + Roger Quadros 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most signoffs (total 307) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Minkyu Kang 41 (13.4%) + Mattijs Korpershoek 34 (11.1%) + Michal Simek 27 (8.8%) + Peng Fan 25 (8.1%) + Neil Armstrong 19 (6.2%) + Nathan Barrett-Morrison 13 (4.2%) + Greg Malysa 12 (3.9%) + Ilias Apalodimas 10 (3.3%) + Heiko Stuebner 10 (3.3%) + Chintan Vankar 8 (2.6%) + Siddharth Vadapalli 7 (2.3%) + Jan Kiszka 6 (2.0%) + Miquel Raynal 6 (2.0%) + Trevor Woerner 6 (2.0%) + Linus Walleij 6 (2.0%) + Leo Yan 5 (1.6%) + Svyatoslav Ryhel 5 (1.6%) + Jonas Karlman 5 (1.6%) + Tom Rini 5 (1.6%) + Max Krummenacher 4 (1.3%) + Ashok Reddy Soma 4 (1.3%) + Patrick Rudolph 4 (1.3%) + Simon Glass 3 (1.0%) + Marek Vasut 2 (0.7%) + Tejas Bhumkar 2 (0.7%) + Nishanth Menon 2 (0.7%) + Alice Guo 2 (0.7%) + Wang Jie 2 (0.7%) + Chen-Yu Tsai 2 (0.7%) + Prasanth Babu Mantena 2 (0.7%) + Guillaume La Roque 2 (0.7%) + Venkatesh Yadav Abbarapu 2 (0.7%) + Caleb Connolly 1 (0.3%) + Lad Prabhakar 1 (0.3%) + Hiago De Franco 1 (0.3%) + Mikhail Kshevetskiy 1 (0.3%) + Francesco Dolcini 1 (0.3%) + Chris Paterson 1 (0.3%) + T Karthik Reddy 1 (0.3%) + Srinivas Goud 1 (0.3%) + Shawn Guo 1 (0.3%) + Jackson Cooper-Driver 1 (0.3%) + Cody Schuffelen 1 (0.3%) + Jayesh Choudhary 1 (0.3%) + Ian Roberts 1 (0.3%) + Wei Liang Lim 1 (0.3%) + Andreas Dannenberg 1 (0.3%) + Vignesh Raghavendra 1 (0.3%) + Benjamin SzÅ‘ke 1 (0.3%) + Jernej Skrabec 1 (0.3%) + Francis Laniel 1 (0.3%) + Daniel Schultz 1 (0.3%) + Kishon Vijay Abraham I 1 (0.3%) + William Zhang 1 (0.3%) + Heinrich Schuchardt 1 (0.3%) + Ye Li 1 (0.3%) + ==================================== ===== + + +.. table:: Developers with the most reviews (total 1015) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 195 (19.2%) + Ilias Apalodimas 103 (10.1%) + Tom Rini 62 (6.1%) + Mattijs Korpershoek 57 (5.6%) + Kever Yang 57 (5.6%) + Marek Vasut 39 (3.8%) + Leo Yu-Chi Liang 36 (3.5%) + Peng Fan 30 (3.0%) + Neil Armstrong 30 (3.0%) + Quentin Schulz 30 (3.0%) + Stefan Roese 28 (2.8%) + Heiko Schocher 26 (2.6%) + Peter Robinson 25 (2.5%) + Heinrich Schuchardt 24 (2.4%) + Patrick Delaunay 21 (2.1%) + Caleb Connolly 19 (1.9%) + Fabio Estevam 15 (1.5%) + Michael Nazzareno Trimarchi 12 (1.2%) + William Zhang 11 (1.1%) + Sumit Garg 11 (1.1%) + Sean Anderson 11 (1.1%) + Jaehoon Chung 10 (1.0%) + Neha Malcom Francis 10 (1.0%) + Aniket Limaye 9 (0.9%) + Michal Simek 8 (0.8%) + Alexander Sverdlin 8 (0.8%) + Jerome Forissier 8 (0.8%) + Jonas Karlman 6 (0.6%) + Ye Li 6 (0.6%) + Tudor Ambarus 6 (0.6%) + Patrice Chotard 6 (0.6%) + Miquel Raynal 5 (0.5%) + Moritz Fischer 5 (0.5%) + Bryan Brattlof 5 (0.5%) + Love Kumar 5 (0.5%) + Andre Przywara 4 (0.4%) + Paul Kocialkowski 4 (0.4%) + Anand Gore 4 (0.4%) + Pratyush Yadav 4 (0.4%) + Florian Fainelli 4 (0.4%) + Linus Walleij 3 (0.3%) + Guillaume La Roque 3 (0.3%) + Paul Barker 3 (0.3%) + Daniel Golle 3 (0.3%) + Dhruva Gole 3 (0.3%) + Venkatesh Yadav Abbarapu 2 (0.2%) + Andrew Davis 2 (0.2%) + david regan 2 (0.2%) + Roger Quadros 2 (0.2%) + Heiko Thiery 2 (0.2%) + Dragan Simic 2 (0.2%) + Jagan Teki 2 (0.2%) + Udit Kumar 2 (0.2%) + Siddharth Vadapalli 1 (0.1%) + Leo Yan 1 (0.1%) + Francesco Dolcini 1 (0.1%) + Jayesh Choudhary 1 (0.1%) + Vignesh Raghavendra 1 (0.1%) + Andy Shevchenko 1 (0.1%) + Tony Dinh 1 (0.1%) + Frieder Schrempf 1 (0.1%) + Qu Wenruo 1 (0.1%) + Igor Opaniuk 1 (0.1%) + Christoph Niedermaier 1 (0.1%) + Andrew Lunn 1 (0.1%) + Patrick Wildt 1 (0.1%) + Aurelien Jarno 1 (0.1%) + Kamal Dasu 1 (0.1%) + Julien Masson 1 (0.1%) + Hari Prasath Gujulan Elango 1 (0.1%) + Jacky Cao 1 (0.1%) + Toyama, Yoshihiro 1 (0.1%) + Andrejs Cainikovs 1 (0.1%) + Padmarao Begari 1 (0.1%) + Benjamin Hahn 1 (0.1%) + Tim Harvey 1 (0.1%) + Sughosh Ganu 1 (0.1%) + Raymond Mao 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most test credits (total 164) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 23 (14.0%) + Julius Lehmann 17 (10.4%) + Uwe Kleine-König 14 (8.5%) + Venkatesh Yadav Abbarapu 13 (7.9%) + Derald D. Woods 12 (7.3%) + Michal Simek 9 (5.5%) + Mattijs Korpershoek 8 (4.9%) + Caleb Connolly 7 (4.3%) + Guillaume La Roque 6 (3.7%) + Soeren Moch 5 (3.0%) + Anand Moon 5 (3.0%) + Frank Wunderlich 4 (2.4%) + Chris Morgan 4 (2.4%) + Ilias Apalodimas 3 (1.8%) + Daniel Golle 3 (1.8%) + Quentin Schulz 2 (1.2%) + Heiko Schocher 2 (1.2%) + Patrick Delaunay 2 (1.2%) + Patrice Chotard 2 (1.2%) + Heiko Thiery 2 (1.2%) + Loic Devulder 2 (1.2%) + Adam Ford 2 (1.2%) + Javier Fernandez Pastrana 2 (1.2%) + Vaishnav Achath 2 (1.2%) + Neil Armstrong 1 (0.6%) + Fabio Estevam 1 (0.6%) + William Zhang 1 (0.6%) + Sughosh Ganu 1 (0.6%) + Johan Jonker 1 (0.6%) + E Shattow 1 (0.6%) + Enric Balletbo i Serra 1 (0.6%) + Ryan Walklin 1 (0.6%) + Teresa Remmet 1 (0.6%) + Andreas Schwab 1 (0.6%) + Andrew Goodbody 1 (0.6%) + Jonathan Humphreys 1 (0.6%) + Gilles Talis 1 (0.6%) + ==================================== ===== + + +.. table:: Developers who gave the most tested-by credits (total 164) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Neil Armstrong 23 (14.0%) + Simon Glass 21 (12.8%) + Heiko Stuebner 14 (8.5%) + Paul Kocialkowski 13 (7.9%) + Bhupesh Sharma 12 (7.3%) + Sughosh Ganu 10 (6.1%) + Sebastian Reichel 10 (6.1%) + Dmitry Rokosov 9 (5.5%) + Marek Vasut 8 (4.9%) + Heinrich Schuchardt 6 (3.7%) + Jerome Forissier 4 (2.4%) + Jernej Skrabec 4 (2.4%) + Weijie Gao 4 (2.4%) + Christian Marangi 4 (2.4%) + Peng Fan 2 (1.2%) + Nam Cao 2 (1.2%) + Michael Walle 2 (1.2%) + Sam Protsenko 2 (1.2%) + Tom Rini 1 (0.6%) + Venkatesh Yadav Abbarapu 1 (0.6%) + Caleb Connolly 1 (0.6%) + Chris Morgan 1 (0.6%) + Ilias Apalodimas 1 (0.6%) + William Zhang 1 (0.6%) + Jonas Karlman 1 (0.6%) + Prasanth Babu Mantena 1 (0.6%) + Mark Kettenis 1 (0.6%) + Lukasz Majewski 1 (0.6%) + Ion Agorria 1 (0.6%) + Tomas Paukrt 1 (0.6%) + Rasmus Villemoes 1 (0.6%) + Dmitrii Merkurev 1 (0.6%) + ==================================== ===== + + +.. table:: Developers with the most report credits (total 32) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 5 (15.6%) + Simon Glass 3 (9.4%) + Patrick Delaunay 3 (9.4%) + Heinrich Schuchardt 2 (6.2%) + Ilias Apalodimas 2 (6.2%) + Jonas Karlman 1 (3.1%) + Mattijs Korpershoek 1 (3.1%) + Patrice Chotard 1 (3.1%) + Heiko Thiery 1 (3.1%) + Vaishnav Achath 1 (3.1%) + E Shattow 1 (3.1%) + Enric Balletbo i Serra 1 (3.1%) + Gilles Talis 1 (3.1%) + Leo Yu-Chi Liang 1 (3.1%) + Michael Nazzareno Trimarchi 1 (3.1%) + Conor Dooley 1 (3.1%) + Vinh Nguyen 1 (3.1%) + João Paulo Gonçalves 1 (3.1%) + Adriano Cordova 1 (3.1%) + Rudi Heitbaum 1 (3.1%) + kernel test robot 1 (3.1%) + Alexander Dahl 1 (3.1%) + ==================================== ===== + + +.. table:: Developers who gave the most report credits (total 32) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Jerome Forissier 7 (21.9%) + Heinrich Schuchardt 6 (18.8%) + Marek Vasut 4 (12.5%) + Ilias Apalodimas 3 (9.4%) + Tom Rini 1 (3.1%) + Simon Glass 1 (3.1%) + Sughosh Ganu 1 (3.1%) + Peng Fan 1 (3.1%) + Michael Walle 1 (3.1%) + Michal Simek 1 (3.1%) + Quentin Schulz 1 (3.1%) + Geert Uytterhoeven 1 (3.1%) + Markus Volk 1 (3.1%) + Eva Kurchatova 1 (3.1%) + Devarsh Thakkar 1 (3.1%) + Yasuharu Shibata 1 (3.1%) + ==================================== ===== + + +.. table:: Top changeset contributors by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 576 (32.6%) + Google LLC 355 (20.1%) + Linaro 314 (17.8%) + DENX Software Engineering 96 (5.4%) + AMD 78 (4.4%) + Renesas Electronics 67 (3.8%) + NXP 47 (2.7%) + Texas Instruments 47 (2.7%) + Konsulko Group 33 (1.9%) + Phytec 25 (1.4%) + Analog Devices 21 (1.2%) + ST Microelectronics 14 (0.8%) + ARM 13 (0.7%) + Siemens 12 (0.7%) + Toradex 11 (0.6%) + BayLibre SAS 10 (0.6%) + Bootlin 10 (0.6%) + Broadcom 10 (0.6%) + Collabora Ltd. 10 (0.6%) + Intel 8 (0.5%) + Amarula Solutions 3 (0.2%) + linutronix 2 (0.1%) + SUSE 2 (0.1%) + Sony 1 (0.1%) + Debian.org 1 (0.1%) + Digi International 1 (0.1%) + Marvell 1 (0.1%) + ==================================== ===== + + +.. table:: Top lines changed by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Konsulko Group 929361 (86.0%) + (Unknown) 52999 (4.9%) + Linaro 20228 (1.9%) + Google LLC 18362 (1.7%) + DENX Software Engineering 13574 (1.3%) + NXP 9551 (0.9%) + Texas Instruments 8545 (0.8%) + Renesas Electronics 7339 (0.7%) + Collabora Ltd. 5315 (0.5%) + AMD 3772 (0.3%) + ARM 3416 (0.3%) + Broadcom 2937 (0.3%) + Analog Devices 1930 (0.2%) + Siemens 1458 (0.1%) + Bootlin 393 (0.0%) + Phytec 329 (0.0%) + BayLibre SAS 172 (0.0%) + Amarula Solutions 100 (0.0%) + Intel 87 (0.0%) + ST Microelectronics 80 (0.0%) + Toradex 72 (0.0%) + Marvell 39 (0.0%) + Digi International 32 (0.0%) + Sony 8 (0.0%) + linutronix 7 (0.0%) + SUSE 6 (0.0%) + Debian.org 3 (0.0%) + ==================================== ===== + + +.. table:: Employers with the most signoffs (total 307) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 63 (20.5%) + Samsung 41 (13.4%) + Linaro 36 (11.7%) + AMD 36 (11.7%) + BayLibre SAS 36 (11.7%) + NXP 28 (9.1%) + Texas Instruments 23 (7.5%) + ARM 6 (2.0%) + Siemens 6 (2.0%) + Bootlin 6 (2.0%) + Toradex 6 (2.0%) + Konsulko Group 5 (1.6%) + Google LLC 4 (1.3%) + Renesas Electronics 4 (1.3%) + Rockchip 2 (0.7%) + Broadcom 1 (0.3%) + Phytec 1 (0.3%) + Amarula Solutions 1 (0.3%) + Canonical 1 (0.3%) + Xilinx 1 (0.3%) + ==================================== ===== + + +.. table:: Employers with the most hackers (total 206) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 107 (51.9%) + Linaro 15 (7.3%) + Texas Instruments 15 (7.3%) + AMD 9 (4.4%) + NXP 6 (2.9%) + Toradex 6 (2.9%) + DENX Software Engineering 6 (2.9%) + ARM 5 (2.4%) + Phytec 5 (2.4%) + Renesas Electronics 4 (1.9%) + BayLibre SAS 3 (1.5%) + Siemens 3 (1.5%) + Google LLC 3 (1.5%) + Bootlin 2 (1.0%) + Broadcom 2 (1.0%) + Amarula Solutions 2 (1.0%) + Collabora Ltd. 2 (1.0%) + ST Microelectronics 2 (1.0%) + Konsulko Group 1 (0.5%) + Analog Devices 1 (0.5%) + Intel 1 (0.5%) + Marvell 1 (0.5%) + Digi International 1 (0.5%) + Sony 1 (0.5%) + linutronix 1 (0.5%) + SUSE 1 (0.5%) + Debian.org 1 (0.5%) + ==================================== ===== diff --git a/doc/usage/cmd/optee.rst b/doc/usage/cmd/optee.rst new file mode 100644 index 00000000000..46c569a105f --- /dev/null +++ b/doc/usage/cmd/optee.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. index:: + single: optee (command) + +optee command +============= + +Synopsis +-------- + +:: + + optee hello + optee hello <value> + +Description +----------- + +This is an OP-TEE sanity test which invokes the "Hello World" +Trusted Application (TA). The TA does two things: +- It prints debug and information messages to the secure console (if logging is enabled) +- It increments the integer value passed as a parameter and returns it + + +value + Integer value that the TA is expected to increment and return. + The default value is 0. + +To enable the OP-TEE Hello World example please refer +https://optee.readthedocs.io/en/latest/building/gits/optee_examples/optee_examples.html + +Examples +-------- + +:: + + ==> optee hello + D/TA: TA_CreateEntryPoint:39 has been called + I/TA: Hello World! + Value before: 0x0 + Calling TA + D/TA: inc_value:105 has been called + I/TA: Got value: 0 from NW + I/TA: Increase value to: 1 + Value after: 0x1 + I/TA: Goodbye! + D/TA: TA_DestroyEntryPoint:50 has been called + + ==> optee hello 74 + D/TA: TA_CreateEntryPoint:39 has been called + I/TA: Hello World! + Value before: 0x74 + Calling TA + D/TA: inc_value:105 has been called + I/TA: Got value: 116 from NW + I/TA: Increase value to: 117 + Value after: 0x75 + I/TA: Goodbye! + D/TA: TA_DestroyEntryPoint:50 has been called + +Configuration +------------- + +The optee command is enabled by CONFIG_OPTEE=y and CONFIG_CMD_OPTEE=y. + +Return value +------------ + +The return value $? is 0 (true) if the command succeeds, 1 (false) otherwise. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index cb7a23f1170..4dd00f002cd 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -92,6 +92,7 @@ Shell commands cmd/msr cmd/mtest cmd/mtrr + cmd/optee cmd/panic cmd/part cmd/pause diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 43c44fadbe7..a4ff1c41abb 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -903,11 +903,11 @@ static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *pa int ret; /* - * If the requested parent is in the same clock-controller and - * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal - * clock. + * If the requested parent is in the same clock-controller the + * likely parent is the unexported SCLK_MAC_PLL ("mac_pll_src"), + * switch to the internal clock. */ - if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { + if (parent->dev == clk->dev) { debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); return 0; diff --git a/drivers/core/root.c b/drivers/core/root.c index c7fb58285ca..15b8c83fee9 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -288,26 +288,40 @@ void *dm_priv_to_rw(void *priv) } #endif -static int dm_probe_devices(struct udevice *dev, bool pre_reloc_only) +/** + * dm_probe_devices() - Check whether to probe a device and all children + * + * Probes the device if DM_FLAG_PROBE_AFTER_BIND is enabled for it. Then scans + * all its children recursively to do the same. + * + * @dev: Device to (maybe) probe + * Return 0 if OK, -ve on error + */ +static int dm_probe_devices(struct udevice *dev) { - ofnode node = dev_ofnode(dev); struct udevice *child; - int ret; - - if (pre_reloc_only && - (!ofnode_valid(node) || !ofnode_pre_reloc(node)) && - !(dev->driver->flags & DM_FLAG_PRE_RELOC)) - goto probe_children; if (dev_get_flags(dev) & DM_FLAG_PROBE_AFTER_BIND) { + int ret; + ret = device_probe(dev); if (ret) return ret; } -probe_children: list_for_each_entry(child, &dev->child_head, sibling_node) - dm_probe_devices(child, pre_reloc_only); + dm_probe_devices(child); + + return 0; +} + +int dm_autoprobe(void) +{ + int ret; + + ret = dm_probe_devices(gd->dm_root); + if (ret) + return log_msg_ret("pro", ret); return 0; } @@ -344,7 +358,7 @@ static int dm_scan(bool pre_reloc_only) if (ret) return ret; - return dm_probe_devices(gd->dm_root, pre_reloc_only); + return 0; } int dm_init_and_scan(bool pre_reloc_only) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index dac4023ccfd..3013c4741d0 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1331,6 +1331,8 @@ static int udma_get_mmrs(struct udevice *dev) continue; if (i == MMR_RCHANRT && ud->rchan_cnt == 0) continue; + if (i == MMR_RFLOW && ud->match_data->type == DMA_TYPE_BCDMA) + continue; ud->mmrs[i] = dev_read_addr_name_ptr(dev, mmr_names[i]); if (!ud->mmrs[i]) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6009d55f400..da84b35e804 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -568,7 +568,7 @@ config QFW_MMIO config QFW_SMBIOS bool default y - depends on QFW && SMBIOS && !SANDBOX + depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS help Hidden option to read SMBIOS tables from QEMU. diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index c3490db2a08..57d470521fc 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -74,7 +74,7 @@ static const struct udevice_id tps65941_ids[] = { { .compatible = "ti,tps659412", .data = TPS659411 }, { .compatible = "ti,tps659413", .data = TPS659413 }, { .compatible = "ti,lp876441", .data = LP876441 }, - { .compatible = "ti,tps65224", .data = TPS65224 }, + { .compatible = "ti,tps65224-q1", .data = TPS65224 }, { .compatible = "ti,tps6594-q1", .data = TPS659411 }, { .compatible = "ti,tps6593-q1", .data = TPS659413 }, { .compatible = "ti,lp8764-q1", .data = LP876441 }, diff --git a/drivers/power/regulator/tps65219_regulator.c b/drivers/power/regulator/tps65219_regulator.c index b7124fed024..88abc896b3a 100644 --- a/drivers/power/regulator/tps65219_regulator.c +++ b/drivers/power/regulator/tps65219_regulator.c @@ -72,12 +72,12 @@ static int tps65219_buck_enable(struct udevice *dev, int op, bool *enable) static int tps65219_buck_volt2val(int uV) { - if (uV > TPS65219_BUCK_VOLT_MAX) + if (uV > TPS65219_BUCK_3V4) return -EINVAL; - else if (uV >= 1400000) - return (uV - 1400000) / 100000 + 0x20; - else if (uV >= 600000) - return (uV - 600000) / 25000 + 0x00; + else if (uV >= TPS65219_BUCK_1V4) + return (uV - TPS65219_BUCK_1V4) / TPS65219_VOLT_STEP_100MV + TPS65219_BUCK_REG_1V4; + else if (uV >= TPS65219_BUCK_0V6) + return (uV - TPS65219_BUCK_0V6) / TPS65219_VOLT_STEP_25MV + TPS65219_BUCK_REG_0V6; else return -EINVAL; } @@ -86,12 +86,12 @@ static int tps65219_buck_val2volt(int val) { if (val > TPS65219_VOLT_MASK) return -EINVAL; - else if (val > 0x34) - return TPS65219_BUCK_VOLT_MAX; - else if (val > 0x20) - return 1400000 + (val - 0x20) * 100000; - else if (val >= 0) - return 600000 + val * 25000; + else if (val > TPS65219_BUCK_REG_3V4) + return TPS65219_BUCK_3V4; + else if (val > TPS65219_BUCK_REG_1V4) + return TPS65219_BUCK_1V4 + (val - TPS65219_BUCK_REG_1V4) * TPS65219_VOLT_STEP_100MV; + else if (val >= TPS65219_BUCK_REG_0V6) + return TPS65219_BUCK_0V6 + val * TPS65219_VOLT_STEP_25MV; else return -EINVAL; } @@ -161,7 +161,7 @@ static int tps65219_ldo_volt2val(int idx, int uV) if (uV > max) return -EINVAL; else if (uV >= base) - return (uV - TPS65219_LDO12_VOLT_MIN) / 50000; + return (uV - TPS65219_LDO12_VOLT_MIN) / TPS65219_VOLT_STEP_50MV; else return -EINVAL; } @@ -187,7 +187,7 @@ static int tps65219_ldo_val2volt(int idx, int val) else if (val <= reg_base) return base; else if (val >= 0) - return TPS65219_LDO12_VOLT_MIN + (50000 * val); + return TPS65219_LDO12_VOLT_MIN + (TPS65219_VOLT_STEP_50MV * val); else return -EINVAL; } @@ -250,7 +250,7 @@ static int tps65219_ldo_probe(struct udevice *dev) /* idx must be in 1..TPS65219_LDO_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_LDO_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } @@ -271,7 +271,7 @@ static int tps65219_buck_probe(struct udevice *dev) /* idx must be in 1..TPS65219_BUCK_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_BUCK_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 9c2d1398247..6467f20422b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -294,7 +294,7 @@ config RTC_DAVINCI config RTC_ZYNQMP bool "Enable ZynqMP RTC driver" - depends on ARCH_ZYNQMP + depends on DM_RTC && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 4251bf28cd3..2a095d0c58e 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -255,7 +255,7 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) GQSPI_GFIFO_CS_LOWER | GQSPI_GFIFO_CS_UPPER; else - debug("Wrong Bus selection:0x%x\n", priv->bus); + log_debug("Wrong Bus selection:0x%x\n", priv->bus); } else { if (priv->u_page) gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c index d39720958f0..af54fe87596 100644 --- a/drivers/sysinfo/sandbox.c +++ b/drivers/sysinfo/sandbox.c @@ -13,6 +13,7 @@ struct sysinfo_sandbox_priv { bool called_detect; int test_i1; int test_i2; + u32 test_data[2]; }; char vacation_spots[][64] = {"R'lyeh", "Dreamlands", "Plateau of Leng", @@ -24,6 +25,8 @@ int sysinfo_sandbox_detect(struct udevice *dev) priv->called_detect = true; priv->test_i2 = 100; + priv->test_data[0] = 0xabcdabcd; + priv->test_data[1] = 0xdeadbeef; return 0; } @@ -79,6 +82,21 @@ int sysinfo_sandbox_get_str(struct udevice *dev, int id, size_t size, char *val) return -ENOENT; } +int sysinfo_sandbox_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_sandbox_priv *priv = dev_get_priv(dev); + + switch (id) { + case DATA_TEST: + *buf = priv->test_data; + *size = sizeof(priv->test_data); + return 0; + } + + return -ENOENT; +} + static const struct udevice_id sysinfo_sandbox_ids[] = { { .compatible = "sandbox,sysinfo-sandbox" }, { /* sentinel */ } @@ -89,6 +107,7 @@ static const struct sysinfo_ops sysinfo_sandbox_ops = { .get_bool = sysinfo_sandbox_get_bool, .get_int = sysinfo_sandbox_get_int, .get_str = sysinfo_sandbox_get_str, + .get_data = sysinfo_sandbox_get_data, }; int sysinfo_sandbox_probe(struct udevice *dev) diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index a7cbac0ce18..47b7f5ef9fe 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -9,4 +9,5 @@ enum { INT_TEST1, INT_TEST2, STR_VACATIONSPOT, + DATA_TEST, }; diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index a7ac8e3f072..99104274f72 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -5,14 +5,240 @@ */ #include <dm.h> +#include <smbios_plat.h> #include <sysinfo.h> +/* platform information storage */ +struct processor_info processor_info; +struct cache_info cache_info[SYSINFO_CACHE_LVL_MAX]; +struct sysinfo_plat sysinfo_smbios_p = { + /* Processor Information */ + .processor = &processor_info, + /* Cache Information */ + .cache = &cache_info[0], +}; + +/* structure for smbios private data storage */ +struct sysinfo_plat_priv { + struct processor_info *t4; + struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; + u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; + u8 cache_level; +}; + +static void smbios_cache_info_dump(struct smbios_type7 *cache_info) +{ + log_debug("SMBIOS Type 7 (Cache Information):\n"); + log_debug("Cache Configuration: 0x%04x\n", cache_info->config.data); + log_debug("Maximum Cache Size: %u KB\n", cache_info->max_size.data); + log_debug("Installed Size: %u KB\n", cache_info->inst_size.data); + log_debug("Supported SRAM Type: 0x%04x\n", + cache_info->supp_sram_type.data); + log_debug("Current SRAM Type: 0x%04x\n", + cache_info->curr_sram_type.data); + log_debug("Cache Speed: %u\n", cache_info->speed); + log_debug("Error Correction Type: %u\n", cache_info->err_corr_type); + log_debug("System Cache Type: %u\n", cache_info->sys_cache_type); + log_debug("Associativity: %u\n", cache_info->associativity); + log_debug("Maximum Cache Size 2: %u KB\n", cache_info->max_size2.data); + log_debug("Installed Cache Size 2: %u KB\n", + cache_info->inst_size2.data); +} + +/* weak function for the platforms not yet supported */ +__weak int sysinfo_get_cache_info(u8 level, struct cache_info *cache_info) +{ + return -ENOSYS; +} + +__weak int sysinfo_get_processor_info(struct processor_info *pinfo) +{ + return -ENOSYS; +} + +void sysinfo_cache_info_default(struct cache_info *ci) +{ + memset(ci, 0, sizeof(*ci)); + ci->config.data = SMBIOS_CACHE_LOCATE_UNKNOWN | SMBIOS_CACHE_OP_UND; + ci->supp_sram_type.fields.unknown = 1; + ci->curr_sram_type.fields.unknown = 1; + ci->speed = SMBIOS_CACHE_SPEED_UNKNOWN; + ci->err_corr_type = SMBIOS_CACHE_ERRCORR_UNKNOWN; + ci->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN; +} + +static int sysinfo_plat_detect(struct udevice *dev) +{ + return 0; +} + +static int sysinfo_plat_get_str(struct udevice *dev, int id, + size_t size, char *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + const char *str = NULL; + + switch (id) { + case SYSID_SM_PROCESSOR_MANUFACT: + str = priv->t4->manufacturer; + break; + default: + break; + } + + if (!str) + return -ENOSYS; + + strlcpy(val, str, size); + + return 0; +} + +static int sysinfo_plat_get_int(struct udevice *dev, int id, int *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + u8 i; + + if (id >= SYSID_SM_CACHE_INFO_START && + id <= SYSID_SM_CACHE_INFO_END) { + /* For smbios type 7 */ + for (i = 0; i < priv->cache_level; i++) { + switch (id - i) { + case SYSID_SM_CACHE_MAX_SIZE: + *val = priv->t7[i].max_size.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE: + *val = priv->t7[i].inst_size.data; + return 0; + case SYSID_SM_CACHE_SCACHE_TYPE: + *val = priv->t7[i].sys_cache_type; + return 0; + case SYSID_SM_CACHE_ASSOC: + *val = priv->t7[i].associativity; + return 0; + case SYSID_SM_CACHE_MAX_SIZE2: + *val = priv->t7[i].max_size2.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE2: + *val = priv->t7[i].inst_size2.data; + return 0; + default: + break; + } + } + return -ENOSYS; + } + + switch (id) { + case SYSID_SM_PROCESSOR_CORE_CNT: + *val = priv->t4->core_count; + break; + case SYSID_SM_PROCESSOR_CORE_EN: + *val = priv->t4->core_enabled; + break; + case SYSID_SM_PROCESSOR_CHARA: + *val = priv->t4->characteristics; + break; + case SYSID_SM_CACHE_LEVEL: + if (!priv->cache_level) /* No cache detected */ + return -ENOSYS; + *val = priv->cache_level - 1; + break; + default: + return -ENOSYS; + } + + return 0; +} + +static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_SM_PROCESSOR_ID: + *buf = priv->t4->id; + *size = sizeof(priv->t4->id); + break; + case SYSID_SM_CACHE_HANDLE: + *buf = &priv->cache_handles[0]; + *size = sizeof(priv->cache_handles); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int sysinfo_plat_probe(struct udevice *dev) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + struct sysinfo_plat *plat = &sysinfo_smbios_p; + u8 level; + + if (!sysinfo_get_processor_info(plat->processor)) + priv->t4 = plat->processor; + + for (level = 0; level < SYSINFO_CACHE_LVL_MAX; level++) { + struct cache_info *pcache = plat->cache + level; + + if (sysinfo_get_cache_info(level, pcache)) + break; /* no more levels */ + + /* + * Fill in the SMBIOS type 7 structure, + * skip the header members (type, length, handle), + * and the ones in DT smbios node. + */ + priv->t7[level].sys_cache_type = pcache->cache_type; + priv->t7[level].associativity = pcache->associativity; + + if (pcache->max_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].max_size.data = 0xFFFF; + priv->t7[level].max_size2.fields.size = + pcache->max_size / 64; + priv->t7[level].max_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].max_size.fields.size = pcache->max_size; + priv->t7[level].max_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].max_size2.data = 0; + } + if (pcache->inst_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].inst_size.data = 0xFFFF; + priv->t7[level].inst_size2.fields.size = + pcache->inst_size / 64; + priv->t7[level].inst_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].inst_size.fields.size = + pcache->inst_size; + priv->t7[level].inst_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].inst_size2.data = 0; + } + smbios_cache_info_dump(&priv->t7[level]); + } + if (!level) /* no cache detected */ + return -ENOSYS; + + priv->cache_level = level; + + return 0; +} + static const struct udevice_id sysinfo_smbios_ids[] = { { .compatible = "u-boot,sysinfo-smbios" }, { /* sentinel */ } }; static const struct sysinfo_ops sysinfo_smbios_ops = { + .detect = sysinfo_plat_detect, + .get_str = sysinfo_plat_get_str, + .get_int = sysinfo_plat_get_int, + .get_data = sysinfo_plat_get_data, }; U_BOOT_DRIVER(sysinfo_smbios) = { @@ -20,4 +246,6 @@ U_BOOT_DRIVER(sysinfo_smbios) = { .id = UCLASS_SYSINFO, .of_match = sysinfo_smbios_ids, .ops = &sysinfo_smbios_ops, + .priv_auto = sizeof(struct sysinfo_plat_priv), + .probe = sysinfo_plat_probe, }; diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index d77d1e3ee44..3c0cd51273e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -99,6 +99,26 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val) return ops->get_str(dev, id, size, val); } +int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_priv *priv; + struct sysinfo_ops *ops; + + if (!dev) + return -ENOSYS; + + priv = dev_get_uclass_priv(dev); + ops = sysinfo_get_ops(dev); + + if (!priv->detected) + return -EPERM; + + if (!ops->get_data) + return -ENOSYS; + + return ops->get_data(dev, id, data, size); +} + UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 24786a2bc91..a656265890e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -217,14 +217,14 @@ config USB_EHCI_MX6 Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 - bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 || IMX8M || IMX93 + bool "Support for i.MX7/i.MX8M/i.MX9 on-chip EHCI USB controller" + depends on ARCH_MX7 || IMX8M || IMX93 || IMX95 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 - select PHY if IMX8M || IMX93 - select NOP_PHY if IMX8M || IMX93 + select PHY if IMX8M || IMX93 || IMX95 + select NOP_PHY if IMX8M || IMX93 || IMX95 default y ---help--- - Enables support for the on-chip EHCI controller on i.MX7 SoCs. + Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs. config USB_EHCI_MXS bool "Support for i.MX23/i.MX28 EHCI USB controller" diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index d8f521befe1..1392d29bc13 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -287,9 +287,9 @@ static int ehci_usb_probe(struct udevice *dev) debug("%s: No vbus supply\n", dev->name); if (!ret && priv->vbus_supply) { - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret) { puts("Error enabling VBUS supply\n"); return ret; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a93fa5d5455..a8748cef7ad 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -479,9 +479,9 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { int ret; - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret && ret != -ENOSYS) { printf("Error enabling VBUS supply (ret=%i)\n", ret); return ret; diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 99168d0cad0..7b387266b99 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -131,18 +131,19 @@ static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) u32 timer_margin; int ret; - if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY) + timer_margin = timeout_ms * priv->clk_hz / 1000; + timer_margin >>= WDT_PRELOAD_SHIFT; + if (timer_margin > WDT_PRELOAD_MAX) + timer_margin = WDT_PRELOAD_MAX; + + if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY && + readl(priv->regs + RTIDWDPRLD) != timer_margin) return -EBUSY; ret = rti_wdt_load_fw(dev); if (ret < 0) return ret; - timer_margin = timeout_ms * priv->clk_hz / 1000; - timer_margin >>= WDT_PRELOAD_SHIFT; - if (timer_margin > WDT_PRELOAD_MAX) - timer_margin = WDT_PRELOAD_MAX; - writel(timer_margin, priv->regs + RTIDWDPRLD); writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL); writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL); @@ -186,14 +187,6 @@ static int rti_wdt_probe(struct udevice *dev) priv->clk_hz = clk_get_rate(&clk); - /* - * If watchdog is running at 32k clock, it is not accurate. - * Adjust frequency down in this case so that it does not expire - * earlier than expected. - */ - if (priv->clk_hz < 32768) - priv->clk_hz = priv->clk_hz * 9 / 10; - return 0; } diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts new file mode 100644 index 00000000000..fb1f65c8688 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "FriendlyElec NanoPi R3S"; + compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + label = "reset"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + debounce-interval = <50>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>; + + power_led: led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + lan_led: led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + }; + + wan_led: led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb: regulator-vcc5v0_usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_usbc: regulator-vdd-usbc { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2_level3 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_reset_pin>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_reset_h: pcie-reset-h { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi index d1368418502..7f874c77410 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi @@ -1612,23 +1612,43 @@ pcie20x1 { /omit-if-no-ref/ - pcie20x1m0_pins: pcie20x1m0-pins { + pcie20x1m0_clkreqn: pcie20x1m0-clkreqn { rockchip,pins = /* pcie20x1_2_clkreqn_m0 */ - <3 RK_PC7 4 &pcfg_pull_none>, + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m0_perstn: pcie20x1m0-perstn { + rockchip,pins = /* pcie20x1_2_perstn_m0 */ - <3 RK_PD1 4 &pcfg_pull_none>, + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m0_waken: pcie20x1m0-waken { + rockchip,pins = /* pcie20x1_2_waken_m0 */ <3 RK_PD0 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie20x1m1_pins: pcie20x1m1-pins { + pcie20x1m1_clkreqn: pcie20x1m1-clkreqn { rockchip,pins = /* pcie20x1_2_clkreqn_m1 */ - <4 RK_PB7 4 &pcfg_pull_none>, + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_perstn: pcie20x1m1-perstn { + rockchip,pins = /* pcie20x1_2_perstn_m1 */ - <4 RK_PC1 4 &pcfg_pull_none>, + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_waken: pcie20x1m1-waken { + rockchip,pins = /* pcie20x1_2_waken_m1 */ <4 RK_PC0 4 &pcfg_pull_none>; }; @@ -1654,52 +1674,127 @@ pcie30x1 { /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { + pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn { rockchip,pins = /* pcie30x1_0_clkreqn_m0 */ - <0 RK_PC0 12 &pcfg_pull_none>, + <0 RK_PC0 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_0_perstn: pcie30x1m0-0-perstn { + rockchip,pins = /* pcie30x1_0_perstn_m0 */ - <0 RK_PC5 12 &pcfg_pull_none>, + <0 RK_PC5 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_0_waken: pcie30x1m0-0-waken { + rockchip,pins = /* pcie30x1_0_waken_m0 */ - <0 RK_PC4 12 &pcfg_pull_none>, + <0 RK_PC4 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn { + rockchip,pins = /* pcie30x1_1_clkreqn_m0 */ - <0 RK_PB5 12 &pcfg_pull_none>, + <0 RK_PB5 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_perstn: pcie30x1m0-1-perstn { + rockchip,pins = /* pcie30x1_1_perstn_m0 */ - <0 RK_PB7 12 &pcfg_pull_none>, + <0 RK_PB7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_waken: pcie30x1m0-1-waken { + rockchip,pins = /* pcie30x1_1_waken_m0 */ <0 RK_PB6 12 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { + pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn { rockchip,pins = /* pcie30x1_0_clkreqn_m1 */ - <4 RK_PA3 4 &pcfg_pull_none>, + <4 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_0_perstn: pcie30x1m1-0-perstn { + rockchip,pins = /* pcie30x1_0_perstn_m1 */ - <4 RK_PA5 4 &pcfg_pull_none>, + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_0_waken: pcie30x1m1-0-waken { + rockchip,pins = /* pcie30x1_0_waken_m1 */ - <4 RK_PA4 4 &pcfg_pull_none>, + <4 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn { + rockchip,pins = /* pcie30x1_1_clkreqn_m1 */ - <4 RK_PA0 4 &pcfg_pull_none>, + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_perstn: pcie30x1m1-1-perstn { + rockchip,pins = /* pcie30x1_1_perstn_m1 */ - <4 RK_PA2 4 &pcfg_pull_none>, + <4 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_waken: pcie30x1m1-1-waken { + rockchip,pins = /* pcie30x1_1_waken_m1 */ <4 RK_PA1 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { + pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn { rockchip,pins = /* pcie30x1_0_clkreqn_m2 */ - <1 RK_PB5 4 &pcfg_pull_none>, + <1 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_0_perstn: pcie30x1m2-0-perstn { + rockchip,pins = /* pcie30x1_0_perstn_m2 */ - <1 RK_PB4 4 &pcfg_pull_none>, + <1 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_0_waken: pcie30x1m2-0-waken { + rockchip,pins = /* pcie30x1_0_waken_m2 */ - <1 RK_PB3 4 &pcfg_pull_none>, + <1 RK_PB3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn { + rockchip,pins = /* pcie30x1_1_clkreqn_m2 */ - <1 RK_PA0 4 &pcfg_pull_none>, + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_perstn: pcie30x1m2-1-perstn { + rockchip,pins = /* pcie30x1_1_perstn_m2 */ - <1 RK_PA7 4 &pcfg_pull_none>, + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_waken: pcie30x1m2-1-waken { + rockchip,pins = /* pcie30x1_1_waken_m2 */ <1 RK_PA1 4 &pcfg_pull_none>; }; @@ -1721,45 +1816,85 @@ pcie30x2 { /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { + pcie30x2m0_clkreqn: pcie30x2m0-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m0 */ - <0 RK_PD1 12 &pcfg_pull_none>, + <0 RK_PD1 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m0_perstn: pcie30x2m0-perstn { + rockchip,pins = /* pcie30x2_perstn_m0 */ - <0 RK_PD4 12 &pcfg_pull_none>, + <0 RK_PD4 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m0_waken: pcie30x2m0-waken { + rockchip,pins = /* pcie30x2_waken_m0 */ <0 RK_PD2 12 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { + pcie30x2m1_clkreqn: pcie30x2m1-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m1 */ - <4 RK_PA6 4 &pcfg_pull_none>, + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_perstn: pcie30x2m1-perstn { + rockchip,pins = /* pcie30x2_perstn_m1 */ - <4 RK_PB0 4 &pcfg_pull_none>, + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_waken: pcie30x2m1-waken { + rockchip,pins = /* pcie30x2_waken_m1 */ <4 RK_PA7 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { + pcie30x2m2_clkreqn: pcie30x2m2-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m2 */ - <3 RK_PD2 4 &pcfg_pull_none>, + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_perstn: pcie30x2m2-perstn { + rockchip,pins = /* pcie30x2_perstn_m2 */ - <3 RK_PD4 4 &pcfg_pull_none>, + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_waken: pcie30x2m2-waken { + rockchip,pins = /* pcie30x2_waken_m2 */ <3 RK_PD3 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x2m3_pins: pcie30x2m3-pins { + pcie30x2m3_clkreqn: pcie30x2m3-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m3 */ - <1 RK_PD7 4 &pcfg_pull_none>, + <1 RK_PD7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_perstn: pcie30x2m3-perstn { + rockchip,pins = /* pcie30x2_perstn_m3 */ - <1 RK_PB7 4 &pcfg_pull_none>, + <1 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_waken: pcie30x2m3-waken { + rockchip,pins = /* pcie30x2_waken_m3 */ <1 RK_PB6 4 &pcfg_pull_none>; }; @@ -1774,45 +1909,85 @@ pcie30x4 { /omit-if-no-ref/ - pcie30x4m0_pins: pcie30x4m0-pins { + pcie30x4m0_clkreqn: pcie30x4m0-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m0 */ - <0 RK_PC6 12 &pcfg_pull_none>, + <0 RK_PC6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m0_perstn: pcie30x4m0-perstn { + rockchip,pins = /* pcie30x4_perstn_m0 */ - <0 RK_PD0 12 &pcfg_pull_none>, + <0 RK_PD0 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m0_waken: pcie30x4m0-waken { + rockchip,pins = /* pcie30x4_waken_m0 */ <0 RK_PC7 12 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x4m1_pins: pcie30x4m1-pins { + pcie30x4m1_clkreqn: pcie30x4m1-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m1 */ - <4 RK_PB4 4 &pcfg_pull_none>, + <4 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_perstn: pcie30x4m1-perstn { + rockchip,pins = /* pcie30x4_perstn_m1 */ - <4 RK_PB6 4 &pcfg_pull_none>, + <4 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_waken: pcie30x4m1-waken { + rockchip,pins = /* pcie30x4_waken_m1 */ <4 RK_PB5 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x4m2_pins: pcie30x4m2-pins { + pcie30x4m2_clkreqn: pcie30x4m2-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m2 */ - <3 RK_PC4 4 &pcfg_pull_none>, + <3 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_perstn: pcie30x4m2-perstn { + rockchip,pins = /* pcie30x4_perstn_m2 */ - <3 RK_PC6 4 &pcfg_pull_none>, + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_waken: pcie30x4m2-waken { + rockchip,pins = /* pcie30x4_waken_m2 */ <3 RK_PC5 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x4m3_pins: pcie30x4m3-pins { + pcie30x4m3_clkreqn: pcie30x4m3-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m3 */ - <1 RK_PB0 4 &pcfg_pull_none>, + <1 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_perstn: pcie30x4m3-perstn { + rockchip,pins = /* pcie30x4_perstn_m3 */ - <1 RK_PB2 4 &pcfg_pull_none>, + <1 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_waken: pcie30x4m3-waken { + rockchip,pins = /* pcie30x4_waken_m3 */ <1 RK_PB1 4 &pcfg_pull_none>; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi index fc67585b64b..a337f3fb837 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi @@ -1370,6 +1370,47 @@ status = "disabled"; }; + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfde80000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru CLK_HDMIHDP0>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy_hdmi0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in: port@0 { + reg = <0>; + }; + + hdmi0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts index 294b99dd50d..87fce8d9a96 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -310,7 +310,7 @@ }; &pcie2x1l2 { - pinctrl-0 = <&pcie20x1m0_pins>; + pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>; pinctrl-names = "default"; reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_wf>; @@ -328,6 +328,10 @@ pow_en: pow-en { rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; + + pcie2_reset: pcie2-reset { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; power { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts new file mode 100644 index 00000000000..9b14d5383cd --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts @@ -0,0 +1,920 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3588s.dtsi" + +/ { + model = "Radxa ROCK 5C"; + compatible = "radxa,rock-5c", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + dais = <&i2s0_8ch_p0>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = <LED_COLOR_ID_BLUE>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 10000 0>; + }; + + pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pow_en>; + regulator-name = "pcie2x1l2_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sysin>; + }; + + vcc5v_dcin: regulator-vcc5v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_3v3_pmu: regulator-vcc-3v3-pmu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_pwren_h>; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_sysin: regulator-vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_dcin>; + }; + + vcca: regulator-vcca { + compatible = "regulator-fixed"; + regulator-name = "vcca"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc_sysin>; + }; + + vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_wifi_pwr>; + regulator-name = "vdd_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s0>; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec + &hdmim1_tx0_hpd + &hdmim0_tx0_scl + &hdmim0_tx0_sda>; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <&vcc_3v3_pmu>; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + status = "okay"; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + }; +}; + +&i2c7 { + status = "okay"; + + audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn_m0>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie2x1l2_3v3>; + status = "okay"; +}; + +&pinctrl { + leds { + led_pins: led-pins { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mdio { + gmac1_rstn: gmac1-rstn { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pow_en: pow-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_wifi_pwr: usb-wifi-pwr { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_pwren_h: vcc-5v0-pwren-h { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc_sysin>; + vcc2-supply = <&vcc_sysin>; + vcc3-supply = <&vcc_sysin>; + vcc4-supply = <&vcc_sysin>; + vcc5-supply = <&vcc_sysin>; + vcc6-supply = <&vcc_sysin>; + vcc7-supply = <&vcc_sysin>; + vcc8-supply = <&vcc_sysin>; + vcc9-supply = <&vcc_sysin>; + vcc10-supply = <&vcc_sysin>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_sysin>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcca>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg3 { + regulator-name = "vdd_logic_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu_ddr_s3: dcdc-reg10 { + regulator-name = "vcc1v8_pmu_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg1 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg2 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_usb_otg0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc_5v0 */ + phy-supply = <&vcc_5v0>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/include/configs/khadas-edge2-rk3588s.h b/include/configs/khadas-edge2-rk3588s.h new file mode 100644 index 00000000000..d279cf3826a --- /dev/null +++ b/include/configs/khadas-edge2-rk3588s.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Khadas Technology Co., Ltd. + */ + +#ifndef __KHADAS_EDGE2_RK3588_H +#define __KHADAS_EDGE2_RK3588_H + +#include <configs/rk3588_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif /* __KHADAS_EDGE2_RK3588_H */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index c5bcd7dc5e8..76f40e7cd5f 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -20,16 +20,16 @@ #endif #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ + "scriptaddr=0x00c00000\0" \ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01e00000\0" \ - "fdtoverlay_addr_r=0x01f00000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x06000000\0" \ - "kernel_comp_addr_r=0x08000000\0" \ - "kernel_comp_size=0x2000000\0" + "pxefile_addr_r=0x00e00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "kernel_comp_addr_r=0x0a000000\0" \ + "fdt_addr_r=0x12000000\0" \ + "fdtoverlay_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12180000\0" \ + "kernel_comp_size=0x8000000\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rock-5c-rk3588s.h b/include/configs/rock-5c-rk3588s.h new file mode 100644 index 00000000000..0fd76c96f0c --- /dev/null +++ b/include/configs/rock-5c-rk3588s.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +#ifndef __ROCK_5C_RK3588S_H +#define __ROCK_5C_RK3588S_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __ROCK_5C_RK3588S_H */ diff --git a/include/dm/root.h b/include/dm/root.h index 5651b868c8b..286bd9a2ddd 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -137,6 +137,21 @@ int dm_scan_other(bool pre_reloc_only); int dm_init_and_scan(bool pre_reloc_only); /** + * dm_autoprobe() - Probe devices which are marked for probe-after-bind + * + * This probes all devices with a DM_FLAG_PROBE_AFTER_BIND flag. It checks the + * entire tree, so parent nodes need not have the flag set. + * + * It recursively probes parent nodes, so they do not need to have the flag + * set themselves. Since parents are always probed before children, if a child + * has the flag set, then its parent (and any devices up the chain to the root + * device) will be probed too. + * + * Return: 0 if OK, -ve on error + */ +int dm_autoprobe(void); + +/** * dm_init() - Initialise Driver Model structures * * This function will initialize roots of driver tree and class tree. diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h deleted file mode 100644 index 014eec58668..00000000000 --- a/include/dt-bindings/clock/rk3066a-cru.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H - -#include <dt-bindings/clock/rk3188-cru-common.h> - -/* soft-reset indices */ -#define SRST_SRST1 0 -#define SRST_SRST2 1 - -#define SRST_L2MEM 18 -#define SRST_I2S0 23 -#define SRST_I2S1 24 -#define SRST_I2S2 25 -#define SRST_TIMER2 29 - -#define SRST_GPIO4 36 -#define SRST_GPIO6 38 - -#define SRST_TSADC 92 - -#define SRST_HDMI 96 -#define SRST_HDMI_APB 97 -#define SRST_CIF1 111 - -#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h deleted file mode 100644 index afad90680fc..00000000000 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ /dev/null @@ -1,261 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H - -/* core clocks from */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define CORE_PERI 5 -#define CORE_L2C 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define SCLK_UART0 64 -#define SCLK_UART1 65 -#define SCLK_UART2 66 -#define SCLK_UART3 67 -#define SCLK_MAC 68 -#define SCLK_SPI0 69 -#define SCLK_SPI1 70 -#define SCLK_SARADC 71 -#define SCLK_SDMMC 72 -#define SCLK_SDIO 73 -#define SCLK_EMMC 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_SPDIF 78 -#define SCLK_CIF0 79 -#define SCLK_CIF1 80 -#define SCLK_OTGPHY0 81 -#define SCLK_OTGPHY1 82 -#define SCLK_HSADC 83 -#define SCLK_TIMER0 84 -#define SCLK_TIMER1 85 -#define SCLK_TIMER2 86 -#define SCLK_TIMER3 87 -#define SCLK_TIMER4 88 -#define SCLK_TIMER5 89 -#define SCLK_TIMER6 90 -#define SCLK_JTAG 91 -#define SCLK_SMC 92 -#define SCLK_TSADC 93 - -#define DCLK_LCDC0 190 -#define DCLK_LCDC1 191 - -/* aclk gates */ -#define ACLK_DMA1 192 -#define ACLK_DMA2 193 -#define ACLK_GPS 194 -#define ACLK_LCDC0 195 -#define ACLK_LCDC1 196 -#define ACLK_GPU 197 -#define ACLK_SMC 198 -#define ACLK_CIF1 199 -#define ACLK_IPP 200 -#define ACLK_RGA 201 -#define ACLK_CIF0 202 -#define ACLK_CPU 203 -#define ACLK_PERI 204 -#define ACLK_VEPU 205 -#define ACLK_VDPU 206 - -/* pclk gates */ -#define PCLK_GRF 320 -#define PCLK_PMU 321 -#define PCLK_TIMER0 322 -#define PCLK_TIMER1 323 -#define PCLK_TIMER2 324 -#define PCLK_TIMER3 325 -#define PCLK_PWM01 326 -#define PCLK_PWM23 327 -#define PCLK_SPI0 328 -#define PCLK_SPI1 329 -#define PCLK_SARADC 330 -#define PCLK_WDT 331 -#define PCLK_UART0 332 -#define PCLK_UART1 333 -#define PCLK_UART2 334 -#define PCLK_UART3 335 -#define PCLK_I2C0 336 -#define PCLK_I2C1 337 -#define PCLK_I2C2 338 -#define PCLK_I2C3 339 -#define PCLK_I2C4 340 -#define PCLK_GPIO0 341 -#define PCLK_GPIO1 342 -#define PCLK_GPIO2 343 -#define PCLK_GPIO3 344 -#define PCLK_GPIO4 345 -#define PCLK_GPIO6 346 -#define PCLK_EFUSE 347 -#define PCLK_TZPC 348 -#define PCLK_TSADC 349 -#define PCLK_CPU 350 -#define PCLK_PERI 351 -#define PCLK_DDRUPCTL 352 -#define PCLK_PUBL 353 - -/* hclk gates */ -#define HCLK_SDMMC 448 -#define HCLK_SDIO 449 -#define HCLK_EMMC 450 -#define HCLK_OTG0 451 -#define HCLK_EMAC 452 -#define HCLK_SPDIF 453 -#define HCLK_I2S0 454 -#define HCLK_I2S1 455 -#define HCLK_I2S2 456 -#define HCLK_OTG1 457 -#define HCLK_HSIC 458 -#define HCLK_HSADC 459 -#define HCLK_PIDF 460 -#define HCLK_LCDC0 461 -#define HCLK_LCDC1 462 -#define HCLK_ROM 463 -#define HCLK_CIF0 464 -#define HCLK_IPP 465 -#define HCLK_RGA 466 -#define HCLK_NANDC0 467 -#define HCLK_CPU 468 -#define HCLK_PERI 469 -#define HCLK_CIF1 470 -#define HCLK_VEPU 471 -#define HCLK_VDPU 472 -#define HCLK_HDMI 473 - -#define CLK_NR_CLKS (HCLK_HDMI + 1) - -/* soft-reset indices */ -#define SRST_MCORE 2 -#define SRST_CORE0 3 -#define SRST_CORE1 4 -#define SRST_MCORE_DBG 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE0_WDT 12 -#define SRST_CORE1_WDT 13 -#define SRST_STRC_SYS 14 -#define SRST_L2C 15 - -#define SRST_CPU_AHB 17 -#define SRST_AHB2APB 19 -#define SRST_DMA1 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_SPDIF 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_EFUSE 30 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 - -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_UART3 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_I2C4 47 - -#define SRST_PWM0 48 -#define SRST_PWM1 49 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU_ATB 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERI_AXI 57 -#define SRST_PERI_AHB 58 -#define SRST_PERI_APB 59 -#define SRST_PERI_NIU 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_SMC 65 -#define SRST_MAC 66 -#define SRST_NANC0 68 -#define SRST_USBOTG0 69 -#define SRST_USBPHY0 70 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_USBPHY1 73 -#define SRST_OTGC1 74 -#define SRST_HSADC 76 -#define SRST_PIDFILTER 77 -#define SRST_DDR_MSCH 79 - -#define SRST_TZPC 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_SPI1 85 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_APB 89 -#define SRST_DDRCTL 90 -#define SRST_DDRCTL_APB 91 -#define SRST_DDRPUB 93 - -#define SRST_VIO0_AXI 98 -#define SRST_VIO0_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_LCDC1_AXI 103 -#define SRST_LCDC1_AHB 104 -#define SRST_LCDC1_DCLK 105 -#define SRST_IPP_AXI 106 -#define SRST_IPP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_CIF0 110 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO1_AXI 114 -#define SRST_VCODEC_CPU 115 -#define SRST_VCODEC_NIU 116 -#define SRST_GPU 120 -#define SRST_GPU_NIU 122 -#define SRST_TFUN_ATB 125 -#define SRST_TFUN_APB 126 -#define SRST_CTI4_APB 127 - -#define SRST_TPIU_APB 128 -#define SRST_TRACE 129 -#define SRST_CORE_DBG 130 -#define SRST_DBG_APB 131 -#define SRST_CTI0 132 -#define SRST_CTI0_APB 133 -#define SRST_CTI1 134 -#define SRST_CTI1_APB 135 -#define SRST_PTM_CORE0 136 -#define SRST_PTM_CORE1 137 -#define SRST_PTM0 138 -#define SRST_PTM0_ATB 139 -#define SRST_PTM1 140 -#define SRST_PTM1_ATB 141 -#define SRST_CTM 142 -#define SRST_TS 143 - -#endif diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h deleted file mode 100644 index 1da306e1788..00000000000 --- a/include/dt-bindings/clock/rk3188-cru.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H - -#include <dt-bindings/clock/rk3188-cru-common.h> - -/* soft-reset indices */ -#define SRST_PTM_CORE2 0 -#define SRST_PTM_CORE3 1 -#define SRST_CORE2 5 -#define SRST_CORE3 6 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 - -#define SRST_TIMER2 16 -#define SRST_TIMER4 23 -#define SRST_I2S0 24 -#define SRST_TIMER5 25 -#define SRST_TIMER3 29 -#define SRST_TIMER6 31 - -#define SRST_PTM3 36 -#define SRST_PTM3_ATB 37 - -#define SRST_GPS 67 -#define SRST_HSICPHY 75 -#define SRST_TIMER 78 - -#define SRST_PTM2 92 -#define SRST_CORE2_WDT 94 -#define SRST_CORE3_WDT 95 - -#define SRST_PTM2_ATB 111 - -#define SRST_HSIC 117 -#define SRST_CTI2 118 -#define SRST_CTI2_APB 119 -#define SRST_GPU_BRIDGE 121 -#define SRST_CTI3 123 -#define SRST_CTI3_APB 124 - -#endif diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h deleted file mode 100644 index acf9f310ac5..00000000000 --- a/include/dt-bindings/power/rk3066-power.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ -#define __DT_BINDINGS_POWER_RK3066_POWER_H__ - -/* VD_CORE */ -#define RK3066_PD_A9_0 0 -#define RK3066_PD_A9_1 1 -#define RK3066_PD_DBG 4 -#define RK3066_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3066_PD_VIDEO 6 -#define RK3066_PD_VIO 7 -#define RK3066_PD_GPU 8 -#define RK3066_PD_PERI 9 -#define RK3066_PD_CPU 10 -#define RK3066_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3066_PD_RTC 12 - -#endif diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h deleted file mode 100644 index 93d23dfba33..00000000000 --- a/include/dt-bindings/power/rk3188-power.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ -#define __DT_BINDINGS_POWER_RK3188_POWER_H__ - -/* VD_CORE */ -#define RK3188_PD_A9_0 0 -#define RK3188_PD_A9_1 1 -#define RK3188_PD_A9_2 2 -#define RK3188_PD_A9_3 3 -#define RK3188_PD_DBG 4 -#define RK3188_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3188_PD_VIDEO 6 -#define RK3188_PD_VIO 7 -#define RK3188_PD_GPU 8 -#define RK3188_PD_PERI 9 -#define RK3188_PD_CPU 10 -#define RK3188_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3188_PD_RTC 12 - -#endif diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h deleted file mode 100644 index f710b56ccd8..00000000000 --- a/include/dt-bindings/power/rk3288-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ -#define __DT_BINDINGS_POWER_RK3288_POWER_H__ - -/** - * RK3288 Power Domain and Voltage Domain Summary. - */ - -/* VD_CORE */ -#define RK3288_PD_A17_0 0 -#define RK3288_PD_A17_1 1 -#define RK3288_PD_A17_2 2 -#define RK3288_PD_A17_3 3 -#define RK3288_PD_SCU 4 -#define RK3288_PD_DEBUG 5 -#define RK3288_PD_MEM 6 - -/* VD_LOGIC */ -#define RK3288_PD_BUS 7 -#define RK3288_PD_PERI 8 -#define RK3288_PD_VIO 9 -#define RK3288_PD_ALIVE 10 -#define RK3288_PD_HEVC 11 -#define RK3288_PD_VIDEO 12 - -/* VD_GPU */ -#define RK3288_PD_GPU 13 - -/* VD_PMU */ -#define RK3288_PD_PMU 14 - -#endif diff --git a/include/fdt_support.h b/include/fdt_support.h index 9447a64e060..f0ad2e6b365 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -14,11 +14,12 @@ #include <abuf.h> /** - * arch_fixup_fdt() - Write arch-specific information to fdt + * arch_fixup_fdt() - write arch-specific information to fdt + * + * @blob: FDT blob to write to * * Defined in arch/$(ARCH)/lib/bootm-fdt.c * - * @blob: FDT blob to write to * Return: 0 if ok, or -ve FDT_ERR_... on failure */ int arch_fixup_fdt(void *blob); @@ -33,27 +34,33 @@ u32 fdt_getprop_u32_default(const void *fdt, const char *path, const char *prop, const u32 dflt); /** - * Add data to the root of the FDT before booting the OS. + * fdt_root() - add data to the root of the FDT before booting the OS + * + * @fdt: FDT address in memory * * See doc/device-tree-bindings/root.txt * - * @param fdt FDT address in memory * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_root(void *fdt); /** - * Add chosen data the FDT before booting the OS. + * fdt_chosen() - add chosen data the FDT before booting the OS + * + * @fdt: FDT address in memory * * In particular, this adds the kernel command line (bootargs) to the FDT. * - * @param fdt FDT address in memory * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_chosen(void *fdt); /** - * Add initrd information to the FDT before booting the OS. + * fdt_initrd() - add initrd information to the FDT before booting the OS + * + * @fdt: Pointer to FDT in memory + * @initrd_start: Start of ramdisk + * @initrd_end: End of ramdisk * * Adds linux,initrd-start and linux,initrd-end properties to the /chosen node, * creating it if necessary. @@ -63,9 +70,6 @@ int fdt_chosen(void *fdt); * * If @initrd_start == @initrd_end this function does nothing and returns 0. * - * @fdt: Pointer to FDT in memory - * @initrd_start: Start of ramdisk - * @initrd_end: End of ramdisk * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end); @@ -93,29 +97,35 @@ void do_fixup_by_compat(void *fdt, const char *compat, void do_fixup_by_compat_u32(void *fdt, const char *compat, const char *prop, u32 val, int create); /** + * fdt_fixup_memory() - setup the memory node in the DT + * + * @blob: FDT blob to update + * @start: Begin of DRAM mapping in physical memory + * @size: Size of the single memory bank + * * Setup the memory node in the DT. Creates one if none was existing before. * Calls fdt_fixup_memory_banks() to populate a single reg pair covering the * whole memory. * - * @param blob FDT blob to update - * @param start Begin of DRAM mapping in physical memory - * @param size Size of the single memory bank * Return: 0 if ok, or -1 or -FDT_ERR_... on error */ int fdt_fixup_memory(void *blob, u64 start, u64 size); /** + * fdt_fixup_memory_banks() - fill the DT mem node with multiple memory banks + * + * @blob: FDT blob to update + * @start: Array of size <banks> to hold the start addresses. + * @size: Array of size <banks> to hold the size of each region. + * @banks: Number of memory banks to create. If 0, the reg property + * will be left untouched. + * * Fill the DT memory node with multiple memory banks. * Creates the node if none was existing before. * If banks is 0, it will not touch the existing reg property. This allows * boards to not mess with the existing DT setup, which may have been * filled in properly before. * - * @param blob FDT blob to update - * @param start Array of size <banks> to hold the start addresses. - * @param size Array of size <banks> to hold the size of each region. - * @param banks Number of memory banks to create. If 0, the reg - * property will be left untouched. * Return: 0 if ok, or -1 or -FDT_ERR_... on error */ #ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY @@ -135,14 +145,17 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, void fdt_fixup_qe_firmware(void *fdt); /** + * fdt_fixup_display() - update native-mode property of display-timings + * + * @blob: FDT blob to update + * @path: path within dt + * @display: name of display timing to match + * * Update native-mode property of display-timings node to the phandle * of the timings matching a display by name (case insensitive). * * see kernel Documentation/devicetree/bindings/video/display-timing.txt * - * @param blob FDT blob to update - * @param path path within dt - * @param display name of display timing to match * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_fixup_display(void *blob, const char *path, const char *display); @@ -160,18 +173,21 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} #endif /** + * fdt_record_loadable() - record info about a loadable in /fit-images + * + * @blob: FDT blob to update + * @index: index of this loadable + * @name: name of the loadable + * @load_addr: address the loadable was loaded to + * @size: number of bytes loaded + * @entry_point: entry point (if specified, otherwise pass -1) + * @type: type (if specified, otherwise pass NULL) + * @os: os-type (if specified, otherwise pass NULL) + * @arch: architecture (if specified, otherwise pass NULL) + * * Record information about a processed loadable in /fit-images (creating * /fit-images if necessary). * - * @param blob FDT blob to update - * @param index index of this loadable - * @param name name of the loadable - * @param load_addr address the loadable was loaded to - * @param size number of bytes loaded - * @param entry_point entry point (if specified, otherwise pass -1) - * @param type type (if specified, otherwise pass NULL) - * @param os os-type (if specified, otherwise pass NULL) - * @param arch architecture (if specified, otherwise pass NULL) * Return: 0 if ok, or -1 or -FDT_ERR_... on error */ int fdt_record_loadable(void *blob, u32 index, const char *name, @@ -186,39 +202,43 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose); int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name); /** - * Add board-specific data to the FDT before booting the OS. + * ft_board_setup() - add board-specific data to the FDT before booting the OS + * + * @blob: FDT blob to update + * @bd: Pointer to board data * * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. * This function is called if CONFIG_OF_BOARD_SETUP is defined * - * @param blob FDT blob to update - * @param bd Pointer to board data * Return: 0 if ok, or -FDT_ERR_... on error */ int ft_board_setup(void *blob, struct bd_info *bd); /** - * board_rng_seed() - Provide a seed to be passed via /chosen/rng-seed + * board_rng_seed() - provide a seed to be passed via /chosen/rng-seed + * + * @buf: a struct abuf for returning the seed and its size. * * This function is called if CONFIG_BOARD_RNG_SEED is set, and must * be provided by the board. It should return, via @buf, some suitable * seed value to pass to the kernel. Seed size could be set in a decimal * environment variable rng_seed_size and it defaults to 64 bytes. * - * @param buf A struct abuf for returning the seed and its size. - * @return 0 if ok, negative on error. + * Return: 0 if ok, negative on error. */ int board_rng_seed(struct abuf *buf); /** - * board_fdt_chosen_bootargs() - Arbitrarily amend fdt kernel command line + * board_fdt_chosen_bootargs() - arbitrarily amend fdt kernel command line + * + * @fdt_ba: FDT /chosen/bootargs property from the kernel image if available * * This is used for late modification of kernel command line arguments just * before they are added into the /chosen node in flat device tree. * - * @return: pointer to kernel command line arguments in memory + * Return: pointer to kernel command line arguments in memory */ -char *board_fdt_chosen_bootargs(void); +const char *board_fdt_chosen_bootargs(const struct fdt_property *fdt_ba); /* * The keystone2 SOC requires all 32 bit aliased addresses to be converted @@ -229,13 +249,14 @@ char *board_fdt_chosen_bootargs(void); void ft_board_setup_ex(void *blob, struct bd_info *bd); /** - * Add system-specific data to the FDT before booting the OS. + * ft_system_setup() - add system-specific data to the FDT before booting the OS + * + * @blob: FDT blob to update + * @bd: pointer to board data * * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. * This function is called if CONFIG_OF_SYSTEM_SETUP is defined * - * @param blob FDT blob to update - * @param bd Pointer to board data * Return: 0 if ok, or -FDT_ERR_... on error */ int ft_system_setup(void *blob, struct bd_info *bd); @@ -245,6 +266,9 @@ void set_working_fdt_addr(ulong addr); /** * fdt_shrink_to_minimum() - shrink FDT while allowing for some margin * + * @blob: FDT blob to update + * @extrasize: additional bytes needed + * * Shrink down the given blob to 'minimum' size + some extrasize. * * The new size is enough to hold the existing contents plus @extrasize bytes, @@ -254,8 +278,6 @@ void set_working_fdt_addr(ulong addr); * If there is an existing memory reservation for @blob in the FDT, it is * updated for the new size. * - * @param blob FDT blob to update - * @param extrasize additional bytes needed * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_shrink_to_minimum(void *blob, uint extrasize); @@ -277,9 +299,12 @@ static inline void fdt_fixup_mtdparts(void *fdt, #endif /** - * copy the fixed-partition nodes from U-Boot device tree to external blob + * fdt_copy_fixed_partitions() - copy the fixed-partition nodes + * + * @blob: FDT blob to update + * + * Copy the fixed-partition nodes from U-Boot device tree to external blob * - * @param blob FDT blob to update * Return: 0 if ok, or non-zero on error */ int fdt_copy_fixed_partitions(void *blob); @@ -287,39 +312,45 @@ int fdt_copy_fixed_partitions(void *blob); void fdt_del_node_and_alias(void *blob, const char *alias); /** - * Translate an address from the DT into a CPU physical address + * fdt_translate_address() - translate an addr from the DT into a CPU phys addr + * + * @blob: pointer to device tree blob + * @node_offset: node DT offset + * @in_addr: pointer to the address to translate * * The translation relies on the "ranges" property. * - * @param blob Pointer to device tree blob - * @param node_offset Node DT offset - * @param in_addr Pointer to the address to translate * Return: translated address or OF_BAD_ADDR on error */ u64 fdt_translate_address(const void *blob, int node_offset, const __be32 *in_addr); /** - * Translate a DMA address from the DT into a CPU physical address + * fdt_translate_dma_address() - translate a DMA address to a CPU phys address + * + * @blob: pointer to device tree blob + * @node_offset: node DT offset + * @in_addr: pointer to the DMA address to translate * + * Translate a DMA address from the DT into a CPU physical address. * The translation relies on the "dma-ranges" property. * - * @param blob Pointer to device tree blob - * @param node_offset Node DT offset - * @param in_addr Pointer to the DMA address to translate * Return: translated DMA address or OF_BAD_ADDR on error */ u64 fdt_translate_dma_address(const void *blob, int node_offset, const __be32 *in_addr); /** + * fdt_get_dma_range() - get DMA ranges to perform bus/cpu translations + * + * @blob: pointer to device tree blob + * @node_offset: node DT offset + * @cpu: pointer to variable storing the range's cpu address + * @bus: pointer to variable storing the range's bus address + * @size: pointer to variable storing the range's size + * * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and * cpu->bus address translations * - * @param blob Pointer to device tree blob - * @param node_offset Node DT offset - * @param cpu Pointer to variable storing the range's cpu address - * @param bus Pointer to variable storing the range's bus address - * @param size Pointer to variable storing the range's size * Return: translated DMA address or OF_BAD_ADDR on error */ int fdt_get_dma_range(const void *blob, int node_offset, phys_addr_t *cpu, @@ -431,12 +462,12 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto); int fdt_valid(struct fdt_header **blobp); /** - * fdt_get_cells_len() - Get the length of a type of cell in top-level nodes + * fdt_get_cells_len() - get the length of a type of cell in top-level nodes * - * Returns the length of the cell type in bytes (4 or 8). + * @blob: pointer to device tree blob + * @nr_cells_name: name to lookup, e.g. "#address-cells" * - * @blob: Pointer to device tree blob - * @nr_cells_name: Name to lookup, e.g. "#address-cells" + * Return: the length of the cell type in bytes (4 or 8). */ int fdt_get_cells_len(const void *blob, char *nr_cells_name); @@ -446,11 +477,12 @@ int fdt_get_cells_len(const void *blob, char *nr_cells_name); int fdtdec_get_int(const void *blob, int node, const char *prop_name, int default_val); -/* - * Count child nodes of one parent node. +/** + * fdtdec_get_child_count() - count child nodes of one parent node + * + * @blob: FDT blob + * @node: parent node * - * @param blob FDT blob - * @param node parent node * Return: number of child node; 0 if there is not child node */ int fdtdec_get_child_count(const void *blob, int node); @@ -468,9 +500,10 @@ void fdt_fixup_pstore(void *blob); /** * fdt_kaslrseed() - create a 'kaslr-seed' node in chosen * - * @blob: fdt blob - * @overwrite: do not overwrite existing non-zero node unless true - * Return: 0 if OK, -ve on error + * @blob: fdt blob + * @overwrite: do not overwrite existing non-zero node unless true + * + * Return: 0 if OK, -ve on error */ int fdt_kaslrseed(void *blob, bool overwrite); diff --git a/include/power/tps65219.h b/include/power/tps65219.h index aa81b92266f..e8780af2d81 100644 --- a/include/power/tps65219.h +++ b/include/power/tps65219.h @@ -17,10 +17,20 @@ #define TPS65219_BUCK_DRIVER "tps65219_buck" #define TPS65219_VOLT_MASK 0x3F -#define TPS65219_BUCK_VOLT_MAX 3400000 - #define TPS65219_ENABLE_CTRL_REG 0x2 +#define TPS65219_VOLT_STEP_25MV 25000 +#define TPS65219_VOLT_STEP_50MV 50000 +#define TPS65219_VOLT_STEP_100MV 100000 + +#define TPS65219_BUCK_0V6 600000 +#define TPS65219_BUCK_1V4 1400000 +#define TPS65219_BUCK_3V4 3400000 + +#define TPS65219_BUCK_REG_0V6 0x00 +#define TPS65219_BUCK_REG_1V4 0x20 +#define TPS65219_BUCK_REG_3V4 0x34 + #define TPS65219_BUCK1_VOUT_REG 0xa #define TPS65219_BUCK2_VOUT_REG 0x9 #define TPS65219_BUCK3_VOUT_REG 0x8 diff --git a/include/smbios.h b/include/smbios.h index 00119d7a60c..b5fed57aba2 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -9,6 +9,7 @@ #define _SMBIOS_H_ #include <linux/types.h> +#include <smbios_def.h> /* SMBIOS spec version implemented */ #define SMBIOS_MAJOR_VER 3 @@ -37,6 +38,11 @@ enum { #define SMBIOS_INTERMEDIATE_OFFSET 16 #define SMBIOS_STRUCT_EOS_BYTES 2 +struct str_lookup_table { + u16 idx; + const char *str; +}; + struct __packed smbios_entry { u8 anchor[4]; u8 checksum; @@ -80,19 +86,14 @@ struct __packed smbios3_entry { u64 struct_table_address; }; -/* BIOS characteristics */ -#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) -#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) -#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) - -#define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0) -#define BIOS_CHARACTERISTICS_EXT2_UEFI (1 << 3) -#define BIOS_CHARACTERISTICS_EXT2_TARGET (1 << 2) - -struct __packed smbios_type0 { +struct __packed smbios_header { u8 type; u8 length; u16 handle; +}; + +struct __packed smbios_type0 { + struct smbios_header hdr; u8 vendor; u8 bios_ver; u16 bios_start_segment; @@ -109,37 +110,12 @@ struct __packed smbios_type0 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; -/** - * enum smbios_wakeup_type - wake-up type - * - * These constants are used for the Wake-Up Type field in the SMBIOS - * System Information (Type 1) structure. - */ -enum smbios_wakeup_type { - /** @SMBIOS_WAKEUP_TYPE_RESERVED: Reserved */ - SMBIOS_WAKEUP_TYPE_RESERVED, - /** @SMBIOS_WAKEUP_TYPE_OTHER: Other */ - SMBIOS_WAKEUP_TYPE_OTHER, - /** @SMBIOS_WAKEUP_TYPE_UNKNOWN: Unknown */ - SMBIOS_WAKEUP_TYPE_UNKNOWN, - /** @SMBIOS_WAKEUP_TYPE_APM_TIMER: APM Timer */ - SMBIOS_WAKEUP_TYPE_APM_TIMER, - /** @SMBIOS_WAKEUP_TYPE_MODEM_RING: Modem Ring */ - SMBIOS_WAKEUP_TYPE_MODEM_RING, - /** @SMBIOS_WAKEUP_TYPE_LAN_REMOTE: LAN Remote */ - SMBIOS_WAKEUP_TYPE_LAN_REMOTE, - /** @SMBIOS_WAKEUP_TYPE_POWER_SWITCH: Power Switch */ - SMBIOS_WAKEUP_TYPE_POWER_SWITCH, - /** @SMBIOS_WAKEUP_TYPE_PCI_PME: PCI PME# */ - SMBIOS_WAKEUP_TYPE_PCI_PME, - /** @SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED: AC Power Restored */ - SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED, -}; +#define SMBIOS_TYPE1_LENGTH_V20 0x08 +#define SMBIOS_TYPE1_LENGTH_V21 0x19 +#define SMBIOS_TYPE1_LENGTH_V24 0x1b struct __packed smbios_type1 { - u8 type; - u8 length; - u16 handle; + struct smbios_header hdr; u8 manufacturer; u8 product_name; u8 version; @@ -151,13 +127,10 @@ struct __packed smbios_type1 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; -#define SMBIOS_BOARD_FEATURE_HOSTING (1 << 0) -#define SMBIOS_BOARD_MOTHERBOARD 10 +#define SMBIOS_TYPE2_CON_OBJ_HANDLE_SIZE sizeof(u16) struct __packed smbios_type2 { - u8 type; - u8 length; - u16 handle; + struct smbios_header hdr; u8 manufacturer; u8 product_name; u8 version; @@ -168,17 +141,15 @@ struct __packed smbios_type2 { u16 chassis_handle; u8 board_type; u8 number_contained_objects; + /* + * Dynamic bytes will be inserted here to store the objects. + * length is equal to 'number_contained_objects'. + */ char eos[SMBIOS_STRUCT_EOS_BYTES]; }; -#define SMBIOS_ENCLOSURE_DESKTOP 3 -#define SMBIOS_STATE_SAFE 3 -#define SMBIOS_SECURITY_NONE 3 - struct __packed smbios_type3 { - u8 type; - u8 length; - u16 handle; + struct smbios_header hdr; u8 manufacturer; u8 chassis_type; u8 version; @@ -193,21 +164,17 @@ struct __packed smbios_type3 { u8 number_of_power_cords; u8 element_count; u8 element_record_length; + /* + * Dynamic bytes will be inserted here to store the elements. + * length is equal to 'element_record_length' * 'element_record_length' + */ + u8 sku_number; char eos[SMBIOS_STRUCT_EOS_BYTES]; }; -#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3 -#define SMBIOS_PROCESSOR_STATUS_ENABLED 1 -#define SMBIOS_PROCESSOR_UPGRADE_NONE 6 - -#define SMBIOS_PROCESSOR_FAMILY_OTHER 1 -#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 2 - struct __packed smbios_type4 { - u8 type; - u8 length; - u16 handle; - u8 socket_designation; + struct smbios_header hdr; + u8 socket_design; u8 processor_type; u8 processor_family; u8 processor_manufacturer; @@ -233,6 +200,67 @@ struct __packed smbios_type4 { u16 core_count2; u16 core_enabled2; u16 thread_count2; + u16 thread_enabled; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +union cache_config { + struct { + u16 level:3; + u16 bsocketed:1; + u16 rsvd0:1; + u16 locate:2; + u16 benabled:1; + u16 opmode:2; + u16 rsvd1:6; + } fields; + u16 data; +}; + +union cache_size_word { + struct { + u16 size:15; + u16 granu:1; + } fields; + u16 data; +}; + +union cache_size_dword { + struct { + u32 size:31; + u32 granu:1; + } fields; + u32 data; +}; + +union cache_sram_type { + struct { + u16 other:1; + u16 unknown:1; + u16 nonburst:1; + u16 burst:1; + u16 plburst:1; + u16 sync:1; + u16 async:1; + u16 rsvd:9; + } fields; + u16 data; +}; + +struct __packed smbios_type7 { + struct smbios_header hdr; + u8 socket_design; + union cache_config config; + union cache_size_word max_size; + union cache_size_word inst_size; + union cache_sram_type supp_sram_type; + union cache_sram_type curr_sram_type; + u8 speed; + u8 err_corr_type; + u8 sys_cache_type; + u8 associativity; + union cache_size_dword max_size2; + union cache_size_dword inst_size2; char eos[SMBIOS_STRUCT_EOS_BYTES]; }; @@ -252,12 +280,6 @@ struct __packed smbios_type127 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; -struct __packed smbios_header { - u8 type; - u8 length; - u16 handle; -}; - /** * fill_smbios_header() - Fill the header of an SMBIOS table * diff --git a/include/smbios_def.h b/include/smbios_def.h new file mode 100644 index 00000000000..81c5781217f --- /dev/null +++ b/include/smbios_def.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Linaro Limited + * Author: Raymond Mao <raymond.mao@linaro.org> + */ + +#ifndef _SMBIOS_DEF_H_ +#define _SMBIOS_DEF_H_ + +/* + * BIOS characteristics + */ + +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED 0x80 /* BIT(7) */ +#define BIOS_CHARACTERISTICS_UPGRADEABLE 0x800 /* BIT(11) */ +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT 0x10000 /* BIT(16) */ + +#define BIOS_CHARACTERISTICS_EXT1_ACPI 1 /* BIT(0) */ +#define BIOS_CHARACTERISTICS_EXT2_UEFI 8 /* BIT(3) */ +#define BIOS_CHARACTERISTICS_EXT2_TARGET 4 /* BIT(2) */ + +/* + * System Information + */ + +#define SMBIOS_WAKEUP_TYPE_RESERVED 0 +#define SMBIOS_WAKEUP_TYPE_OTHER 1 +#define SMBIOS_WAKEUP_TYPE_UNKNOWN 2 +#define SMBIOS_WAKEUP_TYPE_APM_TIMER 3 +#define SMBIOS_WAKEUP_TYPE_MODEM_RING 4 +#define SMBIOS_WAKEUP_TYPE_LAN_REMOTE 5 +#define SMBIOS_WAKEUP_TYPE_POWER_SWITCH 6 +#define SMBIOS_WAKEUP_TYPE_PCI_PME 7 +#define SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED 8 + +/* + * Baseboard Information + */ + +#define SMBIOS_BOARD_FEAT_HOST_BOARD 1 /* BIT(0) */ +#define SMBIOS_BOARD_FEAT_REQ_AUX 2 /* BIT(1) */ +#define SMBIOS_BOARD_FEAT_REMOVABLE 4 /* BIT(2) */ +#define SMBIOS_BOARD_FEAT_REPLACEABLE 8 /* BIT(3) */ +#define SMBIOS_BOARD_FEAT_HOT_SWAPPABLE 16 /* BIT(4) */ + +#define SMBIOS_BOARD_TYPE_UNKNOWN 1 +#define SMBIOS_BOARD_TYPE_OTHER 2 +#define SMBIOS_BOARD_TYPE_SERVER_BLADE 3 +#define SMBIOS_BOARD_TYPE_CON_SWITCH 4 +#define SMBIOS_BOARD_TYPE_SM_MODULE 5 +#define SMBIOS_BOARD_TYPE_PROCESSOR_MODULE 6 +#define SMBIOS_BOARD_TYPE_IO_MODULE 7 +#define SMBIOS_BOARD_TYPE_MEM_MODULE 8 +#define SMBIOS_BOARD_TYPE_DAUGHTER_BOARD 9 +#define SMBIOS_BOARD_TYPE_MOTHERBOARD 10 +#define SMBIOS_BOARD_TYPE_PROC_MEM_MODULE 11 +#define SMBIOS_BOARD_TYPE_PROC_IO_MODULE 12 +#define SMBIOS_BOARD_TYPE_INTERCON 13 + +/* + * System Enclosure or Chassis + */ +#define SMBIOS_ENCLOSURE_UNKNOWN 2 +#define SMBIOS_ENCLOSURE_DESKTOP 3 + +#define SMBIOS_STATE_OTHER 1 +#define SMBIOS_STATE_UNKNOWN 2 +#define SMBIOS_STATE_SAFE 3 +#define SMBIOS_STATE_WARNING 4 +#define SMBIOS_STATE_CRITICAL 5 +#define SMBIOS_STATE_NONRECOVERABLE 6 + +#define SMBIOS_SECURITY_OTHER 1 +#define SMBIOS_SECURITY_UNKNOWN 2 +#define SMBIOS_SECURITY_NONE 3 +#define SMBIOS_SECURITY_EXTINT_LOCK 4 +#define SMBIOS_SECURITY_EXTINT_EN 5 + +#define SMBIOS_ENCLOSURE_OEM_UND 0 +#define SMBIOS_ENCLOSURE_HEIGHT_UND 0 +#define SMBIOS_POWCORD_NUM_UND 0 +#define SMBIOS_ELEMENT_TYPE_SELECT 0x80 /* BIT(7) */ + +/* + * Processor Information + */ + +#define SMBIOS_PROCESSOR_TYPE_OTHER 1 +#define SMBIOS_PROCESSOR_TYPE_UNKNOWN 2 +#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3 +#define SMBIOS_PROCESSOR_TYPE_MATH 4 +#define SMBIOS_PROCESSOR_TYPE_DSP 5 +#define SMBIOS_PROCESSOR_TYPE_VIDEO 6 + +#define SMBIOS_PROCESSOR_STATUS_UNKNOWN 0 +#define SMBIOS_PROCESSOR_STATUS_ENABLED 1 +#define SMBIOS_PROCESSOR_STATUS_DISABLED_USER 2 +#define SMBIOS_PROCESSOR_STATUS_DISABLED_BIOS 3 +#define SMBIOS_PROCESSOR_STATUS_IDLE 4 +#define SMBIOS_PROCESSOR_STATUS_OTHER 7 + +#define SMBIOS_PROCESSOR_UPGRADE_OTHER 1 +#define SMBIOS_PROCESSOR_UPGRADE_UNKNOWN 2 +#define SMBIOS_PROCESSOR_UPGRADE_NONE 6 + +#define SMBIOS_PROCESSOR_FAMILY_OTHER 1 +#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 2 +#define SMBIOS_PROCESSOR_FAMILY_RSVD 255 +#define SMBIOS_PROCESSOR_FAMILY_ARMV7 256 +#define SMBIOS_PROCESSOR_FAMILY_ARMV8 257 +#define SMBIOS_PROCESSOR_FAMILY_RV32 512 +#define SMBIOS_PROCESSOR_FAMILY_RV64 513 + +#define SMBIOS_PROCESSOR_FAMILY_EXT 0xfe + +/* Processor Characteristics */ +#define SMBIOS_PROCESSOR_RSVD 1 /* BIT(0) */ +#define SMBIOS_PROCESSOR_UND 2 /* BIT(1) */ +#define SMBIOS_PROCESSOR_64BIT 4 /* BIT(2) */ +#define SMBIOS_PROCESSOR_MULTICORE 8 /* BIT(3) */ +#define SMBIOS_PROCESSOR_HWTHREAD 16 /* BIT(4) */ +#define SMBIOS_PROCESSOR_EXEC_PROT 32 /* BIT(5) */ +#define SMBIOS_PROCESSOR_ENH_VIRT 64 /* BIT(6) */ +#define SMBIOS_PROCESSOR_POW_CON 0x80 /* BIT(7) */ +#define SMBIOS_PROCESSOR_128BIT 0x100 /* BIT(8) */ +#define SMBIOS_PROCESSOR_ARM64_SOCID 0x200 /* BIT(9) */ + +/* + * Cache Information + */ + +#define SMBIOS_CACHE_SIZE_EXT_KB (2047 * 1024) /* 2047 MiB */ +#define SMBIOS_CACHE_HANDLE_NONE 0xffff + +/* System Cache Type */ +#define SMBIOS_CACHE_SYSCACHE_TYPE_OTHER 1 +#define SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN 2 +#define SMBIOS_CACHE_SYSCACHE_TYPE_INST 3 +#define SMBIOS_CACHE_SYSCACHE_TYPE_DATA 4 +#define SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED 5 + +/* Cache Speed */ +#define SMBIOS_CACHE_SPEED_UNKNOWN 0 + +/* SRAM Type */ +#define SMBIOS_CACHE_SRAM_TYPE_UNKNOWN 2 /* BIT(1) */ + +/* Error Correction Type */ +#define SMBIOS_CACHE_ERRCORR_OTHER 1 +#define SMBIOS_CACHE_ERRCORR_UNKNOWN 2 +#define SMBIOS_CACHE_ERRCORR_NONE 3 +#define SMBIOS_CACHE_ERRCORR_PARITY 4 +#define SMBIOS_CACHE_ERRCORR_SBITECC 5 +#define SMBIOS_CACHE_ERRCORR_MBITECC 6 + +/* Cache Configuration */ +#define SMBIOS_CACHE_LEVEL_1 0 +#define SMBIOS_CACHE_LEVEL_2 1 +#define SMBIOS_CACHE_LEVEL_3 2 +#define SMBIOS_CACHE_LEVEL_4 3 +#define SMBIOS_CACHE_LEVEL_5 4 +#define SMBIOS_CACHE_LEVEL_6 5 +#define SMBIOS_CACHE_LEVEL_7 6 +#define SMBIOS_CACHE_LEVEL_8 7 +#define SMBIOS_CACHE_SOCKETED 8 /* BIT(3) */ +#define SMBIOS_CACHE_LOCATE_EXTERNAL 32 /* BIT(5) */ +#define SMBIOS_CACHE_LOCATE_RESERVED 64 /* BIT(6) */ +#define SMBIOS_CACHE_LOCATE_UNKNOWN 96 /* (BIT(5) | BIT(6)) */ +#define SMBIOS_CACHE_ENABLED 0x80 /* BIT(7) */ +#define SMBIOS_CACHE_OP_WB 0x100 /* BIT(8), Write Back */ +#define SMBIOS_CACHE_OP_VAR 0x200 /* BIT(9), Varies with Memory Address */ +#define SMBIOS_CACHE_OP_UND 0x300 /* (BIT(8) | BIT(9)), Unknown*/ + +/* Cache Granularity */ +#define SMBIOS_CACHE_GRANU_1K 0 +#define SMBIOS_CACHE_GRANU_64K 1 + +/* Cache Associativity */ +#define SMBIOS_CACHE_ASSOC_OTHER 1 +#define SMBIOS_CACHE_ASSOC_UNKNOWN 2 +#define SMBIOS_CACHE_ASSOC_DMAPPED 3 +#define SMBIOS_CACHE_ASSOC_2WAY 4 +#define SMBIOS_CACHE_ASSOC_4WAY 5 +#define SMBIOS_CACHE_ASSOC_FULLY 6 +#define SMBIOS_CACHE_ASSOC_8WAY 7 +#define SMBIOS_CACHE_ASSOC_16WAY 8 +#define SMBIOS_CACHE_ASSOC_12WAY 9 +#define SMBIOS_CACHE_ASSOC_24WAY 10 +#define SMBIOS_CACHE_ASSOC_32WAY 11 +#define SMBIOS_CACHE_ASSOC_48WAY 12 +#define SMBIOS_CACHE_ASSOC_64WAY 13 +#define SMBIOS_CACHE_ASSOC_20WAY 14 + +#endif /* _SMBIOS_DEF_H_ */ diff --git a/include/smbios_plat.h b/include/smbios_plat.h new file mode 100644 index 00000000000..70089d5a2ba --- /dev/null +++ b/include/smbios_plat.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Linaro Limited + * Author: Raymond Mao <raymond.mao@linaro.org> + */ +#ifndef __SMBIOS_PLAT_H +#define __SMBIOS_PLAT_H + +#include <smbios.h> + +struct cache_info { + union cache_config config; + union cache_sram_type supp_sram_type; + union cache_sram_type curr_sram_type; + u32 line_size; + u32 associativity; + u32 max_size; + u32 inst_size; + u8 cache_type; + u8 speed; + u8 err_corr_type; + char *socket_design; +}; + +struct processor_info { + u32 id[2]; + u16 ext_clock; + u16 max_speed; + u16 curr_speed; + u16 characteristics; + u16 family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; + u16 thread_enabled; + u8 type; + u8 family; + u8 voltage; + u8 status; + u8 upgrade; + u8 core_count; + u8 core_enabled; + u8 thread_count; + char *socket_design; + char *manufacturer; + char *version; + char *sn; + char *asset_tag; + char *pn; +}; + +struct sysinfo_plat { + struct processor_info *processor; + struct cache_info *cache; + /* add other sysinfo structure here */ +}; + +#if defined CONFIG_SYSINFO_SMBIOS +int sysinfo_get_cache_info(u8 level, struct cache_info *cache_info); +void sysinfo_cache_info_default(struct cache_info *ci); +int sysinfo_get_processor_info(struct processor_info *pinfo); +#else +static inline int sysinfo_get_cache_info(u8 level, + struct cache_info *cache_info) +{ + return -ENOSYS; +} + +static inline void sysinfo_cache_info_default(struct cache_info *ci) +{ +} + +static inline int sysinfo_get_processor_info(struct processor_info *pinfo) +{ + return -ENOSYS; +} +#endif + +#endif /* __SMBIOS_PLAT_H */ diff --git a/include/sysinfo.h b/include/sysinfo.h index 027a463dc33..ba2ac273e8e 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -11,6 +11,8 @@ struct udevice; +#define SYSINFO_CACHE_LVL_MAX 3 + /* * This uclass encapsulates hardware methods to gather information about a * sysinfo or a specific device such as hard-wired GPIOs on GPIO expanders, @@ -42,18 +44,109 @@ struct udevice; enum sysinfo_id { SYSID_NONE, - /* For SMBIOS tables */ + /* BIOS Information (Type 0) */ + SYSID_SM_BIOS_VENDOR, + SYSID_SM_BIOS_VER, + SYSID_SM_BIOS_REL_DATE, + + /* System Information (Type 1) */ SYSID_SM_SYSTEM_MANUFACTURER, SYSID_SM_SYSTEM_PRODUCT, SYSID_SM_SYSTEM_VERSION, SYSID_SM_SYSTEM_SERIAL, + SYSID_SM_SYSTEM_WAKEUP, SYSID_SM_SYSTEM_SKU, SYSID_SM_SYSTEM_FAMILY, + + /* Baseboard (or Module) Information (Type 2) */ SYSID_SM_BASEBOARD_MANUFACTURER, SYSID_SM_BASEBOARD_PRODUCT, SYSID_SM_BASEBOARD_VERSION, SYSID_SM_BASEBOARD_SERIAL, SYSID_SM_BASEBOARD_ASSET_TAG, + SYSID_SM_BASEBOARD_FEATURE, + SYSID_SM_BASEBOARD_CHASSIS_LOCAT, + SYSID_SM_BASEBOARD_TYPE, + SYSID_SM_BASEBOARD_OBJS_NUM, + SYSID_SM_BASEBOARD_OBJS_HANDLE, + + /* System Enclosure or Chassis (Type 3) */ + SYSID_SM_ENCLOSURE_MANUFACTURER, + SYSID_SM_ENCLOSURE_VERSION, + SYSID_SM_ENCLOSURE_SERIAL, + SYSID_SM_ENCLOSURE_ASSET_TAG, + SYSID_SM_ENCLOSURE_TYPE, + SYSID_SM_ENCLOSURE_BOOTUP, + SYSID_SM_ENCLOSURE_POW, + SYSID_SM_ENCLOSURE_THERMAL, + SYSID_SM_ENCLOSURE_SECURITY, + SYSID_SM_ENCLOSURE_OEM, + SYSID_SM_ENCLOSURE_HEIGHT, + SYSID_SM_ENCLOSURE_POWCORE_NUM, + SYSID_SM_ENCLOSURE_ELEMENT_CNT, + SYSID_SM_ENCLOSURE_ELEMENT_LEN, + SYSID_SM_ENCLOSURE_ELEMENTS, + SYSID_SM_ENCLOSURE_SKU, + + /* Processor Information (Type 4) */ + SYSID_SM_PROCESSOR_SOCKET, + SYSID_SM_PROCESSOR_TYPE, + SYSID_SM_PROCESSOR_MANUFACT, + SYSID_SM_PROCESSOR_ID, + SYSID_SM_PROCESSOR_VERSION, + SYSID_SM_PROCESSOR_VOLTAGE, + SYSID_SM_PROCESSOR_EXT_CLOCK, + SYSID_SM_PROCESSOR_MAX_SPEED, + SYSID_SM_PROCESSOR_CUR_SPEED, + SYSID_SM_PROCESSOR_STATUS, + SYSID_SM_PROCESSOR_UPGRADE, + SYSID_SM_PROCESSOR_SN, + SYSID_SM_PROCESSOR_ASSET_TAG, + SYSID_SM_PROCESSOR_PN, + SYSID_SM_PROCESSOR_CORE_CNT, + SYSID_SM_PROCESSOR_CORE_EN, + SYSID_SM_PROCESSOR_THREAD_CNT, + SYSID_SM_PROCESSOR_CHARA, + SYSID_SM_PROCESSOR_FAMILY, + SYSID_SM_PROCESSOR_FAMILY2, + SYSID_SM_PROCESSOR_CORE_CNT2, + SYSID_SM_PROCESSOR_CORE_EN2, + SYSID_SM_PROCESSOR_THREAD_CNT2, + SYSID_SM_PROCESSOR_THREAD_EN, + + /* + * Cache Information (Type 7) + * Each of the id should reserve space for up to + * SYSINFO_CACHE_LVL_MAX levels of cache + */ + SYSID_SM_CACHE_LEVEL, + SYSID_SM_CACHE_HANDLE, + SYSID_SM_CACHE_INFO_START, + SYSID_SM_CACHE_SOCKET = SYSID_SM_CACHE_INFO_START, + SYSID_SM_CACHE_CONFIG = + SYSID_SM_CACHE_SOCKET + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_MAX_SIZE = + SYSID_SM_CACHE_CONFIG + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_INST_SIZE = + SYSID_SM_CACHE_MAX_SIZE + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_SUPSRAM_TYPE = + SYSID_SM_CACHE_INST_SIZE + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_CURSRAM_TYPE = + SYSID_SM_CACHE_SUPSRAM_TYPE + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_SPEED = + SYSID_SM_CACHE_CURSRAM_TYPE + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_ERRCOR_TYPE = + SYSID_SM_CACHE_SPEED + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_SCACHE_TYPE = + SYSID_SM_CACHE_ERRCOR_TYPE + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_ASSOC = + SYSID_SM_CACHE_SCACHE_TYPE + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_MAX_SIZE2 = + SYSID_SM_CACHE_ASSOC + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_INST_SIZE2 = + SYSID_SM_CACHE_MAX_SIZE2 + SYSINFO_CACHE_LVL_MAX, + SYSID_SM_CACHE_INFO_END = + SYSID_SM_CACHE_INST_SIZE2 + SYSINFO_CACHE_LVL_MAX - 1, /* For show_board_info() */ SYSID_BOARD_MODEL, @@ -116,6 +209,18 @@ struct sysinfo_ops { int (*get_str)(struct udevice *dev, int id, size_t size, char *val); /** + * get_data() - Read a specific string data value that describes the + * hardware setup. + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * @data: Pointer to the address of the data area. + * @size: Pointer to the size of the data area. + * + * Return: 0 if OK, -ve on error. + */ + int (*get_data)(struct udevice *dev, int id, void **data, size_t *size); + + /** * get_fit_loadable - Get the name of an image to load from FIT * This function can be used to provide the image names based on runtime * detection. A classic use-case would when DTBOs are used to describe @@ -187,6 +292,18 @@ int sysinfo_get_int(struct udevice *dev, int id, int *val); int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val); /** + * sysinfo_get_data() - Get a data area from the platform. + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * @data: Pointer to the address of the data area. + * @size: Pointer to the size of the data area. + * + * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on + * error. + */ +int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size); + +/** * sysinfo_get() - Return the sysinfo device for the sysinfo in question. * @devp: Pointer to structure to receive the sysinfo device. * @@ -241,6 +358,12 @@ static inline int sysinfo_get_str(struct udevice *dev, int id, size_t size, return -ENOSYS; } +static inline int sysinfo_get_data(struct udevice *dev, int id, void **data, + size_t *size) +{ + return -ENOSYS; +} + static inline int sysinfo_get(struct udevice **devp) { return -ENOSYS; diff --git a/include/tpm-common.h b/include/tpm-common.h index 1ba81386ce1..bfb84a931d1 100644 --- a/include/tpm-common.h +++ b/include/tpm-common.h @@ -43,11 +43,19 @@ enum tpm_version { }; /** + * define TPM2_NUM_PCR_BANKS - number of PCR banks + * The value 16 can be found in the current standard + * TCG TSS 2.0 Overview and Common Structures Specification 1.0, rev 10 + */ +#define TPM2_NUM_PCR_BANKS 16 + +/** * struct tpm_chip_priv - Information about a TPM, stored by the uclass * - * These values must be set up by the device's probe() method before + * Some of hese values must be set up by the device's probe() method before * communcation is attempted. If the device has an xfer() method, this is * not needed. There is no need to set up @buf. + * The active_banks is only valid for TPMv2 after the device is initialized. * * @version: TPM stack to be used * @duration_ms: Length of each duration type in milliseconds @@ -55,6 +63,8 @@ enum tpm_version { * @buf: Buffer used during the exchanges with the chip * @pcr_count: Number of PCR per bank * @pcr_select_min: Minimum size in bytes of the pcrSelect array + * @active_bank_count: Number of active PCR banks + * @active_banks: Array of active PCRs * @plat_hier_disabled: Platform hierarchy has been disabled (TPM is locked * down until next reboot) */ @@ -68,6 +78,10 @@ struct tpm_chip_priv { /* TPM v2 specific data */ uint pcr_count; uint pcr_select_min; +#if IS_ENABLED(CONFIG_TPM_V2) + u8 active_bank_count; + u32 active_banks[TPM2_NUM_PCR_BANKS]; +#endif bool plat_hier_disabled; }; diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 4fd19c52fd7..65681464b37 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -6,6 +6,11 @@ * Copyright (c) 2020 Linaro * Copyright (c) 2018 Bootlin * + * The structures are described in + * Trusted Platform Module Library Part 2: Structures + * http://tcg.tjn.chef.causewaynow.com/resource/tpm-library-specification/ + * + * C header files are listed in * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/ * * Author: Miquel Raynal <miquel.raynal@bootlin.com> @@ -34,16 +39,6 @@ struct udevice; #define TPM2_HDR_LEN 10 -/* - * We deviate from this draft of the specification by increasing the value of - * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2 - * implementations that have enabled a larger than typical number of PCR - * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included - * in a future revision of the specification. - */ -#define TPM2_NUM_PCR_BANKS 16 - -/* Definition of (UINT32) TPM2_CAP Constants */ #define TPM2_CAP_PCRS 0x00000005U #define TPM2_CAP_TPM_PROPERTIES 0x00000006U @@ -55,20 +50,43 @@ struct udevice; #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30) #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31) -/* TPMS_TAGGED_PROPERTY Structure */ +/** + * struct tpms_tagged_property - TPMS_TAGGED_PROPERTY structure + * + * This structure is returned by TPM2_GetCapability() to report + * a u32 property value. + * + * @property: property identifier + * @value: value of the property + */ struct tpms_tagged_property { u32 property; u32 value; } __packed; -/* TPMS_PCR_SELECTION Structure */ +/** + * struct tpms_pcr_selection - TPMS_PCR_SELECTION structure + * + * This structure allows to specify a hash algorithm and a list of + * selected PCRs. A PCR is selected by setting the related bit in + * @pcr_select to 1. + * + * @hash: hash algorithm associated with the selection + * @size_of_select: size in bytes of the @pcr_select array + * @pcr_select: bit map of selected PCRs + */ struct tpms_pcr_selection { u16 hash; u8 size_of_select; u8 pcr_select[TPM2_PCR_SELECT_MAX]; } __packed; -/* TPML_PCR_SELECTION Structure */ +/** + * struct tpml_pcr_selection - TPML_PCR_SELECTION structure + * + * @count: number of selection structures, may be zero + * @selection: list of selections + */ struct tpml_pcr_selection { u32 count; struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS]; @@ -268,6 +286,7 @@ struct digest_info { u16 hash_alg; u32 hash_mask; u16 hash_len; + bool supported; }; /* Algorithm Registry */ @@ -278,38 +297,50 @@ struct digest_info { #define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 static const struct digest_info hash_algo_list[] = { -#if IS_ENABLED(CONFIG_SHA1) { "sha1", TPM2_ALG_SHA1, TCG2_BOOT_HASH_ALG_SHA1, TPM2_SHA1_DIGEST_SIZE, - }, +#if IS_ENABLED(CONFIG_SHA1) + true, +#else + false, #endif -#if IS_ENABLED(CONFIG_SHA256) + }, { "sha256", TPM2_ALG_SHA256, TCG2_BOOT_HASH_ALG_SHA256, TPM2_SHA256_DIGEST_SIZE, - }, +#if IS_ENABLED(CONFIG_SHA256) + true, +#else + false, #endif -#if IS_ENABLED(CONFIG_SHA384) + }, { "sha384", TPM2_ALG_SHA384, TCG2_BOOT_HASH_ALG_SHA384, TPM2_SHA384_DIGEST_SIZE, - }, +#if IS_ENABLED(CONFIG_SHA384) + true, +#else + false, #endif -#if IS_ENABLED(CONFIG_SHA512) + }, { "sha512", TPM2_ALG_SHA512, TCG2_BOOT_HASH_ALG_SHA512, TPM2_SHA512_DIGEST_SIZE, - }, +#if IS_ENABLED(CONFIG_SHA512) + true, +#else + false, #endif + }, }; /* NV index attributes */ @@ -705,6 +736,14 @@ enum tpm2_algorithms tpm2_name_to_algorithm(const char *name); const char *tpm2_algorithm_name(enum tpm2_algorithms); /** + * tpm2_algorithm_supported() - Check if the algorithm supported by U-Boot + * + * @algorithm_id: algorithm defined in enum tpm2_algorithms + * Return: true if supported, otherwise false + */ +bool tpm2_algorithm_supported(enum tpm2_algorithms algo); + +/** * tpm2_algorithm_to_len() - Return an algorithm length for supported algorithm id * * @algorithm_id: algorithm defined in enum tpm2_algorithms @@ -732,20 +771,28 @@ u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo); */ /** - * tpm2_allow_extend() - Check if extending PCRs is allowed and safe + * tpm2_check_active_banks() - Check if the active PCR banks are supported by + * our configuration * * @dev: TPM device * Return: true if allowed */ -bool tpm2_allow_extend(struct udevice *dev); +bool tpm2_check_active_banks(struct udevice *dev); /** - * tpm2_is_active_pcr() - check the pcr_select. If at least one of the PCRs - * supports the algorithm add it on the active ones + * tpm2_is_active_bank() - check the pcr_select. If at least one of the PCRs + * supports the algorithm add it on the active ones * * @selection: PCR selection structure * Return: True if the algorithm is active */ -bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection); +bool tpm2_is_active_bank(struct tpms_pcr_selection *selection); + +/** + * tpm2_print_active_banks() - Print the active TPM PCRs + * + * @dev: TPM device + */ +void tpm2_print_active_banks(struct udevice *dev); #endif /* __TPM_V2_H */ diff --git a/include/tpm_tcg2.h b/include/tpm_tcg2.h index 6519004cc41..eb6afe49e77 100644 --- a/include/tpm_tcg2.h +++ b/include/tpm_tcg2.h @@ -94,17 +94,17 @@ struct tcg_pcr_event { } __packed; /** - * tcg2_get_pcr_info() - get the supported, active PCRs and number of banks + * tcg2_get_pcr_info() - get the supported, active banks and number of banks * * @dev: TPM device - * @supported_pcr: bitmask with the algorithms supported - * @active_pcr: bitmask with the active algorithms - * @pcr_banks: number of PCR banks + * @supported_bank: bitmask with the algorithms supported + * @active_bank: bitmask with the active algorithms + * @bank_num: number of PCR banks * * @return 0 on success, code of operation or negative errno on failure */ -int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, - u32 *pcr_banks); +int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_bank, u32 *active_bank, + u32 *bank_num); /** * Crypto Agile Log Entry Format diff --git a/lib/Kconfig b/lib/Kconfig index 8f1a96d98c4..baeb615626d 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1091,6 +1091,12 @@ config GENERATE_SMBIOS_TABLE See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in the devicetree. +config GENERATE_SMBIOS_TABLE_VERBOSE + bool "Generate a verbose SMBIOS (System Management BIOS) table" + depends on GENERATE_SMBIOS_TABLE + help + Provide verbose SMBIOS information. + endmenu config LIB_RATIONAL diff --git a/lib/smbios.c b/lib/smbios.c index defb6b42f45..78cee8c0c26 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -208,6 +208,43 @@ void get_str_from_dt(const struct map_sysinfo *nprop, char *str, size_t size) } /** + * smbios_get_val_si() - Get value from the devicetree or sysinfo + * + * @ctx: context of SMBIOS + * @prop: property to read + * @sysinfo_id: unique identifier for the value to be read + * @val_def: Default value + * Return: Valid value from sysinfo or device tree, otherwise val_def. + */ +static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, + const char * __maybe_unused prop, + int __maybe_unused sysinfo_id, int val_def) +{ +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + int val; + + if (!ctx->dev) + return val_def; + + if (!sysinfo_get_int(ctx->dev, sysinfo_id, &val)) + return val; + + if (!IS_ENABLED(CONFIG_OF_CONTROL) || !prop) + return val_def; + + if (ofnode_valid(ctx->node) && !ofnode_read_u32(ctx->node, prop, &val)) + return val; + + /* + * If the node or property is not valid fallback and try the root + */ + if (!ofnode_read_u32(ofnode_root(), prop, &val)) + return val; +#endif + return val_def; +} + +/** * smbios_add_prop_si() - Add a property from the devicetree or sysinfo * * Sysinfo is used if available, with a fallback to devicetree @@ -226,9 +263,6 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, if (!dval || !*dval) dval = NULL; - if (!prop) - return smbios_add_string(ctx, dval); - if (sysinfo_id && ctx->dev) { char val[SMBIOS_STR_MAX]; @@ -236,6 +270,9 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, if (!ret) return smbios_add_string(ctx, val); } + if (!prop) + return smbios_add_string(ctx, dval); + if (IS_ENABLED(CONFIG_OF_CONTROL)) { const char *str = NULL; char str_dt[128] = { 0 }; @@ -331,15 +368,17 @@ static int smbios_write_type0(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type0 *t; - int len = sizeof(struct smbios_type0); + int len = sizeof(*t); t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type0)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->vendor = smbios_add_prop(ctx, NULL, "U-Boot"); + t->vendor = smbios_add_prop_si(ctx, NULL, SYSID_SM_BIOS_VENDOR, + "U-Boot"); - t->bios_ver = smbios_add_prop(ctx, "version", PLAIN_VERSION); + t->bios_ver = smbios_add_prop_si(ctx, "version", SYSID_SM_BIOS_VER, + PLAIN_VERSION); if (t->bios_ver) gd->smbios_version = ctx->last_str; log_debug("smbios_version = %p: '%s'\n", gd->smbios_version, @@ -348,7 +387,9 @@ static int smbios_write_type0(ulong *current, int handle, print_buffer((ulong)gd->smbios_version, gd->smbios_version, 1, strlen(gd->smbios_version) + 1, 0); #endif - t->bios_release_date = smbios_add_prop(ctx, NULL, U_BOOT_DMI_DATE); + t->bios_release_date = smbios_add_prop_si(ctx, NULL, + SYSID_SM_BIOS_REL_DATE, + U_BOOT_DMI_DATE); #ifdef CONFIG_ROM_SIZE if (CONFIG_ROM_SIZE < SZ_16M) { t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1; @@ -375,7 +416,7 @@ static int smbios_write_type0(ulong *current, int handle, t->ec_major_release = 0xff; t->ec_minor_release = 0xff; - len = t->length + smbios_string_table_len(ctx); + len = t->hdr.length + smbios_string_table_len(ctx); *current += len; unmap_sysmem(t); @@ -386,37 +427,38 @@ static int smbios_write_type1(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type1 *t; - int len = sizeof(struct smbios_type1); + int len = sizeof(*t); char *serial_str = env_get("serial#"); t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type1)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", SYSID_SM_SYSTEM_MANUFACTURER, NULL); t->product_name = smbios_add_prop_si(ctx, "product", - SYSID_SM_SYSTEM_PRODUCT, - NULL); - t->version = smbios_add_prop_si(ctx, "version", - SYSID_SM_SYSTEM_VERSION, + SYSID_SM_SYSTEM_PRODUCT, NULL); + t->version = smbios_add_prop_si(ctx, "version", SYSID_SM_SYSTEM_VERSION, NULL); if (serial_str) { t->serial_number = smbios_add_prop(ctx, NULL, serial_str); - strncpy((char *)t->uuid, serial_str, sizeof(t->uuid)); + strlcpy((char *)t->uuid, serial_str, sizeof(t->uuid)); } else { t->serial_number = smbios_add_prop_si(ctx, "serial", SYSID_SM_SYSTEM_SERIAL, NULL); } - t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN; - t->sku_number = smbios_add_prop_si(ctx, "sku", - SYSID_SM_SYSTEM_SKU, NULL); - t->family = smbios_add_prop_si(ctx, "family", - SYSID_SM_SYSTEM_FAMILY, NULL); - - len = t->length + smbios_string_table_len(ctx); + t->wakeup_type = smbios_get_val_si(ctx, "wakeup-type", + SYSID_SM_SYSTEM_WAKEUP, + SMBIOS_WAKEUP_TYPE_UNKNOWN); + t->sku_number = smbios_add_prop_si(ctx, "sku", SYSID_SM_SYSTEM_SKU, + NULL); + t->family = smbios_add_prop_si(ctx, "family", SYSID_SM_SYSTEM_FAMILY, + NULL); + + len = t->hdr.length + smbios_string_table_len(ctx); *current += len; unmap_sysmem(t); @@ -427,33 +469,53 @@ static int smbios_write_type2(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type2 *t; - int len = sizeof(struct smbios_type2); + int len = sizeof(*t); + u8 *eos_addr; + /* + * reserve the space for the dynamic bytes of contained object handles. + * TODO: len += <obj_handle_num> * SMBIOS_TYPE2_CON_OBJ_HANDLE_SIZE + * obj_handle_num can be from DT node "baseboard" or sysinfo driver. + */ t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type2)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); - smbios_set_eos(ctx, t->eos); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", SYSID_SM_BASEBOARD_MANUFACTURER, NULL); t->product_name = smbios_add_prop_si(ctx, "product", - SYSID_SM_BASEBOARD_PRODUCT, - NULL); + SYSID_SM_BASEBOARD_PRODUCT, NULL); t->version = smbios_add_prop_si(ctx, "version", - SYSID_SM_BASEBOARD_VERSION, - NULL); - + SYSID_SM_BASEBOARD_VERSION, NULL); t->serial_number = smbios_add_prop_si(ctx, "serial", - SYSID_SM_BASEBOARD_SERIAL, - NULL); + SYSID_SM_BASEBOARD_SERIAL, NULL); t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag", SYSID_SM_BASEBOARD_ASSET_TAG, NULL); - t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; - t->board_type = SMBIOS_BOARD_MOTHERBOARD; + t->feature_flags = smbios_get_val_si(ctx, "feature-flags", + SYSID_SM_BASEBOARD_FEATURE, 0); + + t->chassis_location = + smbios_add_prop_si(ctx, "chassis-location", + SYSID_SM_BASEBOARD_CHASSIS_LOCAT, NULL); + t->board_type = smbios_get_val_si(ctx, "board-type", + SYSID_SM_BASEBOARD_TYPE, + SMBIOS_BOARD_TYPE_UNKNOWN); + + /* + * TODO: + * Populate the Contained Object Handles if they exist + * t->number_contained_objects = <obj_handle_num>; + */ + t->chassis_handle = handle + 1; - len = t->length + smbios_string_table_len(ctx); + len = t->hdr.length + smbios_string_table_len(ctx); *current += len; unmap_sysmem(t); @@ -464,20 +526,77 @@ static int smbios_write_type3(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type3 *t; - int len = sizeof(struct smbios_type3); + int len = sizeof(*t); + u8 *eos_addr; + size_t elem_size = 0; + __maybe_unused u8 *elem_addr; + __maybe_unused u8 *sku_num_addr; + + /* + * reserve the space for the dynamic bytes of contained elements. + * TODO: elem_size = <element_count> * <element_record_length> + * element_count and element_record_length can be from DT node + * "chassis" or sysinfo driver. + */ + len += elem_size; t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type3)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); - smbios_set_eos(ctx, t->eos); - t->manufacturer = smbios_add_prop(ctx, "manufacturer", NULL); - t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; - t->bootup_state = SMBIOS_STATE_SAFE; - t->power_supply_state = SMBIOS_STATE_SAFE; - t->thermal_state = SMBIOS_STATE_SAFE; - t->security_status = SMBIOS_SECURITY_NONE; - - len = t->length + smbios_string_table_len(ctx); +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + elem_addr = (u8 *)t + offsetof(struct smbios_type3, sku_number); + sku_num_addr = elem_addr + elem_size; +#endif + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", + SYSID_SM_ENCLOSURE_MANUFACTURER, + NULL); + t->chassis_type = smbios_get_val_si(ctx, "chassis-type", + SYSID_SM_ENCLOSURE_TYPE, + SMBIOS_ENCLOSURE_UNKNOWN); + t->bootup_state = smbios_get_val_si(ctx, "bootup-state", + SYSID_SM_ENCLOSURE_BOOTUP, + SMBIOS_STATE_UNKNOWN); + t->power_supply_state = smbios_get_val_si(ctx, "power-supply-state", + SYSID_SM_ENCLOSURE_POW, + SMBIOS_STATE_UNKNOWN); + t->thermal_state = smbios_get_val_si(ctx, "thermal-state", + SYSID_SM_ENCLOSURE_THERMAL, + SMBIOS_STATE_UNKNOWN); + t->security_status = smbios_get_val_si(ctx, "security-status", + SYSID_SM_ENCLOSURE_SECURITY, + SMBIOS_SECURITY_UNKNOWN); + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + t->version = smbios_add_prop_si(ctx, "version", + SYSID_SM_ENCLOSURE_VERSION, NULL); + t->serial_number = smbios_add_prop_si(ctx, "serial", + SYSID_SM_ENCLOSURE_SERIAL, NULL); + t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag", + SYSID_SM_BASEBOARD_ASSET_TAG, + NULL); + t->oem_defined = smbios_get_val_si(ctx, "oem-defined", + SYSID_SM_ENCLOSURE_OEM, 0); + t->height = smbios_get_val_si(ctx, "height", + SYSID_SM_ENCLOSURE_HEIGHT, 0); + t->number_of_power_cords = + smbios_get_val_si(ctx, "number-of-power-cords", + SYSID_SM_ENCLOSURE_POWCORE_NUM, 0); + + /* + * TODO: Populate the Contained Element Record if they exist + * t->element_count = <element_num>; + * t->element_record_length = <element_len>; + */ + + *sku_num_addr = smbios_add_prop_si(ctx, "sku", SYSID_SM_ENCLOSURE_SKU, + NULL); +#endif + + len = t->hdr.length + smbios_string_table_len(ctx); *current += len; unmap_sysmem(t); @@ -490,6 +609,8 @@ static void smbios_write_type4_dm(struct smbios_type4 *t, u16 processor_family = SMBIOS_PROCESSOR_FAMILY_UNKNOWN; const char *vendor = NULL; const char *name = NULL; + __maybe_unused void *id_data = NULL; + __maybe_unused size_t id_size = 0; #ifdef CONFIG_CPU char processor_name[49]; @@ -511,46 +632,234 @@ static void smbios_write_type4_dm(struct smbios_type4 *t, name = processor_name; } #endif + if (processor_family == SMBIOS_PROCESSOR_FAMILY_UNKNOWN) + processor_family = + smbios_get_val_si(ctx, "family", + SYSID_SM_PROCESSOR_FAMILY, + SMBIOS_PROCESSOR_FAMILY_UNKNOWN); + + if (processor_family == SMBIOS_PROCESSOR_FAMILY_EXT) + t->processor_family2 = + smbios_get_val_si(ctx, "family2", + SYSID_SM_PROCESSOR_FAMILY2, + SMBIOS_PROCESSOR_FAMILY_UNKNOWN); + + t->processor_family = processor_family; + t->processor_manufacturer = + smbios_add_prop_si(ctx, "manufacturer", + SYSID_SM_PROCESSOR_MANUFACT, vendor); + t->processor_version = smbios_add_prop_si(ctx, "version", + SYSID_SM_PROCESSOR_VERSION, + name); + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + if (t->processor_id[0] || t->processor_id[1] || + sysinfo_get_data(ctx->dev, SYSID_SM_PROCESSOR_ID, &id_data, + &id_size)) + return; - t->processor_family = 0xfe; - t->processor_family2 = processor_family; - t->processor_manufacturer = smbios_add_prop(ctx, NULL, vendor); - t->processor_version = smbios_add_prop(ctx, NULL, name); + if (id_data && id_size == sizeof(t->processor_id)) + memcpy((u8 *)t->processor_id, id_data, id_size); +#endif } static int smbios_write_type4(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type4 *t; - int len = sizeof(struct smbios_type4); + int len = sizeof(*t); + __maybe_unused void *hdl; + __maybe_unused size_t hdl_size; t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type4)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL; + t->socket_design = smbios_add_prop_si(ctx, "socket-design", + SYSID_SM_PROCESSOR_SOCKET, NULL); + t->processor_type = smbios_get_val_si(ctx, "processor-type", + SYSID_SM_PROCESSOR_TYPE, + SMBIOS_PROCESSOR_TYPE_UNKNOWN); smbios_write_type4_dm(t, ctx); - t->status = SMBIOS_PROCESSOR_STATUS_ENABLED; - t->processor_upgrade = SMBIOS_PROCESSOR_UPGRADE_NONE; - t->l1_cache_handle = 0xffff; - t->l2_cache_handle = 0xffff; - t->l3_cache_handle = 0xffff; - len = t->length + smbios_string_table_len(ctx); + t->status = smbios_get_val_si(ctx, "processor-status", + SYSID_SM_PROCESSOR_STATUS, + SMBIOS_PROCESSOR_STATUS_UNKNOWN); + t->processor_upgrade = + smbios_get_val_si(ctx, "upgrade", SYSID_SM_PROCESSOR_UPGRADE, + SMBIOS_PROCESSOR_UPGRADE_UNKNOWN); + + t->l1_cache_handle = SMBIOS_CACHE_HANDLE_NONE; + t->l2_cache_handle = SMBIOS_CACHE_HANDLE_NONE; + t->l3_cache_handle = SMBIOS_CACHE_HANDLE_NONE; + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + t->voltage = smbios_get_val_si(ctx, "voltage", + SYSID_SM_PROCESSOR_VOLTAGE, 0); + t->external_clock = smbios_get_val_si(ctx, "external-clock", + SYSID_SM_PROCESSOR_EXT_CLOCK, 0); + t->max_speed = smbios_get_val_si(ctx, "max-speed", + SYSID_SM_PROCESSOR_MAX_SPEED, 0); + t->current_speed = smbios_get_val_si(ctx, "current-speed", + SYSID_SM_PROCESSOR_CUR_SPEED, 0); + + /* Read the cache handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_CACHE_HANDLE, &hdl, + &hdl_size) && + (hdl_size == SYSINFO_CACHE_LVL_MAX * sizeof(u16))) { + u16 *handle = (u16 *)hdl; + + if (*handle) + t->l1_cache_handle = *handle; + + handle++; + if (*handle) + t->l2_cache_handle = *handle; + + handle++; + if (*handle) + t->l3_cache_handle = *handle; + } + + t->serial_number = smbios_add_prop_si(ctx, "serial", + SYSID_SM_PROCESSOR_SN, NULL); + t->asset_tag = smbios_add_prop_si(ctx, "asset-tag", + SYSID_SM_PROCESSOR_ASSET_TAG, NULL); + t->part_number = smbios_add_prop_si(ctx, "part-number", + SYSID_SM_PROCESSOR_PN, NULL); + t->core_count = smbios_get_val_si(ctx, "core-count", + SYSID_SM_PROCESSOR_CORE_CNT, 0); + t->core_enabled = smbios_get_val_si(ctx, "core-enabled", + SYSID_SM_PROCESSOR_CORE_EN, 0); + t->thread_count = smbios_get_val_si(ctx, "thread-count", + SYSID_SM_PROCESSOR_THREAD_CNT, 0); + t->processor_characteristics = + smbios_get_val_si(ctx, "characteristics", + SYSID_SM_PROCESSOR_CHARA, + SMBIOS_PROCESSOR_UND); + t->core_count2 = smbios_get_val_si(ctx, "core-count2", + SYSID_SM_PROCESSOR_CORE_CNT2, 0); + t->core_enabled2 = smbios_get_val_si(ctx, "core-enabled2", + SYSID_SM_PROCESSOR_CORE_EN2, 0); + t->thread_count2 = smbios_get_val_si(ctx, "thread-count2", + SYSID_SM_PROCESSOR_THREAD_CNT2, 0); + t->thread_enabled = smbios_get_val_si(ctx, "thread-enabled", + SYSID_SM_PROCESSOR_THREAD_EN, 0); +#endif + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + +static int smbios_write_type7_1level(ulong *current, int handle, + struct smbios_ctx *ctx, int level) +{ + struct smbios_type7 *t; + int len = sizeof(*t); + void *hdl; + size_t hdl_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + fill_smbios_header(t, SMBIOS_CACHE_INFORMATION, len, handle); + smbios_set_eos(ctx, t->eos); + + t->socket_design = smbios_add_prop_si(ctx, "socket-design", + SYSID_SM_CACHE_SOCKET + level, + NULL); + t->config.data = smbios_get_val_si(ctx, "config", + SYSID_SM_CACHE_CONFIG + level, + (level - 1) | SMBIOS_CACHE_OP_UND); + t->max_size.data = smbios_get_val_si(ctx, "max-size", + SYSID_SM_CACHE_MAX_SIZE + level, + 0); + t->inst_size.data = smbios_get_val_si(ctx, "installed-size", + SYSID_SM_CACHE_INST_SIZE + level, + 0); + t->supp_sram_type.data = + smbios_get_val_si(ctx, "supported-sram-type", + SYSID_SM_CACHE_SUPSRAM_TYPE + level, + SMBIOS_CACHE_SRAM_TYPE_UNKNOWN); + t->curr_sram_type.data = + smbios_get_val_si(ctx, "current-sram-type", + SYSID_SM_CACHE_CURSRAM_TYPE + level, + SMBIOS_CACHE_SRAM_TYPE_UNKNOWN); + t->speed = smbios_get_val_si(ctx, "speed", SYSID_SM_CACHE_SPEED + level, + 0); + t->err_corr_type = smbios_get_val_si(ctx, "error-correction-type", + SYSID_SM_CACHE_ERRCOR_TYPE + level, + SMBIOS_CACHE_ERRCORR_UNKNOWN); + t->sys_cache_type = + smbios_get_val_si(ctx, "system-cache-type", + SYSID_SM_CACHE_SCACHE_TYPE + level, + SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN); + t->associativity = smbios_get_val_si(ctx, "associativity", + SYSID_SM_CACHE_ASSOC + level, + SMBIOS_CACHE_ASSOC_UNKNOWN); + t->max_size2.data = smbios_get_val_si(ctx, "max-size2", + SYSID_SM_CACHE_MAX_SIZE2 + level, + 0); + t->inst_size2.data = + smbios_get_val_si(ctx, "installed-size2", + SYSID_SM_CACHE_INST_SIZE2 + level, 0); + + /* Save the cache handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_CACHE_HANDLE, &hdl, + &hdl_size)) { + if (hdl_size == SYSINFO_CACHE_LVL_MAX * sizeof(u16)) + *((u16 *)hdl + level) = handle; + } + + len = t->hdr.length + smbios_string_table_len(ctx); *current += len; unmap_sysmem(t); return len; } +static int smbios_write_type7(ulong *current, int handle, + struct smbios_ctx *ctx) +{ + int len = 0; + int i, level; + ofnode parent = ctx->node; + struct smbios_ctx ctx_bak; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + /* Get the number of level */ + level = smbios_get_val_si(ctx, NULL, SYSID_SM_CACHE_LEVEL, 0); + if (level >= SYSINFO_CACHE_LVL_MAX) /* Error, return 0-length */ + return 0; + + for (i = 0; i <= level; i++) { + char buf[9] = ""; + + if (!snprintf(buf, sizeof(buf), "l%d-cache", i + 1)) + return 0; + ctx->subnode_name = buf; + ctx->node = ofnode_find_subnode(parent, ctx->subnode_name); + len += smbios_write_type7_1level(current, handle++, ctx, i); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + } + return len; +} + +#endif /* #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) */ + static int smbios_write_type32(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type32 *t; - int len = sizeof(struct smbios_type32); + int len = sizeof(*t); t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type32)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); @@ -564,10 +873,10 @@ static int smbios_write_type127(ulong *current, int handle, struct smbios_ctx *ctx) { struct smbios_type127 *t; - int len = sizeof(struct smbios_type127); + int len = sizeof(*t); t = map_sysmem(*current, len); - memset(t, 0, sizeof(struct smbios_type127)); + memset(t, 0, len); fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, handle); *current += len; @@ -582,7 +891,11 @@ static struct smbios_write_method smbios_write_funcs[] = { { smbios_write_type2, "baseboard", }, /* Type 3 must immediately follow type 2 due to chassis handle. */ { smbios_write_type3, "chassis", }, - { smbios_write_type4, }, +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + /* Type 7 must ahead of type 4 to get cache handles. */ + { smbios_write_type7, "cache", }, +#endif + { smbios_write_type4, "processor"}, { smbios_write_type32, }, { smbios_write_type127 }, }; @@ -599,7 +912,7 @@ ulong write_smbios_table(ulong addr) int i; ctx.node = ofnode_null(); - if (IS_ENABLED(CONFIG_OF_CONTROL) && CONFIG_IS_ENABLED(SYSINFO)) { + if (CONFIG_IS_ENABLED(SYSINFO)) { uclass_first_device(UCLASS_SYSINFO, &ctx.dev); if (ctx.dev) { int ret; diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index ad2b5ab0c32..bc750b7ca19 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -23,6 +23,27 @@ #include "tpm-utils.h" +static int tpm2_update_active_banks(struct udevice *dev) +{ + struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); + struct tpml_pcr_selection pcrs; + int ret, i; + + ret = tpm2_get_pcr_info(dev, &pcrs); + if (ret) + return ret; + + priv->active_bank_count = 0; + for (i = 0; i < pcrs.count; i++) { + if (!tpm2_is_active_bank(&pcrs.selection[i])) + continue; + priv->active_banks[priv->active_bank_count] = pcrs.selection[i].hash; + priv->active_bank_count++; + } + + return 0; +} + u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) { const u8 command_v2[12] = { @@ -41,7 +62,7 @@ u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) if (ret && ret != TPM2_RC_INITIALIZE) return ret; - return 0; + return tpm2_update_active_banks(dev); } u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test) @@ -69,8 +90,10 @@ u32 tpm2_auto_start(struct udevice *dev) rc = tpm2_self_test(dev, TPMI_YES); } + if (rc) + return rc; - return rc; + return tpm2_update_active_banks(dev); } u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw, @@ -197,7 +220,7 @@ u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm, if (!digest) return -EINVAL; - if (!tpm2_allow_extend(dev)) { + if (!tpm2_check_active_banks(dev)) { log_err("Cannot extend PCRs if all the TPM enabled algorithms are not supported\n"); return -EINVAL; } @@ -847,7 +870,7 @@ u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, return 0; } -bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection) +bool tpm2_is_active_bank(struct tpms_pcr_selection *selection) { int i; @@ -884,6 +907,18 @@ const char *tpm2_algorithm_name(enum tpm2_algorithms algo) return ""; } +bool tpm2_algorithm_supported(enum tpm2_algorithms algo) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { + if (hash_algo_list[i].hash_alg == algo) + return hash_algo_list[i].supported; + } + + return false; +} + u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo) { size_t i; @@ -896,7 +931,7 @@ u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo) return 0; } -bool tpm2_allow_extend(struct udevice *dev) +bool tpm2_check_active_banks(struct udevice *dev) { struct tpml_pcr_selection pcrs; size_t i; @@ -907,10 +942,33 @@ bool tpm2_allow_extend(struct udevice *dev) return false; for (i = 0; i < pcrs.count; i++) { - if (tpm2_is_active_pcr(&pcrs.selection[i]) && - !tpm2_algorithm_to_len(pcrs.selection[i].hash)) + if (tpm2_is_active_bank(&pcrs.selection[i]) && + !tpm2_algorithm_supported(pcrs.selection[i].hash)) return false; } return true; } + +void tpm2_print_active_banks(struct udevice *dev) +{ + struct tpml_pcr_selection pcrs; + size_t i; + int rc; + + rc = tpm2_get_pcr_info(dev, &pcrs); + if (rc) { + log_err("Can't retrieve active PCRs\n"); + return; + } + + for (i = 0; i < pcrs.count; i++) { + if (tpm2_is_active_bank(&pcrs.selection[i])) { + const char *str; + + str = tpm2_algorithm_name(pcrs.selection[i].hash); + if (str) + log_info("%s\n", str); + } + } +} diff --git a/lib/tpm_tcg2.c b/lib/tpm_tcg2.c index 7f868cc8837..4134d93a358 100644 --- a/lib/tpm_tcg2.c +++ b/lib/tpm_tcg2.c @@ -20,38 +20,36 @@ #include <linux/unaligned/le_byteshift.h> #include "tpm-utils.h" -int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, - u32 *pcr_banks) +int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_bank, u32 *active_bank, + u32 *bank_num) { - u8 response[(sizeof(struct tpms_capability_data) - - offsetof(struct tpms_capability_data, data))]; struct tpml_pcr_selection pcrs; size_t i; u32 ret; - *supported_pcr = 0; - *active_pcr = 0; - *pcr_banks = 0; - memset(response, 0, sizeof(response)); + *supported_bank = 0; + *active_bank = 0; + *bank_num = 0; ret = tpm2_get_pcr_info(dev, &pcrs); if (ret) return ret; for (i = 0; i < pcrs.count; i++) { - u32 hash_mask = tcg2_algorithm_to_mask(pcrs.selection[i].hash); + struct tpms_pcr_selection *sel = &pcrs.selection[i]; + u32 hash_mask = tcg2_algorithm_to_mask(sel->hash); - if (hash_mask) { - *supported_pcr |= hash_mask; - if (tpm2_is_active_pcr(&pcrs.selection[i])) - *active_pcr |= hash_mask; - } else { - printf("%s: unknown algorithm %x\n", __func__, - pcrs.selection[i].hash); - } + if (tpm2_algorithm_supported(sel->hash)) + *supported_bank |= hash_mask; + else + log_warning("%s: unknown algorithm %x\n", __func__, + sel->hash); + + if (tpm2_is_active_bank(sel)) + *active_bank |= hash_mask; } - *pcr_banks = pcrs.count; + *bank_num = pcrs.count; return 0; } @@ -95,57 +93,64 @@ u32 tcg2_event_get_size(struct tpml_digest_values *digest_list) int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, struct tpml_digest_values *digest_list) { + struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); u8 final[sizeof(union tpmu_ha)]; +#if IS_ENABLED(CONFIG_SHA256) sha256_context ctx_256; +#endif +#if IS_ENABLED(CONFIG_SHA512) sha512_context ctx_512; +#endif +#if IS_ENABLED(CONFIG_SHA1) sha1_context ctx; - u32 active; +#endif size_t i; u32 len; - int rc; - - rc = tcg2_get_active_pcr_banks(dev, &active); - if (rc) - return rc; digest_list->count = 0; - for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { - if (!(active & hash_algo_list[i].hash_mask)) - continue; + for (i = 0; i < priv->active_bank_count; i++) { - switch (hash_algo_list[i].hash_alg) { + switch (priv->active_banks[i]) { +#if IS_ENABLED(CONFIG_SHA1) case TPM2_ALG_SHA1: sha1_starts(&ctx); sha1_update(&ctx, input, length); sha1_finish(&ctx, final); len = TPM2_SHA1_DIGEST_SIZE; break; +#endif +#if IS_ENABLED(CONFIG_SHA256) case TPM2_ALG_SHA256: sha256_starts(&ctx_256); sha256_update(&ctx_256, input, length); sha256_finish(&ctx_256, final); len = TPM2_SHA256_DIGEST_SIZE; break; +#endif +#if IS_ENABLED(CONFIG_SHA384) case TPM2_ALG_SHA384: sha384_starts(&ctx_512); sha384_update(&ctx_512, input, length); sha384_finish(&ctx_512, final); len = TPM2_SHA384_DIGEST_SIZE; break; +#endif +#if IS_ENABLED(CONFIG_SHA512) case TPM2_ALG_SHA512: sha512_starts(&ctx_512); sha512_update(&ctx_512, input, length); sha512_finish(&ctx_512, final); len = TPM2_SHA512_DIGEST_SIZE; break; +#endif default: printf("%s: unsupported algorithm %x\n", __func__, - hash_algo_list[i].hash_alg); + priv->active_banks[i]); continue; } digest_list->digests[digest_list->count].hash_alg = - hash_algo_list[i].hash_alg; + priv->active_banks[i]; memcpy(&digest_list->digests[digest_list->count].digest, final, len); digest_list->count++; @@ -216,37 +221,17 @@ static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index, static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog) { + struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); struct tcg_efi_spec_id_event *ev; struct tcg_pcr_event *log; u32 event_size; u32 count = 0; u32 log_size; - u32 active; size_t i; u16 len; - int rc; - - rc = tcg2_get_active_pcr_banks(dev, &active); - if (rc) - return rc; + count = priv->active_bank_count; event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes); - for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { - if (!(active & hash_algo_list[i].hash_mask)) - continue; - - switch (hash_algo_list[i].hash_alg) { - case TPM2_ALG_SHA1: - case TPM2_ALG_SHA256: - case TPM2_ALG_SHA384: - case TPM2_ALG_SHA512: - count++; - break; - default: - continue; - } - } - event_size += 1 + (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count); log_size = offsetof(struct tcg_pcr_event, event) + event_size; @@ -273,19 +258,11 @@ static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog) ev->uintn_size = sizeof(size_t) / sizeof(u32); put_unaligned_le32(count, &ev->number_of_algorithms); - count = 0; - for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { - if (!(active & hash_algo_list[i].hash_mask)) - continue; - - len = hash_algo_list[i].hash_len; - if (!len) - continue; - - put_unaligned_le16(hash_algo_list[i].hash_alg, - &ev->digest_sizes[count].algorithm_id); - put_unaligned_le16(len, &ev->digest_sizes[count].digest_size); - count++; + for (i = 0; i < count; ++i) { + len = tpm2_algorithm_to_len(priv->active_banks[i]); + put_unaligned_le16(priv->active_banks[i], + &ev->digest_sizes[i].algorithm_id); + put_unaligned_le16(len, &ev->digest_sizes[i].digest_size); } *((u8 *)ev + (event_size - 1)) = 0; @@ -396,7 +373,6 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) u16 len; int rc; u32 i; - u16 j; if (elog->log_size <= offsetof(struct tcg_pcr_event, event)) return 0; @@ -435,40 +411,51 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) if (evsz != calc_size) return 0; - rc = tcg2_get_active_pcr_banks(dev, &active); - if (rc) - return rc; - + /* + * Go through the algorithms the EventLog contains. If the EventLog + * algorithms don't match the active TPM ones exit and report the + * erroneous banks. + * We've already checked that U-Boot supports all the enabled TPM + * algorithms, so just check the EvenLog against the TPM active ones. + */ digest_list.count = 0; log_active = 0; - for (i = 0; i < count; ++i) { algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id); mask = tcg2_algorithm_to_mask(algo); - if (!(active & mask)) - return 0; - switch (algo) { case TPM2_ALG_SHA1: case TPM2_ALG_SHA256: case TPM2_ALG_SHA384: case TPM2_ALG_SHA512: len = get_unaligned_le16(&event->digest_sizes[i].digest_size); - if (tpm2_algorithm_to_len(algo) != len) - return 0; + if (tpm2_algorithm_to_len(algo) != len) { + log_err("EventLog invalid algorithm length\n"); + return -1; + } digest_list.digests[digest_list.count++].hash_alg = algo; break; default: - return 0; + /* + * We can ignore this if the TPM PCRs is not extended + * by the previous bootloader. But for now just exit + */ + log_err("EventLog has unsupported algorithm 0x%x\n", + algo); + return -1; } - log_active |= mask; } - /* Ensure the previous firmware extended all the PCRs. */ - if (log_active != active) - return 0; + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + /* If the EventLog and active algorithms don't match exit */ + if (log_active != active) { + log_err("EventLog doesn't contain all active PCR banks\n"); + return -1; + } /* Read PCR0 to check if previous firmware extended the PCRs or not. */ rc = tcg2_pcr_read(dev, 0, &digest_list); @@ -476,17 +463,13 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) return rc; for (i = 0; i < digest_list.count; ++i) { - len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg); - for (j = 0; j < len; ++j) { - if (digest_list.digests[i].digest.sha512[j]) - break; - } + u8 hash_buf[TPM2_SHA512_DIGEST_SIZE] = { 0 }; + u16 hash_alg = digest_list.digests[i].hash_alg; - /* PCR is non-zero; it has been extended, so skip extending. */ - if (j != len) { + if (memcmp((u8 *)&digest_list.digests[i].digest, hash_buf, + tpm2_algorithm_to_len(hash_alg))) digest_list.count = 0; - break; - } + } return tcg2_replay_eventlog(elog, dev, &digest_list, @@ -569,11 +552,36 @@ int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, bool ignore_existing_log) { struct tcg2_event_log log; - int rc; + int rc, i; elog->log_position = 0; elog->found = false; + /* + * Make sure U-Boot is compiled with all the active PCRs + * since we are about to create an EventLog and we won't + * measure anything if the PCR banks don't match + */ + if (!tpm2_check_active_banks(dev)) { + log_err("Cannot create EventLog\n"); + log_err("Mismatch between U-Boot and TPM hash algos\n"); + log_info("TPM:\n"); + tpm2_print_active_banks(dev); + log_info("U-Boot:\n"); + for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) { + const struct digest_info *algo = &hash_algo_list[i]; + const char *str; + + if (!algo->supported) + continue; + + str = tpm2_algorithm_name(algo->hash_alg); + if (str) + log_info("%s\n", str); + } + return -EINVAL; + } + rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size); if (!rc) { log.log_position = 0; diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c index 6c0d2d7e4df..14ebe6b42e7 100644 --- a/test/dm/sysinfo.c +++ b/test/dm/sysinfo.c @@ -19,6 +19,9 @@ static int dm_test_sysinfo(struct unit_test_state *uts) bool called_detect = false; char str[64]; int i; + void *data = NULL; + size_t data_size = 0; + u32 gdata[] = {0xabcdabcd, 0xdeadbeef}; ut_assertok(sysinfo_get(&sysinfo)); ut_assert(sysinfo); @@ -57,6 +60,9 @@ static int dm_test_sysinfo(struct unit_test_state *uts) str)); ut_assertok(strcmp(str, "Yuggoth")); + ut_assertok(sysinfo_get_data(sysinfo, DATA_TEST, &data, &data_size)); + ut_assertok(memcmp(gdata, data, data_size)); + return 0; } DM_TEST(dm_test_sysinfo, UTF_SCAN_PDATA | UTF_SCAN_FDT); diff --git a/test/py/tests/test_smbios.py b/test/py/tests/test_smbios.py index 82b0b689830..0405a9b9d38 100644 --- a/test/py/tests/test_smbios.py +++ b/test/py/tests/test_smbios.py @@ -32,10 +32,26 @@ def test_cmd_smbios_sandbox(u_boot_console): """Run the smbios command on the sandbox""" output = u_boot_console.run_command('smbios') assert 'DMI type 0,' in output - assert 'String 1: U-Boot' in output + assert 'Vendor: U-Boot' in output assert 'DMI type 1,' in output assert 'Manufacturer: sandbox' in output assert 'DMI type 2,' in output assert 'DMI type 3,' in output assert 'DMI type 4,' in output assert 'DMI type 127,' in output + +@pytest.mark.buildconfigspec('cmd_smbios') +@pytest.mark.buildconfigspec('sysinfo_smbios') +@pytest.mark.buildconfigspec('generate_smbios_table_verbose') +def test_cmd_smbios_sysinfo_verbose(u_boot_console): + """Run the smbios command""" + output = u_boot_console.run_command('smbios') + assert 'DMI type 0,' in output + assert 'Vendor: U-Boot' in output + assert 'DMI type 1,' in output + assert 'Manufacturer: linux' in output + assert 'DMI type 2,' in output + assert 'DMI type 3,' in output + assert 'DMI type 7,' in output + assert 'DMI type 4,' in output + assert 'DMI type 127,' in output |