diff options
286 files changed, 2976 insertions, 9930 deletions
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds index f83988fd7e6..b7af29183a9 100644 --- a/arch/arm/cpu/arm1136/u-boot-spl.lds +++ b/arch/arm/cpu/arm1136/u-boot-spl.lds @@ -33,11 +33,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } + _end = .; .bss : { diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 7e20448f810..7c6309246f8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -49,11 +49,7 @@ SECTIONS __bss_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .dynsym _image_binary_end : { *(.dynsym) } diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index ef8af67e11c..215cedd69a8 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -53,12 +53,7 @@ SECTIONS . = ALIGN(8); __image_copy_end = .; - - .end : { - . = ALIGN(8); - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : { diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 9ed62395a9c..eee463a1b1c 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -53,12 +53,8 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - _image_binary_end = .; + _end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 707b19795f0..2f50087f57a 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -166,11 +166,7 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; /* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 27f38908f26..b524c885f21 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1179,11 +1179,8 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \ k3-am654-icssg2.dtbo -dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ - k3-j721e-r5-common-proc-board.dtb \ - k3-j7200-common-proc-board.dtb \ +dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ k3-j7200-r5-common-proc-board.dtb \ - k3-j721e-sk.dtb \ k3-j721e-r5-sk.dtb \ k3-j721e-beagleboneai64.dtb \ k3-j721e-r5-beagleboneai64.dtb diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index dd5b335ed2e..1766adc5d4c 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -214,6 +214,33 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See beagleplay.h +#define BEAGLEPLAY_SPL_IMAGE_GUID_STR "b2e7cc49-1a5a-4036-ae01-3387c3bef657" +#define BEAGLEPLAY_UBOOT_IMAGE_GUID_STR "92c92b11-a7ee-486f-aaa2-713d84425b0e" + +&capsule_tispl { + efi-capsule { + image-guid = BEAGLEPLAY_SPL_IMAGE_GUID_STR; + + blob { + filename = "tispl.bin_unsigned"; + }; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = BEAGLEPLAY_UBOOT_IMAGE_GUID_STR; + + blob { + filename = "u-boot.img_unsigned"; + }; + }; +}; + #endif &main_bcdma { diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9db58f093c8..162d4800b17 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -114,3 +114,18 @@ }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See beagleplay.h +#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR "0e225a09-f720-4d57-9120-e28f737f5a5e" + +&capsule_tiboot3 { + efi-capsule { + image-guid = BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR; + + blob { + filename = "tiboot3-am62x-gp-evm.bin"; + }; + }; +}; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index db3a3e91b08..534eb14795b 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -137,6 +137,17 @@ }; }; +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See am62x_evm.h +#define AM62X_SK_TIBOOT3_IMAGE_GUID_STR "abcb83d2-9cb6-4351-b8f1-6494bbe3700a" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM62X_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + #endif #ifdef CONFIG_TARGET_AM625_A53_EVM @@ -149,6 +160,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; @@ -452,4 +464,23 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See am62x_evm.h +#define AM62X_SK_SPL_IMAGE_GUID_STR "aee355fc-bf97-4264-8c82-437255efdc1d" +#define AM62X_SK_UBOOT_IMAGE_GUID_STR "28ab8c6c-fca8-41d3-8ea1-5f171b7d2929" + +&capsule_tispl { + efi-capsule { + image-guid = AM62X_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM62X_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index 841541bb243..5062447547b 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 - * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01 + * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -10,9 +10,11 @@ * Number of Ranks: 1 */ + #define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 #define DDRSS_CTL_0_DATA 0x00000B00 @@ -848,7 +850,7 @@ #define DDRSS_PHY_62_DATA 0x00000000 #define DDRSS_PHY_63_DATA 0x00000000 #define DDRSS_PHY_64_DATA 0x00000000 -#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_65_DATA 0x00000104 #define DDRSS_PHY_66_DATA 0x00000000 #define DDRSS_PHY_67_DATA 0x00000000 #define DDRSS_PHY_68_DATA 0x00000000 @@ -1104,7 +1106,7 @@ #define DDRSS_PHY_318_DATA 0x00000000 #define DDRSS_PHY_319_DATA 0x00000000 #define DDRSS_PHY_320_DATA 0x00000000 -#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_321_DATA 0x00000104 #define DDRSS_PHY_322_DATA 0x00000000 #define DDRSS_PHY_323_DATA 0x00000000 #define DDRSS_PHY_324_DATA 0x00000000 diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 6ccc8b5834c..0658b00ff0b 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -152,6 +152,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index dea14945bf5..eca532d710c 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -59,6 +59,17 @@ }; }; +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See am62px_evm.h +#define AM62PX_SK_TIBOOT3_IMAGE_GUID_STR "b08471b7-be2d-4489-87a1-cab28a0cf743" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM62PX_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + #endif /* CONFIG_TARGET_AM62P5_R5_EVM */ #if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM) @@ -72,6 +83,7 @@ blob-ext { filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; @@ -170,4 +182,22 @@ }; }; +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See am62px_evm.h +#define AM62PX_SK_SPL_IMAGE_GUID_STR "d02ed781-6d71-4c1a-a999-3c6a41c36324" +#define AM62PX_SK_UBOOT_IMAGE_GUID_STR "7e6aea51-965c-44ab-b388-daeb03b54f66" + +&capsule_tispl { + efi-capsule { + image-guid = AM62PX_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM62PX_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif /* CONFIG_TARGET_AM62P5_A53_EVM */ diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index 37817ba60d2..f768c4d946d 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -114,6 +114,17 @@ }; }; +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See am64x_evm.h +#define AM64X_SK_TIBOOT3_IMAGE_GUID_STR "ede0a0d5-9116-4bfb-aa54-09e97b5afe1a" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM64X_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + #endif #ifdef CONFIG_TARGET_AM642_A53_EVM @@ -373,4 +384,23 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See am64x_evm.h +#define AM64X_SK_SPL_IMAGE_GUID_STR "77678f5c-64d4-4910-ad75-52c9d95cdb1d" +#define AM64X_SK_UBOOT_IMAGE_GUID_STR "c6ad43a9-7d31-4f5d-83e9-b8efecae05bf" + +&capsule_tispl { + efi-capsule { + image-guid = AM64X_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM64X_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-binman-capsule-r5.dtsi b/arch/arm/dts/k3-binman-capsule-r5.dtsi new file mode 100644 index 00000000000..959ceb7479d --- /dev/null +++ b/arch/arm/dts/k3-binman-capsule-r5.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&binman { + capsule_tiboot3: capsule-tiboot3 { + filename = "tiboot3-capsule.bin"; + efi-capsule { + image-index = <0x1>; + image-guid = "00000000-0000-0000-0000-000000000000"; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "tiboot3.bin"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-binman-capsule.dtsi b/arch/arm/dts/k3-binman-capsule.dtsi new file mode 100644 index 00000000000..17e83c9fa44 --- /dev/null +++ b/arch/arm/dts/k3-binman-capsule.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&binman { + capsule_tispl: capsule-tispl { + filename = "tispl-capsule.bin"; + efi-capsule { + image-index = <0x2>; + image-guid = "00000000-0000-0000-0000-000000000000"; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "tispl.bin"; + }; + }; + }; +}; + +&binman { + capsule_uboot: capsule-uboot { + filename = "uboot-capsule.bin"; + efi-capsule { + image-index = <0x3>; + image-guid = "00000000-0000-0000-0000-000000000000"; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "u-boot.img"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index e8020fec2dc..ef7d4594f69 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -273,7 +273,7 @@ #ifdef CONFIG_TARGET_J7200_A72_EVM -#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb" +#define SPL_J7200_EVM_DTB "spl/dts/ti/k3-j7200-common-proc-board.dtb" #define J7200_EVM_DTB "u-boot.dtb" &binman { @@ -281,6 +281,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 485f17c5f06..045ef170e17 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -26,8 +26,12 @@ &cbass_mcu_wakeup { bootph-all; - chipid@43000014 { + wkup_conf: bus@43000000 { bootph-all; + + chipid: chipid@14 { + bootph-all; + }; }; }; @@ -40,14 +44,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts deleted file mode 100644 index cee2b4b0eb8..00000000000 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ /dev/null @@ -1,396 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200-som-p0.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy.h> - -#include "k3-serdes.h" - -/ { - compatible = "ti,j7200-evm", "ti,j7200"; - model = "Texas Instruments J7200 EVM"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial5 = &main_uart3; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: gpio-regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; -}; - -&wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ - >; - }; -}; - -&wkup_pmx2 { - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ - >; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ - J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ - J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ - J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ - J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ - >; - }; - - main_uart3_pins_default: main-uart3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ - J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ - J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ - J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ - J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ - J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ - J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ - J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ - J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ - >; - }; -}; - -&main_pmx1 { - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; - clock-frequency = <96000000>; -}; - -&main_uart0 { - status = "okay"; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - status = "okay"; - /* Default pinmux */ - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_uart2 { - /* MAIN UART 2 is used by R5F firmware */ - status = "reserved"; -}; - -&main_uart3 { - /* Shared with MCAN Interface */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart3_pins_default>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_gpio_pins_default>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/* - * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be - * swapped on the CPB. - * - * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. - * The i2c1 of the CPB (as it is labeled) is not connected to j7200. - */ -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", - "UB926_LOCK", "UB926_PWR_SW_CNTRL", - "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; - }; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&serdes_ln_ctrl { - idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, - <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_qsgmii_link: phy@1 { - reg = <2>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_QSGMII>; - resets = <&serdes_wiz0 3>; - }; -}; - -&pcie1_rc { - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie1_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi deleted file mode 100644 index 264913f8328..00000000000 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ /dev/null @@ -1,1284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family Main Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - serdes_refclk: serdes-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x100000>; - - atf-sram@0 { - reg = <0x00 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ - }; - - cpsw0_phy_gmii_sel: phy@4044 { - compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; - ti,qsgmii-main-ports = <1>; - reg = <0x4044 0x10>; - #phy-cells = <1>; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <199>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x310e0000 0x00 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>, - <0x00 0x31080000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x310d0000 0x00 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - cpsw0: ethernet@c000000 { - compatible = "ti,j7200-cpswxg-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0xc000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; - clocks = <&k3_clks 19 33>; - clock-names = "fck"; - power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xca00>, - <&main_udmap 0xca01>, - <&main_udmap 0xca02>, - <&main_udmap 0xca03>, - <&main_udmap 0xca04>, - <&main_udmap 0xca05>, - <&main_udmap 0xca06>, - <&main_udmap 0xca07>, - <&main_udmap 0x4a00>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - cpsw0_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - status = "disabled"; - }; - - cpsw0_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - status = "disabled"; - }; - - cpsw0_port3: port@3 { - reg = <3>; - ti,mac-only; - label = "port3"; - status = "disabled"; - }; - - cpsw0_port4: port@4 { - reg = <4>; - ti,mac-only; - label = "port4"; - status = "disabled"; - }; - }; - - cpsw5g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 19 33>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 19 16>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x0 0x104200 0x0 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x000001ff>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x0 0x104280 0x0 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x10c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c11c 0x00 0xc>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2000000 0x00 0x100>; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 1>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2010000 0x00 0x100>; - interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 1>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2020000 0x00 0x100>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 1>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2030000 0x00 0x100>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 1>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2040000 0x00 0x100>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 1>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2050000 0x00 0x100>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 1>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2060000 0x00 0x100>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 1>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - status = "disabled"; - }; - - serdes_wiz0: wiz@5060000 { - compatible = "ti,j721e-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <4>; - #reset-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; - - assigned-clocks = <&k3_clks 292 85>; - assigned-clock-parents = <&k3_clks 292 89>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_pll0_refclk"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_pll1_refclk"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_refclk_dig"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - serdes0: serdes@5060000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&wiz0_pll0_refclk>; - clock-names = "refclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - cdns,no-bar-match-nbits = <64>; - vendor-id = <0x104c>; - device-id = <0xb00f>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - cdns,phyrst-a-enable; - }; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <145>, <146>, <147>, <148>, - <149>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00610000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <154>, <155>, <156>, <157>, - <158>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00620000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <163>, <164>, <165>, <166>, - <167>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00630000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <172>, <173>, <174>, <175>, - <176>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 266 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 267 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 268 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 269 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 270 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 271 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 272 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 273 1>; - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 49 1>; - assigned-clock-parents = <&k3_clks 49 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; - assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 51 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 51 1>; - assigned-clock-parents = <&k3_clks 51 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 52 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; - assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 53 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 53 1>; - assigned-clock-parents = <&k3_clks 53 2>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 54 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; - assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 55 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 55 1>; - assigned-clock-parents = <&k3_clks 55 2>; - power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 57 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; - assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 58 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 58 1>; - assigned-clock-parents = <&k3_clks 58 2>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 59 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; - assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; - power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 60 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 60 1>; - assigned-clock-parents = <&k3_clks 60 2>; - power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 62 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; - assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; - power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; - assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; - assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; - assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; - assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j7200-r5f"; - reg = <0x5c00000 0x00010000>, - <0x5c10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 245 1>; - firmware-name = "j7200-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j7200-r5f"; - reg = <0x5d00000 0x00008000>, - <0x5d10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 246 1>; - firmware-name = "j7200-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <656>, <657>; - }; -}; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi deleted file mode 100644 index 3fc588b848c..00000000000 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_timer0: timer@40400000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer1: timer@40410000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; - assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer2: timer@40420000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer3: timer@40430000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; - assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer4: timer@40440000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer5: timer@40450000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; - assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer6: timer@40460000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer7: timer@40470000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; - assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer8: timer@40480000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer9: timer@40490000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; - assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x40f00000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x0 0x40f04200 0x0 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x0 0x40f04280 0x0 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; - status = "reserved"; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x34>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x8>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c068 0x00 0xec>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx3: pinctrl@4301c174 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c174 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42110000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <85>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42100000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <85>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>, - <0x00 0x28440000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", - "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x2a480000 0x0 0x80000>, - <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0x46000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 1>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 1>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 1>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 274 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 275 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 0>; - status = "disabled"; - }; - - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x47000000 0x00 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - }; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40200000 0x00 0x1000>; - interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j7200-r5f"; - reg = <0x41000000 0x00010000>, - <0x41010000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <250>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 250 1>; - firmware-name = "j7200-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j7200-r5f"; - reg = <0x41400000 0x00008000>, - <0x41410000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <251>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 251 1>; - firmware-name = "j7200-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_crypto: crypto@40900000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, - <&mcu_udmap 0x7503>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@40910000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x40910000 0x00 0x7d>; - interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; /* Used by OP-TEE */ - }; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0x42040000 0x00 0x350>, - <0x00 0x42050000 0x00 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi deleted file mode 100644 index 5a300d4c8ba..00000000000 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x00 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a4000000 { - reg = <0x00 0xa4000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - >; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "hbmc.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "hbmc.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "hbmc.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "hbmc.env"; - reg = <0x700000 0x40000>; - }; - - partition@800000 { - label = "hbmc.rootfs"; - reg = <0x800000 0x3800000>; - }; - }; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp_som: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", - "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", - "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", - "GPIO_LIN_EN", "CAN_STB"; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "ospi.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "ospi.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "ospi.env"; - reg = <0x700000 0x40000>; - }; - - partition@740000 { - label = "ospi.env.backup"; - reg = <0x740000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j7200-thermal.dtsi b/arch/arm/dts/k3-j7200-thermal.dtsi deleted file mode 100644 index e7e3a643a6f..00000000000 --- a/arch/arm/dts/k3-j7200-thermal.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - mcu_thermal: mcu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup_crit: wkup-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - mpu_thermal: mpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu_crit: mpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main_thermal: main-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - c7x_crit: c7x-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi deleted file mode 100644 index ef73e6d7e85..00000000000 --- a/arch/arm/dts/k3-j7200.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family - * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 J7200 SoC"; - compatible = "ti,j7200"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ - }; - }; - - #include "k3-j7200-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j7200-main.dtsi" -#include "k3-j7200-mcu-wakeup.dtsi" diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index e202ae16644..884f44239e1 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -351,4 +351,27 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See beagleboneai64.h +#define BEAGLEBONEAI64_SPL_IMAGE_GUID_STR "83447222-1e26-40cd-a395-b7de0957e875" +#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR "4249ff77-c17d-4eb7-a1db-45aa9887d49e" + +&capsule_tispl { + efi-capsule { + image-guid = BEAGLEBONEAI64_SPL_IMAGE_GUID_STR; + + blob { + filename = "tispl.bin_unsigned"; + }; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 1514d897634..0d607296f0e 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -295,21 +295,49 @@ }; }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See j721e_evm.h +#define J721E_SK_TIBOOT3_IMAGE_GUID_STR "e672b518-7cd7-4014-bd8d-40724d0ad4dc" +#define J721E_SK_SYSFW_IMAGE_GUID_STR "6fd10680-361b-431f-80aa-899455819e11" + +&capsule_tiboot3 { + efi-capsule { + image-guid = J721E_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + +&binman { + capsule-sysfw { + filename = "sysfw-capsule.bin"; + efi-capsule { + image-index = <0x4>; + image-guid = J721E_SK_SYSFW_IMAGE_GUID_STR; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "sysfw.itb"; + }; + }; + }; +}; + #endif #ifdef CONFIG_TARGET_J721E_A72_EVM -#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb" -#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" - +#define SPL_J721E_EVM_DTB "spl/dts/ti/k3-j721e-common-proc-board.dtb" #define J721E_EVM_DTB "u-boot.dtb" -#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb" &binman { ti-dm { filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { @@ -449,28 +477,13 @@ arch = "arm"; compression = "none"; ti-secure { - content = <&spl_j721e_evm_dtb>; + content = <&spl_j721e_dtb>; keyfile = "custMpk.pem"; }; - spl_j721e_evm_dtb: blob-ext { + spl_j721e_dtb: blob-ext { filename = SPL_J721E_EVM_DTB; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_j721e_sk_dtb>; - keyfile = "custMpk.pem"; - - }; - spl_j721e_sk_dtb: blob-ext { - filename = SPL_J721E_SK_DTB; - }; - }; }; configurations { @@ -482,13 +495,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -510,35 +516,17 @@ arch = "arm"; compression = "none"; ti-secure { - content = <&j721e_evm_dtb>; + content = <&j721e_dtb>; keyfile = "custMpk.pem"; }; - j721e_evm_dtb: blob-ext { + j721e_dtb: blob-ext { filename = J721E_EVM_DTB; }; hash { algo = "crc32"; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&j721e_sk_dtb>; - keyfile = "custMpk.pem"; - - }; - j721e_sk_dtb: blob-ext { - filename = J721E_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; }; configurations { @@ -550,13 +538,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; @@ -579,20 +560,10 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_j721e_dtb_unsigned: blob { filename = SPL_J721E_EVM_DTB; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_J721E_SK_DTB; - }; - }; }; configurations { @@ -604,13 +575,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -631,26 +595,13 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + j721e_dtb_unsigned: blob { filename = J721E_EVM_DTB; }; hash { algo = "crc32"; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = J721E_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; }; configurations { @@ -662,15 +613,27 @@ loadables = "uboot"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See j721e_evm.h +#define J721E_SK_SPL_IMAGE_GUID_STR "86f710ad-10cf-46ea-ac67-856ae06efad2" +#define J721E_SK_UBOOT_IMAGE_GUID_STR "81b58fb0-3b00-4add-a20a-c185bbaca1ed" + +&capsule_tispl { + efi-capsule { + image-guid = J721E_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = J721E_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index aa919b40702..1b119f27357 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -15,10 +15,10 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -30,14 +30,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts deleted file mode 100644 index fe5207ac7d8..00000000000 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ /dev/null @@ -1,976 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * - * Product Link: https://www.ti.com/tool/J721EXCPXEVM - */ - -/dts-v1/; - -#include "k3-j721e-som-p0.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> - -/ { - compatible = "ti,j721e-evm", "ti,j721e"; - model = "Texas Instruments J721e EVM"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial6 = &main_uart4; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; - - sw10: switch-10 { - label = "GPIO Key USER1"; - linux,code = <BTN_0>; - gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; - }; - - sw11: switch-11 { - label = "GPIO Key USER2"; - linux,code = <BTN_1>; - gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; - }; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LMS140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: gpio-regulator-TLV71033 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tlv71033"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - sound0: sound-0 { - compatible = "ti,j721e-cpb-audio"; - model = "j721e-cpb"; - - ti,cpb-mcasp = <&mcasp10>; - ti,cpb-codec = <&pcm3168a_1>; - - clocks = <&k3_clks 184 1>, - <&k3_clks 184 2>, <&k3_clks 184 4>, - <&k3_clks 157 371>, - <&k3_clks 157 400>, <&k3_clks 157 401>; - clock-names = "cpb-mcasp-auxclk", - "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", - "cpb-codec-scki", - "cpb-codec-scki-48000", "cpb-codec-scki-44100"; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; - enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver3: can-phy2 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; - enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - }; - - transceiver4: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan2_gpio_pins_default>; - standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; - }; - - dp_pwr_3v3: regulator-dp-pwr { - compatible = "regulator-fixed"; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ - J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ - J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ - >; - }; - - main_uart2_pins_default: main-uart2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ - J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ - >; - }; - - main_uart4_pins_default: main-uart4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ - J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ - >; - }; - - sw10_button_pins_default: sw10-button-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ - >; - }; - - main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_i2c6_pins_default: main-i2c6-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ - J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ - >; - }; - - mcasp10_pins_default: mcasp10-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ - J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ - J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ - J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ - J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ - J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ - J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ - J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ - J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ - >; - }; - - audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ - >; - }; - - main_mcan0_pins_default: main-mcan0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ - J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ - >; - }; - - main_mcan2_pins_default: main-mcan2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ - J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ - >; - }; - - main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ - >; - }; -}; - -&wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - sw11_button_pins_default: sw11-button-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ - J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ - J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ - J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ - J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ - J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ - J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ - J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ - J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ - J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart2_pins_default>; -}; - -&main_uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart4_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_gpio_pins_default>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&main_gpio1 { - status = "okay"; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD/MMC */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&usb_serdes_mux { - idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ -}; - -&serdes_ln_ctrl { - idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, - <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,usb2-only; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qspi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "qspi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "qspi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "qspi.env"; - reg = <0x680000 0x20000>; - }; - - partition@6a0000 { - label = "qspi.env.backup"; - reg = <0x6a0000 0x20000>; - }; - - partition@6c0000 { - label = "qspi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "qspi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fe0000 { - label = "qspi.phypattern"; - reg = <0x3fe0000 0x20000>; - }; - }; - }; -}; - -&tscadc0 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - p09-hog { - /* P11 - MCASP/TRACE_MUX_S0 */ - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP/TRACE_MUX_S0"; - }; - - p10-hog { - /* P12 - MCASP/TRACE_MUX_S1 */ - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "MCASP/TRACE_MUX_S1"; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_exp4_pins_default>; - interrupt-parent = <&main_gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK2 pin as output */ - pinctrl-names = "default"; - pinctrl-0 = <&audi_ext_refclk2_pins_default>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - - #sound-dai-cells = <1>; - - reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; - - /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ - clocks = <&k3_clks 157 371>; - clock-names = "scki"; - - /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ - assigned-clocks = <&k3_clks 157 371>; - assigned-clock-parents = <&k3_clks 157 400>; - assigned-clock-rates = <24576000>; /* for 48KHz */ - - VDD1-supply = <&vsys_3v3>; - VDD2-supply = <&vsys_3v3>; - VCCAD1-supply = <&vsys_5v0>; - VCCAD2-supply = <&vsys_5v0>; - VCCDA1-supply = <&vsys_5v0>; - VCCDA2-supply = <&vsys_5v0>; - }; -}; - -&main_i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c6_pins_default>; - clock-frequency = <400000>; - - exp5: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - - assigned-clocks = <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* PLL19_HSDIV0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* PLL23_HSDIV0 */ -}; - -&dss_ports { - port { - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&mcasp10 { - status = "okay"; - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mcasp10_pins_default>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - auxclk-fs-ratio = <256>; - - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 1 1 1 - 2 2 2 0 - >; - tx-num-evt = <0>; - rx-num-evt = <0>; -}; - -&cmn_refclk1 { - clock-frequency = <100000000>; -}; - -&wiz0_pll1_refclk { - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz0_refclk_dig { - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz1_pll1_refclk { - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz1_refclk_dig { - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz2_pll1_refclk { - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz2_refclk_dig { - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&serdes0 { - assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz0_pll1_refclk>; - - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz1_pll1_refclk>; - - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&serdes2 { - assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz2_pll1_refclk>; - - serdes2_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&pcie0_rc { - status = "okay"; - reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_rc { - status = "okay"; - reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan0_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan2_pins_default>; - phys = <&transceiver4>; -}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi deleted file mode 100644 index 746b9f8b1c6..00000000000 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ /dev/null @@ -1,2741 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/phy/phy-ti.h> -#include <dt-bindings/mux/mux.h> - -#include "k3-serdes.h" - -/ { - cmn_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - cmn_refclk1: clock-cmnrefclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x800000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ - idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, - <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; - }; - - cpsw0_phy_gmii_sel: phy@4044 { - compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; - ti,qsgmii-main-ports = <2>, <2>; - reg = <0x4044 0x20>; - #phy-cells = <1>; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; - - ehrpwm_tbclk: clock-controller@4140 { - compatible = "ti,am654-ehrpwm-tbclk"; - reg = <0x4140 0x18>; - #clock-cells = <1>; - }; - }; - - main_ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3000000 0x00 0x100>; - power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3010000 0x00 0x100>; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3020000 0x00 0x100>; - power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3030000 0x00 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3040000 0x00 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3050000 0x00 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <199>; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x0 0x310e0000 0x0 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&main_navss_intr>; - msi-controller; - #interrupt-cells = <0>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - smmu0: iommu@36600000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x36600000 0x0 0x100000>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "gerror"; - #iommu-cells = <1>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>, - <0x0 0x31080000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - cpsw0: ethernet@c000000 { - compatible = "ti,j721e-cpswxg-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0xc000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; - clocks = <&k3_clks 19 89>; - clock-names = "fck"; - power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xca00>, - <&main_udmap 0xca01>, - <&main_udmap 0xca02>, - <&main_udmap 0xca03>, - <&main_udmap 0xca04>, - <&main_udmap 0xca05>, - <&main_udmap 0xca06>, - <&main_udmap 0xca07>, - <&main_udmap 0x4a00>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - cpsw0_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - status = "disabled"; - }; - - cpsw0_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - status = "disabled"; - }; - - cpsw0_port3: port@3 { - reg = <3>; - ti,mac-only; - label = "port3"; - status = "disabled"; - }; - - cpsw0_port4: port@4 { - reg = <4>; - ti,mac-only; - label = "port4"; - status = "disabled"; - }; - - cpsw0_port5: port@5 { - reg = <5>; - ti,mac-only; - label = "port5"; - status = "disabled"; - }; - - cpsw0_port6: port@6 { - reg = <6>; - ti,mac-only; - label = "port6"; - status = "disabled"; - }; - - cpsw0_port7: port@7 { - reg = <7>; - ti,mac-only; - label = "port7"; - status = "disabled"; - }; - - cpsw0_port8: port@8 { - reg = <8>; - ti,mac-only; - label = "port8"; - status = "disabled"; - }; - }; - - cpsw9g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 19 89>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 19 16>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x0 0x4e00000 0x0 0x1200>; - power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, - <&main_udmap 0x4001>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x0 0x4e10000 0x0 0x7d>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x2b4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x00 0x104200 0x00 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000007>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x00 0x104280 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - serdes_wiz0: wiz@5000000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; - assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5000000 0x0 0x5000000 0x10000>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 0>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz0_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes0: serdes@5000000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5000000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz0 0>; - reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, - <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz1: wiz@5010000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; - assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5010000 0x0 0x5010000 0x10000>; - - wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll0_refclk>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&k3_clks 293 0>; - }; - - wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz1_refclk_dig>; - #clock-cells = <0>; - }; - - wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz1_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes1: serdes@5010000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5010000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz1 0>; - reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, - <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz2: wiz@5020000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; - assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5020000 0x0 0x5020000 0x10000>; - - wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll0_refclk>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&k3_clks 294 0>; - }; - - wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz2_refclk_dig>; - #clock-cells = <0>; - }; - - wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz2_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes2: serdes@5020000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5020000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz2 0>; - reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, - <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz3: wiz@5030000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; - assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5030000 0x0 0x5030000 0x10000>; - - wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll0_refclk>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll1_refclk>; - assigned-clock-parents = <&k3_clks 295 0>; - }; - - wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_refclk_dig>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz3_refclk_dig>; - #clock-cells = <0>; - }; - - wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz3_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes3: serdes@5030000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5030000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz3 0>; - reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, - <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - pcie0_rc: pcie@2900000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x10000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie2_rc: pcie@2920000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x20000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie3_rc: pcie@2930000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x30000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - serdes_wiz4: wiz@5050000 { - compatible = "ti,am64-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 297 9>; - assigned-clock-parents = <&k3_clks 297 10>; - assigned-clock-rates = <19200000>; - num-lanes = <4>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x05050000 0x00 0x05050000 0x010000>, - <0x0a030a00 0x00 0x0a030a00 0x40>; - - serdes4: serdes@5050000 { - /* - * Note: we also map DPTX PHY registers as the Torrent - * needs to manage those. - */ - compatible = "ti,j721e-serdes-10g"; - reg = <0x05050000 0x010000>, - <0x0a030a00 0x40>; /* DPTX PHY */ - reg-names = "torrent_phy", "dptx_phy"; - - resets = <&serdes_wiz4 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; - clock-names = "refclk"; - assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 297 9>, - <&k3_clks 297 9>, - <&k3_clks 297 9>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 49 1>; - assigned-clock-parents = <&k3_clks 49 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; - assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 51 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 51 1>; - assigned-clock-parents = <&k3_clks 51 2>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 52 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; - assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 53 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 53 1>; - assigned-clock-parents = <&k3_clks 53 2>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 54 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; - assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 55 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 55 1>; - assigned-clock-parents = <&k3_clks 55 2>; - power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 57 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; - assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 58 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 58 1>; - assigned-clock-parents = <&k3_clks 58 2>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 59 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; - assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; - power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 60 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 60 1>; - assigned-clock-parents = <&k3_clks 60 2>; - power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 62 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; - assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; - power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; - assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; - assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; - assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; - assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <256>, <257>, <258>, <259>, - <260>, <261>, <262>, <263>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <288>, <289>, <290>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00610000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <264>, <265>, <266>, <267>, - <268>, <269>, <270>, <271>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio3: gpio@611000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00611000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <292>, <293>, <294>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 108 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00620000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <272>, <273>, <274>, <275>, - <276>, <277>, <278>, <279>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio5: gpio@621000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00621000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <296>, <297>, <298>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 110 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00630000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <280>, <281>, <282>, <283>, - <284>, <285>, <286>, <287>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio7: gpio@631000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00631000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <300>, <301>, <302>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x6>; - ti,otap-del-sel-hs400 = <0x0>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,itap-del-sel-ddr52 = <0x3>; - ti,trm-icp = <0x8>; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; - assigned-clocks = <&k3_clks 92 0>; - assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,itap-del-sel-ddr50 = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - sdhci-caps-mask = <0x2 0x0>; - status = "disabled"; - }; - - main_sdhci2: mmc@4f98000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; - assigned-clocks = <&k3_clks 93 0>; - assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,itap-del-sel-ddr50 = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - sdhci-caps-mask = <0x2 0x0>; - status = "disabled"; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: cdns-usb@4114000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4114000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb1: usb@6400000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6400000 0x00 0x10000>, - <0x00 0x6410000 0x00 0x10000>, - <0x00 0x6420000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 0>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 0>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 0>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 0>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2040000 0x0 0x100>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 0>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2050000 0x0 0x100>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 0>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2060000 0x0 0x100>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 0>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - ufs_wrapper: ufs-wrapper@4e80000 { - compatible = "ti,j721e-ufs"; - reg = <0x0 0x4e80000 0x0 0x100>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - ufs@4e84000 { - compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; - reg = <0x0 0x4e84000 0x0 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; - clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; - clock-names = "core_clk", "phy_clk", "ref_clk"; - dma-coherent; - }; - }; - - mhdp: dp-bridge@a000000 { - compatible = "ti,j721e-mhdp8546"; - /* - * Note: we do not map DPTX PHY area, as that is handled by - * the PHY driver. - */ - reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ - <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ - reg-names = "mhdptx", "j721e-intg"; - - clocks = <&k3_clks 151 36>; - - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; - - power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; - - dp0_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@4 { - reg = <4>; - }; - }; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = - <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - - dss_ports: ports { - }; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 174 1>; - clock-names = "fck"; - power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 175 1>; - clock-names = "fck"; - power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 176 1>; - clock-names = "fck"; - power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp3: mcasp@2b30000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b30000 0x0 0x2000>, - <0x0 0x02b38000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 177 1>; - clock-names = "fck"; - power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp4: mcasp@2b40000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b40000 0x0 0x2000>, - <0x0 0x02b48000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 178 1>; - clock-names = "fck"; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp5: mcasp@2b50000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b50000 0x0 0x2000>, - <0x0 0x02b58000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 179 1>; - clock-names = "fck"; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp6: mcasp@2b60000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b60000 0x0 0x2000>, - <0x0 0x02b68000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 180 1>; - clock-names = "fck"; - power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp7: mcasp@2b70000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b70000 0x0 0x2000>, - <0x0 0x02b78000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 181 1>; - clock-names = "fck"; - power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp8: mcasp@2b80000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b80000 0x0 0x2000>, - <0x0 0x02b88000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 182 1>; - clock-names = "fck"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp9: mcasp@2b90000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b90000 0x0 0x2000>, - <0x0 0x02b98000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 183 1>; - clock-names = "fck"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp10: mcasp@2ba0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02ba0000 0x0 0x2000>, - <0x0 0x02ba8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 184 1>; - clock-names = "fck"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp11: mcasp@2bb0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02bb0000 0x0 0x2000>, - <0x0 0x02bb8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 185 1>; - clock-names = "fck"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5c00000 0x00008000>, - <0x5c10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 245 1>; - firmware-name = "j7-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5d00000 0x00008000>, - <0x5d10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 246 1>; - firmware-name = "j7-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@5e00000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5e00000 0x00 0x5e00000 0x20000>, - <0x5f00000 0x00 0x5f00000 0x20000>; - power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@5e00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5e00000 0x00008000>, - <0x5e10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <247>; - ti,sci-proc-ids = <0x08 0xff>; - resets = <&k3_reset 247 1>; - firmware-name = "j7-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@5f00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5f00000 0x00008000>, - <0x5f10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <248>; - ti,sci-proc-ids = <0x09 0xff>; - resets = <&k3_reset 248 1>; - firmware-name = "j7-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - c66_0: dsp@4d80800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x80800000 0x00 0x00048000>, - <0x4d 0x80e00000 0x00 0x00008000>, - <0x4d 0x80f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <142>; - ti,sci-proc-ids = <0x03 0xff>; - resets = <&k3_reset 142 1>; - firmware-name = "j7-c66_0-fw"; - status = "disabled"; - }; - - c66_1: dsp@4d81800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x81800000 0x00 0x00048000>, - <0x4d 0x81e00000 0x00 0x00008000>, - <0x4d 0x81f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <143>; - ti,sci-proc-ids = <0x04 0xff>; - resets = <&k3_reset 143 1>; - firmware-name = "j7-c66_1-fw"; - status = "disabled"; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721e-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <15>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 15 1>; - firmware-name = "j7-c71_0-fw"; - status = "disabled"; - }; - - icssg0: icssg@b000000 { - compatible = "ti,j721e-icssg"; - reg = <0x00 0xb000000 0x00 0x80000>; - power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x0b000000 0x100000>; - - icssg0_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - icssg0_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg0_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ - <&k3_clks 119 1>; /* icssg0_iclk */ - assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 119 1>; - }; - - icssg0_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ - <&icssg0_coreclk_mux>; /* core_clk */ - assigned-clocks = <&icssg0_iepclk_mux>; - assigned-clock-parents = <&icssg0_coreclk_mux>; - }; - }; - }; - - icssg0_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg0_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg0_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru0_0: pru@34000 { - compatible = "ti,j721e-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru0_0-fw"; - }; - - rtu0_0: rtu@4000 { - compatible = "ti,j721e-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu0_0-fw"; - }; - - tx_pru0_0: txpru@a000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru0_0-fw"; - }; - - pru0_1: pru@38000 { - compatible = "ti,j721e-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru0_1-fw"; - }; - - rtu0_1: rtu@6000 { - compatible = "ti,j721e-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu0_1-fw"; - }; - - tx_pru0_1: txpru@c000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru0_1-fw"; - }; - - icssg0_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 119 1>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - icssg1: icssg@b100000 { - compatible = "ti,j721e-icssg"; - reg = <0x00 0xb100000 0x00 0x80000>; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x0b100000 0x100000>; - - icssg1_mem: memories@b100000 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - icssg1_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg1_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ - <&k3_clks 120 4>; /* icssg1_iclk */ - assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 120 4>; - }; - - icssg1_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ - <&icssg1_coreclk_mux>; /* core_clk */ - assigned-clocks = <&icssg1_iepclk_mux>; - assigned-clock-parents = <&icssg1_coreclk_mux>; - }; - }; - }; - - icssg1_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg1_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg1_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru1_0: pru@34000 { - compatible = "ti,j721e-pru"; - reg = <0x34000 0x4000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru1_0-fw"; - }; - - rtu1_0: rtu@4000 { - compatible = "ti,j721e-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu1_0-fw"; - }; - - tx_pru1_0: txpru@a000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru1_0-fw"; - }; - - pru1_1: pru@38000 { - compatible = "ti,j721e-pru"; - reg = <0x38000 0x4000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru1_1-fw"; - }; - - rtu1_1: rtu@6000 { - compatible = "ti,j721e-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu1_1-fw"; - }; - - tx_pru1_1: txpru@c000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru1_1-fw"; - }; - - icssg1_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 120 4>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - main_mcan0: can@2701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02701000 0x00 0x200>, - <0x00 0x02708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@2711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02711000 0x00 0x200>, - <0x00 0x02718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan2: can@2721000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02721000 0x00 0x200>, - <0x00 0x02728000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan3: can@2731000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02731000 0x00 0x200>, - <0x00 0x02738000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan4: can@2741000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02741000 0x00 0x200>, - <0x00 0x02748000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan5: can@2751000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02751000 0x00 0x200>, - <0x00 0x02758000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan6: can@2761000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02761000 0x00 0x200>, - <0x00 0x02768000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan7: can@2771000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02771000 0x00 0x200>, - <0x00 0x02778000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan8: can@2781000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02781000 0x00 0x200>, - <0x00 0x02788000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan9: can@2791000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02791000 0x00 0x200>, - <0x00 0x02798000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan10: can@27a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027a1000 0x00 0x200>, - <0x00 0x027a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan11: can@27b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027b1000 0x00 0x200>, - <0x00 0x027b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan12: can@27c1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027c1000 0x00 0x200>, - <0x00 0x027c8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan13: can@27d1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027d1000 0x00 0x200>, - <0x00 0x027d8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 266 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 267 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 268 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 269 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 270 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 271 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 272 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 273 1>; - status = "disabled"; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <344>, <345>; - }; -}; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi deleted file mode 100644 index f7ab7719fc0..00000000000 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ /dev/null @@ -1,681 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x0 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x0 0x43000014 0x0 0x4>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04200 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04280 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x0 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mcu_timer0: timer@40400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer1: timer@40410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; - assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer2: timer@40420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer3: timer@40430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; - assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer4: timer@40440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer5: timer@40450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; - assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer6: timer@40460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer7: timer@40470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; - assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer8: timer@40480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer9: timer@40490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; - assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42110000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42100000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 0>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b10000 0x0 0x100>; - interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 0>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x42120000 0x0 0x100>; - interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 0>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - fss: bus@47000000 { - compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: mux-controller@47000004 { - compatible = "reg-mux"; - reg = <0x00 0x47000004 0x00 0x2>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - status = "disabled"; - }; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 104 0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 1>; - assigned-clocks = <&k3_clks 1 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x2a480000 0x0 0x80000>, - <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721e-r5f"; - reg = <0x41000000 0x00008000>, - <0x41010000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <250>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 250 1>; - firmware-name = "j7-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721e-r5f"; - reg = <0x41400000 0x00008000>, - <0x41410000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <251>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 251 1>; - firmware-name = "j7-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_mcan0: can@40528000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40528000 0x00 0x200>, - <0x00 0x40500000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@40568000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40568000 0x00 0x200>, - <0x00 0x40540000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 274 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 275 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 0>; - status = "disabled"; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j721e-vtm"; - reg = <0x00 0x42040000 0x00 0x350>, - <0x00 0x42050000 0x00 0x350>, - <0x00 0x43000300 0x00 0x10>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts index 43da4dafba8..586ddb6e7c8 100644 --- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -12,84 +12,8 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-beagleboneai64-u-boot.dtsi" +#include "k3-j721e-r5.dtsi" -/ { - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - chosen { - tick-timer = &mcu_timer0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 6>, - <&secure_proxy_mcu 8>, - <&secure_proxy_mcu 5>; - mbox-names = "rx", "tx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - /* We require this for boot handshake */ - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - bootph-pre-ram; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; - -&wkup_uart0_pins_default { - bootph-pre-ram; -}; &wkup_i2c0 { bootph-pre-ram; @@ -183,3 +107,32 @@ }; }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsue update GUIDs. See beagleboneai64.h. +#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR "772a4810-2194-4923-8754-0115870ef367" +#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR "dfc9c683-49b7-46bd-b3c1-3a3b2fdb135b" + +&capsule_tiboot3 { + efi-capsule { + image-guid = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR; + }; +}; + +&binman { + capsule-sysfw { + filename = "sysfw-capsule.bin"; + efi-capsule { + image-index = <0x4>; + image-guid = BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "sysfw.itb"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 9655ca21d02..c7e344350c8 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -10,76 +10,7 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-common-proc-board-u-boot.dtsi" -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - bootph-pre-ram; - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721e-r5.dtsi" &wkup_i2c0 { bootph-pre-ram; @@ -111,10 +42,6 @@ }; }; -&wkup_uart0_pins_default { - bootph-pre-ram; -}; - &mcu_uart0_pins_default { bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index b0c108e9693..96a13b2cb2b 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -10,80 +10,7 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-sk-u-boot.dtsi" -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - bootph-pre-ram; - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; - -&wkup_uart0_pins_default { - bootph-pre-ram; -}; +#include "k3-j721e-r5.dtsi" &mcu_uart0_pins_default { bootph-pre-ram; diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi new file mode 100644 index 00000000000..fd0d921272c --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clock-rates = <2000000000>, <200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + status = "okay"; + bootph-pre-ram; +}; + +&dmsc { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + bootph-pre-ram; + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx"; + }; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; + +&wkup_uart0_pins_default { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 8f4f944263e..07ed7b40fed 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -15,10 +15,10 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -26,19 +26,11 @@ }; &mcu_ringacc { - bootph-all; + bootph-all; }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; - bootph-all; + bootph-all; }; &secure_proxy_main { @@ -155,3 +147,26 @@ bootph-all; }; }; + +#ifdef CONFIG_TARGET_J721E_A72_EVM + +#define SPL_J721E_SK_DTB "spl/dts/ti/k3-j721e-sk.dtb" +#define J721E_SK_DTB "u-boot.dtb" + +&spl_j721e_dtb { + filename = SPL_J721E_SK_DTB; +}; + +&j721e_dtb { + filename = J721E_SK_DTB; +}; + +&spl_j721e_dtb_unsigned { + filename = SPL_J721E_SK_DTB; +}; + +&j721e_dtb_unsigned { + filename = J721E_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts deleted file mode 100644 index 42fe8eee9ec..00000000000 --- a/arch/arm/dts/k3-j721e-sk.dts +++ /dev/null @@ -1,1074 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - compatible = "ti,j721e-sk", "ti,j721e"; - model = "Texas Instruments J721E SK"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - ethernet0 = &cpsw_port1; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - vusb_main: fixedregulator-vusb-main5v0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb-main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5141 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_mmc1_en_pins_default>; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: gpio-regulator-tps659411 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tps659411"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - dp_pwr_3v3: fixedregulator-dp-prw { - compatible = "regulator-fixed"; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pwr_en_pins_default>; - gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins_default>; - - ddc-i2c-bus = <&main_i2c1>; - - /* HDMI_HPD */ - hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-bridge { - compatible = "ti,tfp410"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pdn_pins_default>; - - powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; - ti,deskew = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi1_out>; - pclk-sample = <1>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = - <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_pmx0 { - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ - J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ - J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ - >; - }; - - dp_pwr_en_pins_default: dp-pwr-en-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ - >; - }; - - dss_vout0_pins_default: dss-vout0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ - J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ - J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ - J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ - J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ - J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ - J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ - J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ - J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ - J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ - J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ - J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ - J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ - J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ - J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ - J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ - J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ - J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ - J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ - J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ - J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ - J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ - J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ - J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ - J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ - J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ - J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ - J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ - >; - }; - - hdmi_hpd_pins_default: hdmi-hpd-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ - >; - }; - - hdmi_pdn_pins_default: hdmi-pdn-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ - >; - }; - - /* Reset for M.2 E Key slot on PCIe0 */ - ekey_reset_pins_default: ekey-reset-pns-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ - J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ - >; - }; - - rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ - J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ - J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ - J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ - J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ - J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ - J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ - J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ - J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ - J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ - J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ - J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ - J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ - J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ - J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ - J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ - J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ - J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ - J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ - J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ - J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ - J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ - J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ - >; - }; - - rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ - >; - }; -}; - -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ - J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ - >; - }; - - vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ - J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - /* Reset for M.2 M Key slot on PCIe1 */ - mkey_reset_pins_default: mkey-reset-pns-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_sdhci1 { - /* SD Card */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@7c0000 { - label = "ospi.env.backup"; - reg = <0x7c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - i2c-mux@71 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - /* PCIe1 M.2 M Key I2C */ - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - /* PCIe0 M.2 E Key I2C */ - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - /* i2c1 is used for DVI DDC, so we need to use 100kHz */ - clock-frequency = <100000>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - /* CSI0 I2C */ - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - /* CSI1 I2C */ - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&main_i2c5 { - /* Brought out on RPi Header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default>; - clock-frequency = <400000>; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio0_pins_default>; -}; - -&main_gpio1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio1_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&usb_serdes_mux { - idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ -}; - -&serdes_ln_ctrl { - idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, - <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&serdes2 { - serdes2_usb_link: phy@1 { - reg = <1>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz2 2>; - }; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,vbus-divider; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes2_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout0_pins_default>; - - assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ - <&k3_clks 152 4>, /* VP 2 pixel clock */ - <&k3_clks 152 9>, /* VP 3 pixel clock */ - <&k3_clks 152 13>; /* VP 4 pixel clock */ - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; - - port@1 { - reg = <1>; - - dpi1_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&pcie0_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ekey_reset_pins_default>; - reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; - - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mkey_reset_pins_default>; - reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; - - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&ufs_wrapper { - status = "disabled"; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi deleted file mode 100644 index 7f0686c2ce3..00000000000 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ - * - * Product Link: https://www.ti.com/tool/J721EXSOMXEVM - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - >; - }; - - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x20000>; - }; - - partition@6a0000 { - label = "ospi.env.backup"; - reg = <0x6a0000 0x20000>; - }; - - partition@6c0000 { - label = "ospi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fe0000 { - label = "ospi.phypattern"; - reg = <0x3fe0000 0x20000>; - }; - }; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "hbmc.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "hbmc.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "hbmc.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "hbmc.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "hbmc.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "hbmc.rootfs"; - reg = <0x800000 0x3800000>; - }; - }; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721e-thermal.dtsi b/arch/arm/dts/k3-j721e-thermal.dtsi deleted file mode 100644 index c2523279001..00000000000 --- a/arch/arm/dts/k3-j721e-thermal.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - wkup_thermal: wkup-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup_crit: wkup-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - mpu_thermal: mpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu_crit: mpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - c7x_thermal: c7x-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - c7x_crit: c7x-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 3>; - - trips { - gpu_crit: gpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - r5f_thermal: r5f-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 4>; - - trips { - r5f_crit: r5f-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi deleted file mode 100644 index a200810df54..00000000000 --- a/arch/arm/dts/k3-j721e.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ - <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ - <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ - <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ - <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - }; - }; - - #include "k3-j721e-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j721e-main.dtsi" -#include "k3-j721e-mcu-wakeup.dtsi" diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 46297ebef9e..d121d8c0c54 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -149,6 +149,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 91a82b3b7ca..54eb9b4072c 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -102,7 +102,9 @@ }; &ospi0 { - status = "disabled"; + flash@0 { + bootph-all; + }; }; &ospi1 { diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index eb0df42583a..caf696c2d96 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -22,7 +22,7 @@ resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-parents = <&k3_clks 61 3>; assigned-clock-rates = <200000000>, <2000000000>; ti,sci = <&sms>; ti,sci-proc-id = <32>; @@ -79,3 +79,16 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&fss { + /* fss node has 64 bit address regions mapped to it and since the ospi + * nodes is being override, override the fss node ranges as well + */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index e4dd6e14a66..85bdd1f5b6c 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -157,6 +157,22 @@ }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See j784s4_evm.h +#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR; + + blob { + filename = "tiboot3-j784s4-hs-fs-evm.bin"; + }; + }; +}; + #endif #ifdef CONFIG_TARGET_J784S4_A72_EVM @@ -170,6 +186,7 @@ blob-ext { filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; @@ -342,4 +359,23 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See j784s4_evm.h +#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e" +#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617" + +&capsule_tispl { + efi-capsule { + image-guid = AM69_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index db5463b2bbb..07efabaa7dc 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -23,4 +23,3 @@ char __secure_start[0] __section(".__secure_start"); char __secure_end[0] __section(".__secure_end"); char __secure_stack_start[0] __section(".__secure_stack_start"); char __secure_stack_end[0] __section(".__secure_stack_end"); -char _end[0] __section(".__end"); diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index ada6570d971..9502a7384b5 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -61,11 +61,7 @@ SECTIONS __rel_dyn_end = .; } > .nor - .end : - { - *(.__end) - } > .nor - + _end = .; _image_binary_end = .; .bss : { diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 1a8bf94dee0..09cf838cf96 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -33,12 +33,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index 6ca725fc4ce..460a91d93ec 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -40,12 +40,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index ed8d24e0433..72a752d38e8 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -213,6 +213,8 @@ void board_init_f(ulong dummy) preloader_console_init(); + do_board_detect(); + /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive" diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 1a269d6934a..eaa7d361767 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -283,8 +283,10 @@ int misc_init_r(void) } /* Default FIT boot on HS-SE devices */ - if (get_device_type() == K3_DEVICE_TYPE_HS_SE) + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) { env_set("boot_fit", "1"); + env_set("secure_rprocs", "1"); + } return 0; } diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 53aa186b31a..7bd72da1de8 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -2,12 +2,13 @@ /* * K3: Architecture common definitions * - * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ #include <asm/armv7_mpu.h> #include <asm/hardware.h> +#include <mach/security.h> #define K3_FIREWALL_BACKGROUND_BIT (8) @@ -41,7 +42,6 @@ void spl_enable_cache(void); void mmr_unlock(uintptr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); enum k3_device_type get_device_type(void); -void ti_secure_image_post_process(void **p_image, size_t *p_size); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/include/mach/security.h b/arch/arm/mach-k3/include/mach/security.h new file mode 100644 index 00000000000..8502b57bd80 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/security.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: Security related definitions + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Manorit Chawdhry <m-chawdhry@ti.com> + */ + +#include <linux/types.h> + +void ti_secure_image_post_process(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds index 1d6e5d45b46..3bb759d8a1c 100644 --- a/arch/arm/mach-omap2/u-boot-spl.lds +++ b/arch/arm/mach-omap2/u-boot-spl.lds @@ -39,12 +39,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds index ad32654085b..958a1b70aef 100644 --- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -46,12 +46,7 @@ SECTIONS . = ALIGN(8); __image_copy_end = .; - - .end : { - . = ALIGN(8); - *(.__end) - } - + _end = .; _image_binary_end = .; .bss ALIGN(8) : { diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index 3e0c96c5055..f52523edf49 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -68,11 +68,7 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; /* diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 7e0f09f3b5b..56d6f4f114b 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -46,12 +46,7 @@ SECTIONS } >.sram __image_copy_end = .; - - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .bss : diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..f394ace786a 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -4,6 +4,13 @@ config PHYTEC_SOM_DETECTION help Support of I2C EEPROM based SoM detection. +config PHYTEC_SOM_DETECTION_BLOCKS + bool "Extend SoM detection with block support" + depends on PHYTEC_SOM_DETECTION + help + Extend the I2C EEPROM based SoM detection with API v3. This API + introduces blocks with different payloads. + config PHYTEC_IMX8M_SOM_DETECTION bool "Support SoM detection for i.MX8M PHYTEC platforms" depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION @@ -16,6 +23,8 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +34,8 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index c34fc503059..04469d0a924 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -5,10 +5,8 @@ ifdef CONFIG_SPL_BUILD # necessary to create built-in.o obj- := __dummy__.o -else -obj-$(CONFIG_ARCH_K3) += k3/ endif -obj-y += phytec_som_detection.o -obj-$(CONFIG_ARCH_K3) += am6_som_detection.o +obj-y += phytec_som_detection.o phytec_som_detection_blocks.o +obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c index 2e9884dab44..7930ab42d1c 100644 --- a/board/phytec/common/am6_som_detection.c +++ b/board/phytec/common/am6_som_detection.c @@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data, u8 option) * - The size * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { u8 ddr_id = phytec_check_opt(data, 3); @@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) * - Otherwise a board depended code for the size. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { u8 spi = phytec_check_opt(data, 5); @@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) * - 0x1 if 10/100/1000 MBit Phy is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { u8 eth = phytec_check_opt(data, 6); @@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) * - 1 if it is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { u8 rtc = phytec_check_opt(data, 7); @@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) #else -inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data) +inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data) { return -1; } inline u8 __maybe_unused -phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h index 032f9da3aab..c5c6e179da6 100644 --- a/board/phytec/common/am6_som_detection.h +++ b/board/phytec/common/am6_som_detection.h @@ -9,11 +9,19 @@ #include "phytec_som_detection.h" +#define EEPROM_ADDR 0x50 #define PHYTEC_AM62X_SOM 71 #define PHYTEC_AM64X_SOM 72 #define PHYTEC_EEPROM_VALUE_X 0x21 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC +enum { + EEPROM_RAM_SIZE_512MB = 0, + EEPROM_RAM_SIZE_1GB = 1, + EEPROM_RAM_SIZE_2GB = 2, + EEPROM_RAM_SIZE_4GB = 4 +}; + int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data); diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index bcca1a9f846..40e91a43e99 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o +obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 9cb168c36cb..f21e154d4fe 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -8,6 +8,8 @@ #include <spl.h> #include <asm/arch/hardware.h> +#include "../am6_som_detection.h" + #if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) int mmc_get_env_dev(void) { @@ -68,6 +70,27 @@ int board_late_init(void) break; }; + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return 0; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); + } + } + } + return 0; } #endif diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c new file mode 100644 index 00000000000..39f7be8dc92 --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#include "k3_ddrss_patch.h" + +#include <fdt_support.h> +#include <linux/errno.h> + +#ifdef CONFIG_K3_AM64_DDRSS +#define LPDDR4_INTR_CTL_REG_COUNT (423U) +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) +#endif + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss) +{ + int i, j; + int ret; + int mem_offset; + + mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000"); + if (mem_offset < 0) + return -ENODEV; + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + for (j = 0; j < ddrss->ctl_regs_num; j++) + if (i == ddrss->ctl_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,ctl-data", i, + ddrss->ctl_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->pi_regs_num; j++) + if (i == ddrss->pi_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,pi-data", i, + ddrss->pi_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->phy_regs_num; j++) + if (i == ddrss->phy_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,phy-data", i, + ddrss->phy_regs[j].val); + if (ret) + return ret; + } + + return 0; +} diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h new file mode 100644 index 00000000000..0a47c85116a --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef K3_DDRSS_PATCH +#define K3_DDRSS_PATCH + +#include <linux/types.h> + +struct ddr_reg { + u32 off; + u32 val; +}; + +struct ddrss { + struct ddr_reg *ctl_regs; + u32 ctl_regs_num; + struct ddr_reg *pi_regs; + u32 pi_regs_num; + struct ddr_reg *phy_regs; + u32 phy_regs_num; +}; + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss); + +#endif /* K3_DDRSS_PATCH */ diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index b14bb3dbb7f..166c3eae565 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -47,16 +47,9 @@ int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, return ret; } -int phytec_eeprom_data_init(struct phytec_eeprom_data *data, - int bus_num, int addr) +int phytec_eeprom_read(u8 *data, int bus_num, int addr, int size, int offset) { - int ret, i; - unsigned int crc; - u8 *ptr; - const unsigned int payload_size = sizeof(struct phytec_eeprom_payload); - - if (!data) - data = &eeprom_data; + int ret; #if CONFIG_IS_ENABLED(DM_I2C) struct udevice *dev; @@ -64,19 +57,182 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); if (ret) { pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); - goto err; + return ret; } - ret = dm_i2c_read(dev, 0, (uint8_t *)data, payload_size); + ret = dm_i2c_read(dev, offset, (uint8_t *)data, size); if (ret) { pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret); - goto err; + return ret; } #else i2c_set_bus_num(bus_num); - ret = i2c_read(addr, 0, 2, (uint8_t *)data, - sizeof(struct phytec_eeprom_data)); + ret = i2c_read(addr, offset, 2, (uint8_t *)data, size); #endif + return ret; +} + +int phytec_eeprom_data_init_v2(struct phytec_eeprom_data *data) +{ + unsigned int crc; + + if (!data) + return -1; + + crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", + __func__); + return -EINVAL; + } + + return 0; +} + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +int phytec_eeprom_data_init_v3_block(struct phytec_eeprom_data *data, + struct phytec_api3_block_header *header, + u8 *payload) +{ + struct phytec_api3_element *element = NULL; + struct phytec_api3_element *list_iterator; + + if (!header) + return -1; + if (!payload) + return -1; + + debug("%s: block type: %i\n", __func__, header->block_type); + switch (header->block_type) { + case PHYTEC_API3_BLOCK_MAC: + element = phytec_blocks_init_mac(header, payload); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + header->block_type); + } + if (!element) + return -1; + + if (!data->payload.block_head) { + data->payload.block_head = element; + return 0; + } + + list_iterator = data->payload.block_head; + while (list_iterator && list_iterator->next) + list_iterator = list_iterator->next; + list_iterator->next = element; + + return 0; +} + +int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + struct phytec_api3_header header; + unsigned int crc; + u8 *payload; + int block_addr; + struct phytec_api3_block_header *block_header; + + if (!data) + return -1; + + ret = phytec_eeprom_read((uint8_t *)&header, bus_num, addr, + PHYTEC_API3_DATA_HEADER_LEN, + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data header.\n", __func__); + goto err; + } + + crc = crc8(0, (const unsigned char *)&header, + PHYTEC_API3_DATA_HEADER_LEN); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 header is unusable.\n", + __func__); + goto err; + } + + debug("%s: data length: %i\n", __func__, header.data_length); + payload = malloc(header.data_length); + if (!payload) { + pr_err("%s: Unable to allocate memory\n", __func__); + goto err_payload; + } + + ret = phytec_eeprom_read(payload, bus_num, addr, header.data_length, + PHYTEC_API3_DATA_HEADER_LEN + + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data payload.\n", __func__); + goto err_payload; + } + + block_addr = 0; + debug("%s: block count: %i\n", __func__, header.block_count); + for (i = 0; i < header.block_count; i++) { + debug("%s: block_addr: %i\n", __func__, block_addr); + block_header = (struct phytec_api3_block_header *) + &payload[block_addr]; + crc = crc8(0, (const unsigned char *)block_header, + PHYTEC_API3_BLOCK_HEADER_LEN); + + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block header is unusable\n", + __func__); + goto err_payload; + } + + ret = phytec_eeprom_data_init_v3_block(data, block_header, + &payload[block_addr + PHYTEC_API3_BLOCK_HEADER_LEN]); + /* Ignore failed block initialization and continue. */ + if (ret) + debug("%s: Unable to create block with index %i.\n", + __func__, i); + + block_addr = block_header->next_block; + } + + free(payload); + return 0; +err_payload: + free(payload); +err: + return -1; +} + +#else + +inline int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return 0; +} + +#endif + +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + u8 *ptr; + + if (!data) + data = &eeprom_data; + + ret = phytec_eeprom_read((u8 *)data, bus_num, addr, + PHYTEC_API2_DATA_LEN, 0); + if (ret) + goto err; + data->payload.block_head = NULL; if (data->payload.api_rev == 0xff) { pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); @@ -85,31 +241,28 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, } ptr = (u8 *)data; - for (i = 0; i < payload_size; ++i) + for (i = 0; i < PHYTEC_API2_DATA_LEN; ++i) if (ptr[i] != 0x0) break; - if (i == payload_size) { + if (i == PHYTEC_API2_DATA_LEN) { pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); ret = -EINVAL; goto err; } - /* We are done here for early revisions */ - if (data->payload.api_rev <= PHYTEC_API_REV1) { - data->valid = true; - return 0; + if (data->payload.api_rev >= PHYTEC_API_REV2) { + ret = phytec_eeprom_data_init_v2(data); + if (ret) + goto err; } - crc = crc8(0, (const unsigned char *)&data->payload, payload_size); - debug("%s: crc: %x\n", __func__, crc); - - if (crc) { - pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", - __func__); - ret = -EINVAL; - goto err; - } + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + if (data->payload.api_rev >= PHYTEC_API_REV3) { + ret = phytec_eeprom_data_init_v3(data, bus_num, addr); + if (ret) + goto err; + } data->valid = true; return 0; @@ -248,6 +401,17 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, } #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data) +{ + if (!data) + data = &eeprom_data; + if (!data->valid) + return NULL; + + return data->payload.block_head; +} + #else inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, @@ -288,6 +452,12 @@ u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) return PHYTEC_EEPROM_INVAL; } +inline struct phytec_api3_element * __maybe_unused + phytec_get_block_head(struct phytec_eeprom_data *data) +{ + return NULL; +} + #if IS_ENABLED(CONFIG_CMD_EXTENSION) inline struct extension *phytec_add_extension(const char *name, const char *overlay, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 0ad5c14ef4e..5e35a13cb21 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -7,9 +7,13 @@ #ifndef _PHYTEC_SOM_DETECTION_H #define _PHYTEC_SOM_DETECTION_H +#include "phytec_som_detection_blocks.h" + #define PHYTEC_MAX_OPTIONS 17 #define PHYTEC_EEPROM_INVAL 0xff +#define PHYTEC_API2_DATA_LEN 32 + #define PHYTEC_GET_OPTION(option) \ (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') @@ -17,6 +21,7 @@ enum { PHYTEC_API_REV0 = 0, PHYTEC_API_REV1, PHYTEC_API_REV2, + PHYTEC_API_REV3, }; enum phytec_som_type_str { @@ -61,6 +66,7 @@ struct phytec_eeprom_payload { struct phytec_api0_data data_api0; struct phytec_api2_data data_api2; } data; + struct phytec_api3_element *block_head; } __packed; struct phytec_eeprom_data { @@ -86,4 +92,7 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, const char *other); #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data); + #endif /* _PHYTEC_SOM_DETECTION_H */ diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c new file mode 100644 index 00000000000..5f3c27ef0c2 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +#include <malloc.h> +#include <u-boot/crc.h> +#include <net.h> +#include <vsprintf.h> + +#include "phytec_som_detection_blocks.h" + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + struct phytec_api3_element *element; + struct phytec_api3_block_mac *mac; + unsigned int crc; + unsigned int len = sizeof(struct phytec_api3_block_mac); + + if (!header) + return NULL; + if (!payload) + return NULL; + + element = (struct phytec_api3_element *) + calloc(8, PHYTEC_API3_ELEMENT_HEADER_SIZE + len); + if (!element) { + pr_err("%s: Unable to allocate memory\n", __func__); + return NULL; + } + element->block_type = header->block_type; + memcpy(&element->block.mac, payload, len); + mac = &element->block.mac; + + debug("%s: interface: %i\n", __func__, mac->interface); + debug("%s: MAC %pM\n", __func__, mac->address); + + crc = crc8(0, (const unsigned char *)mac, len); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block payload is unusable\n", + __func__); + return NULL; + } + + return element; +} + +int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + char enetenv[9] = "ethaddr"; + char buf[ARP_HLEN_ASCII + 1]; + struct phytec_api3_block_mac *block = &element->block.mac; + int ret; + + if (!is_valid_ethaddr(block->address)) { + pr_err("%s: Invalid MAC address in block.\n", __func__); + return -1; + } + + if (block->interface > 0) { + ret = sprintf(enetenv, "eth%iaddr", block->interface); + if (ret != 8) { + pr_err("%s: Unable to create env string\n", __func__); + return -1; + } + } + + ret = sprintf(buf, "%pM", block->address); + if (ret != ARP_HLEN_ASCII) { + pr_err("%s: Unable to convert MAC address\n", __func__); + return -1; + } + ret = env_set(enetenv, buf); + if (ret) { + pr_err("%s: Failed to set MAC address to env.\n", __func__); + return -1; + } + + debug("%s: Added %s to %s\n", __func__, buf, enetenv); + return 0; +} + +#else + +inline struct phytec_api3_element * + phytec_api3_init_mac_block(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + return NULL; +} + +inline int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + return -1; +} + +#endif diff --git a/board/phytec/common/phytec_som_detection_blocks.h b/board/phytec/common/phytec_som_detection_blocks.h new file mode 100644 index 00000000000..2a5a83c9039 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +#ifndef _PHYTEC_SOM_DETECTION_BLOCKS_H +#define _PHYTEC_SOM_DETECTION_BLOCKS_H + +#define PHYTEC_API3_DATA_HEADER_LEN 8 +#define PHYTEC_API3_BLOCK_HEADER_LEN 4 +#define PHYTEC_API3_PAYLOAD_START \ + (PHYTEC_API2_DATA_LEN + PHYTEC_API3_DATA_HEADER_LEN) + +#define PHYTEC_API3_ELEMENT_HEADER_SIZE \ + (sizeof(struct phytec_api3_element *) + \ + sizeof(enum phytec_api3_block_types)) + +#define PHYTEC_API3_FOREACH_BLOCK(elem, data) \ + for (elem = phytec_get_block_head(data); elem; elem = elem->next) + +struct phytec_api3_header { + u16 data_length; /* Total length in Bytes of all blocks */ + u8 block_count; /* Number of blocks */ + u8 sub_version; /* Block specification version */ + u8 reserved[3]; /* Reserved */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_block_header { + u8 block_type; /* Block payload identifier */ + u16 next_block; /* Address of the next block */ + u8 crc8; /* checksum */ +} __packed; + +enum phytec_api3_block_types { + PHYTEC_API3_BLOCK_MAC = 0, +}; + +struct phytec_api3_block_mac { + u8 interface; /* Ethernet interface number */ + u8 address[6]; /* MAC-Address */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_element { + struct phytec_api3_element *next; + enum phytec_api3_block_types block_type; + union { + struct phytec_api3_block_mac mac; + } block; +} __packed; + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload); + +int __maybe_unused +phytec_blocks_add_mac_to_env(struct phytec_api3_element *element); + +#endif /* _PHYTEC_SOM_DETECTION_BLOCKS_H */ diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index 1de8850c6c4..7c179ef0078 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -35,3 +35,33 @@ config SPL_LDSCRIPT source "board/phytec/common/Kconfig" endif + +config PHYCORE_AM62X_RAM_SIZE_FIX + bool "Set phyCORE-AM62x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-AM62x RAM size" + depends on PHYCORE_AM62X_RAM_SIZE_FIX + default PHYCORE_AM62X_RAM_SIZE_2GB + +config PHYCORE_AM62X_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-AM62x. + +endchoice diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 02ac88e58a4..42463ad054e 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -11,3 +11,4 @@ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst +F: board/phytec/common/k3 diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a082b886bda..4a76f1343d7 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -8,6 +8,13 @@ #include <spl.h> #include <fdt_support.h> +#include "phycore-ddr-data.h" +#include "../common/k3/k3_ddrss_patch.h" +#include "../common/am6_som_detection.h" + +#define AM64_DDRSS_SS_BASE 0x0F300000 +#define DDRSS_V2A_CTL_REG 0x0020 + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -15,16 +22,157 @@ int board_init(void) return 0; } +static u8 phytec_get_am62_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB)) + return EEPROM_RAM_SIZE_4GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size = phytec_get_am62_ddr_size_default(); + + /* + * HACK: ddrss driver support 2GB RAM by default + * V2A_CTL_REG should be updated to support other RAM size + */ + if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) + if (ram_size == EEPROM_RAM_SIZE_4GB) + writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + case EEPROM_RAM_SIZE_4GB: +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + return gd->ram_top; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + case EEPROM_RAM_SIZE_4GB: + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR upper region */ + gd->bd->bi_dram[1].start = 0x880000000; + gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; +#endif + break; + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; +} + +#if defined(CONFIG_K3_DDRSS) +int update_ddrss_timings(void) +{ + int ret; + u8 ram_size; + struct ddrss *ddr_patch = NULL; + void *fdt = (void *)gd->fdt_blob; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_1GB]; + break; + case EEPROM_RAM_SIZE_2GB: + ddr_patch = NULL; + break; + case EEPROM_RAM_SIZE_4GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_4GB]; + break; + default: + break; + } + + /* Nothing to patch */ + if (!ddr_patch) + return 0; + + debug("Applying DDRSS timings patch for ram_size %d\n", ram_size); + + ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch); + if (ret < 0) { + printf("Failed to apply ddrs timings patch %d\n", ret); + return ret; + } + + return 0; } +int do_board_detect(void) +{ + return update_ddrss_timings(); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h new file mode 100644 index 00000000000..fe6eccd959e --- /dev/null +++ b/board/phytec/phycore_am62x/phycore-ddr-data.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef PHYCORE_DDR_DATA +#define PHYCORE_DDR_DATA + +#include "../common/k3/k3_ddrss_patch.h" + +/* 1 GB variant delta */ +struct ddr_reg ddr_1gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x01010000 }, + { 318, 0x3FFF0000 }, + { 327, 0x00000C01 }, + { 328, 0x00000000 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_1gb_pi_regs[] = { + { 77, 0x04000100 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_1gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +/* 4 GB variant delta */ +struct ddr_reg ddr_4gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x00000000 }, + { 318, 0x7FFF0000 }, + { 327, 0x01000C01 }, + { 328, 0x00000001 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_4gb_pi_regs[] = { + { 77, 0x04000000 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_4gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +enum { + PHYCORE_1GB, + PHYCORE_4GB, +}; + +struct ddrss phycore_ddrss_data[] = { + [PHYCORE_1GB] = { + .ctl_regs = &ddr_1gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs), + .pi_regs = &ddr_1gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs), + .phy_regs = &ddr_1gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs), + }, + [PHYCORE_4GB] = { + .ctl_regs = &ddr_4gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs), + .pi_regs = &ddr_4gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs), + .phy_regs = &ddr_4gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs), + }, +}; + +#endif /* PHYCORE_DDR_DATA */ diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index 73cd97a1b1d..9d3b57e98db 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -41,11 +41,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram + _end = .; .bss : { diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS index f5ca7d06a34..06aba53d9b0 100644 --- a/board/ti/j721e/MAINTAINERS +++ b/board/ti/j721e/MAINTAINERS @@ -5,5 +5,7 @@ F: board/ti/j721e F: include/configs/j721e_evm.h F: configs/j721e_evm_r5_defconfig F: configs/j721e_evm_a72_defconfig +F: configs/j721e_sk_r5_defconfig +F: configs/j721e_sk_a72_defconfig F: configs/j7200_evm_r5_defconfig F: configs/j7200_evm_a72_defconfig diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 7e54ca042ef..f5b72c7505e 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -3,6 +3,10 @@ #include <env/ti/ufs.env> #include <env/ti/k3_dfu.env> +#if CONFIG_CMD_REMOTEPROC +#include <env/ti/k3_rproc.env> +#endif + name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000 @@ -15,3 +19,5 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- + +rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index c7035c0d0c4..5a4c125835a 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -143,62 +143,6 @@ static int distro_efi_check(struct udevice *dev, struct bootflow_iter *iter) return 0; } -/** - * distro_efi_get_fdt_name() - Get the filename for reading the .dtb file - * - * @fname: Place to put filename - * @size: Max size of filename - * @seq: Sequence number, to cycle through options (0=first) - * Returns: 0 on success, -ENOENT if the "fdtfile" env var does not exist, - * -EINVAL if there are no more options, -EALREADY if the control FDT should be - * used - */ -static int distro_efi_get_fdt_name(char *fname, int size, int seq) -{ - const char *fdt_fname; - const char *prefix; - - /* select the prefix */ - switch (seq) { - case 0: - /* this is the default */ - prefix = "/dtb"; - break; - case 1: - prefix = ""; - break; - case 2: - prefix = "/dtb/current"; - break; - default: - return log_msg_ret("pref", -EINVAL); - } - - fdt_fname = env_get("fdtfile"); - if (fdt_fname) { - snprintf(fname, size, "%s/%s", prefix, fdt_fname); - log_debug("Using device tree: %s\n", fname); - } else if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE)) { - strcpy(fname, "<prior>"); - return log_msg_ret("pref", -EALREADY); - /* Use this fallback only for 32-bit ARM */ - } else if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64)) { - const char *soc = env_get("soc"); - const char *board = env_get("board"); - const char *boardver = env_get("boardver"); - - /* cf the code in label_boot() which seems very complex */ - snprintf(fname, size, "%s/%s%s%s%s.dtb", prefix, - soc ? soc : "", soc ? "-" : "", board ? board : "", - boardver ? boardver : ""); - log_debug("Using default device tree: %s\n", fname); - } else { - return log_msg_ret("env", -ENOENT); - } - - return 0; -} - /* * distro_efi_try_bootflow_files() - Check that files are present * @@ -240,7 +184,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, ret = -ENOENT; *fname = '\0'; for (seq = 0; ret == -ENOENT; seq++) { - ret = distro_efi_get_fdt_name(fname, sizeof(fname), seq); + ret = efi_get_distro_fdt_name(fname, sizeof(fname), seq); if (ret == -EALREADY) bflow->flags = BOOTFLOWF_USE_PRIOR_FDT; if (!ret) { @@ -339,7 +283,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) sprintf(file_addr, "%lx", fdt_addr); /* We only allow the first prefix with PXE */ - ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0); + ret = efi_get_distro_fdt_name(fname, sizeof(fname), 0); if (ret) return log_msg_ret("nam", ret); diff --git a/boot/image-android.c b/boot/image-android.c index ddd8ffd5e54..ee626972c11 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -63,7 +63,6 @@ static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 data->kcmdline = hdr->cmdline; data->header_version = hdr->header_version; - data->ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0); /* * The header takes a full page, the remaining components are aligned @@ -74,6 +73,7 @@ static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 data->kernel_ptr = end; data->kernel_size = hdr->kernel_size; end += ALIGN(hdr->kernel_size, ANDR_GKI_PAGE_SIZE); + data->ramdisk_ptr = end; data->ramdisk_size = hdr->ramdisk_size; data->boot_ramdisk_size = hdr->ramdisk_size; end += ALIGN(hdr->ramdisk_size, ANDR_GKI_PAGE_SIZE); @@ -393,25 +393,24 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, return -1; } if (img_data.header_version > 2) { - ramdisk_ptr = img_data.ramdisk_ptr; + ramdisk_ptr = img_data.ramdisk_addr; memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr, img_data.vendor_ramdisk_size); - memcpy((void *)(ramdisk_ptr + img_data.vendor_ramdisk_size), - (void *)img_data.ramdisk_ptr, + ramdisk_ptr += img_data.vendor_ramdisk_size; + memcpy((void *)(ramdisk_ptr), (void *)img_data.ramdisk_ptr, img_data.boot_ramdisk_size); + ramdisk_ptr += img_data.boot_ramdisk_size; if (img_data.bootconfig_size) { memcpy((void *) - (ramdisk_ptr + img_data.vendor_ramdisk_size + - img_data.boot_ramdisk_size), - (void *)img_data.bootconfig_addr, + (ramdisk_ptr), (void *)img_data.bootconfig_addr, img_data.bootconfig_size); } } printf("RAM disk load addr 0x%08lx size %u KiB\n", - img_data.ramdisk_ptr, DIV_ROUND_UP(img_data.ramdisk_size, 1024)); + img_data.ramdisk_addr, DIV_ROUND_UP(img_data.ramdisk_size, 1024)); - *rd_data = img_data.ramdisk_ptr; + *rd_data = img_data.ramdisk_addr; *rd_len = img_data.ramdisk_size; return 0; diff --git a/boot/image-board.c b/boot/image-board.c index b7884b8c5dc..f2124013046 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -406,13 +406,20 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { int ret; if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { - void *boot_img = map_sysmem(get_abootimg_addr(), 0); + ulong boot_img = get_abootimg_addr(); + ulong init_boot_img = get_ainit_bootimg_addr(); void *vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); + void *ramdisk_img; - ret = android_image_get_ramdisk(boot_img, vendor_boot_img, + if (init_boot_img == -1) + ramdisk_img = map_sysmem(boot_img, 0); + else + ramdisk_img = map_sysmem(init_boot_img, 0); + + ret = android_image_get_ramdisk(ramdisk_img, vendor_boot_img, rd_datap, rd_lenp); unmap_sysmem(vendor_boot_img); - unmap_sysmem(boot_img); + unmap_sysmem(ramdisk_img); } else { void *ptr = map_sysmem(images->os.start, 0); diff --git a/boot/image.c b/boot/image.c index bacf5146e13..fc774d605d1 100644 --- a/boot/image.c +++ b/boot/image.c @@ -528,10 +528,10 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, printf("Unimplemented compression type %d\n", comp); return ret; } - if (ret) - return ret; *load_end = load + image_len; + if (ret) + return ret; return 0; } diff --git a/cmd/Kconfig b/cmd/Kconfig index c06fec35275..ff0f5941ecc 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -804,9 +804,16 @@ config CMD_EEPROM_LAYOUT types of eeprom fields. Can be used for defining custom layouts. +config EEPROM_LAYOUT_VERSIONS + bool "Support specifying eeprom layout version" + depends on CMD_EEPROM_LAYOUT + help + Support specifying eeprom layout version in the 'eeprom' command + via the -l option. + config EEPROM_LAYOUT_HELP_STRING string "Tells user what layout names are supported" - depends on CMD_EEPROM_LAYOUT + depends on EEPROM_LAYOUT_VERSIONS default "<not defined>" help Help printed with the LAYOUT VERSIONS part of the 'eeprom' diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 88c77d99929..327712a536c 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -14,6 +14,7 @@ /* Please use abootimg_addr() macro to obtain the boot image address */ static ulong _abootimg_addr = -1; +static ulong _ainit_bootimg_addr = -1; static ulong _avendor_bootimg_addr = -1; ulong get_abootimg_addr(void) @@ -21,6 +22,11 @@ ulong get_abootimg_addr(void) return (_abootimg_addr == -1 ? image_load_addr : _abootimg_addr); } +ulong get_ainit_bootimg_addr(void) +{ + return _ainit_bootimg_addr; +} + ulong get_avendor_bootimg_addr(void) { return _avendor_bootimg_addr; @@ -179,7 +185,7 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc, char *endp; ulong img_addr; - if (argc < 2 || argc > 3) + if (argc < 2 || argc > 4) return CMD_RET_USAGE; img_addr = hextoul(argv[1], &endp); @@ -190,16 +196,26 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc, _abootimg_addr = img_addr; - if (argc == 3) { + if (argc > 2) { img_addr = simple_strtoul(argv[2], &endp, 16); if (*endp != '\0') { - printf("Error: Wrong vendor image address\n"); + printf("Error: Wrong vendor_boot image address\n"); return CMD_RET_FAILURE; } _avendor_bootimg_addr = img_addr; } + if (argc == 4) { + img_addr = simple_strtoul(argv[3], &endp, 16); + if (*endp != '\0') { + printf("Error: Wrong init_boot image address\n"); + return CMD_RET_FAILURE; + } + + _ainit_bootimg_addr = img_addr; + } + return CMD_RET_SUCCESS; } @@ -243,7 +259,7 @@ static int do_abootimg_dump(struct cmd_tbl *cmdtp, int flag, int argc, } static struct cmd_tbl cmd_abootimg_sub[] = { - U_BOOT_CMD_MKENT(addr, 3, 1, do_abootimg_addr, "", ""), + U_BOOT_CMD_MKENT(addr, 4, 1, do_abootimg_addr, "", ""), U_BOOT_CMD_MKENT(dump, 2, 1, do_abootimg_dump, "", ""), U_BOOT_CMD_MKENT(get, 5, 1, do_abootimg_get, "", ""), }; @@ -271,7 +287,7 @@ static int do_abootimg(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD( abootimg, CONFIG_SYS_MAXARGS, 0, do_abootimg, "manipulate Android Boot Image", - "addr <boot_img_addr> [<vendor_boot_img_addr>]>\n" + "addr <boot_img_addr> [<vendor_boot_img_addr> [<init_boot_img_addr>]]\n" " - set the address in RAM where boot image is located\n" " ($loadaddr is used by default)\n" "abootimg dump dtb\n" diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 26f3750a80a..cf89cfce3e4 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -21,8 +21,10 @@ #include <config.h> #include <command.h> +#include <dm.h> #include <eeprom.h> #include <i2c.h> +#include <i2c_eeprom.h> #include <eeprom_layout.h> #include <vsprintf.h> #include <linux/delay.h> @@ -208,41 +210,95 @@ static long parse_numeric_param(char *str) return (*endptr != '\0') ? -1 : value; } +struct eeprom_dev_spec { +#if CONFIG_IS_ENABLED(I2C_EEPROM) + struct udevice *dev; +#endif + int i2c_bus; + ulong i2c_addr; +}; + +static void eeprom_dev_spec_init(struct eeprom_dev_spec *dev) +{ +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (!dev->dev) +#endif + eeprom_init(dev->i2c_bus); +} + +static int eeprom_dev_spec_read(struct eeprom_dev_spec *dev, + unsigned offset, uchar *buffer, unsigned cnt) +{ +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (dev->dev) + return i2c_eeprom_read(dev->dev, offset, buffer, cnt); +#endif + return eeprom_read(dev->i2c_addr, offset, buffer, cnt); +} + +static int eeprom_dev_spec_write(struct eeprom_dev_spec *dev, + unsigned offset, uchar *buffer, unsigned cnt) +{ +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (dev->dev) + return i2c_eeprom_write(dev->dev, offset, buffer, cnt); +#endif + return eeprom_write(dev->i2c_addr, offset, buffer, cnt); +} + /** - * parse_i2c_bus_addr - parse the i2c bus and i2c devaddr parameters + * parse_eeprom_dev_spec - parse the eeprom device specifier * - * @i2c_bus: address to store the i2c bus - * @i2c_addr: address to store the device i2c address - * @argc: count of command line arguments left to parse + * @dev: pointer to eeprom device specifier + * @argc: count of command line arguments that can be used to parse + * the device specifier * @argv: command line arguments left to parse - * @argc_no_bus_addr: argc value we expect to see when bus & addr aren't given * * @returns: number of arguments parsed or CMD_RET_USAGE if error */ -static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc, - char *const argv[], int argc_no_bus_addr) +static int parse_eeprom_dev_spec(struct eeprom_dev_spec *dev, int argc, + char *const argv[]) { - int argc_no_bus = argc_no_bus_addr + 1; - int argc_bus_addr = argc_no_bus_addr + 2; +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (argc == 0) { + if (!uclass_first_device_err(UCLASS_I2C_EEPROM, &dev->dev)) + return 0; + } + + if (argc == 1) { + if (!uclass_get_device_by_name(UCLASS_I2C_EEPROM, argv[0], + &dev->dev)) + return 1; + + /* + * If we could not find the device by name and the parameter is + * not numeric (and so won't be handled later), fail. + */ + if (parse_numeric_param(argv[0]) == -1) { + printf("Can't get eeprom device: %s\n", argv[0]); + return CMD_RET_USAGE; + } + } +#endif #ifdef CONFIG_SYS_I2C_EEPROM_ADDR - if (argc == argc_no_bus_addr) { - *i2c_bus = -1; - *i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR; + if (argc == 0) { + dev->i2c_bus = -1; + dev->i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR; return 0; } #endif - if (argc == argc_no_bus) { - *i2c_bus = -1; - *i2c_addr = parse_numeric_param(argv[0]); + if (argc == 1) { + dev->i2c_bus = -1; + dev->i2c_addr = parse_numeric_param(argv[0]); return 1; } - if (argc == argc_bus_addr) { - *i2c_bus = parse_numeric_param(argv[0]); - *i2c_addr = parse_numeric_param(argv[1]); + if (argc == 2) { + dev->i2c_bus = parse_numeric_param(argv[0]); + dev->i2c_addr = parse_numeric_param(argv[1]); return 2; } @@ -252,16 +308,19 @@ static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc, #ifdef CONFIG_CMD_EEPROM_LAYOUT +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS __weak int eeprom_parse_layout_version(char *str) { return LAYOUT_VERSION_UNRECOGNIZED; } +#endif static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE]; #endif enum eeprom_action { + EEPROM_LIST, EEPROM_READ, EEPROM_WRITE, EEPROM_PRINT, @@ -271,6 +330,10 @@ enum eeprom_action { static enum eeprom_action parse_action(char *cmd) { +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (!strncmp(cmd, "list", 4)) + return EEPROM_LIST; +#endif if (!strncmp(cmd, "read", 4)) return EEPROM_READ; if (!strncmp(cmd, "write", 5)) @@ -285,68 +348,115 @@ static enum eeprom_action parse_action(char *cmd) return EEPROM_ACTION_INVALID; } -static int eeprom_execute_command(enum eeprom_action action, int i2c_bus, - ulong i2c_addr, int layout_ver, char *key, - char *value, ulong addr, ulong off, ulong cnt) +#if CONFIG_IS_ENABLED(I2C_EEPROM) +static int do_eeprom_list(void) +{ + struct udevice *dev; + struct uclass *uc; + int err; + + err = uclass_get(UCLASS_I2C_EEPROM, &uc); + if (err) + return CMD_RET_FAILURE; + + uclass_foreach_dev(dev, uc) + printf("%s (%s)\n", dev->name, dev->driver->name); + + return CMD_RET_SUCCESS; +} +#endif + +static int do_eeprom_rw(struct eeprom_dev_spec *dev, bool read, + ulong addr, ulong off, ulong cnt) { - int rcode = 0; const char *const fmt = "\nEEPROM @0x%lX %s: addr 0x%08lx off 0x%04lx count %ld ... "; + uchar *memloc = (uchar *)addr; + int ret; + + printf(fmt, dev->i2c_addr, read ? "read" : "write", addr, off, cnt); + if (read) + ret = eeprom_dev_spec_read(dev, off, memloc, cnt); + else + ret = eeprom_dev_spec_write(dev, off, memloc, cnt); + puts("done\n"); + + return ret; +} + #ifdef CONFIG_CMD_EEPROM_LAYOUT - struct eeprom_layout layout; -#endif - if (action == EEPROM_ACTION_INVALID) - return CMD_RET_USAGE; +static int do_eeprom_layout(struct eeprom_dev_spec *dev, int layout_ver, + struct eeprom_layout *layout) +{ + eeprom_layout_setup(layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, + layout_ver); - eeprom_init(i2c_bus); - if (action == EEPROM_READ) { - printf(fmt, i2c_addr, "read", addr, off, cnt); + return eeprom_dev_spec_read(dev, 0, eeprom_buf, layout->data_size); +} - rcode = eeprom_read(i2c_addr, off, (uchar *)addr, cnt); +static int do_eeprom_print(struct eeprom_dev_spec *dev, int layout_ver) +{ + struct eeprom_layout layout; + int ret; - puts("done\n"); - return rcode; - } else if (action == EEPROM_WRITE) { - printf(fmt, i2c_addr, "write", addr, off, cnt); + ret = do_eeprom_layout(dev, layout_ver, &layout); + if (ret) + return ret; - rcode = eeprom_write(i2c_addr, off, (uchar *)addr, cnt); + layout.print(&layout); - puts("done\n"); - return rcode; - } + return 0; +} -#ifdef CONFIG_CMD_EEPROM_LAYOUT - rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE); - if (rcode < 0) - return rcode; +static int do_eeprom_update(struct eeprom_dev_spec *dev, int layout_ver, + char *key, char *value) +{ + struct eeprom_layout layout; + int ret; - eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, - layout_ver); + ret = do_eeprom_layout(dev, layout_ver, &layout); + if (ret) + return ret; - if (action == EEPROM_PRINT) { - layout.print(&layout); - return 0; - } + ret = layout.update(&layout, key, value); + if (ret) + return CMD_RET_FAILURE; - layout.update(&layout, key, value); + return eeprom_dev_spec_write(dev, 0, layout.data, layout.data_size); +} - rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE); #endif - return rcode; +static int eeprom_action_expected_argc(enum eeprom_action action) +{ + switch (action) { + case EEPROM_LIST: + return 0; + case EEPROM_READ: + case EEPROM_WRITE: + return 3; + case EEPROM_PRINT: + return 0; + case EEPROM_UPDATE: + return 2; + default: + return CMD_RET_USAGE; + } } #define NEXT_PARAM(argc, index) { (argc)--; (index)++; } int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int layout_ver = LAYOUT_VERSION_AUTODETECT; enum eeprom_action action = EEPROM_ACTION_INVALID; - int i2c_bus = -1, index = 0; - ulong i2c_addr = -1, addr = 0, cnt = 0, off = 0; - int ret; + struct eeprom_dev_spec dev; + ulong addr = 0, cnt = 0, off = 0; + int ret, index = 0; +#ifdef CONFIG_CMD_EEPROM_LAYOUT char *field_name = ""; char *field_value = ""; + int layout_ver = LAYOUT_VERSION_AUTODETECT; +#endif if (argc <= 1) return CMD_RET_USAGE; @@ -359,7 +469,12 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (action == EEPROM_ACTION_INVALID) return CMD_RET_USAGE; -#ifdef CONFIG_CMD_EEPROM_LAYOUT +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (action == EEPROM_LIST) + return do_eeprom_list(); +#endif + +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS if (action == EEPROM_PRINT || action == EEPROM_UPDATE) { if (!strcmp(argv[index], "-l")) { NEXT_PARAM(argc, index); @@ -369,25 +484,9 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - switch (action) { - case EEPROM_READ: - case EEPROM_WRITE: - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, - argv + index, 3); - break; - case EEPROM_PRINT: - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, - argv + index, 0); - break; - case EEPROM_UPDATE: - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, - argv + index, 2); - break; - default: - /* Get compiler to stop whining */ - return CMD_RET_USAGE; - } - + ret = parse_eeprom_dev_spec(&dev, + argc - eeprom_action_expected_argc(action), + argv + index); if (ret == CMD_RET_USAGE) return ret; @@ -411,24 +510,64 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver, - field_name, field_value, addr, off, cnt); + eeprom_dev_spec_init(&dev); + + switch (action) { + case EEPROM_READ: + case EEPROM_WRITE: + return do_eeprom_rw(&dev, action == EEPROM_READ, + addr, off, cnt); +#ifdef CONFIG_CMD_EEPROM_LAYOUT + case EEPROM_PRINT: + return do_eeprom_print(&dev, layout_ver); + case EEPROM_UPDATE: + return do_eeprom_update(&dev, layout_ver, + field_name, field_value); +#endif + default: + return CMD_RET_USAGE; + } } +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS +#define EEPROM_LAYOUT_SPEC "[-l <layout_version>] " +#else +#define EEPROM_LAYOUT_SPEC "" +#endif + +#if CONFIG_IS_ENABLED(I2C_EEPROM) +# define EEPROM_DEV_SPEC "[device_specifier]" +#else +# define EEPROM_DEV_SPEC "[[bus] devaddr]" +#endif + U_BOOT_CMD( eeprom, 8, 1, do_eeprom, "EEPROM sub-system", - "read <bus> <devaddr> addr off cnt\n" - "eeprom write <bus> <devaddr> addr off cnt\n" +#if CONFIG_IS_ENABLED(I2C_EEPROM) + "list\n" + "eeprom " +#endif + "read " EEPROM_DEV_SPEC " addr off cnt\n" + "eeprom write " EEPROM_DEV_SPEC " addr off cnt\n" " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'" #ifdef CONFIG_CMD_EEPROM_LAYOUT "\n" - "eeprom print [-l <layout_version>] <bus> <devaddr>\n" + "eeprom print " EEPROM_LAYOUT_SPEC EEPROM_DEV_SPEC "\n" " - Print layout fields and their data in human readable format\n" - "eeprom update [-l <layout_version>] <bus> <devaddr> field_name field_value\n" + "eeprom update " EEPROM_LAYOUT_SPEC EEPROM_DEV_SPEC " field_name field_value\n" " - Update a specific eeprom field with new data.\n" - " The new data must be written in the same human readable format as shown by the print command.\n" - "\n" + " The new data must be written in the same human readable format as shown by the print command." +#endif +#if CONFIG_IS_ENABLED(I2C_EEPROM) + "\n\n" + "DEVICE SPECIFIER - the eeprom device can be specified\n" + " [dev_name] - by device name (devices can listed with the eeprom list command)\n" + " [[bus] devaddr] - or by I2C bus and I2C device address\n" + "If no device specifier is given, the first driver-model found device is used." +#endif +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS + "\n\n" "LAYOUT VERSIONS\n" "The -l option can be used to force the command to interpret the EEPROM data using the chosen layout.\n" "If the -l option is omitted, the command will auto detect the layout based on the data in the EEPROM.\n" diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 4164cb4f9b8..bea09e4ecc7 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -61,6 +61,7 @@ struct eficonfig_filepath_info { struct eficonfig_boot_option { struct eficonfig_select_file_info file_info; struct eficonfig_select_file_info initrd_info; + struct eficonfig_select_file_info fdt_info; unsigned int boot_index; u16 *description; u16 *optional_data; @@ -530,7 +531,7 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_ dp = efi_dp_shorten(dp_volume); if (!dp) dp = dp_volume; - dp = efi_dp_concat(dp, &fp->dp, false); + dp = efi_dp_concat(dp, &fp->dp, 0); free(buf); return dp; @@ -1307,6 +1308,10 @@ static efi_status_t eficonfig_show_boot_option(struct eficonfig_boot_option *bo, if (ret != EFI_SUCCESS) goto out; + ret = prepare_file_selection_entry(efi_menu, "Fdt File: ", &bo->fdt_info); + if (ret != EFI_SUCCESS) + goto out; + ret = create_boot_option_entry(efi_menu, "Optional Data: ", bo->optional_data, eficonfig_boot_add_optional_data, bo); if (ret != EFI_SUCCESS) @@ -1387,27 +1392,44 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo efi_status_t ret; char *tmp = NULL, *p; struct efi_load_option lo = {0}; - efi_uintn_t final_dp_size; + efi_uintn_t dp_size; struct efi_device_path *dp = NULL; efi_uintn_t size = load_option_size; - struct efi_device_path *final_dp = NULL; struct efi_device_path *device_dp = NULL; struct efi_device_path *initrd_dp = NULL; + struct efi_device_path *fdt_dp = NULL; struct efi_device_path *initrd_device_dp = NULL; + struct efi_device_path *fdt_device_dp = NULL; - const struct efi_initrd_dp id_dp = { + const struct efi_lo_dp_prefix initrd_prefix = { .vendor = { { DEVICE_PATH_TYPE_MEDIA_DEVICE, DEVICE_PATH_SUB_TYPE_VENDOR_PATH, - sizeof(id_dp.vendor), + sizeof(initrd_prefix.vendor), }, EFI_INITRD_MEDIA_GUID, }, .end = { DEVICE_PATH_TYPE_END, DEVICE_PATH_SUB_TYPE_END, - sizeof(id_dp.end), + sizeof(initrd_prefix.end), + } + }; + + const struct efi_lo_dp_prefix fdt_prefix = { + .vendor = { + { + DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_VENDOR_PATH, + sizeof(fdt_prefix.vendor), + }, + EFI_FDT_GUID, + }, + .end = { + DEVICE_PATH_TYPE_END, + DEVICE_PATH_SUB_TYPE_END, + sizeof(initrd_prefix.end), } }; @@ -1423,6 +1445,12 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } + bo->fdt_info.current_path = calloc(1, EFICONFIG_FILE_PATH_BUF_SIZE); + if (!bo->fdt_info.current_path) { + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + bo->description = calloc(1, EFICONFIG_DESCRIPTION_MAX * sizeof(u16)); if (!bo->description) { ret = EFI_OUT_OF_RESOURCES; @@ -1455,13 +1483,20 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo if (lo.file_path) fill_file_info(lo.file_path, &bo->file_info, device_dp); - /* Initrd file path(optional) is placed at second instance. */ + /* Initrd file path (optional) is placed at second instance. */ initrd_dp = efi_dp_from_lo(&lo, &efi_lf2_initrd_guid); if (initrd_dp) { fill_file_info(initrd_dp, &bo->initrd_info, initrd_device_dp); efi_free_pool(initrd_dp); } + /* Fdt file path (optional) is placed as third instance. */ + fdt_dp = efi_dp_from_lo(&lo, &efi_guid_fdt); + if (fdt_dp) { + fill_file_info(fdt_dp, &bo->fdt_info, fdt_device_dp); + efi_free_pool(fdt_dp); + } + if (size > 0) memcpy(bo->optional_data, lo.optional_data, size); } @@ -1483,8 +1518,20 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo ret = EFI_OUT_OF_RESOURCES; goto out; } - initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, - dp, false); + initrd_dp = efi_dp_concat((const struct efi_device_path *)&initrd_prefix, + dp, 0); + efi_free_pool(dp); + } + + if (bo->fdt_info.dp_volume) { + dp = eficonfig_create_device_path(bo->fdt_info.dp_volume, + bo->fdt_info.current_path); + if (!dp) { + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + fdt_dp = efi_dp_concat((const struct efi_device_path *)&fdt_prefix, + dp, 0); efi_free_pool(dp); } @@ -1493,16 +1540,9 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo ret = EFI_OUT_OF_RESOURCES; goto out; } - final_dp_size = efi_dp_size(dp) + sizeof(END); - if (initrd_dp) { - final_dp = efi_dp_concat(dp, initrd_dp, true); - final_dp_size += efi_dp_size(initrd_dp) + sizeof(END); - } else { - final_dp = efi_dp_dup(dp); - } - efi_free_pool(dp); - if (!final_dp) + ret = efi_load_option_dp_join(&dp, &dp_size, initrd_dp, fdt_dp); + if (ret != EFI_SUCCESS) goto out; if (utf16_utf8_strlen(bo->optional_data)) { @@ -1514,17 +1554,20 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo utf16_utf8_strncpy(&p, bo->optional_data, u16_strlen(bo->optional_data)); } - ret = eficonfig_set_boot_option(varname, final_dp, final_dp_size, bo->description, tmp); + ret = eficonfig_set_boot_option(varname, dp, dp_size, bo->description, tmp); out: free(tmp); free(bo->optional_data); free(bo->description); free(bo->file_info.current_path); free(bo->initrd_info.current_path); + free(bo->fdt_info.current_path); efi_free_pool(device_dp); efi_free_pool(initrd_device_dp); efi_free_pool(initrd_dp); - efi_free_pool(final_dp); + efi_free_pool(fdt_device_dp); + efi_free_pool(fdt_dp); + efi_free_pool(dp); return ret; } diff --git a/cmd/efidebug.c b/cmd/efidebug.c index e978e74aad9..1a191eb9994 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -653,38 +653,80 @@ static int do_efi_show_tables(struct cmd_tbl *cmdtp, int flag, } /** - * create_initrd_dp() - create a special device for our Boot### option + * enum efi_lo_dp_part - part of device path in load option + */ +enum efi_lo_dp_part { + /** @EFI_LO_DP_PART_BINARY: binary */ + EFI_LO_DP_PART_BINARY, + /** @EFI_LO_DP_PART_INITRD: initial RAM disk */ + EFI_LO_DP_PART_INITRD, + /** @EFI_LP_DP_PART_FDT: device-tree */ + EFI_LP_DP_PART_FDT, +}; + +/** + * create_lo_dp() - create a special device path for our Boot### option * * @dev: device * @part: disk partition * @file: filename * @shortform: create short form device path + * @type: part of device path to be created * Return: pointer to the device path or ERR_PTR */ static -struct efi_device_path *create_initrd_dp(const char *dev, const char *part, - const char *file, int shortform) +struct efi_device_path *create_lo_dp_part(const char *dev, const char *part, + const char *file, bool shortform, + enum efi_lo_dp_part type) { struct efi_device_path *tmp_dp = NULL, *tmp_fp = NULL, *short_fp = NULL; - struct efi_device_path *initrd_dp = NULL; + struct efi_device_path *dp = NULL; + const struct efi_device_path *dp_prefix; efi_status_t ret; - const struct efi_initrd_dp id_dp = { + const struct efi_lo_dp_prefix fdt_dp = { .vendor = { { DEVICE_PATH_TYPE_MEDIA_DEVICE, DEVICE_PATH_SUB_TYPE_VENDOR_PATH, - sizeof(id_dp.vendor), + sizeof(fdt_dp.vendor), + }, + EFI_FDT_GUID, + }, + .end = { + DEVICE_PATH_TYPE_END, + DEVICE_PATH_SUB_TYPE_END, + sizeof(fdt_dp.end), + } + }; + const struct efi_lo_dp_prefix initrd_dp = { + .vendor = { + { + DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_VENDOR_PATH, + sizeof(initrd_dp.vendor), }, EFI_INITRD_MEDIA_GUID, }, .end = { DEVICE_PATH_TYPE_END, DEVICE_PATH_SUB_TYPE_END, - sizeof(id_dp.end), + sizeof(initrd_dp.end), } }; + switch (type) { + case EFI_LO_DP_PART_INITRD: + dp_prefix = &initrd_dp.vendor.dp; + break; + case EFI_LP_DP_PART_FDT: + dp_prefix = &fdt_dp.vendor.dp; + break; + default: + dp_prefix = NULL; + break; + } + ret = efi_dp_from_name(dev, part, file, &tmp_dp, &tmp_fp); if (ret != EFI_SUCCESS) { printf("Cannot create device path for \"%s %s\"\n", part, file); @@ -695,13 +737,12 @@ struct efi_device_path *create_initrd_dp(const char *dev, const char *part, if (!short_fp) short_fp = tmp_fp; - initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, - short_fp, false); + dp = efi_dp_concat(dp_prefix, short_fp, 0); out: efi_free_pool(tmp_dp); efi_free_pool(tmp_fp); - return initrd_dp; + return dp; } /** @@ -792,9 +833,8 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, efi_guid_t guid; u16 *label; struct efi_device_path *file_path = NULL; - struct efi_device_path *fp_free = NULL; - struct efi_device_path *final_fp = NULL; struct efi_device_path *initrd_dp = NULL; + struct efi_device_path *fdt_dp = NULL; struct efi_load_option lo; void *data = NULL; efi_uintn_t size; @@ -842,22 +882,31 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, lo.label = label; /* label will be changed below */ /* file path */ - ret = efi_dp_from_name(argv[3], argv[4], argv[5], - NULL, &fp_free); - if (ret != EFI_SUCCESS) { - printf("Cannot create device path for \"%s %s\"\n", - argv[3], argv[4]); + file_path = create_lo_dp_part(argv[3], argv[4], argv[5], + shortform, + EFI_LO_DP_PART_BINARY); + argc -= 5; + argv += 5; + break; + case 'd': + shortform = 1; + fallthrough; + case 'D': + if (argc < 3 || fdt_dp) { + r = CMD_RET_USAGE; + goto out; + } + + fdt_dp = create_lo_dp_part(argv[1], argv[2], argv[3], + shortform, + EFI_LP_DP_PART_FDT); + if (!fdt_dp) { + printf("Cannot add a device-tree\n"); r = CMD_RET_FAILURE; goto out; } - if (shortform) - file_path = efi_dp_shorten(fp_free); - if (!file_path) - file_path = fp_free; - fp_size += efi_dp_size(file_path) + - sizeof(struct efi_device_path); - argc -= 5; - argv += 5; + argc -= 3; + argv += 3; break; case 'i': shortform = 1; @@ -868,8 +917,9 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, goto out; } - initrd_dp = create_initrd_dp(argv[1], argv[2], argv[3], - shortform); + initrd_dp = create_lo_dp_part(argv[1], argv[2], argv[3], + shortform, + EFI_LO_DP_PART_INITRD); if (!initrd_dp) { printf("Cannot add an initrd\n"); r = CMD_RET_FAILURE; @@ -877,8 +927,6 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, } argc -= 3; argv += 3; - fp_size += efi_dp_size(initrd_dp) + - sizeof(struct efi_device_path); break; case 's': if (argc < 1 || lo.optional_data) { @@ -896,7 +944,6 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, &file_path, &fp_size); if (r != CMD_RET_SUCCESS) goto out; - fp_free = file_path; argc -= 3; argv += 3; } else{ @@ -916,14 +963,14 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, goto out; } - final_fp = efi_dp_concat(file_path, initrd_dp, true); - if (!final_fp) { + ret = efi_load_option_dp_join(&file_path, &fp_size, initrd_dp, fdt_dp); + if (ret != EFI_SUCCESS) { printf("Cannot create final device path\n"); r = CMD_RET_FAILURE; goto out; } - lo.file_path = final_fp; + lo.file_path = file_path; lo.file_path_length = fp_size; size = efi_serialize_load_option(&lo, (u8 **)&data); @@ -944,9 +991,9 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, out: free(data); - efi_free_pool(final_fp); efi_free_pool(initrd_dp); - efi_free_pool(fp_free); + efi_free_pool(fdt_dp); + efi_free_pool(file_path); free(lo.label); return r; @@ -1008,7 +1055,8 @@ static int do_efi_boot_rm(struct cmd_tbl *cmdtp, int flag, */ static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size) { - struct efi_device_path *initrd_path = NULL; + struct efi_device_path *fdt_path; + struct efi_device_path *initrd_path; struct efi_load_option lo; efi_status_t ret; @@ -1037,6 +1085,12 @@ static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size) efi_free_pool(initrd_path); } + fdt_path = efi_dp_from_lo(&lo, &efi_guid_fdt); + if (fdt_path) { + printf(" device-tree path: %pD\n", fdt_path); + efi_free_pool(fdt_path); + } + printf(" data:\n"); print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, lo.optional_data, *size, true); @@ -1564,8 +1618,9 @@ U_BOOT_LONGHELP(efidebug, "\n" "efidebug boot add - set UEFI BootXXXX variable\n" " -b|-B <bootid> <label> <interface> <devnum>[:<part>] <file path>\n" + " -d|-D <interface> <devnum>[:<part>] <device-tree file path>\n" " -i|-I <interface> <devnum>[:<part>] <initrd file path>\n" - " (-b, -i for short form device path)\n" + " (-b, -d, -i for short form device path)\n" #if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) " -u <bootid> <label> <uri>\n" #endif diff --git a/cmd/ximg.c b/cmd/ximg.c index 1467484df8d..c79e8a07860 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -15,6 +15,9 @@ #include <cpu_func.h> #include <env.h> #include <gzip.h> +#if IS_ENABLED(CONFIG_ZSTD) +#include <linux/zstd.h> +#endif #include <image.h> #include <malloc.h> #include <mapmem.h> @@ -237,6 +240,26 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } break; #endif /* CONFIG_BZIP2 */ +#if IS_ENABLED(CONFIG_ZSTD) + case IH_COMP_ZSTD: + { + int ret; + struct abuf in, out; + + printf(" Uncompressing part %d ... ", part); + + abuf_init_set(&in, (void *)data, len); + abuf_init_set(&out, (void *)dest, unc_len); + ret = zstd_decompress(&in, &out); + if (ret < 0) { + printf("ZSTD ERROR %d - " + "image not loaded\n", ret); + return 1; + } + len = ret; + } + break; +#endif default: printf("Unimplemented compression type %d\n", comp); return 1; diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c index 3bacb1ae7eb..64b9db18c25 100644 --- a/common/eeprom/eeprom_field.c +++ b/common/eeprom/eeprom_field.c @@ -56,8 +56,8 @@ static int __eeprom_field_update_bin(struct eeprom_field *field, tmp[k] = value[reverse ? i - 1 + k : i + k]; } - byte = simple_strtoul(tmp, &endptr, 0); - if (*endptr != '\0' || byte < 0) + byte = simple_strtoul(tmp, &endptr, 16); + if (*endptr != '\0') return -1; field->buf[j] = byte; diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c index 1a425c1754d..8c0b7e0b393 100644 --- a/common/eeprom/eeprom_layout.c +++ b/common/eeprom/eeprom_layout.c @@ -57,6 +57,28 @@ static void eeprom_layout_print(const struct eeprom_layout *layout) } /* + * eeprom_layout_find_field() - finds a layout field by name + * @layout: A pointer to an existing struct layout. + * @field_name: The name of the field to update. + * @warn: Whether to print a warning if the field is not found. + * + * Returns: a pointer to the found field or NULL on failure. + */ +struct eeprom_field *eeprom_layout_find_field(struct eeprom_layout *layout, + char *field_name, bool warn) +{ + for (int i = 0; i < layout->num_of_fields; i++) + if (layout->fields[i].name != RESERVED_FIELDS && + !strcmp(layout->fields[i].name, field_name)) + return &layout->fields[i]; + + if (warn) + printf("No such field '%s'\n", field_name); + + return NULL; +} + +/* * eeprom_layout_update_field() - update a single field in the layout data. * @layout: A pointer to an existing struct layout. * @field_name: The name of the field to update. @@ -67,8 +89,8 @@ static void eeprom_layout_print(const struct eeprom_layout *layout) static int eeprom_layout_update_field(struct eeprom_layout *layout, char *field_name, char *new_data) { - int i, err; - struct eeprom_field *fields = layout->fields; + struct eeprom_field *field; + int err; if (new_data == NULL) return 0; @@ -76,21 +98,15 @@ static int eeprom_layout_update_field(struct eeprom_layout *layout, if (field_name == NULL) return -1; - for (i = 0; i < layout->num_of_fields; i++) { - if (fields[i].name == RESERVED_FIELDS || - strcmp(fields[i].name, field_name)) - continue; - - err = fields[i].update(&fields[i], new_data); - if (err) - printf("Invalid data for field %s\n", field_name); - - return err; - } + field = eeprom_layout_find_field(layout, field_name, true); + if (field == NULL) + return -1; - printf("No such field '%s'\n", field_name); + err = field->update(field, new_data); + if (err) + printf("Invalid data for field %s\n", field_name); - return -1; + return err; } /* @@ -111,14 +127,14 @@ void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, else layout->layout_version = layout_version; + layout->data_size = buf_size; + layout->print = eeprom_layout_print; + layout->update = eeprom_layout_update_field; + eeprom_layout_assign(layout, layout_version); layout->data = buf; for (i = 0; i < layout->num_of_fields; i++) { layout->fields[i].buf = buf; buf += layout->fields[i].size; } - - layout->data_size = buf_size; - layout->print = eeprom_layout_print; - layout->update = eeprom_layout_update_field; } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6405374bcc1..e0889401ecc 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -409,6 +409,7 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE hex "Size of malloc_simple heap after switching to DRAM SPL stack" default 0x400000 if ARCH_K3 && ARM64 + default 0x200000 if ARCH_K3 && CPU_V7R default 0x100000 help Specify the amount of the stack to use as memory pool for @@ -1293,7 +1294,7 @@ config SPL_SATA_RAW_U_BOOT_SECTOR config SPL_NVME bool "NVM Express device support" - depends on BLK + depends on SPL_BLK select FS_LOADER select SPL_BLK_FS help diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index e1f0ab4e472..d73b1cb804b 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -74,6 +74,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index ea5b69f58e0..89e212595af 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -50,6 +50,7 @@ CONFIG_DFU_SF=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_POWER_TPS65218=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 89411324720..2ff01193285 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -64,6 +64,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index bf8cdba189e..845b686ac93 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -77,6 +77,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 8a7a3dfbd66..ff5073cbb2b 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index ebfad6a9c52..5ef59d830e5 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -51,6 +51,7 @@ CONFIG_DFU_SF=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_POWER_TPS65218=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index bfa78f0e100..7c3ceeb07db 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -94,6 +94,7 @@ CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 7be94aef27a..1f7eca4691e 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -90,6 +90,7 @@ CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 055e29b43d8..807e1d66a6d 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -88,6 +88,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index b365c7ea902..ace55696737 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c4b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3C000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 CONFIG_SPL_FS_FAT=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 648241488ed..4b2e57b13a0 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index e8dc60c6ce1..6d70cc201c7 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -99,6 +99,7 @@ CONFIG_SYS_MXC_I2C3_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=15000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_FEC_MXC=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 9bbc723f9c7..62dbf2aa48f 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -64,6 +64,7 @@ CONFIG_MMC_SDHCI_MV=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig index 9ddd5d295fe..41382f995d3 100644 --- a/configs/clearfog_sata_defconfig +++ b/configs/clearfog_sata_defconfig @@ -65,6 +65,7 @@ CONFIG_MMC_SDHCI_MV=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig index 4175fdb17a1..f345b12e6c7 100644 --- a/configs/clearfog_spi_defconfig +++ b/configs/clearfog_spi_defconfig @@ -65,6 +65,7 @@ CONFIG_MMC_SDHCI_MV=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index a4d5f91b35f..386616cc420 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_VERSIONS=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 93e667292c8..32f126a5174 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_PROMPT="CM-T43 # " CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_VERSIONS=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index cf7499bb16f..6fe9750841f 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -85,6 +85,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_STMICRO=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig index 8f20f651560..eb5743da64d 100644 --- a/configs/cortina_presidio-asic-base_defconfig +++ b/configs/cortina_presidio-asic-base_defconfig @@ -38,3 +38,4 @@ CONFIG_DM_SERIAL=y CONFIG_CORTINA_UART=y CONFIG_WDT=y CONFIG_WDT_CORTINA=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig index 94dc3e1e2e8..c7367d4d91c 100644 --- a/configs/cortina_presidio-asic-pnand_defconfig +++ b/configs/cortina_presidio-asic-pnand_defconfig @@ -43,3 +43,4 @@ CONFIG_DM_SERIAL=y CONFIG_CORTINA_UART=y CONFIG_WDT=y CONFIG_WDT_CORTINA=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig index a8f17570eca..c3d4594b75f 100644 --- a/configs/crs305-1g-4s-bit_defconfig +++ b/configs/crs305-1g-4s-bit_defconfig @@ -47,3 +47,4 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index c66d291eb92..1919e8c7794 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -48,3 +48,4 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig index b754dac45ec..a584c26eb90 100644 --- a/configs/crs326-24g-2s-bit_defconfig +++ b/configs/crs326-24g-2s-bit_defconfig @@ -47,3 +47,4 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig index 870127d3872..43f7455afbf 100644 --- a/configs/crs326-24g-2s_defconfig +++ b/configs/crs326-24g-2s_defconfig @@ -47,3 +47,4 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig index 2373775dc5a..7bf671643a9 100644 --- a/configs/crs328-4c-20s-4s-bit_defconfig +++ b/configs/crs328-4c-20s-4s-bit_defconfig @@ -47,3 +47,4 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig index 9bac12217a0..2f50bdaf1e7 100644 --- a/configs/crs328-4c-20s-4s_defconfig +++ b/configs/crs328-4c-20s-4s_defconfig @@ -47,3 +47,4 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 33b8b806652..22a1e834247 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -64,6 +64,7 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVPP2=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 540a348fdcf..a6c862234a0 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -71,6 +71,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig index 4d4cf36749a..54457820568 100644 --- a/configs/db-88f6820-amc_nand_defconfig +++ b/configs/db-88f6820-amc_nand_defconfig @@ -75,6 +75,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 4f98ee4f382..ee8cb8ae66c 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -68,6 +68,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index d776693b600..f10a6fbccab 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -70,6 +70,7 @@ CONFIG_NAND_PXA3XX=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig index 1fc73802160..56bd56b1aaf 100644 --- a/configs/ds116_defconfig +++ b/configs/ds116_defconfig @@ -71,6 +71,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index ecf9501ba5a..18c741d4f28 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ANEG_TIMEOUT=16000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig index 00a9211fb05..d37749bd5e3 100644 --- a/configs/gxp_defconfig +++ b/configs/gxp_defconfig @@ -59,3 +59,4 @@ CONFIG_TIMER=y CONFIG_GXP_TIMER=y # CONFIG_RANDOM_UUID is not set CONFIG_SHA512=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index c4c5d48f4eb..29b6230e901 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -64,6 +64,7 @@ CONFIG_MMC_SDHCI_MV=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 149ce0bac0d..fc412d04ac7 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -68,6 +68,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig index a07689894ef..b92488587d8 100644 --- a/configs/hmibsc_defconfig +++ b/configs/hmibsc_defconfig @@ -61,6 +61,8 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCONF=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 68b24ce3fb0..5e6bbb3e508 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -124,6 +124,7 @@ CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_FIXED=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 53249f44a4e..f26a8791cd0 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -193,6 +193,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_DM_MDIO=y diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 3a622727232..05f68c7e2ae 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -87,6 +87,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DWC_ETH_QOS=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index b0dcbc723ba..3c337d4bd25 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -113,6 +113,7 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index 209d896b00c..fe3e757eefd 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -206,6 +206,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_MICREL=y diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig index 70126c961f3..aa1de6d6909 100644 --- a/configs/imx8mp_debix_model_a_defconfig +++ b/configs/imx8mp_debix_model_a_defconfig @@ -76,6 +76,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 76f2fe8fcc9..5944c6c5304 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -201,6 +201,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_SMSC=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 5b338f22195..7b3dae504f8 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -208,6 +208,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_SMSC=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index d907aedb05a..f5ba022b075 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -93,6 +93,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 393a1316cd9..54789365aa9 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -126,6 +126,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 6dd51a3f1fc..4b0b71d03d9 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -127,6 +127,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index 721c4cb9d11..b302df1f351 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -74,6 +74,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_FEC_MXC=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 5ad770f91e1..2246715d822 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -98,6 +98,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index abda6d12662..deed068550a 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -95,6 +95,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index e39d7dc5e88..94ce213f93a 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -112,6 +112,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ADIN=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_REALTEK=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index fe8e84c9214..4db5654ca1c 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -15,7 +15,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j7200-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -96,6 +96,7 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_CCF=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 3d8e9391987..451a6a91c4f 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -14,7 +14,7 @@ CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -88,7 +88,7 @@ CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk" +CONFIG_OF_LIST="ti/k3-j721e-common-proc-board" CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y @@ -101,6 +101,7 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index cea48b26136..37d582b7750 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -81,7 +81,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk" +CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/j721e_sk_a72_defconfig b/configs/j721e_sk_a72_defconfig new file mode 100644 index 00000000000..80e3e90cafd --- /dev/null +++ b/configs/j721e_sk_a72_defconfig @@ -0,0 +1,9 @@ +#include <configs/j721e_evm_a72_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_A72_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-sk" +CONFIG_OF_LIST="ti/k3-j721e-sk" diff --git a/configs/j721e_sk_r5_defconfig b/configs/j721e_sk_r5_defconfig new file mode 100644 index 00000000000..b361c691747 --- /dev/null +++ b/configs/j721e_sk_r5_defconfig @@ -0,0 +1,10 @@ +#include <configs/j721e_evm_r5_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_R5_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-sk" +CONFIG_SPL_OF_LIST="k3-j721e-r5-sk" +CONFIG_OF_LIST="k3-j721e-r5-sk" diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 5ed8d00662e..5c3b52baaee 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -10,6 +10,7 @@ CONFIG_SOC_K3_J721S2=y CONFIG_TARGET_J721S2_A72_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 3c958cafbe8..e676dbc03e4 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -10,6 +10,7 @@ CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J721S2_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000 +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y @@ -24,7 +25,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index bb9603bef0f..937b8810638 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -49,6 +49,8 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y @@ -59,6 +61,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -134,6 +137,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_SCSI=y CONFIG_DM_SERIAL=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index f5fe7432206..07edb7f62db 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -56,6 +55,8 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 88965e273e2..5d54d75f974 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -81,6 +81,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=10000 CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 3a45c41ef74..9adab3af305 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -57,6 +57,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=10000 CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index e2a87c4a81d..c2133470fc9 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -83,6 +83,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_TI=y CONFIG_PHY_GIGE=y CONFIG_FEC_MXC=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index a4a7f1a5cbd..868eeaf6c8e 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -77,6 +77,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MSCC=y CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 9906099e8c5..c5c3a69d73d 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y @@ -62,3 +63,4 @@ CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig index dc5a45fb0d8..2e1d112a3e7 100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -85,6 +85,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_TI=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index 817e4b3e119..3989c79d2b1 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -64,4 +64,5 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MTK_SPIM=y CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 35227ebd340..4d0cc85d0e5 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -64,4 +64,5 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MTK_SPIM=y CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 7f11e6f5d45..4c8a5960d38 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -44,3 +44,4 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y CONFIG_MXC_UART=y CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig index 5e13d2cb768..e7d7deabfe6 100644 --- a/configs/n2350_defconfig +++ b/configs/n2350_defconfig @@ -75,6 +75,7 @@ CONFIG_NAND_PXA3XX=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index 00fcd57f929..cb711f0ad4c 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 2be9e242b58..61513c9e2ec 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -104,5 +104,6 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_LZO=y +# CONFIG_EFI_LOADER is not set CONFIG_POST=y CONFIG_HUSH_OLD_PARSER=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 9245a56adea..ec0f975ae36 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -102,5 +102,6 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_LZO=y +# CONFIG_EFI_LOADER is not set CONFIG_POST=y CONFIG_HUSH_OLD_PARSER=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 033dd82b28e..82923d32ca6 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -104,5 +104,6 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_LZO=y +# CONFIG_EFI_LOADER is not set CONFIG_POST=y CONFIG_HUSH_OLD_PARSER=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 4d34ef6d680..41931e24768 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -102,5 +102,6 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_LZO=y +# CONFIG_EFI_LOADER is not set CONFIG_POST=y CONFIG_HUSH_OLD_PARSER=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index fd36edc29dd..7545bf2ea73 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 @@ -45,6 +46,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y @@ -59,6 +61,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y @@ -73,6 +76,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 389672d5227..82636e8890c 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_R5=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 @@ -26,7 +27,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y @@ -50,6 +50,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y @@ -88,6 +89,7 @@ CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SPL_MISC=y @@ -129,3 +131,4 @@ CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SYS_I2C_OMAP24XX=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 09ea1c54f13..9983dbd50eb 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y @@ -80,3 +81,4 @@ CONFIG_DM_SPI=y CONFIG_RENESAS_RPC_SPI=y CONFIG_TEE=y CONFIG_OPTEE=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig index 089c7544e5e..ab49d547d38 100644 --- a/configs/r8a77970_v3msk_defconfig +++ b/configs/r8a77970_v3msk_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 9f5212f93d8..1e7e430cd8b 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -75,6 +75,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig index 8c85f42ed42..e942acd83a8 100644 --- a/configs/r8a77980_v3hsk_defconfig +++ b/configs/r8a77980_v3hsk_defconfig @@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 3960a250d9e..7418d390d1d 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -89,6 +89,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 01f5b135959..29d921d16c4 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -86,6 +86,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index 40097f9dc34..7dbd1457d87 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig index 9ab46a4d5e0..e822e95eb81 100644 --- a/configs/r8a779f0_spider_defconfig +++ b/configs/r8a779f0_spider_defconfig @@ -64,6 +64,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHYLIB_10G=y CONFIG_PHY_MARVELL_10G=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index abc9a3ba611..a0abc45b72a 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index a986a09b8e0..6cbe27a316d 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 45d2446b8a1..318a9ab03e6 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index b5d81219246..f8e8c92b670 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -90,6 +90,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH_PHY=y diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 234c9650233..eebbaa99379 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ATHEROS=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 4c6009dbe45..d1b1c03cf4c 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -68,6 +68,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_REALTEK=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 54a03790459..256190ddabf 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -39,3 +39,4 @@ CONFIG_ENV_IS_IN_ONENAND=y CONFIG_MTD=y CONFIG_SAMSUNG_ONENAND=y CONFIG_SMC911X=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index f0a364a562b..0fff9080d41 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -68,3 +68,4 @@ CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 603b74401ea..c415248bb6e 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -67,6 +67,7 @@ CONFIG_MMC_DW=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 8442f0bfe94..c3e6b097db0 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -133,6 +133,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_DWC_ETH_QOS=y CONFIG_KS8851_MLL=y CONFIG_PHY=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 91b64f7537a..1eac11b5a44 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -131,6 +131,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DWC_ETH_QOS=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 9fbd7eb1575..87038cc773a 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -48,6 +48,7 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y CONFIG_WDT_ARM_SMC=y CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=32 diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index ed468b8fe9a..d237092bb96 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 247e32d8e37..b754cc01cc8 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -36,3 +36,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SKIP_INIT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 9753e270951..225a76f993d 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -96,6 +96,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_FIXED=y CONFIG_DM_DSA=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 06c63fa6488..8266a7f6e8f 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_LIBDISK_SUPPORT=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 9d3924cc9cb..b97bf5e60a9 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -62,4 +62,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set CONFIG_ARM_DCC=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 7a110350c2c..8f162597603 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -72,4 +72,5 @@ CONFIG_CADENCE_QSPI=y CONFIG_HAS_CQSPI_REF_CLK=y CONFIG_CQSPI_REF_CLK=200000000 CONFIG_CADENCE_OSPI_VERSAL=y +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 58945a1cac9..8fbde1c7d3c 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -76,4 +76,5 @@ CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 7dac1ec54eb..d6ebd080463 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -71,4 +71,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index d78c9f80599..872a4a55952 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -70,4 +70,5 @@ CONFIG_CADENCE_QSPI=y CONFIG_HAS_CQSPI_REF_CLK=y CONFIG_CQSPI_REF_CLK=200000000 CONFIG_CADENCE_OSPI_VERSAL=y +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index b0567f857a3..00319e06102 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -74,4 +74,5 @@ CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 40c6a29a16e..4207974dbdd 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -101,6 +101,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index c9b8a6de013..06c192ce9d0 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -102,6 +102,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index ba42f0c7848..8c6032532a2 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -158,6 +158,7 @@ CONFIG_DM_MTD=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ADIN=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_XILINX_GMII2RGMII=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 7fdd2eee555..4b45074efc4 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -60,4 +60,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index d2e920fc573..b4719536be1 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -60,4 +60,5 @@ CONFIG_SYS_NAND_MAX_CHIPS=2 CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 31f647357f7..7ede17654dd 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -59,4 +59,5 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 957ae07b80e..0d79ecece71 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -92,4 +92,5 @@ CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index ee87beb19c6..89187972fec 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -169,6 +169,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 48473d78443..750ea0db2b2 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -79,4 +79,5 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_ARM_DCC=y CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 9f2b738d9d1..3155fe0b378 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -83,4 +83,5 @@ CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_ARM_DCC=y CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 5b861bdde18..f2e1aa6d3ab 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -93,4 +93,5 @@ CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set # CONFIG_LMB is not set diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 9bc5283c268..6cca561f974 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -61,7 +61,6 @@ config DWC_AHCI config DWC_AHSATA bool "Enable DWC AHSATA driver support" select LIBATA - depends on BLK help Enable this driver to support the DWC AHSATA SATA controller found in i.MX5 and i.MX6 SoCs. diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 6ad18889f61..48529a6982f 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -1,8 +1,8 @@ config BLK bool # "Support block devices" depends on DM - default y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA - default y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK + def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA + def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK help Enable support for block devices, such as SCSI, MMC and USB flash sticks. These provide a block-level interface which permits diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 8af48e199a7..e979c431e33 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -242,20 +242,20 @@ static int get_gpmc_timing_reg(/* timing specifiers */ if (l) time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); - pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", - name, time_ns, time_ns_min, time_ns, l, - invalid ? "; invalid " : " "); + printf("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", + name, time_ns, time_ns_min, time_ns, l, + invalid ? "; invalid " : " "); } else { /* raw format */ - pr_info("gpmc,%s = <%u>;%s\n", name, l, - invalid ? " /* invalid */" : ""); + printf("gpmc,%s = <%u>;%s\n", name, l, + invalid ? " /* invalid */" : ""); } return l; } #define GPMC_PRINT_CONFIG(cs, config) \ - pr_info("CS%i %s: 0x%08x\n", cs, #config, \ + printf("CS%i %s: 0x%08x\n", cs, #config, \ gpmc_cs_read_reg(cs, config)) #define GPMC_GET_RAW(reg, st, end, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) @@ -274,7 +274,7 @@ static int get_gpmc_timing_reg(/* timing specifiers */ static void gpmc_show_regs(int cs, const char *desc) { - pr_info("gpmc cs%i %s:\n", cs, desc); + printf("gpmc cs%i %s:\n", cs, desc); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); @@ -291,7 +291,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) { gpmc_show_regs(cs, desc); - pr_info("gpmc cs%i access configuration:\n", cs); + printf("gpmc cs%i access configuration:\n", cs); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, @@ -318,7 +318,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); - pr_info("gpmc cs%i timings configuration:\n", cs); + printf("gpmc cs%i timings configuration:\n", cs); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); @@ -409,9 +409,9 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max l = gpmc_cs_read_reg(cs, reg); if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) { - pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", - cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, - (l >> st_bit) & mask, time); + printf("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", + cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, + (l >> st_bit) & mask, time); } l &= ~(mask << st_bit); @@ -618,8 +618,8 @@ static int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, return -ENXIO; if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) { - pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", - cs, (div * gpmc_get_fclk_period()) / 1000, div); + printf("GPMC CS%d CLK period is %lu ns (div %d)\n", + cs, (div * gpmc_get_fclk_period()) / 1000, div); } gpmc_cs_bool_timings(cs, &t->bool_timings); diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index d0944793c92..8b13a0821ee 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -41,7 +41,6 @@ config MMC_BROKEN_CD config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM - select BLK help This enables the MultiMediaCard (MMC) uclass which supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) @@ -249,7 +248,6 @@ config MMC_DW_CORTINA bool "Cortina specific extensions for Synopsys DW Memory Card Interface" depends on DM_MMC depends on MMC_DW - depends on BLK help This selects support for Cortina SoC specific extensions to the Synopsys DesignWare Memory Card Interface driver. Select this option @@ -313,7 +311,7 @@ config NEXELL_DWMMC config MMC_MESON_GX bool "Meson GX EMMC controller support" - depends on DM_MMC && BLK && ARCH_MESON + depends on DM_MMC && ARCH_MESON help Support for EMMC host controller on Meson GX ARM SoCs platform (S905) @@ -367,7 +365,7 @@ config MMC_OCTEONTX config MVEBU_MMC bool "Kirkwood MMC controller support" - depends on DM_MMC && BLK && ARCH_KIRKWOOD + depends on DM_MMC && ARCH_KIRKWOOD help Support for MMC host controller on Kirkwood SoCs. If you are on a Kirkwood architecture, say Y here. @@ -420,7 +418,7 @@ config SH_MMCIF config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL help This selects support for the Matsushita SD/MMC Host Controller on @@ -429,7 +427,7 @@ config MMC_UNIPHIER config RENESAS_SDHI bool "Renesas R-Car SD/MMC Host Controller support" depends on ARCH_RENESAS - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL select BOUNCE_BUFFER help @@ -439,7 +437,7 @@ config RENESAS_SDHI config MMC_BCM2835 bool "BCM2835 family custom SD/MMC Host Controller support" depends on ARCH_BCM283X - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL default y help @@ -459,7 +457,7 @@ config JZ47XX_MMC config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX - depends on BLK && DM_MMC && OF_CONTROL + depends on DM_MMC && OF_CONTROL help This select a dummy sandbox MMC driver. At present this does nothing other than allow sandbox to be build with MMC support. This @@ -561,7 +559,7 @@ config MMC_SDHCI_ASPEED config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 - depends on DM_MMC && BLK && ARCH_AT91 + depends on DM_MMC && ARCH_AT91 depends on MMC_SDHCI help This enables support for the Atmel SDHCI controller, which supports @@ -596,7 +594,7 @@ config MMC_SDHCI_BCMSTB config MMC_SDHCI_CADENCE bool "SDHCI support for the Cadence SD/SDIO/eMMC controller" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -608,7 +606,7 @@ config MMC_SDHCI_CADENCE config MMC_SDHCI_CV1800B bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -643,7 +641,7 @@ config MMC_SDHCI_IPROC config MMC_SDHCI_F_SDH30 bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI help This selects the Secure Digital Host Controller Interface (SDHCI) @@ -663,7 +661,7 @@ config MMC_SDHCI_KONA config MMC_SDHCI_MSM bool "Qualcomm SDHCI controller" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI help Enables support for SDHCI 2.0 controller present on some Qualcomm @@ -829,7 +827,7 @@ config MMC_PITON config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" - depends on DM_MMC && BLK && ARCH_AT91 + depends on DM_MMC && ARCH_AT91 help This enables support for Atmel High Speed Multimedia Card Interface (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, @@ -838,7 +836,7 @@ config GENERIC_ATMEL_MCI config STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" - depends on DM_MMC && BLK && OF_CONTROL + depends on DM_MMC && OF_CONTROL help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, @@ -858,7 +856,7 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" depends on ARCH_MEDIATEK || ARCH_MTMIPS - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 982dd251150..aea611fef52 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1804,11 +1804,62 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (ret < 0) return ret; #endif + write_enable(nor); - ret = nor->write(nor, addr, page_remain, buf + i); - if (ret < 0) - goto write_err; - written = ret; + + /* + * On DTR capable flashes like Micron Xcella the writes cannot + * start or end at an odd address in DTR mode. So we need to + * append or prepend extra 0xff bytes to make sure the start + * address and end address are even. + */ + if (spi_nor_protocol_is_dtr(nor->write_proto) && + ((addr | page_remain) & 1)) { + u_char *tmp; + size_t extra_bytes = 0; + + tmp = kmalloc(nor->page_size, 0); + if (!tmp) { + ret = -ENOMEM; + goto write_err; + } + + /* Prepend a 0xff byte if the start address is odd. */ + if (addr & 1) { + tmp[0] = 0xff; + memcpy(tmp + 1, buf + i, page_remain); + addr--; + page_remain++; + extra_bytes++; + } else { + memcpy(tmp, buf + i, page_remain); + } + + /* Append a 0xff byte if the end address is odd. */ + if ((addr + page_remain) & 1) { + tmp[page_remain + extra_bytes] = 0xff; + extra_bytes++; + page_remain++; + } + + ret = nor->write(nor, addr, page_remain, tmp); + + kfree(tmp); + + if (ret < 0) + goto write_err; + + /* + * We write extra bytes but they are not part of the + * original write. + */ + written = ret - extra_bytes; + } else { + ret = nor->write(nor, addr, page_remain, buf + i); + if (ret < 0) + goto write_err; + written = ret; + } ret = spi_nor_wait_till_ready(nor); if (ret) diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c index 4e1f8ed7a4a..a0264dc386d 100644 --- a/drivers/net/bcmgenet.c +++ b/drivers/net/bcmgenet.c @@ -360,6 +360,10 @@ static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, int length) { struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; + u32 addr = readl(desc_base + DMA_DESC_ADDRESS_LO); + + flush_dcache_range(addr, addr + RX_BUF_LENGTH); /* Tell the MAC we have consumed that last receive buffer. */ priv->c_index = (priv->c_index + 1) & 0xFFFF; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3d96938eaba..73064b2af68 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -23,6 +23,12 @@ config PHY_ADDR_ENABLE help Select this if you want to control which phy address is used +config PHY_ANEG_TIMEOUT + int "PHY auto-negotiation timeout" + default 4000 + help + Default PHY auto-negotiation timeout. + if PHY_ADDR_ENABLE config PHY_ADDR int "PHY address" diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 4517a6b13ba..d2db8d9f792 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -566,9 +566,9 @@ int aquantia_startup(struct phy_device *phydev) if ((i++ % 500) == 0) printf("."); } while (!aquantia_link_is_up(phydev) && - i < (4 * PHY_ANEG_TIMEOUT)); + i < (4 * CONFIG_PHY_ANEG_TIMEOUT)); - if (i > PHY_ANEG_TIMEOUT) + if (i > CONFIG_PHY_ANEG_TIMEOUT) printf(" TIMEOUT !\n"); } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index fbf85d90f54..716a1d46111 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -250,7 +250,7 @@ int genphy_update_link(struct phy_device *phydev) /* * Timeout reached ? */ - if (i > (PHY_ANEG_TIMEOUT / 50)) { + if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) { printf(" TIMEOUT !\n"); phydev->link = 0; return -ETIMEDOUT; diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index a1a39f61488..4d87e2d1f36 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -361,7 +361,7 @@ static int pcs_pma_startup(struct axidma_priv *priv) * and the external PHY is not obtained. */ debug("axiemac: waiting for link status of the PCS/PMA PHY"); - while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) { + while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) { rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg); if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) { debug(".Done\n"); diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 076b6f2acdb..e90f75a188c 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -21,6 +21,7 @@ #include <linux/sizes.h> #include <linux/soc/ti/ti_sci_protocol.h> #include "ti_sci_proc.h" +#include <mach/security.h> #define KEYSTONE_RPROC_LOCAL_ADDRESS_MASK (SZ_16M - 1) @@ -127,6 +128,7 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) struct k3_dsp_privdata *dsp = dev_get_priv(dev); struct k3_dsp_boot_data *data = dsp->data; u32 boot_vector; + void *image_addr = (void *)addr; int ret; if (dsp->in_use) { @@ -148,6 +150,8 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) goto proc_release; } + ti_secure_image_post_process(&image_addr, &size); + ret = rproc_elf_load_image(dev, addr, size); if (ret < 0) { dev_err(dev, "Loading elf failed %d\n", ret); diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 74bf0433e12..ef2c1872249 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -20,6 +20,7 @@ #include <linux/kernel.h> #include <linux/soc/ti/ti_sci_protocol.h> #include "ti_sci_proc.h" +#include <mach/security.h> /* * R5F's view of this address can either be for ATCM or BTCM with the other @@ -306,6 +307,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) u64 boot_vector; u32 ctrl, sts, cfg = 0; bool mem_auto_init; + void *image_addr = (void *)addr; int ret; dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size); @@ -333,6 +335,8 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) k3_r5f_init_tcm_memories(core, mem_auto_init); + ti_secure_image_post_process(&image_addr, &size); + ret = rproc_elf_load_image(dev, addr, size); if (ret < 0) { dev_err(dev, "Loading elf failedi %d\n", ret); diff --git a/examples/api/crt0.S b/examples/api/crt0.S index 57bba9d851d..06f6d1f9ad4 100644 --- a/examples/api/crt0.S +++ b/examples/api/crt0.S @@ -33,6 +33,21 @@ _start: str sp, [ip] b main +#elif defined(CONFIG_ARM64) + + .text + .globl _start +_start: + ldr ip0, =search_hint + str sp_el2, [ip0] + b main + + + .globl syscall +syscall: + ldr ip0, =syscall_ptr + ldr pc_el2, [ip0] + .globl syscall syscall: @@ -224,7 +224,7 @@ static struct fstype_info fstypes[] = { .exists = ext4fs_exists, .size = ext4fs_size, .read = ext4_read_file, -#ifdef CONFIG_CMD_EXT4_WRITE +#ifdef CONFIG_EXT4_WRITE .write = ext4_write_file, .ln = ext4fs_create_link, #else diff --git a/include/bcb.h b/include/bcb.h index 1941d8c28b4..a56b547595a 100644 --- a/include/bcb.h +++ b/include/bcb.h @@ -58,7 +58,8 @@ static inline int bcb_set(enum bcb_field field, const char *value) return -EOPNOTSUPP; } -static inline int bcb_get(enum bcb_field field, char *value_out) +static inline int bcb_get(enum bcb_field field, + char *value_out, size_t value_size) { return -EOPNOTSUPP; } diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 983428920fa..87ffa769d15 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -102,8 +102,6 @@ #endif -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ - /* NAND support */ #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 06edde69028..4b4362ccfd8 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -36,7 +36,6 @@ #include <configs/ti_omap5_common.h> /* CPSW Ethernet */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ /* * Default to using SPI for environment, etc. diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 0df3917e200..6fd43511ee4 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -22,7 +22,6 @@ #define CFG_SYS_FSL_USDHC_NUM 3 /* Network */ -#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ /* USB Configs */ /* Host */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 062d3d87026..7c7ada15bd9 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -26,8 +26,6 @@ * image and environment */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 0e922b96644..1ba63b22d59 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -15,8 +15,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* * Environment Configuration */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 54de2d0d833..cf00217a9ee 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -23,8 +23,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index c4ae397e3e6..b174b0db66a 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -12,8 +12,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 2cbe4eb440b..4ac1f3cffd9 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -15,8 +15,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 5c6d7fa1b77..67e62d6f34a 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -19,8 +19,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* NAND */ /* diff --git a/include/configs/ds116.h b/include/configs/ds116.h index 0883ec4d53b..c2326596811 100644 --- a/include/configs/ds116.h +++ b/include/configs/ds116.h @@ -7,8 +7,6 @@ #ifndef _CONFIG_DS116_H #define _CONFIG_DS116_H -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 9446acba792..f1921dac5e7 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -55,6 +55,5 @@ /* increase autoneg timeout, my NIC sucks */ -#define PHY_ANEG_TIMEOUT 16000 #endif /* _CONFIG_SYNOLOGY_DS414_H */ diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 7d81d1cf1e4..a3b6335a541 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -26,8 +26,6 @@ * image and environment */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h index 27404c80fdf..950ec8b190d 100644 --- a/include/configs/hmibsc.h +++ b/include/configs/hmibsc.h @@ -9,7 +9,6 @@ #define __CONFIGS_HMIBSC_H /* PHY needs a longer aneg time */ -#define PHY_ANEG_TIMEOUT 8000 #define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index 5cc60af91e5..7058d632d67 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -9,7 +9,6 @@ #include <configs/verdin-imx8mm.h> /* PHY needs a longer autoneg timeout */ -#define PHY_ANEG_TIMEOUT 20000 /* Custom initial environment variables */ #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index b777fe6073b..9a5e5bd009d 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -28,7 +28,6 @@ #define CFG_MXC_UART_BASE UART3_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ -#define PHY_ANEG_TIMEOUT 20000 /* USDHC */ #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8mp_beacon.h b/include/configs/imx8mp_beacon.h index ee0fd07e650..b36dae7c34f 100644 --- a/include/configs/imx8mp_beacon.h +++ b/include/configs/imx8mp_beacon.h @@ -10,10 +10,6 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#if defined(CONFIG_CMD_NET) -#define PHY_ANEG_TIMEOUT 20000 -#endif - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index 8d7954004c2..f953847ce05 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -21,7 +21,6 @@ #define CFG_MXC_UART_BASE UART3_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ -#define PHY_ANEG_TIMEOUT 20000 #define FEC_QUIRK_ENET_MAC #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mp_debix_model_a.h b/include/configs/imx8mp_debix_model_a.h index e82e8b16b1d..14b91100947 100644 --- a/include/configs/imx8mp_debix_model_a.h +++ b/include/configs/imx8mp_debix_model_a.h @@ -16,8 +16,6 @@ #if defined(CONFIG_CMD_NET) #define CFG_FEC_MXC_PHYADDR 1 -#define PHY_ANEG_TIMEOUT 20000 - #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index ea32fe11a52..c848fce8bda 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -21,7 +21,6 @@ #define CFG_MXC_UART_BASE UART1_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ -#define PHY_ANEG_TIMEOUT 20000 #define FEC_QUIRK_ENET_MAC /* USDHC */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1759318fdd3..71452aa2833 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -15,8 +15,6 @@ #if defined(CONFIG_CMD_NET) #define CFG_FEC_MXC_PHYADDR 1 -#define PHY_ANEG_TIMEOUT 20000 - #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index bbbd91776fe..0a861a107b2 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -18,8 +18,6 @@ #define DWC_NET_PHYADDR 1 -#define PHY_ANEG_TIMEOUT 20000 - #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index e577f60ae72..10a166d781e 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -35,8 +35,6 @@ #if defined(CONFIG_CMD_NET) #define CFG_FEC_MXC_PHYADDR 4 -#define PHY_ANEG_TIMEOUT 20000 - #endif #if IS_ENABLED(CONFIG_CMD_MMC) diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index d77510e1685..750aef1b597 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -19,8 +19,6 @@ /* ENET Config */ #if defined(CONFIG_FEC_MXC) -#define PHY_ANEG_TIMEOUT 20000 - #define CFG_FEC_MXC_PHYADDR 1 #endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 2705587a015..ce6567e2af6 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -134,8 +134,4 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR -#if defined(CONFIG_CMD_NET) -#define PHY_ANEG_TIMEOUT 20000 -#endif - #endif diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h index 18a8ee5deed..9dc10aea407 100644 --- a/include/configs/imx93_var_som.h +++ b/include/configs/imx93_var_som.h @@ -41,8 +41,4 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR -#if defined(CONFIG_CMD_NET) -#define PHY_ANEG_TIMEOUT 20000 -#endif - #endif diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 2f25d393a37..ce7bd6652bb 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -11,7 +11,6 @@ /* Network */ #define CFG_KSNET_CPSW_NUM_PORTS 2 -#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ #include <configs/ti_armv7_keystone2.h> diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 5cf6b5a6dd4..101c59141f7 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -26,8 +26,6 @@ #if defined(CONFIG_CMD_NET) #define CFG_FEC_MXC_PHYADDR 0 -#define PHY_ANEG_TIMEOUT 20000 - #endif #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h index c5b78f9c896..0d29e1ddc73 100644 --- a/include/configs/lion_rk3368.h +++ b/include/configs/lion_rk3368.h @@ -12,6 +12,5 @@ #define DTB_LOAD_ADDR 0x5600000 #define INITRD_LOAD_ADDR 0x5bf0000 /* PHY needs longer aneg time at 1G */ -#define PHY_ANEG_TIMEOUT 8000 #endif diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 413597e09b2..4c2b538f888 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -25,8 +25,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index 3c7d96cb3c0..1325859b039 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -18,7 +18,6 @@ #if defined(CONFIG_CMD_NET) #define CFG_FEC_MXC_PHYADDR 1 -#define PHY_ANEG_TIMEOUT 20000 #endif #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/n2350.h b/include/configs/n2350.h index d8a9814d3e8..f98b9f8582d 100644 --- a/include/configs/n2350.h +++ b/include/configs/n2350.h @@ -7,8 +7,6 @@ #ifndef _CONFIG_N2350_H #define _CONFIG_N2350_H -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h index 5479bdedee5..7d99fd1b019 100644 --- a/include/configs/octeon_ebb7304.h +++ b/include/configs/octeon_ebb7304.h @@ -9,6 +9,4 @@ #include "octeon_common.h" -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - #endif /* __CONFIG_H__ */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 5f4d5ced78f..3f0831a901c 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -20,11 +20,7 @@ /* console */ #define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } -/* PHY needs a longer autoneg timeout */ -#define PHY_ANEG_TIMEOUT 20000 - /* MEMORY */ - #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h index 3465b4d1821..37a37c013df 100644 --- a/include/configs/rcar-gen4-common.h +++ b/include/configs/rcar-gen4-common.h @@ -21,7 +21,6 @@ #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) /* PHY needs a longer autoneg timeout */ -#define PHY_ANEG_TIMEOUT 20000 /* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index caff0cf2523..aa33cf48140 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -12,7 +12,6 @@ /* Ethernet on SoC (EMAC) */ /* The PHY is autodetected, so no MII PHY address is needed here */ -#define PHY_ANEG_TIMEOUT 8000 /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index de39b19219d..c1fca8359d2 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -9,7 +9,6 @@ #define __CONFIG_STM32MP15_DH_DHSOM_H__ /* PHY needs a longer autoneg timeout */ -#define PHY_ANEG_TIMEOUT 20000 #ifdef CONFIG_SPL_BUILD #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 2ce92845f1c..40432c9d6b2 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -32,8 +32,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 47b220ff9ee..302194bc90f 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -19,8 +19,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/x530.h b/include/configs/x530.h index e1678e79e49..982b1292873 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -40,8 +40,6 @@ /* Environment in SPI NOR flash */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - /* NAND */ #include <asm/arch/config.h> diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index b634bb1ab70..dc3f41b94a2 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -28,9 +28,6 @@ #endif /* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM) -# define PHY_ANEG_TIMEOUT 20000 -#endif #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 9cb6b2bfea3..2a03f4c0c22 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -42,9 +42,6 @@ #endif /* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM) -# define PHY_ANEG_TIMEOUT 20000 -#endif #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 5bc117e1900..f76b3c6b163 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -45,9 +45,6 @@ /* Console I/O Buffer Size */ /* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM) -# define PHY_ANEG_TIMEOUT 20000 -#endif #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ diff --git a/include/dm/devres.h b/include/dm/devres.h index 697534aa5be..27761deb6d1 100644 --- a/include/dm/devres.h +++ b/include/dm/devres.h @@ -266,17 +266,13 @@ static inline void *devm_kzalloc(struct udevice *dev, size_t size, gfp_t gfp) static inline void *devm_kmalloc_array(struct udevice *dev, size_t n, size_t size, gfp_t flags) { - /* TODO: add kmalloc_array() to linux/compat.h */ - if (size != 0 && n > SIZE_MAX / size) - return NULL; - return kmalloc(n * size, flags); + return kmalloc_array(n, size, flags); } static inline void *devm_kcalloc(struct udevice *dev, size_t n, size_t size, gfp_t flags) { - /* TODO: add kcalloc() to linux/compat.h */ - return kmalloc(n * size, flags | __GFP_ZERO); + return kcalloc(n, size, flags); } static inline void devm_kfree(struct udevice *dev, void *ptr) diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h index 730d963ab96..b1d62205958 100644 --- a/include/eeprom_layout.h +++ b/include/eeprom_layout.h @@ -9,6 +9,8 @@ #ifndef _LAYOUT_ #define _LAYOUT_ +#include <eeprom_field.h> + #define RESERVED_FIELDS NULL #define LAYOUT_VERSION_UNRECOGNIZED -1 #define LAYOUT_VERSION_AUTODETECT -2 @@ -24,6 +26,8 @@ struct eeprom_layout { char *new_data); }; +struct eeprom_field *eeprom_layout_find_field(struct eeprom_layout *layout, + char *field_name, bool warn); void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, unsigned int buf_size, int layout_version); __weak void __eeprom_layout_assign(struct eeprom_layout *layout, diff --git a/include/efi_load_initrd.h b/include/efi_load_initrd.h index be5d5a7acbe..9feafb18c86 100644 --- a/include/efi_load_initrd.h +++ b/include/efi_load_initrd.h @@ -18,7 +18,17 @@ 0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68) extern const efi_guid_t efi_lf2_initrd_guid; -struct efi_initrd_dp { +/** + * struct efi_lo_dp_prefix - separator device path used in load options + * + * We use vendor media device nodes in UEFI load options to separate + * the binary, initrd, and fdt device-paths. This structure contains + * the vendor media device node and an end node. + * + * @vendor: vendor media device node + * @end: end node + */ +struct efi_lo_dp_prefix { struct efi_device_path_vendor vendor; struct efi_device_path end; } __packed; diff --git a/include/efi_loader.h b/include/efi_loader.h index 9600941aa32..6c993e1a694 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -664,6 +664,10 @@ efi_status_t EFIAPI efi_load_image(bool boot_policy, void *source_buffer, efi_uintn_t source_size, efi_handle_t *image_handle); +/* Load image from path */ +efi_status_t efi_load_image_from_path(bool boot_policy, + struct efi_device_path *file_path, + void **buffer, efi_uintn_t *size); /* Start image */ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, efi_uintn_t *exit_data_size, @@ -946,7 +950,7 @@ struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo, const efi_guid_t *guid); struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, const struct efi_device_path *dp2, - bool split_end_node); + size_t split_end_node); struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path); efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data, efi_uintn_t *size); @@ -1185,4 +1189,22 @@ efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int */ void efi_add_known_memory(void); +/** + * efi_load_option_dp_join() - join device-paths for load option + * + * @dp: in: binary device-path, out: joined device-path + * @dp_size: size of joined device-path + * @initrd_dp: initrd device-path or NULL + * @fdt_dp: device-tree device-path or NULL + * Return: status_code + */ +efi_status_t efi_load_option_dp_join(struct efi_device_path **dp, + size_t *dp_size, + struct efi_device_path *initrd_dp, + struct efi_device_path *fdt_dp); + +int efi_get_distro_fdt_name(char *fname, int size, int seq); + +void efi_load_distro_fdt(void **fdt, efi_uintn_t *fdt_size); + #endif /* _EFI_LOADER_H */ diff --git a/include/env/ti/k3_dfu.env b/include/env/ti/k3_dfu.env index 201529636cc..b42cf21d986 100644 --- a/include/env/ti/k3_dfu.env +++ b/include/env/ti/k3_dfu.env @@ -9,7 +9,7 @@ dfu_alt_info_mmc= dfu_alt_info_emmc= rawemmc raw 0 0x800000 mmcpart 1; - rootfs part 0 1 mmcpart 0; + rootfs part 0 1; tiboot3.bin.raw raw 0x0 0x400 mmcpart 1; tispl.bin.raw raw 0x400 0x1000 mmcpart 1; u-boot.img.raw raw 0x1400 0x2000 mmcpart 1; diff --git a/include/env/ti/k3_rproc.env b/include/env/ti/k3_rproc.env index 87d9d76eba4..d4f0f1708ca 100644 --- a/include/env/ti/k3_rproc.env +++ b/include/env/ti/k3_rproc.env @@ -13,11 +13,15 @@ rproc_load_and_boot_one= boot_rprocs_mmc= env set rproc_id; env set rproc_fw; + env set secure_suffix; + if test ${secure_rprocs} -eq 1; then + env set secure_suffix -sec; + fi; for i in ${rproc_fw_binaries} ; do if test -z "${rproc_id}" ; then env set rproc_id $i; else - env set rproc_fw $i; + env set rproc_fw $i${secure_suffix}; run rproc_load_and_boot_one; env set rproc_id; env set rproc_fw; diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index 02b410c3adc..c5c36421770 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -12,6 +12,7 @@ bootm_size=0x10000000 boot_fdt=try boot_fit=0 +secure_rprocs=0 addr_fit=0x90000000 name_fit=fitImage update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit} diff --git a/include/extension_board.h b/include/extension_board.h index 87d404c0074..22e4104bc54 100644 --- a/include/extension_board.h +++ b/include/extension_board.h @@ -14,7 +14,7 @@ struct extension { char name[32]; char owner[32]; char version[32]; - char overlay[32]; + char overlay[64]; char other[32]; }; diff --git a/include/image.h b/include/image.h index acffd17e0df..c5b288f62b4 100644 --- a/include/image.h +++ b/include/image.h @@ -1971,6 +1971,13 @@ bool is_android_vendor_boot_image_header(const void *vendor_boot_img); ulong get_abootimg_addr(void); /** + * get_ainit_bootimg_addr() - Get Android init boot image address + * + * Return: Android init boot image address + */ +ulong get_ainit_bootimg_addr(void); + +/** * get_avendor_bootimg_addr() - Get Android vendor boot image address * * Return: Android vendor boot image address diff --git a/include/phy.h b/include/phy.h index 90b7e364101..36785031eeb 100644 --- a/include/phy.h +++ b/include/phy.h @@ -58,11 +58,6 @@ struct udevice; #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ SUPPORTED_10000baseT_Full) -#ifndef PHY_ANEG_TIMEOUT -#define PHY_ANEG_TIMEOUT 4000 -#endif - - struct phy_device; #define MDIO_NAME_LEN 32 diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 430bb7f0f7d..ee71f417147 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -10,9 +10,9 @@ config EFI_LOADER depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT - depends on BLK depends on !EFI_APP default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8 + select BLK select CHARSET # We need to send DM events, dynamically, in the EFI block driver select DM_EVENT diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 034e366967f..2af6f2066b5 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -59,6 +59,7 @@ obj-y += efi_device_path.o obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o obj-y += efi_dt_fixup.o +obj-y += efi_fdt.o obj-y += efi_file.o obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o obj-y += efi_image_loader.o diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c index b7910f78fb6..a87006b3c0e 100644 --- a/lib/efi_loader/efi_bootbin.c +++ b/lib/efi_loader/efi_bootbin.c @@ -150,7 +150,7 @@ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) msg_path = file_path; } else { file_path = efi_dp_concat(bootefi_device_path, - bootefi_image_path, false); + bootefi_image_path, 0); msg_path = bootefi_image_path; log_debug("Loaded from disk\n"); } diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 7da3139f917..304ed43595c 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -130,7 +130,7 @@ static efi_status_t try_load_from_file_path(efi_handle_t *fs_handles, if (!dp) continue; - dp = efi_dp_concat(dp, fp, false); + dp = efi_dp_concat(dp, fp, 0); if (!dp) continue; @@ -1186,6 +1186,59 @@ out: } /** + * load_fdt_from_load_option - load device-tree from load option + * + * @fdt: pointer to loaded device-tree or NULL + * Return: status code + */ +static efi_status_t load_fdt_from_load_option(void **fdt) +{ + struct efi_device_path *dp = NULL; + struct efi_file_handle *f = NULL; + efi_uintn_t filesize; + efi_status_t ret; + + *fdt = NULL; + + dp = efi_get_dp_from_boot(&efi_guid_fdt); + if (!dp) + return EFI_SUCCESS; + + /* Open file */ + f = efi_file_from_path(dp); + if (!f) { + log_err("Can't find %pD specified in Boot####\n", dp); + ret = EFI_NOT_FOUND; + goto out; + } + + /* Get file size */ + ret = efi_file_size(f, &filesize); + if (ret != EFI_SUCCESS) + goto out; + + *fdt = calloc(1, filesize); + if (!*fdt) { + log_err("Out of memory\n"); + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + ret = EFI_CALL(f->read(f, &filesize, *fdt)); + if (ret != EFI_SUCCESS) { + log_err("Can't read fdt\n"); + free(*fdt); + *fdt = NULL; + } + +out: + efi_free_pool(dp); + if (f) + EFI_CALL(f->close(f)); + + return ret; +} + +/** * efi_bootmgr_run() - execute EFI boot manager * @fdt: Flat device tree * @@ -1200,6 +1253,8 @@ efi_status_t efi_bootmgr_run(void *fdt) efi_handle_t handle; void *load_options; efi_status_t ret; + void *fdt_lo, *fdt_distro = NULL; + efi_uintn_t fdt_size; /* Initialize EFI drivers */ ret = efi_init_obj_list(); @@ -1215,7 +1270,31 @@ efi_status_t efi_bootmgr_run(void *fdt) return ret; } + if (!IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { + ret = load_fdt_from_load_option(&fdt_lo); + if (ret != EFI_SUCCESS) + return ret; + if (fdt_lo) + fdt = fdt_lo; + if (!fdt) { + efi_load_distro_fdt(&fdt_distro, &fdt_size); + fdt = fdt_distro; + } + } + + /* + * Needed in ACPI case to create reservations based on + * control device-tree. + */ ret = efi_install_fdt(fdt); + + if (!IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { + free(fdt_lo); + if (fdt_distro) + efi_free_pages((uintptr_t)fdt_distro, + efi_size_in_pages(fdt_size)); + } + if (ret != EFI_SUCCESS) { if (EFI_CALL(efi_unload_image(handle)) == EFI_SUCCESS) free(load_options); diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 1951291747c..eedc5f39549 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -1816,7 +1816,7 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, if (device_path) { info->device_handle = efi_dp_find_obj(device_path, NULL, NULL); - dp = efi_dp_concat(device_path, file_path, false); + dp = efi_dp_concat(device_path, file_path, 0); if (!dp) { ret = EFI_OUT_OF_RESOURCES; goto failure; @@ -1996,7 +1996,6 @@ error: * @size: size of the loaded image * Return: status code */ -static efi_status_t efi_load_image_from_path(bool boot_policy, struct efi_device_path *file_path, void **buffer, efi_uintn_t *size) diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index aec224d8466..0f684590f22 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -276,10 +276,11 @@ struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp) * * @dp1: First device path * @dp2: Second device path - * @split_end_node: If true the two device paths will be concatenated and - * separated by an end node (DEVICE_PATH_SUB_TYPE_END). - * If false the second device path will be concatenated to the - * first one as-is. + * @split_end_node: + * * 0 to concatenate + * * 1 to concatenate with end node added as separator + * * size of dp1 excluding last end node to concatenate with end node as + * separator in case dp1 contains an end node * * Return: * concatenated device path or NULL. Caller must free the returned value @@ -287,7 +288,7 @@ struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp) struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, const struct efi_device_path *dp2, - bool split_end_node) + size_t split_end_node) { struct efi_device_path *ret; size_t end_size; @@ -301,10 +302,15 @@ efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, ret = efi_dp_dup(dp1); } else { /* both dp1 and dp2 are non-null */ - unsigned sz1 = efi_dp_size(dp1); - unsigned sz2 = efi_dp_size(dp2); + size_t sz1; + size_t sz2 = efi_dp_size(dp2); void *p; + if (split_end_node < sizeof(struct efi_device_path)) + sz1 = efi_dp_size(dp1); + else + sz1 = split_end_node; + if (split_end_node) end_size = 2 * sizeof(END); else @@ -1127,17 +1133,18 @@ ssize_t efi_dp_check_length(const struct efi_device_path *dp, } /** - * efi_dp_from_lo() - Get the instance of a VenMedia node in a - * multi-instance device path that matches - * a specific GUID. This kind of device paths - * is found in Boot#### options describing an - * initrd location + * efi_dp_from_lo() - get device-path from load option * - * @lo: EFI_LOAD_OPTION containing a valid device path - * @guid: guid to search for + * The load options in U-Boot may contain multiple concatenated device-paths. + * The first device-path indicates the EFI binary to execute. Subsequent + * device-paths start with a VenMedia node where the GUID identifies the + * function (initrd or fdt). + * + * @lo: EFI load option containing a valid device path + * @guid: GUID identifying device-path or NULL for the EFI binary * * Return: - * device path including the VenMedia node or NULL. + * device path excluding the matched VenMedia node or NULL. * Caller must free the returned value. */ struct @@ -1148,6 +1155,9 @@ efi_device_path *efi_dp_from_lo(struct efi_load_option *lo, struct efi_device_path_vendor *vendor; int lo_len = lo->file_path_length; + if (!guid) + return efi_dp_dup(fp); + for (; lo_len >= sizeof(struct efi_device_path); lo_len -= fp->length, fp = (void *)fp + fp->length) { if (lo_len < 0 || efi_dp_check_length(fp, lo_len) < 0) diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c index c95dbfa9b5f..ac250bbfcc9 100644 --- a/lib/efi_loader/efi_device_path_utilities.c +++ b/lib/efi_loader/efi_device_path_utilities.c @@ -76,7 +76,7 @@ static struct efi_device_path * EFIAPI append_device_path( const struct efi_device_path *src2) { EFI_ENTRY("%pD, %pD", src1, src2); - return EFI_EXIT(efi_dp_concat(src1, src2, false)); + return EFI_EXIT(efi_dp_concat(src1, src2, 0)); } /* diff --git a/lib/efi_loader/efi_fdt.c b/lib/efi_loader/efi_fdt.c new file mode 100644 index 00000000000..86ba00c2bdd --- /dev/null +++ b/lib/efi_loader/efi_fdt.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Bootmethod for distro boot via EFI + * + * Copyright 2021 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <efi_loader.h> +#include <env.h> +#include <errno.h> +#include <log.h> +#include <string.h> +#include <vsprintf.h> + +/** + * distro_efi_get_fdt_name() - get the filename for reading the .dtb file + * + * @fname: buffer for filename + * @size: buffer size + * @seq: sequence number, to cycle through options (0=first) + * + * Returns: + * 0 on success, + * -ENOENT if the "fdtfile" env var does not exist, + * -EINVAL if there are no more options, + * -EALREADY if the control FDT should be used + */ +int efi_get_distro_fdt_name(char *fname, int size, int seq) +{ + const char *fdt_fname; + const char *prefix; + + /* select the prefix */ + switch (seq) { + case 0: + /* this is the default */ + prefix = "/dtb"; + break; + case 1: + prefix = ""; + break; + case 2: + prefix = "/dtb/current"; + break; + default: + return log_msg_ret("pref", -EINVAL); + } + + fdt_fname = env_get("fdtfile"); + if (fdt_fname) { + snprintf(fname, size, "%s/%s", prefix, fdt_fname); + log_debug("Using device tree: %s\n", fname); + } else if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE)) { + strcpy(fname, "<prior>"); + return log_msg_ret("pref", -EALREADY); + /* Use this fallback only for 32-bit ARM */ + } else if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64)) { + const char *soc = env_get("soc"); + const char *board = env_get("board"); + const char *boardver = env_get("boardver"); + + /* cf the code in label_boot() which seems very complex */ + snprintf(fname, size, "%s/%s%s%s%s.dtb", prefix, + soc ? soc : "", soc ? "-" : "", board ? board : "", + boardver ? boardver : ""); + log_debug("Using default device tree: %s\n", fname); + } else { + return log_msg_ret("env", -ENOENT); + } + + return 0; +} + +/** + * efi_load_distro_fdt() - load distro device-tree + * + * @fdt: on return device-tree, must be freed via efi_free_pages() + * @fdt_size: buffer size + */ +void efi_load_distro_fdt(void **fdt, efi_uintn_t *fdt_size) +{ + struct efi_device_path *rem, *dp; + efi_status_t ret; + efi_handle_t device; + + *fdt = NULL; + + dp = efi_get_dp_from_boot(NULL); + if (!dp) + return; + device = efi_dp_find_obj(dp, NULL, &rem); + ret = efi_search_protocol(device, &efi_simple_file_system_protocol_guid, + NULL); + if (ret != EFI_SUCCESS) + goto err; + memcpy(rem, &END, sizeof(END)); + + /* try the various available names */ + for (int seq = 0; ; ++seq) { + struct efi_device_path *file; + char buf[255]; + + if (efi_get_distro_fdt_name(buf, sizeof(buf), seq)) + break; + file = efi_dp_from_file(dp, buf); + if (!file) + break; + ret = efi_load_image_from_path(true, file, fdt, fdt_size); + efi_free_pool(file); + if (ret == EFI_SUCCESS) + break; + } + +err: + efi_free_pool(dp); +} diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index 73d0279e843..348612c3dad 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -99,6 +99,50 @@ err: return NULL; } +/** + * efi_load_option_dp_join() - join device-paths for load option + * + * @dp: in: binary device-path, out: joined device-path + * @dp_size: size of joined device-path + * @initrd_dp: initrd device-path or NULL + * @fdt_dp: device-tree device-path or NULL + * Return: status_code + */ +efi_status_t efi_load_option_dp_join(struct efi_device_path **dp, + size_t *dp_size, + struct efi_device_path *initrd_dp, + struct efi_device_path *fdt_dp) +{ + if (!dp) + return EFI_INVALID_PARAMETER; + + *dp_size = efi_dp_size(*dp); + + if (initrd_dp) { + struct efi_device_path *tmp_dp = *dp; + + *dp = efi_dp_concat(tmp_dp, initrd_dp, *dp_size); + efi_free_pool(tmp_dp); + if (!*dp) + return EFI_OUT_OF_RESOURCES; + *dp_size += efi_dp_size(initrd_dp) + sizeof(END); + } + + if (fdt_dp) { + struct efi_device_path *tmp_dp = *dp; + + *dp = efi_dp_concat(tmp_dp, fdt_dp, *dp_size); + efi_free_pool(tmp_dp); + if (!dp) + return EFI_OUT_OF_RESOURCES; + *dp_size += efi_dp_size(fdt_dp) + sizeof(END); + } + + *dp_size += sizeof(END); + + return EFI_SUCCESS; +} + const struct guid_to_hash_map { efi_guid_t guid; const char algo[32]; diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c index d91135436c4..23508431c83 100644 --- a/lib/efi_loader/efi_load_initrd.c +++ b/lib/efi_loader/efi_load_initrd.c @@ -24,7 +24,7 @@ static const struct efi_load_file_protocol efi_lf2_protocol = { * Device path defined by Linux to identify the handle providing the * EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk. */ -static const struct efi_initrd_dp dp_lf2_handle = { +static const struct efi_lo_dp_prefix dp_lf2_handle = { .vendor = { { DEVICE_PATH_TYPE_MEDIA_DEVICE, diff --git a/lib/efi_loader/initrddump.c b/lib/efi_loader/initrddump.c index 0004b6b042b..615119043d1 100644 --- a/lib/efi_loader/initrddump.c +++ b/lib/efi_loader/initrddump.c @@ -33,7 +33,7 @@ static bool nocolor; * Device path defined by Linux to identify the handle providing the * EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk. */ -static const struct efi_initrd_dp initrd_dp = { +static const struct efi_lo_dp_prefix initrd_dp = { .vendor = { { DEVICE_PATH_TYPE_MEDIA_DEVICE, diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py new file mode 100644 index 00000000000..4729ccf07fe --- /dev/null +++ b/test/py/tests/test_net_boot.py @@ -0,0 +1,403 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +import pytest +import u_boot_utils +import test_net +import re + +""" +Note: This test relies on boardenv_* containing configuration values to define +which the network environment available for testing. Without this, this test +will be automatically skipped. + +For example: + +# Details regarding a boot image file that may be read from a TFTP server. This +# variable may be omitted or set to None if TFTP boot testing is not possible +# or desired. +env__net_tftp_bootable_file = { + 'fn': 'image.ub', + 'addr': 0x10000000, + 'size': 5058624, + 'crc32': 'c2244b26', + 'pattern': 'Linux', + 'config': 'config@2', + 'timeout': 50000, + 'check_type': 'boot_error', + 'check_pattern': 'ERROR', +} + +# False or omitted if a TFTP boot test should be tested. +# If TFTP boot testing is not possible or desired, set this variable to True. +# For example: If FIT image is not proper to boot +env__tftp_boot_test_skip = False + +# Here is the example of FIT image configurations: +configurations { + default = "config@1"; + config@1 { + description = "Boot Linux kernel with config@1"; + kernel = "kernel@0"; + fdt = "fdt@0"; + ramdisk = "ramdisk@0"; + hash@1 { + algo = "sha1"; + }; + }; + config@2 { + description = "Boot Linux kernel with config@2"; + kernel = "kernel@1"; + fdt = "fdt@1"; + ramdisk = "ramdisk@1"; + hash@1 { + algo = "sha1"; + }; + }; +}; + +# Details regarding a file that may be read from a TFTP server. This variable +# may be omitted or set to None if PXE testing is not possible or desired. +env__net_pxe_bootable_file = { + 'fn': 'default', + 'addr': 0x10000000, + 'size': 74, + 'timeout': 50000, + 'pattern': 'Linux', + 'valid_label': '1', + 'invalid_label': '2', + 'exp_str_invalid': 'Skipping install for failure retrieving', + 'local_label': '3', + 'exp_str_local': 'missing environment variable: localcmd', + 'empty_label': '4', + 'exp_str_empty': 'No kernel given, skipping boot', + 'check_type': 'boot_error', + 'check_pattern': 'ERROR', +} + +# False or omitted if a PXE boot test should be tested. +# If PXE boot testing is not possible or desired, set this variable to True. +# For example: If pxe configuration file is not proper to boot +env__pxe_boot_test_skip = False + +# Here is the example of pxe configuration file ordered based on the execution +# flow: +1) /tftpboot/pxelinux.cfg/default-arm-zynqmp + + menu include pxelinux.cfg/default-arm + timeout 50 + + default Linux + +2) /tftpboot/pxelinux.cfg/default-arm + + menu title Linux boot selections + menu include pxelinux.cfg/default + + label install + menu label Invalid boot + kernel kernels/install.bin + append console=ttyAMA0,38400 debug earlyprintk + initrd initrds/uzInitrdDebInstall + + label local + menu label Local boot + append root=/dev/sdb1 + localboot 1 + + label boot + menu label Empty boot + +3) /tftpboot/pxelinux.cfg/default + + label Linux + menu label Boot kernel + kernel Image + fdt system.dtb + initrd rootfs.cpio.gz.u-boot +""" + +def setup_networking(u_boot_console): + test_net.test_net_dhcp(u_boot_console) + if not test_net.net_set_up: + test_net.test_net_setup_static(u_boot_console) + +def setup_tftpboot_boot(u_boot_console): + f = u_boot_console.config.env.get('env__net_tftp_bootable_file', None) + if not f: + pytest.skip('No TFTP bootable file to read') + + setup_networking(u_boot_console) + addr = f.get('addr', None) + if not addr: + addr = u_boot_utils.find_ram_base(u_boot_console) + + fn = f['fn'] + timeout = f.get('timeout', 50000) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert expected_text in output + + expected_crc = f.get('crc32', None) + output = u_boot_console.run_command('crc32 %x $filesize' % addr) + if expected_crc: + assert expected_crc in output + + pattern = f.get('pattern') + chk_type = f.get('check_type', 'boot_error') + chk_pattern = re.compile(f.get('check_pattern', 'ERROR')) + config = f.get('config', None) + + return addr, timeout, pattern, chk_type, chk_pattern, config + +@pytest.mark.buildconfigspec('cmd_net') +def test_net_tftpboot_boot(u_boot_console): + """Boot the loaded image + + A boot file (fit image) is downloaded from the TFTP server and booted using + bootm command with the default fit configuration, its boot log pattern are + validated. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__tftp_boot_test_skip', True): + pytest.skip('TFTP boot test is not enabled!') + + addr, timeout, pattern, chk_type, chk_pattern, imcfg = setup_tftpboot_boot( + u_boot_console + ) + + if imcfg: + bootcmd = 'bootm %x#%s' % (addr, imcfg) + else: + bootcmd = 'bootm %x' % addr + + with u_boot_console.enable_check( + chk_type, chk_pattern + ), u_boot_console.temporary_timeout(timeout): + try: + # wait_for_prompt=False makes the core code not wait for the U-Boot + # prompt code to be seen, since it won't be on a successful kernel + # boot + u_boot_console.run_command(bootcmd, wait_for_prompt=False) + + # Wait for boot log pattern + u_boot_console.wait_for(pattern) + finally: + # This forces the console object to be shutdown, so any subsequent + # test will reset the board back into U-Boot. We want to force this + # no matter whether the kernel boot passed or failed. + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +def setup_pxe_boot(u_boot_console): + f = u_boot_console.config.env.get('env__net_pxe_bootable_file', None) + if not f: + pytest.skip('No PXE bootable file to read') + + setup_networking(u_boot_console) + bootfile = u_boot_console.run_command('echo $bootfile') + if not bootfile: + bootfile = '<NULL>' + + return f, bootfile + +@pytest.mark.buildconfigspec('cmd_net') +@pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot(u_boot_console): + """Test the pxe boot command. + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f, bootfile = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + + if addr: + u_boot_console.run_command('setenv pxefile_addr_r %x' % addr) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert f"Config file '{bootfile}' found" in output + + pattern = f.get('pattern') + chk_type = f.get('check_type', 'boot_error') + chk_pattern = re.compile(f.get('check_pattern', 'ERROR')) + + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.enable_check( + chk_type, chk_pattern + ), u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +@pytest.mark.buildconfigspec('cmd_net') +@pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot_config(u_boot_console): + """Test the pxe boot command by selecting different combination of labels + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f, bootfile = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + local_label = f['local_label'] + empty_label = f['empty_label'] + exp_str_local = f['exp_str_local'] + exp_str_empty = f['exp_str_empty'] + + if addr: + u_boot_console.run_command('setenv pxefile_addr_r %x' % addr) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert f"Config file '{bootfile}' found" in output + + pattern = f.get('pattern') + chk_type = f.get('check_type', 'boot_error') + chk_pattern = re.compile(f.get('check_pattern', 'ERROR')) + + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.enable_check( + chk_type, chk_pattern + ), u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + + # pxe config is loaded where multiple labels are there and need to + # select particular label to boot and check for expected string + # In this case, local label is selected and it should look for + # localcmd env variable and if that variable is not defined it + # should not boot it and come out to u-boot prompt + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(local_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_local]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_local} did not match!' + + # In this case, empty label is selected and it should look for + # kernel image path and if it is not set it should fail it and load + # default label to boot + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(empty_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_empty]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_empty} did not match!' + + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +@pytest.mark.buildconfigspec('cmd_net') +@pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot_config_invalid(u_boot_console): + """Test the pxe boot command by selecting invalid label + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f, bootfile = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + invalid_label = f['invalid_label'] + exp_str_invalid = f['exp_str_invalid'] + + if addr: + u_boot_console.run_command('setenv pxefile_addr_r %x' % addr) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert f"Config file '{bootfile}' found" in output + + pattern = f.get('pattern') + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + + # pxe config is loaded where multiple labels are there and need to + # select particular label to boot and check for expected string + # In this case invalid label is selected, it should load invalid + # label and if it fails it should load the default label to boot + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(invalid_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_invalid]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_invalid} did not match!' + + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 3e01be11029..76a550d45a1 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -55,6 +55,32 @@ class ConsoleDisableCheck(object): self.console.disable_check_count[self.check_type] -= 1 self.console.eval_bad_patterns() +class ConsoleEnableCheck(object): + """Context manager (for Python's with statement) that temporarily enables + the specified console output error check. This is useful when executing a + command that might raise an extra bad pattern, beyond the default bad + patterns, in order to validate that the extra bad pattern is actually + detected. This class is used internally by ConsoleBase::enable_check(); it + is not intended for direct usage.""" + + def __init__(self, console, check_type, check_pattern): + self.console = console + self.check_type = check_type + self.check_pattern = check_pattern + + def __enter__(self): + global bad_pattern_defs + self.default_bad_patterns = bad_pattern_defs + bad_pattern_defs += ((self.check_type, self.check_pattern),) + self.console.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs} + self.console.eval_bad_patterns() + + def __exit__(self, extype, value, traceback): + global bad_pattern_defs + bad_pattern_defs = self.default_bad_patterns + self.console.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs} + self.console.eval_bad_patterns() + class ConsoleSetupTimeout(object): """Context manager (for Python's with statement) that temporarily sets up timeout for specific command. This is useful when execution time is greater @@ -492,6 +518,24 @@ class ConsoleBase(object): return ConsoleDisableCheck(self, check_type) + def enable_check(self, check_type, check_pattern): + """Temporarily enable an error check of U-Boot's output. + + Create a new context manager (for use with the "with" statement) which + temporarily enables a particular console output error check. The + arguments form a new element of bad_pattern_defs defined above. + + Args: + check_type: The type of error-check or bad pattern to enable. + check_pattern: The regexes for text error pattern or bad pattern + to be checked. + + Returns: + A context manager object. + """ + + return ConsoleEnableCheck(self, check_type, check_pattern) + def temporary_timeout(self, timeout): """Temporarily set up different timeout for commands. diff --git a/tools/Kconfig b/tools/Kconfig index 667807b3317..5c75af48fe3 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -98,7 +98,7 @@ config TOOLS_SHA512 config TOOLS_MKEFICAPSULE bool "Build efimkcapsule command" - default y if EFI_CAPSULE_ON_DISK + default y if EFI_LOADER help This command allows users to create a UEFI capsule file and, optionally sign that file. If you want to enable UEFI capsule |