diff options
36 files changed, 205 insertions, 315 deletions
diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi deleted file mode 100644 index dd5a208cc1b..00000000000 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board - * - * Copyright (C) 2021-2024 Renesas Electronics Corporation - */ - -#include "r8a774a1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi deleted file mode 100644 index bd91a963cd6..00000000000 --- a/arch/arm/dts/r8a774a1-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on RZ/G2 R8A774A1 SoC - * - * Copyright (C) 2021 Renesas Electronics Corporation - */ - -#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi deleted file mode 100644 index b378cabb22c..00000000000 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board - * - * Copyright (C) 2021-2024 Renesas Electronics Corp. - */ - -#include "r8a774b1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi deleted file mode 100644 index 38a82f065c0..00000000000 --- a/arch/arm/dts/r8a774b1-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774c0-u-boot.dtsi b/arch/arm/dts/r8a774c0-u-boot.dtsi index 4572c22f6c1..17b863d23c9 100644 --- a/arch/arm/dts/r8a774c0-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-u-boot.dtsi @@ -6,8 +6,6 @@ * */ -#include "r8a779x-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi deleted file mode 100644 index 560bea46ad7..00000000000 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board - * - * Copyright (C) 2020-2024 Renesas Electronics Corp. - */ - -#include "r8a774e1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi deleted file mode 100644 index f314b2b0cf8..00000000000 --- a/arch/arm/dts/r8a774e1-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dtsi b/arch/arm/dts/r8a7790-lager-u-boot.dtsi index ed1891706ce..2b18e2e6af4 100644 --- a/arch/arm/dts/r8a7790-lager-u-boot.dtsi +++ b/arch/arm/dts/r8a7790-lager-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7790-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dtsi b/arch/arm/dts/r8a7790-stout-u-boot.dtsi index 3b393045e36..788432bc590 100644 --- a/arch/arm/dts/r8a7790-stout-u-boot.dtsi +++ b/arch/arm/dts/r8a7790-stout-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7790-u-boot.dtsi" - -&scifa0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7790-u-boot.dtsi b/arch/arm/dts/r8a7790-u-boot.dtsi deleted file mode 100644 index 2a7d76bd7b1..00000000000 --- a/arch/arm/dts/r8a7790-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7790 SoC - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi index 541c4191d69..ed258d55e58 100644 --- a/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi +++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7791-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dtsi b/arch/arm/dts/r8a7791-porter-u-boot.dtsi index cbf2c5265d8..cb80842f326 100644 --- a/arch/arm/dts/r8a7791-porter-u-boot.dtsi +++ b/arch/arm/dts/r8a7791-porter-u-boot.dtsi @@ -5,20 +5,13 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7791-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - -&i2c6 { - status = "okay"; - clock-frequency = <400000>; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; + +&i2c6 { + clock-frequency = <400000>; +}; diff --git a/arch/arm/dts/r8a7791-u-boot.dtsi b/arch/arm/dts/r8a7791-u-boot.dtsi deleted file mode 100644 index bb0e2fd106c..00000000000 --- a/arch/arm/dts/r8a7791-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7791 SoC - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dtsi b/arch/arm/dts/r8a7792-blanche-u-boot.dtsi deleted file mode 100644 index 8c36a3e5850..00000000000 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Blanche board - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -#include "r8a7792-u-boot.dtsi" - -&iic3 { - status = "okay"; -}; - -&scif0 { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7792-u-boot.dtsi b/arch/arm/dts/r8a7792-u-boot.dtsi deleted file mode 100644 index ebbdcb7efd5..00000000000 --- a/arch/arm/dts/r8a7792-u-boot.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7792 SoC - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -#include "r8a779x-u-boot.dtsi" - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dtsi b/arch/arm/dts/r8a7793-gose-u-boot.dtsi index 41c4361c6e1..fd99e0ffe76 100644 --- a/arch/arm/dts/r8a7793-gose-u-boot.dtsi +++ b/arch/arm/dts/r8a7793-gose-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7793-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7793-u-boot.dtsi b/arch/arm/dts/r8a7793-u-boot.dtsi deleted file mode 100644 index 08f2248e1f3..00000000000 --- a/arch/arm/dts/r8a7793-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7793 SoC - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dtsi b/arch/arm/dts/r8a7794-alt-u-boot.dtsi index e156b4c93c7..fea7138a1c1 100644 --- a/arch/arm/dts/r8a7794-alt-u-boot.dtsi +++ b/arch/arm/dts/r8a7794-alt-u-boot.dtsi @@ -5,48 +5,9 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7794-u-boot.dtsi" - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&pfc { - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&scif2 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dtsi b/arch/arm/dts/r8a7794-silk-u-boot.dtsi index e448ea7e146..f87d04b0ae0 100644 --- a/arch/arm/dts/r8a7794-silk-u-boot.dtsi +++ b/arch/arm/dts/r8a7794-silk-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7794-u-boot.dtsi" - -&scif2 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7794-u-boot.dtsi b/arch/arm/dts/r8a7794-u-boot.dtsi deleted file mode 100644 index 303afaeb4ce..00000000000 --- a/arch/arm/dts/r8a7794-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7794 SoC - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 768d633ded0..13760f3d5d4 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index db062f8e8c7..9cc0d52f634 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index d67e94e318b..3cf32d84ca0 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index 8dfa56c2f13..d00ef2f3105 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi index 088839907c2..df862978cba 100644 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index b701f68db81..d9dcce00e90 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index f4bafb6d088..85fccbabfb3 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a779x-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi index f506a666518..a4e75a67dc3 100644 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a779f0-u-boot.dtsi b/arch/arm/dts/r8a779f0-u-boot.dtsi index 08d32fef2b9..a7ff4eb708a 100644 --- a/arch/arm/dts/r8a779f0-u-boot.dtsi +++ b/arch/arm/dts/r8a779f0-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index cc9d99b0f34..5aa61314834 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { binman: binman { multiple-images; @@ -135,14 +133,6 @@ }; }; -&cpg { - bootph-all; -}; - -&hscif0 { - bootph-all; -}; - &hscif0_pins { bootph-all; }; @@ -151,19 +141,11 @@ bootph-all; }; -&pfc { - bootph-all; -}; - &rpc { bank-width = <2>; num-cs = <1>; }; -&rst { - bootph-all; -}; - &soc { apmu@e6170000 { /* Remoteproc */ compatible = "renesas,r8a779g0-cr52"; diff --git a/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi b/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi deleted file mode 100644 index b59cc7deca7..00000000000 --- a/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car 64bit SoC - * - * Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org> - */ - -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; diff --git a/arch/arm/dts/r8a779x-u-boot.dtsi b/arch/arm/dts/r8a779x-u-boot.dtsi deleted file mode 100644 index d1441f1f9df..00000000000 --- a/arch/arm/dts/r8a779x-u-boot.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car Gen3 - * - * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> - */ - -/ { - soc { - bootph-all; - }; -}; - -&cpg { - bootph-all; -}; - -&extal_clk { - bootph-all; -}; - -&prr { - bootph-all; -}; diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 375cc4a4930..5745acf4023 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -68,7 +68,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, if (ret) return ret; - if (core->type == CLK_TYPE_GEN3_MDSEL) { + if (core->type == CLK_TYPE_GEN3_MDSEL || core->type == CLK_TYPE_GEN4_MDSEL) { shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16; parent->dev = clk->dev; parent->id = core->parent >> shift; @@ -318,6 +318,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk) "FIXED"); case CLK_TYPE_GEN3_MDSEL: + fallthrough; + case CLK_TYPE_GEN4_MDSEL: shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16; div = (core->div >> shift) & 0xffff; rate = gen3_clk_get_rate64(&parent) / div; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 1bb67f50352..a0f2948335f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -335,6 +335,14 @@ config WDT_K3_RTI_FW_FILE endif +config WDT_RENESAS + bool "Renesas watchdog timer support" + depends on WDT && R8A779F0 + select CLK + select CLK_RENESAS + help + Enables Renesas SoC R8A779F0 watchdog timer support. + config WDT_SANDBOX bool "Enable Watchdog Timer support for Sandbox" depends on SANDBOX && WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index e6bd4c587af..c4467d6e126 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_WDT_MTK) += mtk_wdt.o obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o +obj-$(CONFIG_WDT_RENESAS) += renesas_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c new file mode 100644 index 00000000000..046e11915b9 --- /dev/null +++ b/drivers/watchdog/renesas_wdt.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2025 Red Hat, Inc., Shmuel Leib Melamud <smelamud@redhat.com> + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <wdt.h> + +#define usleep_range(a, b) udelay((a)) + +struct rwdt { + u32 cnt; + u32 csra; + u32 csrb; +}; + +#define RWTCSRA_WOVF BIT(4) +#define RWTCSRA_WRFLG BIT(5) +#define RWTCSRA_TME BIT(7) + +#define CSR_MASK 0xA5A5A500 +#define CNT_MASK 0x5A5A0000 + +#define MAX_CNT_VALUE 65536 +/* + * In probe, clk_rate is checked to be not more than 16 bit * biggest clock + * divider (12 bits). d is only a factor to fully utilize the WDT counter and + * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits. + */ +#define MUL_BY_CLKS_PER_SEC(p, d) \ + DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks]) + +/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */ +#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate) + +static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 }; + +struct rwdt_priv { + struct rwdt __iomem *wdt; + unsigned long clk_rate; + u8 cks; + struct clk clk; +}; + +static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles) +{ + unsigned int delay; + + delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); + + usleep_range(delay, 2 * delay); +} + +static int rwdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct rwdt_priv *priv = dev_get_priv(dev); + u64 max_timeout; + u8 val; + + max_timeout = DIV_BY_CLKS_PER_SEC(priv, MAX_CNT_VALUE); + timeout = min(max_timeout, timeout / 1000); + + /* Stop the timer before we modify any register */ + val = readb_relaxed(&priv->wdt->csra) & ~RWTCSRA_TME; + writel_relaxed(val | CSR_MASK, &priv->wdt->csra); + /* Delay 2 cycles before setting watchdog counter */ + rwdt_wait_cycles(priv, 2); + + while (readb_relaxed(&priv->wdt->csra) & RWTCSRA_WRFLG) + cpu_relax(); + + writel_relaxed((MAX_CNT_VALUE - MUL_BY_CLKS_PER_SEC(priv, timeout)) + | CNT_MASK, &priv->wdt->cnt); + + writel_relaxed(priv->cks | RWTCSRA_TME | CSR_MASK, &priv->wdt->csra); + + return 0; +} + +static int rwdt_stop(struct udevice *dev) +{ + struct rwdt_priv *priv = dev_get_priv(dev); + + writel_relaxed(priv->cks | CSR_MASK, &priv->wdt->csra); + + return 0; +} + +static int rwdt_reset(struct udevice *dev) +{ + struct rwdt_priv *priv = dev_get_priv(dev); + u8 val; + + /* Stop the timer before we modify any register */ + val = readb_relaxed(&priv->wdt->csra) & ~RWTCSRA_TME; + writel_relaxed(val | CSR_MASK, &priv->wdt->csra); + /* Delay 2 cycles before setting watchdog counter */ + rwdt_wait_cycles(priv, 2); + + writel_relaxed(0xffff | CNT_MASK, &priv->wdt->cnt); + /* smallest divider to reboot soon */ + writel_relaxed(0 | CSR_MASK, &priv->wdt->csra); + + readb_poll_timeout(&priv->wdt->csra, val, !(val & RWTCSRA_WRFLG), 100); + + writel_relaxed(RWTCSRA_TME | CSR_MASK, &priv->wdt->csra); + + /* wait 2 cycles, so watchdog will trigger */ + rwdt_wait_cycles(priv, 2); + + return 0; +} + +static int rwdt_probe(struct udevice *dev) +{ + struct rwdt_priv *priv = dev_get_priv(dev); + unsigned long clks_per_sec; + int ret, i; + + priv->wdt = dev_remap_addr(dev); + if (!priv->wdt) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + priv->clk_rate = clk_get_rate(&priv->clk); + if (!priv->clk_rate) { + ret = -ENOENT; + goto err_clk_disable; + } + + /* + * Find the largest possible divider that allows clock rate + * (clks_per_sec) to stay within 16 bits. In this case, we can still + * measure the smallest timeout (1s) and make the largest allowed + * timeout as large as possible. + */ + for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) { + clks_per_sec = priv->clk_rate / clk_divs[i]; + if (clks_per_sec && clks_per_sec < 65536) { + priv->cks = i; + break; + } + } + + /* can't find a suitable clock divider */ + if (i < 0) { + ret = -ERANGE; + goto err_clk_disable; + } + + return 0; + +err_clk_disable: + clk_disable(&priv->clk); + + return ret; +} + +static const struct wdt_ops rwdt_ops = { + .start = rwdt_start, + .reset = rwdt_reset, + .stop = rwdt_stop, +}; + +static const struct udevice_id rwdt_ids[] = { + { .compatible = "renesas,rcar-gen2-wdt" }, + { .compatible = "renesas,rcar-gen3-wdt" }, + { .compatible = "renesas,rcar-gen4-wdt" }, + {} +}; + +U_BOOT_DRIVER(wdt_renesas) = { + .name = "wdt_renesas", + .id = UCLASS_WDT, + .of_match = rwdt_ids, + .ops = &rwdt_ops, + .probe = rwdt_probe, + .priv_auto = sizeof(struct rwdt_priv), +}; |