diff options
357 files changed, 2445 insertions, 1935 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index f200b40dbb2..bda762451fd 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2019 ubuntu_vm: ubuntu-22.04 macos_vm: macOS-12 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-07Oct2022 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7052a6061cb..6f4c34fc4a3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: trini/u-boot-gitlab-ci-runner:jammy-20221003-07Oct2022 +image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022 # We run some tests in different order, to catch some failures quicker. stages: @@ -92,7 +92,6 @@ build all 64bit ARM platforms: script: - virtualenv -p /usr/bin/python3 /tmp/venv - . /tmp/venv/bin/activate - - pip install pyelftools - ret=0; ./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?; if [[ $ret -ne 0 ]]; then @@ -312,9 +312,9 @@ config SYS_MALLOC_LEN default 0x4000000 if SANDBOX default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON default 0x200000 if ARCH_BMIPS || X86 - default 0x120000 if MACH_SUNIV - default 0x220000 if MACH_SUN8I_V3S - default 0x4020000 if ARCH_SUNXI + default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256 + default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64 + default 0x120000 if SUNXI_MINIMUM_DRAM_MB >= 32 default 0x400000 help This defines memory to be allocated for Dynamic allocation diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 963a77229db..eeb0839afe3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -714,7 +714,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6.dtb \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ - sun50i-h616-orangepi-zero2.dtb + sun50i-h616-orangepi-zero2.dtb \ + sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ @@ -1206,7 +1207,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcom-picoitx.dtb \ stm32mp15xx-dhcor-avenger96.dtb \ - stm32mp15xx-dhcor-drc-compact.dtb + stm32mp15xx-dhcor-drc-compact.dtb \ + stm32mp15xx-dhcor-testbench.dtb dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi index 9a008df7506..491412119b1 100644 --- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file was generated by the AM64x_DDR4_RegConfig_Tool, Revision: 0.6.0 - * This file was generated on Oct 26 2020 - * DDR4 Frequency = 800MHz (1600MTs) + * This file was generated with the + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 + * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time) + * DDR Type: DDR4 + * Frequency = 800MHz (1600MTs) * Density: 16Gb * Number of Ranks: 1 */ @@ -49,11 +51,11 @@ #define DDRSS_CTL_35_DATA 0x00000000 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 -#define DDRSS_CTL_38_DATA 0x04000918 +#define DDRSS_CTL_38_DATA 0x0400091C #define DDRSS_CTL_39_DATA 0x1C1C1C1C -#define DDRSS_CTL_40_DATA 0x04000918 +#define DDRSS_CTL_40_DATA 0x0400091C #define DDRSS_CTL_41_DATA 0x1C1C1C1C -#define DDRSS_CTL_42_DATA 0x04000918 +#define DDRSS_CTL_42_DATA 0x0400091C #define DDRSS_CTL_43_DATA 0x1C1C1C1C #define DDRSS_CTL_44_DATA 0x05050404 #define DDRSS_CTL_45_DATA 0x00002706 @@ -215,22 +217,22 @@ #define DDRSS_CTL_201_DATA 0x00000000 #define DDRSS_CTL_202_DATA 0x00000000 #define DDRSS_CTL_203_DATA 0x00000000 -#define DDRSS_CTL_204_DATA 0x00041400 +#define DDRSS_CTL_204_DATA 0x00042400 #define DDRSS_CTL_205_DATA 0x00000301 #define DDRSS_CTL_206_DATA 0x00000000 -#define DDRSS_CTL_207_DATA 0x00000414 +#define DDRSS_CTL_207_DATA 0x00000424 #define DDRSS_CTL_208_DATA 0x00000301 #define DDRSS_CTL_209_DATA 0x00000000 -#define DDRSS_CTL_210_DATA 0x00000414 +#define DDRSS_CTL_210_DATA 0x00000424 #define DDRSS_CTL_211_DATA 0x00000301 #define DDRSS_CTL_212_DATA 0x00000000 -#define DDRSS_CTL_213_DATA 0x00000414 +#define DDRSS_CTL_213_DATA 0x00000424 #define DDRSS_CTL_214_DATA 0x00000301 #define DDRSS_CTL_215_DATA 0x00000000 -#define DDRSS_CTL_216_DATA 0x00000414 +#define DDRSS_CTL_216_DATA 0x00000424 #define DDRSS_CTL_217_DATA 0x00000301 #define DDRSS_CTL_218_DATA 0x00000000 -#define DDRSS_CTL_219_DATA 0x00000414 +#define DDRSS_CTL_219_DATA 0x00000424 #define DDRSS_CTL_220_DATA 0x00000301 #define DDRSS_CTL_221_DATA 0x00000000 #define DDRSS_CTL_222_DATA 0x00000000 @@ -247,12 +249,12 @@ #define DDRSS_CTL_233_DATA 0x00000000 #define DDRSS_CTL_234_DATA 0x00000000 #define DDRSS_CTL_235_DATA 0x00000000 -#define DDRSS_CTL_236_DATA 0x00000401 -#define DDRSS_CTL_237_DATA 0x00000401 -#define DDRSS_CTL_238_DATA 0x00000401 -#define DDRSS_CTL_239_DATA 0x00000401 -#define DDRSS_CTL_240_DATA 0x00000401 -#define DDRSS_CTL_241_DATA 0x00000401 +#define DDRSS_CTL_236_DATA 0x00001401 +#define DDRSS_CTL_237_DATA 0x00001401 +#define DDRSS_CTL_238_DATA 0x00001401 +#define DDRSS_CTL_239_DATA 0x00001401 +#define DDRSS_CTL_240_DATA 0x00001401 +#define DDRSS_CTL_241_DATA 0x00001401 #define DDRSS_CTL_242_DATA 0x00000493 #define DDRSS_CTL_243_DATA 0x00000493 #define DDRSS_CTL_244_DATA 0x00000493 @@ -341,9 +343,9 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x00000000 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01000000 -#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_332_DATA 0x00000100 #define DDRSS_CTL_333_DATA 0x00010000 #define DDRSS_CTL_334_DATA 0x00000000 #define DDRSS_CTL_335_DATA 0x00000000 @@ -386,8 +388,8 @@ #define DDRSS_CTL_372_DATA 0x06060C06 #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x02000000 -#define DDRSS_CTL_375_DATA 0x03020101 -#define DDRSS_CTL_376_DATA 0x00000303 +#define DDRSS_CTL_375_DATA 0x05020101 +#define DDRSS_CTL_376_DATA 0x00000505 #define DDRSS_CTL_377_DATA 0x02020200 #define DDRSS_CTL_378_DATA 0x02020202 #define DDRSS_CTL_379_DATA 0x02020202 @@ -403,7 +405,7 @@ #define DDRSS_CTL_389_DATA 0x00000200 #define DDRSS_CTL_390_DATA 0x0000DB60 #define DDRSS_CTL_391_DATA 0x0001E780 -#define DDRSS_CTL_392_DATA 0x0A0B0302 +#define DDRSS_CTL_392_DATA 0x0C0D0302 #define DDRSS_CTL_393_DATA 0x001E090A #define DDRSS_CTL_394_DATA 0x000030C0 #define DDRSS_CTL_395_DATA 0x00000200 @@ -412,7 +414,7 @@ #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x0000DB60 #define DDRSS_CTL_400_DATA 0x0001E780 -#define DDRSS_CTL_401_DATA 0x0A0B0302 +#define DDRSS_CTL_401_DATA 0x0C0D0302 #define DDRSS_CTL_402_DATA 0x001E090A #define DDRSS_CTL_403_DATA 0x000030C0 #define DDRSS_CTL_404_DATA 0x00000200 @@ -421,7 +423,7 @@ #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x0000DB60 #define DDRSS_CTL_409_DATA 0x0001E780 -#define DDRSS_CTL_410_DATA 0x0A0B0302 +#define DDRSS_CTL_410_DATA 0x0C0D0302 #define DDRSS_CTL_411_DATA 0x0000090A #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A @@ -601,14 +603,14 @@ #define DDRSS_PI_164_DATA 0x00007800 #define DDRSS_PI_165_DATA 0x00780078 #define DDRSS_PI_166_DATA 0x00141414 -#define DDRSS_PI_167_DATA 0x00000038 -#define DDRSS_PI_168_DATA 0x00000038 -#define DDRSS_PI_169_DATA 0x00040038 +#define DDRSS_PI_167_DATA 0x0000003A +#define DDRSS_PI_168_DATA 0x0000003A +#define DDRSS_PI_169_DATA 0x0004003A #define DDRSS_PI_170_DATA 0x04000400 #define DDRSS_PI_171_DATA 0xC8040009 -#define DDRSS_PI_172_DATA 0x04000918 -#define DDRSS_PI_173_DATA 0x000918C8 -#define DDRSS_PI_174_DATA 0x0018C804 +#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_173_DATA 0x00091CC8 +#define DDRSS_PI_174_DATA 0x001CC804 #define DDRSS_PI_175_DATA 0x00000118 #define DDRSS_PI_176_DATA 0x00001860 #define DDRSS_PI_177_DATA 0x00000118 @@ -621,14 +623,14 @@ #define DDRSS_PI_184_DATA 0x010C010C #define DDRSS_PI_185_DATA 0x0000010C #define DDRSS_PI_186_DATA 0x00000000 -#define DDRSS_PI_187_DATA 0x03000000 -#define DDRSS_PI_188_DATA 0x01010303 +#define DDRSS_PI_187_DATA 0x05000000 +#define DDRSS_PI_188_DATA 0x01010505 #define DDRSS_PI_189_DATA 0x01010101 #define DDRSS_PI_190_DATA 0x00181818 #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 -#define DDRSS_PI_193_DATA 0x0B000000 -#define DDRSS_PI_194_DATA 0x0A0A0B0B +#define DDRSS_PI_193_DATA 0x0D000000 +#define DDRSS_PI_194_DATA 0x0A0A0D0D #define DDRSS_PI_195_DATA 0x0303030A #define DDRSS_PI_196_DATA 0x00000000 #define DDRSS_PI_197_DATA 0x00000000 @@ -656,15 +658,15 @@ #define DDRSS_PI_219_DATA 0x001600C8 #define DDRSS_PI_220_DATA 0x010100C8 #define DDRSS_PI_221_DATA 0x00001B01 -#define DDRSS_PI_222_DATA 0x1F0F0051 -#define DDRSS_PI_223_DATA 0x03000001 -#define DDRSS_PI_224_DATA 0x001B0A0B -#define DDRSS_PI_225_DATA 0x1F0F0051 -#define DDRSS_PI_226_DATA 0x03000001 -#define DDRSS_PI_227_DATA 0x001B0A0B -#define DDRSS_PI_228_DATA 0x1F0F0051 -#define DDRSS_PI_229_DATA 0x03000001 -#define DDRSS_PI_230_DATA 0x00000A0B +#define DDRSS_PI_222_DATA 0x1F0F0053 +#define DDRSS_PI_223_DATA 0x05000001 +#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_225_DATA 0x1F0F0053 +#define DDRSS_PI_226_DATA 0x05000001 +#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_228_DATA 0x1F0F0053 +#define DDRSS_PI_229_DATA 0x05000001 +#define DDRSS_PI_230_DATA 0x00010A0D #define DDRSS_PI_231_DATA 0x0C0B0700 #define DDRSS_PI_232_DATA 0x000D0605 #define DDRSS_PI_233_DATA 0x0000C570 @@ -731,52 +733,52 @@ #define DDRSS_PI_294_DATA 0x01000000 #define DDRSS_PI_295_DATA 0x00020201 #define DDRSS_PI_296_DATA 0x00000000 -#define DDRSS_PI_297_DATA 0x00000414 +#define DDRSS_PI_297_DATA 0x00000424 #define DDRSS_PI_298_DATA 0x00000301 #define DDRSS_PI_299_DATA 0x00000000 #define DDRSS_PI_300_DATA 0x00000000 #define DDRSS_PI_301_DATA 0x00000000 -#define DDRSS_PI_302_DATA 0x00000401 +#define DDRSS_PI_302_DATA 0x00001401 #define DDRSS_PI_303_DATA 0x00000493 #define DDRSS_PI_304_DATA 0x00000000 -#define DDRSS_PI_305_DATA 0x00000414 +#define DDRSS_PI_305_DATA 0x00000424 #define DDRSS_PI_306_DATA 0x00000301 #define DDRSS_PI_307_DATA 0x00000000 #define DDRSS_PI_308_DATA 0x00000000 #define DDRSS_PI_309_DATA 0x00000000 -#define DDRSS_PI_310_DATA 0x00000401 +#define DDRSS_PI_310_DATA 0x00001401 #define DDRSS_PI_311_DATA 0x00000493 #define DDRSS_PI_312_DATA 0x00000000 -#define DDRSS_PI_313_DATA 0x00000414 +#define DDRSS_PI_313_DATA 0x00000424 #define DDRSS_PI_314_DATA 0x00000301 #define DDRSS_PI_315_DATA 0x00000000 #define DDRSS_PI_316_DATA 0x00000000 #define DDRSS_PI_317_DATA 0x00000000 -#define DDRSS_PI_318_DATA 0x00000401 +#define DDRSS_PI_318_DATA 0x00001401 #define DDRSS_PI_319_DATA 0x00000493 #define DDRSS_PI_320_DATA 0x00000000 -#define DDRSS_PI_321_DATA 0x00000414 +#define DDRSS_PI_321_DATA 0x00000424 #define DDRSS_PI_322_DATA 0x00000301 #define DDRSS_PI_323_DATA 0x00000000 #define DDRSS_PI_324_DATA 0x00000000 #define DDRSS_PI_325_DATA 0x00000000 -#define DDRSS_PI_326_DATA 0x00000401 +#define DDRSS_PI_326_DATA 0x00001401 #define DDRSS_PI_327_DATA 0x00000493 #define DDRSS_PI_328_DATA 0x00000000 -#define DDRSS_PI_329_DATA 0x00000414 +#define DDRSS_PI_329_DATA 0x00000424 #define DDRSS_PI_330_DATA 0x00000301 #define DDRSS_PI_331_DATA 0x00000000 #define DDRSS_PI_332_DATA 0x00000000 #define DDRSS_PI_333_DATA 0x00000000 -#define DDRSS_PI_334_DATA 0x00000401 +#define DDRSS_PI_334_DATA 0x00001401 #define DDRSS_PI_335_DATA 0x00000493 #define DDRSS_PI_336_DATA 0x00000000 -#define DDRSS_PI_337_DATA 0x00000414 +#define DDRSS_PI_337_DATA 0x00000424 #define DDRSS_PI_338_DATA 0x00000301 #define DDRSS_PI_339_DATA 0x00000000 #define DDRSS_PI_340_DATA 0x00000000 #define DDRSS_PI_341_DATA 0x00000000 -#define DDRSS_PI_342_DATA 0x00000401 +#define DDRSS_PI_342_DATA 0x00001401 #define DDRSS_PI_343_DATA 0x00000493 #define DDRSS_PI_344_DATA 0x00000000 #define DDRSS_PHY_0_DATA 0x04C00000 @@ -871,7 +873,7 @@ #define DDRSS_PHY_89_DATA 0x31804000 #define DDRSS_PHY_90_DATA 0x04BF0340 #define DDRSS_PHY_91_DATA 0x01008080 -#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_92_DATA 0x04050001 #define DDRSS_PHY_93_DATA 0x00000504 #define DDRSS_PHY_94_DATA 0x42100010 #define DDRSS_PHY_95_DATA 0x010C053E @@ -1127,7 +1129,7 @@ #define DDRSS_PHY_345_DATA 0x31804000 #define DDRSS_PHY_346_DATA 0x04BF0340 #define DDRSS_PHY_347_DATA 0x01008080 -#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_348_DATA 0x04050001 #define DDRSS_PHY_349_DATA 0x00000504 #define DDRSS_PHY_350_DATA 0x42100010 #define DDRSS_PHY_351_DATA 0x010C053E @@ -2113,7 +2115,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000046 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2184,4 +2186,4 @@ #define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x300D3F11 #define DDRSS_PHY_1404_DATA 0x01990000 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi index dde5ab150da..f225c1f0674 100644 --- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi +++ b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi @@ -1,18 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 - * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 + * Wed Feb 02 2022 16:59:34 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 - * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz + * F0 = 50MHz F1 = 800MHz F2 = 800MHz * Density (per channel): 16Gb * Number of Ranks: 1 -*/ + */ #define DDRSS_PLL_FHS_CNT 6 -#define DDRSS_PLL_FREQUENCY_1 333350000 -#define DDRSS_PLL_FREQUENCY_2 333350000 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -25,14 +24,14 @@ #define DDRSS_CTL_8_DATA 0x000186A0 #define DDRSS_CTL_9_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x00000064 -#define DDRSS_CTL_11_DATA 0x000208D6 -#define DDRSS_CTL_12_DATA 0x00145856 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000536 -#define DDRSS_CTL_15_DATA 0x000208D6 -#define DDRSS_CTL_16_DATA 0x00145856 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000536 +#define DDRSS_CTL_18_DATA 0x00000640 #define DDRSS_CTL_19_DATA 0x01010100 #define DDRSS_CTL_20_DATA 0x01010100 #define DDRSS_CTL_21_DATA 0x01000110 @@ -48,8 +47,8 @@ #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 -#define DDRSS_CTL_34_DATA 0x02000010 -#define DDRSS_CTL_35_DATA 0x00001B1B +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 #define DDRSS_CTL_38_DATA 0x0000040C @@ -62,64 +61,64 @@ #define DDRSS_CTL_45_DATA 0x00000700 #define DDRSS_CTL_46_DATA 0x09090004 #define DDRSS_CTL_47_DATA 0x00000203 -#define DDRSS_CTL_48_DATA 0x00290006 -#define DDRSS_CTL_49_DATA 0x0909001D -#define DDRSS_CTL_50_DATA 0x0000150C -#define DDRSS_CTL_51_DATA 0x00290006 -#define DDRSS_CTL_52_DATA 0x0909001D -#define DDRSS_CTL_53_DATA 0x0900150C +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000190F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900190F #define DDRSS_CTL_54_DATA 0x000A0A09 #define DDRSS_CTL_55_DATA 0x040006DB #define DDRSS_CTL_56_DATA 0x09092004 -#define DDRSS_CTL_57_DATA 0x00000A0A -#define DDRSS_CTL_58_DATA 0x05005B68 -#define DDRSS_CTL_59_DATA 0x09092005 -#define DDRSS_CTL_60_DATA 0x00000A0A -#define DDRSS_CTL_61_DATA 0x05005B68 -#define DDRSS_CTL_62_DATA 0x03042005 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 #define DDRSS_CTL_63_DATA 0x04050002 -#define DDRSS_CTL_64_DATA 0x0E0D0E0D +#define DDRSS_CTL_64_DATA 0x100F100F #define DDRSS_CTL_65_DATA 0x01010008 -#define DDRSS_CTL_66_DATA 0x041A1A07 -#define DDRSS_CTL_67_DATA 0x030E0E03 -#define DDRSS_CTL_68_DATA 0x00000E0E +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 #define DDRSS_CTL_69_DATA 0x00000101 #define DDRSS_CTL_70_DATA 0x00000000 #define DDRSS_CTL_71_DATA 0x01000000 #define DDRSS_CTL_72_DATA 0x00130803 #define DDRSS_CTL_73_DATA 0x000000BB -#define DDRSS_CTL_74_DATA 0x000000FE -#define DDRSS_CTL_75_DATA 0x00000A20 -#define DDRSS_CTL_76_DATA 0x000000FE -#define DDRSS_CTL_77_DATA 0x00000A20 +#define DDRSS_CTL_74_DATA 0x00000130 +#define DDRSS_CTL_75_DATA 0x00000C28 +#define DDRSS_CTL_76_DATA 0x00000130 +#define DDRSS_CTL_77_DATA 0x00000C28 #define DDRSS_CTL_78_DATA 0x00000005 #define DDRSS_CTL_79_DATA 0x0000000A #define DDRSS_CTL_80_DATA 0x00000010 -#define DDRSS_CTL_81_DATA 0x0000007F -#define DDRSS_CTL_82_DATA 0x0000013D -#define DDRSS_CTL_83_DATA 0x0000007F -#define DDRSS_CTL_84_DATA 0x0000013D +#define DDRSS_CTL_81_DATA 0x00000098 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000098 +#define DDRSS_CTL_84_DATA 0x0000017E #define DDRSS_CTL_85_DATA 0x03004000 #define DDRSS_CTL_86_DATA 0x00001201 -#define DDRSS_CTL_87_DATA 0x00050005 -#define DDRSS_CTL_88_DATA 0x00000005 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 #define DDRSS_CTL_89_DATA 0x00000000 -#define DDRSS_CTL_90_DATA 0x05101008 +#define DDRSS_CTL_90_DATA 0x05121208 #define DDRSS_CTL_91_DATA 0x05030A05 -#define DDRSS_CTL_92_DATA 0x05030A05 -#define DDRSS_CTL_93_DATA 0x01030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 #define DDRSS_CTL_94_DATA 0x02010201 #define DDRSS_CTL_95_DATA 0x00001401 -#define DDRSS_CTL_96_DATA 0x01030014 -#define DDRSS_CTL_97_DATA 0x01030103 -#define DDRSS_CTL_98_DATA 0x00000103 +#define DDRSS_CTL_96_DATA 0x01360014 +#define DDRSS_CTL_97_DATA 0x01360136 +#define DDRSS_CTL_98_DATA 0x00000136 #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x05010303 -#define DDRSS_CTL_101_DATA 0x0A040505 -#define DDRSS_CTL_102_DATA 0x05050203 -#define DDRSS_CTL_103_DATA 0x030A0505 -#define DDRSS_CTL_104_DATA 0x05050502 -#define DDRSS_CTL_105_DATA 0x03030305 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 #define DDRSS_CTL_106_DATA 0x03010000 #define DDRSS_CTL_107_DATA 0x00010000 #define DDRSS_CTL_108_DATA 0x00000000 @@ -140,20 +139,20 @@ #define DDRSS_CTL_123_DATA 0x00002EC0 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x0000051D -#define DDRSS_CTL_126_DATA 0x00028800 -#define DDRSS_CTL_127_DATA 0x00028800 -#define DDRSS_CTL_128_DATA 0x00028800 -#define DDRSS_CTL_129_DATA 0x00028800 -#define DDRSS_CTL_130_DATA 0x00028800 +#define DDRSS_CTL_126_DATA 0x00030A00 +#define DDRSS_CTL_127_DATA 0x00030A00 +#define DDRSS_CTL_128_DATA 0x00030A00 +#define DDRSS_CTL_129_DATA 0x00030A00 +#define DDRSS_CTL_130_DATA 0x00030A00 #define DDRSS_CTL_131_DATA 0x00000000 -#define DDRSS_CTL_132_DATA 0x000046E0 -#define DDRSS_CTL_133_DATA 0x00028800 -#define DDRSS_CTL_134_DATA 0x00028800 -#define DDRSS_CTL_135_DATA 0x00028800 -#define DDRSS_CTL_136_DATA 0x00028800 -#define DDRSS_CTL_137_DATA 0x00028800 +#define DDRSS_CTL_132_DATA 0x00005518 +#define DDRSS_CTL_133_DATA 0x00030A00 +#define DDRSS_CTL_134_DATA 0x00030A00 +#define DDRSS_CTL_135_DATA 0x00030A00 +#define DDRSS_CTL_136_DATA 0x00030A00 +#define DDRSS_CTL_137_DATA 0x00030A00 #define DDRSS_CTL_138_DATA 0x00000000 -#define DDRSS_CTL_139_DATA 0x000046E0 +#define DDRSS_CTL_139_DATA 0x00005518 #define DDRSS_CTL_140_DATA 0x00000000 #define DDRSS_CTL_141_DATA 0x00000000 #define DDRSS_CTL_142_DATA 0x00000000 @@ -209,12 +208,12 @@ #define DDRSS_CTL_192_DATA 0x0005000A #define DDRSS_CTL_193_DATA 0x0404000D #define DDRSS_CTL_194_DATA 0x0000000D -#define DDRSS_CTL_195_DATA 0x00430086 -#define DDRSS_CTL_196_DATA 0x050500A7 -#define DDRSS_CTL_197_DATA 0x000000A7 -#define DDRSS_CTL_198_DATA 0x00430086 -#define DDRSS_CTL_199_DATA 0x050500A7 -#define DDRSS_CTL_200_DATA 0x000000A7 +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 #define DDRSS_CTL_201_DATA 0x00000000 #define DDRSS_CTL_202_DATA 0x00000000 #define DDRSS_CTL_203_DATA 0x00000000 @@ -239,11 +238,11 @@ #define DDRSS_CTL_222_DATA 0x00000000 #define DDRSS_CTL_223_DATA 0x00000000 #define DDRSS_CTL_224_DATA 0x00000031 -#define DDRSS_CTL_225_DATA 0x00000031 -#define DDRSS_CTL_226_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 #define DDRSS_CTL_227_DATA 0x00000031 -#define DDRSS_CTL_228_DATA 0x00000031 -#define DDRSS_CTL_229_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 #define DDRSS_CTL_230_DATA 0x00000000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 @@ -323,12 +322,12 @@ #define DDRSS_CTL_306_DATA 0x00400100 #define DDRSS_CTL_307_DATA 0x00080032 #define DDRSS_CTL_308_DATA 0x01000200 -#define DDRSS_CTL_309_DATA 0x029B0040 -#define DDRSS_CTL_310_DATA 0x00020014 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 #define DDRSS_CTL_311_DATA 0x00400100 -#define DDRSS_CTL_312_DATA 0x0014029B +#define DDRSS_CTL_312_DATA 0x00180320 #define DDRSS_CTL_313_DATA 0x00030000 -#define DDRSS_CTL_314_DATA 0x00220022 +#define DDRSS_CTL_314_DATA 0x00280028 #define DDRSS_CTL_315_DATA 0x00000100 #define DDRSS_CTL_316_DATA 0x01010000 #define DDRSS_CTL_317_DATA 0x00000000 @@ -344,9 +343,9 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x01000100 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01030303 -#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_332_DATA 0x00000001 #define DDRSS_CTL_333_DATA 0x00000000 #define DDRSS_CTL_334_DATA 0x00000000 #define DDRSS_CTL_335_DATA 0x00000000 @@ -390,14 +389,14 @@ #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x01050503 #define DDRSS_CTL_375_DATA 0x05020201 -#define DDRSS_CTL_376_DATA 0x08080B0B +#define DDRSS_CTL_376_DATA 0x08080C0C #define DDRSS_CTL_377_DATA 0x00080308 -#define DDRSS_CTL_378_DATA 0x000C030E -#define DDRSS_CTL_379_DATA 0x000C0310 -#define DDRSS_CTL_380_DATA 0x0C0C0810 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 #define DDRSS_CTL_381_DATA 0x01000000 -#define DDRSS_CTL_382_DATA 0x03010301 -#define DDRSS_CTL_383_DATA 0x04000101 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 #define DDRSS_CTL_384_DATA 0x1B000004 #define DDRSS_CTL_385_DATA 0x00000176 #define DDRSS_CTL_386_DATA 0x00000200 @@ -407,24 +406,24 @@ #define DDRSS_CTL_390_DATA 0x00000693 #define DDRSS_CTL_391_DATA 0x00000E9C #define DDRSS_CTL_392_DATA 0x03050202 -#define DDRSS_CTL_393_DATA 0x00240201 -#define DDRSS_CTL_394_DATA 0x00001440 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001850 #define DDRSS_CTL_395_DATA 0x00000200 #define DDRSS_CTL_396_DATA 0x00000200 #define DDRSS_CTL_397_DATA 0x00000200 #define DDRSS_CTL_398_DATA 0x00000200 -#define DDRSS_CTL_399_DATA 0x00005B20 -#define DDRSS_CTL_400_DATA 0x0000CA80 -#define DDRSS_CTL_401_DATA 0x080D0402 -#define DDRSS_CTL_402_DATA 0x00240405 -#define DDRSS_CTL_403_DATA 0x00001440 +#define DDRSS_CTL_399_DATA 0x00006D68 +#define DDRSS_CTL_400_DATA 0x0000F320 +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001850 #define DDRSS_CTL_404_DATA 0x00000200 #define DDRSS_CTL_405_DATA 0x00000200 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 -#define DDRSS_CTL_408_DATA 0x00005B20 -#define DDRSS_CTL_409_DATA 0x0000CA80 -#define DDRSS_CTL_410_DATA 0x080D0402 +#define DDRSS_CTL_408_DATA 0x00006D68 +#define DDRSS_CTL_409_DATA 0x0000F320 +#define DDRSS_CTL_410_DATA 0x070D0402 #define DDRSS_CTL_411_DATA 0x00000405 #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A @@ -483,7 +482,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x00010100 -#define DDRSS_PI_46_DATA 0x00000014 +#define DDRSS_PI_46_DATA 0x00000015 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -602,8 +601,8 @@ #define DDRSS_PI_162_DATA 0x00000000 #define DDRSS_PI_163_DATA 0x00000000 #define DDRSS_PI_164_DATA 0x00000800 -#define DDRSS_PI_165_DATA 0x00640064 -#define DDRSS_PI_166_DATA 0x000E0E01 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 #define DDRSS_PI_167_DATA 0x00000034 #define DDRSS_PI_168_DATA 0x00000042 #define DDRSS_PI_169_DATA 0x00020042 @@ -614,84 +613,84 @@ #define DDRSS_PI_174_DATA 0x001C0000 #define DDRSS_PI_175_DATA 0x00000013 #define DDRSS_PI_176_DATA 0x000000BB -#define DDRSS_PI_177_DATA 0x000000FE -#define DDRSS_PI_178_DATA 0x00000A20 -#define DDRSS_PI_179_DATA 0x000000FE -#define DDRSS_PI_180_DATA 0x04000A20 +#define DDRSS_PI_177_DATA 0x00000130 +#define DDRSS_PI_178_DATA 0x00000C28 +#define DDRSS_PI_179_DATA 0x00000130 +#define DDRSS_PI_180_DATA 0x04000C28 #define DDRSS_PI_181_DATA 0x01010404 #define DDRSS_PI_182_DATA 0x00001501 -#define DDRSS_PI_183_DATA 0x001B001B +#define DDRSS_PI_183_DATA 0x001D001D #define DDRSS_PI_184_DATA 0x01000100 #define DDRSS_PI_185_DATA 0x00000100 #define DDRSS_PI_186_DATA 0x00000000 #define DDRSS_PI_187_DATA 0x05050503 -#define DDRSS_PI_188_DATA 0x01010B0B +#define DDRSS_PI_188_DATA 0x01010C0C #define DDRSS_PI_189_DATA 0x01010101 #define DDRSS_PI_190_DATA 0x000C0C0A #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 #define DDRSS_PI_193_DATA 0x04000000 -#define DDRSS_PI_194_DATA 0x04020909 +#define DDRSS_PI_194_DATA 0x04020808 #define DDRSS_PI_195_DATA 0x04040204 #define DDRSS_PI_196_DATA 0x00090031 -#define DDRSS_PI_197_DATA 0x000F0037 -#define DDRSS_PI_198_DATA 0x000F0037 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 #define DDRSS_PI_199_DATA 0x01010101 -#define DDRSS_PI_200_DATA 0x0001000D -#define DDRSS_PI_201_DATA 0x000100A7 -#define DDRSS_PI_202_DATA 0x010000A7 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 #define DDRSS_PI_203_DATA 0x000E000E -#define DDRSS_PI_204_DATA 0x00A80100 -#define DDRSS_PI_205_DATA 0x010000A8 -#define DDRSS_PI_206_DATA 0x00A800A8 +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 #define DDRSS_PI_207_DATA 0x32103200 #define DDRSS_PI_208_DATA 0x01013210 #define DDRSS_PI_209_DATA 0x0A070601 -#define DDRSS_PI_210_DATA 0x0B08070D -#define DDRSS_PI_211_DATA 0x0B08070D +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D #define DDRSS_PI_212_DATA 0x000C000D #define DDRSS_PI_213_DATA 0x00001000 #define DDRSS_PI_214_DATA 0x00000C00 #define DDRSS_PI_215_DATA 0x00001000 #define DDRSS_PI_216_DATA 0x00000C00 #define DDRSS_PI_217_DATA 0x02001000 -#define DDRSS_PI_218_DATA 0x0015000D -#define DDRSS_PI_219_DATA 0x001500A7 -#define DDRSS_PI_220_DATA 0x000000A7 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 #define DDRSS_PI_221_DATA 0x00001900 #define DDRSS_PI_222_DATA 0x32000056 #define DDRSS_PI_223_DATA 0x06000101 #define DDRSS_PI_224_DATA 0x001D0204 -#define DDRSS_PI_225_DATA 0x32120059 +#define DDRSS_PI_225_DATA 0x32120058 #define DDRSS_PI_226_DATA 0x05000101 -#define DDRSS_PI_227_DATA 0x001D0409 -#define DDRSS_PI_228_DATA 0x32120059 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 #define DDRSS_PI_229_DATA 0x05000101 -#define DDRSS_PI_230_DATA 0x00000409 +#define DDRSS_PI_230_DATA 0x00000408 #define DDRSS_PI_231_DATA 0x05030900 #define DDRSS_PI_232_DATA 0x00040900 #define DDRSS_PI_233_DATA 0x0000062B #define DDRSS_PI_234_DATA 0x20010004 #define DDRSS_PI_235_DATA 0x0A0A0A03 -#define DDRSS_PI_236_DATA 0x0E090000 -#define DDRSS_PI_237_DATA 0x0E09000D -#define DDRSS_PI_238_DATA 0x00005244 -#define DDRSS_PI_239_DATA 0x2003001D -#define DDRSS_PI_240_DATA 0x0A0A0A0A -#define DDRSS_PI_241_DATA 0x0E090000 -#define DDRSS_PI_242_DATA 0x0E09000D -#define DDRSS_PI_243_DATA 0x00005244 -#define DDRSS_PI_244_DATA 0x2003001D -#define DDRSS_PI_245_DATA 0x0A0A0A0A +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C #define DDRSS_PI_246_DATA 0x00000000 #define DDRSS_PI_247_DATA 0x00000176 #define DDRSS_PI_248_DATA 0x00000E9C -#define DDRSS_PI_249_DATA 0x00001440 -#define DDRSS_PI_250_DATA 0x0000CA80 -#define DDRSS_PI_251_DATA 0x00001440 -#define DDRSS_PI_252_DATA 0x0000CA80 -#define DDRSS_PI_253_DATA 0x01030014 -#define DDRSS_PI_254_DATA 0x03030103 +#define DDRSS_PI_249_DATA 0x00001850 +#define DDRSS_PI_250_DATA 0x0000F320 +#define DDRSS_PI_251_DATA 0x00001850 +#define DDRSS_PI_252_DATA 0x0000F320 +#define DDRSS_PI_253_DATA 0x01360014 +#define DDRSS_PI_254_DATA 0x03030136 #define DDRSS_PI_255_DATA 0x00000003 #define DDRSS_PI_256_DATA 0x00000000 #define DDRSS_PI_257_DATA 0x05030503 @@ -701,23 +700,23 @@ #define DDRSS_PI_261_DATA 0x00000005 #define DDRSS_PI_262_DATA 0x00000064 #define DDRSS_PI_263_DATA 0x00000014 -#define DDRSS_PI_264_DATA 0x000208D6 +#define DDRSS_PI_264_DATA 0x00027100 #define DDRSS_PI_265_DATA 0x000186A0 #define DDRSS_PI_266_DATA 0x00000005 -#define DDRSS_PI_267_DATA 0x00000536 -#define DDRSS_PI_268_DATA 0x00000103 -#define DDRSS_PI_269_DATA 0x000208D6 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000136 +#define DDRSS_PI_269_DATA 0x00027100 #define DDRSS_PI_270_DATA 0x000186A0 #define DDRSS_PI_271_DATA 0x00000005 -#define DDRSS_PI_272_DATA 0x00000536 -#define DDRSS_PI_273_DATA 0x01000103 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000136 #define DDRSS_PI_274_DATA 0x00320040 #define DDRSS_PI_275_DATA 0x00010008 -#define DDRSS_PI_276_DATA 0x029B0040 -#define DDRSS_PI_277_DATA 0x00010014 -#define DDRSS_PI_278_DATA 0x029B0040 -#define DDRSS_PI_279_DATA 0x00000314 -#define DDRSS_PI_280_DATA 0x00280021 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 #define DDRSS_PI_281_DATA 0x03040404 #define DDRSS_PI_282_DATA 0x00000303 #define DDRSS_PI_283_DATA 0x02020101 @@ -745,7 +744,7 @@ #define DDRSS_PI_305_DATA 0x00000000 #define DDRSS_PI_306_DATA 0x00000024 #define DDRSS_PI_307_DATA 0x00000012 -#define DDRSS_PI_308_DATA 0x00000031 +#define DDRSS_PI_308_DATA 0x000000B1 #define DDRSS_PI_309_DATA 0x00000000 #define DDRSS_PI_310_DATA 0x00000000 #define DDRSS_PI_311_DATA 0x46000000 @@ -753,7 +752,7 @@ #define DDRSS_PI_313_DATA 0x00000000 #define DDRSS_PI_314_DATA 0x00000024 #define DDRSS_PI_315_DATA 0x00000012 -#define DDRSS_PI_316_DATA 0x00000031 +#define DDRSS_PI_316_DATA 0x000000B1 #define DDRSS_PI_317_DATA 0x00000000 #define DDRSS_PI_318_DATA 0x00000000 #define DDRSS_PI_319_DATA 0x46000000 @@ -769,7 +768,7 @@ #define DDRSS_PI_329_DATA 0x00000000 #define DDRSS_PI_330_DATA 0x00000024 #define DDRSS_PI_331_DATA 0x00000012 -#define DDRSS_PI_332_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x000000B1 #define DDRSS_PI_333_DATA 0x00000000 #define DDRSS_PI_334_DATA 0x00000000 #define DDRSS_PI_335_DATA 0x46000000 @@ -777,7 +776,7 @@ #define DDRSS_PI_337_DATA 0x00000000 #define DDRSS_PI_338_DATA 0x00000024 #define DDRSS_PI_339_DATA 0x00000012 -#define DDRSS_PI_340_DATA 0x00000031 +#define DDRSS_PI_340_DATA 0x000000B1 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x00000000 #define DDRSS_PI_343_DATA 0x46000000 @@ -869,29 +868,29 @@ #define DDRSS_PHY_84_DATA 0x00100010 #define DDRSS_PHY_85_DATA 0x00100010 #define DDRSS_PHY_86_DATA 0x00100010 -#define DDRSS_PHY_87_DATA 0x02000010 +#define DDRSS_PHY_87_DATA 0x02020010 #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 #define DDRSS_PHY_91_DATA 0x0000C0C0 -#define DDRSS_PHY_92_DATA 0x03040000 -#define DDRSS_PHY_93_DATA 0x00000403 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 #define DDRSS_PHY_94_DATA 0x42100010 #define DDRSS_PHY_95_DATA 0x010C053E -#define DDRSS_PHY_96_DATA 0x000F0C1A +#define DDRSS_PHY_96_DATA 0x000F0C1D #define DDRSS_PHY_97_DATA 0x01000140 -#define DDRSS_PHY_98_DATA 0x00660120 +#define DDRSS_PHY_98_DATA 0x007A0120 #define DDRSS_PHY_99_DATA 0x00000C00 -#define DDRSS_PHY_100_DATA 0x000001AA +#define DDRSS_PHY_100_DATA 0x000001CC #define DDRSS_PHY_101_DATA 0x20100200 -#define DDRSS_PHY_102_DATA 0x00000004 +#define DDRSS_PHY_102_DATA 0x00000005 #define DDRSS_PHY_103_DATA 0x76543210 #define DDRSS_PHY_104_DATA 0x00000008 -#define DDRSS_PHY_105_DATA 0x032A032A -#define DDRSS_PHY_106_DATA 0x032A032A -#define DDRSS_PHY_107_DATA 0x032A032A -#define DDRSS_PHY_108_DATA 0x032A032A -#define DDRSS_PHY_109_DATA 0x0000032A +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C #define DDRSS_PHY_110_DATA 0x00008000 #define DDRSS_PHY_111_DATA 0x00800080 #define DDRSS_PHY_112_DATA 0x00800080 @@ -901,7 +900,7 @@ #define DDRSS_PHY_116_DATA 0x00800080 #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 -#define DDRSS_PHY_119_DATA 0x01190080 +#define DDRSS_PHY_119_DATA 0x01800080 #define DDRSS_PHY_120_DATA 0x01A00001 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 @@ -1125,29 +1124,29 @@ #define DDRSS_PHY_340_DATA 0x00100010 #define DDRSS_PHY_341_DATA 0x00100010 #define DDRSS_PHY_342_DATA 0x00100010 -#define DDRSS_PHY_343_DATA 0x02000010 +#define DDRSS_PHY_343_DATA 0x02020010 #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 #define DDRSS_PHY_347_DATA 0x0000C0C0 -#define DDRSS_PHY_348_DATA 0x03040000 -#define DDRSS_PHY_349_DATA 0x00000403 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 #define DDRSS_PHY_350_DATA 0x42100010 #define DDRSS_PHY_351_DATA 0x010C053E -#define DDRSS_PHY_352_DATA 0x000F0C1A +#define DDRSS_PHY_352_DATA 0x000F0C1D #define DDRSS_PHY_353_DATA 0x01000140 -#define DDRSS_PHY_354_DATA 0x00660120 +#define DDRSS_PHY_354_DATA 0x007A0120 #define DDRSS_PHY_355_DATA 0x00000C00 -#define DDRSS_PHY_356_DATA 0x000001AA +#define DDRSS_PHY_356_DATA 0x000001CC #define DDRSS_PHY_357_DATA 0x20100200 -#define DDRSS_PHY_358_DATA 0x00000004 +#define DDRSS_PHY_358_DATA 0x00000005 #define DDRSS_PHY_359_DATA 0x76543210 #define DDRSS_PHY_360_DATA 0x00000008 -#define DDRSS_PHY_361_DATA 0x032A032A -#define DDRSS_PHY_362_DATA 0x032A032A -#define DDRSS_PHY_363_DATA 0x032A032A -#define DDRSS_PHY_364_DATA 0x032A032A -#define DDRSS_PHY_365_DATA 0x0000032A +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C #define DDRSS_PHY_366_DATA 0x00008000 #define DDRSS_PHY_367_DATA 0x00800080 #define DDRSS_PHY_368_DATA 0x00800080 @@ -1157,7 +1156,7 @@ #define DDRSS_PHY_372_DATA 0x00800080 #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 -#define DDRSS_PHY_375_DATA 0x01190080 +#define DDRSS_PHY_375_DATA 0x01800080 #define DDRSS_PHY_376_DATA 0x01A00001 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 @@ -1326,7 +1325,7 @@ #define DDRSS_PHY_541_DATA 0x003F0000 #define DDRSS_PHY_542_DATA 0x000F013F #define DDRSS_PHY_543_DATA 0x0000000F -#define DDRSS_PHY_544_DATA 0x000002CC +#define DDRSS_PHY_544_DATA 0x020002CC #define DDRSS_PHY_545_DATA 0x00030000 #define DDRSS_PHY_546_DATA 0x00000300 #define DDRSS_PHY_547_DATA 0x00000300 @@ -1582,7 +1581,7 @@ #define DDRSS_PHY_797_DATA 0x00000000 #define DDRSS_PHY_798_DATA 0x000F0000 #define DDRSS_PHY_799_DATA 0x0000000F -#define DDRSS_PHY_800_DATA 0x000002CC +#define DDRSS_PHY_800_DATA 0x020002CC #define DDRSS_PHY_801_DATA 0x00030000 #define DDRSS_PHY_802_DATA 0x00000300 #define DDRSS_PHY_803_DATA 0x00000300 @@ -1838,7 +1837,7 @@ #define DDRSS_PHY_1053_DATA 0x10000000 #define DDRSS_PHY_1054_DATA 0x000F0000 #define DDRSS_PHY_1055_DATA 0x0000000F -#define DDRSS_PHY_1056_DATA 0x000002CC +#define DDRSS_PHY_1056_DATA 0x020002CC #define DDRSS_PHY_1057_DATA 0x00030000 #define DDRSS_PHY_1058_DATA 0x00000300 #define DDRSS_PHY_1059_DATA 0x00000300 @@ -2116,7 +2115,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000076 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2154,7 +2153,7 @@ #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 #define DDRSS_PHY_1371_DATA 0x0001F7C0 -#define DDRSS_PHY_1372_DATA 0x00000002 +#define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 #define DDRSS_PHY_1375_DATA 0x03020000 @@ -2187,4 +2186,4 @@ #define DDRSS_PHY_1402_DATA 0x019900E0 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index cf3ba0e209c..97f44e220a3 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -9,7 +9,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/net/ti-dp83867.h> #include "k3-am642.dtsi" -#include "k3-am64-sk-lp4-1333MTs.dtsi" +#include "k3-am64-sk-lp4-1600MTs.dtsi" #include "k3-am64-ddr.dtsi" / { diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi index 37d4547b3e8..543f24c2f4f 100644 --- a/arch/arm/dts/stm32mp15-scmi.dtsi +++ b/arch/arm/dts/stm32mp15-scmi.dtsi @@ -103,7 +103,3 @@ /delete-node/ &clk_lse; /delete-node/ &clk_lsi; /delete-node/ &clk_csi; -/delete-node/ ®11; -/delete-node/ ®18; -/delete-node/ &usb33; -/delete-node/ &pwr_regulators; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 8a7156c93bf..b72a2f63f16 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -190,6 +190,21 @@ CLK_LPTIM45_LSE >; + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; @@ -208,7 +223,7 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ + /* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 5bed53e3fdb..6dee51dc1c2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -19,7 +19,6 @@ }; }; - ðernet0 { phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; @@ -102,6 +101,10 @@ hnp-srp-disable; }; +&vdd { + /delete-property/ regulator-always-on; +}; + &vdd_io { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi new file mode 100644 index 00000000000..5b051b8ac45 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15xx-dhcor-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + usb0 = &usbotg_hs; + }; + + config { + dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>; + }; +}; + +ðernet0 { + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_b { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_c { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_b { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; + hnp-srp-disable; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts new file mode 100644 index 00000000000..c9163e1c028 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP15xx DHCOR Testbench"; + compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vdd { + /delete-property/ regulator-always-on; + regulator-min-microvolt = <1200000>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 19f4221f876..25a288b0475 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -144,6 +144,21 @@ CLK_LPTIM45_LSE >; + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; @@ -162,7 +177,7 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts index 0a562b2cc5b..62e7aa587f8 100644 --- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts @@ -63,7 +63,7 @@ compatible = "gpio-keys-polled"; poll-interval = <20>; - left-joystick-left { + event-left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -71,7 +71,7 @@ gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ }; - left-joystick-right { + event-left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -79,7 +79,7 @@ gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ }; - left-joystick-up { + event-left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -87,7 +87,7 @@ gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ }; - left-joystick-down { + event-left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -95,7 +95,7 @@ gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ }; - right-joystick-left { + event-right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -103,7 +103,7 @@ gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ }; - right-joystick-right { + event-right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -111,7 +111,7 @@ gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ }; - right-joystick-up { + event-right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -119,7 +119,7 @@ gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ }; - right-joystick-down { + event-right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -127,7 +127,7 @@ gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ }; - dpad-left { + event-dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -135,7 +135,7 @@ gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ }; - dpad-right { + event-dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -143,7 +143,7 @@ gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ }; - dpad-up { + event-dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -151,7 +151,7 @@ gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ }; - dpad-down { + event-dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -159,49 +159,49 @@ gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ }; - x { + event-x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ }; - y { + event-y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ }; - a { + event-a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ }; - b { + event-b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ }; - select { + event-select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ }; - start { + event-start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ }; - top-left { + event-top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ }; - top-right { + event-top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts index 1ac82376bae..a332d61fd56 100644 --- a/arch/arm/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/dts/sun4i-a10-pcduino.dts @@ -77,19 +77,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-a64-amarula-relic.dts b/arch/arm/dts/sun50i-a64-amarula-relic.dts index c7bd73f35ed..ce8f6aa164e 100644 --- a/arch/arm/dts/sun50i-a64-amarula-relic.dts +++ b/arch/arm/dts/sun50i-a64-amarula-relic.dts @@ -58,7 +58,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index f7fe9fa50cb..bf66b640816 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -56,7 +56,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -355,7 +355,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo2>; vddio-supply = <®_dldo4>; diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts index 09b3c7fb82c..ffc3b4c7068 100644 --- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts +++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts @@ -43,7 +43,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index f3f8e177ab6..22d350249c1 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -58,6 +58,15 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; @@ -74,6 +83,10 @@ cpu-supply = <®_dcdc2>; }; +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -328,6 +341,23 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack Left", + "Microphone", "Microphone Jack Right", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP", + "ADCL", "Left ADC", + "ADCR", "Right ADC", + "Microphone Jack Left", "MBIAS", + "MIC1", "Microphone Jack Left", + "Microphone Jack Right", "MBIAS", + "MIC2", "Microphone Jack Right"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts index 8eee8051ac5..714a270a558 100644 --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -40,7 +40,7 @@ leds { compatible = "gpio-leds"; - status { + led-0 { label = "orangepi:green:status"; gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ }; @@ -71,7 +71,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -369,7 +369,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo2>; vddio-supply = <®_dldo4>; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts index 68b6ab4707c..c00c4c1e9e7 100644 --- a/arch/arm/dts/sun50i-a64-pinebook.dts +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -35,10 +35,10 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - lid_switch { + lid-switch { label = "Lid Switch"; gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ linux,input-type = <EV_SW>; diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts index fb65319a3bd..219f720b8b7 100644 --- a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts +++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts @@ -10,6 +10,10 @@ compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64"; }; +&codec_analog { + allwinner,internal-bias-resistor; +}; + &sgm3140 { enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts index 5e59d375217..723af64a9ce 100644 --- a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts +++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts @@ -29,6 +29,10 @@ default-brightness-level = <400>; }; +&codec_analog { + allwinner,internal-bias-resistor; +}; + &sgm3140 { enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts index 6668431dcb4..945afdb508d 100644 --- a/arch/arm/dts/sun50i-a64-teres-i.dts +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -197,6 +197,14 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dldo2>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; /* No dedicated supply-pin for this */ + vcc-pg-supply = <®_aldo2>; +}; + &pwm { status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 555bc92a6f8..b04f492c0f2 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -4,6 +4,7 @@ // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> #include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -660,7 +661,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -672,7 +673,8 @@ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -1224,7 +1226,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -1284,7 +1286,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts index 55b369534a0..a3e040da38a 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts @@ -52,10 +52,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index 1010c1b22d2..b5c1ff19b4c 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -54,10 +54,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + key-sw4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts index 74e0444af19..d7f8bad6bb9 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts @@ -48,10 +48,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + key-sw4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts index 9f12c05e21f..f1957bb1edb 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-3.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts @@ -86,7 +86,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; @@ -314,7 +314,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts index e8770858b5d..fb31dcb1cb6 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts @@ -13,7 +13,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; @@ -64,7 +64,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ diff --git a/arch/arm/dts/sun50i-h6-tanix.dtsi b/arch/arm/dts/sun50i-h6-tanix.dtsi index edb71e4a030..4903d635811 100644 --- a/arch/arm/dts/sun50i-h6-tanix.dtsi +++ b/arch/arm/dts/sun50i-h6-tanix.dtsi @@ -78,7 +78,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ }; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index 71a45a624da..afbbfc25269 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h6-ccu.h> #include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun50i-h6-ccu.h> @@ -237,7 +238,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h6-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -316,7 +317,7 @@ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -724,7 +725,7 @@ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_XHCI>, <&ccu CLK_BUS_XHCI>, - <&rtc 0>; + <&rtc CLK_OSC32K>; clock-names = "ref", "bus_early", "suspend"; resets = <&ccu RST_BUS_XHCI>; /* @@ -929,7 +930,7 @@ r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -958,7 +959,8 @@ reg = <0x07022000 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index e6de49f89e3..02893f3ac99 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -49,29 +49,8 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - status = "okay"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; }; -/* USB 2 & 3 are on headers only. */ - &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; @@ -97,14 +76,6 @@ status = "okay"; }; -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - &r_rsb { status = "okay"; @@ -181,14 +152,14 @@ reg_dcdca: dcdca { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1100000>; regulator-name = "vdd-cpu"; }; reg_dcdcc: dcdcc { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <990000>; regulator-name = "vdd-gpu-sys"; }; @@ -200,7 +171,7 @@ }; reg_dcdce: dcdce { - regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-eth-mmc"; @@ -213,8 +184,18 @@ }; }; +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_aldo1>; + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_aldo1>; + vcc-pi-supply = <®_aldo1>; +}; + &spi0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; flash@0 { #address-cells = <1>; @@ -230,13 +211,3 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts new file mode 100644 index 00000000000..6619db34714 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-x96-mate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2021 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "X96 Mate"; + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ir { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdce>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdce>; + vqmmc-supply = <®_bldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp305: pmic@745 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x745>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sys"; + }; + + /* Enabled by the Android BSP */ + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext"; + status = "disabled"; + }; + + /* Enabled by the Android BSP */ + reg_aldo3: aldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext2"; + status = "disabled"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Enabled by the Android BSP */ + reg_bldo2: bldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8-2"; + status = "disabled"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc2v5"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi index 2f71e853e96..622a1f7d164 100644 --- a/arch/arm/dts/sun50i-h616.dtsi +++ b/arch/arm/dts/sun50i-h616.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h616-ccu.h> #include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun50i-h616-ccu.h> #include <dt-bindings/reset/sun50i-h6-r-ccu.h> @@ -51,7 +52,23 @@ }; }; - osc24M: osc24M_clk { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 256 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { + reg = <0x0 0x40000000 0x0 0x40000>; + no-map; + }; + }; + + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -110,7 +127,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h616-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -135,7 +152,7 @@ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -161,7 +178,7 @@ function = "i2c3"; }; - ir_rx_pin: ir_rx_pin { + ir_rx_pin: ir-rx-pin { pins = "PH10"; function = "ir_rx"; }; @@ -174,6 +191,7 @@ bias-pull-up; }; + /omit-if-no-ref/ mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; @@ -191,17 +209,26 @@ bias-pull-up; }; + /omit-if-no-ref/ spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC3", "PC4"; + pins = "PC0", "PC2", "PC4"; function = "spi0"; }; + /omit-if-no-ref/ + spi0_cs0_pin: spi0-cs0-pin { + pins = "PC3"; + function = "spi0"; + }; + + /omit-if-no-ref/ spi1_pins: spi1-pins { pins = "PH6", "PH7", "PH8"; function = "spi1"; }; - spi1_cs_pin: spi1-cs-pin { + /omit-if-no-ref/ + spi1_cs0_pin: spi1-cs0-pin { pins = "PH5"; function = "spi1"; }; @@ -211,11 +238,13 @@ function = "uart0"; }; + /omit-if-no-ref/ uart1_pins: uart1-pins { pins = "PG6", "PG7"; function = "uart1"; }; + /omit-if-no-ref/ uart1_rts_cts_pins: uart1-rts-cts-pins { pins = "PG8", "PG9"; function = "uart1"; @@ -245,10 +274,10 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; status = "disabled"; + max-frequency = <150000000>; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-3_3v; - mmc-ddr-1_8v; cap-sdio-irq; #address-cells = <1>; #size-cells = <0>; @@ -266,10 +295,10 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; status = "disabled"; + max-frequency = <150000000>; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-3_3v; - mmc-ddr-1_8v; cap-sdio-irq; #address-cells = <1>; #size-cells = <0>; @@ -287,10 +316,10 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; status = "disabled"; + max-frequency = <150000000>; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-3_3v; - mmc-ddr-1_8v; cap-sdio-irq; #address-cells = <1>; #size-cells = <0>; @@ -364,6 +393,7 @@ i2c0: i2c@5002000 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002000 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -378,6 +408,7 @@ i2c1: i2c@5002400 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002400 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -390,6 +421,7 @@ i2c2: i2c@5002800 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002800 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -402,6 +434,7 @@ i2c3: i2c@5002c00 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002c00 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -414,6 +447,7 @@ i2c4: i2c@5003000 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05003000 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -432,8 +466,6 @@ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_SPI0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -447,224 +479,46 @@ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_SPI1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; emac0: ethernet@5020000 { - compatible = "allwinner,sun50i-h616-emac", + compatible = "allwinner,sun50i-h616-emac0", "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; reg = <0x05020000 0x10000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC0>; - reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC0>; clock-names = "stmmaceth"; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - emac1: ethernet@5030000 { - compatible = "allwinner,sun50i-h616-emac"; - syscon = <&syscon 1>; - reg = <0x05030000 0x10000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC1>; + resets = <&ccu RST_BUS_EMAC0>; reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC1>; - clock-names = "stmmaceth"; + syscon = <&syscon>; status = "disabled"; - mdio1: mdio { + mdio0: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@5100400 { - compatible = "allwinner,sun50i-h616-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x14>, - <0x05200800 0x14>, - <0x05310800 0x14>, - <0x05311800 0x14>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@5200000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05200000 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@5200400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05200400 0x100>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@5310000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05310000 0x100>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_BUS_EHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>, - <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@5310400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05310400 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc", - "allwinner,sun50i-h6-rtc"; + compatible = "allwinner,sun50i-h616-rtc"; reg = <0x07000000 0x400>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - clock-output-names = "osc32k", "osc32k-out", "iosc"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, + <&ccu CLK_PLL_SYSTEM_32K>; + clock-names = "bus", "hosc", + "pll-32k"; #clock-cells = <1>; }; r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h616-r-ccu"; - reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + reg = <0x07010000 0x210>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -674,14 +528,13 @@ r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h616-r-pinctrl"; reg = <0x07022000 0x400>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; + /omit-if-no-ref/ r_i2c_pins: r-i2c-pins { pins = "PL0", "PL1"; function = "s_i2c"; @@ -694,21 +547,22 @@ }; ir: ir@7040000 { - compatible = "allwinner,sun50i-h616-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx_pin>; - status = "disabled"; + compatible = "allwinner,sun50i-h616-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx_pin>; + status = "disabled"; }; r_i2c: i2c@7081400 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/sun5i-a13-licheepi-one.dts b/arch/arm/dts/sun5i-a13-licheepi-one.dts index 2ce361f8fed..3a6c4bd0a44 100644 --- a/arch/arm/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/dts/sun5i-a13-licheepi-one.dts @@ -67,18 +67,18 @@ compatible = "gpio-leds"; led-0 { - label ="licheepi:red:usr"; + label = "licheepi:red:usr"; gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; }; led-1 { - label ="licheepi:green:usr"; + label = "licheepi:green:usr"; gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; default-state = "on"; }; led-2 { - label ="licheepi:blue:usr"; + label = "licheepi:blue:usr"; gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi index d7d920e9e48..f6701ece7b7 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun6i-a31-ccu.h> / { @@ -598,7 +599,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -611,7 +612,8 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1316,7 +1318,7 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&rtc 0>, <&osc24M>, + clocks = <&rtc CLK_OSC32K>, <&osc24M>, <&ccu CLK_PLL_PERIPH>, <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; @@ -1351,7 +1353,7 @@ ir_clk: ir_clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&rtc 0>, <&osc24M>; + clocks = <&rtc CLK_OSC32K>, <&osc24M>; clock-output-names = "ir"; }; @@ -1381,9 +1383,8 @@ reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts index 4f8d55d3ba7..928b86a95f3 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -78,19 +78,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index a42fac676b3..06809c3a1f2 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -44,6 +44,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> @@ -329,7 +330,7 @@ ccu: clock@1c20000 { reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -339,7 +340,8 @@ /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -806,9 +808,8 @@ compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts index 51097c77a15..c2f22fc3381 100644..120000 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts @@ -1,73 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a23-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts index 51097c77a15..c2f22fc3381 100644..120000 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts @@ -1,73 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a23-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts index 9c5750c2561..4519fd791a8 100644..120000 --- a/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts +++ b/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts @@ -1,57 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a33-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts index 9c5750c2561..4519fd791a8 100644..120000 --- a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts @@ -1,57 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a33-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d5c7b7984d8..d729b7c705d 100644 --- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -47,10 +47,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -106,7 +106,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -181,7 +181,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index f19ed981da9..3706216ffb4 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -169,7 +169,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; }; diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts index cd9f655e4f9..27a0d51289d 100644 --- a/arch/arm/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts @@ -93,10 +93,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -125,7 +125,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; diff --git a/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts index ff0a7a952e0..f5c8ccc5b87 100644 --- a/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts +++ b/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts @@ -39,16 +39,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ }; - user { + key-user { label = "user"; linux,code = <BTN_0>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts index 8e7dfcffe1f..43641cb8239 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts @@ -37,10 +37,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - k1 { + key-0 { label = "k1"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ @@ -90,7 +90,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -151,7 +151,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts index cd3df12b657..9e1a33f94ca 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -127,7 +127,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts index 26e2e6172e0..42cd1131adf 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts @@ -46,7 +46,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -147,7 +147,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h3-nanopi.dtsi b/arch/arm/dts/sun8i-h3-nanopi.dtsi index fc45d5aaa67..cf8413fba6c 100644 --- a/arch/arm/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/dts/sun8i-h3-nanopi.dtsi @@ -73,11 +73,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - input-name = "k1"; - k1 { + key-0 { label = "k1"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index 9daffd90c12..f1f9dbead32 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -88,16 +88,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw2 { + switch-2 { label = "sw2"; linux,code = <BTN_1>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; }; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts index 6f9c97add54..305b34a321f 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts @@ -87,10 +87,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts index 4759ba3f298..59f6f6d5e7c 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index 90f75fa85e6..b96e015f54e 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts index 293016d081c..f97218e70c1 100644 --- a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts @@ -91,7 +91,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -283,7 +283,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo1>; vddio-supply = <®_aldo3>; diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index a6a1087a0c9..28197bbcb1d 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -113,6 +114,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/dts/sun8i-r40-cpu-opp.dtsi new file mode 100644 index 00000000000..649928b361a --- /dev/null +++ b/arch/arm/dts/sun8i-r40-cpu-opp.dtsi @@ -0,0 +1,52 @@ +/{ + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1000000 1000000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1160000 1160000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1240000 1240000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <2000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; diff --git a/arch/arm/dts/sun8i-r40-feta40i.dtsi b/arch/arm/dts/sun8i-r40-feta40i.dtsi index 265e0fa57a3..9f39b5a2bb3 100644 --- a/arch/arm/dts/sun8i-r40-feta40i.dtsi +++ b/arch/arm/dts/sun8i-r40-feta40i.dtsi @@ -5,6 +5,11 @@ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; &i2c0 { status = "okay"; diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 03d3e5f45a0..4ef26d8f534 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> #include <dt-bindings/clock/sun8i-tcon-top.h> @@ -84,24 +85,36 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; }; @@ -117,6 +130,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu_thermal: gpu-thermal { @@ -485,7 +522,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -504,7 +541,8 @@ compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1231,7 +1269,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; diff --git a/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts index 6931aaab238..9f472521f4a 100644 --- a/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts +++ b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts @@ -45,6 +45,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -88,6 +89,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index 084323d5c61..db194c606fd 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> #include <dt-bindings/clock/sun8i-de2.h> @@ -321,7 +322,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -342,7 +343,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 47954551f57..434871040ac 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -107,6 +108,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi index ce4fa6706d0..7d3f3300f43 100644 --- a/arch/arm/dts/sun9i-a80.dtsi +++ b/arch/arm/dts/sun9i-a80.dtsi @@ -1218,7 +1218,6 @@ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi index d03f5853ef7..e899d14f38c 100644 --- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi @@ -77,10 +77,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -101,7 +101,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -221,7 +221,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi index fc67e30fe21..60804b0e6c5 100644 --- a/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi +++ b/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi @@ -22,7 +22,7 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ post-power-on-delay-ms = <200>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -124,7 +124,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi index 6cea57e07f8..64391418609 100644 --- a/arch/arm/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -40,6 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> @@ -386,7 +387,7 @@ ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -397,7 +398,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -817,7 +819,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -876,7 +878,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -928,7 +930,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi index 9e14fe5fdcd..89731bb34c6 100644 --- a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi @@ -42,10 +42,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 8428322ed9a..0e30cc47f54 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -23,7 +23,6 @@ #include <mmc.h> #include <dm/root.h> -#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRLMMR_MCU_RST_CTRL 0x04518170 static void ctrl_mmr_unlock(void) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 14c37acbce7..227706e8dca 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -606,5 +606,9 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } + /* Default FIT boot on non-GP devices */ + if (get_device_type() != K3_DEVICE_TYPE_GP) + env_set("boot_fit", "1"); + return 0; } diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 9118d052042..278beb587f1 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -44,23 +44,6 @@ /* Backup Bootmode USB Config macros */ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism - * shared register definitions. The same registers are also used for - * PADCFG_MMR lock/kick-mechanism. - */ -#define CTRLMMR_LOCK_KICK0 0x1008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK1 0x100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index e06e1f9532f..6c9332e2bd9 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -7,12 +7,13 @@ #ifndef __ASM_ARCH_AM64_HARDWARE_H #define __ASM_ARCH_AM64_HARDWARE_H +#define PADCFG_MMR1_BASE 0x000f0000 +#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRL_MMR0_BASE 0x43000000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) - -#define PADCFG_MMR1_BASE 0xf0000 -#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 @@ -35,23 +36,6 @@ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 -/* - * The CTRL_MMR and PADCFG_MMR memory space is divided into several - * equally-spaced partitions, so defining the partition size allows us to - * determine register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00 /* Use Last 2K as Scratch pad */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index f533e22e061..f9f32918f7c 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -13,8 +13,10 @@ #endif #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) @@ -28,27 +30,6 @@ #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9 #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9) -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 028482b3b6d..d6d2cf6dc26 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -27,7 +27,7 @@ #endif /* Assuming these addresses and definitions stay common across K3 devices */ -#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 @@ -43,6 +43,23 @@ #define SYS_STATUS_SUB_TYPE_MASK (0xf << 8) #define SYS_STATUS_SUB_TYPE_VAL_FS 0xa +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + #define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT" struct rom_extended_boot_data { diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index b98f0a82f19..032cb2657ae 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -12,9 +12,11 @@ #include <linux/bitops.h> #endif +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00 diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 23dfe2e9e9d..e47f40eac25 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -12,9 +12,11 @@ #include <linux/bitops.h> #endif +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00 diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 12da8136f9e..dd0c7ba18f0 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -164,7 +164,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM 0 init failed: %d\n", ret); - ret = uclass_next_device(&dev); + ret = uclass_next_device_err(&dev); if (ret) panic("DRAM 1 init failed: %d\n", ret); } diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index d8d41ec5154..092588f4b5e 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -18,6 +18,7 @@ #include <mach/spl.h> #include <spl.h> #include <asm/arch/sys_proto.h> +#include <linux/dma-mapping.h> #include "common.h" @@ -47,7 +48,6 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) u32 image_size; int ret; - image_addr = (uintptr_t)*p_image; image_size = *p_size; if (!image_size) @@ -80,13 +80,12 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) return; } + /* Clean out image so it can be seen by system firmware */ + image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL); + debug("Authenticating image at address 0x%016llx\n", image_addr); debug("Authenticating image of size %d bytes\n", image_size); - flush_dcache_range((unsigned long)image_addr, - ALIGN((unsigned long)image_addr + image_size, - ARCH_DMA_MINALIGN)); - /* Authenticate image */ ret = proc_ops->proc_auth_boot_image(ti_sci, &image_addr, &image_size); if (ret) { @@ -94,10 +93,9 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) hang(); } + /* Invalidate any stale lines over data written by system firmware */ if (image_size) - invalidate_dcache_range((unsigned long)image_addr, - ALIGN((unsigned long)image_addr + - image_size, ARCH_DMA_MINALIGN)); + dma_unmap_single(image_addr, image_size, DMA_BIDIRECTIONAL); /* * The image_size returned may be 0 when the authentication process has diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 7f1b84e466d..f393ff91441 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -265,8 +265,8 @@ int arch_misc_init(void) struct udevice *dev; int ret; - ret = uclass_first_device(UCLASS_MISC, &dev); - if (ret || !dev) + ret = uclass_first_device_err(UCLASS_MISC, &dev); + if (ret) return ret; #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x index d516270292a..5bd9b53a5d8 100644 --- a/arch/arm/mach-stm32mp/Kconfig.15x +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -117,7 +117,7 @@ endif if DEBUG_UART config DEBUG_UART_BOARD_INIT - default y + default y if SPL # debug on UART4 by default config DEBUG_UART_BASE diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 57125761844..fc5d8bb3c19 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -185,6 +185,8 @@ config MACH_SUNIV select CPU_ARM926EJS select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SKIP_LOWLEVEL_INIT_ONLY + select SPL_SKIP_LOWLEVEL_INIT_ONLY config MACH_SUN4I bool "sun4i (Allwinner A10)" @@ -615,6 +617,18 @@ config SYS_BOARD config SYS_SOC default "sunxi" +config SUNXI_MINIMUM_DRAM_MB + int "minimum DRAM size" + default 32 if MACH_SUNIV + default 64 if MACH_SUN8I_V3S + default 256 + ---help--- + Minimum DRAM size expected on the board. Traditionally we assumed + 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM + we have smaller sizes, though, so that U-Boot's own load address and + the default payload addresses must be shifted down. + This is expected to be fixed by the SoC selection. + config UART0_PORT_F bool "UART0 on MicroSD breakout board" ---help--- @@ -998,7 +1012,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 62bb40b8c89..220ed80ba79 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); @@ -488,7 +492,7 @@ void reset_cpu(void) } #endif -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 925bf85f2d2..520f14e5155 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -78,7 +78,7 @@ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) #define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) -#ifdef CONFIG_MACH_SUN50I_H6 +#ifdef CONFIG_SUN50I_GEN_H6 #define CCM_SPI0_CLK (0x03001000 + 0x940) #else #define CCM_SPI0_CLK (0x01C20000 + 0xA0) @@ -97,7 +97,7 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5. + * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. */ static void spi0_pinmux_setup(unsigned int pin_function) { @@ -105,11 +105,14 @@ static void spi0_pinmux_setup(unsigned int pin_function) sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - /* All chips except H6 use PC1, and only H6 uses PC5. */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + /* All chips except H6 and H616 use PC1. */ + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - else + + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); /* Older generations use PC23 for CS, newer ones use PC3. */ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || @@ -122,7 +125,7 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6); + IS_ENABLED(CONFIG_SUN50I_GEN_H6); } static uintptr_t spi0_base_address(void) @@ -130,7 +133,7 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) return 0x01C05000; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) return 0x05010000; if (!is_sun6i_gen_spi() || @@ -148,14 +151,14 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); if (IS_ENABLED(CONFIG_MACH_SUNIV)) { @@ -202,11 +205,11 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -218,7 +221,7 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6)) pin_function = SUN50I_GPC_SPI0; else if (IS_ENABLED(CONFIG_MACH_SUNIV)) pin_function = SUNIV_GPC_SPI0; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32a90b83b5a..8f9578171d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,21 @@ config RISCV_ISA_C when building U-Boot, which results in compressed instructions in the U-Boot binary. +config RISCV_ISA_F + bool "Standard extension for Single-Precision Floating Point" + default y + help + Adds "F" to the ISA string passed to the compiler. + +config RISCV_ISA_D + bool "Standard extension for Double-Precision Floating Point" + depends on RISCV_ISA_F + default y + help + Adds "D" to the ISA string passed to the compiler and changes the + riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to + lp64d. + config RISCV_ISA_A def_bool y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 53d1194ffb6..4963b5109b2 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,15 +5,22 @@ ifeq ($(CONFIG_ARCH_RV64I),y) ARCH_BASE = rv64im - ABI = lp64 + ABI_BASE = lp64 endif ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im - ABI = ilp32 + ABI_BASE = ilp32 endif ifeq ($(CONFIG_RISCV_ISA_A),y) ARCH_A = a endif +ifeq ($(CONFIG_RISCV_ISA_F),y) + ARCH_F = f +endif +ifeq ($(CONFIG_RISCV_ISA_D),y) + ARCH_D = d + ABI_D = d +endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif @@ -24,7 +31,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) +ABI = $(ABI_BASE)$(ABI_D) # Newer binutils versions default to ISA spec version 20191213 which moves some # instructions from the I extension to the Zicsr and Zifencei extensions. diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 68514758a86..1eabcacd09d 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -27,8 +27,8 @@ /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) -#define ENABLE_HART_IPI (0x80808080) -#define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) +#define ENABLE_HART_IPI (0x01010101) +#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) DECLARE_GLOBAL_DATA_PTR; @@ -36,8 +36,9 @@ static int enable_ipi(int hart) { unsigned int en; - en = ENABLE_HART_IPI >> hart; + en = ENABLE_HART_IPI << hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); return 0; } diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index c1742f94de7..28f4a746fb6 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -50,8 +50,25 @@ int bootz_setup(ulong image, ulong *start, ulong *end) return ret; } +/* Subcommand: PREP */ +static int boot_prep_linux(struct bootm_headers *images) +{ + int ret; + + if (CONFIG_IS_ENABLED(LMB)) { + ret = image_setup_linux(images); + if (ret) + return ret; + } + + return 0; +} + int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images) { + if (flag & BOOTM_STATE_OS_PREP) + return boot_prep_linux(images); + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { bootstage_mark(BOOTSTAGE_ID_RUN_OS); printf("## Transferring control to Linux (at address %08lx)...\n", diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 2adcf4b242c..7877961451a 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -31,11 +31,9 @@ static int broadwell_init_cpu(void *ctx, struct event *event) int ret; /* Start up the LPC so we have serial */ - ret = uclass_first_device(UCLASS_LPC, &dev); + ret = uclass_first_device_err(UCLASS_LPC, &dev); if (ret) return ret; - if (!dev) - return -ENODEV; ret = cpu_set_flex_ratio_to_tdp_nominal(); if (ret) return ret; diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 96d05e2eb3a..8f489e6c651 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -61,11 +61,9 @@ int cpu_common_init(void) /* Early chipset init required before RAM init can work */ uclass_first_device(UCLASS_NORTHBRIDGE, &dev); - ret = uclass_first_device(UCLASS_LPC, &lpc); + ret = uclass_first_device_err(UCLASS_LPC, &lpc); if (ret) return ret; - if (!lpc) - return -ENODEV; /* Cause the SATA device to do its early init */ uclass_first_device(UCLASS_AHCI, &dev); diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index fd5e311b291..c93f245845d 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -160,11 +160,9 @@ static int ich6_pinctrl_probe(struct udevice *dev) u32 iobase = -1; debug("%s: start\n", __func__); - ret = uclass_first_device(UCLASS_PCH, &pch); + ret = uclass_first_device_err(UCLASS_PCH, &pch); if (ret) return ret; - if (!pch) - return -ENODEV; /* * Get the memory/io base address to configure every pins. diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 36f0dd4b0fd..63a966e0924 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -60,7 +60,7 @@ void *board_fdt_blob_setup(int *err) *err = 0; if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (gd->arch.firmware_fdt_addr) + if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) return (void *)(ulong)gd->arch.firmware_fdt_addr; } diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c index a723ba723c9..4606008c697 100644 --- a/board/atmel/common/mac_eeprom.c +++ b/board/atmel/common/mac_eeprom.c @@ -56,7 +56,7 @@ int at91_set_eth1addr(int offset) return ret; /* attempt to obtain a second eeprom device */ - ret = uclass_next_device(&dev); + ret = uclass_next_device_err(&dev); if (ret) return ret; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 2bc0d7b943a..8d8104ad4bd 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -547,7 +547,7 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv) if (!prop || !len) return -ENODEV; - if (!strstr(prop, "avenger96")) + if (!strstr(prop, "avenger96") && !strstr(prop, "dhcor-testbench")) return -EINVAL; /* Read out STPMIC1 NVM and determine default Buck3 voltage. */ @@ -564,18 +564,32 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv) bucks_vout >>= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(3); bucks_vout &= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK; - /* - * Avenger96 board comes in multiple regulator configurations: - * - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on - * boot and contains extra Enpirion EP53A8LQI DCDC converter which - * supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power. - * - rev.200L have Buck3 preconfigured to 1V8 operation and have no - * Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3. - */ - if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) - *uv = 2900000; - else - *uv = 1800000; + if (strstr(prop, "avenger96")) { + /* + * Avenger96 board comes in multiple regulator configurations: + * - rev.100 or rev.200 have Buck3 preconfigured to + * 3V3 operation on boot and contains extra Enpirion + * EP53A8LQI DCDC converter which supplies the IO. + * Reduce Buck3 voltage to 2V9 to not waste power. + * - rev.200L have Buck3 preconfigured to 1V8 operation + * and have no Enpirion EP53A8LQI DCDC anymore, the + * IO is supplied from Buck3. + */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 2900000; + else + *uv = 1800000; + } else { + /* Testbench always respects Buck3 NVM settings */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 3300000; + else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V0) + *uv = 3000000; + else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V8) + *uv = 1800000; + else /* STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 */ + *uv = 1200000; + } return 0; } @@ -595,6 +609,7 @@ static void board_init_regulator_av96(void) /* Adjust Buck3 per preconfigured PMIC voltage from NVM. */ regulator_set_value(rdev, uv); + regulator_set_enable(rdev, true); } static void board_init_regulator(void) diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its index de7dcb317f3..f9c1075616b 100644 --- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its +++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its @@ -18,7 +18,7 @@ fdt-1 { description = ".dtb"; - data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb"); + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-testbench.dtb"); type = "flat_dt"; arch = "arm"; compression = "none"; @@ -26,6 +26,14 @@ fdt-2 { description = ".dtb"; + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + }; + + fdt-3 { + description = ".dtb"; data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtb"); type = "flat_dt"; arch = "arm"; @@ -38,18 +46,25 @@ config-1 { /* DT+SoM+board model */ - description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1"; + description = "dh,stm32mp15xx-dhcor-testbench_somrev0_boardrev1"; firmware = "uboot"; fdt = "fdt-1"; }; config-2 { /* DT+SoM+board model */ - description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0"; + description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1"; firmware = "uboot"; fdt = "fdt-2"; }; + config-3 { + /* DT+SoM+board model */ + description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0"; + firmware = "uboot"; + fdt = "fdt-3"; + }; + /* Add 586-200..586-400 with fdt-2..fdt-4 here */ }; }; diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index d8c57e6bb05..f9883f18b0b 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -23,7 +23,7 @@ config SPL_TEXT_BASE config SPL_OPENSBI_LOAD_ADDR hex - default 0x81000000 + default 0x80100000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/board/engicam/stm32mp1/Makefile b/board/engicam/stm32mp1/Makefile index 65560df2900..155d33f9eec 100644 --- a/board/engicam/stm32mp1/Makefile +++ b/board/engicam/stm32mp1/Makefile @@ -8,3 +8,5 @@ obj-y += spl.o else obj-y += stm32mp1.o endif + +obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += ../../st/stm32mp1/debug_uart.o diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c index 3aa738b3faa..2b7779cc01d 100644 --- a/board/engicam/stm32mp1/spl.c +++ b/board/engicam/stm32mp1/spl.c @@ -6,7 +6,6 @@ */ #include <common.h> -#include <asm/io.h> /* board early initialisation in board_f: need to use global variable */ static u32 opp_voltage_mv __section(".data"); @@ -22,27 +21,3 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_DEBUG_UART_BOARD_INIT -void board_debug_uart_init(void) -{ -#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) - -#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) -#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) - - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); - -#define GPIOG_BASE 0x50008000 - /* GPIOG clock enable */ - writel(BIT(6), RCC_MP_AHB4ENSETR); - /* GPIO configuration for ST boards: Uart4 TX = G11 */ - writel(0xffbfffff, GPIOG_BASE + 0x00); - writel(0x00006000, GPIOG_BASE + 0x24); -#else - -#error("CONFIG_DEBUG_UART_BASE: not supported value") - -#endif -} -#endif diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c index 3d4a7e57fee..ba88401f13d 100644 --- a/board/gdsys/mpc8308/gazerbeam.c +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -49,8 +49,10 @@ int board_early_init_r(void) int mc = 0; int con = 0; - if (sysinfo_get(&sysinfo)) + if (sysinfo_get(&sysinfo)) { puts("Could not find sysinfo information device.\n"); + sysinfo = NULL; + } /* Initialize serdes */ uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, "serdes", &serdes); @@ -92,8 +94,10 @@ int checksysinfo(void) int mc = 0; int con = 0; - if (sysinfo_get(&sysinfo)) + if (sysinfo_get(&sysinfo)) { puts("Could not find sysinfo information device.\n"); + sysinfo = NULL; + } sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc); sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); @@ -130,8 +134,10 @@ int last_stage_init(void) struct udevice *tpm; int ret; - if (sysinfo_get(&sysinfo)) + if (sysinfo_get(&sysinfo)) { puts("Could not find sysinfo information device.\n"); + sysinfo = NULL; + } if (sysinfo) { int res = sysinfo_get_int(sysinfo, BOARD_HWVERSION, diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c index ce11eae59d5..7f61ef8b366 100644 --- a/board/intel/cougarcanyon2/cougarcanyon2.c +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -21,11 +21,9 @@ int board_early_init_f(void) struct udevice *pch; int ret; - ret = uclass_first_device(UCLASS_PCH, &pch); + ret = uclass_first_device_err(UCLASS_PCH, &pch); if (ret) return ret; - if (!pch) - return -ENODEV; /* Initialize LPC interface to turn on superio chipset decode range */ dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE); diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index 1cf8f8d8b2f..4b66e0a8614 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -7,7 +7,7 @@ #include <config.h> kernoffs: /* offset of kernel image from this address */ - .word KERNEL_OFFSET - (. - CONFIG_SYS_TEXT_BASE) + .word . - CONFIG_SYS_TEXT_BASE - KERNEL_OFFSET kernaddr: /* address of kernel after copying */ .word KERNEL_ADDRESS @@ -49,7 +49,7 @@ save_boot_params: /* r0 - start of kernel before */ adr r0, kernoffs /* r0 - current address of kernoffs section */ ldr r1, kernoffs /* r1 - offset of kernel image from kernoffs section */ - add r0, r0, r1 + sub r0, r0, r1 /* r3 - start of kernel after */ ldr r3, kernaddr diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile index 65560df2900..f2d720b67b3 100644 --- a/board/st/stm32mp1/Makefile +++ b/board/st/stm32mp1/Makefile @@ -8,3 +8,5 @@ obj-y += spl.o else obj-y += stm32mp1.o endif + +obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += debug_uart.o diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c new file mode 100644 index 00000000000..24e3f9f2201 --- /dev/null +++ b/board/st/stm32mp1/debug_uart.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#include <config.h> +#include <debug_uart.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <linux/bitops.h> + +#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) +#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) + +#define GPIOG_BASE 0x50008000 + +void board_debug_uart_init(void) +{ + if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) { + /* UART4 clock enable */ + setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + + /* GPIOG clock enable */ + writel(BIT(6), RCC_MP_AHB4ENSETR); + /* GPIO configuration for ST boards: Uart4 TX = G11 */ + writel(0xffbfffff, GPIOG_BASE + 0x00); + writel(0x00006000, GPIOG_BASE + 0x24); + } +} diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 8e4549a1b35..747ec7e445a 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -5,11 +5,7 @@ #include <config.h> #include <common.h> -#include <init.h> -#include <asm/io.h> #include <asm/arch/sys_proto.h> -#include <linux/bitops.h> -#include <linux/delay.h> #include "../common/stpmic1.h" /* board early initialisation in board_f: need to use global variable */ @@ -29,27 +25,3 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_DEBUG_UART_BOARD_INIT -void board_debug_uart_init(void) -{ -#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) - -#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) -#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) - - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); - -#define GPIOG_BASE 0x50008000 - /* GPIOG clock enable */ - writel(BIT(6), RCC_MP_AHB4ENSETR); - /* GPIO configuration for ST boards: Uart4 TX = G11 */ - writel(0xffbfffff, GPIOG_BASE + 0x00); - writel(0x00006000, GPIOG_BASE + 0x24); -#else - -#error("CONFIG_DEBUG_UART_BASE: not supported value") - -#endif -} -#endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 5a0b598a338..80e3f4be4b9 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -535,6 +535,11 @@ M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained F: configs/Wexler_TAB7200_defconfig +X96 MATE TV BOX +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/x96_mate_defconfig + YONES TOPTECH BD1078 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained diff --git a/boot/Kconfig b/boot/Kconfig index 6b3b8f072cb..45f86e946cd 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -499,8 +499,8 @@ config SYS_TEXT_BASE default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 default 0x81700000 if MACH_SUNIV default 0x2a000000 if MACH_SUN9I - default 0x42e00000 if MACH_SUN8I_V3S - default 0x4a000000 if ARCH_SUNXI + default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256 + default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64 hex "Text Base" help The address in memory that U-Boot will be running from, initially. diff --git a/boot/Makefile b/boot/Makefile index 67e335255f1..dd45d786f8c 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -47,5 +47,5 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o endif -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE) += vbe.o +obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE) += vbe.o vbe_fixup.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_SIMPLE) += vbe_simple.o diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 13ac69eb392..9d98bee4549 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -195,7 +195,7 @@ void bootdev_list(bool probe) printf("Seq Probed Status Uclass Name\n"); printf("--- ------ ------ -------- ------------------\n"); if (probe) - ret = uclass_first_device_err(UCLASS_BOOTDEV, &dev); + ret = uclass_first_device_check(UCLASS_BOOTDEV, &dev); else ret = uclass_find_first_device(UCLASS_BOOTDEV, &dev); for (i = 0; dev; i++) { @@ -204,7 +204,7 @@ void bootdev_list(bool probe) ret ? simple_itoa(ret) : "OK", dev_get_uclass_name(dev_get_parent(dev)), dev->name); if (probe) - ret = uclass_next_device_err(&dev); + ret = uclass_next_device_check(&dev); else ret = uclass_find_next_device(&dev); } diff --git a/boot/bootm.c b/boot/bootm.c index 5b20b418dba..a4c0870c0fe 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -790,7 +790,7 @@ int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, /* Check for unsupported subcommand. */ if (ret) { - puts("subcommand not supported\n"); + printf("subcommand failed (err=%d)\n", ret); return ret; } diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 884e089f2d8..b830a0ab418 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -186,24 +186,25 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) /* If fdt_high is set use it to select the relocation address */ fdt_high = env_get("fdt_high"); if (fdt_high) { - void *desired_addr = (void *)hextoul(fdt_high, NULL); + ulong desired_addr = hextoul(fdt_high, NULL); + ulong addr; - if (((ulong) desired_addr) == ~0UL) { + if (desired_addr == ~0UL) { /* All ones means use fdt in place */ of_start = fdt_blob; - lmb_reserve(lmb, (ulong)of_start, of_len); + lmb_reserve(lmb, map_to_sysmem(of_start), of_len); disable_relocation = 1; } else if (desired_addr) { - of_start = - (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, - (ulong)desired_addr); + addr = lmb_alloc_base(lmb, of_len, 0x1000, + desired_addr); + of_start = map_sysmem(addr, of_len); if (of_start == NULL) { puts("Failed using fdt_high value for Device Tree"); goto error; } } else { - of_start = - (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000); + addr = lmb_alloc(lmb, of_len, 0x1000); + of_start = map_sysmem(addr, of_len); } } else { mapsize = env_get_bootm_mapsize(); @@ -224,9 +225,8 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) * At least part of this DRAM bank is usable, try * using it for LMB allocation. */ - of_start = - (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, - start + usable); + of_start = map_sysmem((ulong)lmb_alloc_base(lmb, + of_len, 0x1000, start + usable), of_len); /* Allocation succeeded, use this block. */ if (of_start != NULL) break; @@ -665,15 +665,18 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, goto err; } } - if (CONFIG_IS_ENABLED(EVENT)) { + if (!of_live_active() && CONFIG_IS_ENABLED(EVENT)) { struct event_ft_fixup fixup; - fixup.tree = oftree_default(); + fixup.tree = oftree_from_fdt(blob); fixup.images = images; - ret = event_notify(EVT_FT_FIXUP, &fixup, sizeof(fixup)); - if (ret) { - printf("ERROR: fdt fixup event failed: %d\n", ret); - goto err; + if (oftree_valid(fixup.tree)) { + ret = event_notify(EVT_FT_FIXUP, &fixup, sizeof(fixup)); + if (ret) { + printf("ERROR: fdt fixup event failed: %d\n", + ret); + goto err; + } } } diff --git a/boot/vbe_fixup.c b/boot/vbe_fixup.c new file mode 100644 index 00000000000..53d88678c92 --- /dev/null +++ b/boot/vbe_fixup.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Verified Boot for Embedded (VBE) device tree fixup functions + * + * Copyright 2022 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY LOGC_BOOT + +#include <common.h> +#include <dm.h> +#include <event.h> +#include <image.h> +#include <malloc.h> +#include <rng.h> +#include <dm/ofnode.h> + +#define VBE_PREFIX "vbe," +#define VBE_PREFIX_LEN (sizeof(VBE_PREFIX) - 1) +#define VBE_ERR_STR_LEN 128 +#define VBE_MAX_RAND_SIZE 256 + +struct vbe_result { + int errnum; + char err_str[VBE_ERR_STR_LEN]; +}; + +typedef int (*vbe_req_func)(ofnode node, struct vbe_result *result); + +static int handle_random_req(ofnode node, int default_size, + struct vbe_result *result) +{ + char buf[VBE_MAX_RAND_SIZE]; + struct udevice *dev; + u32 size; + int ret; + + if (!IS_ENABLED(CONFIG_DM_RNG)) + return -ENOTSUPP; + + if (ofnode_read_u32(node, "vbe,size", &size)) { + if (!default_size) { + snprintf(result->err_str, VBE_ERR_STR_LEN, + "Missing vbe,size property"); + return log_msg_ret("byt", -EINVAL); + } + size = default_size; + } + if (size > VBE_MAX_RAND_SIZE) { + snprintf(result->err_str, VBE_ERR_STR_LEN, + "vbe,size %#x exceeds max size %#x", size, + VBE_MAX_RAND_SIZE); + return log_msg_ret("siz", -E2BIG); + } + ret = uclass_first_device_err(UCLASS_RNG, &dev); + if (ret) { + snprintf(result->err_str, VBE_ERR_STR_LEN, + "Cannot find random-number device (err=%d)", ret); + return log_msg_ret("wr", ret); + } + ret = dm_rng_read(dev, buf, size); + if (ret) { + snprintf(result->err_str, VBE_ERR_STR_LEN, + "Failed to read random-number device (err=%d)", ret); + return log_msg_ret("rd", ret); + } + ret = ofnode_write_prop(node, "data", buf, size, true); + if (ret) + return log_msg_ret("wr", -EINVAL); + + return 0; +} + +static int vbe_req_random_seed(ofnode node, struct vbe_result *result) +{ + return handle_random_req(node, 0, result); +} + +static int vbe_req_aslr_move(ofnode node, struct vbe_result *result) +{ + return -ENOTSUPP; +} + +static int vbe_req_aslr_rand(ofnode node, struct vbe_result *result) +{ + return handle_random_req(node, 4, result); +} + +static int vbe_req_efi_runtime_rand(ofnode node, struct vbe_result *result) +{ + return handle_random_req(node, 4, result); +} + +static struct vbe_req { + const char *compat; + vbe_req_func func; +} vbe_reqs[] = { + /* address space layout randomization - move the OS in memory */ + { "aslr-move", vbe_req_aslr_move }, + + /* provide random data for address space layout randomization */ + { "aslr-rand", vbe_req_aslr_rand }, + + /* provide random data for EFI-runtime-services address */ + { "efi-runtime-rand", vbe_req_efi_runtime_rand }, + + /* generate random data bytes to see the OS's rand generator */ + { "random-rand", vbe_req_random_seed }, + +}; + +static int vbe_process_request(ofnode node, struct vbe_result *result) +{ + const char *compat, *req_name; + int i; + + compat = ofnode_read_string(node, "compatible"); + if (!compat) + return 0; + + if (strlen(compat) <= VBE_PREFIX_LEN || + strncmp(compat, VBE_PREFIX, VBE_PREFIX_LEN)) + return -EINVAL; + + req_name = compat + VBE_PREFIX_LEN; /* drop "vbe," prefix */ + for (i = 0; i < ARRAY_SIZE(vbe_reqs); i++) { + if (!strcmp(vbe_reqs[i].compat, req_name)) { + int ret; + + ret = vbe_reqs[i].func(node, result); + if (ret) + return log_msg_ret("req", ret); + return 0; + } + } + snprintf(result->err_str, VBE_ERR_STR_LEN, "Unknown request: %s", + req_name); + + return -ENOTSUPP; +} + +/** + * bootmeth_vbe_ft_fixup() - Process VBE OS requests and do device tree fixups + * + * If there are no images provided, this does nothing and returns 0. + * + * @ctx: Context for event + * @event: Event to process + * @return 0 if OK, -ve on error + */ +static int bootmeth_vbe_ft_fixup(void *ctx, struct event *event) +{ + const struct event_ft_fixup *fixup = &event->data.ft_fixup; + const struct bootm_headers *images = fixup->images; + ofnode parent, dest_parent, root, node; + oftree fit; + + if (!images || !images->fit_hdr_os) + return 0; + + /* Get the image node with requests in it */ + log_debug("fit=%p, noffset=%d\n", images->fit_hdr_os, + images->fit_noffset_os); + fit = oftree_from_fdt(images->fit_hdr_os); + root = oftree_root(fit); + if (of_live_active()) { + log_warning("Cannot fix up live tree\n"); + return 0; + } + if (!ofnode_valid(root)) + return log_msg_ret("rt", -EINVAL); + parent = noffset_to_ofnode(root, images->fit_noffset_os); + if (!ofnode_valid(parent)) + return log_msg_ret("img", -EINVAL); + dest_parent = oftree_path(fixup->tree, "/chosen"); + if (!ofnode_valid(dest_parent)) + return log_msg_ret("dst", -EINVAL); + + ofnode_for_each_subnode(node, parent) { + const char *name = ofnode_get_name(node); + struct vbe_result result; + ofnode dest; + int ret; + + log_debug("copy subnode: %s\n", name); + ret = ofnode_add_subnode(dest_parent, name, &dest); + if (ret && ret != -EEXIST) + return log_msg_ret("add", ret); + ret = ofnode_copy_props(node, dest); + if (ret) + return log_msg_ret("cp", ret); + + *result.err_str = '\0'; + ret = vbe_process_request(dest, &result); + if (ret) { + result.errnum = ret; + log_err("Failed to process VBE request %s (err=%d)\n", + ofnode_get_name(dest), ret); + if (*result.err_str) { + char *msg = strdup(result.err_str); + + if (!msg) + return log_msg_ret("msg", -ENOMEM); + ret = ofnode_write_string(dest, "vbe,error", + msg); + if (ret) { + free(msg); + return log_msg_ret("str", -ENOMEM); + } + } + if (result.errnum) { + ret = ofnode_write_u32(dest, "vbe,errnum", + result.errnum); + if (ret) + return log_msg_ret("num", -ENOMEM); + if (result.errnum != -ENOTSUPP) + return log_msg_ret("pro", + result.errnum); + if (result.errnum == -ENOTSUPP && + ofnode_read_bool(dest, "vbe,required")) { + log_err("Cannot handle required request: %s\n", + ofnode_get_name(dest)); + return log_msg_ret("req", + result.errnum); + } + } + } + } + + return 0; +} +EVENT_SPY(EVT_FT_FIXUP, bootmeth_vbe_ft_fixup); diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c index 61b6322ebe2..076b650c25a 100644 --- a/boot/vbe_simple.c +++ b/boot/vbe_simple.c @@ -6,6 +6,8 @@ * Written by Simon Glass <sjg@chromium.org> */ +#define LOG_CATEGORY LOGC_BOOT + #include <common.h> #include <log.h> #include <memalign.h> @@ -199,17 +201,17 @@ int vbe_simple_fixup_node(ofnode node, struct simple_state *state) version = strdup(state->fw_version); if (!version) - return log_msg_ret("ver", -ENOMEM); + return log_msg_ret("dup", -ENOMEM); ret = ofnode_write_string(node, "cur-version", version); if (ret) return log_msg_ret("ver", ret); ret = ofnode_write_u32(node, "cur-vernum", state->fw_vernum); if (ret) - return log_msg_ret("ver", ret); + return log_msg_ret("num", ret); ret = ofnode_write_string(node, "bootloader-version", version_string); if (ret) - return log_msg_ret("fix", ret); + return log_msg_ret("bl", ret); return 0; } @@ -233,7 +235,7 @@ static int bootmeth_vbe_simple_ft_fixup(void *ctx, struct event *event) */ for (vbe_find_first_device(&dev); dev; vbe_find_next_device(&dev)) { struct simple_state state; - ofnode node; + ofnode node, subnode; int ret; if (strcmp("vbe_simple", dev->driver->name)) @@ -243,8 +245,8 @@ static int bootmeth_vbe_simple_ft_fixup(void *ctx, struct event *event) node = oftree_path(tree, "/chosen/fwupd"); if (!ofnode_valid(node)) continue; - node = ofnode_find_subnode(node, dev->name); - if (!ofnode_valid(node)) + subnode = ofnode_find_subnode(node, dev->name); + if (!ofnode_valid(subnode)) continue; log_debug("Fixing up: %s\n", dev->name); @@ -255,7 +257,7 @@ static int bootmeth_vbe_simple_ft_fixup(void *ctx, struct event *event) if (ret) return log_msg_ret("read", ret); - ret = vbe_simple_fixup_node(node, &state); + ret = vbe_simple_fixup_node(subnode, &state); if (ret) return log_msg_ret("fix", ret); } diff --git a/cmd/Kconfig b/cmd/Kconfig index 49247a41c00..16030e34a12 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -86,6 +86,7 @@ config SYS_CBSIZE config SYS_PBSIZE int "Buffer size for console output" + default 1024 if ARCH_SUNXI default 1044 config SYS_XTRACE diff --git a/cmd/adc.c b/cmd/adc.c index 1c5d3e10a39..a739d9e4641 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -12,23 +12,19 @@ static int do_adc_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct udevice *dev; - int ret; + int ret, err; - ret = uclass_first_device_err(UCLASS_ADC, &dev); - if (ret) { - printf("No available ADC device\n"); - return CMD_RET_FAILURE; - } + ret = err = uclass_first_device_check(UCLASS_ADC, &dev); - do { - printf("- %s\n", dev->name); + while (dev) { + printf("- %s status: %i\n", dev->name, ret); - ret = uclass_next_device(&dev); + ret = uclass_next_device_check(&dev); if (ret) - return CMD_RET_FAILURE; - } while (dev); + err = ret; + } - return CMD_RET_SUCCESS; + return err ? CMD_RET_FAILURE : CMD_RET_SUCCESS; } static int do_adc_info(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/bootm.c b/cmd/bootm.c index d764a27002d..37c2af96e08 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -111,7 +111,7 @@ static int do_bootm_subcommand(struct cmd_tbl *cmdtp, int flag, int argc, bootm_get_addr(argc, argv) + image_load_offset); #endif - return ret; + return ret ? CMD_RET_FAILURE : 0; } /*******************************************************************/ @@ -120,6 +120,9 @@ static int do_bootm_subcommand(struct cmd_tbl *cmdtp, int flag, int argc, int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + int states; + int ret; + #ifdef CONFIG_NEEDS_MANUAL_RELOC static int relocated = 0; @@ -152,17 +155,17 @@ int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return do_bootm_subcommand(cmdtp, flag, argc, argv); } - return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | - BOOTM_STATE_FINDOS | BOOTM_STATE_PRE_LOAD | BOOTM_STATE_FINDOTHER | - BOOTM_STATE_LOADOS | -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH - BOOTM_STATE_RAMDISK | -#endif -#if defined(CONFIG_PPC) || defined(CONFIG_MIPS) - BOOTM_STATE_OS_CMDLINE | -#endif + states = BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_PRE_LOAD | + BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS | BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | - BOOTM_STATE_OS_GO, &images, 1); + BOOTM_STATE_OS_GO; + if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH)) + states |= BOOTM_STATE_RAMDISK; + if (IS_ENABLED(CONFIG_PPC) || IS_ENABLED(CONFIG_MIPS)) + states |= BOOTM_STATE_OS_CMDLINE; + ret = do_bootm_states(cmdtp, flag, argc, argv, states, &images, 1); + + return ret ? CMD_RET_FAILURE : 0; } int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd) diff --git a/cmd/demo.c b/cmd/demo.c index 571f562ec68..ebd5a241c36 100644 --- a/cmd/demo.c +++ b/cmd/demo.c @@ -64,20 +64,23 @@ static int do_demo_light(struct cmd_tbl *cmdtp, int flag, int argc, int do_demo_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct udevice *dev; - int i, ret; + int i, ret, err = 0; puts("Demo uclass entries:\n"); - for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev); + for (i = 0, ret = uclass_first_device_check(UCLASS_DEMO, &dev); dev; - ret = uclass_next_device(&dev)) { - printf("entry %d - instance %08x, ops %08x, plat %08x\n", + ret = uclass_next_device_check(&dev)) { + printf("entry %d - instance %08x, ops %08x, plat %08x, status %i\n", i++, (uint)map_to_sysmem(dev), (uint)map_to_sysmem(dev->driver->ops), - (uint)map_to_sysmem(dev_get_plat(dev))); + (uint)map_to_sysmem(dev_get_plat(dev)), + ret); + if (ret) + err = ret; } - return cmd_process_error(cmdtp, ret); + return cmd_process_error(cmdtp, err); } static struct cmd_tbl demo_commands[] = { diff --git a/cmd/fdt.c b/cmd/fdt.c index 6fbd9205d38..4b2dcfec863 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -40,6 +40,7 @@ void set_working_fdt_addr(ulong addr) { void *buf; + printf("Working FDT set to %lx\n", addr); buf = map_sysmem(addr, 0); working_fdt = buf; env_set_hex("fdtaddr", addr); diff --git a/cmd/gpio.c b/cmd/gpio.c index 53e9ce666f9..f4565982ecd 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -77,17 +77,24 @@ static int do_gpio_status(bool all, const char *gpio_name) struct udevice *dev; int banklen; int flags; - int ret; + int ret, err = 0; flags = 0; if (gpio_name && !*gpio_name) gpio_name = NULL; - for (ret = uclass_first_device(UCLASS_GPIO, &dev); + for (ret = uclass_first_device_check(UCLASS_GPIO, &dev); dev; - ret = uclass_next_device(&dev)) { + ret = uclass_next_device_check(&dev)) { const char *bank_name; int num_bits; + if (ret) { + printf("GPIO device %s probe error %i\n", + dev->name, ret); + err = ret; + continue; + } + flags |= FLAG_SHOW_BANK; if (all) flags |= FLAG_SHOW_ALL; @@ -120,7 +127,7 @@ static int do_gpio_status(bool all, const char *gpio_name) flags |= FLAG_SHOW_NEWLINE; } - return ret; + return err; } #endif diff --git a/cmd/pmic.c b/cmd/pmic.c index 0cb44d07409..49a405fa297 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -51,25 +51,26 @@ static int do_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct udevice *dev; - int ret; + int ret, err = 0; printf("| %-*.*s| %-*.*s| %s @ %s\n", LIMIT_DEV, LIMIT_DEV, "Name", LIMIT_PARENT, LIMIT_PARENT, "Parent name", "Parent uclass", "seq"); - for (ret = uclass_first_device(UCLASS_PMIC, &dev); dev; - ret = uclass_next_device(&dev)) { + for (ret = uclass_first_device_check(UCLASS_PMIC, &dev); dev; + ret = uclass_next_device_check(&dev)) { if (ret) - continue; + err = ret; - printf("| %-*.*s| %-*.*s| %s @ %d\n", + printf("| %-*.*s| %-*.*s| %s @ %d | status: %i\n", LIMIT_DEV, LIMIT_DEV, dev->name, LIMIT_PARENT, LIMIT_PARENT, dev->parent->name, - dev_get_uclass_name(dev->parent), dev_seq(dev->parent)); + dev_get_uclass_name(dev->parent), dev_seq(dev->parent), + ret); } - if (ret) + if (err) return CMD_RET_FAILURE; return CMD_RET_SUCCESS; diff --git a/cmd/regulator.c b/cmd/regulator.c index 60a70036d68..ed4996dbd2b 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -205,7 +205,7 @@ static void do_status_detail(struct udevice *dev, constraint(" * mode id:", mode, mode_name); } -static void do_status_line(struct udevice *dev) +static void do_status_line(struct udevice *dev, int status) { struct dm_regulator_uclass_plat *pdata; int current, value, mode; @@ -231,6 +231,7 @@ static void do_status_line(struct udevice *dev) printf("%-10s", mode_name); else printf("%-10s", "-"); + printf(" %i", status); printf("\n"); } @@ -250,11 +251,11 @@ static int do_status(struct cmd_tbl *cmdtp, int flag, int argc, } /* Show all of them in a list, probing them as needed */ - printf("%-20s %-10s %10s %10s %-10s\n", "Name", "Enabled", "uV", "mA", - "Mode"); - for (ret = uclass_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_next_device(&dev)) - do_status_line(dev); + printf("%-20s %-10s %10s %10s %-10s %s\n", "Name", "Enabled", "uV", "mA", + "Mode", "Status"); + for (ret = uclass_first_device_check(UCLASS_REGULATOR, &dev); dev; + ret = uclass_next_device_check(&dev)) + do_status_line(dev, ret); return CMD_RET_SUCCESS; } diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 522f502435b..6f2cad4e7ed 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -30,15 +30,15 @@ static struct sbi_imp implementations[] = { }; static struct sbi_ext extensions[] = { - { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" }, - { SBI_EXT_0_1_CONSOLE_PUTCHAR, "sbi_console_putchar" }, - { SBI_EXT_0_1_CONSOLE_GETCHAR, "sbi_console_getchar" }, - { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" }, - { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" }, - { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" }, - { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" }, - { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" }, - { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" }, + { SBI_EXT_0_1_SET_TIMER, "Set Timer" }, + { SBI_EXT_0_1_CONSOLE_PUTCHAR, "Console Putchar" }, + { SBI_EXT_0_1_CONSOLE_GETCHAR, "Console Getchar" }, + { SBI_EXT_0_1_CLEAR_IPI, "Clear IPI" }, + { SBI_EXT_0_1_SEND_IPI, "Send IPI" }, + { SBI_EXT_0_1_REMOTE_FENCE_I, "Remote FENCE.I" }, + { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "Remote SFENCE.VMA" }, + { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "Remote SFENCE.VMA with ASID" }, + { SBI_EXT_0_1_SHUTDOWN, "System Shutdown" }, { SBI_EXT_BASE, "SBI Base Functionality" }, { SBI_EXT_TIME, "Timer Extension" }, { SBI_EXT_IPI, "IPI Extension" }, @@ -56,8 +56,11 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, long mvendorid, marchid, mimpid; ret = sbi_get_spec_version(); - if (ret >= 0) - printf("SBI %ld.%ld", ret >> 24, ret & 0xffffff); + if (ret < 0) { + printf("No SBI 0.2+\n"); + return CMD_RET_FAILURE; + } + printf("SBI %ld.%ld", ret >> 24, ret & 0xffffff); impl_id = sbi_get_impl_id(); if (impl_id >= 0) { for (i = 0; i < ARRAY_SIZE(implementations); ++i) { @@ -74,6 +77,7 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, vers >> 16, vers & 0xffff); break; case 3: /* KVM */ + case 4: /* RustSBI */ printf("%ld.%ld.%ld", vers >> 16, (vers >> 8) & 0xff, diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f2422d28f9e..b1b9e09dc8f 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -81,6 +81,7 @@ config SPL_MAX_SIZE default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000 default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616 + default 0xbfa0 if MACH_SUN50I_H616 default 0x7000 if RCAR_GEN3 default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 default 0x10000 if ASPEED_AST2600 @@ -353,6 +354,11 @@ config SPL_STACK default 0x946bb8 if ARCH_MX7 default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB + default 0x118000 if MACH_SUN50I_H6 + default 0x58000 if MACH_SUN50I_H616 + default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 + default 0x18000 if MACH_SUN9I + default 0x8000 if ARCH_SUNXI help Address of the start of the stack SPL will use before SDRAM is initialized. diff --git a/common/stdio.c b/common/stdio.c index 13083842cbd..e316a355fae 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -314,7 +314,6 @@ int stdio_init_tables(void) int stdio_add_devices(void) { struct udevice *dev; - struct uclass *uc; int ret; if (IS_ENABLED(CONFIG_DM_KEYBOARD)) { @@ -324,24 +323,18 @@ int stdio_add_devices(void) * have a list of input devices to start up in the stdin * environment variable. That work probably makes more sense * when stdio itself is converted to driver model. - * - * TODO(sjg@chromium.org): Convert changing - * uclass_first_device() etc. to return the device even on - * error. Then we could use that here. */ - ret = uclass_get(UCLASS_KEYBOARD, &uc); - if (ret) - return ret; /* * Don't report errors to the caller - assume that they are * non-fatal */ - uclass_foreach_dev(dev, uc) { - ret = device_probe(dev); + for (ret = uclass_first_device_check(UCLASS_KEYBOARD, &dev); + dev; + ret = uclass_next_device_check(&dev)) { if (ret) - printf("Failed to probe keyboard '%s'\n", - dev->name); + printf("%s: Failed to probe keyboard '%s' (ret=%d)\n", + __func__, dev->name, ret); } } #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) @@ -361,13 +354,14 @@ int stdio_add_devices(void) int ret; if (!IS_ENABLED(CONFIG_SYS_CONSOLE_IS_IN_ENV)) { - for (ret = uclass_first_device(UCLASS_VIDEO, &vdev); - vdev; - ret = uclass_next_device(&vdev)) - ; - if (ret) - printf("%s: Video device failed (ret=%d)\n", - __func__, ret); + for (ret = uclass_first_device_check(UCLASS_VIDEO, + &vdev); + vdev; + ret = uclass_next_device_check(&vdev)) { + if (ret) + printf("%s: Failed to probe video device '%s' (ret=%d)\n", + __func__, vdev->name, ret); + } } if (IS_ENABLED(CONFIG_SPLASH_SCREEN) && IS_ENABLED(CONFIG_CMD_BMP)) diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 26a921279b5..6727932f7fe 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -11,9 +11,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 7e9b92ee5ee..99f57857517 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,9 +9,7 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 625a331e445..f9d17b19500 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,8 +13,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 5e0396c150f..8c9043559bd 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_DFU_RAM=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index b5802818ec3..bccadcc7b4a 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -13,9 +13,7 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index de4f6311f2d..0a9de5ee671 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,9 +11,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index ebb3a02b824..38daf33b95b 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -9,9 +9,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index c8802435b41..d73e64c4605 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -11,9 +11,7 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index f4496412456..8a6bb885e9c 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,9 +12,7 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 67b47f51f1b..5de6c2d9a9e 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -12,9 +12,7 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index e02d67da5e7..6e9bdc27d98 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -13,9 +13,7 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 317a1e695d8..e0517459ee6 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -12,9 +12,7 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index c9eec1f8879..351a454339b 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -16,7 +16,5 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 8cd38f7905b..9a18af8c6e1 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 68707ed3e95..7bf3dfcd8a5 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 703df186b27..7d81f12f766 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,9 +8,7 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index a8d236eaf9d..4c7154b04c4 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,9 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index be5be9ae2fb..18ee81b6378 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -12,9 +12,7 @@ CONFIG_USB2_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 053ba137652..6c2a1f630e8 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,9 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 6a07f26c02c..bad38a66568 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -10,8 +10,6 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 36f9bf8b32e..94fd74754ea 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,9 +11,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 40d2c5b668a..cd9bdbfd36f 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -7,9 +7,7 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y CONFIG_CHIP_DIP_SCAN=y -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 90168010bb8..29179601907 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -5,9 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0" diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 49be3fc4a2d..1cd39d498f2 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index b59d1786e6e..02b3e69584f 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 24b55bfa8cc..270bd7d351a 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -15,8 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PM1" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 315c52f3448..ab5e53fb62e 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -8,9 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 928299e8a51..04ed79afb6d 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -12,7 +12,5 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y -CONFIG_SPL_STACK=0x18000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 49eb0186953..c017b126b8c 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -8,9 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 62668df01ec..c85468e5827 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -13,9 +13,7 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 8119b8b9cf6..13f958977be 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -16,8 +16,6 @@ CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index 0187b896f87..a9bbe8bcffa 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -16,9 +16,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 6570b97ca4c..fc1f26b7a99 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 3afe4c56ae4..24e8b5be1b5 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -9,8 +9,6 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 8bf7d1efba6..482e0fb7a83 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 1a161555842..99df9cff24f 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -8,9 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 3627e4dd3af..f97dc131f28 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -10,9 +10,7 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 2e0b0b71e14..9815348badd 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -5,6 +5,4 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 # CONFIG_NETDEVICES is not set diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 41ed46a7b5a..e3e30a49490 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -10,9 +10,7 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 44a3901e22d..1fda0db4c9d 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -8,9 +8,7 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 279641551b3..49dcfa098ee 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,9 +6,7 @@ CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 4e678bdf051..3ed962d7cd9 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,9 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 7a4b224bf2a..071169fd298 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,9 +10,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index bb820fd0a39..e77b0072923 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -13,8 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB_MUSB_HOST=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 1584778dc74..3c5312d8824 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index acd751b19c8..c697d286dc1 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index eb3e7988005..f5b6d908cdc 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -8,9 +8,7 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 48dad606b88..2b9bca13d08 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index ce962395a25..77cb464c932 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,9 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 2e6d5dd4604..b07dbbde2e4 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -9,9 +9,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index b84a2aebe20..be6dd417545 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 3709a11ec03..c5d1f40df39 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -12,7 +12,5 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y -CONFIG_SPL_STACK=0x18000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 76b6b7d2bce..e8bc1485766 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,9 +6,7 @@ CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 5b1a1d40614..b66023418ae 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,8 +9,6 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y # CONFIG_MMC is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index ba976f8f5f3..c89a9a1f9dd 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -12,9 +12,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 720e9e5df4c..8757dcb461c 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 2d33331f3d3..238b0073e79 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -10,8 +10,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index fcee14b5462..4eb5300b046 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -13,8 +13,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index c080a247105..aba95270eb2 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 9760f9fdf4a..5116fab52d7 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -16,8 +16,6 @@ CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_INITIAL_USB_SCAN_DELAY=500 diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index 749bf1cff9d..bb62ae9a7a9 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -12,5 +12,3 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x18000 -CONFIG_SYS_PBSIZE=1024 diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 4e6652db18f..b021b0a8865 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,9 +20,7 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index f63d18c327f..101ce57aa44 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,9 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index c9d22534d5c..f401ac74ef4 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -12,9 +12,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index ab919c0795a..e0687bf887d 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,9 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 1117e147cc1..f1ceb8b5527 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,9 +19,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index ef30aee8281..6701ecce2fe 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -16,7 +16,5 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index afa0c24b688..8ec9eb3e9c2 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -6,9 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index ccb5abc9845..16cef18beef 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -6,9 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index 72f97cee4de..ae44b66d109 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -7,9 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 66c444fc750..b89dd8ea62b 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,9 +9,7 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 290e9c17e21..0fbb619d623 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -9,9 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index e6b8f0f8a3f..588eea2a27d 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -9,9 +9,7 @@ CONFIG_USB1_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index d0981f6481a..26ced59fb02 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index a68742e9d6a..fb6c945919a 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -7,9 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index 6a3594c0938..ac3f8f5ab8b 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -6,5 +6,3 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 36aa80a09ba..5463b046fdb 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -7,9 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index 2c440e44f5d..42925eabcb0 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -8,9 +8,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x118000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index 4065e64d523..6206d909003 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -6,7 +6,5 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=567 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index f17083310a2..5d3636e34e8 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 CONFIG_USB_MUSB_HOST=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index a3917eaf179..e1067b66eec 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index c737cdb4d99..60910c3ce35 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index 73121f2f4eb..a3b43dffc63 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -8,7 +8,4 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 7cdb6c56755..599eeb96b4f 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -17,8 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index c81f0f6c5eb..1a5fe06bbe1 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 8af0b3c3332..29f965200e1 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -11,8 +11,6 @@ CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 29cea180201..257dd89af45 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -7,9 +7,7 @@ CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 8b6936497fd..436e3a8c209 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index a05876a18f3..6978f8b0aab 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 3a9f30877b0..2c8ecb51de0 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,9 +13,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 664745c9f13..9a90252dbd7 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -17,8 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=5 diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index e50db015cdc..c759d7e2357 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -17,9 +17,7 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_UNZIP=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index dae6b23a936..f81120b1197 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 0382a4a0541..3ade9fea824 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index f3e374c2e34..d5d2dc32c93 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,9 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index c392fc2bb87..bd6c45bd661 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 81a1c9940fd..4485f930236 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,9 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index a4a828c70a3..1769256b7d1 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -15,8 +15,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 5fce5836c9c..0ff666b2ee5 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -8,9 +8,7 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index ca995568024..8725fe64cdc 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 7ca312c8fbc..5275fdc36da 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 13ff7582124..96274019499 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -6,9 +6,6 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index 75280ee1e3b..cb7ffb4d7da 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -7,9 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index f42747e9466..c3aa4b10617 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -7,9 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index a9776bbcace..12a43c1ec10 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -1,7 +1,4 @@ CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y -CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" CONFIG_SPL=y @@ -10,8 +7,6 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y CONFIG_SPI=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 11e3dfcf4ba..0e4cdc44670 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -9,8 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 3ce7e5f1d68..21f7a6e535d 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,9 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 0fd8d3adbd2..416565e5af2 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 942911bddba..965a9cd5c4b 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,9 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 226ccaa12ff..70fc257eebd 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index 47a6b7804e3..dc2dbd62900 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -5,7 +5,5 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index c71d721f743..37b7817d869 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -8,8 +8,6 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 6fedf056ff7..95dd56aa04c 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -7,9 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index b83b6a3499d..806d95c1cc7 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -7,7 +7,5 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index f8377535e97..c0255196384 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -7,8 +7,6 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 3f834b756df..924ff38f17c 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -9,9 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig index a0cf8ff0442..27cf172d72a 100644 --- a/configs/nanopi_r1s_h5_defconfig +++ b/configs/nanopi_r1s_h5_defconfig @@ -9,9 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 1cd8e9f2b68..7ce63ba665d 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -10,9 +10,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index e18b8610847..7aaa5190b3a 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -7,9 +7,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index dbca66d1429..ebecf49ebda 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -8,9 +8,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x118000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_PHY_SUN50I_USB3=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 14c88062812..75c97d6b897 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -7,8 +7,5 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x118000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index c7174170dbf..96bbd1bab6f 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -5,7 +5,5 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 112ff5e5b6a..1064b4a39de 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index a4336332fc7..55a8b003fb5 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -7,8 +7,5 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x118000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index d0cad2a7461..777af8c60ea 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -8,10 +8,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 28107ad5f7a..905ff7b1271 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -5,9 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index 30638679bc6..f845138153d 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -6,9 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 85b25ddd167..138a6a72b8c 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -7,9 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index dff0a2fd6e9..76de72aa228 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -9,9 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 690a5f195b6..95a82e20f3e 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -7,9 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index e15069c048e..4496aa4a45c 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -8,8 +8,6 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 7a9ca8e88a8..3b78ad7e52d 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,9 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index cad7a7bb064..ceef51b3db6 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -9,12 +9,9 @@ CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y CONFIG_MACH_SUN50I_H616=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_MAX_SIZE=0xbfa0 -CONFIG_SPL_STACK=0x58000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index b6de0b9aa26..f7f3bfbcc41 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -8,8 +8,6 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 02f70ccf0c0..9583d24c8d6 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -9,9 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig index b2d4f3f8e07..55a251374a1 100644 --- a/configs/orangepi_zero_plus2_h3_defconfig +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -8,8 +8,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index 15520955f5e..f3ecf35eee1 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,9 +7,6 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index 14e9b455feb..d56c4504b6a 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -11,8 +11,6 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 3f9ea1e329f..7e7c2d79104 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,9 +10,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 62608f93bdb..f42f4e5923a 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -6,9 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 2f511c80517..09a4275f0e7 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -11,9 +11,6 @@ CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x118000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 982f68143b9..26918dd3875 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -8,9 +8,6 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 531cf0f83b6..28e347b4d95 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -8,9 +8,7 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 905b47d29e6..9d39204a439 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -10,9 +10,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig index e20d20a2fd5..0cc24146b39 100644 --- a/configs/pinetab_defconfig +++ b/configs/pinetab_defconfig @@ -8,6 +8,3 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 74ffaf1d011..17fffeb1e26 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index 10057ade9a5..e542b711132 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index 523de63fc27..a62c9f8fa37 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 83981d3ac74..f269b8a5889 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index 11d208a34a0..dda1a0c51f6 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index c848e62d73c..7925677d30e 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index ee5654185b1..f3335f9d233 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -16,8 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index f5adbd3686c..8875a09b2c9 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,9 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index fdd7b351189..9d8da25648d 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -11,7 +11,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_BOOTMETH_VBE is not set CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y @@ -84,6 +83,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y +CONFIG_OFNODE_MULTI_TREE=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y CONFIG_AXI=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 55116f72d0d..fbbef7a9f9a 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -11,9 +11,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index f47e70be44a..67e238af3a1 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -79,6 +79,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=nor0" diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 02cce50691e..a630713f926 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -77,6 +77,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=nor0" diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index 59315cdb05d..a3b1d76d8bb 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -9,8 +9,6 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index b77c4e7a3cb..3fee7c2e50c 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,9 +11,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y -CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig index 84dbf106d49..0390347415c 100644 --- a/configs/tanix_tx6_defconfig +++ b/configs/tanix_tx6_defconfig @@ -8,6 +8,3 @@ CONFIG_DRAM_CLK=648 CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x118000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 3dd9252a742..b3c2e69d6cd 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -13,8 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 6f202dc8a43..e7de85eb506 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -9,9 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" -CONFIG_SPL_STACK=0x54000 -CONFIG_SYS_PBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig new file mode 100644 index 00000000000..4276f4f543b --- /dev/null +++ b/configs/x96_mate_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-x96-mate" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y +CONFIG_MACH_SUN50I_H616=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig index 7d45440c0cc..11f3715e6dc 100644 --- a/configs/zeropi_defconfig +++ b/configs/zeropi_defconfig @@ -8,8 +8,6 @@ CONFIG_MACPWR="PD6" # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_STACK=0x8000 -CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/disk/part_efi.c b/disk/part_efi.c index ad94504ed90..26738a57d5d 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -264,20 +264,19 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, /* "part" argument must be at least 1 */ if (part < 1) { - printf("%s: Invalid Argument(s)\n", __func__); - return -1; + log_debug("Invalid Argument(s)\n"); + return -EINVAL; } /* This function validates AND fills in the GPT header and PTE */ if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) - return -1; + return -EINVAL; if (part > le32_to_cpu(gpt_head->num_partition_entries) || !is_pte_valid(&gpt_pte[part - 1])) { - debug("%s: *** ERROR: Invalid partition number %d ***\n", - __func__, part); + log_debug("*** ERROR: Invalid partition number %d ***\n", part); free(gpt_pte); - return -1; + return -EPERM; } /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */ @@ -300,8 +299,8 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, info->type_guid, UUID_STR_FORMAT_GUID); #endif - debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__, - info->start, info->size, info->name); + log_debug("start 0x" LBAF ", size 0x" LBAF ", name %s\n", info->start, + info->size, info->name); /* Remember to free pte */ free(gpt_pte); diff --git a/doc/develop/driver-model/livetree.rst b/doc/develop/driver-model/livetree.rst index 55aa3eac929..579eef5ca9f 100644 --- a/doc/develop/driver-model/livetree.rst +++ b/doc/develop/driver-model/livetree.rst @@ -255,7 +255,7 @@ So long as OF_LIVE is disabled, it is possible to do fixups using the ofnode interface. The OF_LIVE support required addition of the flattening step at the end. -See dm_test_ofnode_root() for some examples. The ofnode_path_root() function +See dm_test_ofnode_root() for some examples. The oftree_from_fdt() function causes a flat device tree to be 'registered' such that it can be used by the ofnode interface. diff --git a/doc/develop/vbe.rst b/doc/develop/vbe.rst index 8f147fd9360..cca193c8fd4 100644 --- a/doc/develop/vbe.rst +++ b/doc/develop/vbe.rst @@ -19,8 +19,9 @@ listing methods and getting the status for a method. For a detailed overview of VBE, see vbe-intro_. A fuller description of bootflows is at vbe-bootflows_ and the firmware-update mechanism is described at -vbe-fwupdate_. +vbe-fwupdate_. VBE OS requests are described at vbe-osrequests_. .. _vbe-intro: https://docs.google.com/document/d/e/2PACX-1vQjXLPWMIyVktaTMf8edHZYDrEvMYD_iNzIj1FgPmKF37fpglAC47Tt5cvPBC5fvTdoK-GA5Zv1wifo/pub .. _vbe-bootflows: https://docs.google.com/document/d/e/2PACX-1vR0OzhuyRJQ8kdeOibS3xB1rVFy3J4M_QKTM5-3vPIBNcdvR0W8EXu9ymG-yWfqthzWoM4JUNhqwydN/pub .. _vbe-fwupdate: https://docs.google.com/document/d/e/2PACX-1vTnlIL17vVbl6TVoTHWYMED0bme7oHHNk-g5VGxblbPiKIdGDALE1HKId8Go5f0g1eziLsv4h9bocbk/pub +.. _vbe-osrequests: https://docs.google.com/document/d/e/2PACX-1vTHhxX7WSZe68i9rAkW-DHdx6koU-jxYHhamLhZn9GQ9QT2_epSBosMV1_r7yPHOXZccx71rF_t0PXL/pub diff --git a/doc/usage/cmd/fdt.rst b/doc/usage/cmd/fdt.rst index 07fed732e45..36b8230877c 100644 --- a/doc/usage/cmd/fdt.rst +++ b/doc/usage/cmd/fdt.rst @@ -60,6 +60,7 @@ The second word shows the size of the FDT. Now set the working FDT to that address and expand it to 0xf000 in size:: => fdt addr 10000 f000 + Working FDT set to 10000 => md 10000 4 00010000: edfe0dd0 00f00000 78000000 7c270000 ...........x..'| diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 7d12d5413f1..bcc14a684be 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -593,11 +593,9 @@ int blk_find_next(enum blk_flag_t flags, struct udevice **devp) int blk_first_device_err(enum blk_flag_t flags, struct udevice **devp) { - int ret; - - for (ret = uclass_first_device_err(UCLASS_BLK, devp); - !ret; - ret = uclass_next_device_err(devp)) { + for (uclass_first_device(UCLASS_BLK, devp); + *devp; + uclass_next_device(devp)) { if (!blk_flags_check(*devp, flags)) return 0; } @@ -607,11 +605,9 @@ int blk_first_device_err(enum blk_flag_t flags, struct udevice **devp) int blk_next_device_err(enum blk_flag_t flags, struct udevice **devp) { - int ret; - - for (ret = uclass_next_device_err(devp); - !ret; - ret = uclass_next_device_err(devp)) { + for (uclass_next_device(devp); + *devp; + uclass_next_device(devp)) { if (!blk_flags_check(*devp, flags)) return 0; } diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf794..2f9635524cf 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -505,7 +505,7 @@ struct clk *clk_get_parent(struct clk *clk) return pclk; } -long long clk_get_parent_rate(struct clk *clk) +ulong clk_get_parent_rate(struct clk *clk) { const struct clk_ops *ops; struct clk *pclk; @@ -544,6 +544,19 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_get_priv(struct clk *clk, struct clk **clkp) +{ + *clkp = clk; + + /* get private clock struct associated to the provided clock */ + if (CONFIG_IS_ENABLED(CLK_CCF)) { + /* Take id 0 as a non-valid clk, such as dummy */ + if (clk->id) + clk_get_by_id(clk->id, clkp); + } +} + +/* clean cache, called with private clock struct */ static void clk_clean_rate_cache(struct clk *clk) { struct udevice *child_dev; @@ -563,6 +576,7 @@ static void clk_clean_rate_cache(struct clk *clk) ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; + struct clk *clkp; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); if (!clk_valid(clk)) @@ -572,8 +586,10 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* get private clock struct used for cache */ + clk_get_priv(clk, &clkp); /* Clean up cached rates for us and all child clocks */ - clk_clean_rate_cache(clk); + clk_clean_rate_cache(clkp); return ops->set_rate(clk, rate); } diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index 1961efaa5e7..f7d36963f85 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -846,7 +846,7 @@ again: error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); /* The lower 16 bits are spurious */ - error = abs((error - BIT(32))) >> 16; + error = abs64((error - BIT_ULL(32))) >> 16; if (error < best_error) { best->r = r; diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 8d2aaf5b843..09b97cf57a2 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table; #define RK3036_PLLCON1_DSMPD_SHIFT 12 #define RK3036_PLLCON2_FRAC_MASK 0xffffff #define RK3036_PLLCON2_FRAC_SHIFT 0 -#define RK3036_PLLCON1_PWRDOWN_SHIT 13 +#define RK3036_PLLCON1_PWRDOWN_SHIFT 13 #define MHZ 1000000 #define KHZ 1000 @@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power down */ rk_setreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); rk_clrsetreg(base + pll->con_offset, (RK3036_PLLCON0_POSTDIV1_MASK | @@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power Up */ rk_clrreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); /* waiting for pll lock */ while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 5ccbf9abb8a..e33bb9d798d 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -4,6 +4,8 @@ * Written by Simon Glass <sjg@chromium.org> */ +#define LOG_CATEGORY LOGC_DM + #include <common.h> #include <dm.h> #include <errno.h> @@ -37,6 +39,22 @@ struct regmap_field { DECLARE_GLOBAL_DATA_PTR; /** + * do_range_check() - Control whether range checks are done + * + * Returns: true to do range checks, false to skip + * + * This is used to reduce code size on SPL where range checks are known not to + * be needed + * + * Add this to the top of the file to enable them: #define LOG_DEBUG + */ +static inline bool do_range_check(void) +{ + return _LOG_DEBUG || !IS_ENABLED(CONFIG_SPL); + +} + +/** * regmap_alloc() - Allocate a regmap with a given number of ranges. * * @count: Number of ranges to be allocated for the regmap. @@ -391,7 +409,7 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, struct regmap_range *range; void *ptr; - if (range_num >= map->range_count) { + if (do_range_check() && range_num >= map->range_count) { debug("%s: range index %d larger than range count\n", __func__, range_num); return -ERANGE; @@ -399,7 +417,8 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, range = &map->ranges[range_num]; offset <<= map->reg_offset_shift; - if (offset + val_len > range->size || offset + val_len < offset) { + if (do_range_check() && + (offset + val_len > range->size || offset + val_len < offset)) { debug("%s: offset/size combination invalid\n", __func__); return -ERANGE; } diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 08d9ed82de2..b7d11bdd23a 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -586,19 +586,6 @@ int uclass_first_device(enum uclass_id id, struct udevice **devp) return uclass_get_device_tail(dev, ret, devp); } -int uclass_first_device_err(enum uclass_id id, struct udevice **devp) -{ - int ret; - - ret = uclass_first_device(id, devp); - if (ret) - return ret; - else if (!*devp) - return -ENODEV; - - return 0; -} - int uclass_next_device(struct udevice **devp) { struct udevice *dev = *devp; @@ -611,11 +598,24 @@ int uclass_next_device(struct udevice **devp) return uclass_get_device_tail(dev, ret, devp); } +int uclass_first_device_err(enum uclass_id id, struct udevice **devp) +{ + int ret; + + ret = uclass_first_device_check(id, devp); + if (ret) + return ret; + else if (!*devp) + return -ENODEV; + + return 0; +} + int uclass_next_device_err(struct udevice **devp) { int ret; - ret = uclass_next_device(devp); + ret = uclass_next_device_check(devp); if (ret) return ret; else if (!*devp) @@ -799,20 +799,18 @@ int uclass_pre_remove_device(struct udevice *dev) int uclass_probe_all(enum uclass_id id) { struct udevice *dev; - int ret; + int ret, err; - ret = uclass_first_device(id, &dev); - if (ret || !dev) - return ret; + err = uclass_first_device_check(id, &dev); /* Scanning uclass to probe all devices */ while (dev) { - ret = uclass_next_device(&dev); + ret = uclass_next_device_check(&dev); if (ret) - return ret; + err = ret; } - return 0; + return err; } int uclass_id_count(enum uclass_id id) diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 71e5900d70e..a7548325265 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -20,25 +20,13 @@ DECLARE_GLOBAL_DATA_PTR; int cpu_probe_all(void) { - struct udevice *cpu; - int ret; + int ret = uclass_probe_all(UCLASS_CPU); - ret = uclass_first_device(UCLASS_CPU, &cpu); if (ret) { - debug("%s: No CPU found (err = %d)\n", __func__, ret); - return ret; - } - - while (cpu) { - ret = uclass_next_device(&cpu); - if (ret) { - debug("%s: Error while probing CPU (err = %d)\n", - __func__, ret); - return ret; - } + debug("%s: Error while probing CPUs (err = %d %s)\n", + __func__, ret, errno_str(ret)); } - - return 0; + return ret; } int cpu_is_current(struct udevice *cpu) diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index 012609bb537..81dbb4da107 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -19,6 +19,7 @@ #include <asm/cache.h> #include <dm/read.h> #include <dma-uclass.h> +#include <linux/dma-mapping.h> #include <dt-structs.h> #include <errno.h> @@ -235,6 +236,8 @@ int dma_memcpy(void *dst, void *src, size_t len) { struct udevice *dev; const struct dma_ops *ops; + dma_addr_t destination; + dma_addr_t source; int ret; ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev); @@ -245,11 +248,17 @@ int dma_memcpy(void *dst, void *src, size_t len) if (!ops->transfer) return -ENOSYS; - /* Invalidate the area, so no writeback into the RAM races with DMA */ - invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + - roundup(len, ARCH_DMA_MINALIGN)); + /* Clean the areas, so no writeback into the RAM races with DMA */ + destination = dma_map_single(dst, len, DMA_FROM_DEVICE); + source = dma_map_single(src, len, DMA_TO_DEVICE); - return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len); + ret = ops->transfer(dev, DMA_MEM_TO_MEM, destination, source, len); + + /* Clean+Invalidate the areas after, so we can see DMA'd data */ + dma_unmap_single(destination, len, DMA_FROM_DEVICE); + dma_unmap_single(source, len, DMA_TO_DEVICE); + + return ret; } UCLASS_DRIVER(dma) = { diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c index aebf3eef966..2b8259a35b4 100644 --- a/drivers/dma/sandbox-dma-test.c +++ b/drivers/dma/sandbox-dma-test.c @@ -39,9 +39,9 @@ struct sandbox_dma_dev { }; static int sandbox_dma_transfer(struct udevice *dev, int direction, - void *dst, void *src, size_t len) + dma_addr_t dst, dma_addr_t src, size_t len) { - memcpy(dst, src, len); + memcpy((void *)dst, (void *)src, len); return 0; } diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index ec3dc62d2f3..1ad3b92dbf4 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -13,6 +13,7 @@ #include <common.h> #include <dm.h> #include <dma-uclass.h> +#include <linux/dma-mapping.h> #include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> @@ -395,7 +396,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) } void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, - void *dst, void *src, size_t len, size_t s_len) + dma_addr_t dst, dma_addr_t src, size_t len, size_t s_len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -483,12 +484,14 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, } void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, - void *dst, u8 val, size_t len) + dma_addr_t dst, u8 val, size_t len) { int xfer_len; int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535; + dma_addr_t source; memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer)); + source = dma_map_single(edma_fill_buffer, len, DMA_TO_DEVICE); while (len) { xfer_len = len; @@ -496,11 +499,13 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, xfer_len = max_xfer; __edma3_transfer(edma3_base_addr, edma_slot_num, dst, - edma_fill_buffer, xfer_len, + source, xfer_len, EDMA_FILL_BUFFER_SIZE); len -= xfer_len; dst += xfer_len; } + + dma_unmap_single(source, len, DMA_FROM_DEVICE); } #ifndef CONFIG_DMA @@ -508,19 +513,33 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len) { - __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len); + /* Clean the areas, so no writeback into the RAM races with DMA */ + dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE); + dma_addr_t source = dma_map_single(src, len, DMA_TO_DEVICE); + + __edma3_transfer(edma3_base_addr, edma_slot_num, destination, source, len, len); + + /* Clean+Invalidate the areas after, so we can see DMA'd data */ + dma_unmap_single(destination, len, DMA_FROM_DEVICE); + dma_unmap_single(source, len, DMA_TO_DEVICE); } void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, u8 val, size_t len) { - __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len); + /* Clean the area, so no writeback into the RAM races with DMA */ + dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE); + + __edma3_fill(edma3_base_addr, edma_slot_num, destination, val, len); + + /* Clean+Invalidate the area after, so we can see DMA'd data */ + dma_unmap_single(destination, len, DMA_FROM_DEVICE); } #else -static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst, - void *src, size_t len) +static int ti_edma3_transfer(struct udevice *dev, int direction, + dma_addr_t dst, dma_addr_t src, size_t len) { struct ti_edma3_priv *priv = dev_get_priv(dev); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 1a9197bfc82..d92b9644369 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2305,7 +2305,7 @@ err_res_free: } static int udma_transfer(struct udevice *dev, int direction, - void *dst, void *src, size_t len) + dma_addr_t dst, dma_addr_t src, size_t len) { struct udma_dev *ud = dev_get_priv(dev); /* Channel0 is reserved for memcpy */ @@ -2326,7 +2326,7 @@ static int udma_transfer(struct udevice *dev, int direction, if (ret) return ret; - udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len); + udma_prep_dma_memcpy(uc, dst, src, len); udma_start(uc); udma_poll_completion(uc, &paddr); udma_stop(uc); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index b2f4a4e7219..a2595d19e7f 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -644,7 +644,7 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) return 0; - ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev); + ret = uclass_first_device_err(UCLASS_THERMAL, &thermal_dev); if (ret) { printf("Couldn't get thermal device for tuning\n"); return ret; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 058b2f6359d..5cff81ac443 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1217,7 +1217,7 @@ static int skip_to_next_device(struct udevice *bus, struct udevice **devp) * Scan through all the PCI controllers. On x86 there will only be one * but that is not necessarily true on other hardware. */ - do { + while (bus) { device_find_first_child(bus, &dev); if (dev) { *devp = dev; @@ -1226,7 +1226,7 @@ static int skip_to_next_device(struct udevice *bus, struct udevice **devp) ret = uclass_next_device(&bus); if (ret) return ret; - } while (bus); + } return 0; } diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index fb6b6cf3fff..6646b15d410 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -69,14 +69,20 @@ static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); static const struct reg_field pll1_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 29, 29); +static const struct reg_field pll1_refclk_mux_sel_2 = + REG_FIELD(WIZ_SERDES_RST, 22, 23); static const struct reg_field pll0_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 28, 28); +static const struct reg_field pll0_refclk_mux_sel_2 = + REG_FIELD(WIZ_SERDES_RST, 28, 29); static const struct reg_field refclk_dig_sel_16g = REG_FIELD(WIZ_SERDES_RST, 24, 25); static const struct reg_field refclk_dig_sel_10g = REG_FIELD(WIZ_SERDES_RST, 24, 24); static const struct reg_field pma_cmn_refclk_int_mode = REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); +static const struct reg_field pma_cmn_refclk1_int_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); static const struct reg_field pma_cmn_refclk_mode = REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); static const struct reg_field pma_cmn_refclk_dig_div = @@ -204,6 +210,27 @@ static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { }, }; +static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { + { + .num_parents = 3, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table = { 2, 3, 0 }, + .node_name = "pll0-refclk", + }, + { + .num_parents = 3, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table = { 2, 3, 0 }, + .node_name = "pll1-refclk", + }, + { + .num_parents = 3, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table = { 2, 3, 0 }, + .node_name = "refclk-dig", + }, +}; + static struct wiz_clk_div_sel clk_div_sel[] = { { .div_sel = CMN_REFCLK, @@ -219,6 +246,7 @@ enum wiz_type { J721E_WIZ_16G, J721E_WIZ_10G, AM64_WIZ_10G, + J784S4_WIZ_10G, }; struct wiz_data { @@ -227,6 +255,7 @@ struct wiz_data { const struct reg_field *pll1_refclk_mux_sel; const struct reg_field *refclk_dig_sel; const struct reg_field *pma_cmn_refclk1_dig_div; + const struct reg_field *pma_cmn_refclk1_int_mode; const struct wiz_clk_mux_sel *clk_mux_sel; unsigned int clk_div_sel_num; }; @@ -259,6 +288,16 @@ static struct wiz_data am64_10g_data = { .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, }; +static struct wiz_data j784s4_wiz_10g = { + .type = J784S4_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, + .refclk_dig_sel = &refclk_dig_sel_16g, + .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, + .clk_mux_sel = clk_mux_sel_10g_2_refclk, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 @@ -279,6 +318,7 @@ struct wiz { struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; + struct regmap_field *pma_cmn_refclk1_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; struct regmap_field *pma_cmn_refclk1_dig_div; @@ -729,6 +769,15 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->pma_cmn_refclk_int_mode); } + if (data->pma_cmn_refclk1_int_mode) { + wiz->pma_cmn_refclk1_int_mode = + devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_int_mode); + if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { + dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); + } + } + wiz->pma_cmn_refclk_mode = devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); if (IS_ERR(wiz->pma_cmn_refclk_mode)) { @@ -844,8 +893,6 @@ static int wiz_clock_init(struct wiz *wiz) return ret; } wiz->input_clks[WIZ_CORE_REFCLK] = clk; - /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */ - wiz->input_clks[WIZ_CORE_REFCLK1] = clk; rate = clk_get_rate(clk); if (rate >= 100000000) @@ -853,6 +900,25 @@ static int wiz_clock_init(struct wiz *wiz) else regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + if (wiz->data->pma_cmn_refclk1_int_mode) { + clk = devm_clk_get(dev, "core_ref1_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref1_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + wiz->input_clks[WIZ_CORE_REFCLK1] = clk; + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); + else + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); + } else { + /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */ + wiz->input_clks[WIZ_CORE_REFCLK1] = clk; + } + clk = devm_clk_get(dev, "ext_ref_clk"); if (IS_ERR(clk)) { dev_err(dev, "ext_ref_clk clock not found\n"); @@ -933,7 +999,7 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz) ofnode node; int i, rc; - if (type == AM64_WIZ_10G) + if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G) return j721e_wiz_bind_clocks(wiz); div_clk_drv = lists_driver_lookup_name("wiz_div_clk"); @@ -1173,6 +1239,9 @@ static const struct udevice_id j721e_wiz_ids[] = { { .compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data, }, + { + .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g, + }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = { #else { "uart0", 5 }, /* PE0-PE1 */ #endif + { "uart1", 5 }, /* PA0-PA3 */ }; static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = { diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index da3e1eb3ab1..83cda1f2040 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -143,7 +143,7 @@ static void serial_find_console_or_panic(void) #else if (!uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) || !uclass_get_device(UCLASS_SERIAL, INDEX, &dev) || - (!uclass_first_device(UCLASS_SERIAL, &dev) && dev)) { + !uclass_first_device_err(UCLASS_SERIAL, &dev)) { gd->cur_serial_dev = dev; return; } diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c index 493a42b4ccc..12cbcb9858c 100644 --- a/drivers/serial/serial_bcm283x_mu.c +++ b/drivers/serial/serial_bcm283x_mu.c @@ -147,7 +147,7 @@ static bool bcm283x_is_serial_muxed(void) int serial_gpio = 15; struct udevice *dev; - if (uclass_first_device(UCLASS_PINCTRL, &dev) || !dev) + if (uclass_first_device_err(UCLASS_PINCTRL, &dev)) return false; if (pinctrl_get_gpio_mux(dev, 0, serial_gpio) != BCM2835_GPIO_ALT5) diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c index fe746294cdc..7d172cdac0a 100644 --- a/drivers/serial/serial_bcm283x_pl011.c +++ b/drivers/serial/serial_bcm283x_pl011.c @@ -24,7 +24,7 @@ static bool bcm283x_is_serial_muxed(void) int serial_gpio = 15; struct udevice *dev; - if (uclass_first_device(UCLASS_PINCTRL, &dev) || !dev) + if (uclass_first_device_err(UCLASS_PINCTRL, &dev)) return false; if (pinctrl_get_gpio_mux(dev, 0, serial_gpio) != BCM2835_GPIO_ALT0) diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index d747ed00a7f..92fad96871b 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -18,7 +18,7 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct udevice *wdt; u32 reset_mode; - int ret = uclass_first_device(UCLASS_WDT, &wdt); + int ret = uclass_first_device_err(UCLASS_WDT, &wdt); if (ret) return ret; diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 6ce389de9f0..43aec7ffa70 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -2636,18 +2636,17 @@ static const struct eth_ops usb_eth_ops = { int usb_ether_init(void) { - struct udevice *dev; struct udevice *usb_dev; int ret; - ret = uclass_first_device(UCLASS_USB_GADGET_GENERIC, &usb_dev); - if (!usb_dev || ret) { + uclass_first_device(UCLASS_USB_GADGET_GENERIC, &usb_dev); + if (!usb_dev) { pr_err("No USB device found\n"); - return ret; + return -ENODEV; } - ret = device_bind_driver(usb_dev, "usb_ether", "usb_ether", &dev); - if (!dev || ret) { + ret = device_bind_driver(usb_dev, "usb_ether", "usb_ether", NULL); + if (ret) { pr_err("usb - not able to bind usb_ether device\n"); return ret; } diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index 69992b3c2ba..86970a6d5d2 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -640,25 +640,17 @@ static int exynos_fb_probe(struct udevice *dev) #endif exynos_fimd_lcd_init(dev); - ret = uclass_first_device(UCLASS_PANEL, &panel); + ret = uclass_first_device_err(UCLASS_PANEL, &panel); if (ret) { - printf("LCD panel failed to probe\n"); + printf("%s: LCD panel failed to probe %d\n", __func__, ret); return ret; } - if (!panel) { - printf("LCD panel not found\n"); - return -ENODEV; - } - ret = uclass_first_device(UCLASS_DISPLAY, &dp); + ret = uclass_first_device_err(UCLASS_DISPLAY, &dp); if (ret) { debug("%s: Display device error %d\n", __func__, ret); return ret; } - if (!dev) { - debug("%s: Display device missing\n", __func__); - return -ENODEV; - } ret = display_enable(dp, 18, NULL); if (ret) { debug("%s: Display enable error %d\n", __func__, ret); diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 49bbeefdd8e..8b01a1be112 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -609,12 +609,11 @@ static int ipuv3_video_probe(struct udevice *dev) return ret; #if defined(CONFIG_DISPLAY) - ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev); - if (disp_dev) { + ret = uclass_first_device_err(UCLASS_DISPLAY, &disp_dev); + if (!ret) ret = display_enable(disp_dev, 16, NULL); - if (ret < 0) - return ret; - } + if (ret < 0) + return ret; #endif if (CONFIG_IS_ENABLED(PANEL)) { struct udevice *panel_dev; diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c index ba1ddd64e08..cbcdb99e1f0 100644 --- a/drivers/video/mali_dp.c +++ b/drivers/video/mali_dp.c @@ -244,7 +244,7 @@ static int malidp_update_timings_from_edid(struct udevice *dev, struct udevice *disp_dev; int err; - err = uclass_first_device(UCLASS_DISPLAY, &disp_dev); + err = uclass_first_device_err(UCLASS_DISPLAY, &disp_dev); if (err) return err; diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 5871ac7c4ff..e6347bb8da6 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -346,7 +346,7 @@ static int stm32_dsi_attach(struct udevice *dev) struct display_timing timings; int ret; - ret = uclass_first_device(UCLASS_PANEL, &priv->panel); + ret = uclass_first_device_err(UCLASS_PANEL, &priv->panel); if (ret) { dev_err(dev, "panel device error %d\n", ret); return ret; diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c index ee4f09a0c49..b27b1633bab 100644 --- a/drivers/video/tegra124/dp.c +++ b/drivers/video/tegra124/dp.c @@ -1494,8 +1494,8 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp, return -ENOLINK; } - ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor); - if (ret || !sor) { + ret = uclass_first_device_err(UCLASS_VIDEO_BRIDGE, &sor); + if (ret) { debug("dp: failed to find SOR device: ret=%d\n", ret); return ret; } diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index 9e2d0e06a1e..da4f2f26a63 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -183,21 +183,8 @@ void virtio_driver_features_init(struct virtio_dev_priv *priv, int virtio_init(void) { - struct udevice *bus; - int ret; - /* Enumerate all known virtio devices */ - ret = uclass_first_device(UCLASS_VIRTIO, &bus); - if (ret) - return ret; - - while (bus) { - ret = uclass_next_device(&bus); - if (ret) - break; - } - - return ret; + return uclass_probe_all(UCLASS_VIRTIO); } static int virtio_uclass_pre_probe(struct udevice *udev) diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c index 52b519c21d2..de4f25bcf95 100644 --- a/drivers/w1/w1-uclass.c +++ b/drivers/w1/w1-uclass.c @@ -16,6 +16,7 @@ #include <common.h> #include <dm.h> +#include <errno.h> #include <log.h> #include <w1.h> #include <w1-eeprom.h> @@ -182,24 +183,25 @@ static int w1_enumerate(struct udevice *bus) int w1_get_bus(int busnum, struct udevice **busp) { int ret, i = 0; - struct udevice *dev; - for (ret = uclass_first_device(UCLASS_W1, &dev); - dev && !ret; - ret = uclass_next_device(&dev), i++) { + for (ret = uclass_first_device_check(UCLASS_W1, &dev); + dev; + ret = uclass_next_device_check(&dev), i++) { if (i == busnum) { + if (ret) { + debug("Cannot probe w1 bus %d: %d (%s)\n", + busnum, ret, errno_str(ret)); + return ret; + } *busp = dev; return 0; } } - if (!ret) { - debug("Cannot find w1 bus %d\n", busnum); - ret = -ENODEV; - } + debug("Cannot find w1 bus %d\n", busnum); - return ret; + return -ENODEV; } u8 w1_get_device_family(struct udevice *dev) diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index ca2bc7cfb59..f0e57b4f728 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -39,7 +39,7 @@ #include <common.h> #include <log.h> #include <watchdog.h> -#include <asm/arch/hardware.h> +#include <asm/ti-common/omap_wdt.h> #include <asm/io.h> #include <asm/processor.h> #include <asm/arch/cpu.h> diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c index 970182cd904..95e298d7ddc 100644 --- a/drivers/xen/pvblock.c +++ b/drivers/xen/pvblock.c @@ -852,10 +852,7 @@ static int pvblock_probe(struct udevice *udev) ret = uclass_get(UCLASS_BLK, &uc); if (ret) return ret; - uclass_foreach_dev_probe(UCLASS_BLK, udev) { - if (_ret) - return _ret; - }; + uclass_foreach_dev_probe(UCLASS_BLK, udev); return 0; } diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index c80f8e80283..3f0d9f1c113 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include <common.h> #include <fs_internal.h> +#include <log.h> #include <uuid.h> #include <memalign.h> #include "kernel-shared/btrfs_tree.h" @@ -910,9 +911,9 @@ static int btrfs_scan_fs_devices(struct blk_desc *desc, if (round_up(BTRFS_SUPER_INFO_SIZE + BTRFS_SUPER_INFO_OFFSET, desc->blksz) > (part->size << desc->log2blksz)) { - error("superblock end %u is larger than device size " LBAFU, - BTRFS_SUPER_INFO_SIZE + BTRFS_SUPER_INFO_OFFSET, - part->size << desc->log2blksz); + log_debug("superblock end %u is larger than device size " LBAFU, + BTRFS_SUPER_INFO_SIZE + BTRFS_SUPER_INFO_OFFSET, + part->size << desc->log2blksz); return -EINVAL; } diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index d49ba4a9954..1185cb2c046 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2415,7 +2415,7 @@ int ext4fs_mount(unsigned part_length) return 1; fail: - printf("Failed to mount ext2 filesystem...\n"); + log_debug("Failed to mount ext2 filesystem...\n"); fail_noerr: free(data); ext4fs_root = NULL; diff --git a/fs/fs_internal.c b/fs/fs_internal.c index ae1cb8584c7..111f91b355d 100644 --- a/fs/fs_internal.c +++ b/fs/fs_internal.c @@ -29,8 +29,7 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition, /* Check partition boundaries */ if ((sector + ((byte_offset + byte_len - 1) >> log2blksz)) >= partition->size) { - log_err("%s read outside partition " LBAFU "\n", __func__, - sector); + log_debug("read outside partition " LBAFU "\n", sector); return 0; } diff --git a/include/clk.h b/include/clk.h index 407513e0fa2..138766bd49f 100644 --- a/include/clk.h +++ b/include/clk.h @@ -474,7 +474,7 @@ struct clk *clk_get_parent(struct clk *clk); * * Return: clock rate in Hz, or -ve error code. */ -long long clk_get_parent_rate(struct clk *clk); +ulong clk_get_parent_rate(struct clk *clk); /** * clk_round_rate() - Adjust a rate to the exact rate a clock can provide @@ -607,7 +607,7 @@ static inline struct clk *clk_get_parent(struct clk *clk) return ERR_PTR(-ENOSYS); } -static inline long long clk_get_parent_rate(struct clk *clk) +static inline ulong clk_get_parent_rate(struct clk *clk) { return -ENOSYS; } diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0f0ef4f64bb..fe90d55bd45 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -135,7 +135,21 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) -#elif defined(CONFIG_MACH_SUN8I_V3S) +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 256) +/* + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. + */ +#define BOOTM_SIZE __stringify(0xa000000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) + +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 64) /* * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, @@ -149,33 +163,22 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000)) -#elif defined(CONFIG_MACH_SUNIV) +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 32) /* - * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc. - * 8M uncompressed kernel, 4M compressed kernel, 512K fdt, - * 512K script, 512K pxe and the ramdisk at the end. + * 32M RAM minus 2.5MB for u-boot, heap, stack, etc. + * 16M uncompressed kernel, 7M compressed kernel, 128K fdt, 64K script, + * 128K DT overlay, 128K PXE and the ramdisk in the rest (max. 5MB) */ #define BOOTM_SIZE __stringify(0x1700000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0500000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(0C00000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C50000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(0D00000)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D50000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000)) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1d50000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1d40000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1d00000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1d20000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1800000)) #else -/* - * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. - * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, - * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. - */ -#define BOOTM_SIZE __stringify(0xa000000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) +#error Need at least 32MB of DRAM. Please adjust load addresses. #endif #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 7aae2c29ef1..fa9865602d8 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -59,6 +59,9 @@ __attribute_const__ int ofnode_to_offset(ofnode node); /** * oftree_from_fdt() - Returns an oftree from a flat device tree pointer * + * If @fdt is not already registered in the list of current device trees, it is + * added to the list. + * * @fdt: Device tree to use * * Returns: reference to the given node diff --git a/include/dm/uclass.h b/include/dm/uclass.h index f6c0110b061..823a16527f7 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -333,17 +333,6 @@ int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, int uclass_first_device(enum uclass_id id, struct udevice **devp); /** - * uclass_first_device_err() - Get the first device in a uclass - * - * The device returned is probed if necessary, and ready for use - * - * @id: Uclass ID to look up - * @devp: Returns pointer to the first device in that uclass, or NULL if none - * Return: 0 if found, -ENODEV if not found, other -ve on error - */ -int uclass_first_device_err(enum uclass_id id, struct udevice **devp); - -/** * uclass_next_device() - Get the next device in a uclass * * The device returned is probed if necessary, and ready for use @@ -359,6 +348,17 @@ int uclass_first_device_err(enum uclass_id id, struct udevice **devp); int uclass_next_device(struct udevice **devp); /** + * uclass_first_device_err() - Get the first device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * @id: Uclass ID to look up + * @devp: Returns pointer to the first device in that uclass, or NULL if none + * Return: 0 if found, -ENODEV if not found, other -ve on error + */ +int uclass_first_device_err(enum uclass_id id, struct udevice **devp); + +/** * uclass_next_device_err() - Get the next device in a uclass * * The device returned is probed if necessary, and ready for use @@ -491,7 +491,7 @@ int uclass_id_count(enum uclass_id id); * are no more devices. */ #define uclass_foreach_dev_probe(id, dev) \ - for (int _ret = uclass_first_device_err(id, &dev); !_ret && dev; \ - _ret = uclass_next_device_err(&dev)) + for (uclass_first_device(id, &dev); dev; \ + uclass_next_device(&dev)) #endif diff --git a/include/dma-uclass.h b/include/dma-uclass.h index 340437acc13..ea721baae69 100644 --- a/include/dma-uclass.h +++ b/include/dma-uclass.h @@ -132,8 +132,8 @@ struct dma_ops { * @len: Length of the data to be copied (number of bytes). * @return zero on success, or -ve error code. */ - int (*transfer)(struct udevice *dev, int direction, void *dst, - void *src, size_t len); + int (*transfer)(struct udevice *dev, int direction, dma_addr_t dst, + dma_addr_t src, size_t len); }; #endif /* _DMA_UCLASS_H */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h index 890368d252c..a96087abc86 100644 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -22,5 +22,6 @@ #define CLK_W1 12 #define CLK_R_APB2_RSB 13 +#define CLK_R_APB1_RTC 14 #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 4fc08b0df2f..1191aca53ac 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -111,5 +111,6 @@ #define CLK_BUS_TVE0 125 #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 +#define CLK_PLL_SYSTEM_32K 128 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h new file mode 100644 index 00000000000..c845493e4d3 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ +#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index f8642f99420..7c4189e2434 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -40,7 +40,7 @@ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) struct udevice *cpu; int ret; - ret = uclass_first_device(UCLASS_CPU, &cpu); + ret = uclass_first_device_err(UCLASS_CPU, &cpu); if (ret) return log_msg_ret("cpu", ret); ret = cpu_get_info(cpu, &info); diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 5908b5c6466..20bd7fff086 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -482,7 +482,7 @@ efi_status_t efi_gop_register(void) struct video_priv *priv; /* We only support a single video output device for now */ - if (uclass_first_device(UCLASS_VIDEO, &vdev) || !vdev) { + if (uclass_first_device_err(UCLASS_VIDEO, &vdev)) { debug("WARNING: No video device\n"); return EFI_SUCCESS; } diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 0f6b45b002c..f41da4b37b3 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -91,8 +91,10 @@ struct udevice *eth_get_dev(void) eth_errno = uclass_get_device_by_seq(UCLASS_ETH, 0, &uc_priv->current); if (eth_errno) - eth_errno = uclass_first_device(UCLASS_ETH, - &uc_priv->current); + eth_errno = uclass_first_device_err(UCLASS_ETH, + &uc_priv->current); + if (eth_errno) + uc_priv->current = NULL; } return uc_priv->current; } diff --git a/test/boot/Makefile b/test/boot/Makefile index 9e9d5ae21f3..5bb3f889759 100644 --- a/test/boot/Makefile +++ b/test/boot/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_BOOTSTD) += bootdev.o bootstd_common.o bootflow.o bootmeth.o ifdef CONFIG_OF_LIVE obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o endif +obj-$(CONFIG_BOOTMETH_VBE) += vbe_fixup.o diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 85305234e01..1e8ea754bcd 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -329,6 +329,8 @@ static int bootflow_system(struct unit_test_state *uts) { struct udevice *dev; + if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) + return 0; ut_assertok(uclass_get_device_by_name(UCLASS_BOOTMETH, "efi_mgr", &dev)); sandbox_set_fake_efi_mgr_dev(dev, true); diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c index fb627313396..f0b5ab9adb3 100644 --- a/test/boot/bootmeth.c +++ b/test/boot/bootmeth.c @@ -156,7 +156,7 @@ static int bootmeth_state(struct unit_test_state *uts) struct udevice *dev; char buf[50]; - ut_assertok(uclass_first_device(UCLASS_BOOTMETH, &dev)); + ut_assertok(uclass_first_device_err(UCLASS_BOOTMETH, &dev)); ut_assertnonnull(dev); ut_assertok(bootmeth_get_state_desc(dev, buf, sizeof(buf))); diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c index 05347d87106..7a40836507a 100644 --- a/test/boot/bootstd_common.c +++ b/test/boot/bootstd_common.c @@ -9,10 +9,52 @@ #include <common.h> #include <bootstd.h> #include <dm.h> +#include <memalign.h> +#include <mmc.h> +#include <linux/log2.h> #include <test/suites.h> #include <test/ut.h> +#include <u-boot/crc.h> #include "bootstd_common.h" +/* tracks whether bootstd_setup_for_tests() has been run yet */ +bool vbe_setup_done; + +/* set up MMC for VBE tests */ +int bootstd_setup_for_tests(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(u8, buf, MMC_MAX_BLOCK_LEN); + struct udevice *mmc; + struct blk_desc *desc; + int ret; + + if (vbe_setup_done) + return 0; + + /* Set up the version string */ + ret = uclass_get_device(UCLASS_MMC, 1, &mmc); + if (ret) + return log_msg_ret("mmc", -EIO); + desc = blk_get_by_device(mmc); + + memset(buf, '\0', MMC_MAX_BLOCK_LEN); + strcpy(buf, TEST_VERSION); + if (blk_dwrite(desc, VERSION_START_BLK, 1, buf) != 1) + return log_msg_ret("wr1", -EIO); + + /* Set up the nvdata */ + memset(buf, '\0', MMC_MAX_BLOCK_LEN); + buf[1] = ilog2(0x40) << 4 | 1; + *(u32 *)(buf + 4) = TEST_VERNUM; + buf[0] = crc8(0, buf + 1, 0x3f); + if (blk_dwrite(desc, NVDATA_START_BLK, 1, buf) != 1) + return log_msg_ret("wr2", -EIO); + + vbe_setup_done = true; + + return 0; +} + int bootstd_test_drop_bootdev_order(struct unit_test_state *uts) { struct bootstd_priv *priv; @@ -29,6 +71,13 @@ int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct unit_test *tests = UNIT_TEST_SUITE_START(bootstd_test); const int n_ents = UNIT_TEST_SUITE_COUNT(bootstd_test); + int ret; + + ret = bootstd_setup_for_tests(); + if (ret) { + printf("Failed to set up for bootstd tests (err=%d)\n", ret); + return CMD_RET_FAILURE; + } return cmd_ut_category("bootstd", "bootstd_test_", tests, n_ents, argc, argv); diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h index 676ef0a57f9..c5e0fd1ceab 100644 --- a/test/boot/bootstd_common.h +++ b/test/boot/bootstd_common.h @@ -9,10 +9,17 @@ #ifndef __bootstd_common_h #define __bootstd_common_h +#include <version_string.h> + /* Declare a new bootdev test */ #define BOOTSTD_TEST(_name, _flags) \ UNIT_TEST(_name, _flags, bootstd_test) +#define NVDATA_START_BLK ((0x400 + 0x400) / MMC_MAX_BLOCK_LEN) +#define VERSION_START_BLK ((0x400 + 0x800) / MMC_MAX_BLOCK_LEN) +#define TEST_VERSION "U-Boot v2022.04-local2" +#define TEST_VERNUM 0x00010002 + struct unit_test_state; /** @@ -24,4 +31,13 @@ struct unit_test_state; */ int bootstd_test_drop_bootdev_order(struct unit_test_state *uts); +/** + * bootstd_setup_for_tests() - Set up MMC data for VBE tests + * + * Some data is needed for VBE tests to work. This function sets that up. + * + * @return 0 if OK, -ve on error + */ +int bootstd_setup_for_tests(void); + #endif diff --git a/test/boot/vbe_fixup.c b/test/boot/vbe_fixup.c new file mode 100644 index 00000000000..1b488e25ab6 --- /dev/null +++ b/test/boot/vbe_fixup.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for VBE device tree fix-ups + * + * Copyright 2022 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <dm/ofnode.h> +#include <linux/libfdt.h> +#include <test/test.h> +#include <test/ut.h> +#include "bootstd_common.h" + +/* Basic test of reading nvdata and updating a fwupd node in the device tree */ +static int vbe_test_fixup(struct unit_test_state *uts) +{ + ofnode chosen, node; + const char *data; + oftree tree; + int size; + + /* + * This test works when called from test_vbe.py and it must use the + * flat tree, since device tree fix-ups do not yet support live tree. + */ + if (!working_fdt) + return 0; + + tree = oftree_from_fdt(working_fdt); + ut_assert(oftree_valid(tree)); + + chosen = oftree_path(tree, "/chosen"); + ut_assert(ofnode_valid(chosen)); + + /* check the things set up for the FIT in test_vbe.py */ + node = ofnode_find_subnode(chosen, "random"); + + /* ignore if this test is run on its own */ + if (!ofnode_valid(node)) + return 0; + data = ofnode_read_prop(node, "data", &size); + ut_asserteq(0x40, size); + + node = ofnode_find_subnode(chosen, "aslr2"); + ut_assert(ofnode_valid(node)); + data = ofnode_read_prop(node, "data", &size); + ut_asserteq(4, size); + + node = ofnode_find_subnode(chosen, "efi-runtime"); + ut_assert(ofnode_valid(node)); + data = ofnode_read_prop(node, "data", &size); + ut_asserteq(4, size); + + return 0; +} +BOOTSTD_TEST(vbe_test_fixup, + UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE); diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c index 8acd777f4cd..faba9e8f90b 100644 --- a/test/boot/vbe_simple.c +++ b/test/boot/vbe_simple.c @@ -10,54 +10,27 @@ #include <bootmeth.h> #include <dm.h> #include <image.h> -#include <memalign.h> -#include <mmc.h> #include <of_live.h> #include <vbe.h> -#include <version_string.h> -#include <linux/log2.h> #include <test/suites.h> #include <test/ut.h> -#include <u-boot/crc.h> #include "bootstd_common.h" -#define NVDATA_START_BLK ((0x400 + 0x400) / MMC_MAX_BLOCK_LEN) -#define VERSION_START_BLK ((0x400 + 0x800) / MMC_MAX_BLOCK_LEN) -#define TEST_VERSION "U-Boot v2022.04-local2" -#define TEST_VERNUM 0x00010002 - /* Basic test of reading nvdata and updating a fwupd node in the device tree */ static int vbe_simple_test_base(struct unit_test_state *uts) { - ALLOC_CACHE_ALIGN_BUFFER(u8, buf, MMC_MAX_BLOCK_LEN); const char *version, *bl_version; struct event_ft_fixup fixup; - struct udevice *dev, *mmc; + struct udevice *dev; struct device_node *np; - struct blk_desc *desc; char fdt_buf[0x400]; char info[100]; int node_ofs; ofnode node; u32 vernum; - /* Set up the version string */ - ut_assertok(uclass_get_device(UCLASS_MMC, 1, &mmc)); - desc = blk_get_by_device(mmc); - ut_assertnonnull(desc); - - memset(buf, '\0', MMC_MAX_BLOCK_LEN); - strcpy(buf, TEST_VERSION); - if (blk_dwrite(desc, VERSION_START_BLK, 1, buf) != 1) - return log_msg_ret("write", -EIO); - - /* Set up the nvdata */ - memset(buf, '\0', MMC_MAX_BLOCK_LEN); - buf[1] = ilog2(0x40) << 4 | 1; - *(u32 *)(buf + 4) = TEST_VERNUM; - buf[0] = crc8(0, buf + 1, 0x3f); - if (blk_dwrite(desc, NVDATA_START_BLK, 1, buf) != 1) - return log_msg_ret("write", -EIO); + /* Set up the VBE info */ + ut_assertok(bootstd_setup_for_tests()); /* Read the version back */ ut_assertok(vbe_find_by_any("firmware0", &dev)); @@ -90,6 +63,7 @@ static int vbe_simple_test_base(struct unit_test_state *uts) * * Two fix this we need image_setup_libfdt() is updated to use ofnode */ + fixup.images = NULL; ut_assertok(event_notify(EVT_FT_FIXUP, &fixup, sizeof(fixup))); node = oftree_path(fixup.tree, "/chosen/fwupd/firmware0"); diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index 100a7ef5ebf..ba9eaa42c14 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -55,6 +55,7 @@ static int fdt_test_addr(struct unit_test_state *uts) /* The working fdt is not set, so this should fail */ set_working_fdt_addr(0); + ut_assert_nextline("Working FDT set to 0"); ut_asserteq(CMD_RET_FAILURE, run_command("fdt addr", 0)); ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); ut_assertok(ut_check_console_end(uts)); @@ -63,18 +64,22 @@ static int fdt_test_addr(struct unit_test_state *uts) ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt))); addr = map_to_sysmem(fdt); set_working_fdt_addr(addr); + ut_assert_nextline("Working FDT set to %lx", addr); ut_assertok(run_command("fdt addr", 0)); ut_assert_nextline("Working fdt: %08lx", (ulong)map_to_sysmem(fdt)); ut_assertok(ut_check_console_end(uts)); /* Set the working FDT */ set_working_fdt_addr(0); + ut_assert_nextline("Working FDT set to 0"); ut_assertok(run_commandf("fdt addr %08x", addr)); + ut_assert_nextline("Working FDT set to %lx", addr); ut_asserteq(addr, map_to_sysmem(working_fdt)); ut_assertok(ut_check_console_end(uts)); set_working_fdt_addr(0); + ut_assert_nextline("Working FDT set to 0"); - /* Set the working FDT */ + /* Set the control FDT */ fdt_blob = gd->fdt_blob; gd->fdt_blob = NULL; ret = run_commandf("fdt addr -c %08x", addr); @@ -93,6 +98,7 @@ static int fdt_test_addr(struct unit_test_state *uts) /* Test detecting an invalid FDT */ fdt[0] = 123; set_working_fdt_addr(addr); + ut_assert_nextline("Working FDT set to %lx", addr); ut_asserteq(1, run_commandf("fdt addr")); ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); ut_assertok(ut_check_console_end(uts)); @@ -115,16 +121,19 @@ static int fdt_test_resize(struct unit_test_state *uts) /* Test setting and resizing the working FDT to a larger size */ ut_assertok(console_record_reset_enable()); ut_assertok(run_commandf("fdt addr %08x %x", addr, newsize)); + ut_assert_nextline("Working FDT set to %lx", addr); ut_assertok(ut_check_console_end(uts)); /* Try shrinking it */ ut_assertok(run_commandf("fdt addr %08x %x", addr, sizeof(fdt) / 4)); + ut_assert_nextline("Working FDT set to %lx", addr); ut_assert_nextline("New length %d < existing length %d, ignoring", (int)sizeof(fdt) / 4, newsize); ut_assertok(ut_check_console_end(uts)); /* ...quietly */ ut_assertok(run_commandf("fdt addr -q %08x %x", addr, sizeof(fdt) / 4)); + ut_assert_nextline("Working FDT set to %lx", addr); ut_assertok(ut_check_console_end(uts)); /* We cannot easily provoke errors in fdt_open_into(), so ignore that */ diff --git a/test/dm/acpi.c b/test/dm/acpi.c index edad91329f9..9634fc2e900 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -169,28 +169,28 @@ static int dm_test_acpi_get_name(struct unit_test_state *uts) ut_asserteq_str("GHIJ", name); /* Test getting the name from acpi_device_get_name() */ - ut_assertok(uclass_first_device(UCLASS_I2C, &i2c)); + ut_assertok(uclass_first_device_err(UCLASS_I2C, &i2c)); ut_assertok(acpi_get_name(i2c, name)); ut_asserteq_str("I2C0", name); - ut_assertok(uclass_first_device(UCLASS_SPI, &spi)); + ut_assertok(uclass_first_device_err(UCLASS_SPI, &spi)); ut_assertok(acpi_get_name(spi, name)); ut_asserteq_str("SPI0", name); /* ACPI doesn't know about the timer */ - ut_assertok(uclass_first_device(UCLASS_TIMER, &timer)); + ut_assertok(uclass_first_device_err(UCLASS_TIMER, &timer)); ut_asserteq(-ENOENT, acpi_get_name(timer, name)); /* May as well test the rest of the cases */ - ut_assertok(uclass_first_device(UCLASS_SOUND, &sound)); + ut_assertok(uclass_first_device_err(UCLASS_SOUND, &sound)); ut_assertok(acpi_get_name(sound, name)); ut_asserteq_str("HDAS", name); - ut_assertok(uclass_first_device(UCLASS_PCI, &pci)); + ut_assertok(uclass_first_device_err(UCLASS_PCI, &pci)); ut_assertok(acpi_get_name(pci, name)); ut_asserteq_str("PCI0", name); - ut_assertok(uclass_first_device(UCLASS_ROOT, &root)); + ut_assertok(uclass_first_device_err(UCLASS_ROOT, &root)); ut_assertok(acpi_get_name(root, name)); ut_asserteq_str("\\_SB", name); @@ -219,7 +219,7 @@ static int dm_test_acpi_create_dmar(struct unit_test_state *uts) struct acpi_dmar dmar; struct udevice *cpu; - ut_assertok(uclass_first_device(UCLASS_CPU, &cpu)); + ut_assertok(uclass_first_device_err(UCLASS_CPU, &cpu)); ut_assertnonnull(cpu); ut_assertok(acpi_create_dmar(&dmar, DMAR_INTR_REMAP)); ut_asserteq(DMAR_INTR_REMAP, dmar.flags); diff --git a/test/dm/core.c b/test/dm/core.c index fd4d7569728..84eb76ed5fc 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -512,23 +512,15 @@ static int dm_test_leak(struct unit_test_state *uts) int i; for (i = 0; i < 2; i++) { - struct udevice *dev; int ret; - int id; dm_leak_check_start(uts); ut_assertok(dm_scan_plat(false)); ut_assertok(dm_scan_fdt(false)); - /* Scanning the uclass is enough to probe all the devices */ - for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) { - for (ret = uclass_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_next_device(&dev)) - ; - ut_assertok(ret); - } + ret = uclass_probe_all(UCLASS_TEST); + ut_assertok(ret); ut_assertok(dm_leak_check_end(uts)); } @@ -653,10 +645,7 @@ static int dm_test_children(struct unit_test_state *uts) ut_asserteq(2 + NODE_COUNT, dm_testdrv_op_count[DM_TEST_OP_PROBE]); /* Probe everything */ - for (ret = uclass_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_next_device(&dev)) - ; + ret = uclass_probe_all(UCLASS_TEST); ut_assertok(ret); ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_PROBE]); diff --git a/test/dm/devres.c b/test/dm/devres.c index 524114c833c..3df0f64362d 100644 --- a/test/dm/devres.c +++ b/test/dm/devres.c @@ -165,8 +165,8 @@ static int dm_test_devres_phase(struct unit_test_state *uts) ut_asserteq(TEST_DEVRES_SIZE + TEST_DEVRES_SIZE3, stats.total_size); /* Probing the device should add one allocation */ - ut_assertok(uclass_first_device(UCLASS_TEST_DEVRES, &dev)); - ut_assert(dev != NULL); + ut_assertok(uclass_first_device_err(UCLASS_TEST_DEVRES, &dev)); + ut_assertnonnull(dev); devres_get_stats(dev, &stats); ut_asserteq(3, stats.allocs); ut_asserteq(TEST_DEVRES_SIZE + TEST_DEVRES_SIZE2 + TEST_DEVRES_SIZE3, diff --git a/test/dm/i2c.c b/test/dm/i2c.c index 74b20971956..b46a22e79b1 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -124,7 +124,7 @@ static int dm_test_i2c_bytewise(struct unit_test_state *uts) ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf)); /* Tell the EEPROM to only read/write one register at a time */ - ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom)); + ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom)); ut_assertnonnull(eeprom); sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE); @@ -177,7 +177,7 @@ static int dm_test_i2c_offset(struct unit_test_state *uts) /* Do a transfer so we can find the emulator */ ut_assertok(dm_i2c_read(dev, 0, buf, 5)); - ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom)); + ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom)); /* Offset length 0 */ sandbox_i2c_eeprom_set_offset_len(eeprom, 0); @@ -250,7 +250,7 @@ static int dm_test_i2c_addr_offset(struct unit_test_state *uts) /* Do a transfer so we can find the emulator */ ut_assertok(dm_i2c_read(dev, 0, buf, 5)); - ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom)); + ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom)); /* Offset length 0 */ sandbox_i2c_eeprom_set_offset_len(eeprom, 0); @@ -315,7 +315,7 @@ static int dm_test_i2c_reg_clrset(struct unit_test_state *uts) /* Do a transfer so we can find the emulator */ ut_assertok(dm_i2c_read(dev, 0, buf, 5)); - ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom)); + ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom)); /* Dummy data for the test */ ut_assertok(dm_i2c_write(dev, 0, "\xff\x00\xff\x00\x10", 5)); diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c index a0cc84c3961..354720f61e2 100644 --- a/test/dm/k210_pll.c +++ b/test/dm/k210_pll.c @@ -33,7 +33,7 @@ static int dm_test_k210_pll_calc_config(u32 rate, u32 rate_in, error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); /* The lower 16 bits are spurious */ - error = abs((error - BIT(32))) >> 16; + error = abs64((error - BIT_ULL(32))) >> 16; if (error < best_error) { best->r = r; best->f = f; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 012f2f455f6..1f14513d9f1 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -392,10 +392,10 @@ DM_TEST(dm_test_fdt_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE); /** - * Test various error conditions with uclass_first_device() and - * uclass_next_device() + * Test various error conditions with uclass_first_device(), + * uclass_next_device(), and uclass_probe_all() */ -static int dm_test_first_next_device(struct unit_test_state *uts) +static int dm_test_first_next_device_probeall(struct unit_test_state *uts) { struct dm_testprobe_pdata *pdata; struct udevice *dev, *parent = NULL; @@ -428,9 +428,20 @@ static int dm_test_first_next_device(struct unit_test_state *uts) device_remove(parent, DM_REMOVE_NORMAL); ut_asserteq(-ENOENT, uclass_first_device(UCLASS_TEST_PROBE, &dev)); + /* Now that broken devices are set up test probe_all */ + device_remove(parent, DM_REMOVE_NORMAL); + /* There are broken devices so an error should be returned */ + ut_assert(uclass_probe_all(UCLASS_TEST_PROBE) < 0); + /* but non-error device should be probed nonetheless */ + ut_assertok(uclass_get_device(UCLASS_TEST_PROBE, 2, &dev)); + ut_assert(dev_get_flags(dev) & DM_FLAG_ACTIVATED); + ut_assertok(uclass_get_device(UCLASS_TEST_PROBE, 3, &dev)); + ut_assert(dev_get_flags(dev) & DM_FLAG_ACTIVATED); + return 0; } -DM_TEST(dm_test_first_next_device, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +DM_TEST(dm_test_first_next_device_probeall, + UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); /* Test iteration through devices in a uclass */ static int dm_test_uclass_foreach(struct unit_test_state *uts) diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c index d0195e6bf09..b5c4523a028 100644 --- a/test/dm/virtio_device.c +++ b/test/dm/virtio_device.c @@ -22,7 +22,7 @@ static int dm_test_virtio_base(struct unit_test_state *uts) u8 status; /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertok(uclass_first_device_err(UCLASS_VIRTIO, &bus)); ut_assertnonnull(bus); /* check the child virtio-rng device is bound */ @@ -60,7 +60,7 @@ static int dm_test_virtio_all_ops(struct unit_test_state *uts) struct virtqueue *vqs[2]; /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertok(uclass_first_device_err(UCLASS_VIRTIO, &bus)); ut_assertnonnull(bus); /* check the child virtio-rng device is bound */ @@ -102,7 +102,7 @@ static int dm_test_virtio_remove(struct unit_test_state *uts) struct udevice *bus, *dev; /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertok(uclass_first_device_err(UCLASS_VIRTIO, &bus)); ut_assertnonnull(bus); /* check the child virtio-rng device is bound */ @@ -134,7 +134,7 @@ static int dm_test_virtio_ring(struct unit_test_state *uts) u8 buffer[2][32]; /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertok(uclass_first_device_err(UCLASS_VIRTIO, &bus)); ut_assertnonnull(bus); /* check the child virtio-blk device is bound */ diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c index ff5646b4e11..8b9a04b1fde 100644 --- a/test/dm/virtio_rng.c +++ b/test/dm/virtio_rng.c @@ -28,7 +28,7 @@ static int dm_test_virtio_rng_check_len(struct unit_test_state *uts) u8 buffer[16]; /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertok(uclass_first_device_err(UCLASS_VIRTIO, &bus)); ut_assertnonnull(bus); /* check the child virtio-rng device is bound */ diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c index 0cc01dc199c..e2f44f3ecb6 100644 --- a/test/fuzz/cmd_fuzz.c +++ b/test/fuzz/cmd_fuzz.c @@ -29,7 +29,7 @@ static struct udevice *find_fuzzing_engine(void) { struct udevice *dev; - if (uclass_first_device(UCLASS_FUZZING_ENGINE, &dev)) + if (uclass_first_device_err(UCLASS_FUZZING_ENGINE, &dev)) return NULL; return dev; diff --git a/test/fuzz/virtio.c b/test/fuzz/virtio.c index e5363d5638e..8a47667e778 100644 --- a/test/fuzz/virtio.c +++ b/test/fuzz/virtio.c @@ -30,7 +30,7 @@ static int fuzz_vring(const uint8_t *data, size_t size) return 0; /* check probe success */ - if (uclass_first_device(UCLASS_VIRTIO, &bus) || !bus) + if (uclass_first_device_err(UCLASS_VIRTIO, &bus)) panic("Could not find virtio bus\n"); /* check the child virtio-rng device is bound */ diff --git a/test/py/tests/fit_util.py b/test/py/tests/fit_util.py new file mode 100644 index 00000000000..79718d431a0 --- /dev/null +++ b/test/py/tests/fit_util.py @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2022 Google LLC + +"""Common utility functions for FIT tests""" + +import os + +import u_boot_utils as util + +def make_fname(cons, basename): + """Make a temporary filename + + Args: + cons (ConsoleBase): u_boot_console to use + basename (str): Base name of file to create (within temporary directory) + Return: + Temporary filename + """ + + return os.path.join(cons.config.build_dir, basename) + +def make_its(cons, base_its, params, basename='test.its'): + """Make a sample .its file with parameters embedded + + Args: + cons (ConsoleBase): u_boot_console to use + base_its (str): Template text for the .its file, typically containing + %() references + params (dict of str): Parameters to embed in the %() strings + basename (str): base name to write to (will be placed in the temp dir) + Returns: + str: Filename of .its file created + """ + its = make_fname(cons, basename) + with open(its, 'w', encoding='utf-8') as outf: + print(base_its % params, file=outf) + return its + +def make_fit(cons, mkimage, base_its, params, basename='test.fit', base_fdt=None): + """Make a sample .fit file ready for loading + + This creates a .its script with the selected parameters and uses mkimage to + turn this into a .fit image. + + Args: + cons (ConsoleBase): u_boot_console to use + mkimage (str): Filename of 'mkimage' utility + base_its (str): Template text for the .its file, typically containing + %() references + params (dict of str): Parameters to embed in the %() strings + basename (str): base name to write to (will be placed in the temp dir) + Return: + Filename of .fit file created + """ + fit = make_fname(cons, basename) + its = make_its(cons, base_its, params) + util.run_and_log(cons, [mkimage, '-f', its, fit]) + if base_fdt: + with open(make_fname(cons, 'u-boot.dts'), 'w') as fd: + fd.write(base_fdt) + return fit + +def make_kernel(cons, basename, text): + """Make a sample kernel with test data + + Args: + cons (ConsoleBase): u_boot_console to use + basename (str): base name to write to (will be placed in the temp dir) + text (str): Contents of the kernel file (will be repeated 100 times) + Returns: + str: Full path and filename of the kernel it created + """ + fname = make_fname(cons, basename) + data = '' + for i in range(100): + data += f'this {text} {i} is unlikely to boot\n' + with open(fname, 'w', encoding='utf-8') as outf: + print(data, file=outf) + return fname + +def make_dtb(cons, base_fdt, basename): + """Make a sample .dts file and compile it to a .dtb + + Returns: + cons (ConsoleBase): u_boot_console to use + Filename of .dtb file created + """ + src = make_fname(cons, f'{basename}.dts') + dtb = make_fname(cons, f'{basename}.dtb') + with open(src, 'w', encoding='utf-8') as outf: + outf.write(base_fdt) + util.run_and_log(cons, ['dtc', src, '-O', 'dtb', '-o', dtb]) + return dtb diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py index bc54149e8f2..e63c25df537 100644 --- a/test/py/tests/test_event_dump.py +++ b/test/py/tests/test_event_dump.py @@ -16,6 +16,7 @@ def test_event_dump(u_boot_console): out = util.run_and_log(cons, ['scripts/event_dump.py', sandbox]) expect = '''.*Event type Id Source location -------------------- ------------------------------ ------------------------------ +EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_fixup.c:.* EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple.c:.* EVT_MISC_INIT_F sandbox_misc_init_f .*arch/sandbox/cpu/start.c:''' assert re.match(expect, out, re.MULTILINE) is not None diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py index 5856960be23..f45848484eb 100755 --- a/test/py/tests/test_fit.py +++ b/test/py/tests/test_fit.py @@ -7,6 +7,7 @@ import os import pytest import struct import u_boot_utils as util +import fit_util # Define a base ITS which we can adjust using % and a dictionary base_its = ''' @@ -126,7 +127,6 @@ def test_fit(u_boot_console): Return: Temporary filename """ - return os.path.join(cons.config.build_dir, leaf) def filesize(fname): @@ -150,67 +150,6 @@ def test_fit(u_boot_console): with open(fname, 'rb') as fd: return fd.read() - def make_dtb(): - """Make a sample .dts file and compile it to a .dtb - - Returns: - Filename of .dtb file created - """ - src = make_fname('u-boot.dts') - dtb = make_fname('u-boot.dtb') - with open(src, 'w') as fd: - fd.write(base_fdt) - util.run_and_log(cons, ['dtc', src, '-O', 'dtb', '-o', dtb]) - return dtb - - def make_its(params): - """Make a sample .its file with parameters embedded - - Args: - params: Dictionary containing parameters to embed in the %() strings - Returns: - Filename of .its file created - """ - its = make_fname('test.its') - with open(its, 'w') as fd: - print(base_its % params, file=fd) - return its - - def make_fit(mkimage, params): - """Make a sample .fit file ready for loading - - This creates a .its script with the selected parameters and uses mkimage to - turn this into a .fit image. - - Args: - mkimage: Filename of 'mkimage' utility - params: Dictionary containing parameters to embed in the %() strings - Return: - Filename of .fit file created - """ - fit = make_fname('test.fit') - its = make_its(params) - util.run_and_log(cons, [mkimage, '-f', its, fit]) - with open(make_fname('u-boot.dts'), 'w') as fd: - fd.write(base_fdt) - return fit - - def make_kernel(filename, text): - """Make a sample kernel with test data - - Args: - filename: the name of the file you want to create - Returns: - Full path and filename of the kernel it created - """ - fname = make_fname(filename) - data = '' - for i in range(100): - data += 'this %s %d is unlikely to boot\n' % (text, i) - with open(fname, 'w') as fd: - print(data, file=fd) - return fname - def make_ramdisk(filename, text): """Make a sample ramdisk with test data @@ -321,10 +260,10 @@ def test_fit(u_boot_console): - run code coverage to make sure we are testing all the code """ # Set up invariant files - control_dtb = make_dtb() - kernel = make_kernel('test-kernel.bin', 'kernel') + control_dtb = fit_util.make_dtb(cons, base_fdt, 'u-boot') + kernel = fit_util.make_kernel(cons, 'test-kernel.bin', 'kernel') ramdisk = make_ramdisk('test-ramdisk.bin', 'ramdisk') - loadables1 = make_kernel('test-loadables1.bin', 'lenrek') + loadables1 = fit_util.make_kernel(cons, 'test-loadables1.bin', 'lenrek') loadables2 = make_ramdisk('test-loadables2.bin', 'ksidmar') kernel_out = make_fname('kernel-out.bin') fdt = make_fname('u-boot.dtb') @@ -372,7 +311,7 @@ def test_fit(u_boot_console): } # Make a basic FIT and a script to load it - fit = make_fit(mkimage, params) + fit = fit_util.make_fit(cons, mkimage, base_its, params) params['fit'] = fit cmd = base_script % params @@ -403,7 +342,7 @@ def test_fit(u_boot_console): # Now a kernel and an FDT with cons.log.section('Kernel + FDT load'): params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr'] - fit = make_fit(mkimage, params) + fit = fit_util.make_fit(cons, mkimage, base_its, params) cons.restart_uboot() output = cons.run_command_list(cmd.splitlines()) check_equal(kernel, kernel_out, 'Kernel not loaded') @@ -415,7 +354,7 @@ def test_fit(u_boot_console): with cons.log.section('Kernel + FDT + Ramdisk load'): params['ramdisk_config'] = 'ramdisk = "ramdisk-1";' params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr'] - fit = make_fit(mkimage, params) + fit = fit_util.make_fit(cons, mkimage, base_its, params) cons.restart_uboot() output = cons.run_command_list(cmd.splitlines()) check_equal(ramdisk, ramdisk_out, 'Ramdisk not loaded') @@ -427,7 +366,7 @@ def test_fit(u_boot_console): params['loadables1_addr']) params['loadables2_load'] = ('load = <%#x>;' % params['loadables2_addr']) - fit = make_fit(mkimage, params) + fit = fit_util.make_fit(cons, mkimage, base_its, params) cons.restart_uboot() output = cons.run_command_list(cmd.splitlines()) check_equal(loadables1, loadables1_out, @@ -441,7 +380,7 @@ def test_fit(u_boot_console): params['kernel'] = make_compressed(kernel) params['fdt'] = make_compressed(fdt) params['ramdisk'] = make_compressed(ramdisk) - fit = make_fit(mkimage, params) + fit = fit_util.make_fit(cons, mkimage, base_its, params) cons.restart_uboot() output = cons.run_command_list(cmd.splitlines()) check_equal(kernel, kernel_out, 'Kernel not loaded') diff --git a/test/py/tests/test_vbe.py b/test/py/tests/test_vbe.py new file mode 100644 index 00000000000..559c2918868 --- /dev/null +++ b/test/py/tests/test_vbe.py @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2022 Google LLC +# +# Test addition of VBE + +import pytest + +import fit_util + +# Define a base ITS which we can adjust using % and a dictionary +base_its = ''' +/dts-v1/; + +/ { + description = "Example kernel"; + + images { + kernel-1 { + data = /incbin/("%(kernel)s"); + type = "kernel"; + arch = "sandbox"; + os = "linux"; + load = <0x40000>; + entry = <0x8>; + compression = "%(compression)s"; + + random { + compatible = "vbe,random-rand"; + vbe,size = <0x40>; + vbe,required; + }; + aslr1 { + compatible = "vbe,aslr-move"; + vbe,align = <0x100000>; + }; + aslr2 { + compatible = "vbe,aslr-rand"; + }; + efi-runtime { + compatible = "vbe,efi-runtime-rand"; + }; + wibble { + compatible = "vbe,wibble"; + }; + }; + + fdt-1 { + description = "snow"; + data = /incbin/("%(fdt)s"); + type = "flat_dt"; + arch = "sandbox"; + load = <%(fdt_addr)#x>; + compression = "%(compression)s"; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel-1"; + fdt = "fdt-1"; + }; + }; +}; +''' + +# Define a base FDT - currently we don't use anything in this +base_fdt = ''' +/dts-v1/; + +/ { + chosen { + }; +}; +''' + +# This is the U-Boot script that is run for each test. First load the FIT, +# then run the 'bootm' command, then run the unit test which checks that the +# working tree has the required things filled in according to the OS requests +# above (random, aslr2, etc.) +base_script = ''' +host load hostfs 0 %(fit_addr)x %(fit)s +fdt addr %(fit_addr)x +bootm start %(fit_addr)x +bootm loados +bootm prep +fdt addr +fdt print +ut bootstd vbe_test_fixup +''' + +@pytest.mark.boardspec('sandbox_flattree') +@pytest.mark.requiredtool('dtc') +def test_vbe(u_boot_console): + cons = u_boot_console + kernel = fit_util.make_kernel(cons, 'vbe-kernel.bin', 'kernel') + fdt = fit_util.make_dtb(cons, base_fdt, 'vbe-fdt') + fdt_out = fit_util.make_fname(cons, 'fdt-out.dtb') + + params = { + 'fit_addr' : 0x1000, + + 'kernel' : kernel, + + 'fdt' : fdt, + 'fdt_out' : fdt_out, + 'fdt_addr' : 0x80000, + 'fdt_size' : 0x1000, + + 'compression' : 'none', + } + mkimage = cons.config.build_dir + '/tools/mkimage' + fit = fit_util.make_fit(cons, mkimage, base_its, params, 'test-vbe.fit', + base_fdt) + params['fit'] = fit + cmd = base_script % params + + with cons.log.section('Kernel load'): + output = cons.run_command_list(cmd.splitlines()) + + # This is a little wonky since there are two tests running in CI. The final + # one is the 'ut bootstd' command above + failures = [line for line in output if 'Failures' in line] + assert len(failures) >= 1 and 'Failures: 0' in failures[-1] diff --git a/test/test-main.c b/test/test-main.c index d74df297c43..a98a77d68fc 100644 --- a/test/test-main.c +++ b/test/test-main.c @@ -165,16 +165,7 @@ static int dm_test_post_run(struct unit_test_state *uts) /* Ensure all the test devices are probed */ static int do_autoprobe(struct unit_test_state *uts) { - struct udevice *dev; - int ret; - - /* Scanning the uclass is enough to probe all the devices */ - for (ret = uclass_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_next_device(&dev)) - ; - - return ret; + return uclass_probe_all(UCLASS_TEST); } /* diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 84b7777e888..42ab81283d2 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -97,6 +97,7 @@ RUN apt-get update && apt-get install -y \ python3 \ python3-dev \ python3-pip \ + python3-pyelftools \ python3-sphinx \ python3-virtualenv \ rpm2cpio \ |