diff options
199 files changed, 6878 insertions, 413 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 31850ae5718..53a83eef7db 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -426,7 +426,7 @@ stages: cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/; fi if [[ "${TEST_PY_BD}" == "coreboot" ]]; then - wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom; + wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom; wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool; chmod a+x cbfstool; ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000; diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8010afae951..1df13261c2d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -69,7 +69,7 @@ stages: fi - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then wget -O - - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" | + "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" | xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom; wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" > diff --git a/MAINTAINERS b/MAINTAINERS index bf851cffd6b..84de9de5319 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,6 +132,7 @@ M: Tom Rini <trini@konsulko.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git F: arch/arm/ +F: arch/arm/dts/Makefile F: cmd/arm/ ARM ALTERA SOCFPGA @@ -633,6 +634,7 @@ F: include/dt-bindings/clock/stm32mp* F: include/dt-bindings/pinctrl/stm32-pinfunc.h F: include/dt-bindings/reset/stm32mp* F: include/stm32_rcc.h +F: tools/logos/st.bmp F: tools/stm32image.c N: stm N: stm32 @@ -1597,7 +1599,8 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ UFS -M: Faiz Abbas <faiz_abbas@ti.com> +M: Bhupesh Sharma <bhupesh.sharma@linaro.org> +M: Neha Malcom Francis <n-francis@ti.com> S: Maintained F: drivers/ufs/ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd518064f35..85fd5b1157b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -178,6 +178,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-soquartz-cm4.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ + rk3568-lubancat-2.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ @@ -254,9 +255,22 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-ventana.dtb \ tegra20-colibri.dtb \ tegra30-apalis.dtb \ + tegra30-asus-nexus7-grouper-PM269.dtb \ + tegra30-asus-nexus7-grouper-E1565.dtb \ + tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-p1801-t.dtb \ + tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf300tl.dtb \ + tegra30-asus-tf600t.dtb \ + tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ tegra30-colibri.dtb \ + tegra30-htc-endeavoru.dtb \ + tegra30-lg-p880.dtb \ + tegra30-lg-p895.dtb \ tegra30-tec-ng.dtb \ tegra114-dalmore.dtb \ tegra124-apalis.dtb \ diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index 09694b41e53..d88dee80573 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -12,6 +12,31 @@ &uart0 { bootph-all; - clock-frequency = <24000000>; - status = "okay"; +}; + +&pinctrl { + bootph-some-ram; + + uart0 { + bootph-some-ram; + }; + rtc { + bootph-some-ram; + }; +}; + +&uart0_xfer { + bootph-some-ram; +}; + +&uart0_cts { + bootph-some-ram; +}; + +&uart0_rts { + bootph-some-ram; +}; + +&rtc_32k { + bootph-some-ram; }; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 849854302ee..6904515b969 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -54,7 +54,7 @@ }; &spi0 { - spi_flash: spiflash@0 { + spi_flash: flash@0 { bootph-all; }; }; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 1b0f7e4551e..f69a38f42d2 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -345,7 +345,7 @@ &spi0 { status = "okay"; - spiflash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index ce96ce40a73..a9f2536de2a 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -26,6 +26,12 @@ 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; }; + + rng: rng@ff060000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff060000 0x0 0x4000>; + status = "okay"; + }; }; &cru { diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi new file mode 100644 index 00000000000..27c62775233 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Rockchip Electronics Co., Ltd + * (C) Copyright 2023 Andy Yan <andyshrk@163.com> + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts new file mode 100644 index 00000000000..e653b067aa5 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2.dts @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "EmbedFire LubanCat 2"; + compatible = "embedfire,lubancat-2", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user-led { + label = "user_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + dc_5v: dc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_5v>; + }; + + vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "m2_pcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_m2_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "minipcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_mini_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb30_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg_vbus"; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_otg_vbus_en>; + pinctrl-names = "default"; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x22>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x21>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gic { + mbi-ranges = <94 31>, <229 31>, <289 31>; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2_pcie>; + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_mini_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm8 { + status = "okay"; +}; + +&pwm9 { + status = "disabled"; +}; + +&pwm10 { + status = "disabled"; +}; + +&pwm14 { + status = "disabled"; +}; + +&spi3 { + pinctrl-0 = <&spi3m1_pins>; + status = "disabled"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&sdhci { + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + supports-emmc; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +/* USB OTG/USB Host_1 USB 2.0 Comb */ +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg_vbus>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Host_2/USB Host_3 USB 2.0 Comb */ +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */ +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +/* USB3.0 Host */ +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&pinctrl { + leds { + user_led_pin: user-status-led-pin { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index d21b1820522..32f687f2924 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -126,12 +126,11 @@ &sdhci { bootph-pre-ram; - status = "okay"; + max-frequency = <200000000>; }; &sdmmc0 { bootph-pre-ram; - status = "okay"; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 19b5451db44..522cffb1ac9 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -169,7 +169,7 @@ ltdc_pins: ltdc@0 { pins { pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */ - <STM32_PINMUX('G',12, AF14)>, /* B4 */ + <STM32_PINMUX('G',12, AF9)>, /* B4 */ <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */ <STM32_PINMUX('I',10, AF14)>, /* HSYNC */ <STM32_PINMUX('I',14, AF14)>, /* CLK */ diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index b2dce3a29f3..27e0c382678 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -258,4 +258,133 @@ bias-disable; }; }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */ + <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ + <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ + <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */ + <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */ + <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ + <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index d94ba254726..d163c267e34 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -397,12 +397,42 @@ status = "disabled"; }; + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x5>, + <&dmamux1 46 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; resets = <&rcc UART4_R>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x5>, + <&dmamux1 64 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x5>, + <&dmamux1 66 0x400 0x1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -442,6 +472,32 @@ status = "disabled"; }; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x5>, + <&dmamux1 80 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x5>, + <&dmamux1 82 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers1: timer@44000000 { #address-cells = <1>; #size-cells = <0>; @@ -524,6 +580,19 @@ }; }; + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x5>, + <&dmamux1 72 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s1: audio-controller@44004000 { compatible = "st,stm32h7-i2s"; reg = <0x44004000 0x400>; @@ -748,6 +817,32 @@ status = "disabled"; }; + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s4: audio-controller@4c002000 { compatible = "st,stm32h7-i2s"; reg = <0x4c002000 0x400>; @@ -1001,8 +1096,6 @@ reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; clocks = <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index c40686cb2b9..f0900ca672b 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -19,6 +19,13 @@ aliases { serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory@c0000000 { @@ -267,8 +274,41 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index a9d2bec9901..e86d989dd35 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1880,6 +1880,21 @@ }; }; + spi1_pins_b: spi1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ @@ -2163,7 +2178,7 @@ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins2 { pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ @@ -2181,7 +2196,7 @@ pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins3 { pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ @@ -2448,19 +2463,4 @@ bias-disable; }; }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ - bias-disable; - }; - }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index b3baacbb269..21d11be328c 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1148,8 +1148,8 @@ usbotg_hs: usb-otg@49000000 { compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index 4c8be9c8eb2..0da3667ab1e 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -17,9 +17,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; }; chosen { diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 2bc92ef3aeb..ab13e340f4e 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -18,9 +18,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; serial3 = &usart2; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fe5c8f25cec..3541a17dceb 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -16,6 +16,10 @@ model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + aliases { + serial0 = &uart4; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -65,15 +69,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; - }; - - aliases { - serial0 = &uart4; }; sd_switch: regulator-sd_switch { @@ -148,10 +143,6 @@ status = "okay"; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 542226cfcfd..ba8e9d9a42f 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -14,16 +14,15 @@ model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - serial0 = &uart4; serial1 = &usart3; ethernet0 = ðernet0; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + clocks { clk_ext_camera: clk-ext-camera { #clock-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index de761743b24..d3b85a8764d 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -450,6 +449,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index a808620e121..f12941b05f6 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -153,6 +153,20 @@ }; &rcc { + /* + * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick + * used in stm32mp15xx-dhcom-som.dtsi is not supported by the + * U-Boot clock framework. + */ + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; + + /* The MCO2 is already configured correctly, remove those. */ + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 49b3e768c89..f4de6c0b758 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -8,6 +8,12 @@ #include <dt-bindings/mfd/st,stpmic1.h> / { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -53,11 +59,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -159,10 +160,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index e19001ee2bd..fa942d26078 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -27,7 +27,13 @@ spi@7000c380 { status = "okay"; - spi-max-frequency = <25000000>; + spi-max-frequency = <48000000>; + + flash@0 { + compatible = "winbond,w25q80bl", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <48000000>; + }; }; pcie@80003000 { diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi new file mode 100644 index 00000000000..4fa980f24f9 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + nvidia,180-rotation; + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + output-low; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 50000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + + hactive = <800>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + + vactive = <1280>; + vfront-porch = <5>; + vback-porch = <32>; + vsync-len = <1>; + }; + }; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts new file mode 100644 index 00000000000..a98d3e21455 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-grouper-common.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; + compatible = "asus,grouper", "nvidia,tegra30"; + + i2c@7000d000 { + pmic: max77663@3c { + compatible = "maxim,max77663"; + reg = <0x3c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo3 { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts new file mode 100644 index 00000000000..44ea218a472 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-grouper-common.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; + compatible = "asus,grouper", "nvidia,tegra30"; + + i2c@7000d000 { + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts new file mode 100644 index 00000000000..812d5a1ba70 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-grouper-common.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; + compatible = "asus,tilapia", "nvidia,tegra30"; + + i2c@7000d000 { + pmic: max77663@3c { + compatible = "maxim,max77663"; + reg = <0x3c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo3 { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + }; + }; + }; + + panel { + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <81750000>; + + hactive = <800>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + + vactive = <1280>; + vfront-porch = <5>; + vback-porch = <2>; + vsync-len = <1>; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts new file mode 100644 index 00000000000..4b2dc61713c --- /dev/null +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Portable AiO P1801-T"; + compatible = "asus,p1801-t", "nvidia,tegra30"; + + /delete-node/ host1x@50000000; + /delete-node/ pwm@7000a000; + + /delete-node/ backlight; + /delete-node/ panel; + + /delete-node/ regulator-pnl; + /delete-node/ regulator-bl; +}; diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts new file mode 100644 index 00000000000..54f359ef960 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf201.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Prime TF201"; + compatible = "asus,tf201", "nvidia,tegra30"; +}; diff --git a/arch/arm/dts/tegra30-asus-tf300t.dts b/arch/arm/dts/tegra30-asus-tf300t.dts new file mode 100644 index 00000000000..db08488420e --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf300t.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Pad TF300T"; + compatible = "asus,tf300t", "nvidia,tegra30"; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-tf300tg.dts b/arch/arm/dts/tegra30-asus-tf300tg.dts new file mode 100644 index 00000000000..6f42182c99d --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf300tg.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Pad 3G TF300TG"; + compatible = "asus,tf300tg", "nvidia,tegra30"; +}; diff --git a/arch/arm/dts/tegra30-asus-tf300tl.dts b/arch/arm/dts/tegra30-asus-tf300tl.dts new file mode 100644 index 00000000000..242f79170c4 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf300tl.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Pad LTE TF300TL"; + compatible = "asus,tf300tl", "nvidia,tegra30"; +}; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts new file mode 100644 index 00000000000..c9b8f4fa140 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS VivoTab RT TF600T"; + compatible = "asus,tf600t", "nvidia,tegra30"; + + aliases { + spi0 = &spi4; + }; + + /delete-node/ host1x@50000000; + + pmic_i2c: i2c@7000d000 { + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + regulators { + vdd_1v2_bl: vdd1 { + regulator-name = "vdd_1v2_backlight"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + /delete-node/ ldo2; + /delete-node/ ldo3; + + /* uSD slot VDDIO */ + vddio_usd: ldo5 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + avdd_dsi_csi: ldo6 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + }; + + spi4: spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + spi-flash@1 { + compatible = "winbond,w25q32", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + backlight { + power-supply = <&vdd_1v2_bl>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + /delete-node/ panel; + + vdd_usd: regulator-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /delete-node/ regulator-pnl; + /delete-node/ regulator-bl; +}; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts new file mode 100644 index 00000000000..d530527c9f8 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Infinity TF700T"; + compatible = "asus,tf700t", "nvidia,tegra30"; + + /delete-node/ host1x@50000000; + + /delete-node/ panel; +}; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi new file mode 100644 index 00000000000..4eee1df084c --- /dev/null +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &gen1_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3100000>; + }; + }; + }; + }; + + sdmmc1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 4000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + + hactive = <1280>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + + vactive = <800>; + vfront-porch = <3>; + vback-porch = <12>; + vsync-len = <5>; + }; + }; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts new file mode 100644 index 00000000000..c55e193d1d7 --- /dev/null +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/* This dts file describes the HTC One X smartphone */ +/* CPU Speedo ID 4, Soc Speedo ID 1, CPU Process: 1, Core Process: 0 */ + +#include <dt-bindings/input/input.h> + +#include "tegra30.dtsi" + +/ { + model = "HTC One X"; + compatible = "htc,endeavoru", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&dsia>; + }; + }; + + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel = <&panel>; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + /* Texas Instruments TPS80032 PMIC */ + pmic: tps80032@48 { + compatible = "ti,tps80032"; + reg = <0x48>; + + regulators { + /* DSI VDD */ + avdd_dsi_csi: ldo1 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + micro_usb: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "nvidia,tegra-pwm-backlight"; + + nvidia,pwm-source = <1>; + nvidia,default-brightness = <0x8E>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + panel: panel { + compatible = "htc,edge-panel"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_3v3_panel>; + vddio-supply = <&vdd_1v8_panel>; + + backlight = <&backlight>; + }; + + vcore_emmc: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "vdd_2v85_sdmmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + gpio = <&gpio TEGRA_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_3v3_panel: regulator-lcm { + compatible = "regulator-fixed"; + regulator-name = "v_lcm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(E, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_panel: regulator-lcmio { + compatible = "regulator-fixed"; + regulator-name = "v_lcmio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts new file mode 100644 index 00000000000..81d364310d0 --- /dev/null +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus 4X HD"; + compatible = "lge,p880", "nvidia,tegra30"; + + aliases { + mmc1 = &sdmmc3; /* uSD slot */ + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + }; + + panel: panel { + compatible = "jdi,dx12d100vm0eaa"; + + enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; +}; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts new file mode 100644 index 00000000000..074205d5a98 --- /dev/null +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus Vu"; + compatible = "lge,p895", "nvidia,tegra30"; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + }; + + panel: panel { + compatible = "hitachi,tx13d100vm0eaa"; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + renesas,gamma = <3>; + renesas,inversion; + renesas,contrast; + + vcc-supply = <&vcc_3v0_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + }; + + vcc_3v0_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + iovcc_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi new file mode 100644 index 00000000000..922e39915e5 --- /dev/null +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &gen2_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + spi0 = &dsi_spi; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&bridge>; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + backlight: lm3533@36 { + compatible = "ti,lm3533"; + reg = <0x36>; + + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + default-brightness-level = <128>; + }; + + muic@44 { + compatible = "maxim,max14526-muic"; + reg = <0x44>; + + maxim,ap-usb; + + usif-gpios = <&gpio TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>; + dp2t-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>; + }; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + regulators { + vdd_1v8_vio: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_usd: ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + dsi_spi: spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + + bridge: bridge-spi@2 { + compatible = "solomon,ssd2825"; + reg = <2>; + + spi-cpol; + spi-cpha; + + spi-max-frequency = <1000000>; + + power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>; + + clocks = <&ssd2825_refclk>; + clock-names = "tx_clk"; + + panel = <&panel>; + }; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + micro_usb: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + ssd2825_refclk: clock-ssd2825 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "ssd2825-refclk"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h index 86c906bb0ed..84b63e4d568 100644 --- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h +++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h @@ -189,6 +189,21 @@ enum { DCLK_VOP_DIV_SHIFT = 0, DCLK_VOP_DIV_MASK = 0xff, + /* CRU_CLKSEL_CON10 */ + /* CRU_CLKSEL_CON13 */ + /* CRU_CLKSEL_CON16 */ + /* CRU_CLKSEL_CON19 */ + /* CRU_CLKSEL_CON22 */ + CLK_UART_PLL_SEL_SHIFT = 13, + CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT, + CLK_UART_PLL_SEL_DPLL = 0, + CLK_UART_PLL_SEL_VPLL0, + CLK_UART_PLL_SEL_VPLL1, + CLK_UART_PLL_SEL_480M, + CLK_UART_PLL_SEL_24M, + CLK_UART_DIV_CON_SHIFT = 0, + CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT, + /* CRU_CLK_SEL25_CON */ /* CRU_CLK_SEL26_CON */ /* CRU_CLK_SEL27_CON */ diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 13ea4aba8eb..9778790f348 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -15,6 +15,8 @@ # include <asm/arch-rockchip/cru_rk3288.h> #elif defined(CONFIG_ROCKCHIP_RK3399) # include <asm/arch-rockchip/cru_rk3399.h> +#elif defined(CONFIG_ROCKCHIP_RK3568) +#include <asm/arch-rockchip/cru_rk3568.h> #endif /* CRU_GLB_RST_ST */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 399f19ad21e..9c7ddd751f7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -106,6 +106,8 @@ struct rk3568_cru { unsigned int emmc_con[2];/* Address Offset: 0x0598 */ }; +#define rockchip_cru rk3568_cru + check_member(rk3568_cru, mode_con00, 0xc0); check_member(rk3568_cru, softrst_con[0], 0x400); @@ -493,7 +495,7 @@ enum { /* CRU_CLK_SEL81_CON */ CPLL_25M_DIV_SHIFT = 8, - CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT, + CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT, CPLL_50M_DIV_SHIFT = 0, CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h index 5b8e0bd8d16..f3f2ad8e3f2 100644 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ b/arch/arm/include/asm/arch-tegra/fuse.h @@ -19,4 +19,11 @@ struct fuse_regs { u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ }; +/** + * Calculate SoC UID + * + * Return: uid if ok, 0 on error + */ +unsigned long long tegra_chip_uid(void); + #endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index d5254886bed..78b775f449d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -333,7 +333,7 @@ phys_size_t get_effective_memsize(void) } } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { ulong top_addr; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index d3a95730be5..4c67f1aba4d 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define USABLE_RAM_SIZE 0x80000000ULL -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 49da93d54b4..a279582f4f6 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + imply OF_LIBFDT_OVERLAY imply TPL_DM imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index a7cc91a952c..cbd2ea047dc 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -280,15 +280,5 @@ void spl_board_init(void) if (cru->glb_rst_st != 0) rk3399_force_power_on_reset(); } - - if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) { - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - if (regulators_enable_boot_on(false)) - debug("%s: Cannot enable boot on regulator\n", - __func__); - } } #endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 1d17a740ade..99ecbdc3412 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -216,7 +216,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 30be6404252..87280e2ba7c 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -112,19 +112,6 @@ void board_init_f(ulong dummy) { int ret; -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - debug("\nspl:debug uart enabled in %s\n", __func__); -#endif - board_early_init_f(); ret = spl_early_init(); diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 80ba5c27741..7f37b0d2aa2 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -40,7 +40,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { phys_size_t size; phys_addr_t reg; diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 39b5200949a..8cdeb0ab3f2 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -729,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); setbits_le32(STM32_PWR_BASE + PWR_MPUCR, - PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 391a65a5495..78597ad932c 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -64,7 +64,7 @@ static struct mm_region sunxi_mem_map[] = { }; struct mm_region *mem_map = sunxi_mem_map; -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* Some devices (like the EMAC) have a 32-bit DMA limit. */ if (gd->ram_top > (1ULL << 32)) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 9147050b323..a5733b0bf6b 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -32,6 +32,10 @@ endif obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-y += pmc.o +ifndef CONFIG_TEGRA186 +obj-y += fuse.o +endif + obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ obj-$(CONFIG_TEGRA114) += tegra114/ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 0df18360ca6..981768bb0e1 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -403,7 +403,7 @@ int dram_init_banksize(void) * This function is called before dram_init_banksize(), so we can't simply * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { ulong ram_top; diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c new file mode 100644 index 00000000000..83bd5055384 --- /dev/null +++ b/arch/arm/mach-tegra/fuse.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <linux/delay.h> +#include <asm/io.h> + +#include <asm/arch/tegra.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/fuse.h> + +#include "cpu.h" + +#define FUSE_UID_LOW 0x108 +#define FUSE_UID_HIGH 0x10c + +#define FUSE_VENDOR_CODE 0x200 +#define FUSE_FAB_CODE 0x204 +#define FUSE_LOT_CODE_0 0x208 +#define FUSE_LOT_CODE_1 0x20c +#define FUSE_WAFER_ID 0x210 +#define FUSE_X_COORDINATE 0x214 +#define FUSE_Y_COORDINATE 0x218 + +#define FUSE_VENDOR_CODE_MASK 0xf +#define FUSE_FAB_CODE_MASK 0x3f +#define FUSE_WAFER_ID_MASK 0x3f +#define FUSE_X_COORDINATE_MASK 0x1ff +#define FUSE_Y_COORDINATE_MASK 0x1ff + +static u32 tegra_fuse_readl(unsigned long offset) +{ + return readl(NV_PA_FUSE_BASE + offset); +} + +static void tegra_fuse_init(void) +{ + u32 reg; + + /* + * Performed by downstream and is not + * documented by TRM. Whithout setting + * this bit fuse region will not work. + */ + reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48); + reg |= BIT(28); + writel(reg, NV_PA_CLK_RST_BASE + 0x48); + + clock_enable(PERIPH_ID_FUSE); + udelay(2); + reset_set_enable(PERIPH_ID_FUSE, 0); +} + +unsigned long long tegra_chip_uid(void) +{ + u64 uid = 0ull; + u32 reg; + u32 cid; + u32 vendor; + u32 fab; + u32 lot; + u32 wafer; + u32 x; + u32 y; + u32 i; + + tegra_fuse_init(); + + /* This used to be so much easier in prior chips. Unfortunately, there + is no one-stop shopping for the unique id anymore. It must be + constructed from various bits of information burned into the fuses + during the manufacturing process. The 64-bit unique id is formed + by concatenating several bit fields. The notation used for the + various fields is <fieldname:size_in_bits> with the UID composed + thusly: + <CID:4><VENDOR:4><FAB:6><LOT:26><WAFER:6><X:9><Y:9> + Where: + Field Bits Position Data + ------- ---- -------- ---------------------------------------- + CID 4 60 Chip id + VENDOR 4 56 Vendor code + FAB 6 50 FAB code + LOT 26 24 Lot code (5-digit base-36-coded-decimal, + re-encoded to 26 bits binary) + WAFER 6 18 Wafer id + X 9 9 Wafer X-coordinate + Y 9 0 Wafer Y-coordinate + ------- ---- + Total 64 + */ + + switch (tegra_get_chip()) { + case CHIPID_TEGRA20: + /* T20 has simple calculation */ + return ((unsigned long long)tegra_fuse_readl(FUSE_UID_HIGH) << 32ull) | + (unsigned long long)tegra_fuse_readl(FUSE_UID_LOW); + case CHIPID_TEGRA30: + /* T30 chip id is 0 */ + cid = 0; + break; + case CHIPID_TEGRA114: + /* T11x chip id is 1 */ + cid = 1; + break; + case CHIPID_TEGRA124: + /* T12x chip id is 3 */ + cid = 3; + break; + case CHIPID_TEGRA210: + /* T210 chip id is 5 */ + cid = 5; + default: + return 0; + } + + vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK; + fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK; + + /* Lot code must be re-encoded from a 5 digit base-36 'BCD' number + to a binary number. */ + lot = 0; + reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2; + + for (i = 0; i < 5; ++i) { + u32 digit = (reg & 0xFC000000) >> 26; + lot *= 36; + lot += digit; + reg <<= 6; + } + + wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK; + x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK; + y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK; + + uid = ((unsigned long long)cid << 60ull) + | ((unsigned long long)vendor << 56ull) + | ((unsigned long long)fab << 50ull) + | ((unsigned long long)lot << 24ull) + | ((unsigned long long)wafer << 18ull) + | ((unsigned long long)x << 9ull) + | ((unsigned long long)y << 0ull); + + return uid; +} diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 85b8ce294f2..3e478b3b7b3 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -20,10 +20,26 @@ config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" select BOARD_LATE_INIT +config TARGET_ENDEAVORU + bool "HTC Endeavoru T30 board" + select BOARD_LATE_INIT + +config TARGET_GROUPER + bool "Asus and Google Grouper board" + select BOARD_LATE_INIT + config TARGET_TEC_NG bool "Avionic Design TEC-NG board" select BOARD_LATE_INIT +config TARGET_TRANSFORMER_T30 + bool "Asus Tegra30 Transformer board" + select BOARD_LATE_INIT + +config TARGET_X3_T30 + bool "LG X3 Tegra30 board" + select BOARD_LATE_INIT + endchoice config SYS_SOC @@ -33,6 +49,10 @@ source "board/toradex/apalis_t30/Kconfig" source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" source "board/toradex/colibri_t30/Kconfig" +source "board/htc/endeavoru/Kconfig" +source "board/asus/grouper/Kconfig" source "board/avionic-design/tec-ng/Kconfig" +source "board/asus/transformer-t30/Kconfig" +source "board/lg/x3-t30/Kconfig" endif diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index 15d1eff2ba7..676c305fd3e 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -76,7 +76,7 @@ void board_init_f(ulong dummy) } #endif /* CONFIG_SPL_BUILD */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 85cb084c13f..5b1311d8b5b 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -77,7 +77,7 @@ phys_size_t get_effective_memsize(void) return UBOOT_RAM_SIZE_MAX; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 44e11bd56c5..94d8018407e 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c index d6d4a41d25e..8657fcd165c 100644 --- a/arch/riscv/cpu/fu740/dram.c +++ b/arch/riscv/cpu/fu740/dram.c @@ -20,7 +20,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_64BIT /* diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 44e11bd56c5..94d8018407e 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 2ad3f2044a2..1a9fa46d14b 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index 1295121ae5b..f477d513efc 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -25,7 +25,7 @@ #include <asm/arch/pei_data.h> #include <asm/arch/pm.h> -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return mrc_common_board_get_usable_ram_top(total_size); } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index f4ee4cdf5d8..26352df421f 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -27,7 +27,7 @@ unsigned int install_e820_map(unsigned int max_entries, * address, and how far U-Boot is moved by relocation are set in the global * data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { uintptr_t dest_addr = 0; int i; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 19a25dd6408..d8920effd39 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { struct efi_mem_desc *desc, *end; struct efi_entry_memmap *map; diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index f3086db42c4..56f3326146c 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR; -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return (ulong)efi_get_ram_base() + gd->ram_size; } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 0718aefbb1f..95a826da713 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CMOS_OFFSET_MRC_SEED_S3 156 #define CMOS_OFFSET_MRC_SEED_CHK 160 -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return mrc_common_board_get_usable_ram_top(total_size); } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index 1a52d1dc522..d83abf00527 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -72,7 +72,7 @@ int dram_init_banksize(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return qemu_get_low_memory_size(); } diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 8b1ee2d5ae5..ad98f3e07ba 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -184,7 +184,7 @@ int dram_init_banksize(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return gd->ram_size; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index d748d5c7d46..fbb33b246e5 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -48,7 +48,7 @@ static struct sbl_memory_map_info *get_memory_map_info(void) * @total_size: The memory size that u-boot occupies * Return: : The top available memory address lower than 4GB */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { struct sbl_memory_map_info *data; int i; diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 8a4b1c5d2d7..ee74a1f0433 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -204,7 +204,7 @@ unsigned int install_e820_map(unsigned int max_entries, * address, and how far U-Boot is moved by relocation are set in the global * data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { struct sfi_table_simple *sb; struct sfi_mem_entry *mentry; diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 02a8b0f1527..3acc58ad74b 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -77,7 +77,7 @@ int x86_cleanup_before_linux(void); void x86_enable_caches(void); void x86_disable_caches(void); int x86_init_cache(void); -phys_size_t board_get_usable_ram_top(phys_size_t total_size); +phys_addr_t board_get_usable_ram_top(phys_size_t total_size); int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index 5825221d1e5..eee9ce54b1c 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -34,7 +34,7 @@ int dram_init(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return fsp_get_usable_lowmem_top(gd->arch.hob_list); } diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index f9ea1ab3baa..a1432239cfc 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -77,7 +77,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { if (!ll_boot_init()) return gd->ram_size; diff --git a/board/anbernic/rgxx3_rk3566/MAINTAINERS b/board/anbernic/rgxx3_rk3566/MAINTAINERS index 1c0d3fe7b5b..7970e5a4aad 100644 --- a/board/anbernic/rgxx3_rk3566/MAINTAINERS +++ b/board/anbernic/rgxx3_rk3566/MAINTAINERS @@ -3,4 +3,7 @@ M: Chris Morgan <macromorgan@hotmail.com> S: Maintained F: board/anbernic/rgxx3_rk3566 F: include/configs/anbernic-rgxx3-rk3566.h -F: configs/anbernic-rgxx3_defconfig +F: configs/anbernic-rgxx3-rk3566_defconfig +F: arch/arm/dts/rk3566-anbernic-rgxx3.dts +F: arch/arm/dts/rk3566-anbernic-rgxx3.dtsi +F: arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS index 8c905686de7..1cc9aaa29a8 100644 --- a/board/armltd/corstone1000/MAINTAINERS +++ b/board/armltd/corstone1000/MAINTAINERS @@ -1,6 +1,6 @@ CORSTONE1000 BOARD -M: Rui Miguel Silva <rui.silva@linaro.org> -M: Vishnu Banavath <vishnu.banavath@arm.com> +M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +M: Xueliang Zhong <xueliang.zhong@arm.com> S: Maintained F: board/armltd/corstone1000/ F: include/configs/corstone1000.h diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig new file mode 100644 index 00000000000..912c6c5fbae --- /dev/null +++ b/board/asus/grouper/Kconfig @@ -0,0 +1,22 @@ +if TARGET_GROUPER + +config SYS_BOARD + default "grouper" + +config SYS_VENDOR + default "asus" + +config SYS_CONFIG_NAME + default "grouper" + +config GROUPER_TPS65911 + bool "Enable support TI TPS65911 PMIC" + select CMD_POWEROFF + default n + +config GROUPER_MAX77663 + bool "Enable support MAXIM MAX77663 PMIC" + select CMD_POWEROFF + default n + +endif diff --git a/board/asus/grouper/MAINTAINERS b/board/asus/grouper/MAINTAINERS new file mode 100644 index 00000000000..18b4f0641f4 --- /dev/null +++ b/board/asus/grouper/MAINTAINERS @@ -0,0 +1,10 @@ +GROUPER BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/asus/grouper/ +F: configs/grouper_E1565.config +F: configs/grouper_PM269.config +F: configs/tilapia.config +F: configs/grouper_common_defconfig +F: doc/board/asus/grouper_common.rst +F: include/configs/grouper.h diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile new file mode 100644 index 00000000000..e4a477a3669 --- /dev/null +++ b/board/asus/grouper/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_GROUPER_MAX77663) += grouper-spl-max.o +obj-$(CONFIG_GROUPER_TPS65911) += grouper-spl-ti.o +endif + +obj-y += grouper.o diff --git a/board/asus/grouper/grouper-spl-max.c b/board/asus/grouper/grouper-spl-max.c new file mode 100644 index 00000000000..844383766a7 --- /dev/null +++ b/board/asus/grouper/grouper-spl-max.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 Grouper MAX SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define MAX77663_I2C_ADDR (0x3C << 1) + +#define MAX77663_REG_SD0 0x16 +#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) +#define MAX77663_REG_SD1 0x17 +#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) +#define MAX77663_REG_LDO4 0x2B +#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) + +#define MAX77663_REG_GPIO4 0x3A +#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); + udelay(1000); + + /* Bring up VDD_RTC to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); + udelay(10 * 1000); + + /* Set 32k-out gpio state */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); +} diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c new file mode 100644 index 00000000000..e5b78f01215 --- /dev/null +++ b/board/asus/grouper/grouper-spl-ti.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 Grouper TI SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c new file mode 100644 index 00000000000..2769313e681 --- /dev/null +++ b/board/asus/grouper/grouper.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <fdt_support.h> +#include <i2c.h> +#include <log.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/gpio.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include "pinmux-config-grouper.h" + +#define TPS65911_I2C_ADDRESS 0x2D + +#define TPS65911_REG_LDO1 0x30 +#define TPS65911_REG_DEVCTRL 0x3F +#define DEVCTRL_PWR_OFF_MASK BIT(7) +#define DEVCTRL_DEV_ON_MASK BIT(2) +#define DEVCTRL_DEV_OFF_MASK BIT(0) + +#define MAX77663_I2C_ADDRESS 0x3C + +#define MAX77663_REG_SD2 0x18 +#define MAX77663_REG_LDO3 0x29 +#define MAX77663_REG_ONOFF_CFG1 0x41 +#define ONOFF_PWR_OFF BIT(1) + +#ifdef CONFIG_CMD_POWEROFF +#ifdef CONFIG_GROUPER_TPS65911 +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS65911_REG_DEVCTRL, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= DEVCTRL_PWR_OFF_MASK; + + ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= DEVCTRL_DEV_OFF_MASK; + data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK; + + ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + + printf("Failed to power off!!!\n"); + return 1; +} +#endif /* CONFIG_GROUPER_TPS65911 */ + +#ifdef CONFIG_GROUPER_MAX77663 +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= ONOFF_PWR_OFF; + + ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + + printf("Failed to power off!!!\n"); + return 1; +} +#endif /* CONFIG_GROUPER_MAX77663 */ +#endif /* CONFIG_CMD_POWEROFF */ + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(grouper_pinmux_common, + ARRAY_SIZE(grouper_pinmux_common)); + + pinmux_config_drvgrp_table(grouper_padctrl, + ARRAY_SIZE(grouper_padctrl)); +} + +#ifdef CONFIG_MMC_SDHCI_TEGRA +static void __maybe_unused tps65911_voltage_init(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return; + } + + /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */ + ret = dm_i2c_reg_write(dev, TPS65911_REG_LDO1, 0xC9); + if (ret) + log_debug("vcore_emmc set failed: %d\n", ret); +} + +static void __maybe_unused max77663_voltage_init(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return; + } + + /* 0x60 for 1.8v, bit7:0 = voltage */ + ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60); + if (ret) + log_debug("vdd_1v8_vio set failed: %d\n", ret); + + /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC); + if (ret) + log_debug("vcore_emmc set failed: %d\n", ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ +#ifdef CONFIG_GROUPER_MAX77663 + /* Bring up eMMC power on MAX PMIC */ + max77663_voltage_init(); +#endif + +#ifdef CONFIG_GROUPER_TPS65911 + /* Bring up eMMC power on TI PMIC */ + tps65911_voltage_init(); +#endif +} +#endif /* MMC */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif + +void nvidia_board_late_init(void) +{ + char serialno_str[17]; + + /* Set chip id as serialno */ + sprintf(serialno_str, "%016llx", tegra_chip_uid()); + env_set("serial#", serialno_str); + env_set("platform", "Tegra 3 T30"); +} diff --git a/board/asus/grouper/pinmux-config-grouper.h b/board/asus/grouper/pinmux-config-grouper.h new file mode 100644 index 00000000000..98134f74f1a --- /dev/null +++ b/board/asus/grouper/pinmux-config-grouper.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _PINMUX_CONFIG_GROUPER_H_ +#define _PINMUX_CONFIG_GROUPER_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config grouper_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* HDMI-CEC pinmux */ + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, RSVD1, NORMAL, TRISTATE, OUTPUT), + + /* DAP3 pinmux */ + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, TRISTATE, INPUT), + + DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, INPUT), + + /* CLK2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + + /* LCD pinmux */ + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + + /* VI-group pinmux */ + LV_PINMUX(VI_D0_PT4, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, SDMMC2, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), + + /* UART-B pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + + /* UART-C pinmux */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + + /* U-gpio group pinmux */ + DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU6, RSVD4, NORMAL, NORMAL, INPUT), + + /* DAP4 pinmux */ + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* CLK3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(PCC1, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT), + + /* CLK */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* DAP1 pinmux */ + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + + /* CLK1 pinmux */ + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + + /* DAP2 pinmux */ + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, NORMAL, NORMAL, INPUT), + + /* PEX pinmux */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, OUTPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N_PJ0, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, PWM2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD14_PH6, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD15_PH7, RSVD1, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_RST_N_PI4, NAND, UP, NORMAL, OUTPUT), +}; + +static struct pmux_drvgrp_config grouper_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_GROUPER_H_ */ diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig new file mode 100644 index 00000000000..3c36f4ada20 --- /dev/null +++ b/board/asus/transformer-t30/Kconfig @@ -0,0 +1,23 @@ +if TARGET_TRANSFORMER_T30 + +config SYS_BOARD + default "transformer-t30" + +config SYS_VENDOR + default "asus" + +config SYS_CONFIG_NAME + default "transformer-t30" + +config TRANSFORMER_SPI_BOOT + bool "Enable support for SPI based flash" + select TEGRA20_SLINK + select DM_SPI_FLASH + select SPI_FLASH_WINBOND + default n + help + Tegra 3 based Transformers with Windows RT have core + boot sequence (BCT and EBT) on separate SPI FLASH + memory with 4MB size. + +endif diff --git a/board/asus/transformer-t30/MAINTAINERS b/board/asus/transformer-t30/MAINTAINERS new file mode 100644 index 00000000000..c6c15323b28 --- /dev/null +++ b/board/asus/transformer-t30/MAINTAINERS @@ -0,0 +1,15 @@ +TRANSFORMER BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/asus/transformer-t30/ +F: configs/p1801-t.config +F: configs/tf201.config +F: configs/tf300t.config +F: configs/tf300tg.config +F: configs/tf300tl.config +F: configs/tf600t.config +F: configs/tf700t.config +F: configs/transformer_t30_defconfig +F: doc/board/asus/transformer_t30.rst +F: include/configs/transformer-common.h +F: include/configs/transformer-t30.h diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile new file mode 100644 index 00000000000..c083f2289ba --- /dev/null +++ b/board/asus/transformer-t30/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o + +obj-y += transformer-t30.o diff --git a/board/asus/transformer-t30/pinmux-config-transformer.h b/board/asus/transformer-t30/pinmux-config-transformer.h new file mode 100644 index 00000000000..96ff45d3750 --- /dev/null +++ b/board/asus/transformer-t30/pinmux-config-transformer.h @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2021, Svyatoslav Ryhel. + */ + +#ifndef _PINMUX_CONFIG_TRANSFORMER_H_ +#define _PINMUX_CONFIG_TRANSFORMER_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config transformer_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* HDMI-CEC pinmux */ + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, DOWN, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, TRISTATE, OUTPUT), + + /* DAP3 pinmux */ + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, OUTPUT), + + /* CLK2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + + /* LCD pinmux */ + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, TRISTATE, OUTPUT), + + /* VI-group pinmux */ + LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* UART-B pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + + /* UART-C pinmux */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + + /* U-gpio group pinmux */ + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU6, RSVD1, DOWN, NORMAL, INPUT), + + /* DAP4 pinmux */ + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* CLK3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, TRISTATE, INPUT), + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, RSVD4, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT), + + /* CLK */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* DAP1 pinmux */ + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, INPUT), + + /* CLK1 pinmux */ + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT), + + /* DAP2 pinmux */ + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), + + /* PEX pinmux */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD15_PH7, NAND, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct pmux_pingrp_config tf700t_mipi_pinmux[] = { + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, TRISTATE, INPUT), +}; + +static struct pmux_drvgrp_config transformer_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */ diff --git a/board/asus/transformer-t30/transformer-t30-spl.c b/board/asus/transformer-t30/transformer-t30-spl.c new file mode 100644 index 00000000000..89819b2b921 --- /dev/null +++ b/board/asus/transformer-t30/transformer-t30-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 Transformers SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c new file mode 100644 index 00000000000..b6fd19d28e4 --- /dev/null +++ b/board/asus/transformer-t30/transformer-t30.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* T30 Transformers derive from Cardhu board */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <fdt_support.h> +#include <i2c.h> +#include <log.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/gpio.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include "pinmux-config-transformer.h" + +#define TPS65911_I2C_ADDRESS 0x2D + +#define TPS65911_VDD1 0x21 +#define TPS65911_VDD1_OP 0x22 +#define TPS65911_LDO1 0x30 +#define TPS65911_LDO2 0x31 +#define TPS65911_LDO3 0x37 +#define TPS65911_LDO5 0x32 +#define TPS65911_LDO6 0x35 + +#define TPS65911_GPIO0 0x60 +#define TPS65911_GPIO6 0x66 +#define TPS65911_GPIO7 0x67 +#define TPS65911_GPIO8 0x68 + +#define TPS65911_DEVCTRL 0x3F +#define DEVCTRL_PWR_OFF_MASK BIT(7) +#define DEVCTRL_DEV_ON_MASK BIT(2) +#define DEVCTRL_DEV_OFF_MASK BIT(0) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS65911_DEVCTRL, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= DEVCTRL_PWR_OFF_MASK; + + ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= DEVCTRL_DEV_OFF_MASK; + data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK; + + ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + printf("Failed to power off!!!\n"); + return 1; +} +#endif + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(transformer_pinmux_common, + ARRAY_SIZE(transformer_pinmux_common)); + + pinmux_config_drvgrp_table(transformer_padctrl, + ARRAY_SIZE(transformer_padctrl)); + + if (of_machine_is_compatible("asus,tf700t")) { + pinmux_config_pingrp_table(tf700t_mipi_pinmux, + ARRAY_SIZE(tf700t_mipi_pinmux)); + } +} + +#ifdef CONFIG_MMC_SDHCI_TEGRA +static void tps65911_voltage_init(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return; + } + + /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */ + ret = dm_i2c_reg_write(dev, TPS65911_LDO1, 0xc9); + if (ret) + log_debug("vcore_emmc set failed: %d\n", ret); + + if (of_machine_is_compatible("asus,tf600t")) { + /* TPS659110: VDD1_REG = 1.2v, ACTIVE to backlight */ + ret = dm_i2c_reg_write(dev, TPS65911_VDD1_OP, 0x33); + if (ret) + log_debug("vdd_bl set failed: %d\n", ret); + + ret = dm_i2c_reg_write(dev, TPS65911_VDD1, 0x0d); + if (ret) + log_debug("vdd_bl enable failed: %d\n", ret); + + /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 VIO */ + ret = dm_i2c_reg_write(dev, TPS65911_LDO5, 0x65); + if (ret) + log_debug("vdd_usd set failed: %d\n", ret); + + /* TPS659110: LDO6_REG = 1.2v, ACTIVE to MIPI */ + ret = dm_i2c_reg_write(dev, TPS65911_LDO6, 0x11); + if (ret) + log_debug("vdd_mipi set failed: %d\n", ret); + } else { + /* TPS659110: LDO2_REG = 3.1v, ACTIVE to SDMMC1 */ + ret = dm_i2c_reg_write(dev, TPS65911_LDO2, 0xb9); + if (ret) + log_debug("vdd_usd set failed: %d\n", ret); + + /* TPS659110: LDO3_REG = 3.1v, ACTIVE to SDMMC1 VIO */ + ret = dm_i2c_reg_write(dev, TPS65911_LDO3, 0x5d); + if (ret) + log_debug("vddio_usd set failed: %d\n", ret); + } + + /* TPS659110: GPIO0_REG output high to VDD_5V0_SBY */ + ret = dm_i2c_reg_write(dev, TPS65911_GPIO0, 0x07); + if (ret) + log_debug("vdd_5v0_sby set failed: %d\n", ret); + + /* TPS659110: GPIO6_REG output high to VDD_3V3_SYS */ + ret = dm_i2c_reg_write(dev, TPS65911_GPIO6, 0x07); + if (ret) + log_debug("vdd_3v3_sys set failed: %d\n", ret); + + /* TPS659110: GPIO7_REG output high to VDD_1V5_DDR */ + ret = dm_i2c_reg_write(dev, TPS65911_GPIO7, 0x07); + if (ret) + log_debug("vdd_1v5_ddr set failed: %d\n", ret); + + /* TPS659110: GPIO8_REG pull_down output high to VDD_5V0_SYS */ + ret = dm_i2c_reg_write(dev, TPS65911_GPIO8, 0x0f); + if (ret) + log_debug("vdd_5v0_sys set failed: %d\n", ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* Bring up uSD and eMMC power */ + tps65911_voltage_init(); +} +#endif /* MMC */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif + +void nvidia_board_late_init(void) +{ + char serialno_str[17]; + + /* Set chip id as serialno */ + sprintf(serialno_str, "%016llx", tegra_chip_uid()); + env_set("serial#", serialno_str); + env_set("platform", "Tegra 3 T30"); +} diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 2a78df670cc..7ae6742c4be 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -183,7 +183,7 @@ int dram_init_banksize(void) } /* Limit RAM used by U-Boot to the DDR first bank End region */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return BCM_NS3_MEM_END; } diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS index bc7f9b0e680..42e5df506bf 100644 --- a/board/edgeble/neural-compute-module-6/MAINTAINERS +++ b/board/edgeble/neural-compute-module-6/MAINTAINERS @@ -5,3 +5,9 @@ F: board/edgeble/neural-compute-module-6 F: include/configs/neural-compute-module-6.h F: configs/neu6a-io-rk3588_defconfig F: configs/neu6b-io-rk3588_defconfig +F: arch/arm/dts/rk3588-edgeble-neu6a.dtsi +F: arch/arm/dts/rk3588-edgeble-neu6a-io.dts +F: arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi +F: arch/arm/dts/rk3588-edgeble-neu6b.dtsi +F: arch/arm/dts/rk3588-edgeble-neu6b-io.dts +F: arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig new file mode 100644 index 00000000000..0b72c4a687d --- /dev/null +++ b/board/htc/endeavoru/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ENDEAVORU + +config SYS_BOARD + default "endeavoru" + +config SYS_VENDOR + default "htc" + +config SYS_CONFIG_NAME + default "endeavoru" + +endif diff --git a/board/htc/endeavoru/MAINTAINERS b/board/htc/endeavoru/MAINTAINERS new file mode 100644 index 00000000000..85f439f4672 --- /dev/null +++ b/board/htc/endeavoru/MAINTAINERS @@ -0,0 +1,7 @@ +ENDEAVORU BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/htc/endeavoru/ +F: configs/endeavoru_defconfig +F: doc/board/htc/endeavoru.rst +F: include/configs/endeavoru.h diff --git a/board/htc/endeavoru/Makefile b/board/htc/endeavoru/Makefile new file mode 100644 index 00000000000..0c6ba4af3b1 --- /dev/null +++ b/board/htc/endeavoru/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_SPL_BUILD) += endeavoru-spl.o + +obj-y += endeavoru.o diff --git a/board/htc/endeavoru/endeavoru-spl.c b/board/htc/endeavoru/endeavoru-spl.c new file mode 100644 index 00000000000..7921ff1a733 --- /dev/null +++ b/board/htc/endeavoru/endeavoru-spl.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 HTC Endeavoru SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +/* + * Endeavoru uses TPS80032 PMIC with SMPS1 and SMPS2 in strandard + * mode with zero offset. + */ + +#define TPS80032_DVS_I2C_ADDR (0x12 << 1) +#define TPS80032_SMPS1_CFG_VOLTAGE_REG 0x56 +#define TPS80032_SMPS2_CFG_VOLTAGE_REG 0x5C +#define TPS80032_SMPS1_CFG_VOLTAGE_DATA (0x2100 | TPS80032_SMPS1_CFG_VOLTAGE_REG) +#define TPS80032_SMPS2_CFG_VOLTAGE_DATA (0x3000 | TPS80032_SMPS2_CFG_VOLTAGE_REG) + +#define TPS80032_CTL1_I2C_ADDR (0x48 << 1) +#define TPS80032_SMPS1_CFG_STATE_REG 0x54 +#define TPS80032_SMPS2_CFG_STATE_REG 0x5A +#define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG) +#define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA); + udelay(10 * 1000); +} diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c new file mode 100644 index 00000000000..1d92870f91a --- /dev/null +++ b/board/htc/endeavoru/endeavoru.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <fdt_support.h> +#include <i2c.h> +#include <log.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/gpio.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include "pinmux-config-endeavoru.h" + +#define TPS80032_CTL1_I2C_ADDR 0x48 +#define TPS80032_PHOENIX_DEV_ON 0x25 +#define DEVOFF BIT(0) +#define TPS80032_LDO1_CFG_STATE 0x9E +#define TPS80032_LDO1_CFG_VOLTAGE 0x9F + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_reg_write(dev, TPS80032_PHOENIX_DEV_ON, DEVOFF); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + + printf("Failed to power off!!!\n"); + return 1; +} +#endif + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(endeavoru_pinmux_common, + ARRAY_SIZE(endeavoru_pinmux_common)); +} + +#ifdef CONFIG_MMC_SDHCI_TEGRA +static void tps80032_voltage_init(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev); + if (ret) + log_debug("cannot find PMIC I2C chip\n"); + + /* TPS80032: LDO1_REG = 1.2v to DSI */ + ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_VOLTAGE, 0x03); + if (ret) + log_debug("avdd_dsi_csi voltage set failed: %d\n", ret); + + /* TPS80032: LDO1_REG enable */ + ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_STATE, 0x01); + if (ret) + log_debug("avdd_dsi_csi enable failed: %d\n", ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* Bring up DSI power */ + tps80032_voltage_init(); +} +#endif /* MMC */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif + +void nvidia_board_late_init(void) +{ + char serialno_str[17]; + + /* Set chip id as serialno */ + sprintf(serialno_str, "%016llx", tegra_chip_uid()); + env_set("serial#", serialno_str); + env_set("platform", "Tegra 3 T30"); +} diff --git a/board/htc/endeavoru/pinmux-config-endeavoru.h b/board/htc/endeavoru/pinmux-config-endeavoru.h new file mode 100644 index 00000000000..a00c5c988f1 --- /dev/null +++ b/board/htc/endeavoru/pinmux-config-endeavoru.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2022, Svyatoslav Ryhel. + */ + +#ifndef _PINMUX_CONFIG_ENDEAVORU_H_ +#define _PINMUX_CONFIG_ENDEAVORU_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config endeavoru_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, UARTE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, UARTE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, INVALID, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, INVALID, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* HDMI pinmux */ + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, HSI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, INPUT), + + /* DAP3 pinmux */ + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + + /* PV-gpio group pinmux */ + DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, RSVD2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD2, NORMAL, NORMAL, OUTPUT), + + /* CLK2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* LCD pinmux */ + DEFAULT_PINMUX(LCD_PWR1_PC1, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, RSVD4, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D22_PM6, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D23_PM7, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* VI-group pinmux */ + LV_PINMUX(VI_D0_PT4, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* UART-2 pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, SPI4, NORMAL, NORMAL, INPUT), + + /* UART-3 pinmux */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + + /* PU-gpio group pinmux */ + DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU2, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU5, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PU6, PWM3, UP, TRISTATE, INPUT), + + /* DAP4 pinmux */ + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* CLK3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD4, NORMAL, TRISTATE, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS6_N_PI3, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14_PH6, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD15_PH7, NAND, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_RST_N_PI4, RSVD4, UP, TRISTATE, INPUT), + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, RSVD3, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT), + + /* CLK */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, UP, NORMAL, INPUT), + + /* DAP1 pinmux */ + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, OUTPUT), + + /* CLK1 pinmux */ + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, RSVD4, NORMAL, NORMAL, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT), + + /* DAP2 pinmux */ + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, DOWN, NORMAL, INPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), + + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* PEX pinmux */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), +}; + +#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */ diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index 8532225dc0d..cecf454011c 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -23,7 +23,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { DECLARE_GLOBAL_DATA_PTR; diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig new file mode 100644 index 00000000000..20ea4f5f324 --- /dev/null +++ b/board/lg/x3-t30/Kconfig @@ -0,0 +1,26 @@ +if TARGET_X3_T30 + +config SYS_BOARD + default "x3-t30" + +config SYS_VENDOR + default "lg" + +config SYS_CONFIG_NAME + default "x3-t30" + +config DEVICE_P880 + bool "Enable support for LG Optimus 4X HD" + default n + help + LG Optimus 4X HD derives from x3 board but has slight + differences. + +config DEVICE_P895 + bool "Enable support for LG Optimus Vu" + default n + help + LG Optimus Vu derives from x3 board but has slight + differences. + +endif diff --git a/board/lg/x3-t30/MAINTAINERS b/board/lg/x3-t30/MAINTAINERS new file mode 100644 index 00000000000..0ad29563e92 --- /dev/null +++ b/board/lg/x3-t30/MAINTAINERS @@ -0,0 +1,9 @@ +X3 BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/lg/x3-t30/ +F: configs/p880.config +F: configs/p895.config +F: configs/x3_t30_defconfig +F: doc/board/lg/x3_t30.rst +F: include/configs/x3-t30.h diff --git a/board/lg/x3-t30/Makefile b/board/lg/x3-t30/Makefile new file mode 100644 index 00000000000..3eeb132f3c6 --- /dev/null +++ b/board/lg/x3-t30/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_SPL_BUILD) += x3-t30-spl.o + +obj-y += x3-t30.o diff --git a/board/lg/x3-t30/pinmux-config-x3.h b/board/lg/x3-t30/pinmux-config-x3.h new file mode 100644 index 00000000000..cdb28095f3c --- /dev/null +++ b/board/lg/x3-t30/pinmux-config-x3.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2021, Svyatoslav Ryhel. + */ + +#ifndef _PINMUX_CONFIG_X3_H_ +#define _PINMUX_CONFIG_X3_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +static struct pmux_pingrp_config tegra3_x3_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ +// DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), // device specific + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), +// LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), // device specific + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* HDMI-CEC pinmux */ + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, SPI3, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, SPI3, UP, NORMAL, OUTPUT), // LCD_BRIDGE_RESET_N + DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, SPI3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT), +// DEFAULT_PINMUX(ULPI_DATA5_PO6, SPI2, UP, TRISTATE, INPUT), // unconfigured +// DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, UP, NORMAL, INPUT), // unconfigured + DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, DOWN, NORMAL, OUTPUT), // LCD_EN + DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT), + + /* DAP3 pinmux */ + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD2, DOWN, NORMAL, INPUT), + + /* CLK2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, OUTPUT), + + /* LCD pinmux */ + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), // unconfigured + DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDI + DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDO + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_CS + DEFAULT_PINMUX(LCD_DC0_PN6, RSVD3, NORMAL, NORMAL, OUTPUT), // LCD_CP_EN / BL + DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SCL + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_PCLK + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_HSYNC + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_VSYNC + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, OUTPUT), // LCD_RESET_N + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), // LCD_MAKER_ID + DEFAULT_PINMUX(LCD_DC1_PD2, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD2, NORMAL, NORMAL, INPUT), + + /* VI-group pinmux */ + LV_PINMUX(VI_D0_PT4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, RSVD2, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* UART-B pinmux */ +// DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), // device specific + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + + /* UART-C pinmux */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + + /* PU-gpio group pinmux */ +// DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), // device specific +// DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), // device specific + DEFAULT_PINMUX(PU5, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, PWM3, DOWN, NORMAL, INPUT), + + /* DAP4 pinmux */ + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* CLK3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), // MIPI_BRIDGE_CLK + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // device specific + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PCC2, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + + /* CLK */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), +// DEFAULT_PINMUX(CORE_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(CPU_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(PWR_INT_N, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(CLK_32K_IN, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* DAP1 pinmux */ + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + + /* CLK1 pinmux */ + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, DOWN, NORMAL, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), // device specific + + /* DAP2 pinmux */ + DEFAULT_PINMUX(DAP2_FS_PA2, HDA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, HDA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, HDA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, HDA, DOWN, NORMAL, INPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI2, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), // device specific +// DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), // device specific + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MISO_PX1, GMI, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI6, UP, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(SPI2_SCK_PX2, SPI6, UP, NORMAL, INPUT), // unconfigured + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), +// DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), // unconfigured + + /* PEX pinmux */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, TRISTATE, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT_PI7, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, TRISTATE, INPUT), // LCD_RGB_DE + DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), // device specific + DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, UP, NORMAL, INPUT), +// DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), // device specific + DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, GMI, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14_PH6, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD15_PH7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, NORMAL, OUTPUT), // RGB_IC_EN + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_RST_N_PI4, GMI, UP, NORMAL, INPUT), +}; + +#ifdef CONFIG_DEVICE_P880 +static struct pmux_pingrp_config tegra3_p880_pinmux[] = { + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, TRISTATE, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, NORMAL, NORMAL, INPUT), + + /* UART-B pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, UP, NORMAL, OUTPUT), + + /* GPIO group pinmux */ + DEFAULT_PINMUX(PU0, UARTA, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU1, UARTA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PU2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, I2S4, NORMAL, TRISTATE, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, UP, TRISTATE, OUTPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, DOWN, NORMAL, OUTPUT), +}; +#endif /* CONFIG_DEVICE_P880 */ + +#ifdef CONFIG_DEVICE_P895 +static struct pmux_pingrp_config tegra3_p895_pinmux[] = { + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), + + /* UART-B pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + + /* Gpio group pinmux */ + DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // LCD_EN_3V0 + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), +}; +#endif /* CONFIG_DEVICE_P895 */ +#endif /* _PINMUX_CONFIG_X3_H_ */ diff --git a/board/lg/x3-t30/x3-t30-spl.c b/board/lg/x3-t30/x3-t30-spl.c new file mode 100644 index 00000000000..864f2de45f1 --- /dev/null +++ b/board/lg/x3-t30/x3-t30-spl.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 LGE X3 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define MAX77663_I2C_ADDR (0x1C << 1) + +#define MAX77663_REG_SD0 0x16 +#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) +#define MAX77663_REG_SD1 0x17 +#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) +#define MAX77663_REG_LDO4 0x2B +#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) + +#define MAX77663_REG_GPIO1 0x37 +#define MAX77663_REG_GPIO1_DATA (0x0800 | MAX77663_REG_GPIO1) +#define MAX77663_REG_GPIO4 0x3A +#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); + udelay(1000); + + /* Bring up VDD_RTC to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); + udelay(10 * 1000); + + /* Set GPIO4 and GPIO1 states */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO1_DATA); +} diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c new file mode 100644 index 00000000000..594563cf52d --- /dev/null +++ b/board/lg/x3-t30/x3-t30.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <fdt_support.h> +#include <i2c.h> +#include <log.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include "pinmux-config-x3.h" + +#define MAX77663_I2C_ADDR 0x1C + +#define MAX77663_REG_SD2 0x18 +#define MAX77663_REG_LDO2 0x27 +#define MAX77663_REG_LDO3 0x29 +#define MAX77663_REG_LDO5 0x2D +#define MAX77663_REG_ONOFF_CFG1 0x41 +#define ONOFF_PWR_OFF BIT(1) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= ONOFF_PWR_OFF; + + ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); + if (ret) + return ret; + + /* wait some time and then print error */ + mdelay(5000); + + printf("Failed to power off!!!\n"); + return 1; +} +#endif + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_x3_pinmux_common, + ARRAY_SIZE(tegra3_x3_pinmux_common)); + +#ifdef CONFIG_DEVICE_P880 + pinmux_config_pingrp_table(tegra3_p880_pinmux, + ARRAY_SIZE(tegra3_p880_pinmux)); +#endif + +#ifdef CONFIG_DEVICE_P895 + pinmux_config_pingrp_table(tegra3_p895_pinmux, + ARRAY_SIZE(tegra3_p895_pinmux)); +#endif +} + +#ifdef CONFIG_MMC_SDHCI_TEGRA +static void max77663_voltage_init(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return; + } + + /* 0x60 for 1.8v, bit7:0 = voltage */ + ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60); + if (ret) + log_debug("vdd_1v8_vio set failed: %d\n", ret); + + /* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2); + if (ret) + log_debug("avdd_usb set failed: %d\n", ret); + + /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC); + if (ret) + log_debug("vdd_usd set failed: %d\n", ret); + + /* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9); + if (ret) + log_debug("vcore_emmc set failed: %d\n", ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* Bring up uSD and eMMC power */ + max77663_voltage_init(); +} +#endif /* MMC */ + +int nvidia_board_init(void) +{ + /* Set up panel bridge clocks */ + clock_start_periph_pll(PERIPH_ID_EXTPERIPH3, CLOCK_ID_PERIPH, + 24 * 1000000); + clock_external_output(3); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* First 3 bytes refer to LG vendor */ + u8 btmacaddr[6] = { 0x00, 0x00, 0x00, 0xD0, 0xC9, 0x88 }; + + /* Generate device 3 bytes based on chip sd */ + u64 bt_device = tegra_chip_uid() >> 24ull; + + btmacaddr[0] = (bt_device >> 1 & 0x0F) | + (bt_device >> 5 & 0xF0); + btmacaddr[1] = (bt_device >> 11 & 0x0F) | + (bt_device >> 17 & 0xF0); + btmacaddr[2] = (bt_device >> 23 & 0x0F) | + (bt_device >> 29 & 0xF0); + + /* Set BT MAC address */ + fdt_find_and_setprop(blob, "/serial@70006200/bluetooth", + "local-bd-address", btmacaddr, 6, 1); + + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif + +void nvidia_board_late_init(void) +{ + char serialno_str[17]; + + /* Set chip id as serialno */ + sprintf(serialno_str, "%016llx", tegra_chip_uid()); + env_set("serial#", serialno_str); + env_set("platform", "Tegra 3 T30"); +} diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index ca3b81c57ff..b8dffb0e485 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; static u32 mx53_dram_size[2]; -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * WARNING: We must override get_effective_memsize() function here diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS index 62fb6b4c0ee..a569efa74e3 100644 --- a/board/radxa/rock5a-rk3588s/MAINTAINERS +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -1,6 +1,9 @@ ROCK5A-RK3588 M: Eugen Hristev <eugen.hristev@collabora.com> +R: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: board/radxa/rock5a-rk3588s F: include/configs/rock5a-rk3588s.h F: configs/rock5a-rk3588s_defconfig +F: arch/arm/dts/rk3588s-rock-5a.dts +F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index 693751e583d..4460c9971a9 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -1,6 +1,9 @@ ROCK5B-RK3588 M: Eugen Hristev <eugen.hristev@collabora.com> +R: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: board/radxa/rock5b-rk3588 -F: include/configs/rock5b-rk3588 +F: include/configs/rock5b-rk3588.h F: configs/rock5b-rk3588_defconfig +F: arch/arm/dts/rk3588-rock-5b.dts +F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 1057ebb9948..cd823ad7465 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -334,7 +334,7 @@ static void set_fdt_addr(void) /* * Prevent relocation from stomping on a firmware provided FDT blob. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { if ((gd->ram_top - fw_dtb_pointer) > SZ_64M) return gd->ram_top; @@ -561,6 +561,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); if (node < 0) fdt_simplefb_add_node(blob); + else + fdt_simplefb_enable_and_mem_rsv(blob); #ifdef CONFIG_EFI_LOADER /* Reserve the spin table */ diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index cb44bc9fda4..c7e412b54ee 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -80,7 +80,7 @@ F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi -RADXA ROCK 4C+ +ROCK-4C+ M: FUKAUMI Naoki <naoki@radxa.com> S: Maintained F: configs/rock-4c-plus-rk3399_defconfig diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 82a92b89fa6..cc9eb432a8b 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -1,31 +1,44 @@ EVB-RK3568 -M: Joseph Chen <chenjh@rock-chips.com> -S: Maintained -F: board/rockchip/evb_rk3568 -F: include/configs/evb_rk3568.h -F: configs/evb-rk3568_defconfig -F: arch/arm/dts/rk3568-evb-boot.dtsi +M: Joseph Chen <chenjh@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rk3568 +F: include/configs/evb_rk3568.h +F: configs/evb-rk3568_defconfig +F: arch/arm/dts/rk3568-evb-u-boot.dtsi F: arch/arm/dts/rk3568-evb.dts +LUBANCAT-2 +M: Andy Yan <andyshrk@163.com> +S: Maintained +F: configs/lubancat-2-rk3568_defconfig +F: arch/arm/dts/rk3568-lubancat-2.dts +F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi + NANOPI-R5C -M: Tianling Shen <cnsztl@gmail.com> -S: Maintained -F: configs/nanopi-r5c-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5c.dts -F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +M: Tianling Shen <cnsztl@gmail.com> +R: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/nanopi-r5c-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5c.dts +F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi NANOPI-R5S -M: Tianling Shen <cnsztl@gmail.com> -S: Maintained -F: configs/nanopi-r5s-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5s.dts -F: arch/arm/dts/rk3568-nanopi-r5s.dtsi -F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +M: Tianling Shen <cnsztl@gmail.com> +R: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/nanopi-r5s-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5s.dts +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -RADXA-CM3 +RADXA-CM3-IO M: Jagan Teki <jagan@amarulasolutions.com> +R: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig +F: arch/arm/dts/rk3566-radxa-cm3.dtsi +F: arch/arm/dts/rk3566-radxa-cm3-io.dts +F: arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi RADXA-E25 M: Jonas Karlman <jonas@kwiboo.se> @@ -36,8 +49,9 @@ F: arch/arm/dts/rk3568-radxa-e25.dts F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi ROCK-3A -M: Akash Gajjar <gajjar04akash@gmail.com> -S: Maintained -F: configs/rock-3a-rk3568_defconfig -F: arch/arm/dts/rk3568-rock-3a.dts -F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +M: Akash Gajjar <gajjar04akash@gmail.com> +R: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/rock-3a-rk3568_defconfig +F: arch/arm/dts/rk3568-rock-3a.dts +F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 7b7df3c5a8a..6b2c257a170 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -4,4 +4,5 @@ S: Maintained F: board/rockchip/evb_rk3588 F: include/configs/evb_rk3588.h F: configs/evb-rk3588_defconfig -F: arch/arm/dts/rk3588-evb-u-boot.dtsi +F: arch/arm/dts/rk3588-evb1-v10.dts +F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index d52dce4f657..969ad484864 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv) } /* early init of PMIC */ -void stpmic1_init(u32 voltage_mv) +struct udevice *stpmic1_init(u32 voltage_mv) { struct udevice *dev; if (uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(pmic_stpmic1), &dev)) - return; + return NULL; /* update VDDCORE = BUCK1 */ if (voltage_mv) stmpic_buck1_set(dev, voltage_mv); - /* Keep vdd on during the reset cycle */ - pmic_clrsetbits(dev, - STPMIC1_BUCKS_MRST_CR, - STPMIC1_MRST_BUCK(STPMIC1_BUCK3), - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + return dev; } diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h index b17d6f16338..7a7169d7cea 100644 --- a/board/st/common/stpmic1.h +++ b/board/st/common/stpmic1.h @@ -3,4 +3,4 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -void stpmic1_init(u32 voltage_mv); +struct udevice *stpmic1_init(u32 voltage_mv); diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 747ec7e445a..8b4a529f759 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -5,6 +5,8 @@ #include <config.h> #include <common.h> +#include <power/pmic.h> +#include <power/stpmic1.h> #include <asm/arch/sys_proto.h> #include "../common/stpmic1.h" @@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv) int board_early_init_f(void) { - if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) - stpmic1_init(opp_voltage_mv); + if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) { + struct udevice *dev = stpmic1_init(opp_voltage_mv); + + /* Keep vdd on during the reset cycle */ + pmic_clrsetbits(dev, + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + } return 0; } diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 706b2198183..d52ac332f81 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -59,7 +59,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT /* Limit RAM used by U-Boot to the DDR low region */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 2398bead782..38fe447d8fa 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -55,7 +55,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT /* Limit RAM used by U-Boot to the DDR low region */ diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 8eaca9d5af2..7795300abc8 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -43,7 +43,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT /* Limit RAM used by U-Boot to the DDR low region */ diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 5b166b14ca6..a3d1d07a0cb 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -37,7 +37,7 @@ int dram_init(void) /* * Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return 0x9C000000; } diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 0328d68e751..906d5e3c2d7 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -627,7 +627,7 @@ int embedded_dtb_select(void) #endif #if defined(CONFIG_LMB) -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { phys_size_t size; phys_addr_t reg; diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 1c9f2b1e2fe..ae936c8daa1 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -409,7 +409,7 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) return 0; } -int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) +static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) { ulong kernel, fdt; char cmd[50]; diff --git a/cmd/ubi.c b/cmd/ubi.c index b61ae1efea4..0a6a80bdd10 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -653,7 +653,7 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (strcmp(argv[1], "list") == 0) { int numeric = 0; - if (argc >= 2 && argv[2][0] == '-') { + if (argc >= 3 && argv[2][0] == '-') { if (strcmp(argv[2], "-numeric") == 0) numeric = 1; else diff --git a/common/board_f.c b/common/board_f.c index 791c1e601c4..e9f4edb93db 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -330,7 +330,7 @@ __weak int mach_cpu_init(void) } /* Get the top of usable RAM */ -__weak phys_size_t board_get_usable_ram_top(phys_size_t total_size) +__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0 /* diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index 16ecece7023..eb6f5266896 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -44,7 +44,6 @@ int spl_blk_load_image(struct spl_image_info *spl_image, enum uclass_id uclass_id, int devnum, int partnum) { const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; - struct disk_partition part_info = {}; struct legacy_img_hdr *header; struct blk_desc *blk_desc; loff_t actlen, filesize; @@ -59,11 +58,6 @@ int spl_blk_load_image(struct spl_image_info *spl_image, blk_show_device(uclass_id, devnum); header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); - ret = part_get_info(blk_desc, 1, &part_info); - if (ret) { - printf("spl: no partition table found. Err - %d\n", ret); - goto out; - } dev.ifname = blk_get_uclass_name(uclass_id); snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x", diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index ed6643d9d4f..ed6643d9d4f 100644 --- a/configs/anbernic-rgxx3_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig new file mode 100644 index 00000000000..38f26f2dcc5 --- /dev/null +++ b/configs/endeavoru_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru" +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_PROMPT="Tegra30 (Endeavoru) # " +CONFIG_SPL_STACK=0x800ffffc +CONFIG_TEGRA30=y +CONFIG_TARGET_ENDEAVORU=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_SPL_DM=y +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="HTC" +CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0c02 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_ENDEAVORU=y +CONFIG_VIDEO_DSI_TEGRA30=y +CONFIG_TEGRA_BACKLIGHT_PWM=y +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set diff --git a/configs/grouper_E1565.config b/configs/grouper_E1565.config new file mode 100644 index 00000000000..4d8d5263fa9 --- /dev/null +++ b/configs/grouper_E1565.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565" +CONFIG_GROUPER_MAX77663=y diff --git a/configs/grouper_PM269.config b/configs/grouper_PM269.config new file mode 100644 index 00000000000..fc768b20517 --- /dev/null +++ b/configs/grouper_PM269.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269" +CONFIG_GROUPER_TPS65911=y diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig new file mode 100644 index 00000000000..8dc88851f5a --- /dev/null +++ b/configs/grouper_common_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565" +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_PROMPT="Tegra30 (Grouper) # " +CONFIG_SPL_STACK=0x800ffffc +CONFIG_TEGRA30=y +CONFIG_TARGET_GROUPER=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_SPL_DM=y +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_GPIO_HOG=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASUS Google" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4e41 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_TEGRA20=y +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig new file mode 100644 index 00000000000..b01d3bd2a1a --- /dev/null +++ b/configs/lubancat-2-rk3568_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y +CONFIG_EFI_VAR_BUF_SIZE=16384 diff --git a/configs/p1801-t.config b/configs/p1801-t.config new file mode 100644 index 00000000000..fab2912132c --- /dev/null +++ b/configs/p1801-t.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-p1801-t" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4cb0 diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 5b91631367b..7716655278d 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index ae235058afd..3cdb1a7271e 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 0ea47192dda..41a108d3ffb 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index b0d538f0f83..febd82e2300 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/p880.config b/configs/p880.config new file mode 100644 index 00000000000..1a47b5f7692 --- /dev/null +++ b/configs/p880.config @@ -0,0 +1,4 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880" +CONFIG_DEVICE_P880=y +CONFIG_SYS_PROMPT="Tegra30 (P880) # " +CONFIG_VIDEO_LCD_RENESAS_R69328=y diff --git a/configs/p895.config b/configs/p895.config new file mode 100644 index 00000000000..019a5662d62 --- /dev/null +++ b/configs/p895.config @@ -0,0 +1,4 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895" +CONFIG_DEVICE_P895=y +CONFIG_SYS_PROMPT="Tegra30 (P895) # " +CONFIG_VIDEO_LCD_RENESAS_R61307=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 5e36612bb80..c2641f65b50 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -72,8 +72,11 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 424ae5dbdfa..9ea5aaa7145 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -171,6 +171,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y @@ -178,6 +179,8 @@ CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y CONFIG_VIDEO_STM32_MAX_XRES=1280 CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 2700b5c4991..4d0a81f8a87 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -147,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y @@ -154,6 +155,8 @@ CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y CONFIG_VIDEO_STM32_MAX_XRES=1280 CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5b94e0c6d2e..0a7d8624858 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -147,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y @@ -154,6 +155,8 @@ CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y CONFIG_VIDEO_STM32_MAX_XRES=1280 CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y diff --git a/configs/tf201.config b/configs/tf201.config new file mode 100644 index 00000000000..296743b7748 --- /dev/null +++ b/configs/tf201.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/configs/tf300t.config b/configs/tf300t.config new file mode 100644 index 00000000000..32a92fe76fa --- /dev/null +++ b/configs/tf300t.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300t" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/configs/tf300tg.config b/configs/tf300tg.config new file mode 100644 index 00000000000..1396294f6de --- /dev/null +++ b/configs/tf300tg.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tg" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4c80 diff --git a/configs/tf300tl.config b/configs/tf300tl.config new file mode 100644 index 00000000000..3db033c8df4 --- /dev/null +++ b/configs/tf300tl.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tl" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/configs/tf600t.config b/configs/tf600t.config new file mode 100644 index 00000000000..89d8db4eb1c --- /dev/null +++ b/configs/tf600t.config @@ -0,0 +1,4 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t" +CONFIG_TRANSFORMER_SPI_BOOT=y +CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/configs/tf700t.config b/configs/tf700t.config new file mode 100644 index 00000000000..066c884d082 --- /dev/null +++ b/configs/tf700t.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf700t" +CONFIG_USB_GADGET_PRODUCT_NUM=0x4c90 diff --git a/configs/tilapia.config b/configs/tilapia.config new file mode 100644 index 00000000000..1fb0633e3a7 --- /dev/null +++ b/configs/tilapia.config @@ -0,0 +1,3 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565" +CONFIG_GROUPER_MAX77663=y +CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # " diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig new file mode 100644 index 00000000000..6fe6f2548dc --- /dev/null +++ b/configs/transformer_t30_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201" +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_PROMPT="Tegra30 (Transformer) # " +CONFIG_SPL_STACK=0x800ffffc +CONFIG_TEGRA30=y +CONFIG_TARGET_TRANSFORMER_T30=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_SPL_DM=y +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_GPIO_HOG=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASUS" +CONFIG_USB_GADGET_VENDOR_NUM=0x0b05 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_TEGRA20=y +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig new file mode 100644 index 00000000000..540c43096d8 --- /dev/null +++ b/configs/x3_t30_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880" +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_PROMPT="Tegra30 (x3) # " +CONFIG_SPL_STACK=0x800ffffc +CONFIG_TEGRA30=y +CONFIG_TARGET_X3_T30=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_SPL_DM=y +CONFIG_BUTTON=y +CONFIG_EXTCON=y +CONFIG_EXTCON_MAX14526=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="LG" +CONFIG_USB_GADGET_VENDOR_NUM=0x1004 +CONFIG_USB_GADGET_PRODUCT_NUM=0x7100 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_BACKLIGHT_LM3533=y +CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y +CONFIG_VIDEO_TEGRA20=y +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set diff --git a/doc/api/index.rst b/doc/api/index.rst index a9338cfef9f..3a80ae0635a 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -15,6 +15,7 @@ U-Boot API documentation lmb logging nvmem + part pinctrl rng sandbox diff --git a/doc/api/part.rst b/doc/api/part.rst new file mode 100644 index 00000000000..d1df1d84945 --- /dev/null +++ b/doc/api/part.rst @@ -0,0 +1,6 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Partition API +============= + +.. kernel-doc:: include/part.h diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst index 325fb80346e..4ecdc31716a 100644 --- a/doc/arch/arm64.ffa.rst +++ b/doc/arch/arm64.ffa.rst @@ -231,7 +231,7 @@ Please refer the command documentation at :doc:`../usage/cmd/armffa` Example of boot logs with FF-A enabled -------------------------------------- -For example, when using FF-A with Corstone-1000 the logs are as follows: +For example, when using FF-A with Corstone-1000, debug logs enabled, the output is as follows: :: diff --git a/doc/board/asus/grouper_common.rst b/doc/board/asus/grouper_common.rst new file mode 100644 index 00000000000..2e4450b40e0 --- /dev/null +++ b/doc/board/asus/grouper_common.rst @@ -0,0 +1,94 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the ASUS/Google Nexus 7 (2012) +========================================= + +``DISCLAMER!`` Moving your ASUS/Google Nexus 7 (2012) to use +U-Boot assumes replacement of the vendor ASUS bootloader. Vendor +android firmwares will no longer be able to run on the device. +This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Pack U-Boot into repart-block +- Flash repart-block into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +Device support is implemented by applying config fragment to a generic +board defconfig. Valid fragments are ``grouper_E1565.config``, +``grouper_PM269.config`` and ``tilapia.config``. + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-linux-gnueabi- + $ make grouper_common_defconfig grouper_E1565.config # For maxim based grouper + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for flashing (but check the next section for additional +adjustments). + +Pack U-Boot into repar-block +---------------------------- + +``DISCLAMER!`` All questions related to re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in +form usable by device. This process is required only on the first +installation or to recover the device in case of a failed update. +You need to know your tablet's individual SBK to continue. + +.. code-block:: bash + + $ git clone https://github.com/clamor-s/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-regra.bin here + $ ./re-crypt.sh -d grouper -k deadbeefdeadc0dedeadd00dfee1dead + +Script will produce you a ``repart-block.bin`` ready to flash. + +Flash repart-block into the eMMC +-------------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked +in the proper place. NOT HERE! Flashing repart-block will erase +all your eMMC, so make a backup before! + +``repart-block.bin`` contains BCT and bootloader in encrypted state +in form which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ wheelie --blob blob.bin + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +Boot +---- + +After flashing ``repart-block.bin`` the device should reboot and turn +itself off. This is normal behavior if no boot configuration is +found. + +To boot Linux, U-Boot will look for an ``extlinux.conf`` configuration +on eMMC. Additionally if Volume Down button is pressed while booting +device will enter bootmenu. Bootmenu contains entries to mount eMMC as +mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot +console and update bootloader (check next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC +and allows the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the +eMMC (using ability of u-boot to mount it). Enter bootmenu, choose +update bootloader option with Power button and U-Boot should update +itself. Once the process is completed, U-Boot will ask to press any +button to reboot. diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst new file mode 100644 index 00000000000..87e535fe34f --- /dev/null +++ b/doc/board/asus/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ASUS +==== + +.. toctree:: + :maxdepth: 2 + + grouper_common + transformer_t30 diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst new file mode 100644 index 00000000000..b6b61015409 --- /dev/null +++ b/doc/board/asus/transformer_t30.rst @@ -0,0 +1,116 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the ASUS Transformer device family +============================================= + +``DISCLAMER!`` Moving your ASUS Transformer to use U-Boot +assumes replacement of the vendor ASUS bootloader. Vendor +android firmwares will no longer be able to run on the device. +This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Pack U-Boot into repart-block +- Flash repart-block into the eMMC +- Flash repart-block into TF600T SPI flash +- Boot +- Self Upgrading + +Build U-Boot +------------ + +Device support is implemented by applying config fragment +to a generic board defconfig. Valid fragments are ``tf201.config``, +``tf300t.config``, ``tf300tg.config``, ``tf300tl.config``, +``tf700t.config``, ``tf600t.config`` and ``p1801-t.config``. + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-linux-gnueabi- + $ make transformer_t30_defconfig tf201.config # For TF201 + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for flashing (but check the next section for additional +adjustments). + +Pack U-Boot into repar-block +---------------------------- + +``DISCLAMER!`` All questions related to re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in +form usable by device. This process is required only on the first +installation or to recover the device in case of a failed update. +You need to know your tablet's individual SBK to continue. + +.. code-block:: bash + + $ git clone https://github.com/clamor-s/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-regra.bin here + $ ./re-crypt.sh -d tf201 -k deadbeefdeadc0dedeadd00dfee1dead + +Script will produce you a `repart-block.bin` ready to flash. + +Flash repart-block into the eMMC +-------------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked +in the proper place. NOT HERE! Flashing repart-block will erase +all your eMMC, so make a backup before! + +``repart-block.bin`` contains BCT and bootloader in encrypted state +in form which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ wheelie --blob blob.bin + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +Flash repart-block into TF600T SPI flash +---------------------------------------- + +Unlike other transformers TF600T uses separate 4 MB SPI flash which +contains all data required for boot. It is flashed from within u-boot +itself preloaded into RAM using fusee gelee. After creating your +``repart-block.bin`` you have to place it on a 1st partition of microSD +card formated in fat. Then insert this microSD card into your tablet +and boot it using fusee gelee and u-boot which was included into +repart-block.bin, while booting you must hold volume down button. +Process should take less then a minute, if everything goes correct, +on microSD will appear ``spi-flash-backup.bin`` file, which is dump of +your spi flash content and can be used to restore UEFI, do not loose it, +tablet will power itself off. + +Self-updating of u-boot is performed by placing ``u-boot-dtb-tegra.bin`` +on 1st partition of microSD, inserting it into tablet and booting with +pressed volume down button. + +Boot +---- + +After flashing ``repart-block.bin`` the device should reboot and turn +itself off. This is normal behavior if no boot configuration is +found. + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD +and then on eMMC. Additionally if Volume Down button is pressed +while booting device will enter bootmenu. Bootmenu contains entries +to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot +RCM, poweroff, enter U-Boot console and update bootloader (check next +chapter). + +Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC +and allows the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the +MicroSD card and insert it into the tablet. Enter bootmenu, choose +update bootloader option with Power button and U-Boot should update +itself. Once the process is completed, U-Boot will ask to press any +button to reboot. diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 21801a8a4d9..d660a223d9c 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -134,3 +134,23 @@ input clock is 1843200. So you can add the following CONFIG options:: CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y + +coreboot in CI +-------------- + +CI runs tests using a pre-built coreboot image. This ensures that U-Boot can +boot as a coreboot payload, based on a known-good build of coreboot. + +To update the `coreboot.rom` file which is used: + +#. Build coreboot with `CONFIG_LINEAR_FRAMEBUFFER=y`. If using `make menuconfig` + this is under + `Devices ->Display->Framebuffer mode->Linear "high resolution" framebuffer`. + +#. Compress the resulting `coreboot.rom`:: + + xz -c /path/to/coreboot/build/coreboot.rom >coreboot.rom.xz + +#. Upload the file to Google drive + +#. Send a patch to change the file ID used by wget in the CI yaml files. diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst new file mode 100644 index 00000000000..950c713f2fa --- /dev/null +++ b/doc/board/htc/endeavoru.rst @@ -0,0 +1,89 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the HTC One X (endeavoru) +==================================== + +``DISCLAMER!`` Moving your HTC ONe X to use U-Boot assumes +replacement of the vendor hboot. Vendor android firmwares +will no longer be able to run on the device. +This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Pack U-Boot into repart-block +- Flash repart-block into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-linux-gnueabi- + $ make endeavoru_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for flashing (but check the next section for additional +adjustments). + +Pack U-Boot into repar-block +---------------------------- + +``DISCLAMER!`` All questions related to re-crypt work should be +asked in re-crypt repo issues. NOT HERE! + +re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in +form usable by device. This process is required only on the first +installation or to recover the device in case of a failed update. + +.. code-block:: bash + + $ git clone https://github.com/clamor-s/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-regra.bin here + $ ./re-crypt.sh -d endeavoru + +Script will produce you a ``repart-block.bin`` ready to flash. + +Flash repart-block into the eMMC +-------------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked +in the proper place. NOT HERE! Flashing repart-block will erase +all your eMMC, so make a backup before! + +``repart-block.bin`` contains BCT and bootloader in encrypted state +in form which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ wheelie --blob blob.bin + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +Boot +---- + +After flashing ``repart-block.bin`` the device should reboot and turn +itself off. This is normal behavior if no boot configuration is +found. + +To boot Linux, U-Boot will look for an ``extlinux.conf`` configuration +on eMMC. Additionally if Volume Down button is pressed while booting +device will enter bootmenu. Bootmenu contains entries to mount eMMC as +mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot +console and update bootloader (check next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC +and allows the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the +eMMC (using ability of u-boot to mount it). Enter bootmenu, choose +update bootloader option with Power button and U-Boot should update +itself. Once the process is completed, U-Boot will ask to press any +button to reboot. diff --git a/doc/board/htc/index.rst b/doc/board/htc/index.rst new file mode 100644 index 00000000000..955c9b9e03d --- /dev/null +++ b/doc/board/htc/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +HTC +=== + +.. toctree:: + :maxdepth: 2 + + endeavoru diff --git a/doc/board/index.rst b/doc/board/index.rst index 84aa8c158ab..0194f0aaa3e 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -14,6 +14,7 @@ Board-specific doc anbernic/index apple/index armltd/index + asus/index atmel/index beacon/index broadcom/index @@ -25,8 +26,10 @@ Board-specific doc gateworks/index google/index highbank/index + htc/index intel/index kontron/index + lg/index mediatek/index microchip/index nokia/index diff --git a/doc/board/lg/index.rst b/doc/board/lg/index.rst new file mode 100644 index 00000000000..3af3681e0bb --- /dev/null +++ b/doc/board/lg/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LG +== + +.. toctree:: + :maxdepth: 2 + + x3_t30 diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst new file mode 100644 index 00000000000..5c564aabc6a --- /dev/null +++ b/doc/board/lg/x3_t30.rst @@ -0,0 +1,93 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the LG X3 T30 device family +====================================== + +``DISCLAMER!`` Moving your LG P880 or P895 to use U-Boot +assumes replacement of the vendor LG bootloader. Vendor +android firmwares will no longer be able to run on the +device. This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Pack U-Boot into repart-block +- Flash repart-block into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +Device support is implemented by applying config fragment to a generic +board defconfig. Valid fragments are ``p880.config`` and ``p895.config``. + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-linux-gnueabi- + $ make x3_t30_defconfig p895.config # For LG Optimus Vu + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for flashing (but check the next section for additional +adjustments). + +Pack U-Boot into repar-block +---------------------------- + +``DISCLAMER!`` All questions related to re-crypt work should be +asked in re-crypt repo issues. NOT HERE! + +re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in +form usable by device. This process is required only on the first +installation or to recover the device in case of a failed update. + +.. code-block:: bash + + $ git clone https://github.com/clamor-s/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-regra.bin here + $ ./re-crypt.sh -d p895 + +Script will produce you a ``repart-block.bin`` ready to flash. + +Flash repart-block into the eMMC +-------------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked +in the proper place. NOT HERE! Flashing repart-block will erase +all your eMMC, so make a backup before! + +``repart-block.bin`` contains BCT and bootloader in encrypted state +in form which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ wheelie --blob blob.bin + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +Boot +---- + +After flashing ``repart-block.bin`` the device should reboot and turn +itself off. This is normal behavior if no boot configuration is +found. + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD +and then on eMMC. Additionally if Volume Down button is pressed +while booting device will enter bootmenu. Bootmenu contains entries +to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot +RCM, poweroff, enter U-Boot console and update bootloader (check next +chapter). + +Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC +and allows the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the +eMMC (using ability of u-boot to mount it). Enter bootmenu, choose +update bootloader option with Power button and U-Boot should update +itself. Once the process is completed, U-Boot will ask to press any +button to reboot. diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 49a0c5797ad..de9fe8e642b 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -91,17 +91,22 @@ List of mainline supported Rockchip boards: - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399) * rk3566 - - Anbernic RGxx3 (rgxx3-rk3566) + - Anbernic RGxx3 (anbernic-rgxx3-rk3566) + - Pine64 Quartz64-A Board (quartz64-a-rk3566) + - Pine64 Quartz64-B Board (quartz64-b-rk3566) + - Pine64 SOQuartz on Blade (soquartz-blade-rk3566) + - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566) + - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566) + - Radxa CM3 IO Board (radxa-cm3-io-rk3566) * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) + - EmbedFire LubanCat 2 (lubancat-2-rk3568) + - FriendlyElec NanoPi R5C (nanopi-r5c-rk3568) + - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) - - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) - - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) - - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig) + - Radxa E25 Carrier Board (radxa-e25-rk3568) + - Radxa ROCK 3 Model A (rock-3a-rk3568) * rk3588 - Rockchip EVB (evb-rk3588) diff --git a/doc/develop/printf.rst b/doc/develop/printf.rst index 7b9aea06876..99d05061b14 100644 --- a/doc/develop/printf.rst +++ b/doc/develop/printf.rst @@ -105,19 +105,19 @@ for the individual integer types. =================== ================== Type Format specifier =================== ================== -bool %d, %x +bool %d, %x char %d, %x unsigned char %u, %x short %d, %x unsigned short %u, %x int %d, %x -unsigned int %d, %x +unsigned int %u, %x long %ld, %lx unsigned long %lu, %lx long long %lld, %llx unsigned long long %llu, %llx off_t %llu, %llx -ptr_diff_t %td, %tx +ptr_diff_t %td, %tx fdt_addr_t %pa, see pointers fdt_size_t %pa, see pointers phys_addr_t %pa, see pointers diff --git a/doc/develop/trace.rst b/doc/develop/trace.rst index 9bbe1345d2d..546862020b1 100644 --- a/doc/develop/trace.rst +++ b/doc/develop/trace.rst @@ -139,7 +139,7 @@ There is a -f option available to select a function graph: .. code-block:: console - $ ./sandbox/tools/proftool -m sandbox/System.map -t trace -f funcgraph dump-ftrace >trace.dat + $ ./sandbox/tools/proftool -m sandbox/System.map -t trace -f funcgraph dump-ftrace -o trace.dat Again, you can use kernelshark or trace-cmd to look at the output. In this case you will see the time taken by each function shown against its exit record. @@ -171,7 +171,7 @@ command: .. code-block:: console - $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph >trace.fg + $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph -o trace.fg $ flamegraph.pl trace.fg >trace.svg You can load the .svg file into a viewer. If you use Chrome (and some other @@ -191,7 +191,7 @@ spend in each call stack: .. code-block:: console - $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph -f timing >trace.fg + $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph -f timing -o trace.fg $ flamegraph.pl trace.fg >trace.svg Note that trace collection does slow down execution so the timings will be diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index d87015f6c4e..65c143073cb 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -11,7 +11,6 @@ # 1) Build U-Boot (e.g. for i.MX8MM) # -# export ATF_LOAD_ADDR=0x920000 # cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin . # cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* . # make -j imx8mm_board_defconfig diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index b74661ad3f1..4f411f78d03 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -1,6 +1,6 @@ alabaster==0.7.12 Babel==2.9.1 -certifi==2023.5.7 +certifi==2023.07.22 charset-normalizer==2.0.12 docutils==0.16 idna==3.3 diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 64f33587e28..d0a3f654466 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -150,7 +150,7 @@ static ulong rk3308_i2c_get_clk(struct clk *clk) } con = readl(&cru->clksel_con[con_id]); - div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT; return DIV_TO_RATE(priv->dpll_hz, div); } @@ -314,7 +314,7 @@ static ulong rk3308_saradc_get_clk(struct clk *clk) u32 div, con; con = readl(&cru->clksel_con[34]); - div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; + div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT; return DIV_TO_RATE(OSC_HZ, div); } @@ -342,7 +342,7 @@ static ulong rk3308_tsadc_get_clk(struct clk *clk) u32 div, con; con = readl(&cru->clksel_con[33]); - div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; + div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT; return DIV_TO_RATE(OSC_HZ, div); } @@ -385,7 +385,7 @@ static ulong rk3308_spi_get_clk(struct clk *clk) } con = readl(&cru->clksel_con[con_id]); - div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; + div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT; return DIV_TO_RATE(priv->dpll_hz, div); } @@ -429,7 +429,7 @@ static ulong rk3308_pwm_get_clk(struct clk *clk) u32 div, con; con = readl(&cru->clksel_con[29]); - div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; + div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT; return DIV_TO_RATE(priv->dpll_hz, div); } @@ -451,6 +451,58 @@ static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz) return rk3308_pwm_get_clk(clk); } +static ulong rk3308_uart_get_clk(struct clk *clk) +{ + struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3308_cru *cru = priv->cru; + u32 div, pll_sel, con, con_id, parent; + + switch (clk->id) { + case SCLK_UART0: + con_id = 10; + break; + case SCLK_UART1: + con_id = 13; + break; + case SCLK_UART2: + con_id = 16; + break; + case SCLK_UART3: + con_id = 19; + break; + case SCLK_UART4: + con_id = 22; + break; + default: + printf("do not support this uart interface\n"); + return -EINVAL; + } + + con = readl(&cru->clksel_con[con_id]); + pll_sel = (con & CLK_UART_PLL_SEL_MASK) >> CLK_UART_PLL_SEL_SHIFT; + div = (con & CLK_UART_DIV_CON_MASK) >> CLK_UART_DIV_CON_SHIFT; + + switch (pll_sel) { + case CLK_UART_PLL_SEL_DPLL: + parent = priv->dpll_hz; + break; + case CLK_UART_PLL_SEL_VPLL0: + parent = priv->vpll0_hz; + break; + case CLK_UART_PLL_SEL_VPLL1: + parent = priv->vpll0_hz; + break; + case CLK_UART_PLL_SEL_24M: + parent = OSC_HZ; + break; + default: + printf("do not support this uart pll sel\n"); + return -EINVAL; + } + + return DIV_TO_RATE(parent, div); +} + static ulong rk3308_vop_get_clk(struct clk *clk) { struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); @@ -813,6 +865,13 @@ static ulong rk3308_clk_get_rate(struct clk *clk) case SCLK_EMMC_SAMPLE: rate = rk3308_mmc_get_clk(clk); break; + case SCLK_UART0: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + rate = rk3308_uart_get_clk(clk); + break; case SCLK_I2C0: case SCLK_I2C1: case SCLK_I2C2: diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 0df82f59715..599b7b130eb 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -702,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv, } div = DIV_ROUND_UP(priv->cpll_hz, rate); - assert(div - 1 <= 31); + if (clk_id == CPLL_25M) + assert(div - 1 <= 63); + else + assert(div - 1 <= 31); rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift); return rk3568_cpll_div_get_rate(priv, clk_id); @@ -1142,7 +1145,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) switch (clk_id) { case CLK_PWM1: - sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; break; case CLK_PWM2: sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; @@ -2186,6 +2189,7 @@ static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv, return rk3568_rkvdec_get_clk(priv, clk_id); } +#endif static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id) { @@ -2321,7 +2325,6 @@ static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv, return rk3568_uart_get_rate(priv, clk_id); } -#endif static ulong rk3568_clk_get_rate(struct clk *clk) { @@ -2460,6 +2463,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case TCLK_WDT_NS: rate = OSC_HZ; break; +#endif case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: @@ -2471,7 +2475,6 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case SCLK_UART9: rate = rk3568_uart_get_rate(priv, clk->id); break; -#endif case ACLK_SECURE_FLASH: case ACLK_CRYPTO_NS: case HCLK_SECURE_FLASH: @@ -2645,6 +2648,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case TCLK_WDT_NS: ret = OSC_HZ; break; +#endif case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: @@ -2656,7 +2660,6 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case SCLK_UART9: ret = rk3568_uart_set_rate(priv, clk->id, rate); break; -#endif case ACLK_SECURE_FLASH: case ACLK_CRYPTO_NS: case HCLK_SECURE_FLASH: @@ -2840,6 +2843,10 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent) case CLK_RKVDEC_CORE: return rk3568_rkvdec_set_parent(clk, parent); case I2S1_MCLKOUT_TX: + case SCLK_GMAC0_RGMII_SPEED: + case SCLK_GMAC0_RMII_SPEED: + case SCLK_GMAC1_RGMII_SPEED: + case SCLK_GMAC1_RMII_SPEED: break; default: return -ENOENT; diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 4f4524fcb2c..61502876949 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -881,7 +881,8 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, return sel[s].parent[p]; } - log_err("no parents defined for clk id %d\n", (u32)id); + /* clock is DISABLED when the clock src is not in clk_parent[] range */ + log_debug("no parents defined for clk id %d\n", (u32)id); return -EINVAL; } diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index ffa9d81fa74..8c17b19eaf5 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -201,11 +201,11 @@ int ffa_get_version_hdlr(struct udevice *dev) major = GET_FFA_MAJOR_VERSION(res.a0); minor = GET_FFA_MINOR_VERSION(res.a0); - log_info("FF-A driver %d.%d\nFF-A framework %d.%d\n", + log_debug("FF-A driver %d.%d\nFF-A framework %d.%d\n", FFA_MAJOR_VERSION, FFA_MINOR_VERSION, major, minor); if (major == FFA_MAJOR_VERSION && minor >= FFA_MINOR_VERSION) { - log_info("FF-A versions are compatible\n"); + log_debug("FF-A versions are compatible\n"); if (dev) { uc_priv = dev_get_uclass_priv(dev); diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c index 68df75bd9e5..ee0bf9a55b4 100644 --- a/drivers/firmware/arm-ffa/arm-ffa.c +++ b/drivers/firmware/arm-ffa/arm-ffa.c @@ -42,7 +42,7 @@ static bool arm_ffa_discover(struct udevice *dev) { int ret; - log_info("Arm FF-A framework discovery\n"); + log_debug("Arm FF-A framework discovery\n"); ret = ffa_get_version_hdlr(dev); if (ret) diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c index 5562bbaac3a..4bf9f6041fe 100644 --- a/drivers/firmware/arm-ffa/ffa-emul-uclass.c +++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c @@ -695,7 +695,7 @@ int ffa_emul_find(struct udevice *dev, struct udevice **emulp) return ret; } - log_info("FF-A emulator ready to use\n"); + log_debug("FF-A emulator ready to use\n"); return 0; } diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c index ef9491ccead..11142429c09 100644 --- a/drivers/firmware/arm-ffa/sandbox_ffa.c +++ b/drivers/firmware/arm-ffa/sandbox_ffa.c @@ -30,7 +30,7 @@ static int sandbox_ffa_discover(struct udevice *dev) int ret; struct udevice *emul; - log_info("Emulated FF-A framework discovery\n"); + log_debug("Emulated FF-A framework discovery\n"); ret = ffa_emul_find(dev, &emul); if (ret) { diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 93bbc6916e5..14cdb0f6635 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -142,6 +142,8 @@ enum mvtwsi_ctrl_register_fields { * code. */ enum mvstwsi_status_values { + /* Protocol violation on bus; this is a terminal state */ + MVTWSI_BUS_ERROR = 0x00, /* START condition transmitted */ MVTWSI_STATUS_START = 0x08, /* Repeated START condition transmitted */ @@ -526,6 +528,36 @@ static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, } /* + * __twsi_i2c_reinit() - Reset and reinitialize the I2C controller. + * + * This function should be called to get the MVTWSI controller out of the + * "bus error" state. It saves and restores the baud and address registers. + * + * @twsi: The MVTWSI register structure to use. + * @tick: The duration of a clock cycle at the current I2C speed. + */ +static void __twsi_i2c_reinit(struct mvtwsi_registers *twsi, uint tick) +{ + uint baud; + uint slaveadd; + + /* Save baud, address registers */ + baud = readl(&twsi->baudrate); + slaveadd = readl(&twsi->slave_address); + + /* Reset controller */ + twsi_reset(twsi); + + /* Restore baud, address registers */ + writel(baud, &twsi->baudrate); + writel(slaveadd, &twsi->slave_address); + writel(0, &twsi->xtnd_slave_addr); + + /* Assert STOP, but don't care for the result */ + (void) twsi_stop(twsi, tick); +} + +/* * i2c_begin() - Start a I2C transaction. * * Begin a I2C transaction with a given expected start status and chip address. @@ -621,6 +653,11 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, int stop_status; int expected_start = MVTWSI_STATUS_START; + /* Check for (and clear) a bus error from a previous failed transaction + * or another master on the same bus */ + if (readl(&twsi->status) == MVTWSI_BUS_ERROR) + __twsi_i2c_reinit(twsi, tick); + if (alen > 0) { /* Begin i2c write to send the address bytes */ status = i2c_begin(twsi, expected_start, (chip << 1), tick); @@ -668,6 +705,11 @@ static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, { int status, stop_status; + /* Check for (and clear) a bus error from a previous failed transaction + * or another master on the same bus */ + if (readl(&twsi->status) == MVTWSI_BUS_ERROR) + __twsi_i2c_reinit(twsi, tick); + /* Begin i2c write to send first the address bytes, then the * data bytes */ status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 72b41398f27..624841e9d8b 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -12,23 +12,15 @@ */ #include <common.h> -#include <clk.h> #include <dm.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <generic-phy.h> #include <pci.h> -#include <power-domain.h> #include <power/regulator.h> #include <reset.h> -#include <syscon.h> -#include <asm/io.h> #include <asm-generic/gpio.h> -#include <asm/arch-rockchip/clock.h> #include <linux/iopoll.h> -DECLARE_GLOBAL_DATA_PTR; - #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) @@ -383,41 +375,38 @@ static int rockchip_pcie_set_vpcie(struct udevice *dev) struct rockchip_pcie *priv = dev_get_priv(dev); int ret; - if (priv->vpcie3v3) { - ret = regulator_set_enable(priv->vpcie3v3, true); - if (ret) { - dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", - ret); - return ret; - } + ret = regulator_set_enable_if_allowed(priv->vpcie12v, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable vpcie12v (ret=%d)\n", ret); + return ret; } - if (priv->vpcie1v8) { - ret = regulator_set_enable(priv->vpcie1v8, true); - if (ret) { - dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", - ret); - goto err_disable_3v3; - } + ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret); + goto err_disable_12v; } - if (priv->vpcie0v9) { - ret = regulator_set_enable(priv->vpcie0v9, true); - if (ret) { - dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", - ret); - goto err_disable_1v8; - } + ret = regulator_set_enable_if_allowed(priv->vpcie1v8, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret); + goto err_disable_3v3; + } + + ret = regulator_set_enable_if_allowed(priv->vpcie0v9, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret); + goto err_disable_1v8; } return 0; err_disable_1v8: - if (priv->vpcie1v8) - regulator_set_enable(priv->vpcie1v8, false); + regulator_set_enable_if_allowed(priv->vpcie1v8, false); err_disable_3v3: - if (priv->vpcie3v3) - regulator_set_enable(priv->vpcie3v3, false); + regulator_set_enable_if_allowed(priv->vpcie3v3, false); +err_disable_12v: + regulator_set_enable_if_allowed(priv->vpcie12v, false); return ret; } @@ -427,19 +416,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) int ret; priv->axi_base = dev_read_addr_name(dev, "axi-base"); - if (!priv->axi_base) - return -ENODEV; + if (priv->axi_base == FDT_ADDR_T_NONE) + return -EINVAL; priv->apb_base = dev_read_addr_name(dev, "apb-base"); - if (!priv->axi_base) - return -ENODEV; - - ret = gpio_request_by_name(dev, "ep-gpios", 0, - &priv->ep_gpio, GPIOD_IS_OUT); - if (ret) { - dev_err(dev, "failed to find ep-gpios property\n"); - return ret; - } + if (priv->apb_base == FDT_ADDR_T_NONE) + return -EINVAL; ret = reset_get_by_name(dev, "core", &priv->core_rst); if (ret) { @@ -483,6 +465,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) return ret; } + ret = device_get_supply_regulator(dev, "vpcie12v-supply", + &priv->vpcie12v); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get vpcie12v supply (ret=%d)\n", ret); + return ret; + } + ret = device_get_supply_regulator(dev, "vpcie3v3-supply", &priv->vpcie3v3); if (ret && ret != -ENOENT) { @@ -510,6 +499,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) return ret; } + ret = gpio_request_by_name(dev, "ep-gpios", 0, + &priv->ep_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "failed to find ep-gpios property\n"); + return ret; + } + return 0; } @@ -529,16 +525,26 @@ static int rockchip_pcie_probe(struct udevice *dev) ret = rockchip_pcie_set_vpcie(dev); if (ret) - return ret; + goto err_gpio_free; ret = rockchip_pcie_init_port(dev); if (ret) - return ret; + goto err_disable_vpcie; dev_info(dev, "PCIE-%d: Link up (Bus%d)\n", dev_seq(dev), hose->first_busno); return 0; + +err_disable_vpcie: + regulator_set_enable_if_allowed(priv->vpcie0v9, false); + regulator_set_enable_if_allowed(priv->vpcie1v8, false); + regulator_set_enable_if_allowed(priv->vpcie3v3, false); + regulator_set_enable_if_allowed(priv->vpcie12v, false); +err_gpio_free: + if (dm_gpio_is_valid(&priv->ep_gpio)) + dm_gpio_free(dev, &priv->ep_gpio); + return ret; } static const struct dm_pci_ops rockchip_pcie_ops = { @@ -552,10 +558,10 @@ static const struct udevice_id rockchip_pcie_ids[] = { }; U_BOOT_DRIVER(rockchip_pcie) = { - .name = "rockchip_pcie", - .id = UCLASS_PCI, - .of_match = rockchip_pcie_ids, - .ops = &rockchip_pcie_ops, - .probe = rockchip_pcie_probe, + .name = "rockchip_pcie", + .id = UCLASS_PCI, + .of_match = rockchip_pcie_ids, + .ops = &rockchip_pcie_ops, + .probe = rockchip_pcie_probe, .priv_auto = sizeof(struct rockchip_pcie), }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 314edb5a606..1d439198260 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -113,11 +113,9 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct rockchip_pinctrl_priv *priv = bank->priv; int iomux_num = (pin / 8); struct regmap *regmap; - int reg, ret, mask; + int reg, mask; u8 bit; - u32 data; - - debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + u32 data, rmask; if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) regmap = priv->regmap_pmu; @@ -131,10 +129,10 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) mask = 0xf; data = (mask << (bit + 16)); + rmask = data | (data >> 16); data |= (mux & mask) << bit; - ret = regmap_write(regmap, reg, data); - return ret; + return regmap_update_bits(regmap, reg, rmask, data); } #define RK3568_PULL_PMU_OFFSET 0x20 @@ -225,7 +223,7 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, struct regmap *regmap; int reg, ret; u8 bit, type; - u32 data; + u32 data, rmask; if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) return -ENOTSUPP; @@ -249,52 +247,59 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, /* enable the write to the equivalent lower bits */ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - + rmask = data | (data >> 16); data |= (ret << bit); - ret = regmap_write(regmap, reg, data); - return ret; + return regmap_update_bits(regmap, reg, rmask, data); } +#define GRF_GPIO1C5_DS 0x0840 +#define GRF_GPIO2A2_DS 0x0844 +#define GRF_GPIO2B0_DS 0x0848 +#define GRF_GPIO3A0_DS 0x084c +#define GRF_GPIO3A6_DS 0x0850 +#define GRF_GPIO4A0_DS 0x0854 + static int rk3568_set_drive(struct rockchip_pin_bank *bank, int pin_num, int strength) { struct regmap *regmap; - int reg; - u32 data; + int reg, ret; + u32 data, rmask; u8 bit; int drv = (1 << (strength + 1)) - 1; - int ret = 0; rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); /* enable the write to the equivalent lower bits */ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); data |= (drv << bit); - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); if (ret) return ret; if (bank->bank_num == 1 && pin_num == 21) - reg = 0x0840; + reg = GRF_GPIO1C5_DS; else if (bank->bank_num == 2 && pin_num == 2) - reg = 0x0844; + reg = GRF_GPIO2A2_DS; else if (bank->bank_num == 2 && pin_num == 8) - reg = 0x0848; + reg = GRF_GPIO2B0_DS; else if (bank->bank_num == 3 && pin_num == 0) - reg = 0x084c; + reg = GRF_GPIO3A0_DS; else if (bank->bank_num == 3 && pin_num == 6) - reg = 0x0850; + reg = GRF_GPIO3A6_DS; else if (bank->bank_num == 4 && pin_num == 0) - reg = 0x0854; + reg = GRF_GPIO4A0_DS; else return 0; data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; - data |= drv; + rmask = data | (data >> 16); + data |= drv >> 6; - return regmap_write(regmap, reg, data); + return regmap_update_bits(regmap, reg, rmask, data); } static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, @@ -302,16 +307,17 @@ static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, { struct regmap *regmap; int reg; - u32 data; + u32 data, rmask; u8 bit; rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); /* enable the write to the equivalent lower bits */ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); - data |= (enable << bit); + rmask = data | (data >> 16); + data |= ((enable ? 0x2 : 0x1) << bit); - return regmap_write(regmap, reg, data); + return regmap_update_bits(regmap, reg, rmask, data); } static struct rockchip_pin_bank rk3568_pin_banks[] = { diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 0085113f674..23d476fba28 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -22,6 +22,14 @@ #include "serial_stm32.h" #include <dm/device_compat.h> +/* + * At 115200 bits/s + * 1 bit = 1 / 115200 = 8,68 us + * 8 bits = 69,444 us + * 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us + */ +#define ONE_BYTE_B115200_US 87 + static void _stm32_serial_setbrg(fdt_addr_t base, struct stm32_uart_info *uart_info, u32 clock_rate, @@ -209,12 +217,10 @@ static int stm32_serial_probe(struct udevice *dev) * before uart initialization, wait for TC bit (Transmission Complete) * in case there is still chars from previous bootstage to transmit */ - ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 10, 150, - plat->base + ISR_OFFSET(stm32f4)); - if (ret) { - clk_disable(&clk); - return ret; - } + ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50, + 16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4)); + if (ret) + dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret); ret = reset_get_by_index(dev, 0, &reset); if (!ret) { diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2a37d026bc2..69f4809cf4a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1115,7 +1115,7 @@ config SPL_VIDEO_REMOVE bool "Remove video driver after SPL stage" help if this option is enabled video driver will be removed at the end of - SPL stage, beforeloading the next stage. + SPL stage, before loading the next stage. if SPL_SPLASH_SCREEN diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index c2962932c97..14942526f19 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -54,6 +54,9 @@ static const struct udevice_id bcm2835_video_ids[] = { { .compatible = "brcm,bcm2835-hdmi" }, { .compatible = "brcm,bcm2711-hdmi0" }, { .compatible = "brcm,bcm2708-fb" }, +#if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) + { .compatible = "simple-framebuffer" }, +#endif { } }; diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c index 46c16a8f447..aa0e2928666 100644 --- a/drivers/video/pwm_backlight.c +++ b/drivers/video/pwm_backlight.c @@ -14,6 +14,7 @@ #include <pwm.h> #include <asm/gpio.h> #include <linux/delay.h> +#include <linux/math64.h> #include <power/regulator.h> /** @@ -59,12 +60,14 @@ struct pwm_backlight_priv { static int set_pwm(struct pwm_backlight_priv *priv) { + u64 width; uint duty_cycle; int ret; if (priv->period_ns) { - duty_cycle = (u64)priv->period_ns * (priv->cur_level - priv->min_level) / - (priv->max_level - priv->min_level); + width = priv->period_ns * (priv->cur_level - priv->min_level); + duty_cycle = div_u64(width, + (priv->max_level - priv->min_level)); ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns, duty_cycle); } else { diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 05f93047809..b5b3b662590 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -603,7 +603,7 @@ int vidconsole_measure(struct udevice *dev, const char *name, uint size, struct vidconsole_ops *ops = vidconsole_get_ops(dev); int ret; - if (ops->select_font) { + if (ops->measure) { ret = ops->measure(dev, name, size, text, bbox); if (ret != -ENOSYS) return ret; diff --git a/fs/erofs/super.c b/fs/erofs/super.c index d33926281b4..d405d488fd2 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -68,14 +68,14 @@ int erofs_read_superblock(void) ret = erofs_blk_read(data, 0, erofs_blknr(sizeof(data))); if (ret < 0) { - erofs_err("cannot read erofs superblock: %d", ret); + erofs_dbg("cannot read erofs superblock: %d", ret); return -EIO; } dsb = (struct erofs_super_block *)(data + EROFS_SUPER_OFFSET); ret = -EINVAL; if (le32_to_cpu(dsb->magic) != EROFS_SUPER_MAGIC_V1) { - erofs_err("cannot find valid erofs superblock"); + erofs_dbg("cannot find valid erofs superblock"); return ret; } diff --git a/include/clk-uclass.h b/include/clk-uclass.h index 65ebff9ed27..a22f1a5d848 100644 --- a/include/clk-uclass.h +++ b/include/clk-uclass.h @@ -64,7 +64,7 @@ int of_xlate(struct clk *clock, struct ofnode_phandle_args *args); /** * request() - Request a translated clock. - * @clock: The clock struct to request; this has been fille in by + * @clock: The clock struct to request; this has been filled in by * a previoux xxx_xlate() function call, or by the caller * of clk_request(). * diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h new file mode 100644 index 00000000000..46c582e963e --- /dev/null +++ b/include/configs/endeavoru.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2012 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#include "tegra30-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "HTC One X" + +#define ENDEAVORU_FLASH_UBOOT \ + "flash_uboot=echo Preparing RAM;" \ + "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ + "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ + "echo Reading BCT;" \ + "mmc dev 0 1;" \ + "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ + "echo Reading bootloader;" \ + "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \ + "then echo Calculating bootloader size;" \ + "size mmc 0:1 ${bootloader_file};" \ + "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ + "echo Writing bootloader to eMMC;" \ + "mmc dev 0 1;" \ + "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ + "mmc dev 0 2;" \ + "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ + "echo Bootloader written successfully;" \ + "pause 'Press ANY key to reboot device...'; reset;" \ + "else echo Reading bootloader failed;" \ + "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" + +#define ENDEAVORU_BOOTMENU \ + ENDEAVORU_FLASH_UBOOT \ + "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ + "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ + "bootmenu_2=update bootloader=run flash_uboot\0" \ + "bootmenu_3=reboot RCM=enterrcm\0" \ + "bootmenu_4=reboot=reset\0" \ + "bootmenu_5=power off=poweroff\0" \ + "bootmenu_delay=-1\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "boot_block_size_r=0x200000\0" \ + "boot_block_size=0x1000\0" \ + "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "check_button=gpio input 179; test $? -eq 0\0" \ + "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ + ENDEAVORU_BOOTMENU + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h new file mode 100644 index 00000000000..93304ddc6e8 --- /dev/null +++ b/include/configs/grouper.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#include "tegra30-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" + +#define GROUPER_FLASH_UBOOT \ + "flash_uboot=echo Preparing RAM;" \ + "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ + "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ + "echo Reading BCT;" \ + "mmc dev 0 1;" \ + "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ + "echo Reading bootloader;" \ + "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \ + "then echo Calculating bootloader size;" \ + "size mmc 0:1 ${bootloader_file};" \ + "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ + "echo Writing bootloader to eMMC;" \ + "mmc dev 0 1;" \ + "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ + "mmc dev 0 2;" \ + "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ + "echo Bootloader written successfully;" \ + "pause 'Press ANY key to reboot device...'; reset;" \ + "else echo Reading bootloader failed;" \ + "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" + +#define GROUPER_BOOTMENU \ + GROUPER_FLASH_UBOOT \ + "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ + "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ + "bootmenu_2=update bootloader=run flash_uboot\0" \ + "bootmenu_3=reboot RCM=enterrcm\0" \ + "bootmenu_4=reboot=reset\0" \ + "bootmenu_5=power off=poweroff\0" \ + "bootmenu_delay=-1\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "boot_block_size_r=0x200000\0" \ + "boot_block_size=0x1000\0" \ + "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "check_button=gpio input 131; test $? -eq 0;\0" \ + "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ + GROUPER_BOOTMENU + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index 1ec1640f99d..a64c0c63642 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -24,6 +24,7 @@ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ "fdt_addr_r=0x08300000\0" \ + "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02008000\0" \ "ramdisk_addr_r=0x0a200000\0" diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index b45982a35b8..60838cb0e3f 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -10,7 +10,9 @@ #define STM32MP_BOARD_EXTRA_ENV \ "usb_pgood_delay=2000\0" \ - "console=ttySTM0\0" + "console=ttySTM0\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "splashpos=m,m\0" #include <configs/stm32mp15_common.h> diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 991ffbb7dff..0d0965ecce2 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -8,9 +8,21 @@ #define __TEGRA_COMMON_POST_H #if IS_ENABLED(CONFIG_CMD_USB) -# define BOOT_TARGET_USB(func) func(USB, usb, 0) +#define BOOT_TARGET_USB(func) func(USB, usb, 0) #else -# define BOOT_TARGET_USB(func) +#define BOOT_TARGET_USB(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) && CONFIG_IS_ENABLED(CMD_PXE) +#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) +#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DHCP(func) #endif #ifndef BOOT_TARGET_DEVICES @@ -18,8 +30,8 @@ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ BOOT_TARGET_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) #endif #include <config_distro_bootcmd.h> @@ -35,6 +47,12 @@ #define STDIN_KBD_USB "" #endif +#ifdef CONFIG_BUTTON_KEYBOARD +#define STDIN_BTN_KBD ",button-kbd" +#else +#define STDIN_BTN_KBD "" +#endif + #ifdef CONFIG_VIDEO #define STDOUT_VIDEO ",vidconsole" #else @@ -48,7 +66,7 @@ #endif #define TEGRA_DEVICE_SETTINGS \ - "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \ + "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC STDIN_BTN_KBD "\0" \ "stdout=serial" STDOUT_VIDEO "\0" \ "stderr=serial" STDOUT_VIDEO "\0" \ "" diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h new file mode 100644 index 00000000000..dcdda1ec5b4 --- /dev/null +++ b/include/configs/transformer-common.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>. + */ + +#ifndef __TRANSFORMER_COMMON_H +#define __TRANSFORMER_COMMON_H + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" + +#define TRANSFORMER_FLASH_UBOOT \ + "flash_uboot=echo Preparing RAM;" \ + "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ + "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ + "echo Reading BCT;" \ + "mmc dev 0 1;" \ + "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ + "echo Reading bootloader;" \ + "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \ + "then echo Calculating bootloader size;" \ + "size mmc 1:1 ${bootloader_file};" \ + "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ + "echo Writing bootloader to eMMC;" \ + "mmc dev 0 1;" \ + "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ + "mmc dev 0 2;" \ + "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ + "echo Bootloader written successfully;" \ + "pause 'Press ANY key to reboot device...'; reset;" \ + "else echo Reading bootloader failed;" \ + "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" + +#define TRANSFORMER_FLASH_SPI \ + "update_spi=sf probe 0:1;" \ + "echo Dumping current SPI flash content ...;" \ + "sf read ${kernel_addr_r} 0x0 ${spi_size};" \ + "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \ + "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \ + "echo Reading SPI flash binary;" \ + "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \ + "then echo Writing bootloader into SPI flash;" \ + "sf probe 0:1;" \ + "sf update ${kernel_addr_r} 0x0 ${spi_size};" \ + "poweroff;" \ + "else echo Preparing RAM;" \ + "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ + "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ + "echo Reading BCT;" \ + "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \ + "echo Reading bootloader;" \ + "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \ + "then echo Calculating bootloader size;" \ + "size mmc 1:1 ${bootloader_file};" \ + "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ + "echo Writing bootloader into SPI flash;" \ + "sf probe 0:1;" \ + "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \ + "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \ + "echo Bootloader written successfully; poweroff;" \ + "else echo Reading bootloader failed;" \ + "poweroff; fi;" \ + "fi;" \ + "else echo SPI flash backup FAILED! Aborting ...;" \ + "poweroff; fi\0" + +#define TRANSFORMER_REFRESH_USB \ + "refresh_usb=usb start; usb reset; usb tree; usb info;" \ + "pause 'Press ANY key to return to bootmenu...'; bootmenu\0" + +#define TRANSFORMER_BOOTMENU \ + TRANSFORMER_FLASH_UBOOT \ + TRANSFORMER_FLASH_SPI \ + TRANSFORMER_REFRESH_USB \ + "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ + "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ + "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ + "bootmenu_3=update bootloader=run flash_uboot\0" \ + "bootmenu_4=refresh USB=run refresh_usb\0" \ + "bootmenu_5=reboot RCM=enterrcm\0" \ + "bootmenu_6=reboot=reset\0" \ + "bootmenu_7=power off=poweroff\0" \ + "bootmenu_delay=-1\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "spi_size=0x400000\0" \ + "boot_block_size_r=0x200000\0" \ + "boot_block_size=0x1000\0" \ + "check_button=gpio input ${gpio_button}; test $? -eq 0;\0" \ + "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ + TRANSFORMER_BOOTMENU + +#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h new file mode 100644 index 00000000000..d2a16f12c18 --- /dev/null +++ b/include/configs/transformer-t30.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2012 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#include "tegra30-common.h" +#include "transformer-common.h" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h new file mode 100644 index 00000000000..d29ea700b2e --- /dev/null +++ b/include/configs/x3-t30.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2012 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#include "tegra30-common.h" + +#define CFG_TEGRA_BOARD_STRING "LG X3 Board" + +#ifdef CONFIG_DEVICE_P880 +/* High-level configuration options */ +#undef CFG_TEGRA_BOARD_STRING +#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD" +#endif + +#ifdef CONFIG_DEVICE_P895 +/* High-level configuration options */ +#undef CFG_TEGRA_BOARD_STRING +#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu" +#endif + +#define X3_FLASH_UBOOT \ + "flash_uboot=echo Preparing RAM;" \ + "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ + "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ + "echo Reading BCT;" \ + "mmc dev 0 1;" \ + "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ + "echo Reading bootloader;" \ + "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \ + "then echo Calculating bootloader size;" \ + "size mmc 0:1 ${bootloader_file};" \ + "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ + "echo Writing bootloader to eMMC;" \ + "mmc dev 0 1;" \ + "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ + "mmc dev 0 2;" \ + "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ + "echo Bootloader written successfully;" \ + "pause 'Press ANY key to reboot device...'; reset;" \ + "else echo Reading bootloader failed;" \ + "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" + +#define X3_BOOTMENU \ + X3_FLASH_UBOOT \ + "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ + "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ + "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ + "bootmenu_3=update bootloader=run flash_uboot\0" \ + "bootmenu_4=reboot RCM=enterrcm\0" \ + "bootmenu_5=reboot=reset\0" \ + "bootmenu_6=power off=poweroff\0" \ + "bootmenu_delay=-1\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "boot_block_size_r=0x200000\0" \ + "boot_block_size=0x1000\0" \ + "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "check_button=gpio input 116; test $? -eq 0\0" \ + "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ + X3_BOOTMENU + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/init.h b/include/init.h index 88730816851..3bf30476a2e 100644 --- a/include/init.h +++ b/include/init.h @@ -296,15 +296,20 @@ int checkboard(void); int show_board_info(void); /** - * Get the uppermost pointer that is valid to access + * board_get_usable_ram_top() - get uppermost address for U-Boot relocation * - * Some systems may not map all of their address space. This function allows - * boards to indicate what their highest support pointer value is for DRAM - * access. + * Some systems have reserved memory areas in high memory. By implementing this + * function boards can indicate the highest address value to be used when + * relocating U-Boot. The returned address is exclusive (i.e. 1 byte above the + * last usable address). * - * @param total_size Size of U-Boot (unused?) + * Due to overflow on systems with 32bit phys_addr_t a value 0 is used instead + * of 4GiB. + * + * @total_size: monitor length in bytes (size of U-Boot code) + * Return: uppermost address for U-Boot relocation */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size); +phys_addr_t board_get_usable_ram_top(phys_size_t total_size); int board_early_init_f(void); diff --git a/include/irq.h b/include/irq.h index 1d08cb858d0..5638c10128e 100644 --- a/include/irq.h +++ b/include/irq.h @@ -109,7 +109,7 @@ struct irq_ops { * xxx_xlate() call, or as the only step in implementing a client's * irq_request() call. * - * @irq: The irq struct to request; this has been fille in by + * @irq: The irq struct to request; this has been filled in by * a previoux xxx_xlate() function call, or by the caller * of irq_request(). * @return 0 if OK, or a negative error code. diff --git a/include/lmb.h b/include/lmb.h index 07bf22144ea..231b68b27d9 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -116,16 +116,31 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr); phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size); phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr); + +/** + * lmb_is_reserved() - test if address is in reserved region + * + * The function checks if a reserved region comprising @addr exists. + * + * @lmb: the logical memory block struct + * @addr: address to be tested + * Return: 1 if reservation exists, 0 otherwise + */ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); + /** - * lmb_is_reserved_flags - test if tha address is in reserved region with a bitfield flag + * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set + * + * The function checks if a reserved region comprising @addr exists which has + * all flag bits set which are set in @flags. * * @lmb: the logical memory block struct * @addr: address to be tested - * @flags: flags bitfied to be tested - * Return: if not reserved or reserved without the requested flag else 1 + * @flags: bitmap with bits to be tested + * Return: 1 if matching reservation exists, 0 otherwise */ int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags); + long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); void lmb_dump_all(struct lmb *lmb); diff --git a/include/part.h b/include/part.h index edc46f8dcbe..8e451bbdff9 100644 --- a/include/part.h +++ b/include/part.h @@ -98,8 +98,8 @@ struct disk_part { * @ifname: Interface name (e.g. "ide", "scsi") * @dev: Device number (0 for first device on that interface, 1 for * second, etc. - * Return: pointer to the block device, or NULL if not available, or an - * error occurred. + * Return: + * pointer to the block device, or NULL if not available, or an error occurred. */ struct blk_desc *blk_get_dev(const char *ifname, int dev); @@ -128,6 +128,10 @@ int part_get_info(struct blk_desc *dev_desc, int part, /** * part_get_info_whole_disk() - get partition info for the special case of * a partition occupying the entire disk. + * + * @dev_desc: block device descriptor + * @info: returned partition information + * Return: 0 on success */ int part_get_info_whole_disk(struct blk_desc *dev_desc, struct disk_partition *info); @@ -170,15 +174,18 @@ int blk_get_device_by_str(const char *ifname, const char *dev_str, * This calls blk_get_device_by_str() to look up a device. It also looks up * a partition and returns information about it. * - * @dev_part_str is in the format: - * <dev>.<hw_part>:<part> where <dev> is the device number, - * <hw_part> is the optional hardware partition number and - * <part> is the partition number + * @dev_part_str is in the format <dev>.<hw_part>:<part> where + * + * * <dev> is the device number, + * + * * <hw_part> is the optional hardware partition number and * - * If ifname is "hostfs" then this function returns the sandbox host block + * * <part> is the partition number. + * + * If @ifname is "hostfs", then this function returns the sandbox host block * device. * - * If ifname is ubi, then this function returns 0, with @info set to a + * If @ifname is "ubi", then this function returns 0, with @info set to a * special UBI device. * * If @dev_part_str is NULL or empty or "-", then this function looks up @@ -187,13 +194,13 @@ int blk_get_device_by_str(const char *ifname, const char *dev_str, * If the partition string is empty then the first partition is used. If the * partition string is "auto" then the first bootable partition is used. * - * @ifname: Interface name (e.g. "ide", "scsi") + * @ifname: Interface name (e.g. "ide", "scsi") * @dev_part_str: Device and partition string - * @dev_desc: Returns a pointer to the block device on success - * @info: Returns partition information + * @dev_desc: Returns a pointer to the block device on success + * @info: Returns partition information * @allow_whole_dev: true to allow the user to select partition 0 - * (which means the whole device), false to require a valid - * partition number >= 1 + * (which means the whole device), false to require a valid + * partition number >= 1 * Return: partition number, or -1 on error * */ @@ -205,18 +212,20 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, * part_get_info_by_name() - Search for a partition by name * among all available registered partitions * - * @param dev_desc - block device descriptor - * @param gpt_name - the specified table entry name - * @param info - returns the disk partition info + * @dev_desc: block device descriptor + * @name: the specified table entry name + * @info: returns the disk partition info * - * Return: - the partition number on match (starting on 1), -1 on no match, + * Return: the partition number on match (starting on 1), -1 on no match, * otherwise error */ int part_get_info_by_name(struct blk_desc *dev_desc, const char *name, struct disk_partition *info); /** - * Get partition info from dev number + part name, or dev number + part number. + * part_get_info_by_dev_and_name_or_num() - Get partition info from dev number + * and part name, or dev number and + * part number. * * Parse a device number and partition description (either name or number) * in the form of device number plus partition name separated by a "#" @@ -225,14 +234,14 @@ int part_get_info_by_name(struct blk_desc *dev_desc, * partition descriptions for a given interface. If the partition is found, sets * dev_desc and part_info accordingly with the information of the partition. * - * @param[in] dev_iface Device interface - * @param[in] dev_part_str Input partition description, like "0#misc" or "0:1" - * @param[out] dev_desc Place to store the device description pointer - * @param[out] part_info Place to store the partition information - * @param[in] allow_whole_dev true to allow the user to select partition 0 - * (which means the whole device), false to require a valid - * partition number >= 1 - * Return: the partition number on success, or negative errno on error + * @dev_iface: Device interface + * @dev_part_str: Input partition description, like "0#misc" or "0:1" + * @dev_desc: Place to store the device description pointer + * @part_info: Place to store the partition information + * @allow_whole_dev: true to allow the user to select partition 0 + * (which means the whole device), false to require a valid + * partition number >= 1 + * Return: the partition number on success, or negative errno on error */ int part_get_info_by_dev_and_name_or_num(const char *dev_iface, const char *dev_part_str, @@ -322,7 +331,7 @@ int part_create_block_devices(struct udevice *blk_dev); * @start: Start block number to read in the partition (0=first) * @blkcnt: Number of blocks to read * @buffer: Destination buffer for data read - * Returns: number of blocks read, or -ve error number (see the + * Return: number of blocks read, or -ve error number (see the * IS_ERR_VALUE() macro */ ulong disk_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, @@ -335,7 +344,7 @@ ulong disk_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, * @start: Start block number to write in the partition (0=first) * @blkcnt: Number of blocks to write * @buffer: Source buffer for data to write - * Returns: number of blocks written, or -ve error number (see the + * Return: number of blocks written, or -ve error number (see the * IS_ERR_VALUE() macro */ ulong disk_blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, @@ -347,7 +356,7 @@ ulong disk_blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, * @dev: Device to (partially) erase (UCLASS_PARTITION) * @start: Start block number to erase in the partition (0=first) * @blkcnt: Number of blocks to erase - * Returns: number of blocks erased, or -ve error number (see the + * Return: number of blocks erased, or -ve error number (see the * IS_ERR_VALUE() macro */ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); @@ -369,35 +378,40 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); #define part_get_info_ptr(x) x #endif - +/** + * struct part_driver - partition driver + */ struct part_driver { + /** @name: partition name */ const char *name; + /** @part_type: (MBR) partition type */ int part_type; - const int max_entries; /* maximum number of entries to search */ - + /** @max_entries: maximum number of partition table entries */ + const int max_entries; /** - * get_info() - Get information about a partition + * @get_info: Get information about a partition * - * @dev_desc: Block device descriptor - * @part: Partition number (1 = first) - * @info: Returns partition information + * @get_info.dev_desc: Block device descriptor + * @get_info.part: Partition number (1 = first) + * @get_info.info: Returns partition information */ int (*get_info)(struct blk_desc *dev_desc, int part, struct disk_partition *info); /** - * print() - Print partition information + * @print: Print partition information * - * @dev_desc: Block device descriptor + * @print.dev_desc: Block device descriptor */ void (*print)(struct blk_desc *dev_desc); /** - * test() - Test if a device contains this partition type + * @test: Test if a device contains this partition type * - * @dev_desc: Block device descriptor - * @return 0 if the block device appears to contain this partition - * type, -ve if not + * @test.dev_desc: Block device descriptor + * @test.Return: + * 0 if the block device appears to contain this partition type, + * -ve if not */ int (*test)(struct blk_desc *dev_desc); }; @@ -413,52 +427,52 @@ struct part_driver { /** * write_gpt_table() - Write the GUID Partition Table to disk * - * @param dev_desc - block device descriptor - * @param gpt_h - pointer to GPT header representation - * @param gpt_e - pointer to GPT partition table entries + * @dev_desc: block device descriptor + * @gpt_h: pointer to GPT header representation + * @gpt_e: pointer to GPT partition table entries * - * Return: - zero on success, otherwise error + * Return: zero on success, otherwise error */ int write_gpt_table(struct blk_desc *dev_desc, gpt_header *gpt_h, gpt_entry *gpt_e); /** - * gpt_fill_pte(): Fill the GPT partition table entry + * gpt_fill_pte() - Fill the GPT partition table entry * - * @param dev_desc - block device descriptor - * @param gpt_h - GPT header representation - * @param gpt_e - GPT partition table entries - * @param partitions - list of partitions - * @param parts - number of partitions + * @dev_desc: block device descriptor + * @gpt_h: GPT header representation + * @gpt_e: GPT partition table entries + * @partitions: list of partitions + * @parts: number of partitions * - * Return: zero on success + * Return: zero on success */ int gpt_fill_pte(struct blk_desc *dev_desc, gpt_header *gpt_h, gpt_entry *gpt_e, struct disk_partition *partitions, int parts); /** - * gpt_fill_header(): Fill the GPT header + * gpt_fill_header() - Fill the GPT header * - * @param dev_desc - block device descriptor - * @param gpt_h - GPT header representation - * @param str_guid - disk guid string representation - * @param parts_count - number of partitions + * @dev_desc: block device descriptor + * @gpt_h: GPT header representation + * @str_guid: disk guid string representation + * @parts_count: number of partitions * - * Return: - error on str_guid conversion error + * Return: error on str_guid conversion error */ int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h, char *str_guid, int parts_count); /** - * gpt_restore(): Restore GPT partition table + * gpt_restore() - Restore GPT partition table * - * @param dev_desc - block device descriptor - * @param str_disk_guid - disk GUID - * @param partitions - list of partitions - * @param parts - number of partitions + * @dev_desc: block device descriptor + * @str_disk_guid: disk GUID + * @partitions: list of partitions + * @parts_count: number of partitions * - * Return: zero on success + * Return: 0 on success */ int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid, struct disk_partition *partitions, const int parts_count); @@ -466,34 +480,34 @@ int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid, /** * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid * - * @param dev_desc - block device descriptor - * @param buf - buffer which contains the MBR and Primary GPT info + * @dev_desc: block device descriptor + * @buf: buffer which contains the MBR and Primary GPT info * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf); /** * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT * - * @param dev_desc - block device descriptor - * @param buf - buffer which contains the MBR and Primary GPT info + * @dev_desc: block device descriptor + * @buf: buffer which contains the MBR and Primary GPT info * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf); /** - * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header + * gpt_verify_headers() - Read and check CRC32 of the GPT's header * and partition table entries (PTE) * * As a side effect if sets gpt_head and gpt_pte so they point to GPT data. * - * @param dev_desc - block device descriptor - * @param gpt_head - pointer to GPT header data read from medium - * @param gpt_pte - pointer to GPT partition table enties read from medium + * @dev_desc: block device descriptor + * @gpt_head: pointer to GPT header data read from medium + * @gpt_pte: pointer to GPT partition table enties read from medium * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head, gpt_entry **gpt_pte); @@ -502,9 +516,9 @@ int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head, * gpt_repair_headers() - Function to repair the GPT's header * and partition table entries (PTE) * - * @param dev_desc - block device descriptor + * @dev_desc: block device descriptor * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int gpt_repair_headers(struct blk_desc *dev_desc); @@ -516,13 +530,13 @@ int gpt_repair_headers(struct blk_desc *dev_desc); * provided in '$partitions' environment variable. Specificially, name, start * and size of the partition is checked. * - * @param dev_desc - block device descriptor - * @param partitions - partition data read from '$partitions' env variable - * @param parts - number of partitions read from '$partitions' env variable - * @param gpt_head - pointer to GPT header data read from medium - * @param gpt_pte - pointer to GPT partition table enties read from medium + * @dev_desc: block device descriptor + * @partitions: partition data read from '$partitions' env variable + * @parts: number of partitions read from '$partitions' env variable + * @gpt_head: pointer to GPT header data read from medium + * @gpt_pte: pointer to GPT partition table enties read from medium * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int gpt_verify_partitions(struct blk_desc *dev_desc, struct disk_partition *partitions, int parts, @@ -530,15 +544,15 @@ int gpt_verify_partitions(struct blk_desc *dev_desc, /** - * get_disk_guid() - Function to read the GUID string from a device's GPT + * get_disk_guid() - Read the GUID string from a device's GPT * * This function reads the GUID string from a block device whose descriptor * is provided. * - * @param dev_desc - block device descriptor - * @param guid - pre-allocated string in which to return the GUID + * @dev_desc: block device descriptor + * @guid: pre-allocated string in which to return the GUID * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int get_disk_guid(struct blk_desc *dev_desc, char *guid); @@ -548,19 +562,19 @@ int get_disk_guid(struct blk_desc *dev_desc, char *guid); /** * is_valid_dos_buf() - Ensure that a DOS MBR image is valid * - * @param buf - buffer which contains the MBR + * @buf: buffer which contains the MBR * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int is_valid_dos_buf(void *buf); /** * write_mbr_sector() - write DOS MBR * - * @param dev_desc - block device descriptor - * @param buf - buffer which contains the MBR + * @dev_desc: block device descriptor + * @buf: buffer which contains the MBR * - * Return: - '0' on success, otherwise error + * Return: 0 on success, otherwise error */ int write_mbr_sector(struct blk_desc *dev_desc, void *buf); @@ -575,7 +589,7 @@ int layout_mbr_partitions(struct disk_partition *p, int count, /** * part_driver_get_count() - get partition driver count * - * Return: - number of partition drivers + * Return: number of partition drivers */ static inline int part_driver_get_count(void) { @@ -585,7 +599,7 @@ static inline int part_driver_get_count(void) /** * part_driver_get_first() - get first partition driver * - * Return: - pointer to first partition driver on success, otherwise NULL + * Return: pointer to first partition driver on success, otherwise NULL */ static inline struct part_driver *part_driver_get_first(void) { @@ -595,9 +609,9 @@ static inline struct part_driver *part_driver_get_first(void) /** * part_get_type_by_name() - Get partition type by name * - * @name: Name of partition type to look up (not case-sensitive) - * Returns: Corresponding partition type (PART_TYPE_...) or PART_TYPE_UNKNOWN if - * not known + * @name: Name of partition type to look up (not case-sensitive) + * Return: + * Corresponding partition type (PART\_TYPE\_...) or PART\_TYPE\_UNKNOWN */ int part_get_type_by_name(const char *name); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index ebf4a2d5fa3..f752703b438 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -877,7 +877,7 @@ efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end, */ __weak void efi_add_known_memory(void) { - u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK; + u64 ram_top = gd->ram_top & ~EFI_PAGE_MASK; int i; /* diff --git a/tools/logos/st.bmp b/tools/logos/st.bmp Binary files differnew file mode 100644 index 00000000000..f59d3c5cef6 --- /dev/null +++ b/tools/logos/st.bmp |
