diff options
277 files changed, 11861 insertions, 8296 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 76ffdeebd66..3c1846a5bc3 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -89,7 +89,7 @@ stages: virtualenv -p /usr/bin/python3 /tmp/venvhtml . /tmp/venvhtml/bin/activate pip install -r doc/sphinx/requirements.txt - make htmldocs + make htmldocs KDOC_WERROR=1 make infodocs - job: todo diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b193fee98f8..e6c6ab3586e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -171,7 +171,7 @@ docs: - virtualenv -p /usr/bin/python3 /tmp/venvhtml - . /tmp/venvhtml/bin/activate - pip install -r doc/sphinx/requirements.txt - - make htmldocs + - make htmldocs KDOC_WERROR=1 - make infodocs # some statistics about the code base diff --git a/MAINTAINERS b/MAINTAINERS index f752132a1fc..c8f72e9ec6a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -291,6 +291,7 @@ S: Maintained F: arch/arm/cpu/armv8/hisilicon F: arch/arm/include/asm/arch-hi6220/ F: arch/arm/include/asm/arch-hi3660/ +F: arch/arm/mach-histb ARM HPE GXP ARCHITECTURE M: Jean-Marie Verdun <verdun@hpe.com> @@ -987,10 +988,12 @@ F: cmd/fastboot.c F: doc/android/fastboot*.rst F: include/fastboot.h F: include/fastboot-internal.h -F: include/net/fastboot.h +F: include/net/fastboot_tcp.h +F: include/net/fastboot_udp.h F: drivers/fastboot/ F: drivers/usb/gadget/f_fastboot.c -F: net/fastboot.c +F: net/fastboot_tcp.c +F: net/fastboot_udp.c F: test/dm/fastboot.c FPGA @@ -1493,18 +1496,16 @@ F: configs/k2g_hs_evm_defconfig F: configs/k2l_hs_evm_defconfig F: configs/am65x_hs_evm_r5_defconfig F: configs/am65x_hs_evm_a53_defconfig -F: configs/j7200_hs_evm_a72_defconfig -F: configs/j7200_hs_evm_r5_defconfig F: configs/j721e_hs_evm_a72_defconfig F: configs/j721e_hs_evm_r5_defconfig -F: configs/j721s2_hs_evm_a72_defconfig -F: configs/j721s2_hs_evm_r5_defconfig TPM DRIVERS M: Ilias Apalodimas <ilias.apalodimas@linaro.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-tpm.git +F: cmd/tpm* F: drivers/tpm/ +F: include/tpm* TQ GROUP #M: Martin Krause <martin.krause@tq-systems.de> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b84c494989a..99264a64780 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -357,7 +357,7 @@ config SYS_ARM_ARCH choice prompt "Select the ARM data write cache policy" - default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1 + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1 default SYS_ARM_CACHE_WRITEBACK config SYS_ARM_CACHE_WRITEBACK @@ -578,6 +578,16 @@ config ARCH_DAVINCI help Support for TI's DaVinci platform. +config ARCH_HISTB + bool "Hisilicon HiSTB SoCs" + select DM + select DM_SERIAL + select OF_CONTROL + select PL01X_SERIAL + imply CMD_DM + help + Support for HiSTB SoCs. + config ARCH_KIRKWOOD bool "Marvell Kirkwood" select ARCH_MISC_INIT @@ -671,6 +681,25 @@ config TARGET_BCMCYGNUS imply HASH_VERIFY imply NETDEVICES +config TARGET_BCMNS + bool "Support Broadcom Northstar" + select CPU_V7A + select DM + select DM_GPIO + select DM_SERIAL + select OF_CONTROL + select TIMER + select SYS_NS16550 + select ARM_GLOBAL_TIMER + imply SYS_THUMB_BUILD + imply MTD_RAW_NAND + imply NAND_BRCMNAND + imply NAND_BRCMNAND_IPROC + help + Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit + ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094, + BCM5301x etc. + config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 @@ -2155,6 +2184,8 @@ source "arch/arm/mach-hpe/gxp/Kconfig" source "arch/arm/mach-highbank/Kconfig" +source "arch/arm/mach-histb/Kconfig" + source "arch/arm/mach-integrator/Kconfig" source "arch/arm/mach-ipq40xx/Kconfig" @@ -2266,6 +2297,7 @@ source "board/Marvell/octeontx2/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" +source "board/broadcom/bcmns/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/eets/pdu001/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac602aed9c9..5ebe0619d39 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -61,6 +61,7 @@ machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_GXP) += hpe machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_HISTB) += histb machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4f91db49eeb..22ce6992165 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -387,6 +387,10 @@ void fdt_fixup_remove_jr(void *blob) u64 jr_offset, used_jr; fdt32_t *reg; + /* Return if crypto node not found */ + if (crypto_node < 0) + return; + used_jr = sec_firmware_used_jobring_offset(); fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3385948d22c..935b2f1517f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -961,6 +961,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ imx8qm-cgtqmx8.dtb \ + imx8qm-dmsse20-a1.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ @@ -1142,9 +1143,6 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \ omap4-sdp.dtb \ omap4-sdp-es23plus.dtb -dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \ - omap5-uevm.dtb - dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ at91-sama7g5ek.dtb @@ -1200,6 +1198,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2837-rpi-cm3-io3.dtb \ bcm2711-rpi-4-b.dtb +dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb + dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb @@ -1308,6 +1308,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7981-rfb.dtb \ mt7981-emmc-rfb.dtb \ mt7981-sd-rfb.dtb \ + mt7986a-bpi-r3-sd.dtb \ + mt7986a-bpi-r3-emmc.dtb \ mt7986a-rfb.dtb \ mt7986b-rfb.dtb \ mt7986a-sd-rfb.dtb \ diff --git a/arch/arm/dts/bcm5301x.dtsi b/arch/arm/dts/bcm5301x.dtsi new file mode 100644 index 00000000000..5fc1b847f4a --- /dev/null +++ b/arch/arm/dts/bcm5301x.dtsi @@ -0,0 +1,581 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include <dt-bindings/clock/bcm-nsp.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + chipcommon-a-bus@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550"; + reg = <0x0300 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550"; + reg = <0x0400 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1>; + status = "disabled"; + }; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + scu@20000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x20000 0x100>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; + clocks = <&periph_clk>; + }; + + timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>; + clocks = <&periph_clk>; + }; + + watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; + cache-level = <2>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; + }; + + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + ehci: usb@21000 { + #usb-cells = <0>; + + compatible = "generic-ehci"; + reg = <0x00021000 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@22000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + }; + + usb3: usb3@23000 { + reg = <0x00023000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + xhci: usb@23000 { + #usb-cells = <0>; + + compatible = "generic-xhci"; + reg = <0x00023000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy>; + phy-names = "usb"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; + }; + + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; + + gmac1: ethernet@25000 { + reg = <0x25000 0x800>; + }; + + gmac2: ethernet@26000 { + reg = <0x26000 0x800>; + }; + + gmac3: ethernet@27000 { + reg = <0x27000 0x800>; + }; + }; + + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; + }; + + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: clock-controller@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + + pinctrl: pinctrl@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + groups = "spi_grp"; + function = "spi"; + }; + + pinmux_i2c: i2c-pins { + groups = "i2c_grp"; + function = "i2c"; + }; + + pinmux_pwm: pwm-pins { + groups = "pwm0_grp", "pwm1_grp", + "pwm2_grp", "pwm3_grp"; + function = "pwm"; + }; + + pinmux_uart1: uart1-pins { + groups = "uart1_grp"; + function = "uart1"; + }; + }; + + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + }; + }; + + srab: ethernet-switch@18007000 { + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; + + nand_controller: nand-controller@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + spi@18029200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18029200 0x184>, + <0x18029000 0x124>, + <0x1811b408 0x004>, + <0x180293a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "disabled"; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts index 1722dce33ff..b4f057ac653 100644 --- a/arch/arm/dts/dragonboard845c.dts +++ b/arch/arm/dts/dragonboard845c.dts @@ -21,7 +21,7 @@ }; aliases { - serial0 = &debug_uart; + serial0 = &uart9; }; memory { diff --git a/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi new file mode 100644 index 00000000000..298adb849b3 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi new file mode 100644 index 00000000000..298adb849b3 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi new file mode 100644 index 00000000000..89566bf8493 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + }; +}; + +&i2c0 { + uc: board-controller@7e { + compatible = "traverse,ten64-controller"; + reg = <0x7e>; + }; +}; + diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts index 55a7d41fb01..0d11440d88d 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ b/arch/arm/dts/fsl-ls1088a-ten64.dts @@ -1,9 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree file for Travese Ten64 (LS1088) board + * Device Tree file for Traverse Technologies Ten64 + * (LS1088A) board * Based on fsl-ls1088a-rdb.dts * Copyright 2017-2020 NXP - * Copyright 2019-2021 Traverse Technologies + * Copyright 2019-2023 Traverse Technologies * * Author: Mathew McBride <matt@traverse.com.au> */ @@ -22,7 +23,6 @@ aliases { serial0 = &duart0; serial1 = &duart1; - spi0 = &qspi; }; chosen { @@ -36,18 +36,16 @@ * external power off (e.g ATX Power Button) * asserted */ - powerdn { + button-powerdn { label = "External Power Down"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>; linux,code = <KEY_POWER>; }; /* Rear Panel 'ADMIN' button (GPIO_H) */ - admin { + button-admin { label = "ADMIN button"; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>; linux,code = <KEY_WPS_BUTTON>; }; }; @@ -55,17 +53,17 @@ leds { compatible = "gpio-leds"; - sfp1down { + led-0 { label = "ten64:green:sfp1:down"; gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; }; - sfp2up { + led-1 { label = "ten64:green:sfp2:up"; gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; }; - admin { + led-2 { label = "ten64:admin"; gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; }; @@ -95,17 +93,17 @@ /* XG1 - Upper SFP */ &dpmac1 { sfp = <&sfp_xg1>; + pcs-handle = <&pcs1>; phy-connection-type = "10gbase-r"; managed = "in-band-status"; - status = "okay"; }; /* XG0 - Lower SFP */ &dpmac2 { sfp = <&sfp_xg0>; + pcs-handle = <&pcs2>; phy-connection-type = "10gbase-r"; managed = "in-band-status"; - status = "okay"; }; /* DPMAC3..6 is GE4 to GE8 */ @@ -113,28 +111,28 @@ phy-handle = <&mdio1_phy5>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_0>; }; &dpmac4 { phy-handle = <&mdio1_phy6>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_1>; }; &dpmac5 { phy-handle = <&mdio1_phy7>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_2>; }; &dpmac6 { phy-handle = <&mdio1_phy8>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_3>; }; /* DPMAC7..10 is GE0 to GE3 */ @@ -142,28 +140,28 @@ phy-handle = <&mdio1_phy1>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_0>; }; &dpmac8 { phy-handle = <&mdio1_phy2>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_1>; }; &dpmac9 { phy-handle = <&mdio1_phy3>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_2>; }; &dpmac10 { phy-handle = <&mdio1_phy4>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_3>; }; &duart0 { @@ -234,11 +232,6 @@ compatible = "atmel,at97sc3204t"; reg = <0x29>; }; - - uc: board-controller@7e { - compatible = "traverse,ten64-controller"; - reg = <0x7e>; - }; }; &i2c2 { @@ -253,7 +246,7 @@ &i2c3 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9540"; #address-cells = <1>; #size-cells = <0>; @@ -273,6 +266,22 @@ }; }; +&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi new file mode 100644 index 00000000000..efcfdd96aef --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +/{ + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; +}; + +&duart0 { + bootph-all; +}; + +&duart1 { + bootph-all; +}; + +/* MDIO controllers - U-Boot uses a different + * driver for the DPAA2 (LS/LX2) family, + * so must match fsl,ls-mdio first. + */ +&emdio1 { + compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; +}; + +&emdio2 { + compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; +}; + +/* DPAA2 Management Complex (MC) + * "simple-mfd" compatible used by U-Boot only, + * to allow driver model functionality. + */ +&fsl_mc { + compatible = "fsl,qoriq-mc", "simple-mfd"; + + dpmacs { + compatible = "simple-mfd"; + }; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie3 { + status = "okay"; +}; + +&usb0 { + compatible = "fsl,layerscape-dwc3", "snps,dwc3"; +}; + +&usb1 { + compatible = "fsl,layerscape-dwc3", "snps,dwc3"; +}; + diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 4782b83515a..e5fb137ac02 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -1,39 +1,202 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * NXP ls1088a SOC common device tree source + * Device Tree Include file for NXP Layerscape-1088A family SoC. + * + * Copyright 2017-2020 NXP + * + * Harninder Rai <harninder.rai@nxp.com> * - * Copyright 2017, 2020-2021, 2023 NXP */ - #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> + / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ + aliases { + crypto = &crypto; + rtc1 = &ftm_alarm0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* We have 2 clusters having 4 Cortex-A53 cores each */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x0>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; }; gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ #interrupt-cells = <3>; interrupt-controller; - interrupts = <1 9 0x4>; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + thermal-zones { + core-cluster { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ - <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ - <1 11 0x8>, /* Virtual PPI, active-low */ - <1 10 0x8>; /* Hypervisor PPI, active-low */ + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; }; sysclk: sysclk { @@ -43,6 +206,13 @@ clock-output-names = "sysclk"; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -57,6 +227,121 @@ clocks = <&sysclk>; }; + dcfg: dcfg@1e00000 { + compatible = "fsl,ls1088a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + + isc: syscon@1f70000 { + compatible = "fsl,ls1088a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xf 0x0>; + }; + }; + + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000030 + 0x00000003 0x00000037 + 0x00000004 0x0000003d + 0x00000005 0x00000044 + 0x00000006 0x0000004a + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005e + 0x0000000a 0x00000064 + 0x0000000b 0x0000006b + /* Calibration data group 2 */ + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a + /* Calibration data group 3 */ + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x00000040 + 0x00020004 0x0000004a + 0x00020005 0x00000054 + 0x00020006 0x0000005e + /* Calibration data group 4 */ + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000027 + 0x00030003 0x00000032 + 0x00030004 0x0000003e + 0x00030005 0x00000049 + 0x00030006 0x00000054 + 0x00030007 0x00000060>; + little-endian; + #thermal-sensor-cells = <1>; + }; + + dspi: spi@2100000 { + compatible = "fsl,ls1088a-dspi", + "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + spi-num-chipselects = <6>; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; @@ -64,7 +349,6 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - bootph-all; }; duart1: serial@21c0600 { @@ -74,328 +358,694 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - bootph-all; }; - }; - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 4>; - }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 4>; - }; + gpio1: gpio@2310000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 4>; - }; + gpio2: gpio@2320000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 4>; - }; + gpio3: gpio@2330000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - dspi: dspi@2100000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; /* Level high type */ - spi-num-chipselects = <6>; - }; + ifc: memory-controller@2240000 { + compatible = "fsl,ifc"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; - qspi: quadspi@1550000 { - compatible = "fsl,ls1088a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - status = "disabled"; - }; + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - esdhc: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - little-endian; - bus-width = <4>; - }; + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - gpio0: gpio@2300000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - gpio1: gpio@2310000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - gpio2: gpio@2320000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + qspi: spi@20c0000 { + compatible = "fsl,ls2080a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + status = "disabled"; + }; - gpio3: gpio@2330000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + esdhc: esdhc@2140000 { + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + status = "disabled"; + }; - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 0x4>; /* Level high type */ - }; + usb0: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; - usb0: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - }; + usb1: usb@3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; - usb1: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - }; + sata: sata@3200000 { + compatible = "fsl,ls1088a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x7 0x100520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + dma-coherent; + status = "disabled"; + }; - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - dma-coherent; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; }; - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + pcie1: pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <256>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; }; - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x20 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <24>; + num-ob-windows = <256>; + max-functions = /bits/ 8 <2>; + status = "disabled"; }; - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + pcie2: pcie@3500000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; }; - }; - pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ - 0x00 0x03480000 0x0 0x80000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x20 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x28 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; - pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ - 0x00 0x03580000 0x0 0x80000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x28 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + pcie3: pcie@3600000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; - pcie3: pcie@3600000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ - 0x00 0x03680000 0x0 0x80000 /* lut registers */ - 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ - 0x30 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x30 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; - sata: sata@3200000 { - compatible = "fsl,ls1088a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "ahci", "sata-ecc"; - interrupts = <0 133 4>; - status = "disabled"; - }; + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + stream-match-mask = <0x7C00>; + dma-coherent; + #global-interrupts = <12>; + // global secure fault + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + // combined secure + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + // global non-secure fault + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + // combined non-secure + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + // performance counter interrupts 0-7 + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + // per context interrupt, 64 interrupts + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + }; - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; + console@8340020 { + compatible = "fsl,dpaa2-console"; + reg = <0x00000000 0x08340020 0 0x2>; + }; + + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + little-endian; + fsl,extts-fifo; + }; + + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <2500000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + status = "disabled"; + }; - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc", "simple-mfd"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - compatible = "simple-mfd"; + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; #address-cells = <1>; #size-cells = <0>; + clock-frequency = <2500000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + status = "disabled"; + }; - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - status = "disabled"; + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - status = "disabled"; + pcs2: ethernet-phy@0 { + reg = <0>; }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - status = "disabled"; + pcs3_0: ethernet-phy@0 { + reg = <0>; }; - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - status = "disabled"; + pcs3_1: ethernet-phy@1 { + reg = <1>; }; - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - status = "disabled"; + pcs3_2: ethernet-phy@2 { + reg = <2>; }; - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - status = "disabled"; + pcs3_3: ethernet-phy@3 { + reg = <3>; }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - status = "disabled"; + pcs7_0: ethernet-phy@0 { + reg = <0>; }; - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - status = "disabled"; + pcs7_1: ethernet-phy@1 { + reg = <1>; }; - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - status = "disabled"; + pcs7_2: ethernet-phy@2 { + reg = <2>; }; - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - status = "disabled"; + pcs7_3: ethernet-phy@3 { + reg = <3>; }; }; - }; - emdio1: mdio@8B96000 { - compatible = "fsl,ls-mdio"; - reg = <0x0 0x8B96000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core2_watchdog: wdt@c020000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc020000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core3_watchdog: wdt@c030000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc030000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt@c100000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt@c110000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core2_watchdog: wdt@c120000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc120000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core3_watchdog: wdt@c130000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc130000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ + dma-coherent; + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: ethernet@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <1>; + }; + + dpmac2: ethernet@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <2>; + }; + + dpmac3: ethernet@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <3>; + }; + + dpmac4: ethernet@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <4>; + }; + + dpmac5: ethernet@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <5>; + }; + + dpmac6: ethernet@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <6>; + }; + + dpmac7: ethernet@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <7>; + }; + + dpmac8: ethernet@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <8>; + }; + + dpmac9: ethernet@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <9>; + }; + + dpmac10: ethernet@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + }; + }; + }; + + rcpm: power-controller@1e34040 { + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1088a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; }; - emdio2: mdio@8B97000 { - compatible = "fsl,ls-mdio"; - reg = <0x0 0x8B97000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; }; }; diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi new file mode 100644 index 00000000000..eb320761f2f --- /dev/null +++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "hi3798mv200-u-boot.dtsi" + +/* The clock driver is missing */ +&sd0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts new file mode 100644 index 00000000000..c4ca5ed2354 --- /dev/null +++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS File for Skyworth HC2910 with board label 2AGHD05 set-top box. + * + * Released under the GPLv2 only. + */ + +/dts-v1/; + +#include "hi3798mv200.dtsi" + +/ { + // Usually known as Henan Guangdian HC2910 + model = "Skyworth HC2910 with board label 2AGHD05"; + compatible = "skyworth,hc2910-2aghd05", "hisilicon,hi3798mv200"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&ehci { + status = "okay"; +}; + +&emmc { + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&gmac { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ð_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + + eth_phy1: phy@3 { + reg = <3>; + }; +}; + +&ohci { + status = "okay"; +}; + +&sd0 { + bus-width = <4>; + cap-sd-highspeed; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/hi3798mv200-u-boot.dtsi b/arch/arm/dts/hi3798mv200-u-boot.dtsi new file mode 100644 index 00000000000..8917bcf33d3 --- /dev/null +++ b/arch/arm/dts/hi3798mv200-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot addition to: + * 1) use platform data for the console + * + */ + +#include <dt-bindings/reset/ti-syscon.h> + +/* The driver in U-Boot does not support "snps,dw-mshc" compatible. */ +&sd0 { + compatible = "hisilicon,hi3798mv200-dw-mshc"; +}; + +&sd1 { + compatible = "hisilicon,hi3798mv200-dw-mshc"; +}; + +/* The clock driver is missing */ +&uart0 { + clock = <75000000>; +}; diff --git a/arch/arm/dts/hi3798mv200.dtsi b/arch/arm/dts/hi3798mv200.dtsi new file mode 100644 index 00000000000..fedf87ac679 --- /dev/null +++ b/arch/arm/dts/hi3798mv200.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS File for HiSilicon Hi3798mv200 SoC. + * + * Released under the GPLv2 only. + */ + +#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/ti-syscon.h> + +/ { + compatible = "hisilicon,hi3798mv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ + <0x0 0xf1002000 0x0 0x100>; /* GICC */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + /* Initialization is done in boot loader */ + usb2_phy1: hsusb1_phy { + compatible = "usb-nop-xceiv"; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + clock-names = "main"; + #phy-cells = <0>; + }; + + soc: soc@f0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xf0000000 0x10000000>; + + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + sysctrl: system-controller@8000000 { + compatible = "hisilicon,hi3798mv200-sysctrl", "syscon"; + reg = <0x8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798mv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798mv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = <PHY_TYPE_USB3>; + }; + }; + + pmx0: pinconf@8a21000 { + compatible = "pinconf-single"; + reg = <0x8a21000 0x180>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + }; + + uart0: serial@8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b00000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + sd0: mmc@9820000 { + compatible = "snps,dw-mshc"; + reg = <0x9820000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_SDIO0_CIU_CLK>, + <&crg HISTB_SDIO0_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x9c 4>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798mv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + resets = <&crg 0xa0 4>; + reset-names = "reset"; + status = "disabled"; + }; + + gmac: ethernet@9840000 { + compatible = "hisilicon,hi3798mv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9840000 0x1000>, + <0x984300c 0x4>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 0>, + <&crg 0xcc 2>, + <&crg 0xcc 5>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + ohci: ohci@9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "bus", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + status = "disabled"; + }; + + ehci: ehci@9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>, + <&crg HISTB_USB2_UTMI_CLK>; + clock-names = "bus", "phy", "utmi"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>, + <&crg 0xb8 13>; + reset-names = "bus", "phy", "utmi"; + phys = <&usb2_phy1>; + phy-names = "usb"; + status = "disabled"; + }; + + sd1: mmc@9c40000 { + compatible = "snps,dw-mshc"; + reg = <0x9c40000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_SDIO1_CIU_CLK>, + <&crg HISTB_SDIO1_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x28c 4>; + reset-names = "reset"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi new file mode 100644 index 00000000000..46a4dfe4e8a --- /dev/null +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "imx8mq-u-boot.dtsi" + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&uart1 { /* console */ + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts new file mode 100644 index 00000000000..cff150de07c --- /dev/null +++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2017-2018 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" + +/ { + model = "Advantech iMX8QM DMSSE20"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_rtc_mc_8803: rtc-mc-8803-grp{ + fsl,pins = < + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c + SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020 + SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-names = "default","state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec1 { + fsl,ar8031-phy-fixup; + fsl,magic-packet; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&fec2 { + fsl,ar8031-phy-fixup; + fsl,magic-packet; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_mc_8803>; + status = "okay"; + + rv8803@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + 24c02@50 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,24c04"; + reg = <0x50>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi index e7e0ca41597..e73458ca690 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi @@ -49,5 +49,3 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; }; - -#include "k3-am65-iot2050-common-pg2-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi index 0d215b4d668..4a9bf7d7c07 100644 --- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi @@ -11,9 +11,6 @@ #include "k3-am65-iot2050-common.dtsi" -#include "k3-am65-iot2050-common-u-boot.dtsi" -#include "k3-am65-iot2050-boot-image.dtsi" - / { memory@80000000 { device_type = "memory"; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi new file mode 100644 index 00000000000..1e393042ac0 --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +#include "k3-am65-iot2050-common-u-boot.dtsi" +#include "k3-am65-iot2050-common-pg2-u-boot.dtsi" +#include "k3-am65-iot2050-boot-image.dtsi" diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi new file mode 100644 index 00000000000..64afe25e38f --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +#include "k3-am65-iot2050-common-u-boot.dtsi" +#include "k3-am65-iot2050-boot-image.dtsi" diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi index 816a4cb4a68..d25e8b26187 100644 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi @@ -13,9 +13,6 @@ #include "k3-am65-iot2050-common.dtsi" -#include "k3-am65-iot2050-common-u-boot.dtsi" -#include "k3-am65-iot2050-boot-image.dtsi" - / { memory@80000000 { device_type = "memory"; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi new file mode 120000 index 00000000000..859776d3ffe --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi new file mode 120000 index 00000000000..859776d3ffe --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi new file mode 120000 index 00000000000..ac30e4ef46e --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi index 42ac8c5c89c..9ec8dff44be 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0 - * This file was generated on 08/07/2020 - * Includes hand-edits - */ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0 + * This file was generated on 06/01/2021 +*/ #define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 666500000 #define DDRSS_PLL_FREQUENCY_2 666500000 @@ -17,10 +17,10 @@ #define DDRSS_CTL_04_DATA 0x00000000 #define DDRSS_CTL_05_DATA 0x00000000 #define DDRSS_CTL_06_DATA 0x00000000 -#define DDRSS_CTL_07_DATA 0x00002710 -#define DDRSS_CTL_08_DATA 0x000186A0 +#define DDRSS_CTL_07_DATA 0x00002AF8 +#define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 -#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_10_DATA 0x0000006E #define DDRSS_CTL_11_DATA 0x000411AB #define DDRSS_CTL_12_DATA 0x0028B0AB #define DDRSS_CTL_13_DATA 0x00000005 @@ -33,11 +33,11 @@ #define DDRSS_CTL_20_DATA 0x02011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 -#define DDRSS_CTL_23_DATA 0x0000000A -#define DDRSS_CTL_24_DATA 0x00000019 +#define DDRSS_CTL_23_DATA 0x0000000B +#define DDRSS_CTL_24_DATA 0x0000001C #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 -#define DDRSS_CTL_27_DATA 0x02020200 +#define DDRSS_CTL_27_DATA 0x03020200 #define DDRSS_CTL_28_DATA 0x00003636 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 @@ -54,7 +54,7 @@ #define DDRSS_CTL_41_DATA 0x113C0057 #define DDRSS_CTL_42_DATA 0x2000291B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x040006DB +#define DDRSS_CTL_44_DATA 0x0400078A #define DDRSS_CTL_45_DATA 0x130E0B04 #define DDRSS_CTL_46_DATA 0x0A00B6D0 #define DDRSS_CTL_47_DATA 0x130E0B0A @@ -62,7 +62,7 @@ #define DDRSS_CTL_49_DATA 0x0203040A #define DDRSS_CTL_50_DATA 0x1C040500 #define DDRSS_CTL_51_DATA 0x081D1C1D -#define DDRSS_CTL_52_DATA 0x14000D0A +#define DDRSS_CTL_52_DATA 0x14000E0A #define DDRSS_CTL_53_DATA 0x02010A0A #define DDRSS_CTL_54_DATA 0x01010002 #define DDRSS_CTL_55_DATA 0x04383808 @@ -70,15 +70,15 @@ #define DDRSS_CTL_57_DATA 0x00001F1F #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 -#define DDRSS_CTL_60_DATA 0x00000E08 -#define DDRSS_CTL_61_DATA 0x000000BB +#define DDRSS_CTL_60_DATA 0x00001008 +#define DDRSS_CTL_61_DATA 0x000000CE #define DDRSS_CTL_62_DATA 0x00000176 #define DDRSS_CTL_63_DATA 0x00001448 #define DDRSS_CTL_64_DATA 0x00000176 #define DDRSS_CTL_65_DATA 0x00001448 #define DDRSS_CTL_66_DATA 0x00000005 -#define DDRSS_CTL_67_DATA 0x00030000 -#define DDRSS_CTL_68_DATA 0x005D0010 +#define DDRSS_CTL_67_DATA 0x00040000 +#define DDRSS_CTL_68_DATA 0x005D0012 #define DDRSS_CTL_69_DATA 0x005D0282 #define DDRSS_CTL_70_DATA 0x00400282 #define DDRSS_CTL_71_DATA 0x00120103 @@ -89,7 +89,7 @@ #define DDRSS_CTL_76_DATA 0x03130A07 #define DDRSS_CTL_77_DATA 0x0A070301 #define DDRSS_CTL_78_DATA 0x00010313 -#define DDRSS_CTL_79_DATA 0x000F000F +#define DDRSS_CTL_79_DATA 0x00100010 #define DDRSS_CTL_80_DATA 0x01800180 #define DDRSS_CTL_81_DATA 0x01800180 #define DDRSS_CTL_82_DATA 0x03050505 @@ -112,13 +112,13 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00002EC0 -#define DDRSS_CTL_103_DATA 0x00002EC0 -#define DDRSS_CTL_104_DATA 0x00002EC0 -#define DDRSS_CTL_105_DATA 0x00002EC0 -#define DDRSS_CTL_106_DATA 0x00002EC0 +#define DDRSS_CTL_102_DATA 0x00003380 +#define DDRSS_CTL_103_DATA 0x00003380 +#define DDRSS_CTL_104_DATA 0x00003380 +#define DDRSS_CTL_105_DATA 0x00003380 +#define DDRSS_CTL_106_DATA 0x00003380 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x0000051D +#define DDRSS_CTL_108_DATA 0x000005A2 #define DDRSS_CTL_109_DATA 0x00051200 #define DDRSS_CTL_110_DATA 0x00051200 #define DDRSS_CTL_111_DATA 0x00051200 @@ -174,9 +174,9 @@ #define DDRSS_CTL_161_DATA 0x00000000 #define DDRSS_CTL_162_DATA 0x00000000 #define DDRSS_CTL_163_DATA 0x00000000 -#define DDRSS_CTL_164_DATA 0x000A0000 -#define DDRSS_CTL_165_DATA 0x000D0005 -#define DDRSS_CTL_166_DATA 0x000D0404 +#define DDRSS_CTL_164_DATA 0x000B0000 +#define DDRSS_CTL_165_DATA 0x000E0006 +#define DDRSS_CTL_166_DATA 0x000E0404 #define DDRSS_CTL_167_DATA 0x0086010B #define DDRSS_CTL_168_DATA 0x0A0A014E #define DDRSS_CTL_169_DATA 0x010B014E @@ -191,7 +191,7 @@ #define DDRSS_CTL_178_DATA 0x36000000 #define DDRSS_CTL_179_DATA 0x27270036 #define DDRSS_CTL_180_DATA 0x0F0F0000 -#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_181_DATA 0x15000000 #define DDRSS_CTL_182_DATA 0x00841515 #define DDRSS_CTL_183_DATA 0x24C424C4 #define DDRSS_CTL_184_DATA 0x2B2B2B00 @@ -199,7 +199,7 @@ #define DDRSS_CTL_186_DATA 0x00363600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F -#define DDRSS_CTL_189_DATA 0x15150000 +#define DDRSS_CTL_189_DATA 0x15151500 #define DDRSS_CTL_190_DATA 0x00000020 #define DDRSS_CTL_191_DATA 0x00000000 #define DDRSS_CTL_192_DATA 0x00000001 @@ -268,7 +268,7 @@ #define DDRSS_CTL_255_DATA 0x00000000 #define DDRSS_CTL_256_DATA 0x00000000 #define DDRSS_CTL_257_DATA 0x01000200 -#define DDRSS_CTL_258_DATA 0x00320040 +#define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 #define DDRSS_CTL_261_DATA 0x00280536 @@ -399,13 +399,13 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x2E2E1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x00000176 +#define DDRSS_CTL_389_DATA 0x0000019C #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x00000462 -#define DDRSS_CTL_395_DATA 0x00000E9C +#define DDRSS_CTL_394_DATA 0x000004D4 +#define DDRSS_CTL_395_DATA 0x00001018 #define DDRSS_CTL_396_DATA 0x00000204 #define DDRSS_CTL_397_DATA 0x00002890 #define DDRSS_CTL_398_DATA 0x00000200 @@ -432,7 +432,7 @@ #define DDRSS_CTL_419_DATA 0x00000000 #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 -#define DDRSS_CTL_422_DATA 0x0006001E +#define DDRSS_CTL_422_DATA 0x0007001F #define DDRSS_CTL_423_DATA 0x0013002B #define DDRSS_CTL_424_DATA 0x0013002B #define DDRSS_CTL_425_DATA 0x00000000 @@ -633,14 +633,14 @@ #define DDRSS_PI_160_DATA 0x00000000 #define DDRSS_PI_161_DATA 0x00010000 #define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x1B1B0100 +#define DDRSS_PI_163_DATA 0x1B1B0200 #define DDRSS_PI_164_DATA 0x00000034 #define DDRSS_PI_165_DATA 0x00000051 #define DDRSS_PI_166_DATA 0x00020051 #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x300C0C04 -#define DDRSS_PI_169_DATA 0x000E300C -#define DDRSS_PI_170_DATA 0x000000BB +#define DDRSS_PI_169_DATA 0x0010300C +#define DDRSS_PI_170_DATA 0x000000CE #define DDRSS_PI_171_DATA 0x00000176 #define DDRSS_PI_172_DATA 0x00001448 #define DDRSS_PI_173_DATA 0x00000176 @@ -658,14 +658,14 @@ #define DDRSS_PI_185_DATA 0x0E040100 #define DDRSS_PI_186_DATA 0x0808020E #define DDRSS_PI_187_DATA 0x00040402 -#define DDRSS_PI_188_DATA 0x000C8034 +#define DDRSS_PI_188_DATA 0x000D0035 #define DDRSS_PI_189_DATA 0x00198041 #define DDRSS_PI_190_DATA 0x00198041 #define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0002000D +#define DDRSS_PI_192_DATA 0x0002000E #define DDRSS_PI_193_DATA 0x0002014E #define DDRSS_PI_194_DATA 0x0100014E -#define DDRSS_PI_195_DATA 0x000E000E +#define DDRSS_PI_195_DATA 0x000F000F #define DDRSS_PI_196_DATA 0x014F0100 #define DDRSS_PI_197_DATA 0x0100014F #define DDRSS_PI_198_DATA 0x014F014F @@ -678,7 +678,7 @@ #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x001C000D +#define DDRSS_PI_208_DATA 0x001C000E #define DDRSS_PI_209_DATA 0x001C014E #define DDRSS_PI_210_DATA 0x0011014E #define DDRSS_PI_211_DATA 0x32000056 @@ -689,7 +689,7 @@ #define DDRSS_PI_216_DATA 0x3212005A #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x0400062B +#define DDRSS_PI_219_DATA 0x040006C9 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x1C1F0B0A #define DDRSS_PI_222_DATA 0x00001D12 @@ -699,43 +699,43 @@ #define DDRSS_PI_226_DATA 0x00001D12 #define DDRSS_PI_227_DATA 0x3C00A488 #define DDRSS_PI_228_DATA 0x13142005 -#define DDRSS_PI_229_DATA 0x0001760E -#define DDRSS_PI_230_DATA 0x00000E9C +#define DDRSS_PI_229_DATA 0x00019C0E +#define DDRSS_PI_230_DATA 0x00001018 #define DDRSS_PI_231_DATA 0x00002890 #define DDRSS_PI_232_DATA 0x000195A0 #define DDRSS_PI_233_DATA 0x00002890 #define DDRSS_PI_234_DATA 0x000195A0 -#define DDRSS_PI_235_DATA 0x0180000F +#define DDRSS_PI_235_DATA 0x01800010 #define DDRSS_PI_236_DATA 0x03030180 -#define DDRSS_PI_237_DATA 0x00271003 -#define DDRSS_PI_238_DATA 0x000186A0 +#define DDRSS_PI_237_DATA 0x002AF803 +#define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 -#define DDRSS_PI_240_DATA 0x00000064 -#define DDRSS_PI_241_DATA 0x0000000F +#define DDRSS_PI_240_DATA 0x0000006E +#define DDRSS_PI_241_DATA 0x00000010 #define DDRSS_PI_242_DATA 0x000411AB -#define DDRSS_PI_243_DATA 0x000186A0 +#define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 #define DDRSS_PI_245_DATA 0x00000A6B #define DDRSS_PI_246_DATA 0x00000180 #define DDRSS_PI_247_DATA 0x000411AB -#define DDRSS_PI_248_DATA 0x000186A0 +#define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 #define DDRSS_PI_250_DATA 0x00000A6B #define DDRSS_PI_251_DATA 0x01000180 -#define DDRSS_PI_252_DATA 0x00320040 +#define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 #define DDRSS_PI_254_DATA 0x05360040 #define DDRSS_PI_255_DATA 0x00010028 #define DDRSS_PI_256_DATA 0x05360040 #define DDRSS_PI_257_DATA 0x00000328 #define DDRSS_PI_258_DATA 0x00430043 -#define DDRSS_PI_259_DATA 0x00040404 +#define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 -#define DDRSS_PI_261_DATA 0x55003C5A +#define DDRSS_PI_261_DATA 0x55083C5A #define DDRSS_PI_262_DATA 0x5A000000 -#define DDRSS_PI_263_DATA 0x0055003C +#define DDRSS_PI_263_DATA 0x0055083C #define DDRSS_PI_264_DATA 0x3C5A0000 -#define DDRSS_PI_265_DATA 0x00005500 +#define DDRSS_PI_265_DATA 0x00005508 #define DDRSS_PI_266_DATA 0x0C3C5A00 #define DDRSS_PI_267_DATA 0x080F0E0D #define DDRSS_PI_268_DATA 0x000B0A09 @@ -879,7 +879,7 @@ #define DDRSS_PHY_105_DATA 0x0F0C2701 #define DDRSS_PHY_106_DATA 0x01000140 #define DDRSS_PHY_107_DATA 0x04000420 -#define DDRSS_PHY_108_DATA 0x00000255 +#define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 @@ -1135,7 +1135,7 @@ #define DDRSS_PHY_361_DATA 0x0F0C2701 #define DDRSS_PHY_362_DATA 0x01000140 #define DDRSS_PHY_363_DATA 0x04000420 -#define DDRSS_PHY_364_DATA 0x00000255 +#define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 @@ -1391,7 +1391,7 @@ #define DDRSS_PHY_617_DATA 0x0F0C2701 #define DDRSS_PHY_618_DATA 0x01000140 #define DDRSS_PHY_619_DATA 0x04000420 -#define DDRSS_PHY_620_DATA 0x00000255 +#define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 @@ -1647,7 +1647,7 @@ #define DDRSS_PHY_873_DATA 0x0F0C2701 #define DDRSS_PHY_874_DATA 0x01000140 #define DDRSS_PHY_875_DATA 0x04000420 -#define DDRSS_PHY_876_DATA 0x00000255 +#define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 @@ -2081,7 +2081,7 @@ #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00050000 +#define DDRSS_PHY_1310_DATA 0x00052000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index ca05e06e933..5a6f9b11b8e 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0 - * This file was generated on 09/25/2020 + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1 + * This file was generated on 07/17/2022 */ #define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,10 +17,10 @@ #define DDRSS_CTL_04_DATA 0x00000000 #define DDRSS_CTL_05_DATA 0x00000000 #define DDRSS_CTL_06_DATA 0x00000000 -#define DDRSS_CTL_07_DATA 0x00002710 -#define DDRSS_CTL_08_DATA 0x000186A0 +#define DDRSS_CTL_07_DATA 0x00002AF8 +#define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 -#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_10_DATA 0x0000006E #define DDRSS_CTL_11_DATA 0x000681C8 #define DDRSS_CTL_12_DATA 0x004111C9 #define DDRSS_CTL_13_DATA 0x00000005 @@ -32,11 +33,11 @@ #define DDRSS_CTL_20_DATA 0x02011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 -#define DDRSS_CTL_23_DATA 0x0000000A -#define DDRSS_CTL_24_DATA 0x00000019 +#define DDRSS_CTL_23_DATA 0x0000000B +#define DDRSS_CTL_24_DATA 0x0000001C #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 -#define DDRSS_CTL_27_DATA 0x02020200 +#define DDRSS_CTL_27_DATA 0x03020200 #define DDRSS_CTL_28_DATA 0x00005656 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 @@ -53,7 +54,7 @@ #define DDRSS_CTL_41_DATA 0x1B60008B #define DDRSS_CTL_42_DATA 0x2000422B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x040006DB +#define DDRSS_CTL_44_DATA 0x0400078A #define DDRSS_CTL_45_DATA 0x1E161104 #define DDRSS_CTL_46_DATA 0x10012458 #define DDRSS_CTL_47_DATA 0x1E161110 @@ -61,7 +62,7 @@ #define DDRSS_CTL_49_DATA 0x02030410 #define DDRSS_CTL_50_DATA 0x2C040500 #define DDRSS_CTL_51_DATA 0x082D2C2D -#define DDRSS_CTL_52_DATA 0x14000D0A +#define DDRSS_CTL_52_DATA 0x14000E0A #define DDRSS_CTL_53_DATA 0x04010A0A #define DDRSS_CTL_54_DATA 0x01010004 #define DDRSS_CTL_55_DATA 0x04585808 @@ -69,15 +70,15 @@ #define DDRSS_CTL_57_DATA 0x00003131 #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 -#define DDRSS_CTL_60_DATA 0x00000E08 -#define DDRSS_CTL_61_DATA 0x000000BB +#define DDRSS_CTL_60_DATA 0x00001008 +#define DDRSS_CTL_61_DATA 0x000000CE #define DDRSS_CTL_62_DATA 0x00000256 #define DDRSS_CTL_63_DATA 0x00002073 #define DDRSS_CTL_64_DATA 0x00000256 #define DDRSS_CTL_65_DATA 0x00002073 #define DDRSS_CTL_66_DATA 0x00000005 -#define DDRSS_CTL_67_DATA 0x00030000 -#define DDRSS_CTL_68_DATA 0x00950010 +#define DDRSS_CTL_67_DATA 0x00040000 +#define DDRSS_CTL_68_DATA 0x00950012 #define DDRSS_CTL_69_DATA 0x00950408 #define DDRSS_CTL_70_DATA 0x00400408 #define DDRSS_CTL_71_DATA 0x00120103 @@ -88,7 +89,7 @@ #define DDRSS_CTL_76_DATA 0x041E100B #define DDRSS_CTL_77_DATA 0x100B0401 #define DDRSS_CTL_78_DATA 0x0001041E -#define DDRSS_CTL_79_DATA 0x000F000F +#define DDRSS_CTL_79_DATA 0x00100010 #define DDRSS_CTL_80_DATA 0x02660266 #define DDRSS_CTL_81_DATA 0x02660266 #define DDRSS_CTL_82_DATA 0x03050505 @@ -111,13 +112,13 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00002EC0 -#define DDRSS_CTL_103_DATA 0x00002EC0 -#define DDRSS_CTL_104_DATA 0x00002EC0 -#define DDRSS_CTL_105_DATA 0x00002EC0 -#define DDRSS_CTL_106_DATA 0x00002EC0 +#define DDRSS_CTL_102_DATA 0x00003380 +#define DDRSS_CTL_103_DATA 0x00003380 +#define DDRSS_CTL_104_DATA 0x00003380 +#define DDRSS_CTL_105_DATA 0x00003380 +#define DDRSS_CTL_106_DATA 0x00003380 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x0000051D +#define DDRSS_CTL_108_DATA 0x000005A2 #define DDRSS_CTL_109_DATA 0x00081CC0 #define DDRSS_CTL_110_DATA 0x00081CC0 #define DDRSS_CTL_111_DATA 0x00081CC0 @@ -173,9 +174,9 @@ #define DDRSS_CTL_161_DATA 0x00000000 #define DDRSS_CTL_162_DATA 0x00000000 #define DDRSS_CTL_163_DATA 0x00000000 -#define DDRSS_CTL_164_DATA 0x000A0000 -#define DDRSS_CTL_165_DATA 0x000D0005 -#define DDRSS_CTL_166_DATA 0x000D0404 +#define DDRSS_CTL_164_DATA 0x000B0000 +#define DDRSS_CTL_165_DATA 0x000E0006 +#define DDRSS_CTL_166_DATA 0x000E0404 #define DDRSS_CTL_167_DATA 0x00D601AB #define DDRSS_CTL_168_DATA 0x10100216 #define DDRSS_CTL_169_DATA 0x01AB0216 @@ -190,15 +191,15 @@ #define DDRSS_CTL_178_DATA 0x56000000 #define DDRSS_CTL_179_DATA 0x27270056 #define DDRSS_CTL_180_DATA 0x0F0F0000 -#define DDRSS_CTL_181_DATA 0x00000000 -#define DDRSS_CTL_182_DATA 0x00840606 +#define DDRSS_CTL_181_DATA 0x16000000 +#define DDRSS_CTL_182_DATA 0x00841616 #define DDRSS_CTL_183_DATA 0x3FF43FF4 #define DDRSS_CTL_184_DATA 0x33333300 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00565600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F -#define DDRSS_CTL_189_DATA 0x06060000 +#define DDRSS_CTL_189_DATA 0x16161600 #define DDRSS_CTL_190_DATA 0x00000020 #define DDRSS_CTL_191_DATA 0x00000000 #define DDRSS_CTL_192_DATA 0x00000001 @@ -238,17 +239,17 @@ #define DDRSS_CTL_226_DATA 0x00000000 #define DDRSS_CTL_227_DATA 0x15110000 #define DDRSS_CTL_228_DATA 0x00040C18 -#define DDRSS_CTL_229_DATA 0x00000000 -#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0xF000C000 +#define DDRSS_CTL_230_DATA 0x0000F000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 -#define DDRSS_CTL_233_DATA 0x00000000 -#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0xC0000000 +#define DDRSS_CTL_234_DATA 0xF000F000 #define DDRSS_CTL_235_DATA 0x00000000 #define DDRSS_CTL_236_DATA 0x00000000 #define DDRSS_CTL_237_DATA 0x00000000 -#define DDRSS_CTL_238_DATA 0x00000000 -#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0xF000C000 +#define DDRSS_CTL_239_DATA 0x0000F000 #define DDRSS_CTL_240_DATA 0x00000000 #define DDRSS_CTL_241_DATA 0x00000000 #define DDRSS_CTL_242_DATA 0x00030000 @@ -267,7 +268,7 @@ #define DDRSS_CTL_255_DATA 0x00000000 #define DDRSS_CTL_256_DATA 0x00000000 #define DDRSS_CTL_257_DATA 0x01000200 -#define DDRSS_CTL_258_DATA 0x00320040 +#define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 #define DDRSS_CTL_261_DATA 0x00400855 @@ -276,7 +277,7 @@ #define DDRSS_CTL_264_DATA 0x00000040 #define DDRSS_CTL_265_DATA 0x006B0003 #define DDRSS_CTL_266_DATA 0x0100006B -#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_267_DATA 0x03030303 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 #define DDRSS_CTL_270_DATA 0x00000FFF @@ -398,13 +399,13 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x3A3A1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x00000176 +#define DDRSS_CTL_389_DATA 0x0000019C #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x00000462 -#define DDRSS_CTL_395_DATA 0x00000E9C +#define DDRSS_CTL_394_DATA 0x000004D4 +#define DDRSS_CTL_395_DATA 0x00001018 #define DDRSS_CTL_396_DATA 0x00000204 #define DDRSS_CTL_397_DATA 0x000040E6 #define DDRSS_CTL_398_DATA 0x00000200 @@ -431,7 +432,7 @@ #define DDRSS_CTL_419_DATA 0x00000000 #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 -#define DDRSS_CTL_422_DATA 0x0006001E +#define DDRSS_CTL_422_DATA 0x0007001F #define DDRSS_CTL_423_DATA 0x001B0033 #define DDRSS_CTL_424_DATA 0x001B0033 #define DDRSS_CTL_425_DATA 0x00000000 @@ -632,14 +633,14 @@ #define DDRSS_PI_160_DATA 0x00000000 #define DDRSS_PI_161_DATA 0x00010000 #define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x2B2B0100 +#define DDRSS_PI_163_DATA 0x2B2B0200 #define DDRSS_PI_164_DATA 0x00000034 #define DDRSS_PI_165_DATA 0x00000064 #define DDRSS_PI_166_DATA 0x00020064 #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x48120C04 -#define DDRSS_PI_169_DATA 0x000E4812 -#define DDRSS_PI_170_DATA 0x000000BB +#define DDRSS_PI_169_DATA 0x00104812 +#define DDRSS_PI_170_DATA 0x000000CE #define DDRSS_PI_171_DATA 0x00000256 #define DDRSS_PI_172_DATA 0x00002073 #define DDRSS_PI_173_DATA 0x00000256 @@ -657,14 +658,14 @@ #define DDRSS_PI_185_DATA 0x15040000 #define DDRSS_PI_186_DATA 0x0E0E0215 #define DDRSS_PI_187_DATA 0x00040402 -#define DDRSS_PI_188_DATA 0x000C8034 +#define DDRSS_PI_188_DATA 0x000D0035 #define DDRSS_PI_189_DATA 0x00218049 #define DDRSS_PI_190_DATA 0x00218049 #define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0004000D +#define DDRSS_PI_192_DATA 0x0004000E #define DDRSS_PI_193_DATA 0x00040216 #define DDRSS_PI_194_DATA 0x01000216 -#define DDRSS_PI_195_DATA 0x000E000E +#define DDRSS_PI_195_DATA 0x000F000F #define DDRSS_PI_196_DATA 0x02170100 #define DDRSS_PI_197_DATA 0x01000217 #define DDRSS_PI_198_DATA 0x02170217 @@ -677,7 +678,7 @@ #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x0024000D +#define DDRSS_PI_208_DATA 0x0024000E #define DDRSS_PI_209_DATA 0x00240216 #define DDRSS_PI_210_DATA 0x00110216 #define DDRSS_PI_211_DATA 0x32000056 @@ -688,7 +689,7 @@ #define DDRSS_PI_216_DATA 0x3212005B #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x0400062B +#define DDRSS_PI_219_DATA 0x040006C9 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x2C31110A #define DDRSS_PI_222_DATA 0x00002D1C @@ -698,43 +699,43 @@ #define DDRSS_PI_226_DATA 0x00002D1C #define DDRSS_PI_227_DATA 0x6001071C #define DDRSS_PI_228_DATA 0x1E202008 -#define DDRSS_PI_229_DATA 0x00017616 -#define DDRSS_PI_230_DATA 0x00000E9C +#define DDRSS_PI_229_DATA 0x00019C16 +#define DDRSS_PI_230_DATA 0x00001018 #define DDRSS_PI_231_DATA 0x000040E6 #define DDRSS_PI_232_DATA 0x000288FC #define DDRSS_PI_233_DATA 0x000040E6 #define DDRSS_PI_234_DATA 0x000288FC -#define DDRSS_PI_235_DATA 0x0266000F +#define DDRSS_PI_235_DATA 0x02660010 #define DDRSS_PI_236_DATA 0x03030266 -#define DDRSS_PI_237_DATA 0x00271003 -#define DDRSS_PI_238_DATA 0x000186A0 +#define DDRSS_PI_237_DATA 0x002AF803 +#define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 -#define DDRSS_PI_240_DATA 0x00000064 -#define DDRSS_PI_241_DATA 0x0000000F +#define DDRSS_PI_240_DATA 0x0000006E +#define DDRSS_PI_241_DATA 0x00000010 #define DDRSS_PI_242_DATA 0x000681C8 -#define DDRSS_PI_243_DATA 0x000186A0 +#define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 #define DDRSS_PI_245_DATA 0x000010A9 #define DDRSS_PI_246_DATA 0x00000266 #define DDRSS_PI_247_DATA 0x000681C8 -#define DDRSS_PI_248_DATA 0x000186A0 +#define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 #define DDRSS_PI_250_DATA 0x000010A9 #define DDRSS_PI_251_DATA 0x01000266 -#define DDRSS_PI_252_DATA 0x00320040 +#define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 #define DDRSS_PI_254_DATA 0x08550040 #define DDRSS_PI_255_DATA 0x00010040 #define DDRSS_PI_256_DATA 0x08550040 #define DDRSS_PI_257_DATA 0x00000340 #define DDRSS_PI_258_DATA 0x006B006B -#define DDRSS_PI_259_DATA 0x00040404 +#define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 -#define DDRSS_PI_261_DATA 0x55003C5A +#define DDRSS_PI_261_DATA 0x55083C5A #define DDRSS_PI_262_DATA 0x5A000000 -#define DDRSS_PI_263_DATA 0x0055003C +#define DDRSS_PI_263_DATA 0x0055083C #define DDRSS_PI_264_DATA 0x3C5A0000 -#define DDRSS_PI_265_DATA 0x00005500 +#define DDRSS_PI_265_DATA 0x00005508 #define DDRSS_PI_266_DATA 0x0C3C5A00 #define DDRSS_PI_267_DATA 0x080F0E0D #define DDRSS_PI_268_DATA 0x000B0A09 @@ -802,8 +803,8 @@ #define DDRSS_PHY_29_DATA 0x00000808 #define DDRSS_PHY_30_DATA 0x0F000000 #define DDRSS_PHY_31_DATA 0x00000F0F -#define DDRSS_PHY_32_DATA 0x10200000 -#define DDRSS_PHY_33_DATA 0x0C002007 +#define DDRSS_PHY_32_DATA 0x10400000 +#define DDRSS_PHY_33_DATA 0x0C002006 #define DDRSS_PHY_34_DATA 0x00000000 #define DDRSS_PHY_35_DATA 0x00000000 #define DDRSS_PHY_36_DATA 0x55555555 @@ -878,7 +879,7 @@ #define DDRSS_PHY_105_DATA 0x0F0C3701 #define DDRSS_PHY_106_DATA 0x01000140 #define DDRSS_PHY_107_DATA 0x0C000420 -#define DDRSS_PHY_108_DATA 0x00000322 +#define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 @@ -1058,8 +1059,8 @@ #define DDRSS_PHY_285_DATA 0x00000808 #define DDRSS_PHY_286_DATA 0x0F000000 #define DDRSS_PHY_287_DATA 0x00000F0F -#define DDRSS_PHY_288_DATA 0x10200000 -#define DDRSS_PHY_289_DATA 0x0C002007 +#define DDRSS_PHY_288_DATA 0x10400000 +#define DDRSS_PHY_289_DATA 0x0C002006 #define DDRSS_PHY_290_DATA 0x00000000 #define DDRSS_PHY_291_DATA 0x00000000 #define DDRSS_PHY_292_DATA 0x55555555 @@ -1134,7 +1135,7 @@ #define DDRSS_PHY_361_DATA 0x0F0C3701 #define DDRSS_PHY_362_DATA 0x01000140 #define DDRSS_PHY_363_DATA 0x0C000420 -#define DDRSS_PHY_364_DATA 0x00000322 +#define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 @@ -1314,8 +1315,8 @@ #define DDRSS_PHY_541_DATA 0x00000808 #define DDRSS_PHY_542_DATA 0x0F000000 #define DDRSS_PHY_543_DATA 0x00000F0F -#define DDRSS_PHY_544_DATA 0x10200000 -#define DDRSS_PHY_545_DATA 0x0C002007 +#define DDRSS_PHY_544_DATA 0x10400000 +#define DDRSS_PHY_545_DATA 0x0C002006 #define DDRSS_PHY_546_DATA 0x00000000 #define DDRSS_PHY_547_DATA 0x00000000 #define DDRSS_PHY_548_DATA 0x55555555 @@ -1390,7 +1391,7 @@ #define DDRSS_PHY_617_DATA 0x0F0C3701 #define DDRSS_PHY_618_DATA 0x01000140 #define DDRSS_PHY_619_DATA 0x0C000420 -#define DDRSS_PHY_620_DATA 0x00000322 +#define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 @@ -1570,8 +1571,8 @@ #define DDRSS_PHY_797_DATA 0x00000808 #define DDRSS_PHY_798_DATA 0x0F000000 #define DDRSS_PHY_799_DATA 0x00000F0F -#define DDRSS_PHY_800_DATA 0x10200000 -#define DDRSS_PHY_801_DATA 0x0C002007 +#define DDRSS_PHY_800_DATA 0x10400000 +#define DDRSS_PHY_801_DATA 0x0C002006 #define DDRSS_PHY_802_DATA 0x00000000 #define DDRSS_PHY_803_DATA 0x00000000 #define DDRSS_PHY_804_DATA 0x55555555 @@ -1646,7 +1647,7 @@ #define DDRSS_PHY_873_DATA 0x0F0C3701 #define DDRSS_PHY_874_DATA 0x01000140 #define DDRSS_PHY_875_DATA 0x0C000420 -#define DDRSS_PHY_876_DATA 0x00000322 +#define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 @@ -2080,7 +2081,7 @@ #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00050000 +#define DDRSS_PHY_1310_DATA 0x00052000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 diff --git a/arch/arm/dts/mt7986a-bpi-r3-emmc.dts b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts new file mode 100644 index 00000000000..4e2e5262f53 --- /dev/null +++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986a-bpi-r3-sd.dts" +#include <dt-bindings/gpio/gpio.h> +/ { + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts new file mode 100644 index 00000000000..4d12440fa3c --- /dev/null +++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "BananaPi BPi-R3"; + compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory { + label = "reset"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: green { + label = "green:status"; + gpios = <&gpio 69 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: blue { + label = "blue:status"; + gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + pwm_pins: pwm0-pins-func-1 { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_51"; + }; + + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + conf-clk { + pins = "EMMC_CK"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-dsl { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <1>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + }; + }; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "factory"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/dts/ns-board.dts b/arch/arm/dts/ns-board.dts new file mode 100644 index 00000000000..bc2a0dd1c96 --- /dev/null +++ b/arch/arm/dts/ns-board.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "bcm5301x.dtsi" + +/ { + /* + * The Northstar does not have a proper fallback compatible, but + * these basic chips will suffice. + */ + model = "Northstar model"; + compatible = "brcm,bcm47094", "brcm,bcm4708"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + nand-controller@18028000 { + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Same as using the bcm5301x-nand-cs0-bch1.dtsi + * include from the Linux kernel. + */ + nand-ecc-algo = "bch"; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; +}; + +&uart0 { + clock-frequency = <125000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi deleted file mode 100644 index 45435bb88c8..00000000000 --- a/arch/arm/dts/omap5-board-common.dtsi +++ /dev/null @@ -1,762 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include "omap5.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - aliases { - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vsys_cobra: fixedregulator-vsys_cobra { - compatible = "regulator-fixed"; - regulator-name = "vsys_cobra"; - vin-supply = <&vmain>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdds_1v8_main: fixedregulator-vdds_1v8_main { - compatible = "regulator-fixed"; - regulator-name = "vdds_1v8_main"; - vin-supply = <&smps7_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vmmcsd_fixed: fixedregulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - mmc3_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clk32kgaudio>; - clock-names = "ext_clock"; - }; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ - enable-active-high; - startup-delay-us = <70000>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ - clocks = <&auxclk1_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ - #phy-cells = <0>; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - /* gpios defined in the board specific dts */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "b"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "omap5-uevm"; - - ti,jack-detection; - ti,mclk-freq = <19200000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; -}; - -&gpio8 { - /* TI trees use GPIO instead of msecure, see also muxing */ - msecure-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "gpio8_234/msecure"; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_pins - &led_gpio_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ - OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ - OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ - OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ - OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ - OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ - OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ - OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ - OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ - OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ - OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ - OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ - OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ - >; - }; - - /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas_msecure_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ - >; - }; - - usbhost_pins: pinmux_usbhost_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ - OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ - >; - }; - - led_gpio_pins: pinmux_led_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ - OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ - OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ - >; - }; - - uart5_pins: pinmux_uart5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ - OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ - OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ - OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; -}; - -&omap5_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_wkup_pins - >; - - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { - pinctrl-single,pins = < - /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - usbhost_wkup_pins: pinmux_usbhost_wkup_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ - >; - }; - - wlcore_irq_pin: pinmux_wlcore_irq_pin { - pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x16a>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wlcore_irq_pin>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ - ref-clock-frequency = <26000000>; - }; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - palmas: palmas@48 { - compatible = "ti,palmas"; - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; - reg = <0x48>; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - ti,mux-pad1 = <0xa1>; - ti,mux-pad2 = <0x1b>; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; - }; - - clk32kgaudio: palmas_clk32k@1 { - compatible = "ti,palmas-clk32kgaudio"; - #clock-cells = <0>; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - - gpadc: gpadc { - compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; - #io-channel-cells = <1>; - ti,channel0-current-microamp = <5>; - ti,channel3-current-microamp = <10>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - smps123-in-supply = <&vsys_cobra>; - smps45-in-supply = <&vsys_cobra>; - smps6-in-supply = <&vsys_cobra>; - smps7-in-supply = <&vsys_cobra>; - smps8-in-supply = <&vsys_cobra>; - smps9-in-supply = <&vsys_cobra>; - smps10_out2-in-supply = <&vsys_cobra>; - smps10_out1-in-supply = <&vsys_cobra>; - ldo1-in-supply = <&vsys_cobra>; - ldo2-in-supply = <&vsys_cobra>; - ldo3-in-supply = <&vdds_1v8_main>; - ldo4-in-supply = <&vdds_1v8_main>; - ldo5-in-supply = <&vsys_cobra>; - ldo6-in-supply = <&vdds_1v8_main>; - ldo7-in-supply = <&vsys_cobra>; - ldo8-in-supply = <&vsys_cobra>; - ldo9-in-supply = <&vmmcsd_fixed>; - ldoln-in-supply = <&vsys_cobra>; - ldousb-in-supply = <&vsys_cobra>; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - ti,smps-range = <0x80>; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VCC_2V8_DISP: Does not go anywhere */ - regulator-name = "ldo2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* Unused */ - status = "disabled"; - }; - - ldo3_reg: ldo3 { - /* VDDAPHY_MDM: vdda_lli */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - /* Only if Modem is used */ - status = "disabled"; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3v0: Does not go anywhere */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - /* Unused */ - status = "disabled"; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas_power_button: palmas_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&palmas>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>; - - /* audpwron gpio defined in the board specific dts */ - - vio-supply = <&smps7_reg>; - v2v1-supply = <&smps9_reg>; - enable-active-high; - - clocks = <&clk32kgaudio>, <&fref_xtal_ck>; - clock-names = "clk32k", "mclk"; - }; -}; - -&mcpdm_module { - /* Module on the SoC needs external clock from the PMIC */ - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - status = "okay"; -}; - -&mcpdm { - clocks = <&twl6040>; - clock-names = "pdmclk"; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&dwc3 { - extcon = <&extcon_usb3>; - dr_mode = "otg"; -}; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&omap5_pmx_core 0x19c>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - - /* vdda-supply populated in board specific dts file */ - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/arch/arm/dts/omap5-l4-abe.dtsi b/arch/arm/dts/omap5-l4-abe.dtsi deleted file mode 100644 index f73eea0b434..00000000000 --- a/arch/arm/dts/omap5-l4-abe.dtsi +++ /dev/null @@ -1,449 +0,0 @@ -&l4_abe { /* 0x40100000 */ - compatible = "ti,omap5-l4-abe", "simple-bus"; - reg = <0x40100000 0x400>, - <0x40100400 0x400>; - reg-names = "la", "ap"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ - <0x49000000 0x49000000 0x100000>; - segment@0 { /* 0x40100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = - /* CPU to L4 ABE mapping */ - <0x00000000 0x00000000 0x000400>, /* ap 0 */ - <0x00000400 0x00000400 0x000400>, /* ap 1 */ - <0x00022000 0x00022000 0x001000>, /* ap 2 */ - <0x00023000 0x00023000 0x001000>, /* ap 3 */ - <0x00024000 0x00024000 0x001000>, /* ap 4 */ - <0x00025000 0x00025000 0x001000>, /* ap 5 */ - <0x00026000 0x00026000 0x001000>, /* ap 6 */ - <0x00027000 0x00027000 0x001000>, /* ap 7 */ - <0x00028000 0x00028000 0x001000>, /* ap 8 */ - <0x00029000 0x00029000 0x001000>, /* ap 9 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ - <0x00030000 0x00030000 0x001000>, /* ap 14 */ - <0x00031000 0x00031000 0x001000>, /* ap 15 */ - <0x00032000 0x00032000 0x001000>, /* ap 16 */ - <0x00033000 0x00033000 0x001000>, /* ap 17 */ - <0x00038000 0x00038000 0x001000>, /* ap 18 */ - <0x00039000 0x00039000 0x001000>, /* ap 19 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ - <0x00080000 0x00080000 0x010000>, /* ap 26 */ - <0x00080000 0x00080000 0x001000>, /* ap 27 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ - <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ - <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ - <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ - <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ - - /* L3 to L4 ABE mapping */ - <0x49000000 0x49000000 0x000400>, /* ap 0 */ - <0x49000400 0x49000400 0x000400>, /* ap 1 */ - <0x49022000 0x49022000 0x001000>, /* ap 2 */ - <0x49023000 0x49023000 0x001000>, /* ap 3 */ - <0x49024000 0x49024000 0x001000>, /* ap 4 */ - <0x49025000 0x49025000 0x001000>, /* ap 5 */ - <0x49026000 0x49026000 0x001000>, /* ap 6 */ - <0x49027000 0x49027000 0x001000>, /* ap 7 */ - <0x49028000 0x49028000 0x001000>, /* ap 8 */ - <0x49029000 0x49029000 0x001000>, /* ap 9 */ - <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ - <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ - <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ - <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ - <0x49030000 0x49030000 0x001000>, /* ap 14 */ - <0x49031000 0x49031000 0x001000>, /* ap 15 */ - <0x49032000 0x49032000 0x001000>, /* ap 16 */ - <0x49033000 0x49033000 0x001000>, /* ap 17 */ - <0x49038000 0x49038000 0x001000>, /* ap 18 */ - <0x49039000 0x49039000 0x001000>, /* ap 19 */ - <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ - <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ - <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ - <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ - <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ - <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ - <0x49080000 0x49080000 0x010000>, /* ap 26 */ - <0x49080000 0x49080000 0x001000>, /* ap 27 */ - <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ - <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ - <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ - <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ - <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ - <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ - - target-module@22000 { /* 0x40122000, ap 2 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2208c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>, - <0x49022000 0x49022000 0x1000>; - - mcbsp1: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x40124000, ap 4 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2408c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>, - <0x49024000 0x49024000 0x1000>; - - mcbsp2: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x40126000, ap 6 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>, - <0x49026000 0x49026000 0x1000>; - - mcbsp3: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x40128000, ap 8 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>; - }; - - target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>, - <0x4902a000 0x4902a000 0x1000>; - }; - - target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>, - <0x4902e000 0x4902e000 0x1000>; - - dmic: dmic@0 { - compatible = "ti,omap4-dmic"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x40130000, ap 14 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>, - <0x49030000 0x49030000 0x1000>; - }; - - mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>, - <0x49032000 0x49032000 0x1000>; - - /* Must be only enabled for boards with pdmclk wired */ - status = "disabled"; - - mcpdm: mcpdm@0 { - compatible = "ti,omap4-mcpdm"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - }; - }; - - target-module@38000 { /* 0x40138000, ap 18 12.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x38000 0x4>, - <0x38010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>, - <0x49038000 0x49038000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>, - <0x4903a000 0x4903a000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>, - <0x4903c000 0x4903c000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - }; - }; - - target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>, - <0x4903e000 0x4903e000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@80000 { /* 0x40180000, ap 26 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>, - <0x49080000 0x49080000 0x10000>; - }; - - target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>, - <0x490a0000 0x490a0000 0x10000>; - }; - - target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x10000>, - <0x490c0000 0x490c0000 0x10000>; - }; - - target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf1000 0x4>, - <0xf1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf1000 0x1000>, - <0x490f1000 0x490f1000 0x1000>; - }; - }; -}; diff --git a/arch/arm/dts/omap5-l4.dtsi b/arch/arm/dts/omap5-l4.dtsi deleted file mode 100644 index 4521b6447f6..00000000000 --- a/arch/arm/dts/omap5-l4.dtsi +++ /dev/null @@ -1,2437 +0,0 @@ -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap5-l4-cfg", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ - <0x00080000 0x4a080000 0x080000>, /* segment 1 */ - <0x00100000 0x4a100000 0x080000>, /* segment 2 */ - <0x00180000 0x4a180000 0x080000>, /* segment 3 */ - <0x00200000 0x4a200000 0x080000>, /* segment 4 */ - <0x00280000 0x4a280000 0x080000>, /* segment 5 */ - <0x00300000 0x4a300000 0x080000>; /* segment 6 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00002000 0x00002000 0x001000>, /* ap 3 */ - <0x00003000 0x00003000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 5 */ - <0x00005000 0x00005000 0x001000>, /* ap 6 */ - <0x00056000 0x00056000 0x001000>, /* ap 7 */ - <0x00057000 0x00057000 0x001000>, /* ap 8 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ - <0x00058000 0x00058000 0x001000>, /* ap 10 */ - <0x00062000 0x00062000 0x001000>, /* ap 11 */ - <0x00063000 0x00063000 0x001000>, /* ap 12 */ - <0x00008000 0x00008000 0x002000>, /* ap 21 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ - <0x00066000 0x00066000 0x001000>, /* ap 23 */ - <0x00067000 0x00067000 0x001000>, /* ap 24 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ - <0x00060000 0x00060000 0x001000>, /* ap 70 */ - <0x00064000 0x00064000 0x001000>, /* ap 71 */ - <0x00065000 0x00065000 0x001000>, /* ap 72 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ - <0x00070000 0x00070000 0x004000>, /* ap 79 */ - <0x00074000 0x00074000 0x001000>, /* ap 80 */ - <0x00075000 0x00075000 0x001000>, /* ap 81 */ - <0x00076000 0x00076000 0x001000>, /* ap 82 */ - <0x00020000 0x00020000 0x020000>, /* ap 109 */ - <0x00040000 0x00040000 0x001000>, /* ap 110 */ - <0x00059000 0x00059000 0x001000>; /* ap 111 */ - - target-module@2000 { /* 0x4a002000, ap 3 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - scm_core: scm@0 { - compatible = "ti,omap5-scm-core", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - scm_padconf_core: scm@800 { - compatible = "ti,omap5-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x800>; - - omap5_pmx_core: pinmux@40 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x40 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0xec>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0xec>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap5", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - }; - - target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - cm_core_aon: cm_core_aon@0 { - compatible = "ti,omap5-cm-core-aon", - "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm_core: cm_core@0 { - compatible = "ti,omap5-cm-core", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - target-module@20000 { /* 0x4a020000, ap 109 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss"; - reg = <0x20000 0x4>, - <0x20010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x20000>; - - usb3: omap_dwc3@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - dwc3: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "peripheral"; - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 7 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ - clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@58000 { /* 0x4a058000, ap 10 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00058000 0x00001000>, - <0x00001000 0x00059000 0x00001000>, - <0x00002000 0x0005a000 0x00001000>, - <0x00003000 0x0005b000 0x00001000>; - }; - - target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_tll_hs"; - reg = <0x62000 0x4>, - <0x62010 0x4>, - <0x62014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - usbhstll: usbhstll@0 { - compatible = "ti,usbhs-tll"; - reg = <0x0 0x1000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_host_hs"; - reg = <0x64000 0x4>, - <0x64010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - usbhshost: usbhshost@0 { - compatible = "ti,usbhs-host"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - clocks = <&l3init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@800 { - compatible = "ti,ohci-omap3"; - reg = <0x800 0x400>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - remote-wakeup-connected; - }; - - usbhsehci: ehci@c00 { - compatible = "ti,ehci-omap"; - reg = <0xc00 0x400>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - - target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66000 0x4>, - <0x66010 0x4>, - <0x66014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ - clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp 1>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - mmu_dsp: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <0>; - }; - }; - - target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x4000>; - }; - - target-module@75000 { /* 0x4a075000, ap 81 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x75000 0x1000>; - }; - }; - - segment@80000 { /* 0x4a080000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ - <0x0005a000 0x000da000 0x001000>, /* ap 14 */ - <0x0005b000 0x000db000 0x001000>, /* ap 15 */ - <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ - <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ - <0x0005e000 0x000de000 0x001000>, /* ap 18 */ - <0x00060000 0x000e0000 0x001000>, /* ap 19 */ - <0x00061000 0x000e1000 0x001000>, /* ap 20 */ - <0x00074000 0x000f4000 0x001000>, /* ap 25 */ - <0x00075000 0x000f5000 0x001000>, /* ap 26 */ - <0x00076000 0x000f6000 0x001000>, /* ap 27 */ - <0x00077000 0x000f7000 0x001000>, /* ap 28 */ - <0x00036000 0x000b6000 0x001000>, /* ap 65 */ - <0x00037000 0x000b7000 0x001000>, /* ap 66 */ - <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ - <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ - <0x00000000 0x00080000 0x004000>, /* ap 83 */ - <0x00004000 0x00084000 0x001000>, /* ap 84 */ - <0x00005000 0x00085000 0x001000>, /* ap 85 */ - <0x00006000 0x00086000 0x001000>, /* ap 86 */ - <0x00007000 0x00087000 0x001000>, /* ap 87 */ - <0x00008000 0x00088000 0x001000>, /* ap 88 */ - <0x00010000 0x00090000 0x004000>, /* ap 89 */ - <0x00014000 0x00094000 0x001000>, /* ap 90 */ - <0x00015000 0x00095000 0x001000>, /* ap 91 */ - <0x00016000 0x00096000 0x001000>, /* ap 92 */ - <0x00017000 0x00097000 0x001000>, /* ap 93 */ - <0x00018000 0x00098000 0x001000>, /* ap 94 */ - <0x00020000 0x000a0000 0x004000>, /* ap 95 */ - <0x00024000 0x000a4000 0x001000>, /* ap 96 */ - <0x00025000 0x000a5000 0x001000>, /* ap 97 */ - <0x00026000 0x000a6000 0x001000>, /* ap 98 */ - <0x00027000 0x000a7000 0x001000>, /* ap 99 */ - <0x00028000 0x000a8000 0x001000>; /* ap 100 */ - - target-module@0 { /* 0x4a080000, ap 83 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x14 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00004000>, - <0x00004000 0x00004000 0x00001000>, - <0x00005000 0x00005000 0x00001000>, - <0x00006000 0x00006000 0x00001000>, - <0x00007000 0x00007000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x20>; - }; - - usb2_phy: usb2phy@4000 { - compatible = "ti,omap-usb2"; - reg = <0x4000 0x7c>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4400 { - compatible = "ti,omap-usb3"; - reg = <0x4400 0x80>, - <0x4800 0x64>, - <0x4c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@10000 { /* 0x4a090000, ap 89 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x10000 0x4>, - <0x10010 0x4>, - <0x10014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x00004000>, - <0x00004000 0x00014000 0x00001000>, - <0x00005000 0x00015000 0x00001000>, - <0x00006000 0x00016000 0x00001000>, - <0x00007000 0x00017000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x20>; - }; - - sata_phy: phy@6000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x6400 0x64>, /* phy_tx */ - <0x6800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00020000 0x00004000>, - <0x00004000 0x00024000 0x00001000>, - <0x00005000 0x00025000 0x00001000>, - <0x00006000 0x00026000 0x00001000>, - <0x00007000 0x00027000 0x00001000>; - }; - - target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000 0x1000>; - }; - - target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - }; - - target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - }; - - target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x74000 0x4>, - <0x74010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox-ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - }; - - target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x76000 0x4>, - <0x76010 0x4>, - <0x76014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ - <0x00003000 0x00103000 0x001000>, /* ap 60 */ - <0x00008000 0x00108000 0x001000>, /* ap 61 */ - <0x00009000 0x00109000 0x001000>, /* ap 62 */ - <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ - <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ - <0x00040000 0x00140000 0x010000>, /* ap 101 */ - <0x00050000 0x00150000 0x001000>; /* ap 102 */ - - target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 61 26.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@40000 { /* 0x4a140000, ap 101 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - }; - }; - - segment@180000 { /* 0x4a180000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ - <0x00006000 0x00206000 0x001000>, /* ap 33 */ - <0x00007000 0x00207000 0x001000>, /* ap 34 */ - <0x00004000 0x00204000 0x001000>, /* ap 35 */ - <0x00005000 0x00205000 0x001000>, /* ap 36 */ - <0x00012000 0x00212000 0x001000>, /* ap 37 */ - <0x00013000 0x00213000 0x001000>, /* ap 38 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ - <0x00010000 0x00210000 0x001000>, /* ap 41 */ - <0x00011000 0x00211000 0x001000>, /* ap 42 */ - <0x00016000 0x00216000 0x001000>, /* ap 43 */ - <0x00017000 0x00217000 0x001000>, /* ap 44 */ - <0x00014000 0x00214000 0x001000>, /* ap 45 */ - <0x00015000 0x00215000 0x001000>, /* ap 46 */ - <0x00018000 0x00218000 0x001000>, /* ap 47 */ - <0x00019000 0x00219000 0x001000>, /* ap 48 */ - <0x00020000 0x00220000 0x001000>, /* ap 49 */ - <0x00021000 0x00221000 0x001000>, /* ap 50 */ - <0x00026000 0x00226000 0x001000>, /* ap 51 */ - <0x00027000 0x00227000 0x001000>, /* ap 52 */ - <0x00028000 0x00228000 0x001000>, /* ap 53 */ - <0x00029000 0x00229000 0x001000>, /* ap 54 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ - <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ - <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ - <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ - <0x00024000 0x00224000 0x001000>, /* ap 75 */ - <0x00025000 0x00225000 0x001000>, /* ap 76 */ - <0x00002000 0x00202000 0x001000>, /* ap 103 */ - <0x00003000 0x00203000 0x001000>, /* ap 104 */ - <0x00008000 0x00208000 0x001000>, /* ap 105 */ - <0x00009000 0x00209000 0x001000>, /* ap 106 */ - <0x00022000 0x00222000 0x001000>, /* ap 107 */ - <0x00023000 0x00223000 0x001000>; /* ap 108 */ - - target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@4000 { /* 0x4a204000, ap 35 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - }; - - target-module@8000 { /* 0x4a208000, ap 105 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 41 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 37 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x4a216000, ap 43 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - }; - - target-module@24000 { /* 0x4a224000, ap 75 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 51 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x4a228000, ap 53 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - }; - - segment@280000 { /* 0x4a280000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@300000 { /* 0x4a300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,omap5-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00055000 0x00055000 0x001000>, /* ap 13 */ - <0x00056000 0x00056000 0x001000>, /* ap 14 */ - <0x00057000 0x00057000 0x001000>, /* ap 15 */ - <0x00058000 0x00058000 0x001000>, /* ap 16 */ - <0x00059000 0x00059000 0x001000>, /* ap 17 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ - <0x00060000 0x00060000 0x001000>, /* ap 23 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ - <0x00070000 0x00070000 0x001000>, /* ap 30 */ - <0x00071000 0x00071000 0x001000>, /* ap 31 */ - <0x00072000 0x00072000 0x001000>, /* ap 32 */ - <0x00073000 0x00073000 0x001000>, /* ap 33 */ - <0x00061000 0x00061000 0x001000>, /* ap 34 */ - <0x00053000 0x00053000 0x001000>, /* ap 35 */ - <0x00054000 0x00054000 0x001000>, /* ap 36 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x001000>, /* ap 39 */ - <0x00079000 0x00079000 0x001000>, /* ap 40 */ - <0x00086000 0x00086000 0x001000>, /* ap 41 */ - <0x00087000 0x00087000 0x001000>, /* ap 42 */ - <0x00088000 0x00088000 0x001000>, /* ap 43 */ - <0x00089000 0x00089000 0x001000>, /* ap 44 */ - <0x00051000 0x00051000 0x001000>, /* ap 45 */ - <0x00052000 0x00052000 0x001000>, /* ap 46 */ - <0x00098000 0x00098000 0x001000>, /* ap 47 */ - <0x00099000 0x00099000 0x001000>, /* ap 48 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ - <0x00068000 0x00068000 0x001000>, /* ap 53 */ - <0x00069000 0x00069000 0x001000>, /* ap 54 */ - <0x00090000 0x00090000 0x002000>, /* ap 55 */ - <0x00092000 0x00092000 0x001000>, /* ap 56 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ - <0x00066000 0x00066000 0x001000>, /* ap 63 */ - <0x00067000 0x00067000 0x001000>, /* ap 64 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ - <0x00001400 0x00001400 0x000400>, /* ap 77 */ - <0x00001800 0x00001800 0x000400>, /* ap 78 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ - <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ - <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ - <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ - <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 3e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 46.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 4e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - }; - }; - - target-module@51000 { /* 0x48051000, ap 45 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x51000 0x4>, - <0x51010 0x4>, - <0x51114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - - gpio7: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@53000 { /* 0x48053000, ap 35 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53000 0x4>, - <0x53010 0x4>, - <0x53114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - - gpio8: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 15 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 23 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@66000 { /* 0x48066000, ap 63 4c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66050 0x4>, - <0x66054 0x4>, - <0x66058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - uart5: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@68000 { /* 0x48068000, ap 53 54.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x68050 0x4>, - <0x68054 0x4>, - <0x68058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x1000>; - - uart6: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@70000 { /* 0x48070000, ap 30 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@72000 { /* 0x48072000, ap 32 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@78000 { /* 0x48078000, ap 39 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - }; - - target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7a000 0x8>, - <0x7a010 0x8>, - <0x7a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7a000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7c000 0x8>, - <0x7c010 0x8>, - <0x7c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x1000>; - - i2c5: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@86000 { /* 0x48086000, ap 41 5e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x86000 0x4>, - <0x86010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - }; - }; - - target-module@88000 { /* 0x48088000, ap 43 66.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - }; - }; - - rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@98000 { /* 0x48098000, ap 47 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - }; - - target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - }; - - target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd5000 0x4>, - <0xd5010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - - mmc5: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_wkup { /* 0x4ae00000 */ - compatible = "ti,omap5-l4-wkup", "simple-bus"; - reg = <0x4ae00000 0x800>, - <0x4ae00800 0x800>, - <0x4ae01000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ - <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ - <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ - - segment@0 { /* 0x4ae00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ - <0x00004000 0x00004000 0x001000>, /* ap 17 */ - <0x00005000 0x00005000 0x001000>, /* ap 18 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ - - target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; - reg = <0x4000 0x4>, - <0x4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,omap5-prm", "simple-bus"; - reg = <0x0 0x2000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - scrm: scrm@0 { - compatible = "ti,omap5-scrm"; - reg = <0x0 0x1000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - omap5_pmx_wkup: pinmux@840 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x840 0x003c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { - compatible = "ti,omap5-scm-wkup-pad-conf", - "simple-bus"; - reg = <0xda0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60>; - - scm_wkup_pad_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x60>; - - scm_wkup_pad_conf_clocks: clocks@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; - }; - - segment@10000 { /* 0x4ae10000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ - - target-module@0 { /* 0x4ae10000, ap 5 10.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, - <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x8000 0x4>, - <0x8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xc000 0x4>, - <0xc010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - keypad: keypad@0 { - compatible = "ti,omap4-keypad"; - reg = <0x0 0x400>; - }; - }; - }; - - segment@20000 { /* 0x4ae20000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 21 */ - <0x00001000 0x00021000 0x001000>, /* ap 22 */ - <0x00002000 0x00022000 0x001000>, /* ap 23 */ - <0x00003000 0x00023000 0x001000>, /* ap 24 */ - <0x00007000 0x00027000 0x000400>, /* ap 25 */ - <0x00008000 0x00028000 0x000800>, /* ap 26 */ - <0x00009000 0x00029000 0x000100>, /* ap 27 */ - <0x00008800 0x00028800 0x000200>, /* ap 28 */ - <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ - - target-module@0 { /* 0x4ae20000, ap 21 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00002800 0x00008800 0x00000200>, - <0x00002a00 0x00008a00 0x00000100>, - <0x00003000 0x00009000 0x00000100>; - }; - }; -}; diff --git a/arch/arm/dts/omap5-uevm.dts b/arch/arm/dts/omap5-uevm.dts deleted file mode 100644 index b289b57d054..00000000000 --- a/arch/arm/dts/omap5-uevm.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap5-board-common.dtsi" - -/ { - model = "TI OMAP5 uEVM board"; - compatible = "ti,omap5-uevm", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - aliases { - ethernet = ðernet; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - evm_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&evm_keys_pins>; - - #address-cells = <7>; - #size-cells = <0>; - - btn1 { - label = "BTN1"; - linux,code = <169>; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ - wakeup-source; - autorepeat; - debounce-interval = <50>; - }; - }; - - evm_leds { - compatible = "gpio-leds"; - - led1 { - label = "omap5:red:led"; - gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "omap5:green:led"; - gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "omap5:blue:led"; - gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - - led4 { - label = "omap5:green:led1"; - gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led5 { - label = "omap5:green:led2"; - gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led6 { - label = "omap5:green:led3"; - gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led7 { - label = "omap5:green:led4"; - gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led8 { - label = "omap5:green:led5"; - gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo4_reg>; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; - - gpio9: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ -}; - -&omap5_pmx_core { - evm_keys_pins: pinmux_evm_keys_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ - OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ - <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ - <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ethernet: ethernet@3 { - compatible = "usb424,9730"; - reg = <3>; - }; -}; - -&wlcore { - compatible = "ti,wl1837"; -}; diff --git a/arch/arm/dts/omap5.dtsi b/arch/arm/dts/omap5.dtsi deleted file mode 100644 index 76ab2cb08f2..00000000000 --- a/arch/arm/dts/omap5.dtsi +++ /dev/null @@ -1,583 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include <dt-bindings/bus/ti-sysc.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/omap.h> -#include <dt-bindings/clock/omap5.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,omap5"; - interrupt-parent = <&wakeupgen>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - }; - - timer { - compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ */ - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-parent = <&gic>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48211000 0 0x1000>, - <0 0x48212000 0 0x2000>, - <0 0x48214000 0 0x2000>, - <0 0x48216000 0 0x2000>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48281000 0 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap5-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xc0000000>; - dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0 0x44000000 0 0x2000>, - <0 0x44800000 0 0x3000>, - <0 0x45000000 0 0x4000>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - - l4_wkup: interconnect@4ae00000 { - }; - - l4_cfg: interconnect@4a000000 { - }; - - l4_per: interconnect@48000000 { - }; - - l4_abe: interconnect@40100000 { - }; - - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x20000>; /* 128k */ - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - ranges = <0x0 0x55082000 0x100>; - #size-cells = <1>; - #address-cells = <1>; - - mmu_ipu: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - }; - - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; - ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4c000000 0x400>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - emif2: emif@4d000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4d000000 0x400>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - compatible = "ti,omap5430-bandgap"; - - #thermal-sensor-cells = <1>; - }; - - /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - - target-module@58000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58000000 4>, - <0x58000014 4>; - reg-names = "rev", "syss"; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; - clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x58000000 0x1000000>; - - dss: dss@0 { - compatible = "ti,omap5-dss"; - reg = <0 0x80>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000000>; - - target-module@1000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x1000 0x4>, - <0x1010 0x4>, - <0x1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x1000>; - - dispc@0 { - compatible = "ti,omap5-dispc"; - reg = <0 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@2000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2010 0x4>, - <0x2014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - - rfbi: encoder@0 { - compatible = "ti,omap5-rfbi"; - reg = <0 0x100>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; - clock-names = "fck", "ick"; - }; - }; - - target-module@5000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5000 0x4>, - <0x5010 0x4>, - <0x5014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5000 0x1000>; - - dsi1: encoder@0 { - compatible = "ti,omap5-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@9000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9000 0x4>, - <0x9010 0x4>, - <0x9014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x9000 0x1000>; - - dsi2: encoder@0 { - compatible = "ti,omap5-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@40000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck", "dss_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000 0x40000>; - - hdmi: encoder@0 { - compatible = "ti,omap5-hdmi"; - reg = <0 0x200>, - <0x200 0x80>, - <0x300 0x80>, - <0x20000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, - <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1250000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - - abb_mm: regulator-abb-mm { - compatible = "ti,abb-v2"; - regulator-name = "abb_mm"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, - <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80000000>; - /* LDOVBBMM_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMM_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0x0 0 0x02000000 0x01F00000 - 1120000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - }; -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ - coefficients = <65 (-1791)>; -}; - -#include "omap5-l4.dtsi" -#include "omap54xx-clocks.dtsi" - -&gpu_thermal { - coefficients = <117 (-2992)>; -}; - -&core_thermal { - coefficients = <0 2000>; -}; - -#include "omap5-l4-abe.dtsi" -#include "omap54xx-clocks.dtsi" - -&prm { - prm_dsp: prm@400 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - }; - - prm_core: prm@700 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - }; - - prm_iva: prm@1200 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #reset-cells = <1>; - }; - - prm_device: prm@1c00 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c00 0x100>; - #reset-cells = <1>; - }; -}; diff --git a/arch/arm/dts/omap54xx-clocks.dtsi b/arch/arm/dts/omap54xx-clocks.dtsi deleted file mode 100644 index 4dd3c93e457..00000000000 --- a/arch/arm/dts/omap54xx-clocks.dtsi +++ /dev/null @@ -1,1208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP5 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_core_aon_clocks { - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - abe_iclk: abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - abe_lp_clk_div: abe_lp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f4>; - ti,index-starts-at-one; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - c2c_fclk: c2c_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h21x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - c2c_iclk: c2c_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&c2c_fclk>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0138>; - ti,index-starts-at-one; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x013c>; - ti,index-starts-at-one; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0144>; - ti,index-starts-at-one; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - reg = <0x0130>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <1165000000>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01b8>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h11x2_ck>; - assigned-clock-rates = <465920000>; - }; - - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01bc>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h12x2_ck>; - assigned-clock-rates = <388300000>; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x0170>; - ti,index-starts-at-one; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - gpu_l3_iclk: gpu_l3_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_root_clk_div: l4_root_clk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <8>; - reg = <0x100>; - clocks = <&l3_iclk_div>; - ti,index-power-of-two; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0540>; - }; - - mcasp_gfclk: mcasp_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin: sys_clkin@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x0108>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <2>; - }; - - dss_syc_gfclk_div: dss_syc_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&wkupaon_iclk_mux>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_core_clocks { - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0164>; - ti,index-starts-at-one; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_unipro1_ck: dpll_unipro1_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro1_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro1_ck>; - ti,max-div = <127>; - reg = <0x0210>; - ti,index-starts-at-one; - }; - - dpll_unipro2_ck: dpll_unipro2_ck@1c0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; - }; - - dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro2_ck>; - ti,max-div = <127>; - reg = <0x01d0>; - ti,index-starts-at-one; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x0190>; - ti,index-starts-at-one; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - iss_ctrlclk: iss_ctrlclk@1320 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1320>; - }; - - lli_txphy_clk: lli_txphy_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x0f20>; - }; - - lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_m2_ck>; - ti,bit-shift = <9>; - reg = <0x0f20>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - fdif_fclk: fdif_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_h11x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1328>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <24>; - reg = <0x1520>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <25>; - reg = <0x1520>; - }; - - hsi_fclk: hsi_fclk@1638 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1638>; - }; -}; - -&cm_core_clockdomains { - l3init_clkdm: l3init_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; -}; - -&cm_core_aon { - mpu_cm: mpu_cm@300 { - compatible = "ti,omap4-cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dsp_cm: dsp_cm@400 { - compatible = "ti,omap4-cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - dsp_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - abe_cm: abe_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - abe_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x64>; - #clock-cells = <2>; - }; - }; - -}; - -&cm_core { - l3main1_cm: l3main1_cm@700 { - compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3main1_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3main2_cm: l3main2_cm@800 { - compatible = "ti,omap4-cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l3main2_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - ipu_cm: ipu_cm@900 { - compatible = "ti,omap4-cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ipu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dma_cm: dma_cm@a00 { - compatible = "ti,omap4-cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - dma_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - emif_cm: emif_cm@b00 { - compatible = "ti,omap4-cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - emif_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l4cfg_cm: l4cfg_cm@d00 { - compatible = "ti,omap4-cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4cfg_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3instr_cm: l3instr_cm@e00 { - compatible = "ti,omap4-cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3instr_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - l4per_cm: clock@1000 { - compatible = "ti,omap4-cm"; - reg = <0x1000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x200>; - - l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; - reg = <0x20 0x15c>; - #clock-cells = <2>; - }; - - l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; - reg = <0x1a0 0x3c>; - #clock-cells = <2>; - }; - }; - - dss_cm: dss_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x100>; - - dss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gpu_cm: gpu_cm@1500 { - compatible = "ti,omap4-cm"; - reg = <0x1500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1500 0x100>; - - gpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3init_cm: l3init_cm@1600 { - compatible = "ti,omap4-cm"; - reg = <0x1600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1600 0x100>; - - l3init_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xd4>; - #clock-cells = <2>; - }; - }; -}; - -&prm { - wkupaon_cm: wkupaon_cm@1900 { - compatible = "ti,omap4-cm"; - reg = <0x1900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1900 0x100>; - - wkupaon_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x5c>; - #clock-cells = <2>; - }; - }; -}; - -&scm_wkup_pad_conf_clocks { - fref_xtal_ck: fref_xtal_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin>; - ti,bit-shift = <28>; - reg = <0x14>; - }; -}; diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 607af277f8b..3b86b9328fc 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -51,16 +51,21 @@ }; }; - debug_uart: serial@a84000 { - compatible = "qcom,msm-geni-uart"; - reg = <0xa84000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9>; - qcom,wrapper-core = <0x8a>; - status = "disabled"; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x00ac0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart9: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9>; + }; }; spmi@c440000 { diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts index 34a4f59cbd1..eec51d165f9 100644 --- a/arch/arm/dts/starqltechn.dts +++ b/arch/arm/dts/starqltechn.dts @@ -9,6 +9,8 @@ /dts-v1/; #include "sdm845.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Samsung S9 (SM-G9600)"; @@ -21,7 +23,7 @@ }; aliases { - serial0 = &debug_uart; + serial0 = &uart9; }; memory { @@ -43,6 +45,22 @@ format = "a8r8g8b8"; }; + gpio-keys { + compatible = "gpio-keys"; + + key-pwr { + label = "Power"; + linux,code = <KEY_ENTER>; + gpios = <&pm8998_pon 0 GPIO_ACTIVE_LOW>; + }; + + key-vol-down { + label = "Volume Down"; + linux,code = <KEY_DOWN>; + gpios = <&pm8998_pon 1 GPIO_ACTIVE_LOW>; + }; + }; + soc: soc { serial@a84000 { status = "okay"; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 8ae49715789..81af89c631f 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -41,6 +41,8 @@ enum mxc_clock { MXC_SATA_CLK, MXC_NFC_CLK, MXC_I2C_CLK, + MXC_LCDIF1_CLK, + MXC_LCDIF2_CLK, }; enum ldb_di_clock { diff --git a/arch/arm/mach-histb/Kconfig b/arch/arm/mach-histb/Kconfig new file mode 100644 index 00000000000..012dbfe8bc6 --- /dev/null +++ b/arch/arm/mach-histb/Kconfig @@ -0,0 +1,39 @@ +if ARCH_HISTB + +choice + prompt "Select a HiSTB SoC" + +config ARCH_HI3798MV2X + bool "Hi3798M V2XX series SoC" + select ARM64 + help + Support for Hi3798MV2XX series SoCs. + +endchoice + +if ARCH_HI3798MV2X + +choice + prompt "Select a Hi3798M V2XX based board" + +config TARGET_HC2910_2AGHD05 + bool "Skyworth HC2910 with board label 2AGHD05" + help + Support for Skyworth HC2910 with board label 2AGHD05. This board features: + - Hisilicon Hi3798MV200 SoC (4xCortex-A53, Mali MP-450) + - 2GiB DRAM + - 8GiB eMMC, uSD slot + - Wifi and Bluetooth module + - 1x USB 2.0, 1x USB 3.0 host port + - HDMI + - SCI + - 3 LED - power, Wifi, Lock(?) + - 1x Fast Ethernet Controller, 1x GBe Ethernet Controller + +endchoice + +endif + +source "board/skyworth/hc2910-2aghd05/Kconfig" + +endif diff --git a/arch/arm/mach-histb/Makefile b/arch/arm/mach-histb/Makefile new file mode 100644 index 00000000000..7975c0f2a03 --- /dev/null +++ b/arch/arm/mach-histb/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += sysmap-histb.o +obj-y += board_common.o diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c new file mode 100644 index 00000000000..a26c2066e02 --- /dev/null +++ b/arch/arm/mach-histb/board_common.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for all histb boards + * + * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <asm/system.h> + +int __weak board_init(void) +{ + return 0; +} + +int __weak dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int __weak dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +void __weak reset_cpu(void) +{ + psci_system_reset(); +} diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c new file mode 100644 index 00000000000..83a2bb94179 --- /dev/null +++ b/arch/arm/mach-histb/sysmap-histb.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hisilicon HiSTB memory map + * + * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com> + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region histb_mem_map[] = { + { + .virt = 0x0UL, /* DRAM */ + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, /* Peripheral block */ + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Terminator */ + 0, + } +}; + +struct mm_region *mem_map = histb_mem_map; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 018b87b85b7..15f844f5030 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -91,6 +91,13 @@ config TARGET_IMX8QM_ROM7720_A1 select SUPPORT_SPL select IMX8QM +config TARGET_IMX8QM_DMSSE20_A1 + bool "Support i.MX8QM DMS-SE20-A1 board" + select BINMAN + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BINMAN @@ -105,6 +112,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/congatec/cgtqmx8/Kconfig" +source "board/advantech/imx8qm_dmsse20_a1/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index dc51f971d45..7639439bdc9 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MQ_REFORM2 + bool "imx8mq_reform2" + select BINMAN + select IMX8MQ + select IMX8M_LPDDR4 + config TARGET_IMX8MM_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Mini" select BINMAN @@ -362,6 +368,7 @@ source "board/kontron/pitx_imx8m/Kconfig" source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" +source "board/mntre/imx8mq_reform2/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/purism/librem5/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index df865e997d3..4705e6c1192 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -914,6 +914,8 @@ static int low_drive_gpu_freq(void *blob) if (cnt != 7) printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt); + if (cnt < 2) + return -1; assignedclks[cnt - 1] = 200000000; assignedclks[cnt - 2] = 200000000; @@ -1395,40 +1397,6 @@ usb_modify_speed: } #endif -#ifdef CONFIG_OF_BOARD_FIXUP -#ifndef CONFIG_SPL_BUILD -int board_fix_fdt(void *fdt) -{ - if (is_imx8mpul()) { - int i = 0; - int nodeoff, ret; - const char *status = "disabled"; - static const char * const dsi_nodes[] = { - "/soc@0/bus@32c00000/mipi_dsi@32e60000", - "/soc@0/bus@32c00000/lcd-controller@32e80000", - "/dsi-host" - }; - - for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) { - nodeoff = fdt_path_offset(fdt, dsi_nodes[i]); - if (nodeoff > 0) { -set_status: - ret = fdt_setprop(fdt, nodeoff, "status", status, - strlen(status) + 1); - if (ret == -FDT_ERR_NOSPACE) { - ret = fdt_increase_size(fdt, 512); - if (!ret) - goto set_status; - } - } - } - } - - return 0; -} -#endif -#endif - #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index cb9d629be40..1bdc568f9b1 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num) static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div, test_div, pll_num, pll_denom; + u64 temp64; switch (pll) { case PLL_SYS: @@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } test_div = 1 << (2 - test_div); - return infreq * (div + pll_num / pll_denom) / test_div; + temp64 = (u64)infreq; + temp64 *= pll_num; + do_div(temp64, pll_denom); + return infreq * div + (unsigned long)temp64; default: return 0; } @@ -414,6 +418,60 @@ static u32 get_uart_clk(void) return freq / (uart_podf + 1); } +static u32 get_lcd_clk(unsigned int ifnum) +{ + u32 pll_rate; + u32 pred, postd; + + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() && + !is_mx6sll()) { + debug("This chip does't support lcd\n"); + return 0; + } + + pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK); + if (ifnum == 1) { + if (!is_mx6sl()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cbcmr); + postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } else { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } + } else if (ifnum == 2) { + if (is_mx6sx()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK; + postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET; + + } else { + goto if_err; + } + } else { + goto if_err; + } + + return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1)); + +if_err: + debug("This chip not support lcd iterface %d\n", ifnum); + return 0; +} + static u32 get_cspi_clk(void) { u32 reg, cspi_podf; @@ -744,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) } enable_lcdif_clock(base_addr, 1); + debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK)); } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) @@ -765,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET)); enable_lcdif_clock(base_addr, 1); + debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK)); } } @@ -1269,6 +1329,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_usdhc_clk(3); case MXC_SATA_CLK: return get_ahb_clk(); + case MXC_LCDIF1_CLK: + return get_lcd_clk(1); + case MXC_LCDIF2_CLK: + return get_lcd_clk(2); default: printf("Unsupported MXC CLK: %d\n", clk); break; diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c index b49e7f80a28..ff0522c2d11 100644 --- a/arch/arm/mach-imx/romapi.c +++ b/arch/arm/mach-imx/romapi.c @@ -70,6 +70,8 @@ enum boot_device get_boot_device(void) boot_dev = SPI_NOR_BOOT; break; case BT_DEV_TYPE_USB: + if (!is_imx8ulp() && !is_imx9()) + boot_instance = 0; boot_dev = boot_instance + USB_BOOT; break; default: diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index a8c3a593d57..0ffbbf9168e 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -52,7 +52,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE config SYS_K3_MCU_SCRATCHPAD_BASE hex default 0x40280000 if SOC_K3_AM654 - default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2 + default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 help Describes the base address of MCU Scratchpad RAM. diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index a89a9b4ae3a..1f51b040896 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -65,6 +65,20 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +#if (IS_ENABLED(CONFIG_CPU_V7R)) +static void setup_qos(void) +{ + u32 i; + + for (i = 0; i < am62a_qos_count; i++) + writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg); +} +#else +static void setup_qos(void) +{ +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -158,6 +172,8 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif + setup_qos(); + printf("am62a_init: %s done\n", __func__); } diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile index c58e52df1fa..02a941805e9 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -4,3 +4,4 @@ obj-y += clk-data.o obj-y += dev-data.o +obj-y += am62a_qos_data.o diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c new file mode 100644 index 00000000000..01b76f7493c --- /dev/null +++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am62a Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include "common.h" + +struct k3_qos_data am62a_qos_data[] = { + /* modules_qosConfig0 - 1 endpoints, 4 channels */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ORDERID_8, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, +}; + +uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]); diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 0c295e7fe28..c871e92330b 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -20,9 +20,15 @@ #include <dm/pinctrl.h> #include <mmc.h> #include <dm/root.h> +#include <command.h> #define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) +#define COLD_BOOT 0 +#define SW_POR_MCU BIT(24) +#define SW_POR_MAIN BIT(25) + static void ctrl_mmr_unlock(void) { /* Unlock all PADCFG_MMR1 module registers */ @@ -164,6 +170,7 @@ void board_init_f(ulong dummy) #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3) struct udevice *dev; int ret; + int rst_src; #endif #if defined(CONFIG_CPU_V7R) @@ -206,6 +213,32 @@ void board_init_f(ulong dummy) k3_mmc_restart_clock); #endif +#if defined(CONFIG_CPU_V7R) + /* + * Errata ID i2331 CPSW: A device lockup can occur during the second + * read of any CPSW subsystem register after any MAIN domain power on + * reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz + * signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or + * CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor + * and internal bus structures may get into a state which is only + * recoverable with full device reset using MCU_PORz. + * Workaround(s): To avoid the lockup, a warm reset should be issued + * after a MAIN domain POR and before any access to the CPSW registers. + * The warm reset realigns internal clocks and prevents the lockup from + * happening. + */ + ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); + if (ret) + printf("\n%s:uclass device error [%d]\n",__func__,ret); + + rst_src = readl(CTRLMMR_MCU_RST_SRC); + if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) { + printf("Resetting on cold boot to workaround ErrataID:i2331\n"); + printf("Please resend tiboot3.bin in case of UART/DFU boot\n"); + do_reset(NULL, 0, 0, NULL); + } +#endif + /* Output System Firmware version info */ k3_sysfw_print_ver(); diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 7baab7d1a5f..3c85caee579 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -580,7 +580,10 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) fwl_ops->get_fwl_region(ti_sci, ®ion); - if (region.control != 0) { + /* Don't disable the background regions */ + if (region.control != 0 && + ((region.control & K3_BACKGROUND_FIREWALL_BIT) == + 0)) { pr_debug("Attempting to disable firewall %5d (%25s)\n", region.fwl_id, fwl_data[i].name); region.control = 0; @@ -641,8 +644,8 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } - /* Default FIT boot on non-GP devices */ - if (get_device_type() != K3_DEVICE_TYPE_GP) + /* Default FIT boot on HS-SE devices */ + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) env_set("boot_fit", "1"); return 0; diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 130f5021123..e7e59f533b7 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -9,6 +9,10 @@ #include <asm/armv7_mpu.h> #include <asm/hardware.h> +#define J721E 0xbb64 +#define J7200 0xbb6d +#define K3_BACKGROUND_FIREWALL_BIT BIT(8) + struct fwl_data { const char *name; u16 fwl_id; diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/include/mach/am62a_qos.h new file mode 100644 index 00000000000..c74d69a28f8 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_qos.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0) + +#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4) + +#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8) + +#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12) + +#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16) + +#define ATYPE_0 (0 << 28) +#define ATYPE_1 (1 << 28) +#define ATYPE_2 (2 << 28) +#define ATYPE_3 (3 << 28) + +#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 +#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 +#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800 +#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000 +#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400 +#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800 +#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400 +#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00 +#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000 +#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400 +#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800 +#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00 +#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000 +#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400 +#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800 +#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00 +#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000 +#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400 +#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800 +#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400 +#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800 +#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000 diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 9faf1d6ff06..65742c4b7c8 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -30,6 +30,7 @@ #ifdef CONFIG_SOC_K3_AM62A7 #include "am62a_hardware.h" +#include "am62a_qos.h" #endif /* Assuming these addresses and definitions stay common across K3 devices */ @@ -96,4 +97,12 @@ struct rom_extended_boot_data { u32 num_components; }; +struct k3_qos_data { + u32 reg; + u32 val; +}; + +extern struct k3_qos_data am62a_qos_data[]; +extern u32 am62a_qos_count; + #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 9bba5f79545..0c5d41a77e6 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -25,6 +25,7 @@ #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { +#if defined(CONFIG_TARGET_J721E_R5_EVM) { "PCIE0_CFG", 2560, 8 }, { "PCIE1_CFG", 2561, 8 }, { "USB3SS0_CORE", 2568, 4 }, @@ -33,11 +34,16 @@ struct fwl_data cbass_hc_cfg0_fwls[] = { { "UFS_HCI0_CFG", 2580, 4 }, { "SERDES0", 2584, 1 }, { "SERDES1", 2585, 1 }, +#elif defined(CONFIG_TARGET_J7200_R5_EVM) + { "PCIE1_CFG", 2561, 7 }, +#endif }, cbass_hc0_fwls[] = { +#if defined(CONFIG_TARGET_J721E_R5_EVM) { "PCIE0_HP", 2528, 24 }, { "PCIE0_LP", 2529, 24 }, { "PCIE1_HP", 2530, 24 }, { "PCIE1_LP", 2531, 24 }, +#endif }, cbass_rc_cfg0_fwls[] = { { "EMMCSD4SS0_CFG", 2380, 4 }, }, cbass_rc0_fwls[] = { diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 0787d192b69..5394529658b 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -17,9 +17,6 @@ choice config TARGET_CM_T54 bool "CompuLab CM-T54" -config TARGET_OMAP5_UEVM - bool "TI OMAP5 uEVM board" - config TARGET_DRA7XX_EVM bool "TI DRA7XX" select BOARD_LATE_INIT @@ -162,7 +159,6 @@ endchoice endmenu endif -source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" source "board/ti/am57xx/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig index 218920cfc9a..1cdb390e79b 100644 --- a/arch/powerpc/cpu/mpc83xx/bats/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig @@ -65,18 +65,12 @@ config BAT0_ACCESS_RW endchoice -config BAT0_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT0_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT0_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT0_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT0_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -120,22 +114,10 @@ config BAT0_PAGE_PROTECTION config BAT0_WIMG_ICACHE hex - default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x0 if !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE config BAT0_WIMG_DCACHE hex @@ -228,18 +210,12 @@ config BAT1_ACCESS_RW endchoice -config BAT1_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT1_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT1_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT1_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT1_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -283,22 +259,10 @@ config BAT1_PAGE_PROTECTION config BAT1_WIMG_ICACHE hex - default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x0 if !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE config BAT1_WIMG_DCACHE hex @@ -391,18 +355,12 @@ config BAT2_ACCESS_RW endchoice -config BAT2_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT2_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT2_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT2_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT2_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -446,22 +404,10 @@ config BAT2_PAGE_PROTECTION config BAT2_WIMG_ICACHE hex - default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x0 if !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE config BAT2_WIMG_DCACHE hex @@ -554,18 +500,12 @@ config BAT3_ACCESS_RW endchoice -config BAT3_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT3_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT3_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT3_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT3_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -609,22 +549,10 @@ config BAT3_PAGE_PROTECTION config BAT3_WIMG_ICACHE hex - default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x0 if !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE config BAT3_WIMG_DCACHE hex @@ -719,18 +647,12 @@ config BAT4_ACCESS_RW endchoice -config BAT4_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT4_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT4_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT4_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT4_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -774,22 +696,10 @@ config BAT4_PAGE_PROTECTION config BAT4_WIMG_ICACHE hex - default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x0 if !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE config BAT4_WIMG_DCACHE hex @@ -882,18 +792,12 @@ config BAT5_ACCESS_RW endchoice -config BAT5_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT5_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT5_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT5_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT5_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -937,22 +841,10 @@ config BAT5_PAGE_PROTECTION config BAT5_WIMG_ICACHE hex - default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x0 if !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE config BAT5_WIMG_DCACHE hex @@ -1045,18 +937,12 @@ config BAT6_ACCESS_RW endchoice -config BAT6_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT6_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT6_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT6_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT6_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -1100,22 +986,10 @@ config BAT6_PAGE_PROTECTION config BAT6_WIMG_ICACHE hex - default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x0 if !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE config BAT6_WIMG_DCACHE hex @@ -1208,18 +1082,12 @@ config BAT7_ACCESS_RW endchoice -config BAT7_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT7_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT7_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT7_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT7_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -1263,22 +1131,10 @@ config BAT7_PAGE_PROTECTION config BAT7_WIMG_ICACHE hex - default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x0 if !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE config BAT7_WIMG_DCACHE hex diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index bcdea0b8e7b..453e53db71a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1816,6 +1816,10 @@ lba_shift = <9>; lba = <2048>; }; + + extcon { + compatible = "sandbox,extcon"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig new file mode 100644 index 00000000000..f249ab446c2 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8QM_DMSSE20_A1 + +config SYS_BOARD + default "imx8qm_dmsse20_a1" + +config SYS_VENDOR + default "advantech" + +config SYS_CONFIG_NAME + default "imx8qm_dmsse20" + +config IMX_CONFIG + default "board/advantech/imx8qm_dmsse20_a1/imximage.cfg" + +endif diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS new file mode 100644 index 00000000000..8292c6ba712 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QM ROM DMSSE20 a1 BOARD +M: Oliver Graute <oliver.graute@kococonnector.com> +S: Maintained +F: board/advantech/imx8qm_dmsse20_a1/ +F: arch/arm/dts/imx8qm-dmsse20-a1.dtb +F: include/configs/imx8qm_dmsse20.h +F: configs/imx8qm_dmsse20a1_defconfig diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile new file mode 100644 index 00000000000..262ffcd6834 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_dmsse20_a1.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env new file mode 100644 index 00000000000..0c9f9c4178a --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env @@ -0,0 +1,48 @@ +script=boot.scr +image=Image +panel=NULL +console=ttyLP0 +earlycon=lpuart32,0x5a060000 +fdt_addr=0x83000000 +boot_fdt=try +fdt_file=imx8qm-dmsse20-a1.dtb +mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV) +mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; + else + echo wait for boot; + fi; +netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} + root=/dev/nfs + ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; + else + booti; + fi; diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c new file mode 100644 index 00000000000..867ceff9961 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +/* #include <power-domain.h> */ + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + /* This is needed to because Kernel do not Power Up DC_0 */ + sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) + +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) + +static void board_gpio_init(void) +{ + /* Enable BB 3V3 */ + gpio_request(BB_GPIO_3V3_1, "bb_3v3_1"); + gpio_direction_output(BB_GPIO_3V3_1, 1); + gpio_request(BB_GPIO_3V3_2, "bb_3v3_2"); + gpio_direction_output(BB_GPIO_3V3_2, 1); + gpio_request(BB_GPIO_3V3_3, "bb_3v3_3"); + gpio_direction_output(BB_GPIO_3V3_3, 1); + + /* enable LVDS SAS boards */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable MIPI SAS boards */ + gpio_request(MIPI_ENABLE, "mipi_enable"); + gpio_direction_output(MIPI_ENABLE, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: DMS-SE20A1 8GB\n"); + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + if (IS_ENABLED(CONFIG_XEN)) { + /* Clear magic number to let xen know uboot is over */ + writel(0x0, (void __iomem *)0x80000000); + return; + } +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(void) +{ + puts("SCI reboot request"); + + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "DMS-SE20A1"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg new file mode 100644 index 00000000000..2e51e5757cd --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2017-2018 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +/* SoC type IMX8QM */ +BOOT_FROM sd + +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c new file mode 100644 index 00000000000..49067bbfd65 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2017-2018 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <init.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <fsl_esdhc_imx.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +void init_clk_usdhc(u32 index); + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void spl_board_init(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) { + puts("Warning: failed to initialize FSPI0\n"); + } + } +#endif + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) { + puts("Warning: failed to turn off FSPI0\n"); + } + } +#endif +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/broadcom/bcmns/Kconfig b/board/broadcom/bcmns/Kconfig new file mode 100644 index 00000000000..82f4709e2d2 --- /dev/null +++ b/board/broadcom/bcmns/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BCMNS + +config SYS_BOARD + default "bcmns" + +config SYS_VENDOR + default "broadcom" + +config SYS_CONFIG_NAME + default "bcmns" + +endif diff --git a/board/broadcom/bcmns/MAINTAINERS b/board/broadcom/bcmns/MAINTAINERS new file mode 100644 index 00000000000..fd37c334a5b --- /dev/null +++ b/board/broadcom/bcmns/MAINTAINERS @@ -0,0 +1,6 @@ +BCMNS BOARD +M: Linus Walleij <linus.walleij@linaro.org> +S: Maintained +F: board/broadcom/bcmnsp/ +F: configs/bcmnsp_defconfig +F: include/configs/bcmnsp.h diff --git a/board/broadcom/bcmns/Makefile b/board/broadcom/bcmns/Makefile new file mode 100644 index 00000000000..8a6a8543a90 --- /dev/null +++ b/board/broadcom/bcmns/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y := ns.o diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c new file mode 100644 index 00000000000..1249e45af03 --- /dev/null +++ b/board/broadcom/bcmns/ns.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Broadcom Northstar generic board set-up code + * Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org> + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <ram.h> +#include <serial.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/armv7m.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int board_late_init(void) +{ + /* LEDs etc can be initialized here */ + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ +} + +int print_cpuinfo(void) +{ + printf("BCMNS Northstar SoC\n"); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *fdt, struct bd_info *bd) +{ + printf("Northstar board setup: DTB at 0x%08lx\n", (ulong)fdt); + return 0; +} + diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig new file mode 100644 index 00000000000..f9260cb7f53 --- /dev/null +++ b/board/mntre/imx8mq_reform2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MQ_REFORM2 + +config SYS_BOARD + default "imx8mq_reform2" + +config SYS_VENDOR + default "mntre" + +config SYS_CONFIG_NAME + default "imx8mq_reform2" + +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage.cfg" + +endif diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS new file mode 100644 index 00000000000..946f287ecf8 --- /dev/null +++ b/board/mntre/imx8mq_reform2/MAINTAINERS @@ -0,0 +1,7 @@ +REFORM2 IMX8MQ BOARD +M: Lukas F. Hartmann <lukas@mntre.com> +M: Patrick Wildt <patrick@blueri.se> +S: Maintained +F: board/mntre/imx8mq_reform2/ +F: include/configs/imx8mq_reform2.h +F: configs/imx8mq_reform2_defconfig diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile new file mode 100644 index 00000000000..2efd56bb4ad --- /dev/null +++ b/board/mntre/imx8mq_reform2/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_reform2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c new file mode 100644 index 00000000000..be5c5060a2a --- /dev/null +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com> + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <malloc.h> +#include <errno.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/clock.h> +#include <spl.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <power/pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + return 0; +} + +#ifdef CONFIG_FEC_MXC + +#define PHY_RESET IMX_GPIO_NR(1, 9) +#define PHY_RX_CTL IMX_GPIO_NR(1, 24) +#define PHY_RXC IMX_GPIO_NR(1, 25) +#define PHY_RD0 IMX_GPIO_NR(1, 26) +#define PHY_RD1 IMX_GPIO_NR(1, 27) +#define PHY_RD2 IMX_GPIO_NR(1, 28) +#define PHY_RD3 IMX_GPIO_NR(1, 29) + +#define STRAP_AR8035 (0x28) // 0010 1000 + +static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1), + IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91), + /* 1.8V(1)/1.5V select(0) */ + IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1), +}; + +static const iomux_v3_cfg_t enet_ar8035_pads[] = { + IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91), +}; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Pull PHY into reset */ + gpio_request(PHY_RESET, "fec_rst"); + gpio_direction_output(PHY_RESET, 0); + + /* Configure ethernet pins value as GPIOs */ + gpio_request(PHY_RD0, "fec_rd0"); + gpio_direction_output(PHY_RD0, 0); + gpio_request(PHY_RD1, "fec_rd1"); + gpio_direction_output(PHY_RD1, 0); + gpio_request(PHY_RD2, "fec_rd2"); + gpio_direction_output(PHY_RD2, 0); + gpio_request(PHY_RD3, "fec_rd3"); + gpio_direction_output(PHY_RD3, 1); + gpio_request(PHY_RX_CTL, "fec_rx_ctl"); + gpio_direction_output(PHY_RX_CTL, 0); + gpio_request(PHY_RXC, "fec_rxc"); + gpio_direction_output(PHY_RXC, 1); + + /* Set ethernet pins to GPIO to bootstrap PHY */ + imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads, + ARRAY_SIZE(enet_ar8035_gpio_pads)); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); + set_clk_enet(ENET_125MHZ); + + /* 1 ms minimum reset pulse for ar8035 */ + mdelay(1); + + /* Release PHY from reset */ + gpio_set_value(PHY_RESET, 1); + + /* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */ + udelay(12); + + /* Change ethernet pins back to normal function */ + imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads, + ARRAY_SIZE(enet_ar8035_pads)); +} +#endif + +#define USB1_HUB_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define USB1_HUB_RESET IMX_GPIO_NR(1, 14) + +static void setup_usb(void) +{ + imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | + MUX_PAD_CTRL(USB1_HUB_PAD_CTRL)); + gpio_request(USB1_HUB_RESET, "usb1_rst"); + gpio_direction_output(USB1_HUB_RESET, 0); + mdelay(10); + gpio_set_value(USB1_HUB_RESET, 1); +} + +int board_init(void) +{ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + setup_usb(); + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) + init_usb_clk(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "Reform2"); + env_set("board_rev", "iMX8MQ"); +#endif + + return 0; +} diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c new file mode 100644 index 00000000000..e5303db0f80 --- /dev/null +++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c @@ -0,0 +1,1014 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ +#include "lpddr4_timing_ch2.h" + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { DDRC_DBG1(0), 1 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 1 }, + { DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) }, + { DDRC_MSTR2(0), 0 }, + { DDRC_DERATEEN(0), 0x0203 }, + { DDRC_DERATEINT(0), 0x0003e800 }, + { DDRC_RFSHTMG(0), 0x006100e0 }, + { DDRC_INIT0(0), 0xc003061c }, + { DDRC_INIT1(0), 0x009e0000 }, + { DDRC_INIT3(0), 0x00d4002d }, + { DDRC_INIT4(0), CH2_VAL_INIT4 }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0016004a }, + { DDRC_DRAMTMG0(0), 0x1a201b22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00c0c000 }, + { DDRC_DRAMTMG4(0), 0x0f04080f }, + { DDRC_DRAMTMG5(0), 0x02040c0c }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x0401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0c100002 }, + { DDRC_DRAMTMG14(0), 0xe6 }, + { DDRC_DRAMTMG17(0), 0x00a00050 }, + { DDRC_ZQCTL0(0), 0xc3200018 }, + { DDRC_ZQCTL1(0), 0x028061a8 }, + { DDRC_ZQCTL2(0), 0 }, + { DDRC_DFITMG0(0), 0x0497820a }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xe0400018 }, + { DDRC_DFIUPD1(0), 0x00df00e4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x11 }, + { DDRC_DFITMG2(0), 0x170a }, + { DDRC_DBICTL(0), 1 }, + { DDRC_DFIPHYMSTR(0), 1 }, + { DDRC_RANKCTL(0), 0x0639 }, + { DDRC_DRAMTMG2(0), 0x070e1617 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 }, + { DDRC_ADDRMAP3(0), 0 }, + /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x1f1f }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 }, + { DDRC_ADDRMAP7(0), 0x0f0f }, + { DDRC_FREQ1_DERATEEN(0), 1 }, + { DDRC_FREQ1_DERATEINT(0), 0xd0c0 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x0014002f }, + { DDRC_FREQ1_INIT3(0), 0x00940009 }, + { DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0016004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x0003040b }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0301 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x00020300 }, + { DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x31 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ1_DFITMG2(0), 0x0502 }, + { DDRC_ODTMAP(0), 0 }, + { DDRC_SCHED(0), 0x29001505 }, + { DDRC_SCHED1(0), 0x2c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + { DDRC_PERFLPR1(0), 0x90000096 }, + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x16 }, + { DDRC_DBG1(0), 0 }, + { DDRC_DBGCMD(0), 0 }, + { DDRC_SWCTL(0), 1 }, + { DDRC_POISONCFG(0), 0x11 }, + { DDRC_PCCFG(0), 0x0111 }, + { DDRC_PCFGR_0(0), 0x10f3 }, + { DDRC_PCFGW_0(0), 0x72ff }, + { DDRC_PCTRL_0(0), 1 }, + { DDRC_PCFGQOS0_0(0), 0x0e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + { DDRC_PCFGWQOS0_0(0), 0x0e00 }, + { DDRC_PCFGWQOS1_0(0), 0xffff }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x100a0, 0 }, + { 0x100a1, 1 }, + { 0x100a2, 2 }, + { 0x100a3, 3 }, + { 0x100a4, 4 }, + { 0x100a5, 5 }, + { 0x100a6, 6 }, + { 0x100a7, 7 }, + { 0x110a0, 0 }, + { 0x110a1, 1 }, + { 0x110a2, 2 }, + { 0x110a3, 3 }, + { 0x110a4, 4 }, + { 0x110a5, 5 }, + { 0x110a6, 6 }, + { 0x110a7, 7 }, + { 0x120a0, 0 }, + { 0x120a1, 1 }, + { 0x120a2, 2 }, + { 0x120a3, 3 }, + { 0x120a4, 4 }, + { 0x120a5, 5 }, + { 0x120a6, 6 }, + { 0x120a7, 7 }, + { 0x130a0, 0 }, + { 0x130a1, 1 }, + { 0x130a2, 2 }, + { 0x130a3, 3 }, + { 0x130a4, 4 }, + { 0x130a5, 5 }, + { 0x130a6, 6 }, + { 0x130a7, 7 }, + { 0x1005f, 0x01ff }, + { 0x1015f, 0x01ff }, + { 0x1105f, 0x01ff }, + { 0x1115f, 0x01ff }, + { 0x1205f, 0x01ff }, + { 0x1215f, 0x01ff }, + { 0x1305f, 0x01ff }, + { 0x1315f, 0x01ff }, + { 0x11005f, 0x01ff }, + { 0x11015f, 0x01ff }, + { 0x11105f, 0x01ff }, + { 0x11115f, 0x01ff }, + { 0x11205f, 0x01ff }, + { 0x11215f, 0x01ff }, + { 0x11305f, 0x01ff }, + { 0x11315f, 0x01ff }, + { 0x0055, 0x01ff }, + { 0x1055, 0x01ff }, + { 0x2055, 0x01ff }, + { 0x3055, 0x01ff }, + { 0x4055, 0x01ff }, + { 0x5055, 0x01ff }, + { 0x6055, 0x01ff }, + { 0x7055, 0x01ff }, + { 0x8055, 0x01ff }, + { 0x9055, 0x01ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 7 }, + { 0x2002e, 2 }, + { 0x12002e, 1 }, + { 0x90204, 0 }, + { 0x190204, 0 }, + { 0x20024, 0x01ab }, + { 0x2003a, 0 }, + { 0x120024, 0x01ab }, + { 0x2003a, 0 }, + { 0x20056, 3 }, + { 0x120056, 3 }, + { 0x1004d, 0x0e00 }, + { 0x1014d, 0x0e00 }, + { 0x1104d, 0x0e00 }, + { 0x1114d, 0x0e00 }, + { 0x1204d, 0x0e00 }, + { 0x1214d, 0x0e00 }, + { 0x1304d, 0x0e00 }, + { 0x1314d, 0x0e00 }, + { 0x11004d, 0x0e00 }, + { 0x11014d, 0x0e00 }, + { 0x11104d, 0x0e00 }, + { 0x11114d, 0x0e00 }, + { 0x11204d, 0x0e00 }, + { 0x11214d, 0x0e00 }, + { 0x11304d, 0x0e00 }, + { 0x11314d, 0x0e00 }, + { 0x10049, 0x0eba }, + { 0x10149, 0x0eba }, + { 0x11049, 0x0eba }, + { 0x11149, 0x0eba }, + { 0x12049, 0x0eba }, + { 0x12149, 0x0eba }, + { 0x13049, 0x0eba }, + { 0x13149, 0x0eba }, + { 0x110049, 0x0eba }, + { 0x110149, 0x0eba }, + { 0x111049, 0x0eba }, + { 0x111149, 0x0eba }, + { 0x112049, 0x0eba }, + { 0x112149, 0x0eba }, + { 0x113049, 0x0eba }, + { 0x113149, 0x0eba }, + { 0x0043, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 3 }, + { 0x20075, 4 }, + { 0x20050, 0 }, + { 0x20008, 0x0320 }, + { 0x120008, 0xa7 }, + { 0x20088, 9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x05a1 }, + { 0x10143, 0x05a1 }, + { 0x11043, 0x05a1 }, + { 0x11143, 0x05a1 }, + { 0x12043, 0x05a1 }, + { 0x12143, 0x05a1 }, + { 0x13043, 0x05a1 }, + { 0x13143, 0x05a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x05a1 }, + { 0x110143, 0x05a1 }, + { 0x111043, 0x05a1 }, + { 0x111143, 0x05a1 }, + { 0x112043, 0x05a1 }, + { 0x112143, 0x05a1 }, + { 0x113043, 0x05a1 }, + { 0x113143, 0x05a1 }, + { 0x200fa, 1 }, + { 0x1200fa, 1 }, + { 0x20019, 1 }, + { 0x120019, 1 }, + { 0x200f0, 0 }, + { 0x200f1, 0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0 }, + { 0x200f6, 0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0 }, + { 0x2002d, 0 }, + { 0x12002d, 0 }, + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x200ca, 0x0106 }, + { 0x1200ca, 0x0106 }, + { 0x20110, 2 }, + { 0x20111, 3 }, + { 0x20112, 4 }, + { 0x20113, 5 }, + { 0x20114, 0 }, + { 0x20115, 1 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0 }, + { 0x54003, 0x0c80 }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, CH2_LPDDR4_CS }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0 }, + { 0x54002, 1 }, + { 0x54003, 0x029c }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x121f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) }, + { 0x54019, 0x0994 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x0994 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, CH2_LPDDR4_CS }, + { 0x54032, 0x9400 }, + { 0x54033, 0x3109 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0x9400 }, + { 0x54039, 0x3109 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0 }, + { 0x54003, 0x0c80 }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x5400d, 0x0100 }, + { 0x5400f, 0x0100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, CH2_LPDDR4_CS }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x0400 }, + { 0x90002, 0x010e }, + { 0x90003, 0 }, + { 0x90004, 0 }, + { 0x90005, 8 }, + { 0x90029, 0x0b }, + { 0x9002a, 0x0480 }, + { 0x9002b, 0x0109 }, + { 0x9002c, 8 }, + { 0x9002d, 0x0448 }, + { 0x9002e, 0x0139 }, + { 0x9002f, 8 }, + { 0x90030, 0x0478 }, + { 0x90031, 0x0109 }, + { 0x90032, 0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x0109 }, + { 0x90035, 2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x0139 }, + { 0x90038, 0x0f }, + { 0x90039, 0x07c0 }, + { 0x9003a, 0x0139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x0630 }, + { 0x9003d, 0x0159 }, + { 0x9003e, 0x014f }, + { 0x9003f, 0x0630 }, + { 0x90040, 0x0159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x0630 }, + { 0x90043, 0x0149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x0630 }, + { 0x90046, 0x0179 }, + { 0x90047, 8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x0109 }, + { 0x9004a, 0 }, + { 0x9004b, 0x07c8 }, + { 0x9004c, 0x0109 }, + { 0x9004d, 0 }, + { 0x9004e, 1 }, + { 0x9004f, 8 }, + { 0x90050, 0 }, + { 0x90051, 0x045a }, + { 0x90052, 9 }, + { 0x90053, 0 }, + { 0x90054, 0x0448 }, + { 0x90055, 0x0109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x0630 }, + { 0x90058, 0x0179 }, + { 0x90059, 1 }, + { 0x9005a, 0x0618 }, + { 0x9005b, 0x0109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x0630 }, + { 0x9005e, 0x0149 }, + { 0x9005f, 8 }, + { 0x90060, 4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x0630 }, + { 0x90064, 0x0149 }, + { 0x90065, 0 }, + { 0x90066, 4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x0630 }, + { 0x9006a, 0x0149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0 }, + { 0x9006f, 4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x0549 }, + { 0x90072, 0x0630 }, + { 0x90073, 0x0159 }, + { 0x90074, 0x0d49 }, + { 0x90075, 0x0630 }, + { 0x90076, 0x0159 }, + { 0x90077, 0x094a }, + { 0x90078, 0x0630 }, + { 0x90079, 0x0159 }, + { 0x9007a, 0x0441 }, + { 0x9007b, 0x0630 }, + { 0x9007c, 0x0149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x0630 }, + { 0x9007f, 0x0149 }, + { 0x90080, 1 }, + { 0x90081, 0x0630 }, + { 0x90082, 0x0149 }, + { 0x90083, 0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x0109 }, + { 0x90086, 0x0a }, + { 0x90087, 0x10 }, + { 0x90088, 0x0109 }, + { 0x90089, 9 }, + { 0x9008a, 0x03c0 }, + { 0x9008b, 0x0149 }, + { 0x9008c, 9 }, + { 0x9008d, 0x03c0 }, + { 0x9008e, 0x0159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x0109 }, + { 0x90092, 0 }, + { 0x90093, 0x03c0 }, + { 0x90094, 0x0109 }, + { 0x90095, 0x18 }, + { 0x90096, 4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0x0a }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x0109 }, + { 0x9009e, 2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x0109 }, + { 0x900a1, 5 }, + { 0x900a2, 0x07c0 }, + { 0x900a3, 0x0109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x0109 }, + { 0x40000, 0x0811 }, + { 0x40020, 0x0880 }, + { 0x40040, 0 }, + { 0x40060, 0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0 }, + { 0x40003, 0x0811 }, + { 0x40023, 0x0880 }, + { 0x40043, 0 }, + { 0x40063, 0 }, + { 0x40004, 0x0720 }, + { 0x40024, 0x0f }, + { 0x40044, 0x1740 }, + { 0x40064, 0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0 }, + { 0x40006, 0x0716 }, + { 0x40026, 0x0f }, + { 0x40046, 0x2001 }, + { 0x40066, 0 }, + { 0x40007, 0x0716 }, + { 0x40027, 0x0f }, + { 0x40047, 0x2800 }, + { 0x40067, 0 }, + { 0x40008, 0x0716 }, + { 0x40028, 0x0f }, + { 0x40048, 0x0f00 }, + { 0x40068, 0 }, + { 0x40009, 0x0720 }, + { 0x40029, 0x0f }, + { 0x40049, 0x1400 }, + { 0x40069, 0 }, + { 0x4000a, 0x0e08 }, + { 0x4002a, 0x0c15 }, + { 0x4004a, 0 }, + { 0x4006a, 0 }, + { 0x4000b, 0x0623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0 }, + { 0x4006b, 0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0 }, + { 0x4006c, 0 }, + { 0x4000d, 0x0e08 }, + { 0x4002d, 0x0c1a }, + { 0x4004d, 0 }, + { 0x4006d, 0 }, + { 0x4000e, 0x0623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0 }, + { 0x4006e, 0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0 }, + { 0x4006f, 0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0 }, + { 0x40070, 0 }, + { 0x40011, 0x0708 }, + { 0x40031, 5 }, + { 0x40051, 0 }, + { 0x40071, 0x2002 }, + { 0x40012, 8 }, + { 0x40032, 0x80 }, + { 0x40052, 0 }, + { 0x40072, 0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0 }, + { 0x40073, 0 }, + { 0x40014, 0x0708 }, + { 0x40034, 0x0a }, + { 0x40054, 0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0 }, + { 0x40075, 0 }, + { 0x40016, 0x060a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0 }, + { 0x40017, 0x061a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0 }, + { 0x40018, 0x060a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0 }, + { 0x40019, 0x0642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x0880 }, + { 0x4005a, 0 }, + { 0x4007a, 0 }, + { 0x900a7, 0 }, + { 0x900a8, 0x0790 }, + { 0x900a9, 0x011a }, + { 0x900aa, 8 }, + { 0x900ab, 0x07aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x07b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0 }, + { 0x900b1, 0x07c8 }, + { 0x900b2, 0x0109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x02a8 }, + { 0x900b5, 0x0129 }, + { 0x900b6, 8 }, + { 0x900b7, 0x0370 }, + { 0x900b8, 0x0129 }, + { 0x900b9, 0x0a }, + { 0x900ba, 0x03c8 }, + { 0x900bb, 0x01a9 }, + { 0x900bc, 0x0c }, + { 0x900bd, 0x0408 }, + { 0x900be, 0x0199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x0790 }, + { 0x900c1, 0x011a }, + { 0x900c2, 8 }, + { 0x900c3, 4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0x0e }, + { 0x900c6, 0x0408 }, + { 0x900c7, 0x0199 }, + { 0x900c8, 8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x0108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x0790 }, + { 0x900cd, 0x016a }, + { 0x900ce, 8 }, + { 0x900cf, 0x01d8 }, + { 0x900d0, 0x0169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x0168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x0788 }, + { 0x900d6, 0x016a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x01e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x0798 }, + { 0x900dc, 0x016a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x07a0 }, + { 0x900df, 0x016a }, + { 0x900e0, 8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x0168 }, + { 0x900e3, 8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x0168 }, + { 0x900e6, 0x0a }, + { 0x900e7, 0x0408 }, + { 0x900e8, 0x0169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0 }, + { 0x900ed, 0x0408 }, + { 0x900ee, 0x0169 }, + { 0x900ef, 0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x0168 }, + { 0x900f2, 0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x0168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x01e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x0798 }, + { 0x900fa, 0x016a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x07a0 }, + { 0x900fd, 0x016a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x0790 }, + { 0x90100, 0x016a }, + { 0x90101, 8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x0168 }, + { 0x90104, 8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x0168 }, + { 0x90107, 0x0a }, + { 0x90108, 0x0408 }, + { 0x90109, 0x0169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0 }, + { 0x9010e, 0x0408 }, + { 0x9010f, 0x0169 }, + { 0x90110, 0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x0168 }, + { 0x90113, 0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x0168 }, + { 0x90116, 0 }, + { 0x90117, 0x01d8 }, + { 0x90118, 0x0169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x0790 }, + { 0x9011b, 0x016a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x07aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0x0a }, + { 0x90120, 0 }, + { 0x90121, 0x01e9 }, + { 0x90122, 8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x0108 }, + { 0x90125, 0x0f }, + { 0x90126, 0x0408 }, + { 0x90127, 0x0169 }, + { 0x90128, 0x0c }, + { 0x90129, 0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 9 }, + { 0x9012c, 0 }, + { 0x9012d, 0x01a9 }, + { 0x9012e, 0 }, + { 0x9012f, 0x0408 }, + { 0x90130, 0x0169 }, + { 0x90131, 0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x0108 }, + { 0x90134, 8 }, + { 0x90135, 0x07aa }, + { 0x90136, 0x6a }, + { 0x90137, 0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x0108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x0790 }, + { 0x9013c, 0x016a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0 }, + { 0x9013f, 0x68 }, + { 0x90140, 8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x0168 }, + { 0x90143, 0x0f }, + { 0x90144, 0x0408 }, + { 0x90145, 0x0169 }, + { 0x90146, 0x0c }, + { 0x90147, 0 }, + { 0x90148, 0x68 }, + { 0x90149, 0 }, + { 0x9014a, 0x0408 }, + { 0x9014b, 0x0169 }, + { 0x9014c, 0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x0168 }, + { 0x9014f, 8 }, + { 0x90150, 0x03c8 }, + { 0x90151, 0x01a9 }, + { 0x90152, 3 }, + { 0x90153, 0x0370 }, + { 0x90154, 0x0129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x02aa }, + { 0x90157, 9 }, + { 0x90158, 0 }, + { 0x90159, 0x0400 }, + { 0x9015a, 0x010e }, + { 0x9015b, 8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x0109 }, + { 0x9015e, 0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x010c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x010c }, + { 0x90164, 8 }, + { 0x90165, 0x07c8 }, + { 0x90166, 0x0101 }, + { 0x90167, 8 }, + { 0x90168, 0 }, + { 0x90169, 8 }, + { 0x9016a, 8 }, + { 0x9016b, 0x0448 }, + { 0x9016c, 0x0109 }, + { 0x9016d, 0x0f }, + { 0x9016e, 0x07c0 }, + { 0x9016f, 0x0109 }, + { 0x90170, 0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x0109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x0630 }, + { 0x90175, 0x0109 }, + { 0x90176, 8 }, + { 0x90177, 0x0618 }, + { 0x90178, 0x0109 }, + { 0x90179, 8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x0109 }, + { 0x9017c, 0 }, + { 0x9017d, 0x07c8 }, + { 0x9017e, 0x0109 }, + { 0x9017f, 8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x010c }, + { 0x90182, 0 }, + { 0x90183, 1 }, + { 0x90184, 8 }, + { 0x90185, 8 }, + { 0x90186, 4 }, + { 0x90187, 8 }, + { 0x90188, 8 }, + { 0x90189, 0x07c8 }, + { 0x9018a, 0x0101 }, + { 0x90006, 0 }, + { 0x90007, 0 }, + { 0x90008, 8 }, + { 0x90009, 0 }, + { 0x9000a, 0 }, + { 0x9000b, 0 }, + { 0xd00e7, 0x0400 }, + { 0x90017, 0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0 }, + { 0x400d1, 0x0101 }, + { 0x400d2, 0x0105 }, + { 0x400d3, 0x0107 }, + { 0x400d4, 0x010f }, + { 0x400d5, 0x0202 }, + { 0x400d6, 0x020a }, + { 0x400d7, 0x020b }, + { 0x2003a, 2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x07d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x01a1 }, + { 0x12000e, 0x10 }, + { 0x9000c, 0 }, + { 0x9000d, 0x0173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x400fd, 0x0f }, + { 0x10011, 1 }, + { 0x10012, 1 }, + { 0x10013, 0x0180 }, + { 0x10018, 1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 1 }, + { 0x101b4, 1 }, + { 0x102b4, 1 }, + { 0x103b4, 1 }, + { 0x104b4, 1 }, + { 0x105b4, 1 }, + { 0x106b4, 1 }, + { 0x107b4, 1 }, + { 0x108b4, 1 }, + { 0x11011, 1 }, + { 0x11012, 1 }, + { 0x11013, 0x0180 }, + { 0x11018, 1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 1 }, + { 0x111b4, 1 }, + { 0x112b4, 1 }, + { 0x113b4, 1 }, + { 0x114b4, 1 }, + { 0x115b4, 1 }, + { 0x116b4, 1 }, + { 0x117b4, 1 }, + { 0x118b4, 1 }, + { 0x12011, 1 }, + { 0x12012, 1 }, + { 0x12013, 0x0180 }, + { 0x12018, 1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 1 }, + { 0x121b4, 1 }, + { 0x122b4, 1 }, + { 0x123b4, 1 }, + { 0x124b4, 1 }, + { 0x125b4, 1 }, + { 0x126b4, 1 }, + { 0x127b4, 1 }, + { 0x128b4, 1 }, + { 0x13011, 1 }, + { 0x13012, 1 }, + { 0x13013, 0x0180 }, + { 0x13018, 1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 1 }, + { 0x131b4, 1 }, + { 0x132b4, 1 }, + { 0x133b4, 1 }, + { 0x134b4, 1 }, + { 0x135b4, 1 }, + { 0x136b4, 1 }, + { 0x137b4, 1 }, + { 0x138b4, 1 }, + { 0x2003a, 2 }, + { 0xc0080, 2 }, + { 0xd0000, 1 } +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_ch2 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 667, }, +}; diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h new file mode 100644 index 00000000000..a55086bb5e2 --- /dev/null +++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h @@ -0,0 +1,95 @@ +/* + * Copyright Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <config.h> +#include <linux/kernel.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +/* MNT Reform2 */ +#define CFG_DDR_MB 4096 +#define CFG_DDR_RANK_BITS 1 +#define CFG_DDR_CHANNEL_CNT 2 + +#ifdef WR_POST_EXT_3200 +#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008) +#else +#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 8) +#endif + +#if CFG_DDR_MB == 1024 + /* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F +#define CH2_VAL_DDRC_ADDRMAP6_R0 0x0F070707 + +#elif CFG_DDR_MB == 2048 + /* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F +#define CH2_VAL_DDRC_ADDRMAP6_R0 0x07070707 + /* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000016 +#define CH2_VAL_DDRC_ADDRMAP6_R1 0x0F070707 + +#elif CFG_DDR_MB == 3072 + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000015 +#define CH2_VAL_DDRC_ADDRMAP6_R1 0x48080707 + +#elif CFG_DDR_MB == 4096 + /* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000017 +#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707 +#else +#error unsupported memory size +#endif + +#define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */ +#define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */ + +#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#ifdef CH2_VAL_DDRC_ADDRMAP0_R0 +#define CH2_LPDDR4_CS LPDDR4_CS_R0 +#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R0 +#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R0 +#else +#error unsupported memory rank/size +#endif +/* + * rank0 will succeed, even if really rank 1, so we need + * to probe memory if rank0 succeeds + */ +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R1 +#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R1 +#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R1 +#endif + +#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0) +#ifdef CH2_VAL_DDRC_ADDRMAP0_R1 +#define CH2_LPDDR4_CS LPDDR4_CS_R1 +#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R1 +#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R1 +#else +#error unsupported memory rank/size +#endif + +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R0 +#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R0 +#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R0 +#endif + +#else +#error unsupported rank bits +#endif + +#if (CFG_DDR_CHANNEL_CNT == 2) +#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0) +#error unsupported options +#endif +#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#error unsupported options +#endif +#endif diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c new file mode 100644 index 00000000000..21fad4972ab --- /dev/null +++ b/board/mntre/imx8mq_reform2/spl.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <linux/delay.h> +#include <power/pmic.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_ch2; + +static void spl_dram_init(void) +{ + ddr_init(&dram_timing_ch2); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_VSEL IMX_GPIO_NR(1, 8) +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_VSEL, "usdhc2_vsel"); + gpio_direction_output(USDHC2_VSEL, 0); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4) +#define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24) +#define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11) +#define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20) + +#define I2C_MUX_ADDR 0x70 +#define I2C_FAN53555_ADDR 0x60 + +static iomux_v3_cfg_t const power_pads[] = { + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46), +}; + +int power_init_board(void) +{ + uint8_t val; + + imx_iomux_v3_setup_multiple_pads(power_pads, + ARRAY_SIZE(usdhc2_pads)); + + /* Release I2C multiplexer reset */ + gpio_request(I2C1_PCA9546_RESET, "pca9546_reset"); + gpio_direction_output(I2C1_PCA9546_RESET, 1); + + /* Select VSEL0 on voltage regulators */ + gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel"); + gpio_direction_output(ARM_DRAM_VSEL, 0); + gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel"); + gpio_direction_output(DRAM_1P1_VSEL, 0); + gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel"); + gpio_direction_output(SOC_GPU_VPU_VSEL, 0); + + /* Set mux to target ARM/DRAM regulator */ + i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0); + /* .6 + .40 = 1.00 */ + val = 0x80 + 40; + i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1); + i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1); + + /* Set mux to target DRAM regulator */ + i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0); + /* .6 + .50 = 1.10 */ + val = 0x80 + 50; + i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1); + i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1); + + /* Set mux to target SoC/GPU/VPU regulator */ + i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0); + /* .6 + .30 = .90 */ + val = 0x80 + 30; + i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1); + i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1); + + /* Set mux to target peripherals */ + i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0); + + return 0; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile index 0abefdaf365..fe585ad2631 100644 --- a/board/qualcomm/dragonboard845c/Makefile +++ b/board/qualcomm/dragonboard845c/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> # # This empty file prevents make error. -# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far. +# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for dragonboard845c so far. # obj-y += dragonboard845c.o diff --git a/board/samsung/starqltechn/Makefile b/board/samsung/starqltechn/Makefile index c38c0b47109..e017c827a78 100644 --- a/board/samsung/starqltechn/Makefile +++ b/board/samsung/starqltechn/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> # # This empty file prevents make error. -# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for starqltechn so far. +# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for starqltechn so far. # obj-y += starqltechn.o diff --git a/board/skyworth/hc2910-2aghd05/Kconfig b/board/skyworth/hc2910-2aghd05/Kconfig new file mode 100644 index 00000000000..f85f1f2631d --- /dev/null +++ b/board/skyworth/hc2910-2aghd05/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HC2910_2AGHD05 + +config SYS_BOARD + default "hc2910-2aghd05" + +config SYS_VENDOR + default "skyworth" + +config SYS_SOC + default "hi3798mv200" + +config SYS_CONFIG_NAME + default "hc2910-2aghd05" + +endif diff --git a/board/skyworth/hc2910-2aghd05/MAINTAINERS b/board/skyworth/hc2910-2aghd05/MAINTAINERS new file mode 100644 index 00000000000..2c1e750018e --- /dev/null +++ b/board/skyworth/hc2910-2aghd05/MAINTAINERS @@ -0,0 +1,6 @@ +HC2910 2AGHD05 BOARD +M: Yang Xiwen <firbidden405@outlook.com> +S: Maintained +F: board/skyworth/hc2910-2aghd05 +F: include/configs/hc2910-2aghd05.h +F: configs/hc2910_2aghd05_defconfig diff --git a/board/skyworth/hc2910-2aghd05/Makefile b/board/skyworth/hc2910-2aghd05/Makefile new file mode 100644 index 00000000000..193fd158fe3 --- /dev/null +++ b/board/skyworth/hc2910-2aghd05/Makefile @@ -0,0 +1 @@ +obj-y := hc2910-2aghd05.o diff --git a/board/skyworth/hc2910-2aghd05/README b/board/skyworth/hc2910-2aghd05/README new file mode 100644 index 00000000000..a838956e59a --- /dev/null +++ b/board/skyworth/hc2910-2aghd05/README @@ -0,0 +1,25 @@ +================================================================================ + Board Information +================================================================================ + +The board features the Hi3798M V200 with an integrated quad-core 64-bit ARM +Cortex A53 processor. +SOC Hisilicon Hi3798CV200 +CPU Quad-core ARM Cortex-A53 64 bit +DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB +USB 1x USB 2.0 ports 1x USB 3.0 ports +CONSOLE USB-micro port for console support +ETHERNET 1 GBe Ethernet, 1 MBe Ethernet +WIFI 802.11n with Bluebooth +CONNECTORS One connector for Smart Card One connector for TSI + + +================================================================================ + BUILD INSTRUCTIONS +================================================================================ + +The U-Boot relies on a modified l-loader and TF-A for Hi3798MV200. +The source for l-loader can be obtained at: [l-loader](https://github.com/185264646/l-loader) +The mainline port for TF-A is still under development. For now, you can use the TF-A for poplar directly. + +For more information, please refer to <board/hisilicon/poplar/README>. diff --git a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c new file mode 100644 index 00000000000..abad5efdafb --- /dev/null +++ b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for Skyworth HC2910 2AGHD05 + */ + +#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <asm/system.h> +#include <linux/io.h> + +#define HI3798MV200_PERI_CTRL_BASE 0xf8a20000 +#define SDIO0_LDO_OFFSET 0x11c + +static int sdio0_set_ldo(void) +{ + // SDIO LDO bypassed, 3.3V + writel(HI3798MV200_PERI_CTRL_BASE + SDIO0_LDO_OFFSET, 0x60); + return 0; +} + +int board_init(void) +{ + sdio0_set_ldo(); + return 0; +} diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig index d8f24695d0d..390214c285b 100644 --- a/board/storopack/smegw01/Kconfig +++ b/board/storopack/smegw01/Kconfig @@ -12,4 +12,11 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/storopack/smegw01/imximage.cfg" +config SYS_BOOT_LOCKED + bool "Lock boot process to EMMC" + default y + help + Say N here if you want to boot from eMMC and SD. + Say Y to boot from eMMC. + endif diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c index e6bff80e556..20c09700bf0 100644 --- a/board/storopack/smegw01/smegw01.c +++ b/board/storopack/smegw01/smegw01.c @@ -14,9 +14,11 @@ #include <asm/io.h> #include <common.h> #include <env.h> +#include <env_internal.h> #include <asm/arch/crm_regs.h> #include <asm/setup.h> #include <asm/bootm.h> +#include <mmc.h> DECLARE_GLOBAL_DATA_PTR; @@ -80,6 +82,7 @@ int board_init(void) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + unsigned char eth1addr[6]; imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); @@ -91,5 +94,35 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); + /* Get the second MAC address */ + imx_get_mac_from_fuse(1, eth1addr); + if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) + eth_env_set_enetaddr("eth1addr", eth1addr); + return 0; } + +uint board_mmc_get_env_part(struct mmc *mmc) +{ + uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == 7) + part = 0; + return part; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_MMC; + + switch (prio) { + case 0: + return ENVL_NOWHERE; + + case 1: + return ENVL_MMC; + } + + return ENVL_UNKNOWN; +} diff --git a/board/storopack/smegw01/smegw01.env b/board/storopack/smegw01/smegw01.env new file mode 100644 index 00000000000..25bc7cdbd28 --- /dev/null +++ b/board/storopack/smegw01/smegw01.env @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +#ifdef CONFIG_SYS_BOOT_LOCKED +#define SETUP_BOOT_MENU setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd +#else +#define SETUP_BOOT_MENU setup_boot_menu= \ + if test "${mmcdev}" = 1; then \ + setenv emmc_priority 0; \ + setenv sd_priority 1; \ + else setenv emmc_priority 1; \ + setenv sd_priority 0; \ + fi; \ + setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \ + setenv bootmenu_${sd_priority} SD=run boot_sd; +#endif + +altbootcmd= + echo Performing rollback...; + if test "${mmcpart_committed}" = 1; then + setenv mmcpart 2; + setenv mmcpart_committed 2; + else + setenv mmcpart 1; + setenv mmcpart_committed 1; + fi; + setenv bootcount 0; + setenv upgrade_available; + setenv ustate 3; + saveenv; + run bootcmd; +boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd; +boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd; +bootcmd=run finduuid; run distro_bootcmd +bootdelay=2 +bootlimit=3 +bootm_size=0x10000000 +commit_mmc= + if test "${ustate}" = 1 -a "${mmcpart}" != "${mmcpart_committed}"; then + setenv mmcpart_committed ${mmcpart}; + saveenv; + fi; +console=ttymxc0 +fdt_addr=0x83000000 +fdtfile=imx7d-smegw01.dtb +fit_addr=0x88000000 +image=fitImage +loadaddr=0x80800000 +loadbootpart=mmc partconf 1 boot_part +loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} boot/${image} +loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed} +mmcargs= + setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part} +mmcboot= + echo Booting...; + echo mmcdev: ${mmcdev}; + run commit_mmc; + echo mmcpart: ${mmcpart_committed}; + run loadpart; + echo gptpart: ${gpt_partition_entry}; + run loadbootpart; + if run loadimage; then + ; + else + run altbootcmd; + fi; + run mmcargs; + if bootm ${fit_addr}; then + ; + else + run altbootcmd; + fi; +mmcdev=1 +mmcpart=1 +mmcpart_committed=1 +persist_mmcdev= + if test "${mmcdev}" != "${mmcdev_wanted}"; then + setenv mmcdev "${mmcdev_wanted}"; + saveenv; + fi; +setup_boot_menu= + if test "${mmcdev}" = 1; then + setenv emmc_priority 0; + setenv sd_priority 1; + else + setenv emmc_priority 1; + setenv sd_priority 0; + fi; + setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; + setenv bootmenu_${sd_priority} SD=run boot_sd; +SETUP_BOOT_MENU diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 034fbed3aa4..e00e42e276c 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -19,9 +19,15 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPLASH_SCREEN +#if CONFIG_IS_ENABLED(SPLASH_SCREEN) static struct splash_location default_splash_locations[] = { { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .flags = SPLASH_STORAGE_RAW, + .offset = 0x700000, + }, + { .name = "mmc", .storage = SPLASH_STORAGE_MMC, .flags = SPLASH_STORAGE_FS, diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 09d26883f19..8eaca9d5af2 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -153,6 +153,135 @@ static void setup_serial(void) snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial); env_set("serial#", serial_string); } + +/* + * Declaration of daughtercards to probe. Note that when adding more + * cards they should be grouped by the 'i2c_addr' field to allow for a + * more efficient probing process. + */ +static const struct { + u8 i2c_addr; /* I2C address of card EEPROM */ + char *card_name; /* EEPROM-programmed card name */ + char *dtbo_name; /* Device tree overlay to apply */ + u8 eth_offset; /* ethXaddr MAC address index offset */ +} ext_cards[] = { + { + 0x52, + "J7X-GESI-EXP", + "k3-j721s2-gesi-exp-board.dtbo", + 1, /* Start populating from eth1addr */ + }, +}; + +#define DAUGHTER_CARD_NO_OF_MAC_ADDR 5 +static bool daughter_card_detect_flags[ARRAY_SIZE(ext_cards)]; + +static int probe_daughtercards(void) +{ + char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN]; + bool eeprom_read_success; + struct ti_am6_eeprom ep; + u8 previous_i2c_addr; + u8 mac_addr_cnt; + int i; + int ret; + + /* Mark previous I2C address variable as not populated */ + previous_i2c_addr = 0xff; + + /* No EEPROM data was read yet */ + eeprom_read_success = false; + + /* Iterate through list of daughtercards */ + for (i = 0; i < ARRAY_SIZE(ext_cards); i++) { + /* Obtain card-specific I2C address */ + u8 i2c_addr = ext_cards[i].i2c_addr; + + /* Read card EEPROM if not already read previously */ + if (i2c_addr != previous_i2c_addr) { + /* Store I2C address so we can avoid reading twice */ + previous_i2c_addr = i2c_addr; + + /* Get and parse the daughter card EEPROM record */ + ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS, + i2c_addr, + &ep, + (char **)mac_addr, + DAUGHTER_CARD_NO_OF_MAC_ADDR, + &mac_addr_cnt); + if (ret) { + debug("%s: No daughtercard EEPROM at 0x%02x found %d\n", + __func__, i2c_addr, ret); + eeprom_read_success = false; + /* Skip to the next daughtercard to probe */ + continue; + } + + /* EEPROM read successful, okay to further process. */ + eeprom_read_success = true; + } + + /* Only continue processing if EEPROM data was read */ + if (!eeprom_read_success) + continue; + + /* Only process the parsed data if we found a match */ + if (strncmp(ep.name, ext_cards[i].card_name, sizeof(ep.name))) + continue; + + printf("Detected: %s rev %s\n", ep.name, ep.version); + daughter_card_detect_flags[i] = true; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + int j; + /* + * Populate any MAC addresses from daughtercard into the U-Boot + * environment, starting with a card-specific offset so we can + * have multiple ext_cards contribute to the MAC pool in a well- + * defined manner. + */ + for (j = 0; j < mac_addr_cnt; j++) { + if (!is_valid_ethaddr((u8 *)mac_addr[j])) + continue; + + eth_env_set_enetaddr_by_index("eth", ext_cards[i].eth_offset + j, + (uchar *)mac_addr[j]); + } + } + } + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + char name_overlays[1024] = { 0 }; + + for (i = 0; i < ARRAY_SIZE(ext_cards); i++) { + if (!daughter_card_detect_flags[i]) + continue; + + /* Skip if no overlays are to be added */ + if (!strlen(ext_cards[i].dtbo_name)) + continue; + + /* + * Make sure we are not running out of buffer space by checking + * if we can fit the new overlay, a trailing space to be used + * as a separator, plus the terminating zero. + */ + if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 > + sizeof(name_overlays)) + return -ENOMEM; + + /* Append to our list of overlays */ + strcat(name_overlays, ext_cards[i].dtbo_name); + strcat(name_overlays, " "); + } + + /* Apply device tree overlay(s) to the U-Boot environment, if any */ + if (strlen(name_overlays)) + return env_set("name_overlays", name_overlays); + } + + return 0; +} #endif /* @@ -182,6 +311,7 @@ int board_late_init(void) if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) { setup_board_eeprom_env(); setup_serial(); + probe_daughtercards(); } return 0; diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig deleted file mode 100644 index aa138445444..00000000000 --- a/board/ti/omap5_uevm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP5_UEVM - -config SYS_BOARD - default "omap5_uevm" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "omap5_uevm" - -endif diff --git a/board/ti/omap5_uevm/MAINTAINERS b/board/ti/omap5_uevm/MAINTAINERS deleted file mode 100644 index ce544828f84..00000000000 --- a/board/ti/omap5_uevm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -OMAP5_UEVM BOARD -M: Tom Rini <trini@konsulko.com> -S: Maintained -F: board/ti/omap5_uevm/ -F: include/configs/omap5_uevm.h -F: configs/omap5_uevm_defconfig diff --git a/board/ti/omap5_uevm/Makefile b/board/ti/omap5_uevm/Makefile deleted file mode 100644 index 17ee516d262..00000000000 --- a/board/ti/omap5_uevm/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := evm.o diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README deleted file mode 100644 index 970e2eceb77..00000000000 --- a/board/ti/omap5_uevm/README +++ /dev/null @@ -1,25 +0,0 @@ -Summary -======= - -This document covers various features of the 'omap5_uevm' build and some -related uses. - -eMMC boot partition use -======================= - -It is possible, depending on SYSBOOT configuration to boot from the eMMC -boot partitions using (name depending on documentation referenced) -Alternative Boot operation mode or Boot Sequence Option 1/2. In this -example we load MLO and u-boot.img from the build into DDR and then use -'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to -set boot0 as the boot device. -U-Boot # setenv autoload no -U-Boot # usb start -U-Boot # dhcp -U-Boot # mmc dev 1 1 -U-Boot # tftp ${loadaddr} omap5uevm/MLO -U-Boot # mmc write ${loadaddr} 0 100 -U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img -U-Boot # mmc write ${loadaddr} 300 400 -U-Boot # mmc bootbus 1 2 0 2 -U-Boot # mmc partconf 1 1 1 0 diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c deleted file mode 100644 index 09cbd6bf719..00000000000 --- a/board/ti/omap5_uevm/evm.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * Steve Sakoman <steve@sakoman.com> - */ -#include <common.h> -#include <init.h> -#include <net.h> -#include <palmas.h> -#include <asm/arch/omap.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mmc_host_def.h> -#include <serial.h> -#include <tca642x.h> -#include <usb.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/usb/gadget.h> -#include <dwc3-uboot.h> -#include <dwc3-omap-uboot.h> -#include <ti-usb-phy-uboot.h> - -#include "mux_data.h" - -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP) -#include <sata.h> -#include <usb.h> -#include <asm/gpio.h> -#include <asm/mach-types.h> -#include <asm/arch/clock.h> -#include <asm/arch/ehci.h> -#include <asm/ehci-omap.h> -#include <asm/arch/sata.h> - -#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) -#define DIE_ID_REG_OFFSET 0x200 - -#endif - -DECLARE_GLOBAL_DATA_PTR; - -const struct omap_sysinfo sysinfo = { - "Board: OMAP5432 uEVM\n" -}; - -/** - * @brief tca642x_init - uEVM default values for the GPIO expander - * input reg, output reg, polarity reg, configuration reg - */ -struct tca642x_bank_info tca642x_init[] = { - { .input_reg = 0x00, - .output_reg = 0x04, - .polarity_reg = 0x00, - .configuration_reg = 0x80 }, - { .input_reg = 0x00, - .output_reg = 0x00, - .polarity_reg = 0x00, - .configuration_reg = 0xff }, - { .input_reg = 0x00, - .output_reg = 0x00, - .polarity_reg = 0x00, - .configuration_reg = 0x40 }, -}; - -#ifdef CONFIG_USB_DWC3 -static struct dwc3_device usb_otg_ss = { - .maximum_speed = USB_SPEED_SUPER, - .base = OMAP5XX_USB_OTG_SS_BASE, - .tx_fifo_resize = false, - .index = 0, -}; - -static struct dwc3_omap_device usb_otg_ss_glue = { - .base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE, - .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, - .index = 0, -}; - -static struct ti_usb_phy_device usb_phy_device = { - .pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL, - .usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER, - .usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER, - .index = 0, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - if (index) { - printf("Invalid Controller Index\n"); - return -EINVAL; - } - - if (init == USB_INIT_DEVICE) { - usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL; - usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; - } - - enable_usb_clocks(index); - ti_usb_phy_uboot_init(&usb_phy_device); - dwc3_omap_uboot_init(&usb_otg_ss_glue); - dwc3_uboot_init(&usb_otg_ss); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - if (index) { - printf("Invalid Controller Index\n"); - return -EINVAL; - } - - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); - disable_usb_clocks(index); - - return 0; -} - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif - -/** - * @brief board_init - * - * Return: 0 - */ -int board_init(void) -{ - gpmc_init(); - gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; - gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ - - tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init); - - return 0; -} - -#if defined(CONFIG_SPL_OS_BOOT) -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; - - return 0; -} -#endif /* CONFIG_SPL_OS_BOOT */ - -int board_eth_init(struct bd_info *bis) -{ - return 0; -} - -/** - * @brief misc_init_r - Configure EVM board specific configurations - * such as power configurations, ethernet initialization as phase2 of - * boot sequence - * - * Return: 0 - */ -int misc_init_r(void) -{ -#ifdef CONFIG_PALMAS_POWER - palmas_init_settings(); -#endif - - omap_die_id_usbethaddr(); - - return 0; -} - -void set_muxconf_regs(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_essential, - sizeof(wkup_padconf_array_essential) / - sizeof(struct pad_conf_entry)); -} - -#if defined(CONFIG_MMC) -int board_mmc_init(struct bd_info *bis) -{ - omap_mmc_init(0, 0, 0, -1, -1); - omap_mmc_init(1, 0, 0, -1, -1); - return 0; -} -#endif - -#ifdef CONFIG_USB_XHCI_OMAP -/** - * @brief board_usb_init - Configure EVM board specific configurations - * for the LDO's and clocks for the USB blocks. - * - * Return: 0 - */ -int board_usb_init(int index, enum usb_init_type init) -{ - int ret; -#ifdef CONFIG_PALMAS_USB_SS_PWR - ret = palmas_enable_ss_ldo(); -#endif - - return 0; -} -#endif diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h deleted file mode 100644 index 3c4ba474977..00000000000 --- a/board/ti/omap5_uevm/mux_data.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated, <www.ti.com> - * - * Sricharan R <r.sricharan@ti.com> - */ -#ifndef _EVM5430_MUX_DATA_H -#define _EVM5430_MUX_DATA_H - -#include <asm/arch/mux_omap5.h> - -const struct pad_conf_entry core_padconf_array_essential[] = { - - {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ - {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ - {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ - {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ - {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ - {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ - {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ - {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ - {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ - {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ - {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ - {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ - {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/ - {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/ - {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/ - {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ - {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ - {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ - {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ - {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ - {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ - {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ - {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ - {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ - {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ - {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ - {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */ -}; - -const struct pad_conf_entry wkup_padconf_array_essential[] = { - - {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ - {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ - {SYS_32K, (IEN | M0)}, /* SYS_32K */ - {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ - -}; - -#endif /* _EVM4430_MUX_DATA_H */ diff --git a/boot/Kconfig b/boot/Kconfig index d95a2a70266..8c27f52ec3e 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -231,7 +231,7 @@ config SPL_LOAD_FIT_APPLY_OVERLAY depends on SPL_LOAD_FIT select OF_LIBFDT_OVERLAY help - The device tree is loaded from the FIT image. Allow the SPL is to + The device tree is loaded from the FIT image. Allow the SPL to also load device-tree overlays from the FIT image an apply them over the device tree. diff --git a/boot/bootmeth_distro.c b/boot/bootmeth_distro.c index 356929828b9..b4b73ecbf58 100644 --- a/boot/bootmeth_distro.c +++ b/boot/bootmeth_distro.c @@ -150,7 +150,7 @@ static int distro_boot(struct udevice *dev, struct bootflow *bflow) info.dev = dev; info.bflow = bflow; ret = pxe_setup_ctx(&ctx, &cmdtp, distro_getfile, &info, true, - bflow->subdir); + bflow->subdir, false); if (ret) return log_msg_ret("ctx", -EINVAL); diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index ecf8557af83..5a8af2bbd0b 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -70,7 +70,7 @@ static int distro_pxe_read_bootflow(struct udevice *dev, struct bootflow *bflow) addr = simple_strtoul(addr_str, NULL, 16); log_debug("calling pxe_get()\n"); - ret = pxe_get(addr, &bootdir, &size); + ret = pxe_get(addr, &bootdir, &size, false); log_debug("pxe_get() returned %d\n", ret); if (ret) return log_msg_ret("pxeb", ret); @@ -146,7 +146,7 @@ static int distro_pxe_boot(struct udevice *dev, struct bootflow *bflow) info.bflow = bflow; info.cmdtp = &cmdtp; ret = pxe_setup_ctx(ctx, &cmdtp, distro_pxe_getfile, &info, false, - bflow->subdir); + bflow->subdir, false); if (ret) return log_msg_ret("ctx", -EINVAL); diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 3a1e50f2b1b..d13c47dd942 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -1578,7 +1578,7 @@ void handle_pxe_menu(struct pxe_context *ctx, struct pxe_menu *cfg) int pxe_setup_ctx(struct pxe_context *ctx, struct cmd_tbl *cmdtp, pxe_getfile_func getfile, void *userdata, - bool allow_abs_path, const char *bootfile) + bool allow_abs_path, const char *bootfile, bool use_ipv6) { const char *last_slash; size_t path_len = 0; @@ -1588,6 +1588,7 @@ int pxe_setup_ctx(struct pxe_context *ctx, struct cmd_tbl *cmdtp, ctx->getfile = getfile; ctx->userdata = userdata; ctx->allow_abs_path = allow_abs_path; + ctx->use_ipv6 = use_ipv6; /* figure out the boot directory, if there is one */ if (bootfile && strlen(bootfile) >= MAX_TFTP_PATH_LEN) diff --git a/cmd/Kconfig b/cmd/Kconfig index e45b8847aef..65957da7f57 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1673,6 +1673,15 @@ config CMD_DHCP help Boot image via network using DHCP/TFTP protocol +config CMD_DHCP6 + bool "dhcp6" + depends on IPV6 + help + Boot image via network using DHCPv6/TFTP protocol using IPv6. + + Will perform 4-message exchange with DHCPv6 server, requesting + the minimum required options to TFTP boot. Complies with RFC 8415. + config BOOTP_MAY_FAIL bool "Allow for the BOOTP/DHCP server to not be found" depends on CMD_BOOTP @@ -1786,6 +1795,23 @@ config BOOTP_VCI_STRING default "U-Boot.arm" if ARM default "U-Boot" +if CMD_DHCP6 + +config DHCP6_PXE_CLIENTARCH + hex + default 0x16 if ARM64 + default 0x15 if ARM + default 0xFF + +config DHCP6_PXE_DHCP_OPTION + bool "Request & store 'pxe_configfile' from DHCP6 server" + +config DHCP6_ENTERPRISE_ID + int "Enterprise ID to send in DHCPv6 Vendor Class Option" + default 0 + +endif + config CMD_TFTPBOOT bool "tftpboot" default y @@ -1916,6 +1942,12 @@ config CMD_NCSI Normally this happens automatically before other network operations. +config IPV6_ROUTER_DISCOVERY + bool "Do IPv6 router discovery" + depends on IPV6 + help + Will automatically perform router solicitation on first IPv6 + network operation endif config CMD_ETHSW diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index f709904c516..365357ca545 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -11,6 +11,7 @@ #include <dm.h> #include <env.h> #include <lmb.h> +#include <mapmem.h> #include <net.h> #include <video.h> #include <vsprintf.h> @@ -41,17 +42,26 @@ void bdinfo_print_num_ll(const char *name, unsigned long long value) printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong), value); } -static void print_eth(int idx) +static void print_eth(void) { - char name[10], *val; + const int idx = eth_get_dev_index(); + uchar enetaddr[6]; + char name[10]; + int ret; + if (idx) sprintf(name, "eth%iaddr", idx); else strcpy(name, "ethaddr"); - val = env_get(name); - if (!val) - val = "(not set)"; - printf("%-12s= %s\n", name, val); + + ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr); + + printf("current eth = %s\n", eth_get_name()); + if (!ret) + printf("%-12s= (not set)\n", name); + else + printf("%-12s= %pM\n", name, enetaddr); + printf("IP addr = %s\n", env_get("ipaddr")); } void bdinfo_print_mhz(const char *name, unsigned long hz) @@ -123,13 +133,10 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) bdinfo_print_num_l("relocaddr", gd->relocaddr); bdinfo_print_num_l("reloc off", gd->reloc_off); printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8); - if (IS_ENABLED(CONFIG_CMD_NET)) { - printf("current eth = %s\n", eth_get_name()); - print_eth(0); - printf("IP addr = %s\n", env_get("ipaddr")); - } - bdinfo_print_num_l("fdt_blob", (ulong)gd->fdt_blob); - bdinfo_print_num_l("new_fdt", (ulong)gd->new_fdt); + if (IS_ENABLED(CONFIG_CMD_NET)) + print_eth(); + bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob)); + bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt)); bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size); if (IS_ENABLED(CONFIG_VIDEO)) show_video_info(); diff --git a/cmd/bmp.c b/cmd/bmp.c index 46d0d916e86..8f43a40dafd 100644 --- a/cmd/bmp.c +++ b/cmd/bmp.c @@ -9,84 +9,12 @@ */ #include <common.h> -#include <bmp_layout.h> #include <command.h> -#include <dm.h> -#include <gzip.h> #include <image.h> -#include <log.h> -#include <malloc.h> #include <mapmem.h> #include <splash.h> #include <video.h> -#include <asm/byteorder.h> - -static int bmp_info (ulong addr); - -/* - * Allocate and decompress a BMP image using gunzip(). - * - * Returns a pointer to the decompressed image data. This pointer is - * aligned to 32-bit-aligned-address + 2. - * See doc/README.displaying-bmps for explanation. - * - * The allocation address is passed to 'alloc_addr' and must be freed - * by the caller after use. - * - * Returns NULL if decompression failed, or if the decompressed data - * didn't contain a valid BMP signature. - */ -#ifdef CONFIG_VIDEO_BMP_GZIP -struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, - void **alloc_addr) -{ - void *dst; - unsigned long len; - struct bmp_image *bmp; - - /* - * Decompress bmp image - */ - len = CONFIG_VIDEO_LOGO_MAX_SIZE; - /* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */ - dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3); - if (!dst) { - puts("Error: malloc in gunzip failed!\n"); - return NULL; - } - - /* align to 32-bit-aligned-address + 2 */ - bmp = dst + 2; - - if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0), - &len)) { - free(dst); - return NULL; - } - if (len == CONFIG_VIDEO_LOGO_MAX_SIZE) - puts("Image could be truncated (increase CONFIG_VIDEO_LOGO_MAX_SIZE)!\n"); - - /* - * Check for bmp mark 'BM' - */ - if (!((bmp->header.signature[0] == 'B') && - (bmp->header.signature[1] == 'M'))) { - free(dst); - return NULL; - } - - debug("Gzipped BMP image detected!\n"); - - *alloc_addr = dst; - return bmp; -} -#else -struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, - void **alloc_addr) -{ - return NULL; -} -#endif +#include <stdlib.h> static int do_bmp_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -137,7 +65,7 @@ static int do_bmp_display(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; } - return (bmp_display(addr, x, y)); + return (bmp_display(addr, x, y)); } static struct cmd_tbl cmd_bmp_sub[] = { @@ -145,22 +73,6 @@ static struct cmd_tbl cmd_bmp_sub[] = { U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""), }; -#ifdef CONFIG_NEEDS_MANUAL_RELOC -void bmp_reloc(void) { - fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub)); -} -#endif - -/* - * Subroutine: do_bmp - * - * Description: Handler for 'bmp' command.. - * - * Inputs: argv[1] contains the subcommand - * - * Return: None - * - */ static int do_bmp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct cmd_tbl *c; @@ -183,73 +95,3 @@ U_BOOT_CMD( "info <imageAddr> - display image info\n" "bmp display <imageAddr> [x y] - display image at x,y" ); - -/* - * Subroutine: bmp_info - * - * Description: Show information about bmp file in memory - * - * Inputs: addr address of the bmp file - * - * Return: None - * - */ -static int bmp_info(ulong addr) -{ - struct bmp_image *bmp = (struct bmp_image *)map_sysmem(addr, 0); - void *bmp_alloc_addr = NULL; - unsigned long len; - - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) - bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr); - - if (bmp == NULL) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - - printf("Image size : %d x %d\n", le32_to_cpu(bmp->header.width), - le32_to_cpu(bmp->header.height)); - printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count)); - printf("Compression : %d\n", le32_to_cpu(bmp->header.compression)); - - if (bmp_alloc_addr) - free(bmp_alloc_addr); - - return(0); -} - -int bmp_display(ulong addr, int x, int y) -{ - struct udevice *dev; - int ret; - struct bmp_image *bmp = map_sysmem(addr, 0); - void *bmp_alloc_addr = NULL; - unsigned long len; - - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) - bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr); - - if (!bmp) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - addr = map_to_sysmem(bmp); - - ret = uclass_first_device_err(UCLASS_VIDEO, &dev); - if (!ret) { - bool align = false; - - if (x == BMP_ALIGN_CENTER || y == BMP_ALIGN_CENTER) - align = true; - - ret = video_bmp_display(dev, addr, x, y, align); - } - - if (bmp_alloc_addr) - free(bmp_alloc_addr); - - return ret ? CMD_RET_FAILURE : 0; -} diff --git a/cmd/fastboot.c b/cmd/fastboot.c index 97dc02ce748..3d5ff951eb6 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -26,7 +26,7 @@ static int do_fastboot_udp(int argc, char *const argv[], return CMD_RET_FAILURE; } - err = net_loop(FASTBOOT); + err = net_loop(FASTBOOT_UDP); if (err < 0) { printf("fastboot udp error: %d\n", err); @@ -36,6 +36,26 @@ static int do_fastboot_udp(int argc, char *const argv[], return CMD_RET_SUCCESS; } +static int do_fastboot_tcp(int argc, char *const argv[], + uintptr_t buf_addr, size_t buf_size) +{ + int err; + + if (!IS_ENABLED(CONFIG_TCP_FUNCTION_FASTBOOT)) { + pr_err("Fastboot TCP not enabled\n"); + return CMD_RET_FAILURE; + } + + err = net_loop(FASTBOOT_TCP); + + if (err < 0) { + printf("fastboot tcp error: %d\n", err); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + static int do_fastboot_usb(int argc, char *const argv[], uintptr_t buf_addr, size_t buf_size) { @@ -141,7 +161,8 @@ NXTARG: if (!strcmp(argv[1], "udp")) return do_fastboot_udp(argc, argv, buf_addr, buf_size); - + if (!strcmp(argv[1], "tcp")) + return do_fastboot_tcp(argc, argv, buf_addr, buf_size); if (!strcmp(argv[1], "usb")) { argv++; argc--; diff --git a/cmd/net.c b/cmd/net.c index d5e20843dda..68d406291ef 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -111,6 +111,29 @@ U_BOOT_CMD( ); #endif +#if defined(CONFIG_CMD_DHCP6) +static int do_dhcp6(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i; + int dhcp_argc; + char *dhcp_argv[] = {NULL, NULL, NULL, NULL}; + + /* Add -ipv6 flag for autoload */ + for (i = 0; i < argc; i++) + dhcp_argv[i] = argv[i]; + dhcp_argc = argc + 1; + dhcp_argv[dhcp_argc - 1] = USE_IP6_CMD_PARAM; + + return netboot_common(DHCP6, cmdtp, dhcp_argc, dhcp_argv); +} + +U_BOOT_CMD(dhcp6, 3, 1, do_dhcp6, + "boot image via network using DHCPv6/TFTP protocol.\n" + "Use IPv6 hostIPaddr framed with [] brackets", + "[loadAddress] [[hostIPaddr:]bootfilename]"); +#endif + #if defined(CONFIG_CMD_DHCP) static int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -186,7 +209,7 @@ U_BOOT_CMD( static void netboot_update_env(void) { - char tmp[22]; + char tmp[44]; if (net_gateway.s_addr) { ip_to_string(net_gateway, tmp); @@ -247,6 +270,27 @@ static void netboot_update_env(void) env_set("ntpserverip", tmp); } #endif + + if (IS_ENABLED(CONFIG_IPV6)) { + if (!ip6_is_unspecified_addr(&net_ip6) || + net_prefix_length != 0) { + sprintf(tmp, "%pI6c", &net_ip6); + if (net_prefix_length != 0) + sprintf(tmp, "%s/%d", tmp, net_prefix_length); + + env_set("ip6addr", tmp); + } + + if (!ip6_is_unspecified_addr(&net_server_ip6)) { + sprintf(tmp, "%pI6c", &net_server_ip6); + env_set("serverip6", tmp); + } + + if (!ip6_is_unspecified_addr(&net_gateway6)) { + sprintf(tmp, "%pI6c", &net_gateway6); + env_set("gatewayip6", tmp); + } + } } /** diff --git a/cmd/pxe.c b/cmd/pxe.c index db8e4697f24..677142520bb 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -8,6 +8,8 @@ #include <command.h> #include <fs.h> #include <net.h> +#include <net6.h> +#include <malloc.h> #include "pxe_utils.h" @@ -29,12 +31,20 @@ static int do_get_tftp(struct pxe_context *ctx, const char *file_path, { char *tftp_argv[] = {"tftp", NULL, NULL, NULL}; int ret; + int num_args; tftp_argv[1] = file_addr; tftp_argv[2] = (void *)file_path; + if (ctx->use_ipv6) { + tftp_argv[3] = USE_IP6_CMD_PARAM; + num_args = 4; + } else { + num_args = 3; + } - if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv)) + if (do_tftpb(ctx->cmdtp, 0, num_args, tftp_argv)) return -ENOENT; + ret = pxe_get_file_size(sizep); if (ret) return log_msg_ret("tftp", ret); @@ -44,6 +54,22 @@ static int do_get_tftp(struct pxe_context *ctx, const char *file_path, } /* + * Looks for a pxe file with specified config file name, + * which is received from DHCPv4 option 209 or + * DHCPv6 option 60. + * + * Returns 1 on success or < 0 on error. + */ +static int pxe_dhcp_option_path(struct pxe_context *ctx, unsigned long pxefile_addr_r) +{ + int ret = get_pxe_file(ctx, pxelinux_configfile, pxefile_addr_r); + + free(pxelinux_configfile); + + return ret; +} + +/* * Looks for a pxe file with a name based on the pxeuuid environment variable. * * Returns 1 on success or < 0 on error. @@ -105,15 +131,24 @@ static int pxe_ipaddr_paths(struct pxe_context *ctx, unsigned long pxefile_addr_ return -ENOENT; } -int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep) +int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep, bool use_ipv6) { struct cmd_tbl cmdtp[] = {}; /* dummy */ struct pxe_context ctx; int i; if (pxe_setup_ctx(&ctx, cmdtp, do_get_tftp, NULL, false, - env_get("bootfile"))) + env_get("bootfile"), use_ipv6)) return -ENOMEM; + + if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION) && + pxelinux_configfile && use_ipv6) { + if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0) + goto done; + + goto error_exit; + } + /* * Keep trying paths until we successfully get a file we're looking * for. @@ -131,6 +166,7 @@ int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep) i++; } +error_exit: pxe_destroy_ctx(&ctx); return -ENOENT; @@ -169,9 +205,18 @@ do_pxe_get(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) char *fname; ulong size; int ret; + bool use_ipv6 = false; - if (argc != 1) - return CMD_RET_USAGE; + if (IS_ENABLED(CONFIG_IPV6)) { + if (!strcmp(argv[argc - 1], USE_IP6_CMD_PARAM)) + use_ipv6 = true; + + if (!(argc == 1 || (argc == 2 && use_ipv6))) + return CMD_RET_USAGE; + } else { + if (argc != 1) + return CMD_RET_USAGE; + } pxefile_addr_str = from_env("pxefile_addr_r"); @@ -183,7 +228,7 @@ do_pxe_get(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (ret < 0) return 1; - ret = pxe_get(pxefile_addr_r, &fname, &size); + ret = pxe_get(pxefile_addr_r, &fname, &size, use_ipv6); switch (ret) { case 0: printf("Config file '%s' found\n", fname); @@ -211,13 +256,19 @@ do_pxe_boot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) char *pxefile_addr_str; struct pxe_context ctx; int ret; + bool use_ipv6 = false; + + if (IS_ENABLED(CONFIG_IPV6)) { + if (!strcmp(argv[argc - 1], USE_IP6_CMD_PARAM)) + use_ipv6 = true; + } - if (argc == 1) { + if (argc == 1 || (argc == 2 && use_ipv6)) { pxefile_addr_str = from_env("pxefile_addr_r"); if (!pxefile_addr_str) return 1; - } else if (argc == 2) { + } else if (argc == 2 || (argc == 3 && use_ipv6)) { pxefile_addr_str = argv[1]; } else { return CMD_RET_USAGE; @@ -229,7 +280,7 @@ do_pxe_boot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } if (pxe_setup_ctx(&ctx, cmdtp, do_get_tftp, NULL, false, - env_get("bootfile"))) { + env_get("bootfile"), use_ipv6)) { printf("Out of memory\n"); return CMD_RET_FAILURE; } @@ -244,8 +295,8 @@ do_pxe_boot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } static struct cmd_tbl cmd_pxe_sub[] = { - U_BOOT_CMD_MKENT(get, 1, 1, do_pxe_get, "", ""), - U_BOOT_CMD_MKENT(boot, 2, 1, do_pxe_boot, "", "") + U_BOOT_CMD_MKENT(get, 2, 1, do_pxe_get, "", ""), + U_BOOT_CMD_MKENT(boot, 3, 1, do_pxe_boot, "", "") }; static void __maybe_unused pxe_reloc(void) @@ -281,9 +332,11 @@ static int do_pxe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_USAGE; } -U_BOOT_CMD(pxe, 3, 1, do_pxe, - "commands to get and boot from pxe files", - "get - try to retrieve a pxe file using tftp\n" - "pxe boot [pxefile_addr_r] - boot from the pxe file at pxefile_addr_r\n" +U_BOOT_CMD(pxe, 4, 1, do_pxe, + "commands to get and boot from pxe files\n" + "To use IPv6 add -ipv6 parameter", + "get [" USE_IP6_CMD_PARAM "] - try to retrieve a pxe file using tftp\n" + "pxe boot [pxefile_addr_r] [-ipv6] - boot from the pxe file at pxefile_addr_r\n" ); -#endif + +#endif /* CONFIG_CMD_NET */ diff --git a/cmd/sysboot.c b/cmd/sysboot.c index 04c07020269..63a7806debe 100644 --- a/cmd/sysboot.c +++ b/cmd/sysboot.c @@ -101,7 +101,7 @@ static int do_sysboot(struct cmd_tbl *cmdtp, int flag, int argc, } if (pxe_setup_ctx(&ctx, cmdtp, sysboot_read_file, &info, true, - filename)) { + filename, false)) { printf("Out of memory\n"); return CMD_RET_FAILURE; } diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index b35eae81dc3..c4ed8e59012 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -471,6 +471,7 @@ static int test_write_limit(struct udevice *dev) break; case TPM_MAXNVWRITES: assert(i >= TPM_MAX_NV_WRITES_NOOWNER); + break; default: pr_err("\tunexpected error code %d (0x%x)\n", result, result); diff --git a/common/Kconfig b/common/Kconfig index f2783ee65d7..bbabadb35e1 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -559,7 +559,7 @@ config BOARD_TYPES config DISPLAY_CPUINFO bool "Display information about the CPU during start up" - default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K + default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K help Display information about the CPU that U-Boot is running on when U-Boot starts up. The function print_cpuinfo() is called @@ -626,7 +626,7 @@ config EVENT_DEBUG bool "Enable event debugging assistance" default y if SANDBOX help - Enable this get usefui features for seeing what is happening with + Enable this to get useful features for seeing what is happening with events, such as event-type names. This adds to the code size of U-Boot so can be turned off for production builds. @@ -1154,3 +1154,15 @@ config FDT_SIMPLEFB config IO_TRACE bool + +config BMP + bool "Enable bmp image display" + default y if CMD_BMP + help + Enable bmp functions to display bmp image and get bmp info. + +config SPL_BMP + bool "Enable bmp image display at SPL" + depends on SPL_VIDEO + help + Enable bmp functions to display bmp image and get bmp info at SPL. diff --git a/common/Makefile b/common/Makefile index a50302d8b52..c87bb2e78b3 100644 --- a/common/Makefile +++ b/common/Makefile @@ -45,6 +45,7 @@ endif # !CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o +obj-$(CONFIG_$(SPL_)BMP) += bmp.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_DFU @@ -56,6 +57,8 @@ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o obj-$(CONFIG_SPL_MUSB_NEW) += usb.o +obj-$(CONFIG_SPL_SPLASH_SCREEN) += splash.o +obj-$(CONFIG_SPL_SPLASH_SOURCE) += splash_source.o endif # CONFIG_SPL_BUILD #others diff --git a/common/bmp.c b/common/bmp.c new file mode 100644 index 00000000000..57764f3653e --- /dev/null +++ b/common/bmp.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2002 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de. + */ + +/* + * BMP handling routines + */ + +#include <common.h> +#include <bmp_layout.h> +#include <command.h> +#include <dm.h> +#include <gzip.h> +#include <log.h> +#include <malloc.h> +#include <mapmem.h> +#include <splash.h> +#include <video.h> +#include <asm/byteorder.h> + +/* + * Allocate and decompress a BMP image using gunzip(). + * + * Returns a pointer to the decompressed image data. This pointer is + * aligned to 32-bit-aligned-address + 2. + * See doc/README.displaying-bmps for explanation. + * + * The allocation address is passed to 'alloc_addr' and must be freed + * by the caller after use. + * + * Returns NULL if decompression failed, or if the decompressed data + * didn't contain a valid BMP signature or decompression is not enabled in + * Kconfig. + */ +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, + void **alloc_addr) +{ + void *dst; + unsigned long len; + struct bmp_image *bmp; + + if (!CONFIG_IS_ENABLED(VIDEO_BMP_GZIP)) + return NULL; + + /* + * Decompress bmp image + */ + len = CONFIG_VAL(VIDEO_LOGO_MAX_SIZE); + /* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */ + dst = malloc(CONFIG_VAL(VIDEO_LOGO_MAX_SIZE) + 3); + if (!dst) { + puts("Error: malloc in gunzip failed!\n"); + return NULL; + } + + /* align to 32-bit-aligned-address + 2 */ + bmp = dst + 2; + + if (gunzip(bmp, CONFIG_VAL(VIDEO_LOGO_MAX_SIZE), map_sysmem(addr, 0), + &len)) { + free(dst); + return NULL; + } + if (len == CONFIG_VAL(VIDEO_LOGO_MAX_SIZE)) + puts("Image could be truncated (increase CONFIG_VIDEO_LOGO_MAX_SIZE)!\n"); + + /* + * Check for bmp mark 'BM' + */ + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + free(dst); + return NULL; + } + + debug("Gzipped BMP image detected!\n"); + + *alloc_addr = dst; + return bmp; +} + +#ifdef CONFIG_NEEDS_MANUAL_RELOC +void bmp_reloc(void) +{ + fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub)); +} +#endif + +int bmp_info(ulong addr) +{ + struct bmp_image *bmp = (struct bmp_image *)map_sysmem(addr, 0); + void *bmp_alloc_addr = NULL; + unsigned long len; + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) + bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr); + + if (!bmp) { + printf("There is no valid bmp file at the given address\n"); + return 1; + } + + printf("Image size : %d x %d\n", le32_to_cpu(bmp->header.width), + le32_to_cpu(bmp->header.height)); + printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count)); + printf("Compression : %d\n", le32_to_cpu(bmp->header.compression)); + + if (bmp_alloc_addr) + free(bmp_alloc_addr); + + return 0; +} + +int bmp_display(ulong addr, int x, int y) +{ + struct udevice *dev; + int ret; + struct bmp_image *bmp = map_sysmem(addr, 0); + void *bmp_alloc_addr = NULL; + unsigned long len; + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) + bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr); + + if (!bmp) { + printf("There is no valid bmp file at the given address\n"); + return 1; + } + addr = map_to_sysmem(bmp); + + ret = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (!ret) { + bool align = false; + + if (x == BMP_ALIGN_CENTER || y == BMP_ALIGN_CENTER) + align = true; + + ret = video_bmp_display(dev, addr, x, y, align); + } + + if (bmp_alloc_addr) + free(bmp_alloc_addr); + + return ret ? CMD_RET_FAILURE : 0; +} diff --git a/common/cli_hush.c b/common/cli_hush.c index 1ad7a509dfa..171069f5f49 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -2171,12 +2171,18 @@ int set_local_var(const char *s, int flg_export) * NAME=VALUE format. So the first order of business is to * split 's' on the '=' into 'name' and 'value' */ value = strchr(name, '='); - if (value == NULL || *(value + 1) == 0) { + if (!value) { free(name); return -1; } *value++ = 0; + if (!*value) { + unset_local_var(name); + free(name); + return 0; + } + for(cur = top_vars; cur; cur = cur->next) { if(strcmp(cur->name, name)==0) break; diff --git a/common/splash.c b/common/splash.c index 4bc54b1bf9e..6820db683bd 100644 --- a/common/splash.c +++ b/common/splash.c @@ -89,19 +89,18 @@ static inline int splash_video_logo_load(void) { return -ENOSYS; } __weak int splash_screen_prepare(void) { - if (IS_ENABLED(CONFIG_SPLASH_SOURCE)) + if (CONFIG_IS_ENABLED(SPLASH_SOURCE)) return splash_source_load(default_splash_locations, ARRAY_SIZE(default_splash_locations)); return splash_video_logo_load(); } -#ifdef CONFIG_SPLASH_SCREEN_ALIGN void splash_get_pos(int *x, int *y) { char *s = env_get("splashpos"); - if (!s) + if (!CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN) || !s) return; if (s[0] == 'm') @@ -117,9 +116,8 @@ void splash_get_pos(int *x, int *y) *y = simple_strtol(s + 1, NULL, 0); } } -#endif /* CONFIG_SPLASH_SCREEN_ALIGN */ -#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION) +#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION) #ifdef CONFIG_VIDEO_LOGO #include <bmp_logo.h> @@ -159,13 +157,13 @@ void splash_display_banner(void) * Common function to show a splash image if env("splashimage") is set. * For additional details please refer to doc/README.splashprepare. */ -#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP) int splash_display(void) { ulong addr; char *s; int x = 0, y = 0, ret; - + if (!CONFIG_IS_ENABLED(SPLASH_SCREEN)) + return -ENOSYS; s = env_get("splashimage"); if (!s) return -EINVAL; @@ -177,16 +175,18 @@ int splash_display(void) splash_get_pos(&x, &y); - ret = bmp_display(addr, x, y); + if (CONFIG_IS_ENABLED(BMP)) + ret = bmp_display(addr, x, y); + else + return -ENOSYS; /* Skip banner output on video console if the logo is not at 0,0 */ if (x || y) goto end; -#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION) +#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION) splash_display_banner(); #endif end: return ret; } -#endif diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7bb878f3697..a402ffa9922 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -47,7 +47,6 @@ CONFIG_BAT2_BASE=0xE0000000 CONFIG_BAT2_LENGTH_8_MBYTES=y CONFIG_BAT2_ACCESS_RW=y CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y CONFIG_BAT2_DCACHE_INHIBITED=y CONFIG_BAT2_DCACHE_GUARDED=y CONFIG_BAT2_USER_MODE_VALID=y @@ -57,7 +56,6 @@ CONFIG_BAT3_NAME="L2_SWITCH" CONFIG_BAT3_BASE=0xF0000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y CONFIG_BAT3_DCACHE_INHIBITED=y CONFIG_BAT3_DCACHE_GUARDED=y CONFIG_BAT3_USER_MODE_VALID=y @@ -93,7 +91,6 @@ CONFIG_BAT7_BASE=0x90000000 CONFIG_BAT7_LENGTH_256_MBYTES=y CONFIG_BAT7_ACCESS_RW=y CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 832243a7312..a2cd4f703dc 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 3205491cebf..642600f92dc 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index b75cae6d803..bb705a1c3ce 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -169,3 +169,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig new file mode 100644 index 00000000000..02e2fbe3db2 --- /dev/null +++ b/configs/bcmns_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_TARGET_BCMNS=y +CONFIG_TEXT_BASE=0x00008000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="ns-board" +CONFIG_IDENT_STRING="Broadcom Northstar" +CONFIG_SYS_LOAD_ADDR=0x00008000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00100000 +# CONFIG_BOOTSTD is not set +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n" +CONFIG_BOOTDELAY=1 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl" +CONFIG_SYS_PROMPT="northstar> " +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_SEAMA=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="NS" +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_CMD_NAND=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +# CONFIG_NET is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 66adeac725c..95f0c30cde6 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -18,6 +18,7 @@ CONFIG_TARGET_BK4R1=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 +CONFIG_LTO=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=520192 CONFIG_FIT=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 5e015932069..3d663130745 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -34,7 +34,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_8_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/hc2910_2aghd05_defconfig b/configs/hc2910_2aghd05_defconfig new file mode 100644 index 00000000000..dfd3e656b9b --- /dev/null +++ b/configs/hc2910_2aghd05_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_HISTB=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x1F0000 +CONFIG_DEFAULT_DEVICE_TREE="hi3798mv200-hc2910-2aghd05" +CONFIG_SYS_PROMPT="HC2910# " +CONFIG_IDENT_STRING="HC2910" +CONFIG_SYS_LOAD_ADDR=0x800000 +# CONFIG_EXPERT is not set +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=537 +CONFIG_CMD_BOOTDEV=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_CAT=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +CONFIG_MMC_DW=y +CONFIG_MMC_DW_K3=y +# CONFIG_POWER is not set +CONFIG_FS_BTRFS=y +CONFIG_FAT_WRITE=y +CONFIG_REGEX=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig new file mode 100644 index 00000000000..9b14a1bca10 --- /dev/null +++ b/configs/imx8mq_reform2_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x600000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_REFORM2=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb" +CONFIG_CONSOLE_MUX=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_MDIO is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="FEC" +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_KEYBOARD=y diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig new file mode 100644 index 00000000000..3341b5e447f --- /dev/null +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -0,0 +1,129 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SYS_MALLOC_LEN=0x2800000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_MMC_IMG_LOAD_PART=0 +CONFIG_TARGET_IMX8QM_DMSSE20_A1=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_REMAKE_ELF=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y +CONFIG_CI_UDC=y +CONFIG_DM_PCA953X=y +CONFIG_EVENT=y +CONFIG_DM_EVENT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BSS_START_ADDR=0x00128000 +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x04000000 +CONFIG_HUSH_PARSER=y +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_FS_EXT4=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FUSE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1" +CONFIG_ENV_SOURCE_FILE="imx8qm_dmsse20-a1" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=0 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_GIGE=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_FEC1_ENET_DEV=0 +CONFIG_ETHPRIME="eth0" +CONFIG_FEC1_MXC_PHYADDR=0x4 +CONFIG_FEC2_ENET_DEV=1 +CONFIG_ETHPRIME1="eth1" +CONFIG_FEC2_MXC_PHYADDR=0x4 +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_IMX_SMMU=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_BAUDRATE=115200 +CONFIG_MISC=y +CONFIG_SMC_FUSE=y +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_TINY_MEMSET=y +CONFIG_AHAB_BOOT=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV8803=y +CONFIG_CMD_DATE=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index fa5ea2aecdd..e40900fffa4 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y @@ -34,7 +35,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 00ec48b83b7..dd4454943c3 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SPL_GPIO=y diff --git a/configs/j7200_hs_evm_a72_defconfig b/configs/j7200_hs_evm_a72_defconfig deleted file mode 100644 index d9560727edb..00000000000 --- a/configs/j7200_hs_evm_a72_defconfig +++ /dev/null @@ -1,205 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y -CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SOC_K3_J721E=y -CONFIG_TARGET_J7200_A72_EVM=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board" -CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_ENV_OFFSET_REDUND=0x6A0000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -# CONFIG_PSCI_RESET is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" -CONFIG_LOGLEVEL=7 -CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 -CONFIG_SPL_DMA=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -# CONFIG_SPL_SPI_FLASH_TINY is not set -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_UFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus" -CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_CLK_CCF=y -CONFIG_CLK_TI_SCI=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_DFU_SF=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 -CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 -CONFIG_DMA_CHANNELS=y -CONFIG_TI_K3_NAVSS_UDMA=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DA8XX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_GPIO=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_DM_MAILBOX=y -CONFIG_K3_SEC_PROXY=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_SPL_MMC_HS400_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ADMA=y -CONFIG_SPL_MMC_SDHCI_ADMA=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_SHOW_PROGRESS=0 -CONFIG_CFI_FLASH=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_HBMC_AM654=y -CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_SPI_FLASH_MTD=y -CONFIG_MULTIPLEXER=y -CONFIG_MUX_MMIO=y -CONFIG_PHY_FIXED=y -CONFIG_TI_AM65_CPSW_NUSS=y -CONFIG_PHY=y -CONFIG_SPL_PHY=y -CONFIG_PHY_CADENCE_TORRENT=y -CONFIG_PHY_J721E_WIZ=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_PINCTRL_SINGLE=y -CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_R5F=y -CONFIG_RESET_TI_SCI=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DM_SERIAL=y -CONFIG_SOC_DEVICE=y -CONFIG_SOC_DEVICE_TI_K3=y -CONFIG_SOC_TI=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_HAS_CQSPI_REF_CLK=y -CONFIG_CQSPI_REF_CLK=133333333 -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_TI_SCI=y -CONFIG_USB=y -CONFIG_DM_USB_GADGET=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y -CONFIG_USB_CDNS3_HOST=y -CONFIG_SPL_USB_CDNS3_GADGET=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 -CONFIG_UFS=y -CONFIG_CADENCE_UFS=y -CONFIG_TI_J721E_UFS=y diff --git a/configs/j7200_hs_evm_r5_defconfig b/configs/j7200_hs_evm_r5_defconfig deleted file mode 100644 index 94a6523f06c..00000000000 --- a/configs/j7200_hs_evm_r5_defconfig +++ /dev/null @@ -1,170 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y -CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x70000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SOC_K3_J721E=y -CONFIG_K3_EARLY_CONS=y -CONFIG_TARGET_J7200_R5_EVM=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc -CONFIG_ENV_SIZE=0x20000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board" -CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_DM_RESET=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 -CONFIG_USE_BOOTCOMMAND=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc -CONFIG_SPL_BSS_MAX_SIZE=0xa000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 -CONFIG_SPL_EARLY_BSS=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 -CONFIG_SPL_DMA=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y -# CONFIG_SPL_SPI_FLASH_TINY is not set -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_SPL_CLK_CCF=y -CONFIG_SPL_CLK_K3_PLL=y -CONFIG_SPL_CLK_K3=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 -CONFIG_DMA_CHANNELS=y -CONFIG_TI_K3_NAVSS_UDMA=y -CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DA8XX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_DM_MAILBOX=y -CONFIG_K3_SEC_PROXY=y -CONFIG_FS_LOADER=y -CONFIG_SPL_FS_LOADER=y -CONFIG_K3_AVS0=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_SPL_MMC_HS400_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_SPL_MMC_SDHCI_ADMA=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_SHOW_PROGRESS=0 -CONFIG_CFI_FLASH=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_HBMC_AM654=y -CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_PINCTRL_SINGLE=y -CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_TI_POWER_DOMAIN=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_TPS65941=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_TPS65941=y -CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_RESET_TI_SCI=y -CONFIG_DM_SERIAL=y -CONFIG_SOC_DEVICE=y -CONFIG_SOC_DEVICE_TI_K3=y -CONFIG_SOC_TI=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_HAS_CQSPI_REF_CLK=y -CONFIG_CQSPI_REF_CLK=133333333 -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_TI_SCI=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_OMAP_TIMER=y -CONFIG_USB=y -CONFIG_DM_USB_GADGET=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y -CONFIG_SPL_USB_CDNS3_GADGET=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_FS_EXT4=y -CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -CONFIG_LIB_RATIONAL=y -CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index addae9f6a29..594c8dad2ca 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y @@ -31,7 +32,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 343e3c16305..7416ba2d38d 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y diff --git a/configs/j721s2_hs_evm_a72_defconfig b/configs/j721s2_hs_evm_a72_defconfig deleted file mode 100644 index d8089cb7dbc..00000000000 --- a/configs/j721s2_hs_evm_a72_defconfig +++ /dev/null @@ -1,212 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y -CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SOC_K3_J721S2=y -CONFIG_TARGET_J721S2_A72_EVM=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board" -CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_ENV_OFFSET_REDUND=0x6A0000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -# CONFIG_PSCI_RESET is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" -CONFIG_LOGLEVEL=7 -CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 -CONFIG_SPL_DMA=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -# CONFIG_SPL_SPI_FLASH_TINY is not set -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -CONFIG_SPL_THERMAL=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_UFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus" -CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_CLK_CCF=y -CONFIG_CLK_TI_SCI=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_DFU_SF=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 -CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 -CONFIG_DMA_CHANNELS=y -CONFIG_TI_K3_NAVSS_UDMA=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DA8XX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_GPIO=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_DM_MAILBOX=y -CONFIG_K3_SEC_PROXY=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_SPL_MMC_HS400_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ADMA=y -CONFIG_SPL_MMC_SDHCI_ADMA=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_SHOW_PROGRESS=0 -CONFIG_CFI_FLASH=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_SOFT_RESET=y -CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MT35XU=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_SPI_FLASH_MTD=y -CONFIG_MULTIPLEXER=y -CONFIG_MUX_MMIO=y -CONFIG_PHY_TI_DP83867=y -CONFIG_PHY_FIXED=y -CONFIG_TI_AM65_CPSW_NUSS=y -CONFIG_PHY=y -CONFIG_SPL_PHY=y -CONFIG_PHY_CADENCE_TORRENT=y -CONFIG_PHY_J721E_WIZ=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_PINCTRL_SINGLE=y -CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y -CONFIG_RESET_TI_SCI=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DM_SERIAL=y -CONFIG_SOC_DEVICE=y -CONFIG_SOC_DEVICE_TI_K3=y -CONFIG_SOC_TI=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_HAS_CQSPI_REF_CLK=y -CONFIG_CQSPI_REF_CLK=133333333 -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_TI_SCI=y -CONFIG_DM_THERMAL=y -CONFIG_USB=y -CONFIG_DM_USB_GADGET=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y -CONFIG_USB_CDNS3_HOST=y -CONFIG_SPL_USB_CDNS3_GADGET=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 -CONFIG_UFS=y -CONFIG_CADENCE_UFS=y -CONFIG_TI_J721E_UFS=y diff --git a/configs/j721s2_hs_evm_r5_defconfig b/configs/j721s2_hs_evm_r5_defconfig deleted file mode 100644 index c8433a1de95..00000000000 --- a/configs/j721s2_hs_evm_r5_defconfig +++ /dev/null @@ -1,175 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y -CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x10000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SOC_K3_J721S2=y -CONFIG_K3_EARLY_CONS=y -CONFIG_TARGET_J721S2_R5_EVM=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board" -CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_DM_RESET=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_SIZE_LIMIT=0x80000 -CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 -CONFIG_USE_BOOTCOMMAND=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y -CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y -CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c76000 -CONFIG_SPL_BSS_MAX_SIZE=0xa000 -CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 -CONFIG_SPL_EARLY_BSS=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 -CONFIG_SPL_DMA=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y -# CONFIG_SPL_SPI_FLASH_TINY is not set -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_THERMAL=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_SPL_CLK_CCF=y -CONFIG_SPL_CLK_K3_PLL=y -CONFIG_SPL_CLK_K3=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 -CONFIG_DMA_CHANNELS=y -CONFIG_TI_K3_NAVSS_UDMA=y -CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DA8XX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_DM_MAILBOX=y -CONFIG_K3_SEC_PROXY=y -CONFIG_FS_LOADER=y -CONFIG_SPL_FS_LOADER=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_SPL_MMC_HS400_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_SPL_MMC_SDHCI_ADMA=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_SHOW_PROGRESS=0 -CONFIG_CFI_FLASH=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_SOFT_RESET=y -CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MT35XU=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_PINCTRL_SINGLE=y -CONFIG_POWER_DOMAIN=y -CONFIG_TI_POWER_DOMAIN=y -CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_RESET_TI_SCI=y -CONFIG_DM_SERIAL=y -CONFIG_SOC_DEVICE=y -CONFIG_SOC_DEVICE_TI_K3=y -CONFIG_SOC_TI=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_HAS_CQSPI_REF_CLK=y -CONFIG_CQSPI_REF_CLK=133333333 -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_TI_SCI=y -CONFIG_DM_THERMAL=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_OMAP_TIMER=y -CONFIG_USB=y -CONFIG_DM_USB_GADGET=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y -CONFIG_SPL_USB_CDNS3_GADGET=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_FS_EXT4=y -CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -CONFIG_PANIC_HANG=y -CONFIG_LIB_RATIONAL=y -CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index a8e48f8e30a..0de6ae06b95 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -27,7 +27,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -38,7 +37,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y @@ -95,7 +93,6 @@ CONFIG_BAT7_BASE=0x10000000 CONFIG_BAT7_LENGTH_256_MBYTES=y CONFIG_BAT7_ACCESS_RW=y CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index da7229896bd..568e55f3998 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -28,7 +28,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -39,7 +38,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 41d0d2ee03d..facd6861cdb 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -22,7 +22,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -33,7 +32,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 538a37b042b..c00e62644f0 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -22,7 +22,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -33,7 +32,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index a2ad34d5d84..8122124c17d 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -22,7 +22,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -33,7 +32,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index 2d4876f299f..5b76512a46f 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -7,15 +7,15 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80000 CONFIG_ENV_OFFSET=0x300000 -CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb" -CONFIG_SYS_PROMPT="MT7986> " +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" +CONFIG_SYS_PROMPT="BPI-R3> " CONFIG_TARGET_MT7986=y CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y # CONFIG_AUTOBOOT is not set -CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb" +CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-emmc" CONFIG_LOGLEVEL=7 CONFIG_LOG=y CONFIG_SYS_CBSIZE=512 diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index 08edfe7ac40..36547db9142 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -7,15 +7,15 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80000 CONFIG_ENV_OFFSET=0x300000 -CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb" -CONFIG_SYS_PROMPT="MT7986> " +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd" +CONFIG_SYS_PROMPT="BPI-R3> " CONFIG_TARGET_MT7986=y CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y # CONFIG_AUTOBOOT is not set -CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb" +CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-sd" CONFIG_LOGLEVEL=7 CONFIG_LOG=y CONFIG_SYS_CBSIZE=512 diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig deleted file mode 100644 index c1ac60ebb0d..00000000000 --- a/configs/omap5_uevm_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00 -CONFIG_DEFAULT_DEVICE_TREE="omap5-uevm" -CONFIG_SPL_TEXT_BASE=0x40300000 -CONFIG_OMAP54XX=y -CONFIG_TARGET_OMAP5_UEVM=y -CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x280000 -CONFIG_ARMV7_LPAE=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; " -CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0x1dc00 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_FALCON_BOOT_MMCSD=y -CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 -CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 -CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SCSI_AHCI=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_TCA642X=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_OMAP_HS=y -CONFIG_HSMMC2_8BIT=y -CONFIG_PALMAS_POWER=y -CONFIG_SCSI=y -CONFIG_SCSI_AHCI_PLAT=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0403 -CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 -CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index dcee179fcff..4e60159a462 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -76,6 +76,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index f5cfdc4c894..f3002de857f 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -69,6 +69,7 @@ CONFIG_CMD_CDP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y +CONFIG_IPV6_ROUTER_DISCOVERY=y CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 24a44483a5a..1ec44d5b33b 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -91,6 +91,7 @@ CONFIG_CMD_AXI=y CONFIG_CMD_CAT=y CONFIG_CMD_SETEXPR_FMT=y CONFIG_CMD_AB_SELECT=y +CONFIG_CMD_DHCP6=y CONFIG_BOOTP_DNS2=y CONFIG_CMD_PCAP=y CONFIG_CMD_TFTPPUT=y @@ -100,6 +101,7 @@ CONFIG_CMD_CDP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y +CONFIG_IPV6_ROUTER_DISCOVERY=y CONFIG_CMD_ETHSW=y CONFIG_CMD_2048=y CONFIG_CMD_BMP=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 5b6b28a348f..e7657d40dc5 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_CDP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y +CONFIG_IPV6_ROUTER_DISCOVERY=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 1e0b9aa5be1..3d2713f5280 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01" CONFIG_TARGET_SMEGW01=y +# CONFIG_SYS_BOOT_LOCKED is not set CONFIG_ENV_OFFSET_REDUND=0x110000 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set @@ -17,19 +18,27 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_AUTOBOOT_MENU_SHOW=y +# CONFIG_BOOTSTD is not set +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; " +CONFIG_BOOTCOMMAND="if test \"${bootcount}\" -gt \"${bootlimit}\"; then run altbootcmd; else if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; fi;" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run setup_boot_menu;" CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y +CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_DHCP=y @@ -38,13 +47,20 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_MMC=y CONFIG_DM_I2C=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig index 3d96e0ae09b..5b85ce5fe96 100644 --- a/configs/starqltechn_defconfig +++ b/configs/starqltechn_defconfig @@ -17,18 +17,24 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GPIO=y CONFIG_CMD_BMP=y # CONFIG_NET is not set +CONFIG_BUTTON=y CONFIG_CLK=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y +CONFIG_DM_KEYBOARD=y +CONFIG_BUTTON_KEYBOARD=y CONFIG_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SPMI_MSM=y CONFIG_VIDEO=y +# CONFIG_VIDEO_FONT_8X16 is not set +CONFIG_VIDEO_FONT_16X32=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_SIMPLE=y CONFIG_VIDEO_DT_SIMPLEFB=y diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index c16e58e660b..9797a343e51 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -81,7 +81,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_RX8025=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 8e5f1c605d1..c10b5c20a73 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -22,7 +22,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -33,7 +32,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index f7f20ae531a..f61fb96ab83 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -22,7 +22,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -33,7 +32,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/doc/board/advantech/imx8qm-dmsse20-a1.rst b/doc/board/advantech/imx8qm-dmsse20-a1.rst new file mode 100644 index 00000000000..b83e678cd9a --- /dev/null +++ b/doc/board/advantech/imx8qm-dmsse20-a1.rst @@ -0,0 +1,58 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NXP i.MX8QM DMSSE20-a1 board +============================ + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/nxp-imx/imx-atf + $ cd imx-atf/ + $ git checkout lf-5.10.72-2.2.0 -b lf-5.10.72-2.2.0 + $ make PLAT=imx8qm bl31 + $ cp build/imx8qm/release/bl31.bin $(builddir) + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.11.0.bin + $ chmod +x imx-sc-firmware-1.11.0.bin + $ ./imx-sc-firmware-1.11.0.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.5.bin + $ chmod +x imx-seco-3.8.5.bin + $ ./imx-seco-3.8.5.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.11.0.bin of=imx-sc-firmware-1.11.0.tar.bz2 bs=42757 skip=1 + $ tar -xf imx-sc-firmware-1.11.0.tar.bz2 + $ cp imx-sc-firmware-1.11.0/mx8qm-val-scfw-tcm.bin $(builddir) + $ dd if=imx-seco-3.8.5.bin of=imx-seco-3.8.5.tar.bz2 bs=43978 skip=1 + $ tar -xf imx-seco-3.8.5.tar.bz2 + $ cp imx-seco-3.8.5/firmware/seco/mx8qmb0-ahab-container.img $(builddir) + +Build U-Boot +------------ +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make imx8qm_dmsse20a1_defconfig + $ make diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst index e9b198c5c3e..125b98c1f76 100644 --- a/doc/board/advantech/index.rst +++ b/doc/board/advantech/index.rst @@ -7,3 +7,4 @@ Advantech :maxdepth: 2 imx8qm-rom7720-a1.rst + imx8qm-dmsse20-a1.rst diff --git a/doc/board/broadcom/index.rst b/doc/board/broadcom/index.rst index a56bd1f0692..ca34afc82be 100644 --- a/doc/board/broadcom/index.rst +++ b/doc/board/broadcom/index.rst @@ -9,3 +9,4 @@ Broadcom bcm7xxx raspberrypi + northstar diff --git a/doc/board/broadcom/northstar.rst b/doc/board/broadcom/northstar.rst new file mode 100644 index 00000000000..f4bc0acd010 --- /dev/null +++ b/doc/board/broadcom/northstar.rst @@ -0,0 +1,44 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org> + +Broadcom Northstar Boards +========================= + +This document describes how to use U-Boot on the Broadcom Northstar +boards, comprised of the Cortex A9 ARM-based BCM470x and BCM5301x SoCs. These +were introduced in 2012-2013 and some of them are also called StrataGX. + +Northstar is part of the iProc SoC family. + +A good overview of these boards can be found in Jon Mason's presentation +"Enabling New Hardware in U-Boot" where the difference between Northstar +and Northstar Plus and Northstar 2 (Aarch64) is addressed. + +The ROM in the Northstar SoC will typically look into NOR flash memory +for a boot loader, and the way this works is undocumented. It should be +possible to execute U-Boot as the first binary from the NOR flash but +this usage path is unexplored. Please add information if you know more. + +D-Link Boards +------------- + +When we use U-Boot with D-Link routers, the NOR flash has a boot loader +and web server that can re-flash the bigger NAND flash memory for object +code in the SEAMA format, so on these platforms U-Boot is converted into +a SEAMA binary and installed in the SoC using the flash tool resident in +the NOR flash. Details can be found in the OpenWrt project codebase. + +Configure +--------- + +.. code-block:: console + + $ make CROSS_COMPILE=${CROSS_COMPILE} bcmns_defconfig + +Build +----- + +.. code-block:: console + + $ make CROSS_COMPILE=${CROSS_COMPILE} + $ ${CROSS_COMPILE}strip u-boot diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst index bbb40b043b3..0cb71d97c98 100644 --- a/doc/board/qualcomm/qcs404.rst +++ b/doc/board/qualcomm/qcs404.rst @@ -9,8 +9,8 @@ About this This document describes the information about Qualcomm QCS404 evaluation board and it's usage steps. -U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader. -It is loaded as an Android boot image through ABL +The current boot flow support loading u-boot as an Android boot image via +Qualcomm's UEFI-based ABL (Android) Bootloader. Installation ------------ diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst index 8ef47492877..71879c2a6e3 100644 --- a/doc/board/qualcomm/sdm845.rst +++ b/doc/board/qualcomm/sdm845.rst @@ -12,8 +12,8 @@ supported boards and it's usage steps. SDM845 - hi-end qualcomm chip, introduced in late 2017. Mostly used in flagship phones and tablets of 2018. -U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader. -It is loaded as an Android boot image through ABL +The current boot flow support loading u-boot as an Android boot image via +Qualcomm's UEFI-based ABL (Android) Bootloader. Installation ------------ diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst index a99442277b6..de2aab59bb1 100644 --- a/doc/board/sifive/unmatched.rst +++ b/doc/board/sifive/unmatched.rst @@ -56,8 +56,10 @@ Flashing ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type 5B193300-FC78-40CD-8002-E86C45580B47 -U-Boot SPL expects u-boot.itb from a partition with GUID -type 2E54B353-1271-4842-806F-E436D6AF6985 +With the default configuration U-Boot SPL expects u-boot.itb starting at sector +2082 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x822). It is recommended to use a +partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985 for storing +main U-Boot. u-boot.itb is a combination of fw_dynamic.bin, u-boot-nodtb.bin and device tree blob (hifive-unmatched-a00.dtb) diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 22d2a31ff59..4d43ac9729c 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -51,6 +51,8 @@ cloned and built for JH7110 as below: cd opensbi make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0 +The VisionFive 2 support for OpenSBI was introduced after the v1.2 release. + More detailed description of steps required to build FW_DYNAMIC firmware is beyond the scope of this document. Please refer OpenSBI documenation. (Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) @@ -79,14 +81,19 @@ This will generate u-boot-spl.bin.normal.out file. Flashing ~~~~~~~~ -SPL loads the U-Boot SPL (u-boot-spl.bin.normal.out) from a partition with GUID type -2E54B353-1271-4842-806F-E436D6AF6985 +The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the +partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free +to choose any partition number. -U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID -type BC13C2FF-59E6-4262-A352-B275FD6F7172 +With the default configuration U-Boot SPL loads the U-Boot FIT image +(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2). +When formatting it is recommended to use GUID +BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition. -FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and -device tree blob (jh7110-starfive-visionfive-2-v1.3b.dtb/jh7110-starfive-visionfive-2-v1.2a.dtb) +The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin, +u-boot-nodtb.bin and the device tree blob +(jh7110-starfive-visionfive-2-v1.3b.dtb or +jh7110-starfive-visionfive-2-v1.2a.dtb). Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) @@ -117,7 +124,9 @@ Program the SD card Booting ~~~~~~~ -Change DIP switches MSEL[1:0] are set to 10, select the boot mode to SD. +The board provides the DIP switches MSEL[1:0] to select the boot device. +To select booting from SD-card set the DIP switches MSEL[1:0] to 10. + Once you plugin the sdcard and power up, you should see the U-Boot prompt. Sample boot log from StarFive VisionFive2 board diff --git a/doc/develop/event.rst b/doc/develop/event.rst index 4ff59348371..e60cbf65691 100644 --- a/doc/develop/event.rst +++ b/doc/develop/event.rst @@ -12,7 +12,7 @@ Rather than using weak functions and direct calls across subsystemss, it is often easier to use an event. An event consists of a type (e.g. EVT_DM_POST_INIT) and some optional data, -in `union event_data`. An event spy can be creasted to watch for events of a +in `union event_data`. An event spy can be created to watch for events of a particular type. When the event is created, it is sent to each spy in turn. diff --git a/doc/develop/trace.rst b/doc/develop/trace.rst index 8425d843e9c..9bbe1345d2d 100644 --- a/doc/develop/trace.rst +++ b/doc/develop/trace.rst @@ -100,7 +100,7 @@ Then run proftool to convert the trace information to ftrace format .. code-block:: console - $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-ftrace >trace.dat + $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-ftrace -o trace.dat Finally run kernelshark to display it (note it only works with `.dat` files!): diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt b/doc/device-tree-bindings/serial/msm-geni-serial.txt index 9eadc2561b4..eaa39c949b1 100644 --- a/doc/device-tree-bindings/serial/msm-geni-serial.txt +++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt @@ -1,6 +1,6 @@ Qualcomm GENI UART Required properties: -- compatible: must be "qcom,msm-geni-uart" +- compatible: must be "qcom,geni-debug-uart" - reg: start address and size of the registers - clock: interface clock (must accept baudrate as a frequency) diff --git a/doc/usage/cmd/cp.rst b/doc/usage/cmd/cp.rst new file mode 100644 index 00000000000..12a24e19fee --- /dev/null +++ b/doc/usage/cmd/cp.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +cp command +========== + +Synopsis +-------- + +:: + + cp source target count + cp.b source target count + cp.w source target count + cp.l source target count + cp.q source target count + +Description +----------- + +The cp command is used to copy *count* chunks of memory from the *source* +address to the *target* address. If the *target* address points to NOR flash, +the flash is programmed. + +The number bytes in one chunk is defined by the suffix defaulting to 4 bytes: + +====== ========== +suffix chunk size +====== ========== +.b 1 byte +.w 2 bytes +.l 4 bytes +.q 8 bytes +<none> 4 bytes +====== ========== + +source + source address, hexadecimal + +target + target address, hexadecimal + +count + number of words to be copied, hexadecimal + +Examples +-------- + +The example device has a NOR flash where the lower part of the flash is +protected. We first copy to RAM, then to unprotected flash. Last we try to +write to protectd flash. + +:: + + => mtd list + List of MTD devices: + * nor0 + - device: flash@0 + - parent: root_driver + - driver: cfi_flash + - path: /flash@0 + - type: NOR flash + - block size: 0x20000 bytes + - min I/O: 0x1 bytes + - 0x000000000000-0x000002000000 : "nor0" + => cp.b 4020000 5000000 200000 + => cp.b 4020000 1e00000 20000 + Copy to Flash... done + => cp.b 4020000 0 20000 + Copy to Flash... Can't write to protected Flash sectors + => + +Configuration +------------- + +The cp command is available if CONFIG_CMD_MEMORY=y. Support for 64 bit words +(cp.q) depends on CONFIG_MEM_SUPPORT_64BIT_DATA=y. Copying to flash depends on +CONFIG_MTD_NOR_FLASH=y. + +Return value +------------ + +The return value $? is set to 0 (true) if the command was successfully, +1 (false) otherwise. diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst index 55e3f9cf98c..71a0303109c 100644 --- a/doc/usage/cmd/mmc.rst +++ b/doc/usage/cmd/mmc.rst @@ -213,10 +213,10 @@ The 'mmc info' command displays device's capabilities: The raw data can be read/written via 'mmc read/write' command: :: - => mmc read 0x40000000 0x5000 0x100 + => mmc read 40000000 5000 100 MMC read: dev # 0, block # 20480, count 256 ... 256 blocks read: OK - => mmc write 0x40000000 0x5000 0x10 + => mmc write 40000000 5000 100 MMC write: dev # 0, block # 20480, count 256 ... 256 blocks written: OK The partition list can be shown via 'mmc part' command: diff --git a/doc/usage/index.rst b/doc/usage/index.rst index cdf710919a2..0fde130a548 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -41,6 +41,7 @@ Shell commands cmd/cmp cmd/coninfo cmd/conitrace + cmd/cp cmd/cyclic cmd/dm cmd/ebtupdate diff --git a/drivers/Kconfig b/drivers/Kconfig index 9101e538b09..75937fbb6d9 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -36,6 +36,8 @@ source "drivers/dfu/Kconfig" source "drivers/dma/Kconfig" +source "drivers/extcon/Kconfig" + source "drivers/fastboot/Kconfig" source "drivers/firmware/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 58be410135d..29be78a3f28 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/ obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ +obj-$(CONFIG_$(SPL_TPL_)EXTCON) += extcon/ obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/ obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/ obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/ @@ -61,6 +62,7 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ +obj-$(CONFIG_SPL_VIDEO) +=video/ endif endif diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig new file mode 100644 index 00000000000..fbb73354aa3 --- /dev/null +++ b/drivers/extcon/Kconfig @@ -0,0 +1,31 @@ +menu "Extcon Support" + +config EXTCON + bool "External Connector Class (extcon) support" + depends on DM + help + Say Y here to enable external connector class (extcon) support. + This allows monitoring external connectors and supports external + connectors with multiple states; i.e., an extcon that may have + multiple cables attached. For example, an external connector + of a device may be used to connect an HDMI cable and a AC adaptor, + and to host USB ports. Many of 30-pin connectors including PDMI + are also good examples. + +config EXTCON_SANDBOX + bool "Sandbox extcon" + depends on EXTCON + help + Enable extcon support for sandbox. This is an emulation of a real + extcon. Currectly all configuration is done in the probe. + +config EXTCON_MAX14526 + bool "Maxim MAX14526 EXTCON Support" + depends on DM_I2C + depends on EXTCON + help + If you say yes here you get support for the MUIC device of + Maxim MAX14526. The MAX14526 MUIC is a USB port accessory + detector and switch. + +endmenu diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile new file mode 100644 index 00000000000..3309f2aac2e --- /dev/null +++ b/drivers/extcon/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_EXTCON) += extcon-uclass.o +obj-$(CONFIG_EXTCON_SANDBOX) += extcon-sandbox.o +obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c new file mode 100644 index 00000000000..a33b5ef919c --- /dev/null +++ b/drivers/extcon/extcon-max14526.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <log.h> +#include <extcon.h> +#include <asm/gpio.h> + +#define CONTROL_1 0x01 +#define SW_CONTROL 0x03 + +#define ID_200 0x10 +#define ADC_EN 0x02 +#define CP_EN 0x01 + +#define DP_USB 0x00 +#define DP_UART 0x08 +#define DP_AUDIO 0x10 +#define DP_OPEN 0x38 + +#define DM_USB 0x00 +#define DM_UART 0x01 +#define DM_AUDIO 0x02 +#define DM_OPEN 0x07 + +#define AP_USB BIT(0) +#define CP_USB BIT(1) +#define CP_UART BIT(2) + +struct max14526_priv { + struct gpio_desc usif_gpio; + struct gpio_desc dp2t_gpio; + struct gpio_desc ifx_usb_vbus_gpio; +}; + +static void max14526_set_mode(struct udevice *dev, int mode) +{ + struct max14526_priv *priv = dev_get_priv(dev); + int ret; + + if ((mode & AP_USB) || (mode & CP_USB)) { + /* Connect CP UART signals to AP */ + ret = dm_gpio_set_value(&priv->usif_gpio, 0); + if (ret) + log_debug("cp-uart > ap failed (%d)\n", ret); + } + + if (mode & CP_UART) { + /* Connect CP UART signals to DP2T */ + ret = dm_gpio_set_value(&priv->usif_gpio, 1); + if (ret) + log_debug("cp-uart > dp2t failed (%d)\n", ret); + } + + if (mode & CP_USB) { + /* Connect CP USB to MUIC UART */ + ret = dm_gpio_set_value(&priv->ifx_usb_vbus_gpio, 1); + if (ret) + log_debug("usb-vbus-gpio enable failed (%d)\n", ret); + + ret = dm_gpio_set_value(&priv->dp2t_gpio, 1); + if (ret) + log_debug("cp-usb > muic-uart failed (%d)\n", ret); + } + + if ((mode & AP_USB) || (mode & CP_UART)) { + /* Connect CP UART to MUIC UART */ + ret = dm_gpio_set_value(&priv->dp2t_gpio, 0); + if (ret) + log_debug("cp-uart > muic-uart failed (%d)\n", ret); + } + + if (mode & AP_USB) { + /* Enables USB Path */ + ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_USB | DM_USB); + if (ret) + log_debug("USB path set failed: %d\n", ret); + } + + if ((mode & CP_USB) || (mode & CP_UART)) { + /* Enables UART Path */ + ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_UART | DM_UART); + if (ret) + log_debug("UART path set failed: %d\n", ret); + } + + /* Enables 200K, Charger Pump, and ADC */ + ret = dm_i2c_reg_write(dev, CONTROL_1, ID_200 | ADC_EN | CP_EN); + if (ret) + log_debug("200K, Charger Pump, and ADC set failed: %d\n", ret); +} + +static int max14526_probe(struct udevice *dev) +{ + struct max14526_priv *priv = dev_get_priv(dev); + int ret, mode = 0; + + ret = gpio_request_by_name(dev, "usif-gpios", 0, + &priv->usif_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode usif-gpios (%d)\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "dp2t-gpios", 0, + &priv->dp2t_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode dp2t-gpios (%d)\n", ret); + return ret; + } + + if (dev_read_bool(dev, "maxim,ap-usb")) + mode |= AP_USB; + + if (dev_read_bool(dev, "maxim,cp-usb")) { + mode |= CP_USB; + + ret = gpio_request_by_name(dev, "usb-vbus-gpios", 0, + &priv->ifx_usb_vbus_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode usb-vbus-gpios (%d)\n", ret); + return ret; + } + } + + if (dev_read_bool(dev, "maxim,cp-uart")) + mode |= CP_UART; + + max14526_set_mode(dev, mode); + + return 0; +} + +static const struct udevice_id max14526_ids[] = { + { .compatible = "maxim,max14526-muic" }, + { } +}; + +U_BOOT_DRIVER(extcon_max14526) = { + .name = "extcon_max14526", + .id = UCLASS_EXTCON, + .of_match = max14526_ids, + .probe = max14526_probe, + .priv_auto = sizeof(struct max14526_priv), +}; diff --git a/drivers/extcon/extcon-sandbox.c b/drivers/extcon/extcon-sandbox.c new file mode 100644 index 00000000000..ab6a6c1cfdc --- /dev/null +++ b/drivers/extcon/extcon-sandbox.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> + +static const struct udevice_id sandbox_extcon_ids[] = { + { .compatible = "sandbox,extcon" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(extcon_sandbox) = { + .name = "extcon_sandbox", + .id = UCLASS_EXTCON, + .of_match = sandbox_extcon_ids, +}; diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c new file mode 100644 index 00000000000..9dd22b57626 --- /dev/null +++ b/drivers/extcon/extcon-uclass.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#define LOG_CATEGORY UCLASS_EXTCON + +#include <common.h> +#include <extcon.h> +#include <dm.h> + +UCLASS_DRIVER(extcon) = { + .id = UCLASS_EXTCON, + .name = "extcon", + .per_device_plat_auto = sizeof(struct extcon_uc_plat), +}; diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index eefa34779c4..a3df9aa3d0f 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -4,6 +4,13 @@ config FASTBOOT bool imply ANDROID_BOOT_IMAGE imply CMD_FASTBOOT + help + Fastboot is a protocol used in Android devices for + communicating between the device and a computer during + the bootloader stage. It allows the user to flash the + device firmware and unlock the bootloader. + More information about the protocol and usecases: + https://android.googlesource.com/platform/system/core/+/refs/heads/master/fastboot/ config USB_FUNCTION_FASTBOOT bool "Enable USB fastboot gadget" @@ -28,6 +35,13 @@ config UDP_FUNCTION_FASTBOOT_PORT help The fastboot protocol requires a UDP port number. +config TCP_FUNCTION_FASTBOOT + depends on NET + select FASTBOOT + bool "Enable fastboot protocol over TCP" + help + This enables the fastboot protocol over TCP. + if FASTBOOT config FASTBOOT_BUF_ADDR diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 57b6182c46a..621146bc6b0 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -15,7 +15,7 @@ #include <command.h> #include <env.h> #include <fastboot.h> -#include <net/fastboot.h> +#include <net.h> /** * fastboot_buf_addr - base address of the fastboot download buffer @@ -157,6 +157,37 @@ void fastboot_boot(void) } /** + * fastboot_handle_boot() - Shared implementation of system reaction to + * fastboot commands + * + * Making desceisions about device boot state (stay in fastboot, reboot + * to bootloader, reboot to OS, etc). + */ +void fastboot_handle_boot(int command, bool success) +{ + if (!success) + return; + + switch (command) { + case FASTBOOT_COMMAND_BOOT: + fastboot_boot(); + net_set_state(NETLOOP_SUCCESS); + break; + + case FASTBOOT_COMMAND_CONTINUE: + net_set_state(NETLOOP_SUCCESS); + break; + + case FASTBOOT_COMMAND_REBOOT: + case FASTBOOT_COMMAND_REBOOT_BOOTLOADER: + case FASTBOOT_COMMAND_REBOOT_FASTBOOTD: + case FASTBOOT_COMMAND_REBOOT_RECOVERY: + do_reset(NULL, 0, 0, NULL); + break; + } +} + +/** * fastboot_set_progress_callback() - set progress callback * * @progress: Pointer to progress callback diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 4e1ae03e9fd..04460f1acb2 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -511,6 +511,13 @@ config WINBOND_W83627 legacy UART or other devices in the Winbond Super IO chips on X86 platforms. +config QCOM_GENI_SE + bool "Qualcomm GENI Serial Engine Driver" + depends on ARCH_SNAPDRAGON + help + The driver manages Generic Interface (GENI) firmware based + Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. + config QFW bool help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 3b792f2a14c..52aed096021 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o +obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o ifdef CONFIG_QFW obj-y += qfw.o obj-$(CONFIG_QFW_PIO) += qfw_pio.o diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c index a195dc5eb1d..b971f32f6a1 100644 --- a/drivers/misc/esm_pmic.c +++ b/drivers/misc/esm_pmic.c @@ -26,6 +26,9 @@ #define ESM_MCU_EN BIT(6) #define ESM_MCU_ENDRV BIT(5) +#define ESM_MCU_MASK_REG 0x59 +#define ESM_MCU_MASK 0x7 + /** * pmic_esm_probe: configures and enables PMIC ESM functionality * @@ -48,6 +51,12 @@ static int pmic_esm_probe(struct udevice *dev) return ret; } + ret = pmic_reg_write(dev->parent, ESM_MCU_MASK_REG, ESM_MCU_MASK); + if (ret) { + dev_err(dev, "clearing ESM masks failed: %d\n", ret); + return ret; + } + ret = pmic_reg_write(dev->parent, ESM_MCU_START_REG, ESM_MCU_START); if (ret) { dev_err(dev, "starting ESM failed: %d\n", ret); diff --git a/drivers/misc/qcom-geni-se.c b/drivers/misc/qcom-geni-se.c new file mode 100644 index 00000000000..281a5ec819a --- /dev/null +++ b/drivers/misc/qcom-geni-se.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper + * + * Copyright (C) 2023 Linaro Ltd. <vladimir.zapolskiy@linaro.org> + */ + +#include <common.h> +#include <dm.h> +#include <misc.h> +#include <asm/io.h> + +static int geni_se_qup_read(struct udevice *dev, int offset, + void *buf, int size) +{ + fdt_addr_t base = dev_read_addr(dev); + + if (size != sizeof(u32)) + return -EINVAL; + + *(u32 *)buf = readl(base + offset); + + return size; +} + +static struct misc_ops geni_se_qup_ops = { + .read = geni_se_qup_read, +}; + +static const struct udevice_id geni_se_qup_ids[] = { + { .compatible = "qcom,geni-se-qup" }, + {} +}; + +U_BOOT_DRIVER(geni_se_qup) = { + .name = "geni_se_qup", + .id = UCLASS_MISC, + .of_match = geni_se_qup_ids, + .ops = &geni_se_qup_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index 2cec5b9ae32..71962cd47e0 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -100,6 +100,8 @@ static const struct udevice_id hi6220_dwmmc_ids[] = { .data = (ulong)&hi6220_mmc_data }, { .compatible = "hisilicon,hi3798cv200-dw-mshc", .data = (ulong)&hi6220_mmc_data }, + { .compatible = "hisilicon,hi3798mv200-dw-mshc", + .data = (ulong)&hi6220_mmc_data }, { .compatible = "hisilicon,hi3660-dw-mshc", .data = (ulong)&hi3660_mmc_data }, { } diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2c3116ee530..6093277f171 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -669,6 +669,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; + fallthrough; case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: @@ -903,6 +904,30 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) } #endif +/** + * spi_nor_erase_chip() - Erase the entire flash memory. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_erase_chip(struct spi_nor *nor) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + int ret; + + spi_nor_setup_op(nor, &op, nor->write_proto); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + return nor->mtd.size; +} + /* * Initiate the erasure of a single sector. Returns the number of bytes erased * on success, a negative error code on error. @@ -974,7 +999,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) if (ret < 0) goto erase_err; - ret = spi_nor_erase_sector(nor, addr); + if (len == mtd->size && + !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + ret = spi_nor_erase_chip(nor); + } else { + ret = spi_nor_erase_sector(nor, addr); + } if (ret < 0) goto erase_err; @@ -3199,6 +3229,87 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, /* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */ #define S25FS256T_ID4 (0x08) +/* Number of dummy cycle for Read Any Register (RDAR) op. */ +#define S25FS_S_RDAR_DUMMY 8 + +static int s25fs_s_quad_enable(struct spi_nor *nor) +{ + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); +} + +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 8 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K); +} + +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* Bank Address Register is not supported */ + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) + return -EOPNOTSUPP; + + /* + * Read CR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25fs_s_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25fs_s_default_init(struct spi_nor *nor) +{ + nor->setup = s25fs_s_setup; +} + +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = nor->info->sector_size; + + /* The S25FS-S chip family reports 512-byte pages in BFPT but + * in reality the write buffer still wraps at the safe default + * of 256 bytes. Overwrite the page size advertised by BFPT + * to get the writes working. + */ + params->page_size = 256; + + return 0; +} + +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_1_1_2 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + /* READ_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25fs_s_quad_enable; +} + +static struct spi_nor_fixups s25fs_s_fixups = { + .default_init = s25fs_s_default_init, + .post_bfpt = s25fs_s_post_bfpt_fixup, + .post_sfdp = s25fs_s_post_sfdp_fixup, +}; + static int s25_mdp_ready(struct spi_nor *nor) { u32 addr; @@ -3897,6 +4008,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) && !strcmp(nor->info->name, "s25fl256l")) nor->fixups = &s25fl256l_fixups; + + /* For FS-S (family ID = 0x81) */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 0x81) + nor->fixups = &s25fs_s_fixups; #endif #ifdef CONFIG_SPI_FLASH_MT35XU diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index ec58697b311..9bbba6eed07 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -794,9 +794,21 @@ static int eqos_start(struct udevice *dev) */ if (!eqos->phy) { int addr = -1; - addr = eqos_get_phy_addr(eqos, dev); - eqos->phy = phy_connect(eqos->mii, addr, dev, - eqos->config->interface(dev)); + ofnode fixed_node; + + if (IS_ENABLED(CONFIG_PHY_FIXED)) { + fixed_node = ofnode_find_subnode(dev_ofnode(dev), + "fixed-link"); + if (ofnode_valid(fixed_node)) + eqos->phy = fixed_phy_create(dev_ofnode(dev)); + } + + if (!eqos->phy) { + addr = eqos_get_phy_addr(eqos, dev); + eqos->phy = phy_connect(eqos->mii, addr, dev, + eqos->config->interface(dev)); + } + if (!eqos->phy) { pr_err("phy_connect() failed"); goto err_stop_resets; diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 4f84403d956..78a40f285aa 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -29,6 +29,7 @@ #include <fsl-mc/fsl_dpsparser.h> #include <fsl-mc/fsl_qbman_portal.h> #include <fsl-mc/ldpaa_wriop.h> +#include <net/ldpaa_eth.h> #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024) #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1)) @@ -383,37 +384,31 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type) { - int i, err = 0, ret = 0; -#define ETH_NAME_LEN 20 struct udevice *eth_dev; - char ethname[ETH_NAME_LEN]; - - for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { - /* port not enabled */ - if (wriop_is_enabled_dpmac(i) != 1) - continue; - - snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i, - phy_interface_strings[wriop_get_enet_if(i)]); - - eth_dev = eth_get_dev_by_name(ethname); - if (eth_dev == NULL) + int err = 0, ret = 0; + struct uclass *uc; + uint32_t dpmac_id; + + uclass_get(UCLASS_ETH, &uc); + uclass_foreach_dev(eth_dev, uc) { + if (!eth_dev->driver || !eth_dev->driver->name || + strcmp(eth_dev->driver->name, LDPAA_ETH_DRIVER_NAME)) continue; + dpmac_id = ldpaa_eth_get_dpmac_id(eth_dev); switch (type) { case MC_FIXUP_DPL: - err = mc_fixup_dpl_mac_addr(blob, i, eth_dev); + err = mc_fixup_dpl_mac_addr(blob, dpmac_id, eth_dev); break; case MC_FIXUP_DPC: - err = mc_fixup_dpc_mac_addr(blob, i, eth_dev); + err = mc_fixup_dpc_mac_addr(blob, dpmac_id, eth_dev); break; default: break; } if (err) - printf("fsl-mc: ERROR fixing mac address for %s\n", - ethname); + printf("fsl-mc: ERROR fixing mac address for %s\n", eth_dev->name); ret |= err; } diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c index fb5c76c600b..6b59b5fcd26 100644 --- a/drivers/net/ksz9477.c +++ b/drivers/net/ksz9477.c @@ -337,11 +337,21 @@ static int ksz_port_setup(struct udevice *dev, int port, return 0; } +static int ksz_port_probe(struct udevice *dev, int port, struct phy_device *phy) +{ + int supported = PHY_GBIT_FEATURES; + + /* configure phy */ + phy->supported &= supported; + phy->advertising &= supported; + + return phy_config(phy); +} + static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy) { struct dsa_pdata *pdata = dev_get_uclass_plat(dev); struct ksz_dsa_priv *priv = dev_get_priv(dev); - int supported = PHY_GBIT_FEATURES; u8 data8; int ret; @@ -365,23 +375,12 @@ static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy if (port == pdata->cpu_port) return 0; - /* configure phy */ - phy->supported &= supported; - phy->advertising &= supported; - ret = phy_config(phy); - if (ret) - return ret; - - ret = phy_startup(phy); - if (ret) - return ret; - /* start switch */ ksz_read8(priv->dev, REG_SW_OPERATION, &data8); data8 |= SW_START; ksz_write8(priv->dev, REG_SW_OPERATION, data8); - return 0; + return phy_startup(phy); } static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *phy) @@ -410,6 +409,7 @@ static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *p } static const struct dsa_ops ksz_dsa_ops = { + .port_probe = ksz_port_probe, .port_enable = ksz_port_enable, .port_disable = ksz_port_disable, }; @@ -443,15 +443,10 @@ static int ksz_i2c_probe(struct udevice *dev) { struct dsa_pdata *pdata = dev_get_uclass_plat(dev); struct ksz_dsa_priv *priv = dev_get_priv(dev); - struct udevice *master = dsa_get_master(dev); int i, ret; u8 data8; u32 id; - if (!master) - return -ENODEV; - - dev_dbg(dev, "%s %s master:%s\n", __func__, dev->name, master->name); dev_set_parent_priv(dev, priv); ret = i2c_set_chip_offset_len(dev, 2); @@ -501,8 +496,6 @@ static int ksz_i2c_probe(struct udevice *dev) ksz_pwrite8(priv->dev, i, REG_PORT_MSTP_STATE, data8); } - dsa_set_tagging(dev, 0, 0); - return 0; }; diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 24850777949..2cb6e9b7d70 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include <common.h> @@ -21,6 +21,7 @@ #include <linux/compat.h> #include <linux/delay.h> #include <asm/global_data.h> +#include <net/ldpaa_eth.h> #include "ldpaa_eth.h" #ifdef CONFIG_PHYLIB @@ -995,7 +996,7 @@ static int ldpaa_eth_probe(struct udevice *dev) return 0; } -static uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev) +uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev) { int port_node = dev_of_offset(dev); @@ -1049,7 +1050,7 @@ static const struct udevice_id ldpaa_eth_of_ids[] = { }; U_BOOT_DRIVER(ldpaa_eth) = { - .name = "ldpaa_eth", + .name = LDPAA_ETH_DRIVER_NAME, .id = UCLASS_ETH, .of_match = ldpaa_eth_of_ids, .of_to_plat = ldpaa_eth_of_to_plat, diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index ea98cfcc1b5..36c70da181a 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -162,18 +162,6 @@ static int bcm5482_config(struct phy_device *phydev) return 0; } -static int bcm_cygnus_startup(struct phy_device *phydev) -{ - int ret; - - /* Read the Status (2x to make sure link is right) */ - ret = genphy_update_link(phydev); - if (ret) - return ret; - - return genphy_parse_link(phydev); -} - static void bcm_cygnus_afe(struct phy_device *phydev) { /* ensures smdspclk is enabled */ @@ -359,6 +347,6 @@ U_BOOT_PHY_DRIVER(bcm_cygnus) = { .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, .config = &bcm_cygnus_config, - .startup = &bcm_cygnus_startup, + .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index b861bf7cef3..7111e36aa0d 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -330,7 +330,7 @@ static int dp83867_config(struct phy_device *phydev) DP83867_RGMIIDCTL, delay); } - if (phy_interface_is_sgmii(phydev)) { + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { if (dp83867->sgmii_ref_clk_en) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, DP83867_SGMII_TYPE); diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index 8864f99bb32..a715e83db98 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -39,7 +39,7 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, if (!IS_ENABLED(CONFIG_DM_ETH_PHY)) { ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio, - GPIOD_ACTIVE_LOW); + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); if (!ret) { assert = ofnode_read_u32_default(node, "reset-assert-us", 0); diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 247d9753a88..396cac76d63 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -384,17 +384,6 @@ static int rtl8211x_startup(struct phy_device *phydev) return rtl8211x_parse_status(phydev); } -static int rtl8211e_startup(struct phy_device *phydev) -{ - int ret; - - ret = genphy_update_link(phydev); - if (ret) - return ret; - - return genphy_parse_link(phydev); -} - static int rtl8211f_startup(struct phy_device *phydev) { int ret; @@ -428,7 +417,7 @@ U_BOOT_PHY_DRIVER(rtl8211e) = { .features = PHY_GBIT_FEATURES, .probe = &rtl8211e_probe, .config = &rtl8211e_config, - .startup = &rtl8211e_startup, + .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; @@ -465,6 +454,6 @@ U_BOOT_PHY_DRIVER(rtl8201f) = { .features = PHY_BASIC_FEATURES, .probe = &rtl8210f_probe, .config = &rtl8201f_config, - .startup = &rtl8211e_startup, + .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index 0b7436a7e1e..e2969bc4842 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -48,7 +48,14 @@ static int xilinxgmiitorgmii_config(struct phy_device *phydev) return -EINVAL; } - ext_phydev->interface = PHY_INTERFACE_MODE_RGMII; + ext_phydev->interface = ofnode_read_phy_mode(node); + if (ext_phydev->interface == PHY_INTERFACE_MODE_NA) { + ext_phydev->interface = PHY_INTERFACE_MODE_RGMII; + } else if (!phy_interface_is_rgmii(ext_phydev)) { + printf("Incorrect external interface type\n"); + return -EINVAL; + } + ext_phydev->node = phandle.node; phydev->priv = ext_phydev; diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index c9c07a5a8ff..2276a465e78 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -118,9 +118,9 @@ enum RTL8169_registers { FLASH = 0x30, ERSR = 0x36, ChipCmd = 0x37, - TxPoll = 0x38, - IntrMask = 0x3C, - IntrStatus = 0x3E, + TxPoll_8169 = 0x38, + IntrMask_8169 = 0x3C, + IntrStatus_8169 = 0x3E, TxConfig = 0x40, RxConfig = 0x44, RxMissed = 0x4C, @@ -148,6 +148,12 @@ enum RTL8169_registers { FuncForceEvent = 0xFC, }; +enum RTL8125_registers { + IntrMask_8125 = 0x38, + IntrStatus_8125 = 0x3C, + TxPoll_8125 = 0x90, +}; + enum RTL8169_register_content { /*InterruptStatusBits */ SYSErr = 0x8000, @@ -263,6 +269,7 @@ static struct { {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, {"RTL-8168h/8111h", 0x54, 0xff7e1880,}, + {"RTL-8125B", 0x64, 0xff7e1880,}, }; enum _DescStatusBit { @@ -347,6 +354,7 @@ static struct pci_device_id supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) }, {} }; @@ -517,6 +525,7 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, /* return true if there's an ethernet packet ready to read */ /* nic->packet should contain data on return */ /* nic->packetlen should contain length of data */ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); int cur_rx; int length = 0; @@ -558,6 +567,10 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, return length; } else { + u32 IntrStatus = IntrStatus_8169; + + if (pplat->device == 0x8125) + IntrStatus = IntrStatus_8125; ushort sts = RTL_R8(IntrStatus); RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); udelay(100); /* wait */ @@ -582,6 +595,7 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, { /* send the packet to destination */ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); u32 to; u8 *ptxb; int entry = tpc->cur_tx % NUM_TX_DESC; @@ -618,7 +632,10 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, ((len > ETH_ZLEN) ? len : ETH_ZLEN)); } rtl_flush_tx_desc(&tpc->TxDescArray[entry]); - RTL_W8(TxPoll, 0x40); /* set polling bit */ + if (pplat->device == 0x8125) + RTL_W8(TxPoll_8125, 0x1); /* set polling bit */ + else + RTL_W8(TxPoll_8169, 0x40); /* set polling bit */ tpc->cur_tx++; to = currticks() + TX_TIMEOUT; @@ -824,21 +841,26 @@ static int rtl8169_eth_start(struct udevice *dev) return 0; } -static void rtl_halt_common(unsigned long dev_iobase) +static void rtl_halt_common(struct udevice *dev) { + struct rtl8169_private *priv = dev_get_priv(dev); + struct pci_child_plat *pplat = dev_get_parent_plat(dev); int i; #ifdef DEBUG_RTL8169 printf ("%s\n", __FUNCTION__); #endif - ioaddr = dev_iobase; + ioaddr = priv->iobase; /* Stop the chip's Tx and Rx DMA processes. */ RTL_W8(ChipCmd, 0x00); /* Disable interrupts by clearing the interrupt mask. */ - RTL_W16(IntrMask, 0x0000); + if (pplat->device == 0x8125) + RTL_W16(IntrMask_8125, 0x0000); + else + RTL_W16(IntrMask_8169, 0x0000); RTL_W32(RxMissed, 0); @@ -849,9 +871,7 @@ static void rtl_halt_common(unsigned long dev_iobase) void rtl8169_eth_stop(struct udevice *dev) { - struct rtl8169_private *priv = dev_get_priv(dev); - - rtl_halt_common(priv->iobase); + rtl_halt_common(dev); } static int rtl8169_write_hwaddr(struct udevice *dev) @@ -1025,23 +1045,25 @@ static int rtl8169_eth_probe(struct udevice *dev) struct pci_child_plat *pplat = dev_get_parent_plat(dev); struct rtl8169_private *priv = dev_get_priv(dev); struct eth_pdata *plat = dev_get_plat(dev); - u32 iobase; int region; int ret; - debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); switch (pplat->device) { case 0x8168: + case 0x8125: region = 2; break; default: region = 1; break; } - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase); - iobase &= ~0xf; - priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase); + priv->iobase = (ulong)dm_pci_map_bar(dev, + PCI_BASE_ADDRESS_0 + region * 4, + 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + + debug("rtl8169: REALTEK RTL8169 @0x%lx\n", priv->iobase); ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); if (ret < 0) { printf(pr_fmt("failed to initialize card: %d\n"), ret); diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 14fd3bbf679..01230360bad 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -580,10 +580,6 @@ int dm_pciauto_config_device(struct udevice *dev) break; #endif - case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ - debug("PCI AutoConfig: Found PowerPC device\n"); - /* fall through */ - default: dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); break; diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 8a81a74067e..249cfe66466 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -22,10 +22,33 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf, struct mpc85xx_pci_priv *priv = dev_get_priv(dev); u32 addr; - addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); + if (offset > 0xff) { + *value = pci_get_ff(size); + return 0; + } + + /* Skip mpc85xx PCI controller's ATMU inbound registers */ + if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) { + *value = 0; + return 0; + } + + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); - *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size); + + switch (size) { + case PCI_SIZE_8: + *value = in_8(priv->cfg_data + (offset & 3)); + break; + case PCI_SIZE_16: + *value = in_le16(priv->cfg_data + (offset & 2)); + break; + case PCI_SIZE_32: + *value = in_le32(priv->cfg_data); + break; + } return 0; } @@ -37,10 +60,30 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf, struct mpc85xx_pci_priv *priv = dev_get_priv(dev); u32 addr; - addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); + if (offset > 0xff) + return 0; + + /* Skip mpc85xx PCI controller's ATMU inbound registers */ + if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) + return 0; + + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); - out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size)); + + switch (size) { + case PCI_SIZE_8: + out_8(priv->cfg_data + (offset & 3), value); + break; + case PCI_SIZE_16: + out_le16(priv->cfg_data + (offset & 2), value); + break; + case PCI_SIZE_32: + out_le32(priv->cfg_data, value); + break; + } + sync(); return 0; } diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4600652f2b1..8d89a1e5919 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -58,6 +58,14 @@ static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } + /* Skip Freescale PCIe controller's PEXCSRBAR register */ + if (PCI_BUS(bdf) - dev_seq(bus) == 0 && + PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) == PCI_BASE_ADDRESS_0) { + *valuep = 0; + return 0; + } + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), PCI_DEV(bdf), PCI_FUNC(bdf), offset); @@ -95,6 +103,12 @@ static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, if (fsl_pcie_addr_valid(pcie, bdf)) return 0; + /* Skip Freescale PCIe controller's PEXCSRBAR register */ + if (PCI_BUS(bdf) - dev_seq(bus) == 0 && + PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) == PCI_BASE_ADDRESS_0) + return 0; + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), PCI_DEV(bdf), PCI_FUNC(bdf), offset); diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 17969e2f236..6a5bf88da23 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -403,6 +403,7 @@ static const struct ls_pcie_drvdata ls1028a_drvdata = { static const struct udevice_id ls_pcie_ids[] = { { .compatible = "fsl,ls-pcie" }, { .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = (ulong)&ls1028a_drvdata }, { } }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 47e2d67426f..5a4d58b3272 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -349,10 +349,10 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, { int err; - /* try pupd_r1_r0 if pullen_pullsel return error */ + /* set pupd_r1_r0 if pullen_pullsel succeeded */ err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, val); - if (err) + if (!err) return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, pullup, val); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 10d07daf277..7faf6784442 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -946,6 +946,8 @@ config MSM_SERIAL config MSM_GENI_SERIAL bool "Qualcomm on-chip GENI UART" + select MISC + imply QCOM_GENI_SE help Support UART based on Generic Interface (GENI) Serial Engine (SE), used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 3943ca43e49..78fd9389c03 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -11,15 +11,10 @@ #include <clk.h> #include <common.h> #include <dm.h> -#include <dm/pinctrl.h> #include <errno.h> -#include <linux/compiler.h> -#include <log.h> #include <linux/delay.h> -#include <malloc.h> +#include <misc.h> #include <serial.h> -#include <watchdog.h> -#include <linux/bug.h> #define UART_OVERSAMPLING 32 #define STALE_TIMEOUT 160 @@ -116,6 +111,10 @@ #define TX_FIFO_DEPTH_MSK (GENMASK(21, 16)) #define TX_FIFO_DEPTH_SHFT 16 +/* GENI SE QUP Registers */ +#define QUP_HW_VER_REG 0x4 +#define QUP_SE_VERSION_2_5 0x20050000 + /* * Predefined packing configuration of the serial engine (CFG0, CFG1 regs) * for uart mode. @@ -133,11 +132,12 @@ DECLARE_GLOBAL_DATA_PTR; struct msm_serial_data { phys_addr_t base; u32 baud; + u32 oversampling; }; unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, - 32000000, 48000000, 64000000, 80000000, - 96000000, 100000000}; + 32000000, 48000000, 64000000, 80000000, + 96000000, 100000000}; /** * get_clk_cfg() - Get clock rate to apply on clock supplier. @@ -166,8 +166,7 @@ static int get_clk_cfg(unsigned long clk_freq) * * Return: frequency, supported by clock supplier, multiple of clk_freq. */ -static int get_clk_div_rate(u32 baud, - u64 sampling_rate, u32 *clk_div) +static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div) { unsigned long ser_clk; unsigned long desired_clk; @@ -189,7 +188,7 @@ static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate) struct clk *clk; int ret; - clk = devm_clk_get(dev, "se-clk"); + clk = devm_clk_get(dev, NULL); if (!clk) return -EINVAL; @@ -234,7 +233,7 @@ static inline u32 geni_se_get_tx_fifo_width(long base) } static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div, - int baud) + int baud) { u32 s_clk_cfg = 0; @@ -245,15 +244,15 @@ static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div, writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG); } -int msm_serial_setbrg(struct udevice *dev, int baud) +static int msm_serial_setbrg(struct udevice *dev, int baud) { struct msm_serial_data *priv = dev_get_priv(dev); + u64 clk_rate; + u32 clk_div; priv->baud = baud; - u32 clk_div; - u64 clk_rate; - clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, &clk_div); + clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div); geni_serial_set_clock_rate(dev, clk_rate); geni_serial_baud(priv->base, clk_div, baud); @@ -274,7 +273,7 @@ int msm_serial_setbrg(struct udevice *dev, int baud) * reached. */ static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset, - int field, bool set) + int field, bool set) { u32 reg; struct msm_serial_data *priv = dev_get_priv(dev); @@ -487,6 +486,31 @@ static const struct dm_serial_ops msm_serial_ops = { .setbrg = msm_serial_setbrg, }; +static void geni_set_oversampling(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + struct udevice *parent_dev = dev_get_parent(dev); + u32 geni_se_version; + int ret; + + priv->oversampling = UART_OVERSAMPLING; + + /* + * It could happen that GENI SE IP is missing in the board's device + * tree or GENI UART node is a direct child of SoC device tree node. + */ + if (device_get_uclass_id(parent_dev) != UCLASS_MISC) + return; + + ret = misc_read(parent_dev, QUP_HW_VER_REG, + &geni_se_version, sizeof(geni_se_version)); + if (ret != sizeof(geni_se_version)) + return; + + if (geni_se_version >= QUP_SE_VERSION_2_5) + priv->oversampling /= 2; +} + static inline void geni_serial_init(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); @@ -530,6 +554,8 @@ static int msm_serial_probe(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); + geni_set_oversampling(dev); + /* No need to reinitialize the UART after relocation */ if (gd->flags & GD_FLG_RELOC) return 0; @@ -554,7 +580,9 @@ static int msm_serial_ofdata_to_platdata(struct udevice *dev) } static const struct udevice_id msm_serial_ids[] = { - {.compatible = "qcom,msm-geni-uart"}, {}}; + { .compatible = "qcom,geni-debug-uart" }, + { } +}; U_BOOT_DRIVER(serial_msm_geni) = { .name = "serial_msm_geni", @@ -564,6 +592,7 @@ U_BOOT_DRIVER(serial_msm_geni) = { .priv_auto = sizeof(struct msm_serial_data), .probe = msm_serial_probe, .ops = &msm_serial_ops, + .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_MSM_GENI diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c7f10c50132..f931e4cf3e2 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -312,13 +312,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, * which is unsupported on some flash devices during register * reads, prefer STIG mode for such small reads. */ - if (!op->addr.nbytes || - op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) + if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) mode = CQSPI_STIG_READ; else mode = CQSPI_READ; } else { - if (!op->addr.nbytes || !op->data.buf.out) + if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) mode = CQSPI_STIG_WRITE; else mode = CQSPI_WRITE; @@ -362,8 +361,15 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave, { bool all_true, all_false; - all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && - op->data.dtr; + /* + * op->dummy.dtr is required for converting nbytes into ncycles. + * Also, don't check the dtr field of the op phase having zero nbytes. + */ + all_true = op->cmd.dtr && + (!op->addr.nbytes || op->addr.dtr) && + (!op->dummy.nbytes || op->dummy.dtr) && + (!op->data.nbytes || op->data.dtr); + all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && !op->data.dtr; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 21fe2e655c5..9ce2c0f254f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -120,7 +120,16 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv, { int ret; - priv->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr; + /* + * For an op to be DTR, cmd phase along with every other non-empty + * phase should have dtr field set to 1. If an op phase has zero + * nbytes, ignore its dtr field; otherwise, check its dtr field. + * Also, dummy checks not performed here Since supports_op() + * already checks that all or none of the fields are DTR. + */ + priv->dtr = op->cmd.dtr && + (!op->addr.nbytes || op->addr.dtr) && + (!op->data.nbytes || op->data.dtr); ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth); if (ret < 0) @@ -367,6 +376,9 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) if (!cadence_qspi_wait_idle(reg_base)) return -EIO; + /* Flush the CMDCTRL reg after the execution */ + writel(0, reg_base + CQSPI_REG_CMDCTRL); + return 0; } @@ -453,11 +465,6 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, unsigned int dummy_clk; u8 opcode; - if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { - printf("QSPI: Invalid input arguments rxlen %u\n", rxlen); - return -EINVAL; - } - if (priv->dtr) opcode = op->cmd.opcode >> 8; else @@ -540,26 +547,12 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, unsigned int reg = 0; unsigned int wr_data; unsigned int wr_len; + unsigned int dummy_clk; unsigned int txlen = op->data.nbytes; const void *txbuf = op->data.buf.out; void *reg_base = priv->regbase; - u32 addr; u8 opcode; - /* Reorder address to SPI bus order if only transferring address */ - if (!txlen) { - addr = cpu_to_be32(op->addr.val); - if (op->addr.nbytes == 3) - addr >>= 8; - txbuf = &addr; - txlen = op->addr.nbytes; - } - - if (txlen > CQSPI_STIG_DATA_LEN_MAX) { - printf("QSPI: Invalid input arguments txlen %u\n", txlen); - return -EINVAL; - } - if (priv->dtr) opcode = op->cmd.opcode >> 8; else @@ -567,6 +560,27 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS); + /* + * address bytes are zero indexed + */ + reg |= (((op->addr.nbytes - 1) & + CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB); + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + } + + /* Set up dummy cycles. */ + dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr); + if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) + return -EOPNOTSUPP; + + if (dummy_clk) + reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) + << CQSPI_REG_CMDCTRL_DUMMY_LSB; + if (txlen) { /* writing data = yes */ reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c index 7000fe5860d..73c506442ae 100644 --- a/drivers/spi/npcm_fiu_spi.c +++ b/drivers/spi/npcm_fiu_spi.c @@ -11,6 +11,7 @@ #include <linux/bitfield.h> #include <linux/log2.h> #include <linux/iopoll.h> +#include <power/regulator.h> #define DW_SIZE 4 #define CHUNK_SIZE 16 @@ -34,6 +35,34 @@ #define UMA_CTS_RDYST BIT(24) #define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8) +/* Direct Write Configuration Register */ +#define DWR_CFG_WBURST_MASK GENMASK(25, 24) +#define DWR_CFG_ADDSIZ_MASK GENMASK(17, 16) +#define DWR_CFG_ABPCK_MASK GENMASK(11, 10) +#define DRW_CFG_DBPCK_MASK GENMASK(9, 8) +#define DRW_CFG_WRCMD 2 +enum { + DWR_WBURST_1_BYTE, + DWR_WBURST_16_BYTE = 3, +}; + +enum { + DWR_ADDSIZ_24_BIT, + DWR_ADDSIZ_32_BIT, +}; + +enum { + DWR_ABPCK_BIT_PER_CLK, + DWR_ABPCK_2_BIT_PER_CLK, + DWR_ABPCK_4_BIT_PER_CLK, +}; + +enum { + DWR_DBPCK_BIT_PER_CLK, + DWR_DBPCK_2_BIT_PER_CLK, + DWR_DBPCK_4_BIT_PER_CLK, +}; + struct npcm_fiu_regs { unsigned int drd_cfg; unsigned int dwr_cfg; @@ -67,19 +96,10 @@ struct npcm_fiu_regs { struct npcm_fiu_priv { struct npcm_fiu_regs *regs; - struct clk clk; }; static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed) { - struct npcm_fiu_priv *priv = dev_get_priv(bus); - int ret; - - debug("%s: set speed %u\n", bus->name, speed); - ret = clk_set_rate(&priv->clk, speed); - if (ret < 0) - return ret; - return 0; } @@ -349,13 +369,38 @@ static int npcm_fiu_exec_op(struct spi_slave *slave, static int npcm_fiu_spi_probe(struct udevice *bus) { struct npcm_fiu_priv *priv = dev_get_priv(bus); - int ret; + struct udevice *vqspi_supply; + int vqspi_uv; priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus); - ret = clk_get_by_index(bus, 0, &priv->clk); - if (ret < 0) - return ret; + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + device_get_supply_regulator(bus, "vqspi-supply", &vqspi_supply); + vqspi_uv = dev_read_u32_default(bus, "vqspi-microvolt", 0); + /* Set IO voltage */ + if (vqspi_supply && vqspi_uv) + regulator_set_value(vqspi_supply, vqspi_uv); + } + + return 0; +} + +static int npcm_fiu_spi_bind(struct udevice *bus) +{ + struct npcm_fiu_regs *regs; + + if (dev_read_bool(bus, "nuvoton,spix-mode")) { + regs = dev_read_addr_ptr(bus); + if (!regs) + return -EINVAL; + + /* Setup direct write cfg for SPIX */ + writel(FIELD_PREP(DWR_CFG_WBURST_MASK, DWR_WBURST_16_BYTE) | + FIELD_PREP(DWR_CFG_ADDSIZ_MASK, DWR_ADDSIZ_24_BIT) | + FIELD_PREP(DWR_CFG_ABPCK_MASK, DWR_ABPCK_4_BIT_PER_CLK) | + FIELD_PREP(DRW_CFG_DBPCK_MASK, DWR_DBPCK_4_BIT_PER_CLK) | + DRW_CFG_WRCMD, ®s->dwr_cfg); + } return 0; } @@ -384,4 +429,5 @@ U_BOOT_DRIVER(npcm_fiu_spi) = { .ops = &npcm_fiu_spi_ops, .priv_auto = sizeof(struct npcm_fiu_priv), .probe = npcm_fiu_spi_probe, + .bind = npcm_fiu_spi_bind, }; diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 8e8995fc537..b7eca583595 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -181,8 +181,12 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave, if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2) return false; - if (op->data.dir != SPI_MEM_NO_DATA && - op->dummy.buswidth == 8 && op->data.nbytes % 2) + /* + * Transactions of odd length do not make sense for 8D-8D-8D mode + * because a byte is transferred in just half a cycle. + */ + if (op->data.dir != SPI_MEM_NO_DATA && op->data.dir != SPI_MEM_DATA_IN && + op->data.buswidth == 8 && op->data.nbytes % 2) return false; return spi_mem_check_buswidth(slave, op); diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index ebf2903d3ea..e3633a52608 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -556,7 +556,7 @@ static bool f_ospi_supports_op(struct spi_slave *slave, if (!f_ospi_supports_op_width(op)) return false; - return true; + return spi_mem_default_supports_op(slave, op); } static int f_ospi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 0cae3dfc778..0f5d0a30c39 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) struct udevice *bus = dev->parent; struct synquacer_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 val, div, bus_width; + u32 val, div, bus_width = 1; int rwflag; rwflag = (rx ? 1 : 0) | (tx ? 2 : 0); @@ -211,6 +211,8 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) bus_width = 4; else if (priv->mode & SPI_TX_OCTAL) bus_width = 8; + else + log_warning("SPI mode not configured, setting to byte mode\n"); div = DIV_ROUND_UP(125000000, priv->speed); diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 91633f013a5..fae20838c60 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -703,6 +703,10 @@ static int ehci_usb_probe(struct udevice *dev) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif +#else + ret = generic_setup_phy(dev, &priv->phy, 0); + if (ret) + goto err_regulator; #endif #if CONFIG_IS_ENABLED(DM_REGULATOR) @@ -725,12 +729,6 @@ static int ehci_usb_probe(struct udevice *dev) mdelay(10); -#if defined(CONFIG_PHY) - ret = generic_setup_phy(dev, &priv->phy, 0); - if (ret) - goto err_regulator; -#endif - hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uintptr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 334d64c9485..fcc0e85d2e6 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -466,6 +466,17 @@ config VIDEO_BCM2835 that same resolution (or as near as possible) and 32bpp depth, so that U-Boot can access it with full colour depth. +config VIDEO_LCD_ENDEAVORU + tristate "Endeavoru 720x1280 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for the IPS-LCD panel + module for HTC One X. Driver supports a family of panels, + made at least by 3 vendors (Sharp, Sony and AUO), but set up + using the same DSI command sequence. The panel has a 720x1280 + resolution and uses 24 bit RGB per pixel. + config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI @@ -480,6 +491,24 @@ config VIDEO_LCD_RAYDIUM_RM68200 Say Y here if you want to enable support for Raydium RM68200 720x1280 DSI video mode panel. +config VIDEO_LCD_RENESAS_R61307 + tristate "Renesas R61307 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for KOE tx13d100vm0eaa + IPS-LCD module with Renesas R69328 IC. The panel has a 1024x768 + resolution and uses 24 bit RGB per pixel. + +config VIDEO_LCD_RENESAS_R69328 + tristate "Renesas R69328 720x1280 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for JDI dx12d100vm0eaa + IPS-LCD module with Renesas R69328 IC. The panel has a 720x1280 + resolution and uses 24 bit RGB per pixel. + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" ---help--- @@ -606,6 +635,15 @@ config ATMEL_HLCD help HLCDC supports video output to an attached LCD panel. +config BACKLIGHT_LM3533 + bool "Backlight Driver for LM3533" + depends on BACKLIGHT + select DM_I2C + help + Say Y to enable the backlight driver for National Semiconductor / TI + LM3533 Lighting Power chip. Only Bank A is supported as for now. + Supported backlight level range is from 2 to 255 with step of 1. + source "drivers/video/ti/Kconfig" source "drivers/video/exynos/Kconfig" @@ -886,7 +924,7 @@ endif # SPLASH_SCREEN config VIDEO_BMP_GZIP bool "Gzip compressed BMP image support" - depends on CMD_BMP || SPLASH_SCREEN + depends on BMP || SPLASH_SCREEN help If this option is set, additionally to standard BMP images, gzipped BMP images can be displayed via the @@ -923,4 +961,225 @@ config BMP_32BPP endif # VIDEO +config SPL_VIDEO + bool "Enable driver model support for LCD/video" + depends on SPL_DM + help + The video subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use video drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up video within SPL, and allows the same drivers to be + used as U-Boot proper. + +if SPL_VIDEO +source "drivers/video/tidss/Kconfig" + +config SPL_VIDEO_LOGO + bool "Show the U-Boot logo on the display at SPL" + default y if !SPL_SPLASH_SCREEN + select SPL_VIDEO_BMP_RLE8 + help + This enables showing the U-Boot logo on the display when a video + device is probed. It appears at the top right. The logo itself is at + tools/logos/u-boot_logo.bmp and looks best when the display has a + black background. + +config SPL_SPLASH_SCREEN + bool "Show a splash-screen image at SPL" + help + If this option is set, the environment is checked for a variable + "splashimage" at spl stage. + +config SPL_SYS_WHITE_ON_BLACK + bool "Display console as white on a black background at SPL" + help + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. + +config SPL_VIDEO_PCI_DEFAULT_FB_SIZE + hex "Default framebuffer size to use if no drivers request it at SPL" + default 0x1000000 if X86 && PCI + default 0 if !(X86 && PCI) + help + Generally, video drivers request the amount of memory they need for + the frame buffer when they are bound, by setting the size field in + struct video_uc_plat. That memory is then reserved for use after + relocation. But PCI drivers cannot be bound before relocation unless + they are mentioned in the devicetree. + + With this value set appropriately, it is possible for PCI video + devices to have a framebuffer allocated by U-Boot. + + Note: the framebuffer needs to be large enough to store all pixels at + maximum resolution. For example, at 1920 x 1200 with 32 bits per + pixel, 2560 * 1600 * 32 / 8 = 0xfa0000 bytes are needed. + +config SPL_CONSOLE_SCROLL_LINES + int "Number of lines to scroll the console by at SPL" + default 1 + help + When the console need to be scrolled, this is the number of + lines to scroll by. It defaults to 1. Increasing this makes the + console jump but can help speed up operation when scrolling + is slow. + +config SPL_CONSOLE_NORMAL + bool "Support a simple text console at SPL" + default y + help + Support drawing text on the frame buffer console so that it can be + used as a console. Rotation is not supported by this driver (see + CONFIG_CONSOLE_ROTATION for that). A built-in 8x16 font is used + for the display. + +config SPL_BACKLIGHT + bool "Enable panel backlight uclass support at SPL" + default y + help + This provides backlight uclass driver that enables basic panel + backlight support. + +config SPL_PANEL + bool "Enable panel uclass support at SPL" + default y + help + This provides panel uclass driver that enables basic panel support. + +config SPL_SIMPLE_PANEL + bool "Enable simple panel support at SPL" + depends on SPL_PANEL && SPL_BACKLIGHT && SPL_DM_GPIO + default y + help + This turns on a simple panel driver that enables a compatible + video panel. + +config SPL_SYS_WHITE_ON_BLACK + bool "Display console as white on a black background at SPL" + help + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. + +if SPL_SPLASH_SCREEN + +config SPL_SPLASH_SCREEN_ALIGN + bool "Allow positioning the splash image anywhere on the display at SPL" + help + If this option is set the splash image can be freely positioned + on the screen only at SPL. Environment variable "splashpos" specifies + the position as "x,y". If a positive number is given it is used as + number of pixel from left/top. If a negative number is given it + is used as number of pixel from right/bottom. + +config SPL_SPLASH_SOURCE + bool "Control the source of the splash image at SPL" + help + Use the splash_source.c library. This library provides facilities to + declare board specific splash image locations, routines for loading + splash image from supported locations, and a way of controlling the + selected splash location using the "splashsource" environment + variable. + + This CONFIG works as follows: + + - If splashsource is set to a supported location name as defined by + board code, use that splash location. + - If splashsource is undefined, use the first splash location as + default. + - If splashsource is set to an unsupported value, do not load a splash + screen. + + A splash source location can describe either storage with raw data, a + storage formatted with a file system or a FIT image. In case of a + filesystem, the splash screen data is loaded as a file. The name of + the splash screen file can be controlled with the environment variable + "splashfile". + + To enable loading the splash image from a FIT image, CONFIG_FIT must + be enabled. The FIT image has to start at the 'offset' field address + in the selected splash location. The name of splash image within the + FIT shall be specified by the environment variable "splashfile". + + In case the environment variable "splashfile" is not defined the + default name 'splash.bmp' will be used. + +endif # SPL_SPLASH_SCREEN + +config SPL_VIDEO_BMP_GZIP + bool "Gzip compressed BMP image support at SPL" + depends on SPL_SPLASH_SCREEN || SPL_BMP + help + If this option is set, additionally to standard BMP + images, gzipped BMP images can be displayed via the + splashscreen supportat SPL stage. + +config SPL_VIDEO_LOGO_MAX_SIZE + hex "Maximum size of the bitmap logo in bytes at SPL" + default 0x100000 + help + Sets the maximum uncompressed size of the logo. This is needed when + decompressing a BMP file using the gzip algorithm, since it cannot + read the size from the bitmap header. + +config SPL_VIDEO_BMP_RLE8 + bool "Run length encoded BMP image (RLE8) support at SPL" + help + If this option is set, the 8-bit RLE compressed BMP images + is supported. + +config SPL_BMP_16BPP + bool "16-bit-per-pixel BMP image support at SPL" + help + Support display of bitmaps file with 16-bit-per-pixel + +config SPL_BMP_24BPP + bool "24-bit-per-pixel BMP image support at SPL" + help + Support display of bitmaps file with 24-bit-per-pixel. + +config SPL_BMP_32BPP + bool "32-bit-per-pixel BMP image support at SPL" + help + Support display of bitmaps file with 32-bit-per-pixel. + +config SPL_VIDEO_BPP8 + bool "Support 8-bit-per-pixel displays at SPL" + default y + help + Support drawing text and bitmaps onto a 8-bit-per-pixel display. + Enabling this will include code to support this display. Without + this option, such displays will not be supported and console output + will be empty. + +config SPL_VIDEO_BPP16 + bool "Support 16-bit-per-pixel displays at SPL" + default y + help + Support drawing text and bitmaps onto a 16-bit-per-pixel display. + Enabling this will include code to support this display. Without + this option, such displays will not be supported and console output + will be empty. + +config SPL_VIDEO_BPP32 + bool "Support 32-bit-per-pixel displays at SPL" + default y + help + Support drawing text and bitmaps onto a 32-bit-per-pixel display. + Enabling this will include code to support this display. Without + this option, such displays will not be supported and console output + will be empty. + +config SPL_HIDE_LOGO_VERSION + bool "Hide the version information on the splash screen at SPL" + help + Normally the U-Boot version string is shown on the display when the + splash screen is enabled. This information is not otherwise visible + since video starts up after U-Boot has displayed the initial banner. + + Enable this option to hide this information. +endif + endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4d75771745d..9a53cd14187 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -4,12 +4,12 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. ifdef CONFIG_DM -obj-$(CONFIG_BACKLIGHT) += backlight-uclass.o +obj-$(CONFIG_$(SPL_TPL_)BACKLIGHT) += backlight-uclass.o obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o -obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o +obj-$(CONFIG_$(SPL_TPL_)CONSOLE_NORMAL) += console_normal.o obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o -ifdef CONFIG_CONSOLE_NORMAL +ifdef CONFIG_$(SPL_TPL_)CONSOLE_NORMAL obj-y += console_core.o else ifdef CONFIG_CONSOLE_ROTATION obj-y += console_core.o @@ -18,21 +18,22 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ obj-$(CONFIG_DISPLAY) += display-uclass.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o -obj-$(CONFIG_VIDEO) += video-uclass.o vidconsole-uclass.o -obj-$(CONFIG_VIDEO) += video_bmp.o -obj-$(CONFIG_PANEL) += panel-uclass.o +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video-uclass.o vidconsole-uclass.o +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video_bmp.o +obj-$(CONFIG_$(SPL_TPL_)PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o -obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o +obj-$(CONFIG_$(SPL_TPL_)SIMPLE_PANEL) += simple_panel.o obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o endif +obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ -obj-${CONFIG_VIDEO_TIDSS} += tidss/ +obj-${CONFIG_$(SPL_)VIDEO_TIDSS} += tidss/ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o @@ -52,9 +53,12 @@ obj-$(CONFIG_VIDEO_EFI) += efi.o obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o +obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o +obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o +obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index 765f7380b89..2311ca2d1a5 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -33,3 +33,10 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345 help The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD panel to be connected to an parallel LCD interface. + +config VIDEO_BRIDGE_SOLOMON_SSD2825 + bool "Solomon SSD2825 bridge driver" + depends on PANEL && DM_GPIO + select VIDEO_MIPI_DSI + help + Solomon SSD2824 SPI RGB-DSI bridge driver wrapped into panel uClass. diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile index 45e54ac1768..22625c8bc67 100644 --- a/drivers/video/bridge/Makefile +++ b/drivers/video/bridge/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o +obj-$(CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825) += ssd2825.o diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c new file mode 100644 index 00000000000..cea20dcffa5 --- /dev/null +++ b/drivers/video/bridge/ssd2825.c @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <log.h> +#include <misc.h> +#include <mipi_display.h> +#include <mipi_dsi.h> +#include <backlight.h> +#include <panel.h> +#include <spi.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <asm/gpio.h> + +#define SSD2825_DEVICE_ID_REG 0xB0 +#define SSD2825_RGB_INTERFACE_CTRL_REG_1 0xB1 +#define SSD2825_RGB_INTERFACE_CTRL_REG_2 0xB2 +#define SSD2825_RGB_INTERFACE_CTRL_REG_3 0xB3 +#define SSD2825_RGB_INTERFACE_CTRL_REG_4 0xB4 +#define SSD2825_RGB_INTERFACE_CTRL_REG_5 0xB5 +#define SSD2825_RGB_INTERFACE_CTRL_REG_6 0xB6 +#define SSD2825_NON_BURST BIT(2) +#define SSD2825_BURST BIT(3) +#define SSD2825_PCKL_HIGH BIT(13) +#define SSD2825_HSYNC_HIGH BIT(14) +#define SSD2825_VSYNC_HIGH BIT(15) +#define SSD2825_CONFIGURATION_REG 0xB7 +#define SSD2825_CONF_REG_HS BIT(0) +#define SSD2825_CONF_REG_CKE BIT(1) +#define SSD2825_CONF_REG_SLP BIT(2) +#define SSD2825_CONF_REG_VEN BIT(3) +#define SSD2825_CONF_REG_HCLK BIT(4) +#define SSD2825_CONF_REG_CSS BIT(5) +#define SSD2825_CONF_REG_DCS BIT(6) +#define SSD2825_CONF_REG_REN BIT(7) +#define SSD2825_CONF_REG_ECD BIT(8) +#define SSD2825_CONF_REG_EOT BIT(9) +#define SSD2825_CONF_REG_LPE BIT(10) +#define SSD2825_VC_CTRL_REG 0xB8 +#define SSD2825_PLL_CTRL_REG 0xB9 +#define SSD2825_PLL_CONFIGURATION_REG 0xBA +#define SSD2825_CLOCK_CTRL_REG 0xBB +#define SSD2825_PACKET_SIZE_CTRL_REG_1 0xBC +#define SSD2825_PACKET_SIZE_CTRL_REG_2 0xBD +#define SSD2825_PACKET_SIZE_CTRL_REG_3 0xBE +#define SSD2825_PACKET_DROP_REG 0xBF +#define SSD2825_OPERATION_CTRL_REG 0xC0 +#define SSD2825_MAX_RETURN_SIZE_REG 0xC1 +#define SSD2825_RETURN_DATA_COUNT_REG 0xC2 +#define SSD2825_ACK_RESPONSE_REG 0xC3 +#define SSD2825_LINE_CTRL_REG 0xC4 +#define SSD2825_INTERRUPT_CTRL_REG 0xC5 +#define SSD2825_INTERRUPT_STATUS_REG 0xC6 +#define SSD2825_ERROR_STATUS_REG 0xC7 +#define SSD2825_DATA_FORMAT_REG 0xC8 +#define SSD2825_DELAY_ADJ_REG_1 0xC9 +#define SSD2825_DELAY_ADJ_REG_2 0xCA +#define SSD2825_DELAY_ADJ_REG_3 0xCB +#define SSD2825_DELAY_ADJ_REG_4 0xCC +#define SSD2825_DELAY_ADJ_REG_5 0xCD +#define SSD2825_DELAY_ADJ_REG_6 0xCE +#define SSD2825_HS_TX_TIMER_REG_1 0xCF +#define SSD2825_HS_TX_TIMER_REG_2 0xD0 +#define SSD2825_LP_RX_TIMER_REG_1 0xD1 +#define SSD2825_LP_RX_TIMER_REG_2 0xD2 +#define SSD2825_TE_STATUS_REG 0xD3 +#define SSD2825_SPI_READ_REG 0xD4 +#define SSD2825_PLL_LOCK_REG 0xD5 +#define SSD2825_TEST_REG 0xD6 +#define SSD2825_TE_COUNT_REG 0xD7 +#define SSD2825_ANALOG_CTRL_REG_1 0xD8 +#define SSD2825_ANALOG_CTRL_REG_2 0xD9 +#define SSD2825_ANALOG_CTRL_REG_3 0xDA +#define SSD2825_ANALOG_CTRL_REG_4 0xDB +#define SSD2825_INTERRUPT_OUT_CTRL_REG 0xDC +#define SSD2825_RGB_INTERFACE_CTRL_REG_7 0xDD +#define SSD2825_LANE_CONFIGURATION_REG 0xDE +#define SSD2825_DELAY_ADJ_REG_7 0xDF +#define SSD2825_INPUT_PIN_CTRL_REG_1 0xE0 +#define SSD2825_INPUT_PIN_CTRL_REG_2 0xE1 +#define SSD2825_BIDIR_PIN_CTRL_REG_1 0xE2 +#define SSD2825_BIDIR_PIN_CTRL_REG_2 0xE3 +#define SSD2825_BIDIR_PIN_CTRL_REG_3 0xE4 +#define SSD2825_BIDIR_PIN_CTRL_REG_4 0xE5 +#define SSD2825_BIDIR_PIN_CTRL_REG_5 0xE6 +#define SSD2825_BIDIR_PIN_CTRL_REG_6 0xE7 +#define SSD2825_BIDIR_PIN_CTRL_REG_7 0xE8 +#define SSD2825_CABC_BRIGHTNESS_CTRL_REG_1 0xE9 +#define SSD2825_CABC_BRIGHTNESS_CTRL_REG_2 0xEA +#define SSD2825_CABC_BRIGHTNESS_STATUS_REG 0xEB +#define SSD2825_READ_REG 0xFF +#define SSD2825_SPI_READ_REG_RESET 0xFA + +#define SSD2825_CMD_MASK 0x00 +#define SSD2825_DAT_MASK 0x01 + +#define SSD2825_CMD_SEND BIT(0) +#define SSD2825_DAT_SEND BIT(1) +#define SSD2825_DSI_SEND BIT(2) + +#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F) +#define SSD2825_LP_MIN_CLK 5000 /* KHz */ +#define SSD2825_REF_MIN_CLK 2000 /* KHz */ + +struct ssd2825_bridge_priv { + struct mipi_dsi_host host; + struct mipi_dsi_device device; + + struct udevice *panel; + struct display_timing timing; + + struct gpio_desc power_gpio; + struct gpio_desc reset_gpio; + + struct clk *tx_clk; + + u32 pll_freq_kbps; /* PLL in kbps */ +}; + +static int ssd2825_spi_write(struct udevice *dev, int reg, + const void *buf, int flags) +{ + u8 command[2]; + + if (flags & SSD2825_CMD_SEND) { + command[0] = SSD2825_CMD_MASK; + command[1] = reg; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + } + + if (flags & SSD2825_DAT_SEND) { + u16 data = *(u16 *)buf; + u8 cmd1, cmd2; + + /* send low byte first and then high byte */ + cmd1 = (data & 0x00FF); + cmd2 = (data & 0xFF00) >> 8; + + command[0] = SSD2825_DAT_MASK; + command[1] = cmd1; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + + command[0] = SSD2825_DAT_MASK; + command[1] = cmd2; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + } + + if (flags & SSD2825_DSI_SEND) { + u16 data = *(u16 *)buf; + data &= 0x00FF; + + debug("%s: dsi command (0x%x)\n", + __func__, data); + + command[0] = SSD2825_DAT_MASK; + command[1] = data; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + } + + return 0; +} + +static int ssd2825_spi_read(struct udevice *dev, int reg, + void *data, int flags) +{ + u8 command[2]; + + command[0] = SSD2825_CMD_MASK; + command[1] = SSD2825_SPI_READ_REG; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + + command[0] = SSD2825_DAT_MASK; + command[1] = SSD2825_SPI_READ_REG_RESET; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + + command[0] = SSD2825_DAT_MASK; + command[1] = 0; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + + command[0] = SSD2825_CMD_MASK; + command[1] = reg; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + + command[0] = SSD2825_CMD_MASK; + command[1] = SSD2825_SPI_READ_REG_RESET; + dm_spi_xfer(dev, 9, &command, + NULL, SPI_XFER_ONCE); + + dm_spi_xfer(dev, 16, NULL, + (u8 *)data, SPI_XFER_ONCE); + + return 0; +} + +static void ssd2825_write_register(struct udevice *dev, u8 reg, + u16 command) +{ + ssd2825_spi_write(dev, reg, &command, + SSD2825_CMD_SEND | + SSD2825_DAT_SEND); +} + +static void ssd2825_write_dsi(struct udevice *dev, const u8 *command, + int len) +{ + int i; + + ssd2825_spi_write(dev, SSD2825_PACKET_SIZE_CTRL_REG_1, &len, + SSD2825_CMD_SEND | SSD2825_DAT_SEND); + + ssd2825_spi_write(dev, SSD2825_PACKET_DROP_REG, NULL, + SSD2825_CMD_SEND); + + for (i = 0; i < len; i++) + ssd2825_spi_write(dev, 0, &command[i], SSD2825_DSI_SEND); +} + +static ssize_t ssd2825_bridge_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct udevice *dev = (struct udevice *)host->dev; + u8 buf = *(u8 *)msg->tx_buf; + u16 config; + int ret; + + ret = ssd2825_spi_read(dev, SSD2825_CONFIGURATION_REG, + &config, 0); + if (ret) + return ret; + + switch (msg->type) { + case MIPI_DSI_DCS_SHORT_WRITE: + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: + case MIPI_DSI_DCS_LONG_WRITE: + config |= SSD2825_CONF_REG_DCS; + break; + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: + case MIPI_DSI_GENERIC_LONG_WRITE: + config &= ~SSD2825_CONF_REG_DCS; + break; + default: + return 0; + } + + ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG, config); + ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); + ssd2825_write_dsi(dev, msg->tx_buf, msg->tx_len); + + if (buf == MIPI_DCS_SET_DISPLAY_ON) { + ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG, + SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN | + SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD | + SSD2825_CONF_REG_EOT); + ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001); + ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); + } + + return 0; +} + +static const struct mipi_dsi_host_ops ssd2825_bridge_host_ops = { + .transfer = ssd2825_bridge_transfer, +}; + +/* + * PLL configuration register settings. + * + * See the "PLL Configuration Register Description" in the SSD2825 datasheet. + */ +static u16 construct_pll_config(struct ssd2825_bridge_priv *priv, + u32 desired_pll_freq_kbps, u32 reference_freq_khz) +{ + u32 div_factor = 1, mul_factor, fr = 0; + + while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK) + div_factor++; + if (div_factor > 31) + div_factor = 31; + + mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, + reference_freq_khz); + + priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor; + + if (priv->pll_freq_kbps >= 501000) + fr = 3; + else if (priv->pll_freq_kbps >= 251000) + fr = 2; + else if (priv->pll_freq_kbps >= 126000) + fr = 1; + + return (fr << 14) | (div_factor << 8) | mul_factor; +} + +static void ssd2825_setup_pll(struct udevice *dev) +{ + struct ssd2825_bridge_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct display_timing *dt = &priv->timing; + u16 pll_config, lp_div; + u32 pclk_mult, tx_freq_khz, pd_lines; + + tx_freq_khz = clk_get_rate(priv->tx_clk) / 1000; + pd_lines = mipi_dsi_pixel_format_to_bpp(device->format); + pclk_mult = pd_lines / device->lanes + 1; + + pll_config = construct_pll_config(priv, pclk_mult * + dt->pixelclock.typ / 1000, + tx_freq_khz); + + lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8); + + /* Disable PLL */ + ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0000); + ssd2825_write_register(dev, SSD2825_LINE_CTRL_REG, 0x0001); + + /* Set delays */ + ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, 0x2103); + + /* Set PLL coeficients */ + ssd2825_write_register(dev, SSD2825_PLL_CONFIGURATION_REG, pll_config); + + /* Clock Control Register */ + ssd2825_write_register(dev, SSD2825_CLOCK_CTRL_REG, + SSD2828_LP_CLOCK_DIVIDER(lp_div)); + + /* Enable PLL */ + ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001); + ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); +} + +static int ssd2825_bridge_enable_panel(struct udevice *dev) +{ + struct ssd2825_bridge_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct display_timing *dt = &priv->timing; + int ret; + + ret = clk_prepare_enable(priv->tx_clk); + if (ret) { + log_err("error enabling tx_clk (%d)\n", ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->power_gpio, 1); + if (ret) { + log_err("error changing power-gpios (%d)\n", ret); + return ret; + } + mdelay(10); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(10); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(10); + + /* Perform panel HW setup */ + ret = panel_enable_backlight(priv->panel); + if (ret) + return ret; + + /* Perform SW reset */ + ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100); + + /* Set panel timings */ + ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_1, + dt->vsync_len.typ << 8 | dt->hsync_len.typ); + ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_2, + (dt->vsync_len.typ + dt->vback_porch.typ) << 8 | + (dt->hsync_len.typ + dt->hback_porch.typ)); + ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_3, + dt->vfront_porch.typ << 8 | dt->hfront_porch.typ); + ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_4, + dt->hactive.typ); + ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_5, + dt->vactive.typ); + ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_6, + SSD2825_HSYNC_HIGH | SSD2825_VSYNC_HIGH | + SSD2825_PCKL_HIGH | SSD2825_NON_BURST | + (3 - device->format)); + ssd2825_write_register(dev, SSD2825_LANE_CONFIGURATION_REG, + device->lanes - 1); + ssd2825_write_register(dev, SSD2825_TEST_REG, 0x0004); + + /* Call PLL configuration */ + ssd2825_setup_pll(dev); + + mdelay(10); + + /* Initial DSI configuration register set */ + ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG, + SSD2825_CONF_REG_CKE | SSD2825_CONF_REG_DCS | + SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT); + ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); + + /* Set up SW panel configuration */ + ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT); + if (ret) + return ret; + + return 0; +} + +static int ssd2825_bridge_set_panel(struct udevice *dev, int percent) +{ + return 0; +} + +static int ssd2825_bridge_panel_timings(struct udevice *dev, + struct display_timing *timing) +{ + struct ssd2825_bridge_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->timing, sizeof(*timing)); + + return 0; +} + +static int ssd2825_bridge_probe(struct udevice *dev) +{ + struct ssd2825_bridge_priv *priv = dev_get_priv(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct mipi_dsi_panel_plat *mipi_plat; + int ret; + + ret = spi_claim_bus(slave); + if (ret) { + log_err("SPI bus allocation failed (%d)\n", ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "panel", &priv->panel); + if (ret) { + log_err("cannot get panel: ret=%d\n", ret); + return ret; + } + + panel_get_display_timing(priv->panel, &priv->timing); + + mipi_plat = dev_get_plat(priv->panel); + mipi_plat->device = device; + + priv->host.dev = (struct device *)dev; + priv->host.ops = &ssd2825_bridge_host_ops; + + device->host = &priv->host; + device->lanes = mipi_plat->lanes; + device->format = mipi_plat->format; + device->mode_flags = mipi_plat->mode_flags; + + /* get panel gpios */ + ret = gpio_request_by_name(dev, "power-gpios", 0, + &priv->power_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode power-gpios (%d)\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode reset-gpios (%d)\n", ret); + return ret; + } + + /* get clk */ + priv->tx_clk = devm_clk_get(dev, "tx_clk"); + if (IS_ERR(priv->tx_clk)) { + log_err("cannot get tx_clk: %ld\n", PTR_ERR(priv->tx_clk)); + return PTR_ERR(priv->tx_clk); + } + + return 0; +} + +static const struct panel_ops ssd2825_bridge_ops = { + .enable_backlight = ssd2825_bridge_enable_panel, + .set_backlight = ssd2825_bridge_set_panel, + .get_display_timing = ssd2825_bridge_panel_timings, +}; + +static const struct udevice_id ssd2825_bridge_ids[] = { + { .compatible = "solomon,ssd2825" }, + { } +}; + +U_BOOT_DRIVER(ssd2825) = { + .name = "ssd2825", + .id = UCLASS_PANEL, + .of_match = ssd2825_bridge_ids, + .ops = &ssd2825_bridge_ops, + .probe = ssd2825_bridge_probe, + .priv_auto = sizeof(struct ssd2825_bridge_priv), +}; diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c index d4f79c656a9..1f93b1b85fa 100644 --- a/drivers/video/console_core.c +++ b/drivers/video/console_core.c @@ -46,11 +46,11 @@ static int console_set_font(struct udevice *dev, struct video_fontdata *fontdata int check_bpix_support(int bpix) { - if (bpix == VIDEO_BPP8 && IS_ENABLED(CONFIG_VIDEO_BPP8)) + if (bpix == VIDEO_BPP8 && CONFIG_IS_ENABLED(VIDEO_BPP8)) return 0; - else if (bpix == VIDEO_BPP16 && IS_ENABLED(CONFIG_VIDEO_BPP16)) + else if (bpix == VIDEO_BPP16 && CONFIG_IS_ENABLED(VIDEO_BPP16)) return 0; - else if (bpix == VIDEO_BPP32 && IS_ENABLED(CONFIG_VIDEO_BPP32)) + else if (bpix == VIDEO_BPP32 && CONFIG_IS_ENABLED(VIDEO_BPP32)) return 0; else return -ENOSYS; diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c new file mode 100644 index 00000000000..79a272128b8 --- /dev/null +++ b/drivers/video/endeavoru-panel.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <misc.h> +#include <mipi_display.h> +#include <mipi_dsi.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <power/regulator.h> + +struct endeavoru_panel_priv { + struct udevice *vdd; + struct udevice *vddio; + + struct udevice *backlight; + + struct gpio_desc reset_gpio; +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 63200000, + .hactive.typ = 720, + .hfront_porch.typ = 55, + .hback_porch.typ = 29, + .hsync_len.typ = 16, + .vactive.typ = 1280, + .vfront_porch.typ = 2, + .vback_porch.typ = 1, + .vsync_len.typ = 1, +}; + +static void dcs_write_one(struct mipi_dsi_device *dsi, u8 cmd, u8 data) +{ + mipi_dsi_dcs_write(dsi, cmd, &data, 1); +} + +/* + * This panel is not able to auto-increment all cmd addresses so for some of + * them, we need to send them one by one... + */ +#define dcs_write_seq(dsi, cmd, seq...) \ +({ \ + static const u8 d[] = { seq }; \ + unsigned int i; \ + \ + for (i = 0; i < ARRAY_SIZE(d) ; i++) \ + dcs_write_one(dsi, cmd + i, d[i]); \ +}) + +static int endeavoru_panel_enable_backlight(struct udevice *dev) +{ + struct endeavoru_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(5); + + ret = regulator_set_enable_if_allowed(priv->vddio, 1); + if (ret) { + log_err("error enabling iovcc-supply (%d)\n", ret); + return ret; + } + mdelay(1); + + ret = regulator_set_enable_if_allowed(priv->vdd, 1); + if (ret) { + log_err("error enabling vcc-supply (%d)\n", ret); + return ret; + } + mdelay(20); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(2); + + /* Reset panel */ + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(1); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(25); + + return 0; +} + +static int endeavoru_panel_set_backlight(struct udevice *dev, int percent) +{ + struct endeavoru_panel_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + int ret; + + dcs_write_one(dsi, 0xc2, 0x08); + + /* color enhancement 2.2 */ + dcs_write_one(dsi, 0xff, 0x03); + dcs_write_one(dsi, 0xfe, 0x08); + dcs_write_one(dsi, 0x18, 0x00); + dcs_write_one(dsi, 0x19, 0x00); + dcs_write_one(dsi, 0x1a, 0x00); + dcs_write_one(dsi, 0x25, 0x26); + + dcs_write_seq(dsi, 0x00, 0x00, 0x05, 0x10, 0x17, + 0x22, 0x26, 0x29, 0x29, 0x26, 0x23, + 0x17, 0x12, 0x06, 0x02, 0x01, 0x00); + + dcs_write_one(dsi, 0xfb, 0x01); + dcs_write_one(dsi, 0xff, 0x00); + dcs_write_one(dsi, 0xfe, 0x01); + + mipi_dsi_dcs_exit_sleep_mode(dsi); + + mdelay(105); + + dcs_write_one(dsi, 0x35, 0x00); + + /* PWM frequency adjust */ + dcs_write_one(dsi, 0xff, 0x04); + dcs_write_one(dsi, 0x0a, 0x07); + dcs_write_one(dsi, 0x09, 0x20); + dcs_write_one(dsi, 0xff, 0x00); + + dcs_write_one(dsi, 0xff, 0xee); + dcs_write_one(dsi, 0x12, 0x50); + dcs_write_one(dsi, 0x13, 0x02); + dcs_write_one(dsi, 0x6a, 0x60); + dcs_write_one(dsi, 0xfb, 0x01); + dcs_write_one(dsi, 0xff, 0x00); + + mipi_dsi_dcs_set_display_on(dsi); + + mdelay(42); + + dcs_write_one(dsi, 0xba, 0x01); + + dcs_write_one(dsi, 0x53, 0x24); + dcs_write_one(dsi, 0x55, 0x80); + dcs_write_one(dsi, 0x5e, 0x06); + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + /* Set backlight */ + dcs_write_one(dsi, 0x51, 0x96); + + ret = backlight_set_brightness(priv->backlight, percent); + if (ret) + return ret; + + return 0; +} + +static int endeavoru_panel_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int endeavoru_panel_of_to_plat(struct udevice *dev) +{ + struct endeavoru_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_err("cannot get backlight: ret = %d\n", ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "vdd-supply", &priv->vdd); + if (ret) { + log_err("cannot get vdd-supply: ret = %d\n", ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "vddio-supply", &priv->vddio); + if (ret) { + log_err("cannot get vddio-supply: ret = %d\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode reser-gpios (%d)\n", ret); + return ret; + } + + return 0; +} + +static int endeavoru_panel_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 2; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO; + + return 0; +} + +static const struct panel_ops endeavoru_panel_ops = { + .enable_backlight = endeavoru_panel_enable_backlight, + .set_backlight = endeavoru_panel_set_backlight, + .get_display_timing = endeavoru_panel_timings, +}; + +static const struct udevice_id endeavoru_panel_ids[] = { + { .compatible = "htc,edge-panel" }, + { } +}; + +U_BOOT_DRIVER(endeavoru_panel) = { + .name = "endeavoru_panel", + .id = UCLASS_PANEL, + .of_match = endeavoru_panel_ids, + .ops = &endeavoru_panel_ops, + .of_to_plat = endeavoru_panel_of_to_plat, + .probe = endeavoru_panel_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct endeavoru_panel_priv), +}; diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c new file mode 100644 index 00000000000..00297a09b7f --- /dev/null +++ b/drivers/video/lm3533_backlight.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT + +#include <backlight.h> +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <asm/gpio.h> + +#define LM3533_BL_MIN_BRIGHTNESS 0x02 +#define LM3533_BL_MAX_BRIGHTNESS 0xFF + +#define LM3533_SINK_OUTPUT_CONFIG_1 0x10 +#define LM3533_CONTROL_BANK_A_PWM 0x14 +#define LM3533_CONTROL_BANK_AB_BRIGHTNESS 0x1A +#define LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT 0x1F +#define LM3533_CONTROL_BANK_ENABLE 0x27 +#define LM3533_OVP_FREQUENCY_PWM_POLARITY 0x2C +#define LM3533_BRIGHTNESS_REGISTER_A 0x40 + +struct lm3533_backlight_priv { + struct gpio_desc enable_gpio; + u32 def_bl_lvl; +}; + +static int lm3533_backlight_enable(struct udevice *dev) +{ + struct lm3533_backlight_priv *priv = dev_get_priv(dev); + int ret; + + dm_gpio_set_value(&priv->enable_gpio, 1); + mdelay(5); + + /* HVLED 1 & 2 are controlled by Bank A */ + ret = dm_i2c_reg_write(dev, LM3533_SINK_OUTPUT_CONFIG_1, 0x00); + if (ret) + return ret; + + /* PWM input is disabled for CABC */ + ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_PWM, 0x00); + if (ret) + return ret; + + /* Linear & Control Bank A is configured for register Current control */ + ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS, 0x02); + if (ret) + return ret; + + /* Full-Scale Current (20.2mA) */ + ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT, 0x13); + if (ret) + return ret; + + /* Control Bank A is enable */ + ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_ENABLE, 0x01); + if (ret) + return ret; + + ret = dm_i2c_reg_write(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY, 0x0A); + if (ret) + return ret; + + return 0; +} + +static int lm3533_backlight_set_brightness(struct udevice *dev, int percent) +{ + struct lm3533_backlight_priv *priv = dev_get_priv(dev); + int ret; + + if (percent == BACKLIGHT_DEFAULT) + percent = priv->def_bl_lvl; + + if (percent < LM3533_BL_MIN_BRIGHTNESS) + percent = LM3533_BL_MIN_BRIGHTNESS; + + if (percent > LM3533_BL_MAX_BRIGHTNESS) + percent = LM3533_BL_MAX_BRIGHTNESS; + + /* Set brightness level */ + ret = dm_i2c_reg_write(dev, LM3533_BRIGHTNESS_REGISTER_A, + percent); + if (ret) + return ret; + + return 0; +} + +static int lm3533_backlight_probe(struct udevice *dev) +{ + struct lm3533_backlight_priv *priv = dev_get_priv(dev); + int ret; + + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + ret = gpio_request_by_name(dev, "enable-gpios", 0, + &priv->enable_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("Could not decode enable-gpios (%d)\n", ret); + return ret; + } + + priv->def_bl_lvl = dev_read_u32_default(dev, "default-brightness-level", + LM3533_BL_MAX_BRIGHTNESS); + + return 0; +} + +static const struct backlight_ops lm3533_backlight_ops = { + .enable = lm3533_backlight_enable, + .set_brightness = lm3533_backlight_set_brightness, +}; + +static const struct udevice_id lm3533_backlight_ids[] = { + { .compatible = "ti,lm3533" }, + { } +}; + +U_BOOT_DRIVER(lm3533_backlight) = { + .name = "lm3533_backlight", + .id = UCLASS_PANEL_BACKLIGHT, + .of_match = lm3533_backlight_ids, + .probe = lm3533_backlight_probe, + .ops = &lm3533_backlight_ops, + .priv_auto = sizeof(struct lm3533_backlight_priv), +}; diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c new file mode 100644 index 00000000000..426fdc6224a --- /dev/null +++ b/drivers/video/renesas-r61307.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas R61307 panel driver + * + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <misc.h> +#include <mipi_display.h> +#include <mipi_dsi.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <power/regulator.h> + +/* + * The datasheet is not publicly available, all values are + * taken from the downstream. If you have access to datasheets, + * corrections are welcome. + */ + +#define R61307_MACP 0xB0 /* Manufacturer CMD Protect */ + +#define R61307_INVERSION 0xC1 +#define R61307_GAMMA_SET_A 0xC8 /* Gamma Setting A */ +#define R61307_GAMMA_SET_B 0xC9 /* Gamma Setting B */ +#define R61307_GAMMA_SET_C 0xCA /* Gamma Setting C */ +#define R61307_CONTRAST_SET 0xCC + +struct renesas_r61307_priv { + struct udevice *vcc; + struct udevice *iovcc; + + struct udevice *backlight; + + struct gpio_desc reset_gpio; + + bool dig_cont_adj; + bool inversion; + u32 gamma; +}; + +static const u8 macp_on[] = { + R61307_MACP, 0x03 +}; + +static const u8 macp_off[] = { + R61307_MACP, 0x04 +}; + +static const u8 address_mode[] = { + MIPI_DCS_SET_ADDRESS_MODE +}; + +static const u8 contrast_setting[] = { + R61307_CONTRAST_SET, + 0xdc, 0xb4, 0xff +}; + +static const u8 column_inversion[] = { + R61307_INVERSION, + 0x00, 0x50, 0x03, 0x22, + 0x16, 0x06, 0x60, 0x11 +}; + +static const u8 line_inversion[] = { + R61307_INVERSION, + 0x00, 0x10, 0x03, 0x22, + 0x16, 0x06, 0x60, 0x01 +}; + +static const u8 gamma_setting[][25] = { + {}, + { + R61307_GAMMA_SET_A, + 0x00, 0x06, 0x0a, 0x0f, + 0x14, 0x1f, 0x1f, 0x17, + 0x12, 0x0c, 0x09, 0x06, + 0x00, 0x06, 0x0a, 0x0f, + 0x14, 0x1f, 0x1f, 0x17, + 0x12, 0x0c, 0x09, 0x06 + }, + { + R61307_GAMMA_SET_A, + 0x00, 0x05, 0x0b, 0x0f, + 0x11, 0x1d, 0x20, 0x18, + 0x18, 0x09, 0x07, 0x06, + 0x00, 0x05, 0x0b, 0x0f, + 0x11, 0x1d, 0x20, 0x18, + 0x18, 0x09, 0x07, 0x06 + }, + { + R61307_GAMMA_SET_A, + 0x0b, 0x0d, 0x10, 0x14, + 0x13, 0x1d, 0x20, 0x18, + 0x12, 0x09, 0x07, 0x06, + 0x0a, 0x0c, 0x10, 0x14, + 0x13, 0x1d, 0x20, 0x18, + 0x12, 0x09, 0x07, 0x06 + }, +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 62000000, + .hactive.typ = 768, + .hfront_porch.typ = 116, + .hback_porch.typ = 81, + .hsync_len.typ = 5, + .vactive.typ = 1024, + .vfront_porch.typ = 24, + .vback_porch.typ = 8, + .vsync_len.typ = 2, +}; + +static int renesas_r61307_enable_backlight(struct udevice *dev) +{ + struct renesas_r61307_priv *priv = dev_get_priv(dev); + int ret; + + ret = regulator_set_enable_if_allowed(priv->vcc, 1); + if (ret) { + log_err("enabling vcc-supply failed (%d)\n", ret); + return ret; + } + mdelay(5); + + ret = regulator_set_enable_if_allowed(priv->iovcc, 1); + if (ret) { + log_err("enabling iovcc-supply failed (%d)\n", ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_err("changing reset-gpio failed (%d)\n", ret); + return ret; + } + mdelay(5); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_err("changing reset-gpio failed (%d)\n", ret); + return ret; + } + + mdelay(5); + + return 0; +} + +static int renesas_r61307_set_backlight(struct udevice *dev, int percent) +{ + struct renesas_r61307_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + int ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + log_err("failed to exit sleep mode: %d\n", ret); + return ret; + } + + mdelay(80); + + mipi_dsi_dcs_write_buffer(dsi, address_mode, + sizeof(address_mode)); + + mdelay(20); + + ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT << 4); + if (ret < 0) { + log_err("failed to set pixel format: %d\n", ret); + return ret; + } + + /* MACP Off */ + mipi_dsi_generic_write(dsi, macp_off, sizeof(macp_off)); + + if (priv->dig_cont_adj) + mipi_dsi_generic_write(dsi, contrast_setting, + sizeof(contrast_setting)); + + if (priv->gamma) + mipi_dsi_generic_write(dsi, gamma_setting[priv->gamma], + sizeof(gamma_setting[priv->gamma])); + + if (priv->inversion) + mipi_dsi_generic_write(dsi, column_inversion, + sizeof(column_inversion)); + else + mipi_dsi_generic_write(dsi, line_inversion, + sizeof(line_inversion)); + + /* MACP On */ + mipi_dsi_generic_write(dsi, macp_on, sizeof(macp_on)); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + log_err("failed to set display on: %d\n", ret); + return ret; + } + + mdelay(50); + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + ret = backlight_set_brightness(priv->backlight, percent); + if (ret) + return ret; + + return 0; +} + +static int renesas_r61307_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int renesas_r61307_of_to_plat(struct udevice *dev) +{ + struct renesas_r61307_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_err("Cannot get backlight: ret = %d\n", ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "vcc-supply", &priv->vcc); + if (ret) { + log_err("Cannot get vcc-supply: ret = %d\n", ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "iovcc-supply", &priv->iovcc); + if (ret) { + log_err("Cannot get iovcc-supply: ret = %d\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("Could not decode reser-gpios (%d)\n", ret); + return ret; + } + + priv->dig_cont_adj = dev_read_bool(dev, "renesas,contrast"); + priv->inversion = dev_read_bool(dev, "renesas,inversion"); + priv->gamma = dev_read_u32_default(dev, "renesas,gamma", 0); + + return 0; +} + +static int renesas_r61307_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO; + + return 0; +} + +static const struct panel_ops renesas_r61307_ops = { + .enable_backlight = renesas_r61307_enable_backlight, + .set_backlight = renesas_r61307_set_backlight, + .get_display_timing = renesas_r61307_timings, +}; + +static const struct udevice_id renesas_r61307_ids[] = { + { .compatible = "koe,tx13d100vm0eaa" }, + { .compatible = "hitachi,tx13d100vm0eaa" }, + { } +}; + +U_BOOT_DRIVER(renesas_r61307) = { + .name = "renesas_r61307", + .id = UCLASS_PANEL, + .of_match = renesas_r61307_ids, + .ops = &renesas_r61307_ops, + .of_to_plat = renesas_r61307_of_to_plat, + .probe = renesas_r61307_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct renesas_r61307_priv), +}; diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c new file mode 100644 index 00000000000..d2f71694681 --- /dev/null +++ b/drivers/video/renesas-r69328.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas R69328 panel driver + * + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <misc.h> +#include <mipi_display.h> +#include <mipi_dsi.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <power/regulator.h> + +/* + * The datasheet is not publicly available, all values are + * taken from the downstream. If you have access to datasheets, + * corrections are welcome. + */ + +#define R69328_MACP 0xB0 /* Manufacturer Command Access Protect */ + +#define R69328_GAMMA_SET_A 0xC8 /* Gamma Setting A */ +#define R69328_GAMMA_SET_B 0xC9 /* Gamma Setting B */ +#define R69328_GAMMA_SET_C 0xCA /* Gamma Setting C */ + +#define R69328_POWER_SET 0xD1 + +struct renesas_r69328_priv { + struct udevice *backlight; + + struct gpio_desc enable_gpio; + struct gpio_desc reset_gpio; +}; + +static const u8 address_mode[] = { + MIPI_DCS_SET_ADDRESS_MODE +}; + +#define dsi_generic_write_seq(dsi, cmd, seq...) do { \ + static const u8 b[] = { cmd, seq }; \ + int ret; \ + ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \ + if (ret < 0) \ + return ret; \ + } while (0) + +static struct display_timing default_timing = { + .pixelclock.typ = 68000000, + .hactive.typ = 720, + .hfront_porch.typ = 92, + .hback_porch.typ = 62, + .hsync_len.typ = 4, + .vactive.typ = 1280, + .vfront_porch.typ = 6, + .vback_porch.typ = 3, + .vsync_len.typ = 1, +}; + +static int renesas_r69328_enable_backlight(struct udevice *dev) +{ + struct renesas_r69328_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->enable_gpio, 1); + if (ret) { + log_err("error changing enable-gpios (%d)\n", ret); + return ret; + } + mdelay(5); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + mdelay(5); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_err("error changing reset-gpios (%d)\n", ret); + return ret; + } + + mdelay(5); + + return 0; +} + +static int renesas_r69328_set_backlight(struct udevice *dev, int percent) +{ + struct renesas_r69328_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + int ret; + + mipi_dsi_dcs_write_buffer(dsi, address_mode, + sizeof(address_mode)); + + ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT << 4); + if (ret < 0) { + log_err("failed to set pixel format: %d\n", ret); + return ret; + } + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + log_err("failed to exit sleep mode: %d\n", ret); + return ret; + } + + mdelay(100); + + /* MACP Off */ + dsi_generic_write_seq(dsi, R69328_MACP, 0x04); + + dsi_generic_write_seq(dsi, R69328_POWER_SET, 0x14, + 0x1d, 0x21, 0x67, 0x11, 0x9a); + + dsi_generic_write_seq(dsi, R69328_GAMMA_SET_A, 0x00, + 0x1a, 0x20, 0x28, 0x25, 0x24, + 0x26, 0x15, 0x13, 0x11, 0x18, + 0x1e, 0x1c, 0x00, 0x00, 0x1a, + 0x20, 0x28, 0x25, 0x24, 0x26, + 0x15, 0x13, 0x11, 0x18, 0x1e, + 0x1c, 0x00); + dsi_generic_write_seq(dsi, R69328_GAMMA_SET_B, 0x00, + 0x1a, 0x20, 0x28, 0x25, 0x24, + 0x26, 0x15, 0x13, 0x11, 0x18, + 0x1e, 0x1c, 0x00, 0x00, 0x1a, + 0x20, 0x28, 0x25, 0x24, 0x26, + 0x15, 0x13, 0x11, 0x18, 0x1e, + 0x1c, 0x00); + dsi_generic_write_seq(dsi, R69328_GAMMA_SET_C, 0x00, + 0x1a, 0x20, 0x28, 0x25, 0x24, + 0x26, 0x15, 0x13, 0x11, 0x18, + 0x1e, 0x1c, 0x00, 0x00, 0x1a, + 0x20, 0x28, 0x25, 0x24, 0x26, + 0x15, 0x13, 0x11, 0x18, 0x1e, + 0x1c, 0x00); + + /* MACP On */ + dsi_generic_write_seq(dsi, R69328_MACP, 0x03); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + log_err("failed to set display on: %d\n", ret); + return ret; + } + + mdelay(50); + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + ret = backlight_set_brightness(priv->backlight, percent); + if (ret) + return ret; + + return 0; +} + +static int renesas_r69328_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int renesas_r69328_of_to_plat(struct udevice *dev) +{ + struct renesas_r69328_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_err("cannot get backlight: ret = %d\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "enable-gpios", 0, + &priv->enable_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode enable-gpios (%d)\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_err("could not decode reser-gpios (%d)\n", ret); + return ret; + } + + return 0; +} + +static int renesas_r69328_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO; + + return 0; +} + +static const struct panel_ops renesas_r69328_ops = { + .enable_backlight = renesas_r69328_enable_backlight, + .set_backlight = renesas_r69328_set_backlight, + .get_display_timing = renesas_r69328_timings, +}; + +static const struct udevice_id renesas_r69328_ids[] = { + { .compatible = "jdi,dx12d100vm0eaa" }, + { } +}; + +U_BOOT_DRIVER(renesas_r69328) = { + .name = "renesas_r69328", + .id = UCLASS_PANEL, + .of_match = renesas_r69328_ids, + .ops = &renesas_r69328_ops, + .of_to_plat = renesas_r69328_of_to_plat, + .probe = renesas_r69328_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct renesas_r69328_priv), +}; diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig index 5b1dfbfbbed..f5c4843e119 100644 --- a/drivers/video/tegra20/Kconfig +++ b/drivers/video/tegra20/Kconfig @@ -15,3 +15,10 @@ config VIDEO_DSI_TEGRA30 help T30 has native support for DSI panels. This option enables support for such panels which can be used on endeavoru and tf600t. + +config TEGRA_BACKLIGHT_PWM + bool "Enable Tegra DC PWM backlight support" + depends on BACKLIGHT + select VIDEO_TEGRA20 + help + Tegra DC dependent backlight. diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile index e82ee96962f..f0b534c5794 100644 --- a/drivers/video/tegra20/Makefile +++ b/drivers/video/tegra20/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o mipi-phy.o +obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c new file mode 100644 index 00000000000..bb677daa8a1 --- /dev/null +++ b/drivers/video/tegra20/tegra-pwm-backlight.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT + +#include <backlight.h> +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/delay.h> +#include <linux/err.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/display.h> + +#define TEGRA_DISPLAY_A_BASE 0x54200000 +#define TEGRA_DISPLAY_B_BASE 0x54240000 + +#define TEGRA_PWM_BL_MIN_BRIGHTNESS 0x10 +#define TEGRA_PWM_BL_MAX_BRIGHTNESS 0xFF + +#define TEGRA_PWM_BL_PERIOD 0xFF +#define TEGRA_PWM_BL_CLK_DIV 0x14 +#define TEGRA_PWM_BL_CLK_SELECT 0x00 + +#define PM_PERIOD_SHIFT 18 +#define PM_CLK_DIVIDER_SHIFT 4 + +#define TEGRA_PWM_PM0 0 +#define TEGRA_PWM_PM1 1 + +struct tegra_pwm_backlight_priv { + struct dc_ctlr *dc; /* Display controller regmap */ + + u32 pwm_source; + u32 period; + u32 clk_div; + u32 clk_select; + u32 dft_brightness; +}; + +static int tegra_pwm_backlight_set_brightness(struct udevice *dev, int percent) +{ + struct tegra_pwm_backlight_priv *priv = dev_get_priv(dev); + struct dc_cmd_reg *cmd = &priv->dc->cmd; + struct dc_com_reg *com = &priv->dc->com; + unsigned int ctrl; + unsigned long out_sel; + unsigned long cmd_state; + + if (percent == BACKLIGHT_DEFAULT) + percent = priv->dft_brightness; + + if (percent < TEGRA_PWM_BL_MIN_BRIGHTNESS) + percent = TEGRA_PWM_BL_MIN_BRIGHTNESS; + + if (percent > TEGRA_PWM_BL_MAX_BRIGHTNESS) + percent = TEGRA_PWM_BL_MAX_BRIGHTNESS; + + ctrl = ((priv->period << PM_PERIOD_SHIFT) | + (priv->clk_div << PM_CLK_DIVIDER_SHIFT) | + priv->clk_select); + + /* The new value should be effected immediately */ + cmd_state = readl(&cmd->state_access); + writel((cmd_state | (1 << 2)), &cmd->state_access); + + switch (priv->pwm_source) { + case TEGRA_PWM_PM0: + /* Select the LM0 on PM0 */ + out_sel = readl(&com->pin_output_sel[5]); + out_sel &= ~(7 << 0); + out_sel |= (3 << 0); + writel(out_sel, &com->pin_output_sel[5]); + writel(ctrl, &com->pm0_ctrl); + writel(percent, &com->pm0_duty_cycle); + break; + case TEGRA_PWM_PM1: + /* Select the LM1 on PM1 */ + out_sel = readl(&com->pin_output_sel[5]); + out_sel &= ~(7 << 4); + out_sel |= (3 << 4); + writel(out_sel, &com->pin_output_sel[5]); + writel(ctrl, &com->pm1_ctrl); + writel(percent, &com->pm1_duty_cycle); + break; + default: + break; + } + + writel(cmd_state, &cmd->state_access); + return 0; +} + +static int tegra_pwm_backlight_enable(struct udevice *dev) +{ + struct tegra_pwm_backlight_priv *priv = dev_get_priv(dev); + + return tegra_pwm_backlight_set_brightness(dev, priv->dft_brightness); +} + +static int tegra_pwm_backlight_probe(struct udevice *dev) +{ + struct tegra_pwm_backlight_priv *priv = dev_get_priv(dev); + + if (dev_read_bool(dev, "nvidia,display-b-base")) + priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_B_BASE; + else + priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_A_BASE; + + if (!priv->dc) { + log_err("no display controller address\n"); + return -EINVAL; + } + + priv->pwm_source = + dev_read_u32_default(dev, "nvidia,pwm-source", + TEGRA_PWM_PM0); + priv->period = + dev_read_u32_default(dev, "nvidia,period", + TEGRA_PWM_BL_PERIOD); + priv->clk_div = + dev_read_u32_default(dev, "nvidia,clock-div", + TEGRA_PWM_BL_CLK_DIV); + priv->clk_select = + dev_read_u32_default(dev, "nvidia,clock-select", + TEGRA_PWM_BL_CLK_SELECT); + priv->dft_brightness = + dev_read_u32_default(dev, "nvidia,default-brightness", + TEGRA_PWM_BL_MAX_BRIGHTNESS); + + return 0; +} + +static const struct backlight_ops tegra_pwm_backlight_ops = { + .enable = tegra_pwm_backlight_enable, + .set_brightness = tegra_pwm_backlight_set_brightness, +}; + +static const struct udevice_id tegra_pwm_backlight_ids[] = { + { .compatible = "nvidia,tegra-pwm-backlight" }, + { } +}; + +U_BOOT_DRIVER(tegra_pwm_backlight) = { + .name = "tegra_pwm_backlight", + .id = UCLASS_PANEL_BACKLIGHT, + .of_match = tegra_pwm_backlight_ids, + .probe = tegra_pwm_backlight_probe, + .ops = &tegra_pwm_backlight_ops, + .priv_auto = sizeof(struct tegra_pwm_backlight_priv), +}; diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig index 2a5e56ea4ee..95086f3a5d6 100644 --- a/drivers/video/tidss/Kconfig +++ b/drivers/video/tidss/Kconfig @@ -16,3 +16,9 @@ menuconfig VIDEO_TIDSS DPI . This option enables these supports which can be used on devices which have OLDI or HDMI display connected. +config SPL_VIDEO_TIDSS + bool "Enable TIDSS video support in SPL Stage" + depends on SPL_VIDEO + help + This options enables tidss driver in SPL stage. If + you need to use tidss at SPL stage use this config. diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile index f4f8c6c470a..a29cee2a414 100644 --- a/drivers/video/tidss/Makefile +++ b/drivers/video/tidss/Makefile @@ -9,4 +9,4 @@ # Author: Tomi Valkeinen <tomi.valkeinen@ti.com> -obj-${CONFIG_VIDEO_TIDSS} = tidss_drv.o +obj-${CONFIG_$(SPL_)VIDEO_TIDSS} = tidss_drv.o diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 1225de23332..a21fde0e1d4 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -86,7 +86,7 @@ static void vidconsole_newline(struct udevice *dev) struct vidconsole_priv *priv = dev_get_uclass_priv(dev); struct udevice *vid_dev = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); - const int rows = CONFIG_CONSOLE_SCROLL_LINES; + const int rows = CONFIG_VAL(CONSOLE_SCROLL_LINES); int i, ret; priv->xcur_frac = priv->xstart_frac; diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index da89f431441..8396bdfb11e 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -132,7 +132,7 @@ int video_reserve(ulong *addrp) /* Allocate space for PCI video devices in case there were not bound */ if (*addrp == gd->video_top) - *addrp -= CONFIG_VIDEO_PCI_DEFAULT_FB_SIZE; + *addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE); gd->video_bottom = *addrp; gd->fb_base = *addrp; @@ -149,7 +149,7 @@ int video_fill(struct udevice *dev, u32 colour) switch (priv->bpix) { case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + if (CONFIG_IS_ENABLED(VIDEO_BPP16)) { u16 *ppix = priv->fb; u16 *end = priv->fb + priv->fb_size; @@ -158,7 +158,7 @@ int video_fill(struct udevice *dev, u32 colour) break; } case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { u32 *ppix = priv->fb; u32 *end = priv->fb + priv->fb_size; @@ -212,14 +212,14 @@ u32 video_index_to_colour(struct video_priv *priv, unsigned int idx) { switch (priv->bpix) { case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + if (CONFIG_IS_ENABLED(VIDEO_BPP16)) { return ((colours[idx].r >> 3) << 11) | ((colours[idx].g >> 2) << 5) | ((colours[idx].b >> 3) << 0); } break; case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { if (priv->format == VIDEO_X2R10G10B10) return (colours[idx].r << 22) | (colours[idx].g << 12) | @@ -513,8 +513,8 @@ static int video_post_probe(struct udevice *dev) return ret; } - if (IS_ENABLED(CONFIG_VIDEO_LOGO) && - !IS_ENABLED(CONFIG_SPLASH_SCREEN) && !plat->hide_logo) { + if (CONFIG_IS_ENABLED(VIDEO_LOGO) && + !CONFIG_IS_ENABLED(SPLASH_SCREEN) && !plat->hide_logo) { ret = show_splash(dev); if (ret) { log_debug("Cannot show splash screen\n"); diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 6188a13e44e..47e52c4f69c 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -320,7 +320,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, switch (bmp_bpix) { case 1: case 8: - if (IS_ENABLED(CONFIG_VIDEO_BMP_RLE8)) { + if (CONFIG_IS_ENABLED(VIDEO_BMP_RLE8)) { u32 compression = get_unaligned_le32( &bmp->header.compression); debug("compressed %d %d\n", compression, BMP_BI_RLE8); @@ -348,7 +348,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, } break; case 16: - if (IS_ENABLED(CONFIG_BMP_16BPP)) { + if (CONFIG_IS_ENABLED(BMP_16BPP)) { for (i = 0; i < height; ++i) { schedule(); for (j = 0; j < width; j++) { @@ -361,7 +361,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, } break; case 24: - if (IS_ENABLED(CONFIG_BMP_24BPP)) { + if (CONFIG_IS_ENABLED(BMP_24BPP)) { for (i = 0; i < height; ++i) { for (j = 0; j < width; j++) { if (bpix == 16) { @@ -395,7 +395,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, } break; case 32: - if (IS_ENABLED(CONFIG_BMP_32BPP)) { + if (CONFIG_IS_ENABLED(BMP_32BPP)) { for (i = 0; i < height; ++i) { for (j = 0; j < width; j++) { if (eformat == VIDEO_X2R10G10B10) { diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 987fb66c17a..65bf8df1e56 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -68,7 +68,7 @@ struct global_data { * @mem_clk: memory clock rate in Hz */ unsigned long mem_clk; -#if defined(CONFIG_VIDEO) +#if CONFIG_IS_ENABLED(VIDEO) /** * @fb_base: base address of frame buffer memory */ @@ -359,7 +359,7 @@ struct global_data { */ struct membuff console_in; #endif -#ifdef CONFIG_VIDEO +#if CONFIG_IS_ENABLED(VIDEO) /** * @video_top: top of video frame buffer area */ diff --git a/include/configs/bcmns.h b/include/configs/bcmns.h new file mode 100644 index 00000000000..6f5f2b7ccf2 --- /dev/null +++ b/include/configs/bcmns.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __BCM_NS_H +#define __BCM_NS_H + +#include <linux/sizes.h> + +/* Physical Memory Map */ +#define V2M_BASE 0x00000000 +#define PHYS_SDRAM_1 V2M_BASE + +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Called "periph_clk" in Linux, used by the global timer */ +#define CFG_SYS_HZ_CLOCK 500000000 + +/* Called "iprocslow" in Linux */ +#define CFG_SYS_NS16550_CLK 125000000 + +/* console configuration */ +#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0" +#define MAX_CPUS "max_cpus=maxcpus=2\0" +#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0" + +#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \ + " ${max_cpus} ${log_level} ${reserved_mem}" +#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0" + +#define KERNEL_LOADADDR_CFG \ + "loadaddr=0x01000000\0" \ + "dtb_loadaddr=0x02000000\0" + +/* + * Hardcoded for the only boards we support, if you add more + * boards, add a more clever bootcmd! + */ +#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000" + +#define ARCH_ENV_SETTINGS \ + CONSOLE_ARGS \ + MAX_CPUS \ + EXTRA_ARGS \ + KERNEL_LOADADDR_CFG \ + NS_BOOTCMD + +#define CFG_EXTRA_ENV_SETTINGS \ + ARCH_ENV_SETTINGS + +#endif /* __BCM_NS_H */ diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h new file mode 100644 index 00000000000..3db9a474ec7 --- /dev/null +++ b/include/configs/hc2910-2aghd05.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __HC2910_2AGHD05_CONFIG_H__ +#define __HC2910_2AGHD05_CONFIG_H__ + +#endif diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h new file mode 100644 index 00000000000..3148e8622e1 --- /dev/null +++ b/include/configs/imx8mq_reform2.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_REFORM2_H +#define __IMX8M_REFORM2_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CFG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#endif + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CFG_FEC_MXC_PHYADDR 4 +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "ramdisk_addr_r=0x44000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=imx8mq-mnt-reform2.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + "stdin=serial,usbkbd\0" + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + + +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GiB DDR */ + +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) + +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 + +#endif diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h new file mode 100644 index 00000000000..f9cda5eec7d --- /dev/null +++ b/include/configs/imx8qm_dmsse20.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2019 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ + +#ifndef __IMX8QM_DMSSE20_H +#define __IMX8QM_DMSSE20_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +/* Flat Device Tree Definitions */ + +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x5B040000 +/* FEC1 */ +#define IMX_FEC1_BASE 0x5B040000 +/* FEC2 */ +#define IMX_FEC2_BASE 0x5B050000 + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +/* Incorporate settings into the U-Boot environment */ +#define CFG_EXTRA_ENV_SETTINGS + +#define CFG_SYS_FSL_USDHC_NUM 2 + +#define CFG_SYS_SDRAM_BASE 0x080000000 +#define PHYS_SDRAM_1 0x080000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#endif /* __IMX8QM_DMSSE20_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h deleted file mode 100644 index 39d0b403139..00000000000 --- a/include/configs/omap5_uevm.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated. - * Sricharan R <r.sricharan@ti.com> - * - * Configuration settings for the TI EVM5430 board. - * See ti_omap5_common.h for omap5 common settings. - */ - -#ifndef __CONFIG_OMAP5_EVM_H -#define __CONFIG_OMAP5_EVM_H - -#include <environment/ti/dfu.h> - -#ifndef CONFIG_SPL_BUILD -/* Define the default GPT table for eMMC */ -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" -#endif - -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM - -#include <configs/ti_omap5_common.h> - -#define CFG_SYS_NS16550_COM3 UART3_BASE - -/* MMC ENV related defines */ - -/* Required support for the TCA642X GPIO we have on the uEVM */ -#define CFG_SYS_I2C_TCA642X_BUS_NUM 4 -#define CFG_SYS_I2C_TCA642X_ADDR 0x22 - -/* Enabled commands */ - -/* USB Networking options */ - -#define CONSOLEDEV "ttyS2" - -#endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index 2211751b540..673268dca98 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -16,7 +16,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ "bootm_low=0x80000000\0" \ - "stdin=serial\0" \ + "stdin=serial,button-kbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "preboot=source $prevbl_initrd_start_addr:prebootscript\0" \ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 11031744bef..0aa25f9e2ea 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -17,23 +17,25 @@ /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CFG_EXTRA_ENV_SETTINGS \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdtfile=imx7d-smegw01.dtb\0" \ - "fdt_addr=0x83000000\0" \ - "bootm_size=0x10000000\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "fi;\0" \ +/* default to no extra bootparams, we need an empty define for stringification*/ +#ifndef EXTRA_BOOTPARAMS +#define EXTRA_BOOTPARAMS +#endif + +#ifdef CONFIG_SYS_BOOT_LOCKED +#define EXTRA_ENV_FLAGS +#else +#define EXTRA_ENV_FLAGS "mmcdev:dw," +#endif + +#define CFG_ENV_FLAGS_LIST_STATIC \ + "mmcpart:dw," \ + "mmcpart_committed:dw," \ + "ustate:dw," \ + "bootcount:dw," \ + "bootlimit:dw," \ + "upgrade_available:dw," \ + EXTRA_ENV_FLAGS /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index d54c208ef66..149a74d98e8 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -55,7 +55,8 @@ "do;" \ "setenv overlaystring ${overlaystring}'#'${overlay};" \ "done;\0" \ - "run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}\0" \ + "get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}\0" \ + "run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}\0" \ /* * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 5386c3faf9f..307ad6931ca 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -56,6 +56,7 @@ enum uclass_id { UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */ UCLASS_ETH, /* Ethernet device */ UCLASS_ETH_PHY, /* Ethernet PHY device */ + UCLASS_EXTCON, /* External Connector Class */ UCLASS_FIRMWARE, /* Firmware */ UCLASS_FPGA, /* FPGA device */ UCLASS_FUZZING_ENGINE, /* Fuzzing engine */ diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 5c5fb9acac0..456eef7f2f3 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -274,7 +274,7 @@ int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node, * The device is probed to activate it ready for use. * * @id: ID to look up - * @node: Device tree path to search for (if no such path then -ENODEV is returned) + * @path: Device tree path to search for (if no such path then -ENODEV is returned) * @devp: Returns pointer to device (there is only one for each node) * Return: 0 if OK, -ve on error */ diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h new file mode 100644 index 00000000000..ad5827cde78 --- /dev/null +++ b/include/dt-bindings/clock/bcm-nsp.h @@ -0,0 +1,51 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_BCM_NSP_H +#define _CLOCK_BCM_NSP_H + +/* GENPLL clock channel ID */ +#define BCM_NSP_GENPLL 0 +#define BCM_NSP_GENPLL_PHY_CLK 1 +#define BCM_NSP_GENPLL_ENET_SW_CLK 2 +#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 +#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 +#define BCM_NSP_GENPLL_SATA1_CLK 5 +#define BCM_NSP_GENPLL_SATA2_CLK 6 + +/* LCPLL0 clock channel ID */ +#define BCM_NSP_LCPLL0 0 +#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 +#define BCM_NSP_LCPLL0_SDIO_CLK 2 +#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 + +#endif /* _CLOCK_BCM_NSP_H */ diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index 136de24733b..8a05790d1a9 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -70,6 +70,18 @@ #define HISTB_USB3_UTMI_CLK1 48 #define HISTB_USB3_PIPE_CLK1 49 #define HISTB_USB3_SUSPEND_CLK1 50 +#define HISTB_SDIO1_BIU_CLK 51 +#define HISTB_SDIO1_CIU_CLK 52 +#define HISTB_SDIO1_DRV_CLK 53 +#define HISTB_SDIO1_SAMPLE_CLK 54 + +/* Hi3798MV200 specific clocks */ + +// reuse clocks of histb +#define HI3798MV200_GMAC_CLK HISTB_ETH0_MAC_CLK +#define HI3798MV200_GMACIF_CLK HISTB_ETH0_MACIF_CLK +#define HI3798MV200_FEMAC_CLK HISTB_ETH1_MAC_CLK +#define HI3798MV200_FEMACIF_CLK HISTB_ETH1_MACIF_CLK /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 diff --git a/include/env_flags.h b/include/env_flags.h index 7de58cc57c3..d785f87cdcb 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -71,7 +71,7 @@ enum env_flags_varaccess { #define NET6_FLAGS \ "ip6addr:s," \ "serverip6:s," \ - "gatewayip6:s" + "gatewayip6:s," #else #define NET6_FLAGS #endif diff --git a/include/environment/ti/ti_armv7_common.env b/include/environment/ti/ti_armv7_common.env index 4d334648c05..0c0929d8628 100644 --- a/include/environment/ti/ti_armv7_common.env +++ b/include/environment/ti/ti_armv7_common.env @@ -20,5 +20,6 @@ get_overlaystring= do; setenv overlaystring ${overlaystring}'#'${overlay}; done; -run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring} +get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} +run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} diff --git a/include/extcon.h b/include/extcon.h new file mode 100644 index 00000000000..d060f5a3c1f --- /dev/null +++ b/include/extcon.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __EXTCON_H +#define __EXTCON_H + +struct udevice; + +/** + * struct extcon_uc_plat - Platform data the uclass stores about each device + * + * To be filled + */ +struct extcon_uc_plat { +}; + +#endif diff --git a/include/fastboot.h b/include/fastboot.h index 07f4c8fa711..296451f89d4 100644 --- a/include/fastboot.h +++ b/include/fastboot.h @@ -124,6 +124,15 @@ void fastboot_init(void *buf_addr, u32 buf_size); void fastboot_boot(void); /** + * fastboot_handle_boot() - Shared implementation of system reaction to + * fastboot commands + * + * Making desceisions about device boot state (stay in fastboot, reboot + * to bootloader, reboot to OS, etc). + */ +void fastboot_handle_boot(int command, bool success); + +/** * fastboot_handle_command() - Handle fastboot command * * @cmd_string: Pointer to command string diff --git a/include/ndisc.h b/include/ndisc.h index f6f8eb6507c..d0fe3acca4a 100644 --- a/include/ndisc.h +++ b/include/ndisc.h @@ -19,6 +19,20 @@ struct nd_msg { __u8 opt[0]; }; +/* struct rs_msg - ICMPv6 Router Solicitation message format */ +struct rs_msg { + struct icmp6hdr icmph; + __u8 opt[0]; +}; + +/* struct ra_msg - ICMPv6 Router Advertisement message format */ +struct ra_msg { + struct icmp6hdr icmph; + __u32 reachable_time; + __u32 retransmission_timer; + __u8 opt[0]; +}; + /* struct echo_msg - ICMPv6 echo request/reply message format */ struct echo_msg { struct icmp6hdr icmph; @@ -57,6 +71,11 @@ extern int net_nd_try; */ void ndisc_init(void); +/* + * ip6_send_rs() - Send IPv6 Router Solicitation Message + */ +void ip6_send_rs(void); + /** * ndisc_receive() - Handle ND packet * @@ -78,6 +97,8 @@ void ndisc_request(void); * Return: 0 if no timeout, -1 otherwise */ int ndisc_timeout_check(void); +bool validate_ra(struct ip6_hdr *ip6); +int process_ra(struct ip6_hdr *ip6, int len); #else static inline void ndisc_init(void) { @@ -97,6 +118,20 @@ static inline int ndisc_timeout_check(void) { return 0; } + +static inline void ip6_send_rs(void) +{ +} + +static inline bool validate_ra(struct ip6_hdr *ip6) +{ + return true; +} + +static inline int process_ra(struct ip6_hdr *ip6, int len) +{ + return 0; +} #endif #endif /* __NDISC_H__ */ diff --git a/include/net.h b/include/net.h index 399af5e0645..785cb1059ef 100644 --- a/include/net.h +++ b/include/net.h @@ -484,6 +484,8 @@ extern char net_hostname[32]; /* Our hostname */ #ifdef CONFIG_NET extern char net_root_path[CONFIG_BOOTP_MAX_ROOT_PATH_LEN]; /* Our root path */ #endif +/* Indicates whether the pxe path prefix / config file was specified in dhcp option */ +extern char *pxelinux_configfile; /** END OF BOOTP EXTENTIONS **/ extern u8 net_ethaddr[ARP_HLEN]; /* Our ethernet address */ extern u8 net_server_ethaddr[ARP_HLEN]; /* Boot server enet address */ @@ -504,8 +506,9 @@ extern ushort net_native_vlan; /* Our Native VLAN */ extern int net_restart_wrap; /* Tried all network devices */ enum proto_t { - BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS, - SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI, WGET + BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP, + NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT_UDP, FASTBOOT_TCP, + WOL, UDP, NCSI, WGET, RS }; extern char net_boot_file_name[1024];/* Boot File name */ diff --git a/include/net/fastboot.h b/include/net/fastboot.h deleted file mode 100644 index 68602095d2b..00000000000 --- a/include/net/fastboot.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (C) 2016 The Android Open Source Project - */ - -#ifndef __NET_FASTBOOT_H__ -#define __NET_FASTBOOT_H__ - -/**********************************************************************/ -/* - * Global functions and variables. - */ - -/** - * Wait for incoming fastboot comands. - */ -void fastboot_start_server(void); - -/**********************************************************************/ - -#endif /* __NET_FASTBOOT_H__ */ diff --git a/include/net/fastboot_tcp.h b/include/net/fastboot_tcp.h new file mode 100644 index 00000000000..6cf29d52e93 --- /dev/null +++ b/include/net/fastboot_tcp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2023 The Android Open Source Project + */ + +#ifndef __NET_FASTBOOT_TCP_H__ +#define __NET_FASTBOOT_TCP_H__ + +/** + * Wait for incoming tcp fastboot comands. + */ +void fastboot_tcp_start_server(void); + +#endif /* __NET_FASTBOOT_TCP_H__ */ diff --git a/include/net/fastboot_udp.h b/include/net/fastboot_udp.h new file mode 100644 index 00000000000..d4382c0a0e0 --- /dev/null +++ b/include/net/fastboot_udp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2016 The Android Open Source Project + */ + +#ifndef __NET_FASTBOOT_H__ +#define __NET_FASTBOOT_H__ + +/** + * Wait for incoming UDP fastboot comands. + */ +void fastboot_udp_start_server(void); + +#endif /* __NET_FASTBOOT_H__ */ diff --git a/include/net/ldpaa_eth.h b/include/net/ldpaa_eth.h new file mode 100644 index 00000000000..7474bfaeec3 --- /dev/null +++ b/include/net/ldpaa_eth.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 NXP + */ + +#define LDPAA_ETH_DRIVER_NAME "ldpaa_eth" + +/** + * ldpaa_eth_get_dpmac_id() - Get the dpmac_id of a DPAA2 ethernet device + * + * @dev: DPAA2 ethernet udevice pointer + * Return: requested dpmac_id + */ + +uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev); diff --git a/include/net/tcp.h b/include/net/tcp.h index 322551694f5..c29d4ce24a7 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -259,6 +259,7 @@ union tcp_build_pkt { * enum tcp_state - TCP State machine states for connection * @TCP_CLOSED: Need to send SYN to connect * @TCP_SYN_SENT: Trying to connect, waiting for SYN ACK + * @TCP_SYN_RECEIVED: Initial SYN received, waiting for ACK * @TCP_ESTABLISHED: both server & client have a connection * @TCP_CLOSE_WAIT: Rec FIN, passed to app for FIN, ACK rsp * @TCP_CLOSING: Rec FIN, sent FIN, ACK waiting for ACK @@ -268,6 +269,7 @@ union tcp_build_pkt { enum tcp_state { TCP_CLOSED, TCP_SYN_SENT, + TCP_SYN_RECEIVED, TCP_ESTABLISHED, TCP_CLOSE_WAIT, TCP_CLOSING, @@ -283,14 +285,18 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, /** * rxhand_tcp() - An incoming packet handler. * @pkt: pointer to the application packet - * @dport: destination UDP port + * @dport: destination TCP port * @sip: source IP address - * @sport: source UDP port + * @sport: source TCP port + * @tcp_seq_num: TCP sequential number + * @tcp_ack_num: TCP acknowledgment number + * @action: TCP action (SYN, ACK, FIN, etc) * @len: packet length */ -typedef void rxhand_tcp(uchar *pkt, unsigned int dport, - struct in_addr sip, unsigned int sport, - unsigned int len); +typedef void rxhand_tcp(uchar *pkt, u16 dport, + struct in_addr sip, u16 sport, + u32 tcp_seq_num, u32 tcp_ack_num, + u8 action, unsigned int len); void tcp_set_tcp_handler(rxhand_tcp *f); void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int len); diff --git a/include/net6.h b/include/net6.h index 2d7c5a09604..beafc053386 100644 --- a/include/net6.h +++ b/include/net6.h @@ -81,8 +81,17 @@ struct udp_hdr { 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00 } } } +/* + * All-routers multicast address is the link-local scope address to reach all + * routers. + */ +#define ALL_ROUTERS_MULT_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x02 } } } #define IPV6_LINK_LOCAL_PREFIX 0xfe80 +#define IPV6_LINK_LOCAL_MASK 0xffb0 /* The first 10-bit of address mask. */ /* hop limit for neighbour discovery packets */ #define IPV6_NDISC_HOPLIMIT 255 @@ -166,6 +175,37 @@ struct icmp6hdr { #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime } __packed; +/* + * struct icmp6_ra_prefix_info - Prefix Information option of the ICMPv6 message + * The Prefix Information option provides hosts with on-link prefixes and + * prefixes for Address Autoconfiguration. Refer to RFC 4861 for more info. + */ +struct icmp6_ra_prefix_info { + u8 type; /* Type is 3 for Prefix Information. */ + u8 len; /* Len is 4 for Prefix Information. */ + /* The number of leading bits in the Prefix that are valid. */ + u8 prefix_len; + u8 reserved1:6, /* MUST be ignored by the receiver. */ + aac:1, /* autonomous address-configuration flag */ + /* Indicates that this prefix can be used for on-link determination. */ + on_link:1; + /* + * The length of time in seconds that the prefix is valid for the + * purpose of on-link determination. + */ + __be32 valid_lifetime; + /* The length of time addresses remain preferred. */ + __be32 preferred_lifetime; + __be32 reserved2; /* MUST be ignored by the receiver. */ + /* + * Prefix is an IP address or a prefix of an IP address. The Prefix + * Length field contains the number of valid leading bits in the prefix. + * The bits in the prefix after the prefix length are reserved and MUST + * be initialized to zero by the sender and ignored by the receiver. + */ + struct in6_addr prefix; +}; + extern struct in6_addr const net_null_addr_ip6; /* NULL IPv6 address */ extern struct in6_addr net_gateway6; /* Our gateways IPv6 address */ extern struct in6_addr net_ip6; /* Our IPv6 addr (0 = unknown) */ diff --git a/include/phy.h b/include/phy.h index a837fed7235..247223d92be 100644 --- a/include/phy.h +++ b/include/phy.h @@ -361,20 +361,15 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); */ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) { - return phydev->interface >= PHY_INTERFACE_MODE_RGMII && - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; -} - -/** - * phy_interface_is_sgmii - Convenience function for testing if a PHY interface - * is SGMII (all variants) - * @phydev: the phy_device struct - * @return: true if MII bus is SGMII or false if it is not - */ -static inline bool phy_interface_is_sgmii(struct phy_device *phydev) -{ - return phydev->interface >= PHY_INTERFACE_MODE_SGMII && - phydev->interface <= PHY_INTERFACE_MODE_QSGMII; + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + return 1; + default: + return 0; + } } bool phy_interface_is_ncsi(void); diff --git a/include/pxe_utils.h b/include/pxe_utils.h index 1e5e8424f53..9f195930487 100644 --- a/include/pxe_utils.h +++ b/include/pxe_utils.h @@ -93,6 +93,7 @@ typedef int (*pxe_getfile_func)(struct pxe_context *ctx, const char *file_path, * @bootdir: Directory that files are loaded from ("" if no directory). This is * allocated * @pxe_file_size: Size of the PXE file + * @use_ipv6: TRUE : use IPv6 addressing, FALSE : use IPv4 addressing */ struct pxe_context { struct cmd_tbl *cmdtp; @@ -112,6 +113,7 @@ struct pxe_context { bool allow_abs_path; char *bootdir; ulong pxe_file_size; + bool use_ipv6; }; /** @@ -209,12 +211,14 @@ int format_mac_pxe(char *outbuf, size_t outbuf_len); * @allow_abs_path: true to allow absolute paths * @bootfile: Bootfile whose directory loaded files are relative to, NULL if * none + * @use_ipv6: TRUE : use IPv6 addressing + * FALSE : use IPv4 addressing * Return: 0 if OK, -ENOMEM if out of memory, -E2BIG if bootfile is larger than * MAX_TFTP_PATH_LEN bytes */ int pxe_setup_ctx(struct pxe_context *ctx, struct cmd_tbl *cmdtp, pxe_getfile_func getfile, void *userdata, - bool allow_abs_path, const char *bootfile); + bool allow_abs_path, const char *bootfile, bool use_ipv6); /** * pxe_destroy_ctx() - Destroy a PXE context @@ -251,7 +255,9 @@ int pxe_get_file_size(ulong *sizep); * "rpi/info", which indicates that all files should be fetched from the * "rpi/" subdirectory * @sizep: Size of the PXE file (not bootfile) + * @use_ipv6: TRUE : use IPv6 addressing + * FALSE : use IPv4 addressing */ -int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep); +int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep, bool use_ipv6); #endif /* __PXE_UTILS_H */ diff --git a/include/splash.h b/include/splash.h index 33e45e69416..c3922375987 100644 --- a/include/splash.h +++ b/include/splash.h @@ -49,7 +49,7 @@ struct splash_location { char *ubivol; /* UBI volume-name for ubifsmount */ }; -#ifdef CONFIG_SPLASH_SOURCE +#if CONFIG_IS_ENABLED(SPLASH_SOURCE) int splash_source_load(struct splash_location *locations, uint size); #else static inline int splash_source_load(struct splash_location *locations, @@ -60,21 +60,8 @@ static inline int splash_source_load(struct splash_location *locations, #endif int splash_screen_prepare(void); - -#ifdef CONFIG_SPLASH_SCREEN_ALIGN void splash_get_pos(int *x, int *y); -#else -static inline void splash_get_pos(int *x, int *y) { } -#endif - -#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP) int splash_display(void); -#else -static inline int splash_display(void) -{ - return -ENOSYS; -} -#endif #define BMP_ALIGN_CENTER 0x7FFF diff --git a/include/video.h b/include/video.h index 4d99e5dc27f..29c4f51efb0 100644 --- a/include/video.h +++ b/include/video.h @@ -357,4 +357,12 @@ void *video_get_u_boot_logo(void); */ int bmp_display(ulong addr, int x, int y); +/* + * bmp_info() - Show information about bmp file + * + * @addr: address of bmp file + * Returns: 0 if OK, else 1 if bmp image not found + */ +int bmp_info(ulong addr); + #endif diff --git a/net/Makefile b/net/Makefile index bea000b2067..3e2d061338d 100644 --- a/net/Makefile +++ b/net/Makefile @@ -22,11 +22,13 @@ obj-$(CONFIG_IPV6) += net6.o obj-$(CONFIG_CMD_NFS) += nfs.o obj-$(CONFIG_CMD_PING) += ping.o obj-$(CONFIG_CMD_PING6) += ping6.o +obj-$(CONFIG_CMD_DHCP6) += dhcpv6.o obj-$(CONFIG_CMD_PCAP) += pcap.o obj-$(CONFIG_CMD_RARP) += rarp.o obj-$(CONFIG_CMD_SNTP) += sntp.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o -obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot.o +obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot_udp.o +obj-$(CONFIG_TCP_FUNCTION_FASTBOOT) += fastboot_tcp.o obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_PROT_UDP) += udp.o obj-$(CONFIG_PROT_TCP) += tcp.o diff --git a/net/dhcpv6.c b/net/dhcpv6.c new file mode 100644 index 00000000000..0d1c600632f --- /dev/null +++ b/net/dhcpv6.c @@ -0,0 +1,719 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) Microsoft Corporation + * Author: Sean Edmond <seanedmond@microsoft.com> + * + */ + +/* Simple DHCP6 network layer implementation. */ + +#include <common.h> +#include <net6.h> +#include <malloc.h> +#include <linux/delay.h> +#include "net_rand.h" +#include "dhcpv6.h" + +#define PORT_DHCP6_S 547 /* DHCP6 server UDP port */ +#define PORT_DHCP6_C 546 /* DHCP6 client UDP port */ + +/* default timeout parameters (in ms) */ +#define SOL_MAX_DELAY_MS 1000 +#define SOL_TIMEOUT_MS 1000 +#define SOL_MAX_RT_MS 3600000 +#define REQ_TIMEOUT_MS 1000 +#define REQ_MAX_RT_MS 30000 +#define REQ_MAX_RC 10 +#define MAX_WAIT_TIME_MS 60000 + +/* global variable to track any updates from DHCP6 server */ +int updated_sol_max_rt_ms = SOL_MAX_RT_MS; +/* state machine parameters/variables */ +struct dhcp6_sm_params sm_params; + +static void dhcp6_state_machine(bool timeout, uchar *rx_pkt, unsigned int len); + +/* Handle DHCP received packets (set as UDP handler) */ +static void dhcp6_handler(uchar *pkt, unsigned int dest, struct in_addr sip, + unsigned int src, unsigned int len) +{ + /* return if ports don't match DHCPv6 ports */ + if (dest != PORT_DHCP6_C || src != PORT_DHCP6_S) + return; + + dhcp6_state_machine(false, pkt, len); +} + +/** + * dhcp6_add_option() - Adds DHCP6 option to a packet + * @option_id: The option ID to add (See DHCP6_OPTION_* definitions) + * @pkt: A pointer to the current write location of the TX packet + * + * Return: The number of bytes written into "*pkt" + */ +static int dhcp6_add_option(int option_id, uchar *pkt) +{ + struct dhcp6_option_duid_ll *duid_opt; + struct dhcp6_option_elapsed_time *elapsed_time_opt; + struct dhcp6_option_ia_ta *ia_ta_opt; + struct dhcp6_option_ia_na *ia_na_opt; + struct dhcp6_option_oro *oro_opt; + struct dhcp6_option_client_arch *client_arch_opt; + struct dhcp6_option_vendor_class *vendor_class_opt; + int opt_len; + long elapsed_time; + size_t vci_strlen; + int num_oro = 0; + int num_client_arch = 0; + int num_vc_data = 0; + struct dhcp6_option_hdr *dhcp_option = (struct dhcp6_option_hdr *)pkt; + uchar *dhcp_option_start = pkt + sizeof(struct dhcp6_option_hdr); + + dhcp_option->option_id = htons(option_id); + + switch (option_id) { + case DHCP6_OPTION_CLIENTID: + /* Only support for DUID-LL in Client ID option for now */ + duid_opt = (struct dhcp6_option_duid_ll *)dhcp_option_start; + duid_opt->duid_type = htons(DUID_TYPE_LL); + duid_opt->hw_type = htons(DUID_HW_TYPE_ENET); + memcpy(duid_opt->ll_addr, net_ethaddr, ETH_ALEN); + opt_len = sizeof(struct dhcp6_option_duid_ll) + ETH_ALEN; + + /* Save DUID for comparison later */ + memcpy(sm_params.duid, duid_opt, opt_len); + break; + case DHCP6_OPTION_ELAPSED_TIME: + /* calculate elapsed time in 1/100th of a second */ + elapsed_time = (sm_params.dhcp6_retry_ms - + sm_params.dhcp6_start_ms) / 10; + if (elapsed_time > 0xFFFF) + elapsed_time = 0xFFFF; + + elapsed_time_opt = (struct dhcp6_option_elapsed_time *)dhcp_option_start; + elapsed_time_opt->elapsed_time = htons(elapsed_time); + + opt_len = sizeof(struct dhcp6_option_elapsed_time); + break; + case DHCP6_OPTION_IA_TA: + ia_ta_opt = (struct dhcp6_option_ia_ta *)dhcp_option_start; + ia_ta_opt->iaid = htonl(sm_params.ia_id); + + opt_len = sizeof(struct dhcp6_option_ia_ta); + break; + case DHCP6_OPTION_IA_NA: + ia_na_opt = (struct dhcp6_option_ia_na *)dhcp_option_start; + ia_na_opt->iaid = htonl(sm_params.ia_id); + /* In a message sent by a client to a server, + * the T1 and T2 fields SHOULD be set to 0 + */ + ia_na_opt->t1 = 0; + ia_na_opt->t2 = 0; + + opt_len = sizeof(struct dhcp6_option_ia_na); + break; + case DHCP6_OPTION_ORO: + oro_opt = (struct dhcp6_option_oro *)dhcp_option_start; + oro_opt->req_option_code[num_oro++] = htons(DHCP6_OPTION_OPT_BOOTFILE_URL); + oro_opt->req_option_code[num_oro++] = htons(DHCP6_OPTION_SOL_MAX_RT); + if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION)) { + oro_opt->req_option_code[num_oro++] = + htons(DHCP6_OPTION_OPT_BOOTFILE_PARAM); + } + + opt_len = sizeof(__be16) * num_oro; + break; + case DHCP6_OPTION_CLIENT_ARCH_TYPE: + client_arch_opt = (struct dhcp6_option_client_arch *)dhcp_option_start; + client_arch_opt->arch_type[num_client_arch++] = htons(CONFIG_DHCP6_PXE_CLIENTARCH); + + opt_len = sizeof(__be16) * num_client_arch; + break; + case DHCP6_OPTION_VENDOR_CLASS: + vendor_class_opt = (struct dhcp6_option_vendor_class *)dhcp_option_start; + vendor_class_opt->enterprise_number = htonl(CONFIG_DHCP6_ENTERPRISE_ID); + + vci_strlen = strlen(DHCP6_VCI_STRING); + vendor_class_opt->vendor_class_data[num_vc_data].vendor_class_len = + htons(vci_strlen); + memcpy(vendor_class_opt->vendor_class_data[num_vc_data].opaque_data, + DHCP6_VCI_STRING, vci_strlen); + num_vc_data++; + + opt_len = sizeof(struct dhcp6_option_vendor_class) + + sizeof(struct vendor_class_data) * num_vc_data + + vci_strlen; + break; + case DHCP6_OPTION_NII: + dhcp_option_start[0] = 1; + dhcp_option_start[1] = 0; + dhcp_option_start[2] = 0; + + opt_len = 3; + break; + default: + printf("***Warning unknown DHCP6 option %d. Not adding to message\n", option_id); + return 0; + } + dhcp_option->option_len = htons(opt_len); + + return opt_len + sizeof(struct dhcp6_option_hdr); +} + +/** + * dhcp6_send_solicit_packet() - Send a SOLICIT packet + * + * Implements RFC 8415: + * - 16.2. Solicit Message + * - 18.2.1. Creation and Transmission of Solicit Messages + * + * Adds DHCP6 header and DHCP6 options. Sends the UDP packet + * and sets the UDP handler. + */ +static void dhcp6_send_solicit_packet(void) +{ + struct in6_addr dhcp_bcast_ip6; + int len = 0; + uchar *pkt; + uchar *dhcp_pkt_start_ptr; + struct dhcp6_hdr *dhcp_hdr; + + pkt = net_tx_packet + net_eth_hdr_size() + IP6_HDR_SIZE + UDP_HDR_SIZE; + dhcp_pkt_start_ptr = pkt; + + /* Add the DHCP6 header */ + dhcp_hdr = (struct dhcp6_hdr *)pkt; + dhcp_hdr->msg_type = DHCP6_MSG_SOLICIT; + dhcp_hdr->trans_id = htons(sm_params.trans_id); + pkt += sizeof(struct dhcp6_hdr); + + /* Add the options */ + pkt += dhcp6_add_option(DHCP6_OPTION_CLIENTID, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_ELAPSED_TIME, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_IA_NA, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_ORO, pkt); + if (CONFIG_DHCP6_PXE_CLIENTARCH != 0xFF) + pkt += dhcp6_add_option(DHCP6_OPTION_CLIENT_ARCH_TYPE, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_VENDOR_CLASS, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_NII, pkt); + + /* calculate packet length */ + len = pkt - dhcp_pkt_start_ptr; + + /* send UDP packet to DHCP6 multicast address */ + string_to_ip6(DHCP6_MULTICAST_ADDR, sizeof(DHCP6_MULTICAST_ADDR), &dhcp_bcast_ip6); + net_set_udp_handler(dhcp6_handler); + net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6, + PORT_DHCP6_S, PORT_DHCP6_C, len); +} + +/** + * dhcp6_send_request_packet() - Send a REQUEST packet + * + * * Implements RFC 8415: + * - 16.4. Request Message + * - 18.2.2. Creation and Transmission of Request Messages + * + * Adds DHCP6 header and DHCP6 options. Sends the UDP packet + * and sets the UDP handler. + */ +static void dhcp6_send_request_packet(void) +{ + struct in6_addr dhcp_bcast_ip6; + int len = 0; + uchar *pkt; + uchar *dhcp_pkt_start_ptr; + struct dhcp6_hdr *dhcp_hdr; + + pkt = net_tx_packet + net_eth_hdr_size() + IP6_HDR_SIZE + UDP_HDR_SIZE; + dhcp_pkt_start_ptr = pkt; + + /* Add the DHCP6 header */ + dhcp_hdr = (struct dhcp6_hdr *)pkt; + dhcp_hdr->msg_type = DHCP6_MSG_REQUEST; + dhcp_hdr->trans_id = htons(sm_params.trans_id); + pkt += sizeof(struct dhcp6_hdr); + + /* add the options */ + pkt += dhcp6_add_option(DHCP6_OPTION_CLIENTID, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_ELAPSED_TIME, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_IA_NA, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_ORO, pkt); + /* copy received IA_TA/IA_NA into the REQUEST packet */ + if (sm_params.server_uid.uid_ptr) { + memcpy(pkt, sm_params.server_uid.uid_ptr, sm_params.server_uid.uid_size); + pkt += sm_params.server_uid.uid_size; + } + if (CONFIG_DHCP6_PXE_CLIENTARCH != 0xFF) + pkt += dhcp6_add_option(DHCP6_OPTION_CLIENT_ARCH_TYPE, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_VENDOR_CLASS, pkt); + pkt += dhcp6_add_option(DHCP6_OPTION_NII, pkt); + + /* calculate packet length */ + len = pkt - dhcp_pkt_start_ptr; + + /* send UDP packet to DHCP6 multicast address */ + string_to_ip6(DHCP6_MULTICAST_ADDR, strlen(DHCP6_MULTICAST_ADDR), &dhcp_bcast_ip6); + net_set_udp_handler(dhcp6_handler); + net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6, + PORT_DHCP6_S, PORT_DHCP6_C, len); +} + +static void dhcp6_parse_ia_options(struct dhcp6_option_hdr *ia_ptr, uchar *ia_option_ptr) +{ + struct dhcp6_option_hdr *ia_option_hdr; + + ia_option_hdr = (struct dhcp6_option_hdr *)ia_option_ptr; + + /* Search for options encapsulated in IA_NA/IA_TA (DHCP6_OPTION_IAADDR + * or DHCP6_OPTION_STATUS_CODE) + */ + while (ia_option_ptr < ((uchar *)ia_ptr + ntohs(ia_ptr->option_len))) { + switch (ntohs(ia_option_hdr->option_id)) { + case DHCP6_OPTION_IAADDR: + sm_params.rx_status.ia_addr_found = true; + net_copy_ip6(&sm_params.rx_status.ia_addr_ipv6, + (ia_option_ptr + sizeof(struct dhcp6_hdr))); + debug("DHCP6_OPTION_IAADDR FOUND\n"); + break; + case DHCP6_OPTION_STATUS_CODE: + sm_params.rx_status.ia_status_code = + ntohs(*((u16 *)(ia_option_ptr + sizeof(struct dhcp6_hdr)))); + printf("ERROR : IA STATUS %d\n", sm_params.rx_status.ia_status_code); + break; + default: + debug("Unknown Option in IA, skipping\n"); + break; + } + + ia_option_ptr += ntohs(((struct dhcp6_option_hdr *)ia_option_ptr)->option_len); + } +} + +/** + * dhcp6_parse_options() - Parse the DHCP6 options + * + * @rx_pkt: pointer to beginning of received DHCP6 packet + * @len: Total length of the DHCP6 packet + * + * Parses the DHCP options from a received DHCP packet. Perform error checking + * on the options received. Any relevant status is available in: + * "sm_params.rx_status" + * + */ +static void dhcp6_parse_options(uchar *rx_pkt, unsigned int len) +{ + uchar *option_ptr; + int sol_max_rt_sec, option_len; + char *s, *e; + struct dhcp6_option_hdr *option_hdr; + + memset(&sm_params.rx_status, 0, sizeof(struct dhcp6_rx_pkt_status)); + + option_hdr = (struct dhcp6_option_hdr *)(rx_pkt + sizeof(struct dhcp6_hdr)); + /* check that required options exist */ + while (option_hdr < (struct dhcp6_option_hdr *)(rx_pkt + len)) { + option_ptr = ((uchar *)option_hdr) + sizeof(struct dhcp6_hdr); + option_len = ntohs(option_hdr->option_len); + + switch (ntohs(option_hdr->option_id)) { + case DHCP6_OPTION_CLIENTID: + if (memcmp(option_ptr, sm_params.duid, option_len) + != 0) { + debug("CLIENT ID DOESN'T MATCH\n"); + } else { + debug("CLIENT ID FOUND and MATCHES\n"); + sm_params.rx_status.client_id_match = true; + } + break; + case DHCP6_OPTION_SERVERID: + sm_params.rx_status.server_id_found = true; + sm_params.rx_status.server_uid_ptr = (uchar *)option_hdr; + sm_params.rx_status.server_uid_size = option_len + + sizeof(struct dhcp6_option_hdr); + debug("SERVER ID FOUND\n"); + break; + case DHCP6_OPTION_IA_TA: + case DHCP6_OPTION_IA_NA: + /* check the IA_ID */ + if (*((u32 *)option_ptr) != htonl(sm_params.ia_id)) { + debug("IA_ID mismatch 0x%08x 0x%08x\n", + *((u32 *)option_ptr), htonl(sm_params.ia_id)); + break; + } + + if (ntohs(option_hdr->option_id) == DHCP6_OPTION_IA_NA) { + /* skip past IA_ID/T1/T2 */ + option_ptr += 3 * sizeof(u32); + } else if (ntohs(option_hdr->option_id) == DHCP6_OPTION_IA_TA) { + /* skip past IA_ID */ + option_ptr += sizeof(u32); + } + /* parse the IA_NA/IA_TA encapsulated options */ + dhcp6_parse_ia_options(option_hdr, option_ptr); + break; + case DHCP6_OPTION_STATUS_CODE: + debug("DHCP6_OPTION_STATUS_CODE FOUND\n"); + sm_params.rx_status.status_code = ntohs(*((u16 *)option_ptr)); + debug("DHCP6 top-level status code %d\n", sm_params.rx_status.status_code); + debug("DHCP6 status message: %.*s\n", len, option_ptr + 2); + break; + case DHCP6_OPTION_SOL_MAX_RT: + debug("DHCP6_OPTION_SOL_MAX_RT FOUND\n"); + sol_max_rt_sec = ntohl(*((u32 *)option_ptr)); + + /* A DHCP client MUST ignore any SOL_MAX_RT option values that are less + * than 60 or more than 86400 + */ + if (sol_max_rt_sec >= 60 && sol_max_rt_sec <= 86400) { + updated_sol_max_rt_ms = sol_max_rt_sec * 1000; + if (sm_params.curr_state == DHCP6_SOLICIT) + sm_params.mrt_ms = updated_sol_max_rt_ms; + } + break; + case DHCP6_OPTION_OPT_BOOTFILE_URL: + debug("DHCP6_OPTION_OPT_BOOTFILE_URL FOUND\n"); + copy_filename(net_boot_file_name, option_ptr, option_len + 1); + debug("net_boot_file_name: %s\n", net_boot_file_name); + + /* copy server_ip6 (required for PXE) */ + s = strchr(net_boot_file_name, '['); + e = strchr(net_boot_file_name, ']'); + if (s && e && e > s) + string_to_ip6(s + 1, e - s - 1, &net_server_ip6); + break; + case DHCP6_OPTION_OPT_BOOTFILE_PARAM: + if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION)) { + debug("DHCP6_OPTION_OPT_BOOTFILE_PARAM FOUND\n"); + + if (pxelinux_configfile) + free(pxelinux_configfile); + + pxelinux_configfile = (char *)malloc((option_len + 1) * + sizeof(char)); + if (pxelinux_configfile) + strlcpy(pxelinux_configfile, option_ptr, option_len + 1); + else + printf("Error: Failed to allocate pxelinux_configfile\n"); + + debug("PXE CONFIG FILE %s\n", pxelinux_configfile); + } + break; + case DHCP6_OPTION_PREFERENCE: + debug("DHCP6_OPTION_PREFERENCE FOUND\n"); + sm_params.rx_status.preference = *option_ptr; + break; + default: + debug("Unknown Option ID: %d, skipping parsing\n", + ntohs(option_hdr->option_id)); + break; + } + /* Increment to next option header */ + option_hdr = (struct dhcp6_option_hdr *)(((uchar *)option_hdr) + + sizeof(struct dhcp6_option_hdr) + option_len); + } +} + +/** + * dhcp6_check_advertise_packet() - Perform error checking on an expected + * ADVERTISE packet. + * + * @rx_pkt: pointer to beginning of received DHCP6 packet + * @len: Total length of the DHCP6 packet + * + * Implements RFC 8415: + * - 16.3. Advertise Message + * - 18.2.10. Receipt of Reply Messages + * + * Return : 0 : ADVERTISE packet was received with no errors. + * State machine can progress + * 1 : - packet received is not an ADVERTISE packet + * - there were errors in the packet received, + * - this is the first SOLICIT packet, but + * received preference is not 255, so we have + * to wait for more server responses. + */ +static int dhcp6_check_advertise_packet(uchar *rx_pkt, unsigned int len) +{ + u16 rx_uid_size; + struct dhcp6_hdr *dhcp6_hdr = (struct dhcp6_hdr *)rx_pkt; + + /* Ignore message if msg-type != advertise */ + if (dhcp6_hdr->msg_type != DHCP6_MSG_ADVERTISE) + return 1; + /* Ignore message if transaction ID doesn't match */ + if (dhcp6_hdr->trans_id != htons(sm_params.trans_id)) + return 1; + + dhcp6_parse_options(rx_pkt, len); + + /* Ignore advertise if any of these conditions met */ + if (!sm_params.rx_status.server_id_found || + !sm_params.rx_status.client_id_match || + sm_params.rx_status.status_code != DHCP6_SUCCESS) { + return 1; + } + + if (sm_params.rx_status.server_id_found) { + /* if no server UID has been received yet, or if the server UID + * received has a higher preference value than the currently saved + * server UID, save the new server UID and preference + */ + if (!sm_params.server_uid.uid_ptr || + (sm_params.server_uid.uid_ptr && + sm_params.server_uid.preference < sm_params.rx_status.preference)) { + rx_uid_size = sm_params.rx_status.server_uid_size; + if (sm_params.server_uid.uid_ptr) + free(sm_params.server_uid.uid_ptr); + sm_params.server_uid.uid_ptr = malloc(rx_uid_size * sizeof(uchar)); + if (sm_params.server_uid.uid_ptr) + memcpy(sm_params.server_uid.uid_ptr, + sm_params.rx_status.server_uid_ptr, rx_uid_size); + + sm_params.server_uid.uid_size = rx_uid_size; + sm_params.server_uid.preference = sm_params.rx_status.preference; + } + + /* If the first SOLICIT and preference code is 255, use right away. + * Otherwise, wait for the first SOLICIT period for more + * DHCP6 servers to respond. + */ + if (sm_params.retry_cnt == 1 && + sm_params.server_uid.preference != 255) { + debug("valid ADVERTISE, waiting for first SOLICIT period\n"); + return 1; + } + } + + return 0; +} + +/** + * dhcp6_check_reply_packet() - Perform error checking on an expected + * REPLY packet. + * + * @rx_pkt: pointer to beginning of received DHCP6 packet + * @len: Total length of the DHCP6 packet + * + * Implements RFC 8415: + * - 16.10. Reply Message + * - 18.2.10. Receipt of Reply Messages + * + * Return : 0 - REPLY packet was received with no errors + * 1 - packet received is not an REPLY packet, + * or there were errors in the packet received + */ +static int dhcp6_check_reply_packet(uchar *rx_pkt, unsigned int len) +{ + struct dhcp6_hdr *dhcp6_hdr = (struct dhcp6_hdr *)rx_pkt; + + /* Ignore message if msg-type != reply */ + if (dhcp6_hdr->msg_type != DHCP6_MSG_REPLY) + return 1; + /* check that transaction ID matches */ + if (dhcp6_hdr->trans_id != htons(sm_params.trans_id)) + return 1; + + dhcp6_parse_options(rx_pkt, len); + + /* if no addresses found, restart DHCP */ + if (!sm_params.rx_status.ia_addr_found || + sm_params.rx_status.ia_status_code == DHCP6_NO_ADDRS_AVAIL || + sm_params.rx_status.status_code == DHCP6_NOT_ON_LINK) { + /* restart DHCP */ + debug("No address found in reply. Restarting DHCP\n"); + dhcp6_start(); + } + + /* ignore reply if any of these conditions met */ + if (!sm_params.rx_status.server_id_found || + !sm_params.rx_status.client_id_match || + sm_params.rx_status.status_code == DHCP6_UNSPEC_FAIL) { + return 1; + } + + return 0; +} + +/* Timeout for DHCP6 SOLICIT/REQUEST */ +static void dhcp6_timeout_handler(void) +{ + /* call state machine with the timeout flag */ + dhcp6_state_machine(true, NULL, 0); +} + +/** + * dhcp6_state_machine() - DHCP6 state machine + * + * @timeout: TRUE : timeout waiting for response from + * DHCP6 server + * FALSE : init or received response from DHCP6 server + * @rx_pkt: Pointer to the beginning of received DHCP6 packet. + * Will be NULL if called as part of init + * or timeout==TRUE + * @len: Total length of the DHCP6 packet if rx_pkt != NULL + * + * Implements RFC 8415: + * - 5.2. Client/Server Exchanges Involving Four Messages + * - 15. Reliability of Client-Initiated Message Exchanges + * + * Handles: + * - transmission of SOLICIT and REQUEST packets + * - retransmission of SOLICIT and REQUEST packets if no + * response is received within the timeout window + * - checking received ADVERTISE and REPLY packets to + * assess if the DHCP state machine can progress + */ +static void dhcp6_state_machine(bool timeout, uchar *rx_pkt, unsigned int len) +{ + int rand_minus_plus_100; + + switch (sm_params.curr_state) { + case DHCP6_INIT: + sm_params.next_state = DHCP6_SOLICIT; + break; + case DHCP6_SOLICIT: + if (!timeout) { + /* check the rx packet and determine if we can transition to next + * state. + */ + if (dhcp6_check_advertise_packet(rx_pkt, len)) + return; + + debug("ADVERTISE good, transition to REQUEST\n"); + sm_params.next_state = DHCP6_REQUEST; + } else if (sm_params.retry_cnt == 1) { + /* If a server UID was received in the first SOLICIT period + * transition to REQUEST + */ + if (sm_params.server_uid.uid_ptr) + sm_params.next_state = DHCP6_REQUEST; + } + break; + case DHCP6_REQUEST: + if (!timeout) { + /* check the rx packet and determine if we can transition to next state */ + if (dhcp6_check_reply_packet(rx_pkt, len)) + return; + + debug("REPLY good, transition to DONE\n"); + sm_params.next_state = DHCP6_DONE; + } + break; + case DHCP6_DONE: + case DHCP6_FAIL: + /* Shouldn't get here, as state machine should exit + * immediately when DHCP6_DONE or DHCP6_FAIL is entered. + * Proceed anyway to proceed DONE/FAIL actions + */ + debug("Unexpected DHCP6 state : %d\n", sm_params.curr_state); + break; + } + /* re-seed the RNG */ + srand(get_ticks() + rand()); + + /* handle state machine entry conditions */ + if (sm_params.curr_state != sm_params.next_state) { + sm_params.retry_cnt = 0; + + if (sm_params.next_state == DHCP6_SOLICIT) { + /* delay a random ammount (special for SOLICIT) */ + udelay((rand() % SOL_MAX_DELAY_MS) * 1000); + /* init timestamp variables after SOLICIT delay */ + sm_params.dhcp6_start_ms = get_timer(0); + sm_params.dhcp6_retry_start_ms = sm_params.dhcp6_start_ms; + sm_params.dhcp6_retry_ms = sm_params.dhcp6_start_ms; + /* init transaction and ia_id */ + sm_params.trans_id = rand() & 0xFFFFFF; + sm_params.ia_id = rand(); + /* initialize retransmission parameters */ + sm_params.irt_ms = SOL_TIMEOUT_MS; + sm_params.mrt_ms = updated_sol_max_rt_ms; + /* RFCs default MRC is be 0 (try infinitely) + * give up after CONFIG_NET_RETRY_COUNT number of tries (same as DHCPv4) + */ + sm_params.mrc = CONFIG_NET_RETRY_COUNT; + sm_params.mrd_ms = 0; + + } else if (sm_params.next_state == DHCP6_REQUEST) { + /* init timestamp variables */ + sm_params.dhcp6_retry_start_ms = get_timer(0); + sm_params.dhcp6_retry_ms = sm_params.dhcp6_start_ms; + /* initialize retransmission parameters */ + sm_params.irt_ms = REQ_TIMEOUT_MS; + sm_params.mrt_ms = REQ_MAX_RT_MS; + sm_params.mrc = REQ_MAX_RC; + sm_params.mrd_ms = 0; + } + } + + if (timeout) + sm_params.dhcp6_retry_ms = get_timer(0); + + /* Check if MRC or MRD have been passed */ + if ((sm_params.mrc != 0 && + sm_params.retry_cnt >= sm_params.mrc) || + (sm_params.mrd_ms != 0 && + ((sm_params.dhcp6_retry_ms - sm_params.dhcp6_retry_start_ms) >= sm_params.mrd_ms))) { + sm_params.next_state = DHCP6_FAIL; + } + + /* calculate retransmission timeout (RT) */ + rand_minus_plus_100 = ((rand() % 200) - 100); + if (sm_params.retry_cnt == 0) { + sm_params.rt_ms = sm_params.irt_ms + + ((sm_params.irt_ms * rand_minus_plus_100) / 1000); + } else { + sm_params.rt_ms = (2 * sm_params.rt_prev_ms) + + ((sm_params.rt_prev_ms * rand_minus_plus_100) / 1000); + } + + if (sm_params.rt_ms > sm_params.mrt_ms) { + sm_params.rt_ms = sm_params.mrt_ms + + ((sm_params.mrt_ms * rand_minus_plus_100) / 1000); + } + + sm_params.rt_prev_ms = sm_params.rt_ms; + + net_set_timeout_handler(sm_params.rt_ms, dhcp6_timeout_handler); + + /* send transmit/retransmit message or fail */ + sm_params.curr_state = sm_params.next_state; + + if (sm_params.curr_state == DHCP6_SOLICIT) { + /* send solicit packet */ + dhcp6_send_solicit_packet(); + printf("DHCP6 SOLICIT %d\n", sm_params.retry_cnt); + } else if (sm_params.curr_state == DHCP6_REQUEST) { + /* send request packet */ + dhcp6_send_request_packet(); + printf("DHCP6 REQUEST %d\n", sm_params.retry_cnt); + } else if (sm_params.curr_state == DHCP6_DONE) { + net_set_timeout_handler(0, NULL); + + /* Duplicate address detection (DAD) should be + * performed here before setting net_ip6 + * (enhancement should be considered) + */ + net_copy_ip6(&net_ip6, &sm_params.rx_status.ia_addr_ipv6); + printf("DHCP6 client bound to %pI6c\n", &net_ip6); + /* will load with TFTP6 */ + net_auto_load(); + } else if (sm_params.curr_state == DHCP6_FAIL) { + printf("DHCP6 FAILED, TERMINATING\n"); + net_set_state(NETLOOP_FAIL); + } + sm_params.retry_cnt++; +} + +/* Start or restart DHCP6 */ +void dhcp6_start(void) +{ + memset(&sm_params, 0, sizeof(struct dhcp6_sm_params)); + + /* seed the RNG with MAC address */ + srand_mac(); + + sm_params.curr_state = DHCP6_INIT; + dhcp6_state_machine(false, NULL, 0); +} diff --git a/net/dhcpv6.h b/net/dhcpv6.h new file mode 100644 index 00000000000..80ca5204325 --- /dev/null +++ b/net/dhcpv6.h @@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Microsoft Corporation + * Author: Sean Edmond <seanedmond@microsoft.com> + * + */ + +#ifndef __DHCP6_H__ +#define __DHCP6_H__ + +/* Message types */ +#define DHCP6_MSG_SOLICIT 1 +#define DHCP6_MSG_ADVERTISE 2 +#define DHCP6_MSG_REQUEST 3 +#define DHCP6_MSG_REPLY 7 + +/* Option Codes */ +#define DHCP6_OPTION_CLIENTID 1 +#define DHCP6_OPTION_SERVERID 2 +#define DHCP6_OPTION_IA_NA 3 +#define DHCP6_OPTION_IA_TA 4 +#define DHCP6_OPTION_IAADDR 5 +#define DHCP6_OPTION_ORO 6 +#define DHCP6_OPTION_PREFERENCE 7 +#define DHCP6_OPTION_ELAPSED_TIME 8 +#define DHCP6_OPTION_STATUS_CODE 13 +#define DHCP6_OPTION_OPT_BOOTFILE_URL 59 +#define DHCP6_OPTION_OPT_BOOTFILE_PARAM 60 +#define DHCP6_OPTION_SOL_MAX_RT 82 +#define DHCP6_OPTION_CLIENT_ARCH_TYPE 61 +#define DHCP6_OPTION_VENDOR_CLASS 16 +#define DHCP6_OPTION_NII 62 + +/* DUID */ +#define DUID_TYPE_LL 3 +#define DUID_HW_TYPE_ENET 1 +#define DUID_LL_SIZE (sizeof(struct dhcp6_option_duid_ll) + ETH_ALEN) +#define DUID_MAX_SIZE DUID_LL_SIZE /* only supports DUID-LL currently */ + +/* vendor-class-data to send in vendor clas option */ +#define DHCP6_VCI_STRING "U-boot" + +#define DHCP6_MULTICAST_ADDR "ff02::1:2" /* DHCP multicast address */ + +/* DHCP6 States supported */ +enum dhcp6_state { + DHCP6_INIT, + DHCP6_SOLICIT, + DHCP6_REQUEST, + DHCP6_DONE, + DHCP6_FAIL, +}; + +/* DHCP6 Status codes */ +enum dhcp6_status { + DHCP6_SUCCESS = 0, + DHCP6_UNSPEC_FAIL = 1, + DHCP6_NO_ADDRS_AVAIL = 2, + DHCP6_NO_BINDING = 3, + DHCP6_NOT_ON_LINK = 4, + DHCP6_USE_MULTICAST = 5, + DHCP6_NO_PREFIX_AVAIL = 6, +}; + +/* DHCP6 message header format */ +struct dhcp6_hdr { + unsigned int msg_type : 8; /* message type */ + unsigned int trans_id : 24; /* transaction ID */ +} __packed; + +/* DHCP6 option header format */ +struct dhcp6_option_hdr { + __be16 option_id; /* option id */ + __be16 option_len; /* Option length */ + u8 option_data[0]; /* Option data */ +} __packed; + +/* DHCP6_OPTION_CLIENTID option (DUID-LL) */ +struct dhcp6_option_duid_ll { + __be16 duid_type; + __be16 hw_type; + u8 ll_addr[0]; +} __packed; + +/* DHCP6_OPTION_ELAPSED_TIME option */ +struct dhcp6_option_elapsed_time { + __be16 elapsed_time; +} __packed; + +/* DHCP6_OPTION_IA_TA option */ +struct dhcp6_option_ia_ta { + __be32 iaid; + u8 ia_ta_options[0]; +} __packed; + +/* DHCP6_OPTION_IA_NA option */ +struct dhcp6_option_ia_na { + __be32 iaid; + __be32 t1; + __be32 t2; + u8 ia_na_options[0]; +} __packed; + +/* OPTION_ORO option */ +struct dhcp6_option_oro { + __be16 req_option_code[0]; +} __packed; + +/* DHCP6_OPTION_CLIENT_ARCH_TYPE option */ +struct dhcp6_option_client_arch { + __be16 arch_type[0]; +} __packed; + +/* vendor-class-data inside OPTION_VENDOR_CLASS option */ +struct vendor_class_data { + __be16 vendor_class_len; + u8 opaque_data[0]; +} __packed; + +/* DHCP6_OPTION_VENDOR_CLASS option */ +struct dhcp6_option_vendor_class { + __be32 enterprise_number; + struct vendor_class_data vendor_class_data[0]; +} __packed; + +/** + * struct dhcp6_rx_pkt_status - Structure that holds status + * from a received message + * @client_id_match: Client ID was found and matches DUID sent + * @server_id_found: Server ID was found in the message + * @server_uid_ptr: Pointer to received server ID + * @server_uid_size: Size of received server ID + * @ia_addr_found: IA addr option was found in received message + * @ia_addr_ipv6: The IPv6 address received in IA + * @ia_status_code: Status code received in the IA + * @status_code: Top-level status code received + * @preference: Preference code received + */ +struct dhcp6_rx_pkt_status { + bool client_id_match; + bool server_id_found; + uchar *server_uid_ptr; + u16 server_uid_size; + bool ia_addr_found; + struct in6_addr ia_addr_ipv6; + enum dhcp6_status ia_status_code; + enum dhcp6_status status_code; + u8 preference; +}; + +/** + * struct dhcp6_server_uid - Structure that holds the server UID + * received from an ADVERTISE and saved + * given the server selection criteria. + * @uid_ptr: Dynamically allocated and copied server UID + * @uid_size: Size of the server UID in uid_ptr (in bytes) + * @preference: Preference code associated with this server UID + */ +struct dhcp6_server_uid { + uchar *uid_ptr; + u16 uid_size; + u8 preference; +}; + +/** + * struct dhcp6_sm_params - Structure that holds DHCP6 + * state machine parameters + * @curr_state: current DHCP6 state + * @next_state: next DHCP6 state + * @dhcp6_start_ms: timestamp DHCP6 start + * @dhcp6_retry_start_ms: timestamp of current TX message start + * @dhcp6_retry_ms: timestamp of last retransmission + * @retry_cnt: retry count + * @trans_id: transaction ID + * @ia_id: transmitted IA ID + * @irt_ms: Initial retransmission time (in ms) + * @mrt_ms: Maximum retransmission time (in ms) + * @mrc: Maximum retransmission count + * @mrd_ms: Maximum retransmission duration (in ms) + * @rt_ms: retransmission timeout (is ms) + * @rt_prev_ms: previous retransmission timeout + * @rx_status: Status from received message + * @server_uid: Saved Server UID for selected server + * @duid: pointer to transmitted Client DUID + */ +struct dhcp6_sm_params { + enum dhcp6_state curr_state; + enum dhcp6_state next_state; + ulong dhcp6_start_ms; + ulong dhcp6_retry_start_ms; + ulong dhcp6_retry_ms; + u32 retry_cnt; + u32 trans_id; + u32 ia_id; + int irt_ms; + int mrt_ms; + int mrc; + int mrd_ms; + int rt_ms; + int rt_prev_ms; + struct dhcp6_rx_pkt_status rx_status; + struct dhcp6_server_uid server_uid; + char duid[DUID_MAX_SIZE]; +}; + +/* Starts a DHCPv6 4-message exchange as a DHCPv6 client. On successful exchange, + * the DHCPv6 state machine will transition from internal states: + * DHCP6_INIT->DHCP6_SOLICIT->DHCP6_REQUEST->DHCP6_DONE + * + * Transmitted SOLICIT and REQUEST packets will set/request the minimum required + * DHCPv6 options to PXE boot. + * + * After a successful exchange, the DHCPv6 assigned address will be set in net_ip6 + * + * Additionally, the following will be set after receiving these options: + * DHCP6_OPTION_OPT_BOOTFILE_URL (option 59) -> net_server_ip6, net_boot_file_name + * DHCP6_OPTION_OPT_BOOTFILE_PARAM (option 60) - > pxelinux_configfile + * + * Illustration of a 4-message exchange with 2 servers (copied from + * https://www.rfc-editor.org/rfc/rfc8415): + * + * Server Server + * (not selected) Client (selected) + * + * v v v + * | | | + * | Begins initialization | + * | | | + * start of | _____________/|\_____________ | + * 4-message |/ Solicit | Solicit \| + * exchange | | | + * Determines | Determines + * configuration | configuration + * | | | + * |\ | ____________/| + * | \________ | /Advertise | + * | Advertise\ |/ | + * | \ | | + * | Collects Advertises | + * | \ | | + * | Selects configuration | + * | | | + * | _____________/|\_____________ | + * |/ Request | Request \| + * | | | + * | | Commits configuration + * | | | + * end of | | _____________/| + * 4-message | |/ Reply | + * exchange | | | + * | Initialization complete | + * | | | + */ +void dhcp6_start(void); + +#endif /* __DHCP6_H__ */ diff --git a/net/fastboot_tcp.c b/net/fastboot_tcp.c new file mode 100644 index 00000000000..2eb52ea2567 --- /dev/null +++ b/net/fastboot_tcp.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2023 The Android Open Source Project + */ + +#include <common.h> +#include <fastboot.h> +#include <net.h> +#include <net/fastboot_tcp.h> +#include <net/tcp.h> + +static char command[FASTBOOT_COMMAND_LEN] = {0}; +static char response[FASTBOOT_RESPONSE_LEN] = {0}; + +static const unsigned short handshake_length = 4; +static const uchar *handshake = "FB01"; + +static u16 curr_sport; +static u16 curr_dport; +static u32 curr_tcp_seq_num; +static u32 curr_tcp_ack_num; +static unsigned int curr_request_len; +static enum fastboot_tcp_state { + FASTBOOT_CLOSED, + FASTBOOT_CONNECTED, + FASTBOOT_DISCONNECTING +} state = FASTBOOT_CLOSED; + +static void fastboot_tcp_answer(u8 action, unsigned int len) +{ + const u32 response_seq_num = curr_tcp_ack_num; + const u32 response_ack_num = curr_tcp_seq_num + + (curr_request_len > 0 ? curr_request_len : 1); + + net_send_tcp_packet(len, htons(curr_sport), htons(curr_dport), + action, response_seq_num, response_ack_num); +} + +static void fastboot_tcp_reset(void) +{ + fastboot_tcp_answer(TCP_RST, 0); + state = FASTBOOT_CLOSED; +} + +static void fastboot_tcp_send_packet(u8 action, const uchar *data, unsigned int len) +{ + uchar *pkt = net_get_async_tx_pkt_buf(); + + memset(pkt, '\0', PKTSIZE); + pkt += net_eth_hdr_size() + IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; + memcpy(pkt, data, len); + fastboot_tcp_answer(action, len); + memset(pkt, '\0', PKTSIZE); +} + +static void fastboot_tcp_send_message(const char *message, unsigned int len) +{ + __be64 len_be = __cpu_to_be64(len); + uchar *pkt = net_get_async_tx_pkt_buf(); + + memset(pkt, '\0', PKTSIZE); + pkt += net_eth_hdr_size() + IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; + // Put first 8 bytes as a big endian message length + memcpy(pkt, &len_be, 8); + pkt += 8; + memcpy(pkt, message, len); + fastboot_tcp_answer(TCP_ACK | TCP_PUSH, len + 8); + memset(pkt, '\0', PKTSIZE); +} + +static void fastboot_tcp_handler_ipv4(uchar *pkt, u16 dport, + struct in_addr sip, u16 sport, + u32 tcp_seq_num, u32 tcp_ack_num, + u8 action, unsigned int len) +{ + int fastboot_command_id; + u64 command_size; + u8 tcp_fin = action & TCP_FIN; + u8 tcp_push = action & TCP_PUSH; + + curr_sport = sport; + curr_dport = dport; + curr_tcp_seq_num = tcp_seq_num; + curr_tcp_ack_num = tcp_ack_num; + curr_request_len = len; + + switch (state) { + case FASTBOOT_CLOSED: + if (tcp_push) { + if (len != handshake_length || + strlen(pkt) != handshake_length || + memcmp(pkt, handshake, handshake_length) != 0) { + fastboot_tcp_reset(); + break; + } + fastboot_tcp_send_packet(TCP_ACK | TCP_PUSH, + handshake, handshake_length); + state = FASTBOOT_CONNECTED; + } + break; + case FASTBOOT_CONNECTED: + if (tcp_fin) { + fastboot_tcp_answer(TCP_FIN | TCP_ACK, 0); + state = FASTBOOT_DISCONNECTING; + break; + } + if (tcp_push) { + // First 8 bytes is big endian message length + command_size = __be64_to_cpu(*(u64 *)pkt); + len -= 8; + pkt += 8; + + // Only single packet messages are supported ATM + if (strlen(pkt) != command_size) { + fastboot_tcp_reset(); + break; + } + strlcpy(command, pkt, len + 1); + fastboot_command_id = fastboot_handle_command(command, response); + fastboot_tcp_send_message(response, strlen(response)); + fastboot_handle_boot(fastboot_command_id, + strncmp("OKAY", response, 4) == 0); + } + break; + case FASTBOOT_DISCONNECTING: + if (tcp_push) + state = FASTBOOT_CLOSED; + break; + } + + memset(command, 0, FASTBOOT_COMMAND_LEN); + memset(response, 0, FASTBOOT_RESPONSE_LEN); + curr_sport = 0; + curr_dport = 0; + curr_tcp_seq_num = 0; + curr_tcp_ack_num = 0; + curr_request_len = 0; +} + +void fastboot_tcp_start_server(void) +{ + printf("Using %s device\n", eth_get_name()); + printf("Listening for fastboot command on tcp %pI4\n", &net_ip); + + tcp_set_tcp_handler(fastboot_tcp_handler_ipv4); +} diff --git a/net/fastboot.c b/net/fastboot_udp.c index e9569d88d2a..d706928d168 100644 --- a/net/fastboot.c +++ b/net/fastboot_udp.c @@ -7,7 +7,7 @@ #include <command.h> #include <fastboot.h> #include <net.h> -#include <net/fastboot.h> +#include <net/fastboot_udp.h> enum { FASTBOOT_ERROR = 0, @@ -40,8 +40,6 @@ static int fastboot_remote_port; /* The UDP port at our end */ static int fastboot_our_port; -static void boot_downloaded_image(void); - /** * fastboot_udp_send_info() - Send an INFO packet during long commands. * @@ -209,40 +207,13 @@ static void fastboot_send(struct fastboot_header header, char *fastboot_data, net_send_udp_packet(net_server_ethaddr, fastboot_remote_ip, fastboot_remote_port, fastboot_our_port, len); - /* Continue boot process after sending response */ - if (!strncmp("OKAY", response, 4)) { - switch (cmd) { - case FASTBOOT_COMMAND_BOOT: - boot_downloaded_image(); - break; - - case FASTBOOT_COMMAND_CONTINUE: - net_set_state(NETLOOP_SUCCESS); - break; - - case FASTBOOT_COMMAND_REBOOT: - case FASTBOOT_COMMAND_REBOOT_BOOTLOADER: - case FASTBOOT_COMMAND_REBOOT_FASTBOOTD: - case FASTBOOT_COMMAND_REBOOT_RECOVERY: - do_reset(NULL, 0, 0, NULL); - break; - } - } + fastboot_handle_boot(cmd, strncmp("OKAY", response, 4) == 0); if (!strncmp("OKAY", response, 4) || !strncmp("FAIL", response, 4)) cmd = -1; } /** - * boot_downloaded_image() - Boots into downloaded image. - */ -static void boot_downloaded_image(void) -{ - fastboot_boot(); - net_set_state(NETLOOP_SUCCESS); -} - -/** * fastboot_handler() - Incoming UDP packet handler. * * @packet: Pointer to incoming UDP packet @@ -300,7 +271,7 @@ static void fastboot_handler(uchar *packet, unsigned int dport, } } -void fastboot_start_server(void) +void fastboot_udp_start_server(void) { printf("Using %s device\n", eth_get_name()); printf("Listening for fastboot command on %pI4\n", &net_ip); diff --git a/net/ndisc.c b/net/ndisc.c index 367dae76766..0b27779ce5a 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -13,6 +13,8 @@ #include <net.h> #include <net6.h> #include <ndisc.h> +#include <stdlib.h> +#include <linux/delay.h> /* IPv6 destination address of packet waiting for ND */ struct in6_addr net_nd_sol_packet_ip6 = ZERO_IPV6_ADDR; @@ -29,31 +31,37 @@ int net_nd_tx_packet_size; ulong net_nd_timer_start; /* the number of requests we have sent so far */ int net_nd_try; +struct in6_addr all_routers = ALL_ROUTERS_MULT_ADDR; + +#define MAX_RTR_SOLICITATIONS 3 +/* The maximum time to delay sending the first router solicitation message. */ +#define MAX_SOLICITATION_DELAY 1 // 1 second +/* The time to wait before sending the next router solicitation message. */ +#define RTR_SOLICITATION_INTERVAL 4000 // 4 seconds #define IP6_NDISC_OPT_SPACE(len) (((len) + 2 + 7) & ~7) /** * ndisc_insert_option() - Insert an option into a neighbor discovery packet * - * @ndisc: pointer to ND packet + * @opt: pointer to the option element of the neighbor discovery packet * @type: option type to insert * @data: option data to insert * @len: data length * Return: the number of bytes inserted (which may be >= len) */ -static int -ndisc_insert_option(struct nd_msg *ndisc, int type, u8 *data, int len) +static int ndisc_insert_option(__u8 *opt, int type, u8 *data, int len) { int space = IP6_NDISC_OPT_SPACE(len); - ndisc->opt[0] = type; - ndisc->opt[1] = space >> 3; - memcpy(&ndisc->opt[2], data, len); + opt[0] = type; + opt[1] = space >> 3; + memcpy(&opt[2], data, len); len += 2; /* fill the remainder with 0 */ if (space - len > 0) - memset(&ndisc->opt[len], '\0', space - len); + memset(&opt[len], '\0', space - len); return space; } @@ -123,7 +131,7 @@ static void ip6_send_ns(struct in6_addr *neigh_addr) /* Set the target address and llsaddr option */ net_copy_ip6(&msg->target, neigh_addr); - ndisc_insert_option(msg, ND_OPT_SOURCE_LL_ADDR, net_ethaddr, + ndisc_insert_option(msg->opt, ND_OPT_SOURCE_LL_ADDR, net_ethaddr, INETHADDRSZ); /* checksum */ @@ -137,6 +145,76 @@ static void ip6_send_ns(struct in6_addr *neigh_addr) net_send_packet(net_tx_packet, (pkt - net_tx_packet)); } +/* + * ip6_send_rs() - Send IPv6 Router Solicitation Message. + * + * A router solicitation is sent to discover a router. RS message creation is + * based on RFC 4861 section 4.1. Router Solicitation Message Format. + */ +void ip6_send_rs(void) +{ + unsigned char enetaddr[6]; + struct rs_msg *msg; + __u16 icmp_len; + uchar *pkt; + unsigned short csum; + unsigned int pcsum; + static unsigned int retry_count; + + if (!ip6_is_unspecified_addr(&net_gateway6) && + net_prefix_length != 0) { + net_set_state(NETLOOP_SUCCESS); + return; + } else if (retry_count >= MAX_RTR_SOLICITATIONS) { + net_set_state(NETLOOP_FAIL); + net_set_timeout_handler(0, NULL); + retry_count = 0; + return; + } + + printf("ROUTER SOLICITATION %d\n", retry_count + 1); + + ip6_make_mult_ethdstaddr(enetaddr, &all_routers); + /* + * ICMP length is the size of ICMP header (8) + one option (8) = 16. + * The option is 2 bytes of type and length + 6 bytes for MAC. + */ + icmp_len = sizeof(struct icmp6hdr) + IP6_NDISC_OPT_SPACE(INETHADDRSZ); + + pkt = (uchar *)net_tx_packet; + pkt += net_set_ether(pkt, enetaddr, PROT_IP6); + pkt += ip6_add_hdr(pkt, &net_link_local_ip6, &all_routers, PROT_ICMPV6, + IPV6_NDISC_HOPLIMIT, icmp_len); + + /* ICMPv6 - RS */ + msg = (struct rs_msg *)pkt; + msg->icmph.icmp6_type = IPV6_NDISC_ROUTER_SOLICITATION; + msg->icmph.icmp6_code = 0; + memset(&msg->icmph.icmp6_cksum, 0, sizeof(__be16)); + memset(&msg->icmph.icmp6_unused, 0, sizeof(__be32)); + + /* Set the llsaddr option */ + ndisc_insert_option(msg->opt, ND_OPT_SOURCE_LL_ADDR, net_ethaddr, + INETHADDRSZ); + + /* checksum */ + pcsum = csum_partial((__u8 *)msg, icmp_len, 0); + csum = csum_ipv6_magic(&net_link_local_ip6, &all_routers, + icmp_len, PROT_ICMPV6, pcsum); + msg->icmph.icmp6_cksum = csum; + pkt += icmp_len; + + /* Wait up to 1 second if it is the first try to get the RA */ + if (retry_count == 0) + udelay(((unsigned int)rand() % 1000000) * MAX_SOLICITATION_DELAY); + + /* send it! */ + net_send_packet(net_tx_packet, (pkt - net_tx_packet)); + + retry_count++; + net_set_timeout_handler(RTR_SOLICITATION_INTERVAL, ip6_send_rs); +} + static void ip6_send_na(uchar *eth_dst_addr, struct in6_addr *neigh_addr, struct in6_addr *target) @@ -167,7 +245,7 @@ ip6_send_na(uchar *eth_dst_addr, struct in6_addr *neigh_addr, msg->icmph.icmp6_dataun.u_nd_advt.override = 1; /* Set the target address and lltargetaddr option */ net_copy_ip6(&msg->target, target); - ndisc_insert_option(msg, ND_OPT_TARGET_LL_ADDR, net_ethaddr, + ndisc_insert_option(msg->opt, ND_OPT_TARGET_LL_ADDR, net_ethaddr, INETHADDRSZ); /* checksum */ @@ -223,6 +301,10 @@ int ndisc_timeout_check(void) return 1; } +/* + * ndisc_init() - Make initial steps for ND state machine. + * Usually move variables into initial state. + */ void ndisc_init(void) { net_nd_packet_mac = NULL; @@ -234,12 +316,125 @@ void ndisc_init(void) net_nd_tx_packet -= (ulong)net_nd_tx_packet % PKTALIGN; } +/* + * validate_ra() - Validate the router advertisement message. + * + * @ip6: Pointer to the router advertisement packet + * + * Check if the router advertisement message is valid. Conditions are + * according to RFC 4861 section 6.1.2. Validation of Router Advertisement + * Messages. + * + * Return: true if the message is valid and false if it is invalid. + */ +bool validate_ra(struct ip6_hdr *ip6) +{ + struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1); + + /* ICMP length (derived from the IP length) should be 16 or more octets. */ + if (ip6->payload_len < 16) + return false; + + /* Source IP Address should be a valid link-local address. */ + if ((ntohs(ip6->saddr.s6_addr16[0]) & IPV6_LINK_LOCAL_MASK) != + IPV6_LINK_LOCAL_PREFIX) + return false; + + /* + * The IP Hop Limit field should have a value of 255, i.e., the packet + * could not possibly have been forwarded by a router. + */ + if (ip6->hop_limit != 255) + return false; + + /* ICMP checksum has already been checked in net_ip6_handler. */ + + if (icmp->icmp6_code != 0) + return false; + + return true; +} + +/* + * process_ra() - Process the router advertisement packet. + * + * @ip6: Pointer to the router advertisement packet + * @len: Length of the router advertisement packet + * + * Process the received router advertisement message. + * Although RFC 4861 requires retaining at least two router addresses, we only + * keep one because of the U-Boot limitations and its goal of lightweight code. + * + * Return: 0 - RA is a default router and contains valid prefix information. + * Non-zero - RA options are invalid or do not indicate it is a default router + * or do not contain valid prefix information. + */ +int process_ra(struct ip6_hdr *ip6, int len) +{ + /* Pointer to the ICMP section of the packet */ + struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1); + struct ra_msg *msg = (struct ra_msg *)icmp; + int remaining_option_len = len - IP6_HDR_SIZE - sizeof(struct ra_msg); + unsigned short int option_len; /* Length of each option */ + /* Pointer to the ICMPv6 message options */ + unsigned char *option = NULL; + /* 8-bit identifier of the type of ICMPv6 option */ + unsigned char type = 0; + struct icmp6_ra_prefix_info *prefix = NULL; + + /* Ignore the packet if router lifetime is 0. */ + if (!icmp->icmp6_rt_lifetime) + return -EOPNOTSUPP; + + /* Processing the options */ + option = msg->opt; + while (remaining_option_len > 0) { + /* The 2nd byte of the option is its length. */ + option_len = option[1]; + /* All included options should have a positive length. */ + if (option_len == 0) + return -EINVAL; + + type = option[0]; + /* All option types except Prefix Information are ignored. */ + switch (type) { + case ND_OPT_SOURCE_LL_ADDR: + case ND_OPT_TARGET_LL_ADDR: + case ND_OPT_REDIRECT_HDR: + case ND_OPT_MTU: + break; + case ND_OPT_PREFIX_INFO: + prefix = (struct icmp6_ra_prefix_info *)option; + /* The link-local prefix 0xfe80::/10 is ignored. */ + if ((ntohs(prefix->prefix.s6_addr16[0]) & + IPV6_LINK_LOCAL_MASK) == IPV6_LINK_LOCAL_PREFIX) + break; + if (prefix->on_link && ntohl(prefix->valid_lifetime)) { + net_prefix_length = prefix->prefix_len; + net_gateway6 = ip6->saddr; + return 0; + } + break; + default: + debug("Unknown IPv6 Neighbor Discovery Option 0x%x\n", + type); + } + + option_len <<= 3; /* Option length is a multiple of 8. */ + remaining_option_len -= option_len; + option += option_len; + } + + return -EADDRNOTAVAIL; +} + int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) { struct icmp6hdr *icmp = (struct icmp6hdr *)(((uchar *)ip6) + IP6_HDR_SIZE); struct nd_msg *ndisc = (struct nd_msg *)icmp; uchar neigh_eth_addr[6]; + int err = 0; // The error code returned calling functions. switch (icmp->icmp6_type) { case IPV6_NDISC_NEIGHBOUR_SOLICITATION: @@ -280,6 +475,36 @@ int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) net_nd_packet_mac = NULL; } break; + case IPV6_NDISC_ROUTER_SOLICITATION: + break; + case IPV6_NDISC_ROUTER_ADVERTISEMENT: + debug("Received router advertisement for %pI6c from %pI6c\n", + &ip6->daddr, &ip6->saddr); + /* + * If gateway and prefix are set, the RA packet is ignored. The + * reason is that the U-Boot code is supposed to be as compact + * as possible and does not need to take care of multiple + * routers. In addition to that, U-Boot does not want to handle + * scenarios like a router setting its lifetime to zero to + * indicate it is not routing anymore. U-Boot program has a + * short life when the system boots up and does not need such + * sophistication. + */ + if (!ip6_is_unspecified_addr(&net_gateway6) && + net_prefix_length != 0) { + break; + } + if (!validate_ra(ip6)) { + debug("Invalid router advertisement message.\n"); + break; + } + err = process_ra(ip6, len); + if (err) + debug("Ignored router advertisement. Error: %d\n", err); + else + printf("Set gatewayip6: %pI6c, prefix_length: %d\n", + &net_gateway6, net_prefix_length); + break; default: debug("Unexpected ICMPv6 type 0x%x\n", icmp->icmp6_type); return -1; diff --git a/net/net.c b/net/net.c index c9a749f6cc8..43abbac7c32 100644 --- a/net/net.c +++ b/net/net.c @@ -24,7 +24,7 @@ * - name of bootfile * Next step: ARP * - * LINK_LOCAL: + * LINKLOCAL: * * Prerequisites: - own ethernet address * We want: - own IP address @@ -93,7 +93,8 @@ #include <net.h> #include <net6.h> #include <ndisc.h> -#include <net/fastboot.h> +#include <net/fastboot_udp.h> +#include <net/fastboot_tcp.h> #include <net/tftp.h> #include <net/ncsi.h> #if defined(CONFIG_CMD_PCAP) @@ -107,6 +108,8 @@ #include <watchdog.h> #include <linux/compiler.h> #include <test/test.h> +#include <net/tcp.h> +#include <net/wget.h> #include "arp.h" #include "bootp.h" #include "cdp.h" @@ -120,8 +123,8 @@ #if defined(CONFIG_CMD_WOL) #include "wol.h" #endif -#include <net/tcp.h> -#include <net/wget.h> +#include "dhcpv6.h" +#include "net_rand.h" /** BOOTP EXTENTIONS **/ @@ -135,6 +138,8 @@ struct in_addr net_dns_server; /* Our 2nd DNS IP address */ struct in_addr net_dns_server2; #endif +/* Indicates whether the pxe path prefix / config file was specified in dhcp option */ +char *pxelinux_configfile; /** END OF BOOTP EXTENTIONS **/ @@ -346,6 +351,8 @@ void net_auto_load(void) static int net_init_loop(void) { + static bool first_call = true; + if (eth_get_dev()) { memcpy(net_ethaddr, eth_get_ethaddr(), 6); @@ -365,6 +372,12 @@ static int net_init_loop(void) */ return -ENONET; + if (IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)) + if (first_call && use_ip6) { + first_call = false; + srand_mac(); /* This is for rand used in ip6_send_rs. */ + net_loop(RS); + } return 0; } @@ -498,9 +511,14 @@ restart: tftp_start_server(); break; #endif -#ifdef CONFIG_UDP_FUNCTION_FASTBOOT - case FASTBOOT: - fastboot_start_server(); +#if defined(CONFIG_UDP_FUNCTION_FASTBOOT) + case FASTBOOT_UDP: + fastboot_udp_start_server(); + break; +#endif +#if defined(CONFIG_TCP_FUNCTION_FASTBOOT) + case FASTBOOT_TCP: + fastboot_tcp_start_server(); break; #endif #if defined(CONFIG_CMD_DHCP) @@ -510,6 +528,10 @@ restart: dhcp_request(); /* Basically same as BOOTP */ break; #endif + case DHCP6: + if (IS_ENABLED(CONFIG_CMD_DHCP6)) + dhcp6_start(); + break; #if defined(CONFIG_CMD_BOOTP) case BOOTP: bootp_reset(); @@ -574,6 +596,10 @@ restart: ncsi_probe_packages(); break; #endif + case RS: + if (IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)) + ip6_send_rs(); + break; default: break; } @@ -671,7 +697,13 @@ restart: x = time_handler; time_handler = (thand_f *)0; (*x)(); - } + } else if (IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)) + if (time_handler && protocol == RS) + if (!ip6_is_unspecified_addr(&net_gateway6) && + net_prefix_length != 0) { + net_set_state(NETLOOP_SUCCESS); + net_set_timeout_handler(0, NULL); + } if (net_state == NETLOOP_FAIL) ret = net_start_again(); @@ -1491,7 +1523,8 @@ common: /* Fall through */ case NETCONS: - case FASTBOOT: + case FASTBOOT_UDP: + case FASTBOOT_TCP: case TFTPSRV: if (IS_ENABLED(CONFIG_IPV6) && use_ip6) { if (!memcmp(&net_link_local_ip6, &net_null_addr_ip6, diff --git a/net/net6.c b/net/net6.c index 75577bcea17..2dd64c0e161 100644 --- a/net/net6.c +++ b/net/net6.c @@ -413,6 +413,7 @@ int net_ip6_handler(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) break; case IPV6_NDISC_NEIGHBOUR_SOLICITATION: case IPV6_NDISC_NEIGHBOUR_ADVERTISEMENT: + case IPV6_NDISC_ROUTER_ADVERTISEMENT: ndisc_receive(et, ip6, len); break; default: diff --git a/net/nfs.c b/net/nfs.c index c6a124885e4..7a8887ef236 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -26,6 +26,10 @@ * NFSv2 is still used by default. But if server does not support NFSv2, then * NFSv3 is used, if available on NFS server. */ +/* NOTE 5: NFSv1 support added by Christian Gmeiner, Thomas Rienoessl, + * September 27, 2018. As of now, NFSv3 is the default choice. If the server + * does not support NFSv3, we fall back to versions 2 or 1. */ + #include <common.h> #include <command.h> #include <display_options.h> @@ -76,10 +80,14 @@ static char *nfs_filename; static char *nfs_path; static char nfs_path_buff[2048]; -#define NFSV2_FLAG 1 -#define NFSV3_FLAG 1 << 1 -static char supported_nfs_versions = NFSV2_FLAG | NFSV3_FLAG; +enum nfs_version { + NFS_UNKOWN = 0, + NFS_V1 = 1, + NFS_V2 = 2, + NFS_V3 = 3, +}; +static enum nfs_version choosen_nfs_version = NFS_V3; static inline int store_block(uchar *src, unsigned offset, unsigned len) { ulong newsize = offset + len; @@ -188,13 +196,41 @@ static void rpc_req(int rpc_prog, int rpc_proc, uint32_t *data, int datalen) rpc_pkt.u.call.prog = htonl(rpc_prog); switch (rpc_prog) { case PROG_NFS: - if (supported_nfs_versions & NFSV2_FLAG) - rpc_pkt.u.call.vers = htonl(2); /* NFS v2 */ - else /* NFSV3_FLAG */ - rpc_pkt.u.call.vers = htonl(3); /* NFS v3 */ + switch (choosen_nfs_version) { + case NFS_V1: + case NFS_V2: + rpc_pkt.u.call.vers = htonl(2); + break; + + case NFS_V3: + rpc_pkt.u.call.vers = htonl(3); + break; + + case NFS_UNKOWN: + /* nothing to do */ + break; + } break; - case PROG_PORTMAP: case PROG_MOUNT: + switch (choosen_nfs_version) { + case NFS_V1: + rpc_pkt.u.call.vers = htonl(1); + break; + + case NFS_V2: + rpc_pkt.u.call.vers = htonl(2); + break; + + case NFS_V3: + rpc_pkt.u.call.vers = htonl(3); + break; + + case NFS_UNKOWN: + /* nothing to do */ + break; + } + break; + case PROG_PORTMAP: default: rpc_pkt.u.call.vers = htonl(2); /* portmapper is version 2 */ } @@ -299,10 +335,10 @@ static void nfs_readlink_req(void) p = &(data[0]); p = rpc_add_credentials(p); - if (supported_nfs_versions & NFSV2_FLAG) { + if (choosen_nfs_version != NFS_V3) { memcpy(p, filefh, NFS_FHSIZE); p += (NFS_FHSIZE / 4); - } else { /* NFSV3_FLAG */ + } else { /* NFS_V3 */ *p++ = htonl(filefh3_length); memcpy(p, filefh, filefh3_length); p += (filefh3_length / 4); @@ -328,7 +364,7 @@ static void nfs_lookup_req(char *fname) p = &(data[0]); p = rpc_add_credentials(p); - if (supported_nfs_versions & NFSV2_FLAG) { + if (choosen_nfs_version != NFS_V3) { memcpy(p, dirfh, NFS_FHSIZE); p += (NFS_FHSIZE / 4); *p++ = htonl(fnamelen); @@ -340,7 +376,7 @@ static void nfs_lookup_req(char *fname) len = (uint32_t *)p - (uint32_t *)&(data[0]); rpc_req(PROG_NFS, NFS_LOOKUP, data, len); - } else { /* NFSV3_FLAG */ + } else { /* NFS_V3 */ *p++ = htonl(NFS_FHSIZE); /* Dir handle length */ memcpy(p, dirfh, NFS_FHSIZE); p += (NFS_FHSIZE / 4); @@ -368,13 +404,13 @@ static void nfs_read_req(int offset, int readlen) p = &(data[0]); p = rpc_add_credentials(p); - if (supported_nfs_versions & NFSV2_FLAG) { + if (choosen_nfs_version != NFS_V3) { memcpy(p, filefh, NFS_FHSIZE); p += (NFS_FHSIZE / 4); *p++ = htonl(offset); *p++ = htonl(readlen); *p++ = 0; - } else { /* NFSV3_FLAG */ + } else { /* NFS_V3 */ *p++ = htonl(filefh3_length); memcpy(p, filefh, filefh3_length); p += (filefh3_length / 4); @@ -398,15 +434,15 @@ static void nfs_send(void) switch (nfs_state) { case STATE_PRCLOOKUP_PROG_MOUNT_REQ: - if (supported_nfs_versions & NFSV2_FLAG) + if (choosen_nfs_version != NFS_V3) rpc_lookup_req(PROG_MOUNT, 1); - else /* NFSV3_FLAG */ + else /* NFS_V3 */ rpc_lookup_req(PROG_MOUNT, 3); break; case STATE_PRCLOOKUP_PROG_NFS_REQ: - if (supported_nfs_versions & NFSV2_FLAG) + if (choosen_nfs_version != NFS_V3) rpc_lookup_req(PROG_NFS, 2); - else /* NFSV3_FLAG */ + else /* NFS_V3 */ rpc_lookup_req(PROG_NFS, 3); break; case STATE_MOUNT_REQ: @@ -431,6 +467,54 @@ static void nfs_send(void) Handlers for the reply from server **************************************************************************/ +static int rpc_handle_error(struct rpc_t *rpc_pkt) +{ + if (rpc_pkt->u.reply.rstatus || + rpc_pkt->u.reply.verifier || + rpc_pkt->u.reply.astatus || + rpc_pkt->u.reply.data[0]) { + switch (ntohl(rpc_pkt->u.reply.astatus)) { + case NFS_RPC_SUCCESS: /* Not an error */ + break; + case NFS_RPC_PROG_MISMATCH: { + /* Remote can't support NFS version */ + const int min = ntohl(rpc_pkt->u.reply.data[0]); + const int max = ntohl(rpc_pkt->u.reply.data[1]); + + if (max < NFS_V1 || max > NFS_V3 || min > NFS_V3) { + puts("*** ERROR: NFS version not supported"); + debug(": Requested: V%d, accepted: min V%d - max V%d\n", + choosen_nfs_version, + ntohl(rpc_pkt->u.reply.data[0]), + ntohl(rpc_pkt->u.reply.data[1])); + puts("\n"); + choosen_nfs_version = NFS_UNKOWN; + break; + } + + debug("*** Warning: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n", + choosen_nfs_version, + ntohl(rpc_pkt->u.reply.data[0]), + ntohl(rpc_pkt->u.reply.data[1])); + debug("Will retry with NFSv%d\n", min); + choosen_nfs_version = min; + return -NFS_RPC_PROG_MISMATCH; + } + case NFS_RPC_PROG_UNAVAIL: + case NFS_RPC_PROC_UNAVAIL: + case NFS_RPC_GARBAGE_ARGS: + case NFS_RPC_SYSTEM_ERR: + default: /* Unknown error on 'accept state' flag */ + debug("*** ERROR: accept state error (%d)\n", + ntohl(rpc_pkt->u.reply.astatus)); + break; + } + return -1; + } + + return 0; +} + static int rpc_lookup_reply(int prog, uchar *pkt, unsigned len) { struct rpc_t rpc_pkt; @@ -464,6 +548,7 @@ static int rpc_lookup_reply(int prog, uchar *pkt, unsigned len) static int nfs_mount_reply(uchar *pkt, unsigned len) { struct rpc_t rpc_pkt; + int ret; debug("%s\n", __func__); @@ -474,11 +559,9 @@ static int nfs_mount_reply(uchar *pkt, unsigned len) else if (ntohl(rpc_pkt.u.reply.id) < rpc_id) return -NFS_RPC_DROP; - if (rpc_pkt.u.reply.rstatus || - rpc_pkt.u.reply.verifier || - rpc_pkt.u.reply.astatus || - rpc_pkt.u.reply.data[0]) - return -1; + ret = rpc_handle_error(&rpc_pkt); + if (ret) + return ret; fs_mounted = 1; /* NFSv2 and NFSv3 use same structure */ @@ -514,6 +597,7 @@ static int nfs_umountall_reply(uchar *pkt, unsigned len) static int nfs_lookup_reply(uchar *pkt, unsigned len) { struct rpc_t rpc_pkt; + int ret; debug("%s\n", __func__); @@ -524,55 +608,15 @@ static int nfs_lookup_reply(uchar *pkt, unsigned len) else if (ntohl(rpc_pkt.u.reply.id) < rpc_id) return -NFS_RPC_DROP; - if (rpc_pkt.u.reply.rstatus || - rpc_pkt.u.reply.verifier || - rpc_pkt.u.reply.astatus || - rpc_pkt.u.reply.data[0]) { - switch (ntohl(rpc_pkt.u.reply.astatus)) { - case NFS_RPC_SUCCESS: /* Not an error */ - break; - case NFS_RPC_PROG_MISMATCH: - /* Remote can't support NFS version */ - switch (ntohl(rpc_pkt.u.reply.data[0])) { - /* Minimal supported NFS version */ - case 3: - debug("*** Warning: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n", - (supported_nfs_versions & NFSV2_FLAG) ? - 2 : 3, - ntohl(rpc_pkt.u.reply.data[0]), - ntohl(rpc_pkt.u.reply.data[1])); - debug("Will retry with NFSv3\n"); - /* Clear NFSV2_FLAG from supported versions */ - supported_nfs_versions &= ~NFSV2_FLAG; - return -NFS_RPC_PROG_MISMATCH; - case 4: - default: - puts("*** ERROR: NFS version not supported"); - debug(": Requested: V%d, accepted: min V%d - max V%d\n", - (supported_nfs_versions & NFSV2_FLAG) ? - 2 : 3, - ntohl(rpc_pkt.u.reply.data[0]), - ntohl(rpc_pkt.u.reply.data[1])); - puts("\n"); - } - break; - case NFS_RPC_PROG_UNAVAIL: - case NFS_RPC_PROC_UNAVAIL: - case NFS_RPC_GARBAGE_ARGS: - case NFS_RPC_SYSTEM_ERR: - default: /* Unknown error on 'accept state' flag */ - debug("*** ERROR: accept state error (%d)\n", - ntohl(rpc_pkt.u.reply.astatus)); - break; - } - return -1; - } + ret = rpc_handle_error(&rpc_pkt); + if (ret) + return ret; - if (supported_nfs_versions & NFSV2_FLAG) { + if (choosen_nfs_version != NFS_V3) { if (((uchar *)&(rpc_pkt.u.reply.data[0]) - (uchar *)(&rpc_pkt) + NFS_FHSIZE) > len) return -NFS_RPC_DROP; memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); - } else { /* NFSV3_FLAG */ + } else { /* NFS_V3 */ filefh3_length = ntohl(rpc_pkt.u.reply.data[1]); if (filefh3_length > NFS3_FHSIZE) filefh3_length = NFS3_FHSIZE; @@ -631,7 +675,7 @@ static int nfs_readlink_reply(uchar *pkt, unsigned len) rpc_pkt.u.reply.data[0]) return -1; - if (!(supported_nfs_versions & NFSV2_FLAG)) { /* NFSV3_FLAG */ + if (choosen_nfs_version == NFS_V3) { nfsv3_data_offset = nfs3_get_attributes_offset(rpc_pkt.u.reply.data); } @@ -692,10 +736,10 @@ static int nfs_read_reply(uchar *pkt, unsigned len) if (!(nfs_offset % ((NFS_READ_SIZE / 2) * 10))) putc('#'); - if (supported_nfs_versions & NFSV2_FLAG) { + if (choosen_nfs_version != NFS_V3) { rlen = ntohl(rpc_pkt.u.reply.data[18]); data_ptr = (uchar *)&(rpc_pkt.u.reply.data[19]); - } else { /* NFSV3_FLAG */ + } else { /* NFS_V3 */ int nfsv3_data_offset = nfs3_get_attributes_offset(rpc_pkt.u.reply.data); @@ -773,6 +817,10 @@ static void nfs_handler(uchar *pkt, unsigned dest, struct in_addr sip, /* just to be sure... */ nfs_state = STATE_UMOUNT_REQ; nfs_send(); + } else if (reply == -NFS_RPC_PROG_MISMATCH && + choosen_nfs_version != NFS_UNKOWN) { + nfs_state = STATE_MOUNT_REQ; + nfs_send(); } else { nfs_state = STATE_LOOKUP_REQ; nfs_send(); @@ -801,7 +849,7 @@ static void nfs_handler(uchar *pkt, unsigned dest, struct in_addr sip, nfs_state = STATE_UMOUNT_REQ; nfs_send(); } else if (reply == -NFS_RPC_PROG_MISMATCH && - supported_nfs_versions != 0) { + choosen_nfs_version != NFS_UNKOWN) { /* umount */ nfs_state = STATE_UMOUNT_REQ; nfs_send(); diff --git a/net/tcp.c b/net/tcp.c index 8d338c72e84..a713e1dd609 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -36,7 +36,6 @@ static u32 rmt_timestamp; static u32 tcp_seq_init; static u32 tcp_ack_edge; -static u32 tcp_seq_max; static int tcp_activity_count; @@ -90,9 +89,10 @@ void tcp_set_tcp_state(enum tcp_state new_state) current_tcp_state = new_state; } -static void dummy_handler(uchar *pkt, unsigned int dport, - struct in_addr sip, unsigned int sport, - unsigned int len) +static void dummy_handler(uchar *pkt, u16 dport, + struct in_addr sip, u16 sport, + u32 tcp_seq_num, u32 tcp_ack_num, + u8 action, unsigned int len) { } @@ -256,7 +256,7 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, switch (action) { case TCP_SYN: debug_cond(DEBUG_DEV_PKT, - "TCP Hdr:SYN (%pI4, %pI4, sq=%d, ak=%d)\n", + "TCP Hdr:SYN (%pI4, %pI4, sq=%u, ak=%u)\n", &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); tcp_activity_count = 0; @@ -271,41 +271,46 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, current_tcp_state = TCP_SYN_SENT; } break; + case TCP_SYN | TCP_ACK: case TCP_ACK: pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(b); b->ip.hdr.tcp_flags = action; debug_cond(DEBUG_DEV_PKT, - "TCP Hdr:ACK (%pI4, %pI4, s=%d, a=%d, A=%x)\n", + "TCP Hdr:ACK (%pI4, %pI4, s=%u, a=%u, A=%x)\n", &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num, action); break; case TCP_FIN: debug_cond(DEBUG_DEV_PKT, - "TCP Hdr:FIN (%pI4, %pI4, s=%d, a=%d)\n", + "TCP Hdr:FIN (%pI4, %pI4, s=%u, a=%u)\n", &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); payload_len = 0; pkt_hdr_len = IP_TCP_HDR_SIZE; current_tcp_state = TCP_FIN_WAIT_1; break; - + case TCP_RST | TCP_ACK: + case TCP_RST: + debug_cond(DEBUG_DEV_PKT, + "TCP Hdr:RST (%pI4, %pI4, s=%u, a=%u)\n", + &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); + current_tcp_state = TCP_CLOSED; + break; /* Notify connection closing */ - case (TCP_FIN | TCP_ACK): case (TCP_FIN | TCP_ACK | TCP_PUSH): if (current_tcp_state == TCP_CLOSE_WAIT) current_tcp_state = TCP_CLOSING; - tcp_ack_edge++; debug_cond(DEBUG_DEV_PKT, - "TCP Hdr:FIN ACK PSH(%pI4, %pI4, s=%d, a=%d, A=%x)\n", + "TCP Hdr:FIN ACK PSH(%pI4, %pI4, s=%u, a=%u, A=%x)\n", &net_server_ip, &net_ip, - tcp_seq_num, tcp_ack_edge, action); + tcp_seq_num, tcp_ack_num, action); fallthrough; default: pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(b); b->ip.hdr.tcp_flags = action | TCP_PUSH | TCP_ACK; debug_cond(DEBUG_DEV_PKT, - "TCP Hdr:dft (%pI4, %pI4, s=%d, a=%d, A=%x)\n", + "TCP Hdr:dft (%pI4, %pI4, s=%u, a=%u, A=%x)\n", &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num, action); } @@ -313,12 +318,12 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, pkt_len = pkt_hdr_len + payload_len; tcp_len = pkt_len - IP_HDR_SIZE; + tcp_ack_edge = tcp_ack_num; /* TCP Header */ b->ip.hdr.tcp_ack = htonl(tcp_ack_edge); b->ip.hdr.tcp_src = htons(sport); b->ip.hdr.tcp_dst = htons(dport); b->ip.hdr.tcp_seq = htonl(tcp_seq_num); - tcp_seq_num = tcp_seq_num + payload_len; /* * TCP window size - TCP header variable tcp_win. @@ -353,9 +358,8 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, * tcp_hole() - Selective Acknowledgment (Essential for fast stream transfer) * @tcp_seq_num: TCP sequence start number * @len: the length of sequence numbers - * @tcp_seq_max: maximum of sequence numbers */ -void tcp_hole(u32 tcp_seq_num, u32 len, u32 tcp_seq_max) +void tcp_hole(u32 tcp_seq_num, u32 len) { u32 idx_sack, sack_in; u32 sack_end = TCP_SACK - 1; @@ -496,7 +500,7 @@ void tcp_parse_options(uchar *o, int o_len) } } -static u8 tcp_state_machine(u8 tcp_flags, u32 *tcp_seq_num, int payload_len) +static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) { u8 tcp_fin = tcp_flags & TCP_FIN; u8 tcp_syn = tcp_flags & TCP_SYN; @@ -527,46 +531,44 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 *tcp_seq_num, int payload_len) switch (current_tcp_state) { case TCP_CLOSED: debug_cond(DEBUG_INT_STATE, "TCP CLOSED %x\n", tcp_flags); - if (tcp_ack) - action = TCP_DATA; - else if (tcp_syn) - action = TCP_RST; - else if (tcp_fin) + if (tcp_syn) { + action = TCP_SYN | TCP_ACK; + tcp_seq_init = tcp_seq_num; + tcp_ack_edge = tcp_seq_num + 1; + current_tcp_state = TCP_SYN_RECEIVED; + } else if (tcp_ack || tcp_fin) { action = TCP_DATA; + } break; + case TCP_SYN_RECEIVED: case TCP_SYN_SENT: - debug_cond(DEBUG_INT_STATE, "TCP_SYN_SENT %x, %d\n", - tcp_flags, *tcp_seq_num); + debug_cond(DEBUG_INT_STATE, "TCP_SYN_SENT | TCP_SYN_RECEIVED %x, %u\n", + tcp_flags, tcp_seq_num); if (tcp_fin) { action = action | TCP_PUSH; current_tcp_state = TCP_CLOSE_WAIT; - } - if (tcp_syn) { - action = action | TCP_ACK | TCP_PUSH; - if (tcp_ack) { - tcp_seq_init = *tcp_seq_num; - *tcp_seq_num = *tcp_seq_num + 1; - tcp_seq_max = *tcp_seq_num; - tcp_ack_edge = *tcp_seq_num; - sack_idx = 0; - edge_a[sack_idx].se.l = *tcp_seq_num; - edge_a[sack_idx].se.r = *tcp_seq_num; - prev_len = 0; - current_tcp_state = TCP_ESTABLISHED; - for (i = 0; i < TCP_SACK; i++) - edge_a[i].st = NOPKT; - } - } else if (tcp_ack) { + } else if (tcp_ack || (tcp_syn && tcp_ack)) { + action |= TCP_ACK; + tcp_seq_init = tcp_seq_num; + tcp_ack_edge = tcp_seq_num + 1; + sack_idx = 0; + edge_a[sack_idx].se.l = tcp_ack_edge; + edge_a[sack_idx].se.r = tcp_ack_edge; + prev_len = 0; + current_tcp_state = TCP_ESTABLISHED; + for (i = 0; i < TCP_SACK; i++) + edge_a[i].st = NOPKT; + + if (tcp_syn && tcp_ack) + action |= TCP_PUSH; + } else { action = TCP_DATA; } - break; case TCP_ESTABLISHED: debug_cond(DEBUG_INT_STATE, "TCP_ESTABLISHED %x\n", tcp_flags); - if (*tcp_seq_num > tcp_seq_max) - tcp_seq_max = *tcp_seq_num; if (payload_len > 0) { - tcp_hole(*tcp_seq_num, payload_len, tcp_seq_max); + tcp_hole(tcp_seq_num, payload_len); tcp_fin = TCP_DATA; /* cause standalone FIN */ } @@ -603,15 +605,14 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 *tcp_seq_num, int payload_len) case TCP_FIN_WAIT_1: debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_1 (%x)\n", tcp_flags); if (tcp_fin) { + tcp_ack_edge++; action = TCP_ACK | TCP_FIN; current_tcp_state = TCP_FIN_WAIT_2; } if (tcp_syn) action = TCP_RST; - if (tcp_ack) { + if (tcp_ack) current_tcp_state = TCP_CLOSED; - tcp_seq_num = tcp_seq_num + 1; - } break; case TCP_CLOSING: debug_cond(DEBUG_INT_STATE, "TCP_CLOSING (%x)\n", tcp_flags); @@ -640,7 +641,6 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) u16 tcp_rx_xsum = b->ip.hdr.ip_sum; u8 tcp_action = TCP_DATA; u32 tcp_seq_num, tcp_ack_num; - struct in_addr action_and_state; int tcp_hdr_len, payload_len; /* Verify IP header */ @@ -685,7 +685,7 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) /* Packets are not ordered. Send to app as received. */ tcp_action = tcp_state_machine(b->ip.hdr.tcp_flags, - &tcp_seq_num, payload_len); + tcp_seq_num, payload_len); tcp_activity_count++; if (tcp_activity_count > TCP_ACTIVITY) { @@ -695,18 +695,17 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) if ((tcp_action & TCP_PUSH) || payload_len > 0) { debug_cond(DEBUG_DEV_PKT, - "TCP Notify (action=%x, Seq=%d,Ack=%d,Pay%d)\n", + "TCP Notify (action=%x, Seq=%u,Ack=%u,Pay%d)\n", tcp_action, tcp_seq_num, tcp_ack_num, payload_len); - action_and_state.s_addr = tcp_action; - (*tcp_packet_handler) ((uchar *)b + pkt_len - payload_len, - tcp_seq_num, action_and_state, - tcp_ack_num, payload_len); + (*tcp_packet_handler) ((uchar *)b + pkt_len - payload_len, b->ip.hdr.tcp_dst, + b->ip.hdr.ip_src, b->ip.hdr.tcp_src, tcp_seq_num, + tcp_ack_num, tcp_action, payload_len); } else if (tcp_action != TCP_DATA) { debug_cond(DEBUG_DEV_PKT, - "TCP Action (action=%x,Seq=%d,Ack=%d,Pay=%d)\n", - tcp_action, tcp_seq_num, tcp_ack_num, payload_len); + "TCP Action (action=%x,Seq=%u,Ack=%u,Pay=%d)\n", + tcp_action, tcp_ack_num, tcp_ack_edge, payload_len); /* * Warning: Incoming Ack & Seq sequence numbers are transposed @@ -715,6 +714,6 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) net_send_tcp_packet(0, ntohs(b->ip.hdr.tcp_src), ntohs(b->ip.hdr.tcp_dst), (tcp_action & (~TCP_PUSH)), - tcp_seq_num, tcp_ack_num); + tcp_ack_num, tcp_ack_edge); } } diff --git a/net/wget.c b/net/wget.c index eebdf80eb54..2dbfeb1a1d5 100644 --- a/net/wget.c +++ b/net/wget.c @@ -88,8 +88,8 @@ static void wget_send_stored(void) { u8 action = retry_action; int len = retry_len; - unsigned int tcp_ack_num = retry_tcp_ack_num + len; - unsigned int tcp_seq_num = retry_tcp_seq_num; + unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len); + unsigned int tcp_seq_num = retry_tcp_ack_num; uchar *ptr, *offset; switch (current_wget_state) { @@ -130,8 +130,8 @@ static void wget_send_stored(void) } } -static void wget_send(u8 action, unsigned int tcp_ack_num, - unsigned int tcp_seq_num, int len) +static void wget_send(u8 action, unsigned int tcp_seq_num, + unsigned int tcp_ack_num, int len) { retry_action = action; retry_tcp_ack_num = tcp_ack_num; @@ -178,10 +178,8 @@ static void wget_timeout_handler(void) #define PKT_QUEUE_PACKET_SIZE 0x800 static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, - struct in_addr action_and_state, - unsigned int tcp_ack_num, unsigned int len) + u8 action, unsigned int tcp_ack_num, unsigned int len) { - u8 action = action_and_state.s_addr; uchar *pkt_in_q; char *pos; int hlen, i; @@ -268,22 +266,25 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, } /** - * wget_handler() - handler of wget - * @pkt: the pointer to the payload - * @tcp_seq_num: tcp sequence number - * @action_and_state: TCP state - * @tcp_ack_num: tcp acknowledge number - * @len: length of the payload + * wget_handler() - TCP handler of wget + * @pkt: pointer to the application packet + * @dport: destination TCP port + * @sip: source IP address + * @sport: source TCP port + * @tcp_seq_num: TCP sequential number + * @tcp_ack_num: TCP acknowledgment number + * @action: TCP action (SYN, ACK, FIN, etc) + * @len: packet length * * In the "application push" invocation, the TCP header with all * its information is pointed to by the packet pointer. */ -static void wget_handler(uchar *pkt, unsigned int tcp_seq_num, - struct in_addr action_and_state, - unsigned int tcp_ack_num, unsigned int len) +static void wget_handler(uchar *pkt, u16 dport, + struct in_addr sip, u16 sport, + u32 tcp_seq_num, u32 tcp_ack_num, + u8 action, unsigned int len) { enum tcp_state wget_tcp_state = tcp_get_tcp_state(); - u8 action = action_and_state.s_addr; net_set_timeout_handler(wget_timeout, wget_timeout_handler); packets++; @@ -294,7 +295,7 @@ static void wget_handler(uchar *pkt, unsigned int tcp_seq_num, break; case WGET_CONNECTING: debug_cond(DEBUG_WGET, - "wget: Connecting In len=%x, Seq=%x, Ack=%x\n", + "wget: Connecting In len=%x, Seq=%u, Ack=%u\n", len, tcp_seq_num, tcp_ack_num); if (!len) { if (wget_tcp_state == TCP_ESTABLISHED) { @@ -310,14 +311,13 @@ static void wget_handler(uchar *pkt, unsigned int tcp_seq_num, } break; case WGET_CONNECTED: - debug_cond(DEBUG_WGET, "wget: Connected seq=%x, len=%x\n", + debug_cond(DEBUG_WGET, "wget: Connected seq=%u, len=%x\n", tcp_seq_num, len); if (!len) { wget_fail("Image not found, no data returned\n", tcp_seq_num, tcp_ack_num, action); } else { - wget_connected(pkt, tcp_seq_num, action_and_state, - tcp_ack_num, len); + wget_connected(pkt, tcp_seq_num, action, tcp_ack_num, len); } break; case WGET_TRANSFERRING: @@ -338,6 +338,7 @@ static void wget_handler(uchar *pkt, unsigned int tcp_seq_num, wget_send(TCP_ACK, tcp_seq_num, tcp_ack_num, len); fallthrough; case TCP_SYN_SENT: + case TCP_SYN_RECEIVED: case TCP_CLOSING: case TCP_FIN_WAIT_1: case TCP_CLOSED: diff --git a/test/dm/Makefile b/test/dm/Makefile index c8534b5cfa8..3799b1ae8fd 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_DM_DSA) += dsa.o obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o obj-$(CONFIG_DM_ETH) += eth.o +obj-$(CONFIG_EXTCON) += extcon.o ifneq ($(CONFIG_EFI_PARTITION),) obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o endif diff --git a/test/dm/eth.c b/test/dm/eth.c index ebf01d8cf38..d05d2a9abe1 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -20,6 +20,7 @@ #include <dm/uclass-internal.h> #include <test/test.h> #include <test/ut.h> +#include <ndisc.h> #define DM_TEST_ETH_NUM 4 @@ -607,3 +608,90 @@ static int dm_test_eth_async_ping_reply(struct unit_test_state *uts) } DM_TEST(dm_test_eth_async_ping_reply, UT_TESTF_SCAN_FDT); + +#if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY) + +static u8 ip6_ra_buf[] = {0x60, 0xf, 0xc5, 0x4a, 0x0, 0x38, 0x3a, 0xff, 0xfe, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x85, 0xe6, + 0x29, 0x77, 0xcb, 0xc8, 0x53, 0xff, 0x2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x86, 0x0, 0xdc, 0x90, 0x40, 0x80, 0x15, 0x18, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x4, + 0x40, 0xc0, 0x0, 0x0, 0x37, 0xdc, 0x0, 0x0, 0x37, + 0x78, 0x0, 0x0, 0x0, 0x0, 0x20, 0x1, 0xca, 0xfe, 0xca, + 0xfe, 0xca, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0x1, 0x0, 0x15, 0x5d, 0xe2, 0x8a, 0x2}; + +static int dm_test_validate_ra(struct unit_test_state *uts) +{ + struct ip6_hdr *ip6 = (struct ip6_hdr *)ip6_ra_buf; + struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1); + __be16 temp = 0; + + ut_assert(validate_ra(ip6) == true); + + temp = ip6->payload_len; + ip6->payload_len = 15; + ut_assert(validate_ra(ip6) == false); + ip6->payload_len = temp; + + temp = ip6->saddr.s6_addr16[0]; + ip6->saddr.s6_addr16[0] = 0x2001; + ut_assert(validate_ra(ip6) == false); + ip6->saddr.s6_addr16[0] = temp; + + temp = ip6->hop_limit; + ip6->hop_limit = 15; + ut_assert(validate_ra(ip6) == false); + ip6->hop_limit = temp; + + temp = icmp->icmp6_code; + icmp->icmp6_code = 15; + ut_assert(validate_ra(ip6) == false); + icmp->icmp6_code = temp; + + return 0; +} + +DM_TEST(dm_test_validate_ra, 0); + +static int dm_test_process_ra(struct unit_test_state *uts) +{ + int len = sizeof(ip6_ra_buf); + struct ip6_hdr *ip6 = (struct ip6_hdr *)ip6_ra_buf; + struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1); + struct ra_msg *msg = (struct ra_msg *)icmp; + unsigned char *option = msg->opt; + struct icmp6_ra_prefix_info *prefix = + (struct icmp6_ra_prefix_info *)option; + __be16 temp = 0; + unsigned char option_len = option[1]; + + ut_assert(process_ra(ip6, len) == 0); + + temp = icmp->icmp6_rt_lifetime; + icmp->icmp6_rt_lifetime = 0; + ut_assert(process_ra(ip6, len) != 0); + icmp->icmp6_rt_lifetime = temp; + + ut_assert(process_ra(ip6, 0) != 0); + + option[1] = 0; + ut_assert(process_ra(ip6, len) != 0); + option[1] = option_len; + + prefix->on_link = false; + ut_assert(process_ra(ip6, len) != 0); + prefix->on_link = true; + + temp = prefix->prefix.s6_addr16[0]; + prefix->prefix.s6_addr16[0] = 0x80fe; + ut_assert(process_ra(ip6, len) != 0); + prefix->prefix.s6_addr16[0] = temp; + + return 0; +} + +DM_TEST(dm_test_process_ra, 0); + +#endif diff --git a/test/dm/extcon.c b/test/dm/extcon.c new file mode 100644 index 00000000000..6a4e22bfdc5 --- /dev/null +++ b/test/dm/extcon.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/test.h> +#include <extcon.h> +#include <test/test.h> +#include <test/ut.h> + +static int dm_test_extcon(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device_by_name(UCLASS_EXTCON, "extcon", &dev)); + + return 0; +} + +DM_TEST(dm_test_extcon, UT_TESTF_SCAN_FDT); diff --git a/test/py/tests/test_efi_bootmgr/conftest.py b/test/py/tests/test_efi_bootmgr/conftest.py index a0a754afbe1..eabafa54298 100644 --- a/test/py/tests/test_efi_bootmgr/conftest.py +++ b/test/py/tests/test_efi_bootmgr/conftest.py @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -"""Fixture for UEFI bootmanager test -""" +"""Fixture for UEFI bootmanager test.""" import os import shutil @@ -10,8 +9,7 @@ import pytest @pytest.fixture(scope='session') def efi_bootmgr_data(u_boot_config): - """Set up a file system to be used in UEFI bootmanager - tests + """Set up a file system to be used in UEFI bootmanager tests. Args: u_boot_config -- U-boot configuration. diff --git a/test/py/tests/test_efi_capsule/capsule_defs.py b/test/py/tests/test_efi_capsule/capsule_defs.py index 59b40f11bd1..3cc695e29b5 100644 --- a/test/py/tests/test_efi_capsule/capsule_defs.py +++ b/test/py/tests/test_efi_capsule/capsule_defs.py @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ +"""Directoreis used for authentication and capsule tests.""" + # Directories CAPSULE_DATA_DIR = '/EFI/CapsuleTestData' CAPSULE_INSTALL_DIR = '/EFI/UpdateCapsule' diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index 0e5137de60d..a337e629362 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -2,8 +2,7 @@ # Copyright (c) 2020, Linaro Limited # Author: AKASHI Takahiro <takahiro.akashi@linaro.org> -"""Fixture for UEFI capsule test -""" +"""Fixture for UEFI capsule test.""" from subprocess import call, check_call, CalledProcessError import pytest @@ -11,13 +10,15 @@ from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR, EFITOOLS_PATH @pytest.fixture(scope='session') def efi_capsule_data(request, u_boot_config): - """Set up a file system to be used in UEFI capsule and authentication test - and return a ath to disk image to be used for testing + """Set up a file system and return path to image. + + The function sets up a file system to be used in UEFI capsule and + authentication test and returns a path to disk image to be used + for testing. request -- Pytest request object. u_boot_config -- U-boot configuration. """ - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' data_dir = mnt_point + CAPSULE_DATA_DIR install_dir = mnt_point + CAPSULE_INSTALL_DIR diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py index 65cde7a2f23..30ff7029438 100644 --- a/test/py/tests/test_efi_secboot/conftest.py +++ b/test/py/tests/test_efi_secboot/conftest.py @@ -2,7 +2,7 @@ # Copyright (c) 2019, Linaro Limited # Author: AKASHI Takahiro <takahiro.akashi@linaro.org> -""" Fixture for UEFI secure boot test """ +"""Fixture for UEFI secure boot test.""" from subprocess import call, check_call, CalledProcessError import pytest @@ -132,7 +132,9 @@ def efi_boot_env(request, u_boot_config): @pytest.fixture(scope='session') def efi_boot_env_intca(request, u_boot_config): - """Set up a file system to be used in UEFI secure boot test + """Set up file system for secure boot test. + + Set up a file system to be used in UEFI secure boot test of intermediate certificates. Args: diff --git a/test/py/tests/test_efi_secboot/defs.py b/test/py/tests/test_efi_secboot/defs.py index b7a2a118511..6a2317e295b 100644 --- a/test/py/tests/test_efi_secboot/defs.py +++ b/test/py/tests/test_efi_secboot/defs.py @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ +"""Constants used for secure boot test.""" + # Owner guid GUID = '11111111-2222-3333-4444-123456789abc' diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py index e92d63cde6e..43f24245582 100644 --- a/test/py/tests/test_efi_selftest.py +++ b/test/py/tests/test_efi_selftest.py @@ -7,7 +7,7 @@ import pytest @pytest.mark.buildconfigspec('cmd_bootefi_selftest') -def test_efi_selftest(u_boot_console): +def test_efi_selftest_base(u_boot_console): """Run UEFI unit tests u_boot_console -- U-Boot console diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py index 37c1608bb22..3b4b6fcaf40 100644 --- a/test/py/tests/test_hush_if_test.py +++ b/test/py/tests/test_hush_if_test.py @@ -182,3 +182,16 @@ def test_hush_if_test_host_file_exists(u_boot_console): expr = 'test -e hostfs - ' + test_file exec_hush_if(u_boot_console, expr, False) + +def test_hush_var(u_boot_console): + """Test the set and unset of variables""" + u_boot_console.run_command('ut_var_nonexistent=') + u_boot_console.run_command('ut_var_exists=1') + u_boot_console.run_command('ut_var_unset=1') + exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True) + exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False) + exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', False) + exec_hush_if(u_boot_console, 'ut_var_unset=', True) + exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', True) + u_boot_console.run_command('ut_var_exists=') + u_boot_console.run_command('ut_var_unset=') diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index 9ca6743afd9..cd4b4dc53cb 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -9,7 +9,7 @@ import u_boot_utils """ Note: This test relies on boardenv_* containing configuration values to define -which the network environment available for testing. Without this, this test +which network environment is available for testing. Without this, this test will be automatically skipped. For example: @@ -29,6 +29,11 @@ env__net_uses_pci = True # set to False. env__net_dhcp_server = True +# True if a DHCPv6 server is attached to the network, and should be tested. +# If DHCPv6 testing is not possible or desired, this variable may be omitted or +# set to False. +env__net_dhcp6_server = True + # A list of environment variables that should be set in order to configure a # static IP. If solely relying on DHCP, this variable may be omitted or set to # an empty list. @@ -55,9 +60,15 @@ env__net_nfs_readable_file = { 'size': 5058624, 'crc32': 'c2244b26', } + +# True if a router advertisement service is connected to the network, and should +# be tested. If router advertisement testing is not possible or desired, this +variable may be omitted or set to False. +env__router_on_net = True """ net_set_up = False +net6_set_up = False def test_net_pre_commands(u_boot_console): """Execute any commands required to enable network hardware. @@ -93,6 +104,25 @@ def test_net_dhcp(u_boot_console): global net_set_up net_set_up = True +@pytest.mark.buildconfigspec('cmd_dhcp6') +def test_net_dhcp6(u_boot_console): + """Test the dhcp6 command. + + The boardenv_* file may be used to enable/disable this test; see the + comment at the beginning of this file. + """ + + test_dhcp6 = u_boot_console.config.env.get('env__net_dhcp6_server', False) + if not test_dhcp6: + pytest.skip('No DHCP6 server available') + + u_boot_console.run_command('setenv autoload no') + output = u_boot_console.run_command('dhcp6') + assert 'DHCP6 client bound to ' in output + + global net6_set_up + net6_set_up = True + @pytest.mark.buildconfigspec('net') def test_net_setup_static(u_boot_console): """Set up a static IP configuration. @@ -126,6 +156,30 @@ def test_net_ping(u_boot_console): output = u_boot_console.run_command('ping $serverip') assert 'is alive' in output +@pytest.mark.buildconfigspec('IPV6_ROUTER_DISCOVERY') +def test_net_network_discovery(u_boot_console): + """Test the network discovery feature of IPv6. + + An IPv6 network command (ping6 in this case) is run to make U-Boot send a + router solicitation packet, receive a router advertisement message, and + parse it. + A router advertisement service needs to be running for this test to succeed. + U-Boot receives the RA, processes it, and if successful, assigns the gateway + IP and prefix length. + The configuration is provided by the boardenv_* file; see the comment at + the beginning of this file. + """ + + router_on_net = u_boot_console.config.env.get('env__router_on_net', False) + if not router_on_net: + pytest.skip('No router on network') + + fake_host_ip = 'fe80::215:5dff:fef6:2ec6' + output = u_boot_console.run_command('ping6 ' + fake_host_ip) + assert 'ROUTER SOLICITATION 1' in output + assert 'Set gatewayip6:' in output + assert '0000:0000:0000:0000:0000:0000:0000:0000' not in output + @pytest.mark.buildconfigspec('cmd_net') def test_net_tftpboot(u_boot_console): """Test the tftpboot command. diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 879ff138ad7..635865c21c8 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -253,6 +253,7 @@ class BuilderThread(threading.Thread): args.extend(['-j', str(self.builder.num_jobs)]) if self.builder.warnings_as_errors: args.append('KCFLAGS=-Werror') + args.append('HOSTCFLAGS=-Werror') if self.builder.allow_missing: args.append('BINMAN_ALLOW_MISSING=1') if self.builder.no_lto: diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index 32fa69cbb01..4fe8d12c403 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -784,8 +784,8 @@ class TestFdtUtil(unittest.TestCase): def test_ensure_compiled_tmpdir(self): """Test providing a temporary directory""" + old_outdir = tools.outdir try: - old_outdir = tools.outdir tools.outdir= None tmpdir = tempfile.mkdtemp(prefix='test_fdt.') dtb = fdt_util.EnsureCompiled(find_dtb_file('dtoc_test_simple.dts'), @@ -793,7 +793,7 @@ class TestFdtUtil(unittest.TestCase): self.assertEqual(tmpdir, os.path.dirname(dtb)) shutil.rmtree(tmpdir) finally: - tools.outdir= old_outdir + tools.outdir = old_outdir def test_get_phandle_name_offset(self): val = fdt_util.GetPhandleNameOffset(self.node, 'missing') |