diff options
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 3 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_agilex.c | 14 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 2 |
3 files changed, 17 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 8e12aeec011..0871cf949e5 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -148,11 +148,14 @@ void populate_sysmgr_pinmux(void); * Bit[30] reserved for FSBL to update the DDR init progress * 1 - means in progress, 0 - haven't started / DDR is up running. * + * Bit[18] reserved for SDM to configure ACF * Bit[17:1] - Setting by Linux EDAC. * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) */ #define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) #define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18 #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index e4655877a78..b36a765a5de 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -73,12 +73,22 @@ int sdram_mmr_init_full(struct udevice *dev) */ /* Configure DDR IO size x16, x32 and x64 mode */ u32 update_value; + u32 reg; update_value = hmc_readl(plat, NIOSRESERVED0); update_value = (update_value & 0xFF) >> 5; - /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */ - update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); + /* Read ACF from boot_scratch_cold_8 register bit[18]*/ + reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + reg = ((reg & SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK) + >> SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT); + + /* bit-2 of DDRIOCTRL: Configure DDR data rate 0-Half-rate 1-Quarter-rate */ + clrsetbits_le32(&update_value, + DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK, + reg << DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_SHIFT); + hmc_ecc_writel(plat, update_value, DDRIOCTRL); /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */ diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 183b1a33080..4c1205b63b6 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -48,6 +48,8 @@ struct altera_sdram_plat { #define RSTHANDSHAKESTAT 0x218 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK BIT(2) +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_SHIFT 2 #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) |