diff options
| -rw-r--r-- | arch/arm/Kconfig | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 11 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/board.c | 9 |
5 files changed, 20 insertions, 14 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb0f5bcfe54..9a62b557869 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -452,9 +452,6 @@ config ENABLE_ARM_SOC_BOOT0_HOOK values, then choose this option, and create a file included as <asm/arch/boot0.h> which contains the required assembler code. -config ARM_CORTEX_CPU_IS_UP - bool - config USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy" default y if !ARM64 diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 60bb0a9e1ec..2eeef3cba96 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -76,4 +76,9 @@ config ARMV7_LPAE Say Y here to use the long descriptor page table format. This is required if U-Boot runs in HYP mode. +config SPL_ARMV7_SET_CORTEX_SMPEN + bool + help + Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup. + endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 698e15b8e18..af87a5432ae 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -173,6 +173,17 @@ ENDPROC(switch_to_hypervisor) * *************************************************************************/ ENTRY(cpu_init_cp15) + +#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) + /* + * The Arm Cortex-A7 TRM says this bit must be enabled before + * "any cache or TLB maintenance operations are performed". + */ + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #1 << 6 @ set SMP bit to enable coherency + mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register +#endif + /* * Invalidate L1 I/D */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d7f9a03152f..6e1f346ca52 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -186,7 +186,6 @@ choice config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A - select ARM_CORTEX_CPU_IS_UP select PHY_SUN4I_USB select DRAM_SUN4I select SUNXI_GEN_SUN4I @@ -197,7 +196,6 @@ config MACH_SUN4I config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7A - select ARM_CORTEX_CPU_IS_UP select DRAM_SUN4I select PHY_SUN4I_USB select SUNXI_GEN_SUN4I @@ -212,6 +210,7 @@ config MACH_SUN6I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN6I select PHY_SUN4I_USB select SPL_I2C @@ -227,6 +226,7 @@ config MACH_SUN7I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN4I select PHY_SUN4I_USB select SUNXI_GEN_SUN4I @@ -315,6 +315,7 @@ config MACH_SUN8I_V3S config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7A + select SPL_ARMV7_SET_CORTEX_SMPEN select DRAM_SUN9I select SPL_I2C select SUN6I_PRCM @@ -365,6 +366,7 @@ endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool + select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64 select SUN6I_PRCM default y if MACH_SUN8I_A23 default y if MACH_SUN8I_A33 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c932a293317..261af9d7bf4 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -218,15 +218,6 @@ void s_init(void) /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ #endif - -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n" - ::: "r0"); -#endif } #define SUNXI_INVALID_BOOT_SOURCE -1 |