diff options
| -rw-r--r-- | arch/arm/dts/rk3588-u-boot.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/dts/rk3588s-u-boot.dtsi | 45 |
2 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi new file mode 100644 index 00000000000..4c8ac804d61 --- /dev/null +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rockchip-u-boot.dtsi" +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi new file mode 100644 index 00000000000..326508d224c --- /dev/null +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rockchip-u-boot.dtsi" + +/ { + dmc { + compatible = "rockchip,rk3588-dmc"; + bootph-all; + status = "okay"; + }; + + pmu1_grf: syscon@fd58a000 { + bootph-all; + compatible = "rockchip,rk3588-pmu1-grf", "syscon"; + reg = <0x0 0xfd58a000 0x0 0x2000>; + }; +}; + +&xin24m { + bootph-all; + status = "okay"; +}; + +&cru { + bootph-pre-ram; + status = "okay"; +}; + +&sys_grf { + bootph-pre-ram; + status = "okay"; +}; + +&uart2 { + clock-frequency = <24000000>; + bootph-pre-ram; + status = "okay"; +}; + +&ioc { + bootph-pre-ram; +}; |