diff options
172 files changed, 9386 insertions, 9937 deletions
diff --git a/.gitignore b/.gitignore index 272257a77bb..bb03833b5f2 100644 --- a/.gitignore +++ b/.gitignore @@ -75,6 +75,7 @@ fit-dtb.blob* /keep-syms-lto.* /*imx8mimage* /*imx8mcst* +/*rcar4-sa0* /drivers/video/u_boot_logo.S /test/overlay/test-fdt-overlay.dtbo.S /test/overlay/test-fdt-overlay-stacked.dtbo.S @@ -27,8 +27,22 @@ config DEPRECATED code that relies on deprecated features that will be removed and the conversion deadline has passed. +config COMPILE_TEST + bool "Compile also drivers which will not load" + help + Some drivers can be compiled on a different platform than they are + intended to be run on. Despite they cannot be loaded there (or even + when they load they cannot be used due to missing HW support), + developers still, opposing to distributors, might want to build such + drivers to compile-test them. + + If you are a developer and want to build everything available, say Y + here. If you are a user/distributor, say N here to exclude useless + drivers to be distributed. + config WERROR bool "Compile U-Boot with warnings as errors" + default COMPILE_TEST help A U-Boot build should not cause any compiler warnings, and this enables the '-Werror' flag to enforce that rule. @@ -523,6 +537,7 @@ config BUILD_TARGET config HAS_BOARD_SIZE_LIMIT bool "Define a maximum size for the U-Boot image" + depends on !COMPILE_TEST default y if RCAR_32 || RCAR_64 help In some cases, we need to enforce a hard limit on how big the U-Boot @@ -541,6 +556,7 @@ config BOARD_SIZE_LIMIT config SYS_CUSTOM_LDSCRIPT bool "Use a custom location for the U-Boot linker script" + depends on !COMPILE_TEST help Normally when linking U-Boot we will look in the board directory, the CPU directory and finally the "cpu" directory of the architecture @@ -635,8 +635,9 @@ ifeq ($(config-targets),1) # Read arch specific Makefile to set KBUILD_DEFCONFIG as needed. # KBUILD_DEFCONFIG may point out an alternative default configuration # used for 'make defconfig' -# Modified for U-Boot --include arch/$(SRCARCH)/Makefile +# Modified for U-Boot: we don't include arch/$(SRCARCH)/Makefile for config +# targets, which is useless since U-Boot has no architecture defining its own +# KBUILD_{DEF,K}CONFIG, or CROSS_COMPILE. export KBUILD_DEFCONFIG KBUILD_KCONFIG CC_VERSION_TEXT config: scripts_basic outputmakefile FORCE @@ -724,8 +725,10 @@ endif ARCH_CPPFLAGS := ARCH_AFLAGS := ARCH_CFLAGS := -# Modified for U-Boot --include arch/$(SRCARCH)/Makefile +# Modified for U-Boot: we put off the include of arch/$(SRCARCH)/Makefile until +# making sure include/config/auto.conf is up-to-date and include of config.mk, +# because the architecture-specific Makefile may make use of variables defined +# in config.mk. See also the comment about autoconf_is_old. ifeq ($(dot-config),1) ifeq ($(may-sync-config),1) @@ -2529,7 +2532,7 @@ distclean: mrproper -o -name '.*.rej' -o -name '*%' -o -name 'core' \ -o -name '*.pyc' \) \ -type f -print | xargs rm -f - @rm -f boards.cfg CHANGELOG + @rm -f boards.cfg CHANGELOG .binman_stamp # See doc/develop/python_cq.rst PHONY += pylint pylint_err @@ -379,15 +379,6 @@ The following options need to be configured: CONFIG_SH_ETHER Support for Renesas on-chip Ethernet controller - CFG_SH_ETHER_USE_PORT - Define the number of ports to be used - - CFG_SH_ETHER_PHY_ADDR - Define the ETH PHY's address - - CFG_SH_ETHER_CACHE_WRITEBACK - If this option is set, the driver enables cache flush. - - TPM Support: CONFIG_TPM Support TPM devices. @@ -1403,10 +1394,6 @@ Low Level (hardware related) configuration options: VPL. Code that needs phase-specific behaviour can check this, or (where possible) use xpl_phase() instead. - Note that CONFIG_XPL_BUILD *is* always defined when either - of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be - counter-intuitive and should perhaps be changed. - - CONFIG_TPL_BUILD Set when the currently running compilation is for an artifact that will end up in the TPL build (as opposed to SPL, VPL or diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9ed55e6cfac..5872455a0fe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -906,6 +906,7 @@ config ARCH_IMX8 config ARCH_IMX8M bool "NXP i.MX8M platform" + select ARCH_MISC_INIT if FSL_CAAM select ARM64 select GPIO_EXTRA_HEADER select MACH_IMX @@ -955,6 +956,7 @@ config ARCH_IMXRT config ARCH_MX23 bool "NXP i.MX23 family" + select ARCH_MISC_INIT select CPU_ARM926EJS select GPIO_EXTRA_HEADER select MACH_IMX @@ -962,17 +964,12 @@ config ARCH_MX23 config ARCH_MX28 bool "NXP i.MX28 family" + select ARCH_MISC_INIT select CPU_ARM926EJS select GPIO_EXTRA_HEADER select MACH_IMX select SUPPORT_SPL -config ARCH_MX31 - bool "NXP i.MX31 family" - select CPU_ARM1136 - select GPIO_EXTRA_HEADER - select MACH_IMX - config ARCH_MX7ULP bool "NXP MX7ULP" select BOARD_POSTCLK_INIT @@ -1109,6 +1106,7 @@ config ARCH_QEMU config ARCH_RENESAS bool "Renesas ARM SoCs" + select ARCH_MISC_INIT if DISPLAY_CPUINFO && !(RZA1 || RZN1) select DM select DM_SERIAL select GPIO_EXTRA_HEADER @@ -1118,7 +1116,6 @@ config ARCH_RENESAS imply FAT_WRITE imply OF_UPSTREAM imply SYS_THUMB_BUILD - imply ARCH_MISC_INIT if DISPLAY_CPUINFO config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" @@ -1547,7 +1544,6 @@ config TARGET_LX2160AQDS config TARGET_LX2162AQDS bool "Support lx2162aqds" select ARCH_LX2162A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1960,7 +1956,6 @@ config TARGET_SL28 config TARGET_TEN64 bool "Support ten64" select ARCH_LS1088A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -2318,8 +2313,6 @@ source "arch/arm/mach-octeontx2/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" -source "arch/arm/mach-imx/mx3/Kconfig" - source "arch/arm/mach-imx/mx5/Kconfig" source "arch/arm/mach-imx/mx6/Kconfig" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 46ace7e5fd6..5c8839583aa 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,5 +1,6 @@ config ARCH_LS1021A bool + select ARCH_MISC_INIT if FSL_CAAM select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI select LS102XA_STREAM_ID diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 080fe3fc327..787c7a7c1da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -328,6 +328,7 @@ config ARCH_LX2160A config FSL_LSCH2 bool + select ARCH_MISC_INIT if FSL_CAAM select SKIP_LOWLEVEL_INIT select SYS_FSL_CCSR_GUR_BE select SYS_FSL_CCSR_SCFG_BE diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 10404ce076e..17795f8f746 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -924,6 +924,7 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RZA1) += \ + r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r7s72100-genmai-u-boot.dtsi b/arch/arm/dts/r7s72100-genmai-u-boot.dtsi new file mode 100644 index 00000000000..782ebfea2fb --- /dev/null +++ b/arch/arm/dts/r7s72100-genmai-u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Genmai board + * Based on GR Peach, Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + */ + +/ { + soc { + bootph-all; + }; +}; + +&bsc { + bootph-all; +}; + +&ostm0 { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&scif2 { + bootph-all; + clock = <66666666>; /* ToDo: Replace by DM clock driver */ +}; + +&scif2_pins { + bootph-all; +}; diff --git a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index 744f4aaaad9..d88e839a890 100644 --- a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index 305c4861520..8269d967af9 100644 --- a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 84a28bf885c..0a1602cdd23 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index 6372f953956..d2a0406be17 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index d9a28fe9bab..518466aca35 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index aa5de3d0465..3905bf4e4f7 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dtsi b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index 34a735ae5b2..382bfe8cacd 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -14,7 +14,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c0/eeprom@50}>; bootph-all; }; }; @@ -22,10 +22,7 @@ &i2c0 { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; }; }; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index b6b7b8f3609..a52c5de4ddf 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -10,23 +10,16 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; &i2c_dvfs { - compatible = "renesas,iic-r8a77990", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dtsi b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 1922c40a438..19d19542efd 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c0/eeprom@50}>; bootph-all; }; }; @@ -18,10 +18,7 @@ &i2c0 { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; }; }; diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index 5aa61314834..bd6a3d0713f 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -7,73 +7,25 @@ / { binman: binman { - multiple-images; - section { filename = "flash.bin"; pad-byte = <0xff>; - /* Offset 0x0000 set to 0x0000_0000 */ - fill@0 { - offset = <0x0>; - size = <0x4>; - fill-byte = [00]; - }; - - /* Offset 0x300c set to 0x0000_0000 */ - fill@300c { - offset = <0x300c>; - size = <0x4>; - fill-byte = [00]; - }; - - /* Offset 0x3154 set to 0xeb21_0000 */ - fill@3154 { - offset = <0x3154>; - size = <0x2>; - fill-byte = [00]; - }; - - fill@3156 { - offset = <0x3156>; - size = <0x1>; - fill-byte = [21]; - }; - - fill@3157 { - offset = <0x3157>; - size = <0x1>; - fill-byte = [eb]; - }; - - /* Offset 0x3264 set to 0x0003_b000 */ - fill@3264 { - offset = <0x3264>; - size = <0x1>; - fill-byte = [00]; - }; - - fill@3265 { - offset = <0x3265>; - size = <0x1>; - fill-byte = [b0]; - }; - - fill@3266 { - offset = <0x3266>; - size = <0x1>; - fill-byte = [03]; - }; - - fill@3267 { - offset = <0x3267>; - size = <0x1>; - fill-byte = [00]; - }; - - u-boot-spl { - offset = <0x40000>; - align-end = <4>; + renesas-rcar4-sa0 { + filename = "sa0.bin"; + pad-byte = <0xff>; + renesas,loader-address = <CONFIG_SPL_TEXT_BASE>; + + /* + * This section starts after 0x40000 Bytes long + * header added by the renesas-rcar4-sa0 binman + * etype. That means u-boot-spl {} below starts + * at offset 0x40000 in flash.bin . + */ + u-boot-spl { + offset = <0x40000>; + align-end = <4>; + }; }; u-boot { diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h deleted file mode 100644 index e99e115f79e..00000000000 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#define MXC_HCLK CONFIG_MX31_HCLK_FREQ - -#define MXC_CLK32 CONFIG_MX31_CLK32 - -enum mxc_clock { - MXC_ARM_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_CSPI_CLK, - MXC_UART_CLK, - MXC_IPU_CLK, - MXC_ESDHC_CLK, - MXC_I2C_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -extern u32 imx_get_uartclk(void); -extern void mx31_gpio_mux(unsigned long mode); -extern void mx31_set_pad(enum iomux_pins pin, u32 config); -extern void mx31_set_gpr(enum iomux_gp_func gp, char en); - -void mx31_uart1_hw_init(void); -void mx31_uart2_hw_init(void); -void mx31_spi2_hw_init(void); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h deleted file mode 100644 index 1bfe28f95c9..00000000000 --- a/arch/arm/include/asm/arch-mx31/gpio.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - -#ifndef __ASM_ARCH_MX31_GPIO_H -#define __ASM_ARCH_MX31_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h deleted file mode 100644 index a608732f765..00000000000 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ /dev/null @@ -1,905 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - -#ifndef __ASM_ARCH_MX31_IMX_REGS_H -#define __ASM_ARCH_MX31_IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock control module registers */ -struct clock_control_regs { - u32 ccmr; - u32 pdr0; - u32 pdr1; - u32 rcsr; - u32 mpctl; - u32 upctl; - u32 spctl; - u32 cosr; - u32 cgr0; - u32 cgr1; - u32 cgr2; - u32 wimr0; - u32 ldc; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; - u32 ltr0; - u32 ltr1; - u32 ltr2; - u32 ltr3; - u32 ltbr0; - u32 ltbr1; - u32 pmcr0; - u32 pmcr1; - u32 pdr2; -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_5[6]; - u32 usr; - u32 fuse7_15[9]; -}; - -struct fuse_bank2_regs { - u32 fuse0; - u32 uid[8]; - u32 fuse9_15[7]; -}; - -struct iomuxc_regs { - u32 unused1; - u32 unused2; - u32 gpr; -}; - -struct mx3_cpu_type { - u8 srev; - u32 v; -}; - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), - MX31_PIN_PWMO = IOMUX_PIN(9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN(8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* Bit definitions for RCSR register in CCM */ -#define CCM_RCSR_NF16B (1 << 31) -#define CCM_RCSR_NFMS (1 << 30) - -/* WEIM CS control registers */ -struct mx31_weim_cscr { - u32 upper; - u32 lower; - u32 additional; - u32 reserved; -}; - -struct mx31_weim { - struct mx31_weim_cscr cscr[6]; -}; - -/* ESD control registers */ -struct esdc_regs { - u32 ctl0; - u32 cfg0; - u32 ctl1; - u32 cfg1; - u32 misc; - u32 dly[5]; - u32 dlyl; -}; - -#endif - -#define ARCH_MXC - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -#define CCM_BASE 0x53f80000 -#define CCM_CCMR (CCM_BASE + 0x00) -#define CCM_PDR0 (CCM_BASE + 0x04) -#define CCM_PDR1 (CCM_BASE + 0x08) -#define CCM_RCSR (CCM_BASE + 0x0c) -#define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x14) -#define CCM_SPCTL (CCM_BASE + 0x18) -#define CCM_COSR (CCM_BASE + 0x1C) -#define CCM_CGR0 (CCM_BASE + 0x20) -#define CCM_CGR1 (CCM_BASE + 0x24) -#define CCM_CGR2 (CCM_BASE + 0x28) - -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) - -#define MX31_IIM_BASE_ADDR 0x5001C000 -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR - -#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) -#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) - -#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) -#define PDR1_USB_PODF(x) (((x) & 0x7) << 27) -#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) -#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) -#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) -#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) -#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) -#define PDR1_SSI1_PODF(x) ((x) & 0x3f) - -#define PLL_BRMO(x) (((x) & 0x1) << 31) -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) -#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) -#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) -#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) -#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) -#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) -#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) -#define GET_PDR0_MCU_PODF(x) ((x) & 0x7) - -#define GET_PLL_PD(x) (((x) >> 26) & 0xf) -#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) -#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) -#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) - -#define WEIM_ESDCTL0 0xB8001000 -#define WEIM_ESDCFG0 0xB8001004 -#define WEIM_ESDCTL1 0xB8001008 -#define WEIM_ESDCFG1 0xB800100C -#define WEIM_ESDMISC 0xB8001010 - -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define UART3_BASE 0x5000C000 -#define UART4_BASE 0x43FB0000 -#define UART5_BASE 0x43FB4000 - -#define UART_BASE_ADDR(n) ( \ - !!sizeof(struct { \ - static_assert((n) >= 1 && (n) <= 5); \ - int pad; \ - }) * ( \ - (n) == 1 ? UART1_BASE : \ - (n) == 2 ? UART2_BASE : \ - (n) == 3 ? UART3_BASE : \ - (n) == 4 ? UART4_BASE : \ - UART5_BASE_ADDR) \ - ) - -#define I2C1_BASE_ADDR 0x43f80000 -#define I2C1_CLK_OFFSET 26 -#define I2C2_BASE_ADDR 0x43F98000 -#define I2C2_CLK_OFFSET 28 -#define I2C3_BASE_ADDR 0x43f84000 -#define I2C3_CLK_OFFSET 30 - -#define ESDCTL_SDE (1 << 31) -#define ESDCTL_CMD_RW (0 << 28) -#define ESDCTL_CMD_PRECHARGE (1 << 28) -#define ESDCTL_CMD_AUTOREFRESH (2 << 28) -#define ESDCTL_CMD_LOADMODEREG (3 << 28) -#define ESDCTL_CMD_MANUALREFRESH (4 << 28) -#define ESDCTL_ROW_13 (2 << 24) -#define ESDCTL_ROW(x) ((x) << 24) -#define ESDCTL_COL_9 (1 << 20) -#define ESDCTL_COL(x) ((x) << 20) -#define ESDCTL_DSIZ(x) ((x) << 16) -#define ESDCTL_SREFR(x) ((x) << 13) -#define ESDCTL_PWDT(x) ((x) << 10) -#define ESDCTL_FP(x) ((x) << 8) -#define ESDCTL_BL(x) ((x) << 7) -#define ESDCTL_PRCT(x) ((x) << 0) - -#define ESDCTL_BASE_ADDR 0xB8001000 - -/* 13 fields of the upper CS control register */ -#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ - (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ - (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -#define WEIM_BASE 0xb8002000 - -#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) - -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -#define ARM_PPMRR 0x40000015 - -#define WDOG1_BASE_ADDR 0x53FDC000 - -/* - * GPIO - */ -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define GPIO_DR 0x00000000 /* data register */ -#define GPIO_GDIR 0x00000004 /* direction register */ -#define GPIO_PSR 0x00000008 /* pad status register */ - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) - -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_CSPI3_MISO 0x0c -#define MUX_CTL_CSPI3_SCLK 0x0d -#define MUX_CTL_CSPI3_SPI_RDY 0x0e -#define MUX_CTL_CSPI3_MOSI 0x13 - -#define MUX_CTL_SD1_DATA1 0x18 -#define MUX_CTL_SD1_DATA2 0x19 -#define MUX_CTL_SD1_DATA3 0x1a -#define MUX_CTL_SD1_CMD 0x1d -#define MUX_CTL_SD1_CLK 0x1e -#define MUX_CTL_SD1_DATA0 0x1f - -#define MUX_CTL_USBH2_DATA1 0x40 -#define MUX_CTL_USBH2_DIR 0x44 -#define MUX_CTL_USBH2_STP 0x45 -#define MUX_CTL_USBH2_NXT 0x46 -#define MUX_CTL_USBH2_DATA0 0x47 -#define MUX_CTL_USBH2_CLK 0x4B - -#define MUX_CTL_TXD2 0x70 -#define MUX_CTL_RTS2 0x71 -#define MUX_CTL_CTS2 0x72 -#define MUX_CTL_RXD2 0x77 - -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -#define MUX_CTL_CSPI2_SS0 0x85 -#define MUX_CTL_CSPI2_SS1 0x86 -#define MUX_CTL_CSPI2_SS2 0x87 -#define MUX_CTL_CSPI1_SS2 0x88 -#define MUX_CTL_CSPI1_SCLK 0x89 -#define MUX_CTL_CSPI1_SPI_RDY 0x8a -#define MUX_CTL_CSPI2_MOSI 0x8b -#define MUX_CTL_CSPI1_MOSI 0x8c -#define MUX_CTL_CSPI1_MISO 0x8d -#define MUX_CTL_CSPI1_SS0 0x8e -#define MUX_CTL_CSPI1_SS1 0x8f -#define MUX_CTL_STXD6 0x90 -#define MUX_CTL_SRXD6 0x91 -#define MUX_CTL_SCK6 0x92 -#define MUX_CTL_SFS6 0x93 - -#define MUX_CTL_STXD3 0x9C -#define MUX_CTL_SRXD3 0x9D -#define MUX_CTL_SCK3 0x9E -#define MUX_CTL_SFS3 0x9F - -#define MUX_CTL_NFC_WP 0xD0 -#define MUX_CTL_NFC_CE 0xD1 -#define MUX_CTL_NFC_RB 0xD2 -#define MUX_CTL_NFC_WE 0xD4 -#define MUX_CTL_NFC_RE 0xD5 -#define MUX_CTL_NFC_ALE 0xD6 -#define MUX_CTL_NFC_CLE 0xD7 - -#define MUX_CTL_CAPTURE 0x150 -#define MUX_CTL_COMPARE 0x151 - -/* - * Helper macros for the MUX_[contact name]__[pin function] macros - */ -#define IOMUX_MODE_POS 9 -#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) - -/* - * These macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) -#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) -#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) -#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) - -#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) -#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) -#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) -#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) - -#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) -#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) -#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) -#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) -#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) -#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) -#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) -#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) -#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) - -/* PAD control registers for SDR/DDR */ -#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) -#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) -#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) -#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) -#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) -#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) -#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) -#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) -#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) -#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) -#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) -#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) -#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) -#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) -#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) -#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) -#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) -#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) -#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) -#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) -#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) -#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) -#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) -#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) -#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) -#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) -#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) -#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) -#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE 0x70000000 -#define CSD0_BASE 0x80000000 -#define CSD1_BASE 0x90000000 -#define CS0_BASE 0xA0000000 -#define CS1_BASE 0xA8000000 -#define CS2_BASE 0xB0000000 -#define CS3_BASE 0xB2000000 -#define CS4_BASE 0xB4000000 -#define CS4_PSRAM_BASE 0xB5000000 -#define CS5_BASE 0xB6000000 -#define PCMCIA_MEM_BASE 0xC0000000 - -/* - * NAND controller - */ -#define NFC_BASE_ADDR 0xB8000000 - -/* SD card controller */ -#define SDHC1_BASE_ADDR 0x50004000 -#define SDHC2_BASE_ADDR 0x50008000 - -/* - * Internal RAM (16KB) - */ -#define IRAM_BASE_ADDR 0x1FFFC000 -#define IRAM_SIZE (16 * 1024) - -#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) -#define IMX_USB_PORT_OFFSET 0x200 - -/* - * CSPI register definitions - */ -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, \ - 0x53f84000, - -/* - * Generic timer support - */ -#ifdef CONFIG_MX31_CLK32 -#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32 -#else -#define CFG_SYS_TIMER_RATE 32768 -#endif - -#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h deleted file mode 100644 index 29fc0fda0e6..00000000000 --- a/arch/arm/include/asm/arch-mx31/sys_proto.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - */ - -#ifndef _MX31_SYS_PROTO_H_ -#define _MX31_SYS_PROTO_H_ - -#include <asm/mach-imx/sys_proto.h> - -struct mxc_weimcs { - u32 upper; - u32 lower; - u32 additional; -}; - -void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); -int mxc_mmc_init(struct bd_info *bis); -#endif diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 3cdb71a2528..1fe083ae94f 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1151,7 +1151,7 @@ int disable_gpu_nodes(void *blob) { static const char * const nodes_path_8mn[] = { "/gpu@38000000", - "/soc@/gpu@38000000" + "/soc@0/gpu@38000000" }; static const char * const nodes_path_8mp[] = { diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 280d255c086..6af45938edb 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -22,10 +22,12 @@ config IMX93 config IMX91 bool select IMX9 + select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS config IMX95 bool + select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS select IMX9 select DM_MAILBOX diff --git a/arch/arm/mach-imx/mx3/Kconfig b/arch/arm/mach-imx/mx3/Kconfig deleted file mode 100644 index 42bba4822e6..00000000000 --- a/arch/arm/mach-imx/mx3/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -if ARCH_MX31 - -config MX31 - bool - default y -choice - prompt "MX31 board select" - optional - -config TARGET_MX31PDK - bool "Support the i.MX31 PDK board from Freescale/NXP" - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - select SUPPORT_SPL - -endchoice - -config MX31_HCLK_FREQ - int "i.MX31 HCLK frequency" - default 26000000 - help - Frequency in Hz of the high frequency input clock. Typically - 26000000 Hz. - -config MX31_CLK32 - int "i.MX31 CLK32 Frequency" - default 32768 - help - Frequency in Hz of the low frequency input clock. Typically - 32768 or 32000 Hz. - - -endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 2f873ed6ddf..3f5e91da204 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -63,6 +63,7 @@ config MX6UL config MX6ULL bool "i.MX 6ULL SoC support" + select ARCH_MISC_INIT select ROM_UNIFIED_SECTIONS select SYSCOUNTER_TIMER select SYS_L2CACHE_OFF diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 46abf070f9d..dff4f1cf202 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -9,6 +9,7 @@ choice config TARGET_AM335X_EVM bool "Support am335x_evm" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_GPIO @@ -70,6 +71,7 @@ config TARGET_AM335X_SHC config TARGET_AM335X_GUARDIAN bool "Support am335x based guardian board from bosch" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_SERIAL @@ -116,6 +118,7 @@ config TARGET_ETAMIN config TARGET_PCM051 bool "Support pcm051" + select ARCH_MISC_INIT select DM select DM_GPIO select DM_SERIAL @@ -123,6 +126,7 @@ config TARGET_PCM051 config TARGET_PHYCORE_AM335X_R2 bool "Support phyCORE AM335X R2" + select ARCH_MISC_INIT select DM select DM_GPIO select DM_SERIAL @@ -130,6 +134,7 @@ config TARGET_PHYCORE_AM335X_R2 config TARGET_PXM2 bool "Support pxm2" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_GPIO @@ -148,6 +153,7 @@ config TARGET_RASTABAN config TARGET_RUT bool "Support rut" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_GPIO diff --git a/arch/arm/mach-renesas/Kconfig.rza1 b/arch/arm/mach-renesas/Kconfig.rza1 index e88f9a2eedb..c9e2b835204 100644 --- a/arch/arm/mach-renesas/Kconfig.rza1 +++ b/arch/arm/mach-renesas/Kconfig.rza1 @@ -14,12 +14,16 @@ choice prompt "Renesas RZ/A1 board select" # Renesas Supported Boards +config TARGET_GENMAI + bool "GENMAI board" + config TARGET_GRPEACH bool "GR-PEACH board" endchoice # Renesas Supported Boards +source "board/renesas/genmai/Kconfig" source "board/renesas/grpeach/Kconfig" endif diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 317fce02d2b..9165ceab4a3 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -19,12 +19,12 @@ ifneq ($(CONFIG_RCAR_64),) obj-$(CONFIG_ARMV8_PSCI) += psci-rcar64.o endif -OBJCOPYFLAGS_u-boot-spl.srec := -O srec +OBJCOPYFLAGS_u-boot-spl.srec := -I binary -O srec --change-addresses=$(CONFIG_SPL_TEXT_BASE) quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ $(OBJCOPYFLAGS_$(@F)) $< $@ -spl/u-boot-spl.srec: spl/u-boot-spl FORCE +spl/u-boot-spl.srec: spl/u-boot-spl.bin FORCE $(call if_changed,objcopy) srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"} @@ -34,6 +34,15 @@ else srec_cat_le_cmd := "-l-e-constant" endif +ifneq ($(CONFIG_RCAR_GEN4),) +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ + -Output_Block_Size 16 \ + -generate 0xeb203000 0xeb203154 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xeb203154 0xeb203158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xeb203158 0xeb203264 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xeb203264 0xeb203268 $(srec_cat_le_cmd) $$(( ( $2 + 4 ) / 4 )) 4 +else ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),) # # The first 6 generate statements generate the R-Car Gen3 SCIF loader header. @@ -90,6 +99,7 @@ quiet_cmd_srec_cat = SRECCAT $@ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif +endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}')) diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 5d2186bba55..6105cdcf96e 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -42,6 +42,7 @@ config TARGET_OCTEON_EBB7304 config TARGET_OCTEON_NIC23 bool "Marvell Octeon NIC23" + select ARCH_MISC_INIT select OCTEON_CN73XX help Choose this for the Octeon NIC23 board diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 7026c73bc69..bb696c5ef7f 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -2150,6 +2150,10 @@ }; }; }; + + aes-engine { + compatible = "software-aes-engine"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index f656f361cd5..6e3f9547fee 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -74,7 +74,14 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) +#define out_64(a,v) writeq(v,a) +#define out_32(a,v) writel(v,a) +#define out_16(a,v) writew(v,a) #define out_8(a,v) writeb(v,a) + +#define in_64(a) readq(a) +#define in_32(a) readl(a) +#define in_16(a) readw(a) #define in_8(a) readb(a) #define clrbits(type, addr, clear) \ @@ -106,6 +113,18 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define clrbits_16(addr, clear) clrbits(16, addr, clear) +#define setbits_16(addr, set) setbits(16, addr, set) +#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set) + +#define clrbits_32(addr, clear) clrbits(32, addr, clear) +#define setbits_32(addr, set) setbits(32, addr, set) +#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set) + +#define clrbits_64(addr, clear) clrbits(64, addr, clear) +#define setbits_64(addr, set) setbits(64, addr, set) +#define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set) + /* I/O access functions */ int _inl(unsigned int addr); int _inw(unsigned int addr); diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 5e51b691178..1849c995aee 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -5,6 +5,7 @@ # # R-Car SoCs +ifndef CONFIG_RZA1 ifndef CONFIG_RZG2L # 32 bit SoCs @@ -45,3 +46,10 @@ endif endif endif +endif + +# RZ/A1 SoCs +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif diff --git a/board/renesas/common/rza1-common.c b/board/renesas/common/rza1-common.c new file mode 100644 index 00000000000..5027319a58a --- /dev/null +++ b/board/renesas/common/rza1-common.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <init.h> +#include <asm/io.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/common/rza1-lowlevel_init.S index b83c4e86867..b83c4e86867 100644 --- a/board/renesas/grpeach/lowlevel_init.S +++ b/board/renesas/common/rza1-lowlevel_init.S diff --git a/board/renesas/genmai/Kconfig b/board/renesas/genmai/Kconfig new file mode 100644 index 00000000000..4e67a9b325a --- /dev/null +++ b/board/renesas/genmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENMAI + +config SYS_BOARD + default "genmai" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "genmai" + +endif diff --git a/board/renesas/genmai/MAINTAINERS b/board/renesas/genmai/MAINTAINERS new file mode 100644 index 00000000000..1f1c2944632 --- /dev/null +++ b/board/renesas/genmai/MAINTAINERS @@ -0,0 +1,5 @@ +GENMAI BOARD +M: Magnus Damm <damm@opensource.se> +S: Maintained +F: arch/arm/dts/r7s72100* +N: genmai diff --git a/board/renesas/genmai/Makefile b/board/renesas/genmai/Makefile new file mode 100644 index 00000000000..73f5e45affd --- /dev/null +++ b/board/renesas/genmai/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Magnus Damm <damm@opensource.se> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := genmai.o diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c new file mode 100644 index 00000000000..8153aed15e3 --- /dev/null +++ b/board/renesas/genmai/genmai.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Magnus Damm <damm@opensource.se> + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> + +#define RZA1_BCR_BASE 0x3FFFC000 +#define CS0BCR (RZA1_BCR_BASE + 0x04) +#define CS0WCR (RZA1_BCR_BASE + 0x28) +#define CS1BCR (RZA1_BCR_BASE + 0x08) +#define CS1WCR (RZA1_BCR_BASE + 0x2c) + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* setup NOR Flash on CS0 and CS1 */ + writel(0x00000b40, CS0WCR); + writel(0x10000c00, CS0BCR); + writel(0x00000b40, CS1WCR); + writel(0x10000c00, CS1BCR); + return 0; +} + +/* + * The Genmai DT will most likely contain memory nodes describing the external + * SDRAM memory connected to CS2 and CS3, however we do not yet have any code + * in U-Boot to setup the memory controller. For now ignore DT and make use of + * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE. + */ + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + gd->ram_size = 10 << 20; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile index 48e185ce3e8..89f8e0e8544 100644 --- a/board/renesas/grpeach/Makefile +++ b/board/renesas/grpeach/Makefile @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a0..3a6393fdce1 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include <cpu_func.h> #include <errno.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ int dram_init_banksize(void) return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} diff --git a/board/ti/am64x/rm-cfg.yaml b/board/ti/am64x/rm-cfg.yaml index 88b37b5972c..1cc4cd34430 100644 --- a/board/ti/am64x/rm-cfg.yaml +++ b/board/ti/am64x/rm-cfg.yaml @@ -1,1215 +1,1215 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM64x +# Resource management configuration for AM64X # --- rm-cfg: - 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# 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - 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+ start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 2124 + host_id: 35 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 2124 + host_id: 36 + reserved: 0 + - + start_resource: 22 + num_resource: 2 + type: 2124 + host_id: 38 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 2124 + host_id: 41 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 2124 + host_id: 43 + reserved: 0 + - + start_resource: 28 + num_resource: 4 + type: 2124 + host_id: 128 + reserved: 0 diff --git a/board/ti/j7200/rm-cfg.yaml b/board/ti/j7200/rm-cfg.yaml index f83184bbfc0..9da0ea91ada 100644 --- a/board/ti/j7200/rm-cfg.yaml +++ b/board/ti/j7200/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J7200 # @@ -7,1779 +7,1779 @@ --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 3 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 2 - host_id: 5 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 3 - host_id: 12 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 4 - host_id: 13 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 5 - host_id: 35 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 6 - host_id: 37 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 7 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 8 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 9 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 10 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 11 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 12 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 13 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 14 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - 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+ start_resource: 40 + num_resource: 4 + type: 15117 + host_id: 37 + reserved: 0 + - + start_resource: 44 + num_resource: 2 + type: 15117 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15119 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 15119 + host_id: 12 + reserved: 0 + - + start_resource: 1 + num_resource: 1 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 11 + num_resource: 20 + type: 15168 + host_id: 3 + reserved: 0 + - + start_resource: 36 + num_resource: 28 + type: 15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml index 0163e3e1717..88ec2026db0 100644 --- a/board/ti/j721e/rm-cfg.yaml +++ b/board/ti/j721e/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721E # @@ -7,2751 +7,2751 @@ --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 3 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 2 - host_id: 5 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 3 - host_id: 12 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 4 - host_id: 13 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 5 - host_id: 21 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - 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+ start_resource: 43 + num_resource: 3 + type: 15117 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 12 + num_resource: 20 + type: 15168 + host_id: 3 + reserved: 0 + - + start_resource: 36 + num_resource: 28 + type: 15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index e32beb84795..62730adf216 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J722S # @@ -16,224 +16,224 @@ rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 3 host_id: 22 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 4 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 5 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 6 host_id: 38 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml index 4a2af0ebcaf..7b2e58a89b3 100644 --- a/board/ti/j722s/tifs-rm-cfg.yaml +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J722S # @@ -16,224 +16,224 @@ tifs-rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - #1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #2 + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #3 + - # 3 host_id: 22 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #4 + - # 4 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #5 + - # 5 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #6 + - # 6 host_id: 38 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #7 + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #8 + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #9 + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #10 + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #11 + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #12 + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #13 + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #14 + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #15 + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #16 + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #17 + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #18 + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #19 + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #20 + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #21 + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #22 + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #23 + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #24 + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #25 + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #26 + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #27 + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #28 + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #29 + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #30 + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #31 + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #32 + - 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+ start_resource: 0 + num_resource: 2 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 12810 + host_id: 20 + reserved: 0 + - + start_resource: 4 + num_resource: 2 + type: 12810 + host_id: 22 + reserved: 0 + - + start_resource: 22 + num_resource: 18 + type: 12810 + host_id: 38 + reserved: 0 + - + start_resource: 1536 + num_resource: 8 + type: 12823 + host_id: 128 + reserved: 0 + - + start_resource: 2048 + num_resource: 8 + type: 12824 + host_id: 128 + reserved: 0 + - + start_resource: 2560 + num_resource: 8 + type: 12825 + host_id: 128 + reserved: 0 + - + start_resource: 3072 + num_resource: 32 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 32 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 32 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 4557ed1f1f2..168840764a1 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -36,7 +36,7 @@ #define VCC_USBO1 TEGRA_GPIO(T, 5) #define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4) -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) { diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 02e8f8eb1fe..2c785da41ea 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; static int pci_reset_status; #endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index d432fd2b843..05c3377a60b 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #define PMU_SUPPLYENE_SYSINEN (1<<5) #define PMU_SUPPLYENE_EXITSLREQ (1<<1) -int arch_misc_init(void) +int misc_init_r(void) { /* Disable PMIC sleep mode on low supply voltage */ struct udevice *dev; diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 342673ac506..1b091ea1694 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -18,7 +18,7 @@ #include "pinmux-config-colibri_t30.h" #include "../common/tdx-common.h" -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 1020078afea..3c2d0ba1dd4 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -53,7 +53,9 @@ void spl_dram_init(void) void spl_board_init(void) { +#if IS_ENABLED(CONFIG_ARCH_MISC_INIT) arch_misc_init(); +#endif } #ifdef CONFIG_SPL_LOAD_FIT diff --git a/cmd/Kconfig b/cmd/Kconfig index 1e86773a143..b3b5be1ea79 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -414,7 +414,7 @@ config BOOTM_RTEMS config CMD_SEAMA bool "Support read SEAMA NAND images" - depends on MTD_RAW_NAND + depends on (TARGET_BCMNS || TARGET_BCMNS3) && MTD_RAW_NAND help Support reading NAND Seattle Image (SEAMA) images. @@ -1693,13 +1693,6 @@ config CMD_TEMPERATURE help Provides a way to list thermal sensors and to get their readings. -config CMD_TSI148 - bool "tsi148 - Command to access tsi148 device" - depends on DM_PCI_COMPAT - help - This provides various sub-commands to initialise and configure the - Turndra tsi148 device. See the command help for full details. - config CMD_UFS bool "ufs - Universal Flash Storage commands" depends on UFS @@ -1707,13 +1700,6 @@ config CMD_UFS "This provides commands to initialise and configure universal flash subsystem devices" -config CMD_UNIVERSE - bool "universe - Command to set up the Turndra Universe controller" - depends on DM_PCI_COMPAT - help - This allows setting up the VMEbus provided by this controller. - See the command help for full details. - config CMD_USB bool "usb" depends on USB_HOST @@ -2643,6 +2629,7 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" depends on !MX6ULL && !MX6SLL && !MX6SL + depends on SYS_FSL_SEC_COMPAT >= 4 select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M help This is used with the Freescale secure boot mechanism. diff --git a/cmd/Makefile b/cmd/Makefile index 40f6ac4a85e..e4ecf2e0493 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -191,10 +191,8 @@ obj-$(CONFIG_CMD_TPM_V1) += tpm-v1.o obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o obj-$(CONFIG_CMD_TPM_V2) += tpm-v2.o obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o -obj-$(CONFIG_CMD_TSI148) += tsi148.o obj-$(CONFIG_CMD_UBI) += ubi.o obj-$(CONFIG_CMD_UBIFS) += ubifs.o -obj-$(CONFIG_CMD_UNIVERSE) += universe.o obj-$(CONFIG_CMD_UNLZ4) += unlz4.o obj-$(CONFIG_CMD_UNZIP) += unzip.o obj-$(CONFIG_CMD_UPL) += upl.o diff --git a/cmd/aes.c b/cmd/aes.c index 87ad1ab82b9..3fd83013ffe 100644 --- a/cmd/aes.c +++ b/cmd/aes.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * Copyright (C) 2025 Ion Agorria <ion@agorria.com> * - * Command for en/de-crypting block of memory with AES-[128/192/256]-CBC cipher. + * Command for AES-[128/192/256] operations. */ #include <command.h> @@ -12,6 +13,8 @@ #include <linux/compiler.h> #include <mapmem.h> #include <vsprintf.h> +#include <dm/uclass.h> +#include <dm/device.h> u32 aes_get_key_len(char *command) { @@ -25,29 +28,30 @@ u32 aes_get_key_len(char *command) return key_len; } -/** - * do_aes() - Handle the "aes" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Returns zero on success, CMD_RET_USAGE in case of misuse and negative - * on error. - */ -static int do_aes(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +int aes_get_driver(struct udevice **dev) +{ + int ret; + + ret = uclass_get_device(UCLASS_AES, 0, dev); + if (ret) { + printf("Failed to get AES driver: %d\n", ret); + return ret; + } + + return 0; +} + +int cmd_aes_cbc_simple(int argc, char *const argv[], u32 key_len) { uint32_t key_addr, iv_addr, src_addr, dst_addr, len; uint8_t *key_ptr, *iv_ptr, *src_ptr, *dst_ptr; u8 key_exp[AES256_EXPAND_KEY_LENGTH]; - u32 aes_blocks, key_len; + u32 aes_blocks; int enc; if (argc != 7) return CMD_RET_USAGE; - key_len = aes_get_key_len(argv[0]); - if (!strncmp(argv[1], "enc", 3)) enc = 1; else if (!strncmp(argv[1], "dec", 3)) @@ -84,26 +88,257 @@ static int do_aes(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) unmap_sysmem(src_ptr); unmap_sysmem(dst_ptr); - return 0; + return CMD_RET_SUCCESS; +} + +int cmd_aes_get_slots(void) +{ + struct udevice *dev; + u8 slots; + int ret; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + slots = dm_aes_get_available_key_slots(dev); + printf("Available slots: %d\n", slots); + + return CMD_RET_SUCCESS; +} + +int cmd_aes_set_key(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 key_addr, slot; + u8 *key_ptr; + int ret; + + if (argc != 4) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + key_addr = hextoul(argv[2], NULL); + slot = hextoul(argv[3], NULL); + + key_ptr = (uint8_t *)map_sysmem(key_addr, key_len); + + ret = dm_aes_set_key_for_key_slot(dev, key_len * 8, key_ptr, slot); + unmap_sysmem(key_ptr); + if (ret) { + printf("Unable to set key at slot: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +int cmd_aes_select_slot(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 slot; + int ret; + + if (argc != 3) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + slot = hextoul(argv[2], NULL); + + ret = dm_aes_select_key_slot(dev, key_len * 8, slot); + if (ret) { + printf("Unable to select key slot: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +int cmd_aes_ecb(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 src_addr, dst_addr, len; + u8 *src_ptr, *dst_ptr; + u32 aes_blocks; + int enc, ret; + + if (argc != 6) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + src_addr = hextoul(argv[3], NULL); + dst_addr = hextoul(argv[4], NULL); + len = hextoul(argv[5], NULL); + + src_ptr = (uint8_t *)map_sysmem(src_addr, len); + dst_ptr = (uint8_t *)map_sysmem(dst_addr, len); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = DIV_ROUND_UP(len, AES_BLOCK_LENGTH); + + if (enc) + ret = dm_aes_ecb_encrypt(dev, src_ptr, dst_ptr, aes_blocks); + else + ret = dm_aes_ecb_decrypt(dev, src_ptr, dst_ptr, aes_blocks); + + unmap_sysmem(src_ptr); + unmap_sysmem(dst_ptr); + + if (ret) { + printf("Unable to do ecb operation: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +int cmd_aes_cbc(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 iv_addr, src_addr, dst_addr, len; + u8 *iv_ptr, *src_ptr, *dst_ptr; + u32 aes_blocks; + int enc, ret; + + if (argc != 7) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + iv_addr = hextoul(argv[3], NULL); + src_addr = hextoul(argv[4], NULL); + dst_addr = hextoul(argv[5], NULL); + len = hextoul(argv[6], NULL); + + iv_ptr = (uint8_t *)map_sysmem(iv_addr, AES_BLOCK_LENGTH); + src_ptr = (uint8_t *)map_sysmem(src_addr, len); + dst_ptr = (uint8_t *)map_sysmem(dst_addr, len); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = DIV_ROUND_UP(len, AES_BLOCK_LENGTH); + + if (enc) + ret = dm_aes_cbc_encrypt(dev, iv_ptr, src_ptr, dst_ptr, aes_blocks); + else + ret = dm_aes_cbc_decrypt(dev, iv_ptr, src_ptr, dst_ptr, aes_blocks); + + unmap_sysmem(iv_ptr); + unmap_sysmem(src_ptr); + unmap_sysmem(dst_ptr); + + if (ret) { + printf("Unable to do cbc operation: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +/** + * do_aes() - Handle the "aes" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_aes(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u32 key_len; + + if (argc < 2) + return CMD_RET_USAGE; + + key_len = aes_get_key_len(argv[0]); + + if (!strncmp(argv[1], "enc", 3) || !strncmp(argv[1], "dec", 3)) + return cmd_aes_cbc_simple(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "get_slots", 9)) + return cmd_aes_get_slots(); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "set_key", 7)) + return cmd_aes_set_key(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "select_slot", 11)) + return cmd_aes_select_slot(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "ecb", 3)) + return cmd_aes_ecb(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "cbc", 3)) + return cmd_aes_cbc(argc, argv, key_len); + else + return CMD_RET_USAGE; } /***************************************************/ U_BOOT_LONGHELP(aes, - "[.128,.192,.256] enc key iv src dst len - Encrypt block of data $len bytes long\n" + "[.128,.192,.256] enc key iv src dst len - CBC encrypt block of data $len bytes long\n" " at address $src using a key at address\n" " $key with initialization vector at address\n" " $iv. Store the result at address $dst.\n" " The $len size must be multiple of 16 bytes.\n" " The $key and $iv must be 16 bytes long.\n" - "aes [.128,.192,.256] dec key iv src dst len - Decrypt block of data $len bytes long\n" + "aes [.128,.192,.256] dec key iv src dst len - CBC decrypt block of data $len bytes long\n" " at address $src using a key at address\n" " $key with initialization vector at address\n" " $iv. Store the result at address $dst.\n" " The $len size must be multiple of 16 bytes.\n" - " The $key and $iv must be 16 bytes long."); + " The $key and $iv must be 16 bytes long." + +#if CONFIG_IS_ENABLED(DM_AES) + "\n" + "aes get_slots - Gives number of available key slots\n" + "aes [.128,.192,.256] set_key key slot - Load key at address $key into the slot $slot\n" + "aes [.128,.192,.256] select_slot slot - Select current active key slot\n" + "aes [.128,.192,.256] ecb enc src dst len - ECB encrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + "aes [.128,.192,.256] ecb dec src dst len - ECB decrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + "aes [.128,.192,.256] cbc enc iv src dst len - CBC encrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot with initialization vector at address\n" + " $iv. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + " The $iv must be 16 bytes long.\n" + "aes [.128,.192,.256] cbc dec iv src dst len - CBC decrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot with initialization vector at address\n" + " $iv. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + " The $iv must be 16 bytes long." +#endif +); U_BOOT_CMD( aes, 7, 1, do_aes, - "AES 128/192/256 CBC encryption", + "AES 128/192/256 operations", aes_help_text ); diff --git a/cmd/tsi148.c b/cmd/tsi148.c deleted file mode 100644 index 113b4e67330..00000000000 --- a/cmd/tsi148.c +++ /dev/null @@ -1,472 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com - * - * base on universe.h by - * - * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com - */ - -#include <command.h> -#include <log.h> -#include <malloc.h> -#include <vsprintf.h> -#include <asm/io.h> -#include <pci.h> - -#include <tsi148.h> - -#define LPCI_VENDOR PCI_VENDOR_ID_TUNDRA -#define LPCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148 - -typedef struct _TSI148_DEV TSI148_DEV; - -struct _TSI148_DEV { - int bus; - pci_dev_t busdevfn; - TSI148 *uregs; - unsigned int pci_bs; -}; - -static TSI148_DEV *dev; - -/* - * Most of the TSI148 register are BIGENDIAN - * This is the reason for the __raw_writel(htonl(x), x) usage! - */ - -int tsi148_init(void) -{ - int j, result; - pci_dev_t busdevfn; - unsigned int val; - - busdevfn = pci_find_device(LPCI_VENDOR, LPCI_DEVICE, 0); - if (busdevfn == -1) { - puts("Tsi148: No Tundra Tsi148 found!\n"); - return -1; - } - - /* Lets turn Latency off */ - pci_write_config_dword(busdevfn, 0x0c, 0); - - dev = malloc(sizeof(*dev)); - if (NULL == dev) { - puts("Tsi148: No memory!\n"); - return -1; - } - - memset(dev, 0, sizeof(*dev)); - dev->busdevfn = busdevfn; - - pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val); - val &= ~0xf; - dev->uregs = (TSI148 *)val; - - debug("Tsi148: Base : %p\n", dev->uregs); - - /* check mapping */ - debug("Tsi148: Read via mapping, PCI_ID = %08X\n", - readl(&dev->uregs->pci_id)); - if (((LPCI_DEVICE << 16) | LPCI_VENDOR) != readl(&dev->uregs->pci_id)) { - printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n", - readl(&dev->uregs->pci_id)); - result = -1; - goto break_30; - } - - debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl)); - - dev->pci_bs = readl(&dev->uregs->pci_mbarl); - - /* turn off windows */ - for (j = 0; j < 8; j++) { - __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat); - __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat); - } - - /* Tsi148 VME timeout etc */ - __raw_writel(htonl(0x00000084), &dev->uregs->vctrl); - -#ifdef DEBUG - if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0) - printf("Tsi148: System Controller!\n"); - else - printf("Tsi148: Not System Controller!\n"); -#endif - - /* - * Lets turn off interrupts - */ - /* Disable interrupts in Tsi148 first */ - __raw_writel(htonl(0x00000000), &dev->uregs->inten); - /* Disable interrupt out */ - __raw_writel(htonl(0x00000000), &dev->uregs->inteo); - eieio(); - /* Reset all IRQ's */ - __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc); - /* Map all ints to 0 */ - __raw_writel(htonl(0x00000000), &dev->uregs->intm1); - __raw_writel(htonl(0x00000000), &dev->uregs->intm2); - eieio(); - - val = __raw_readl(&dev->uregs->vstat); - val &= ~(0x00004000); - __raw_writel(val, &dev->uregs->vstat); - eieio(); - - debug("Tsi148: register struct size %08x\n", sizeof(TSI148)); - - return 0; - - break_30: - free(dev); - dev = NULL; - - return result; -} - -/* - * Create pci slave window (access: pci -> vme) - */ -int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, - int size, int vam, int vdw) -{ - int result, i; - unsigned int ctl = 0; - - if (NULL == dev) { - result = -1; - goto exit_10; - } - - for (i = 0; i < 8; i++) { - if (0x00000000 == readl(&dev->uregs->outbound[i].otat)) - break; - } - - if (i > 7) { - printf("Tsi148: No Image available\n"); - result = -1; - goto exit_10; - } - - debug("Tsi148: Using image %d\n", i); - - printf("Tsi148: Pci addr %08x\n", pciAddr); - - __raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal); - __raw_writel(0x00000000, &dev->uregs->outbound[i].otsau); - __raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal); - __raw_writel(0x00000000, &dev->uregs->outbound[i].oteau); - __raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl); - __raw_writel(0x00000000, &dev->uregs->outbound[i].otofu); - - switch (vam & VME_AM_Axx) { - case VME_AM_A16: - ctl = 0x00000000; - break; - case VME_AM_A24: - ctl = 0x00000001; - break; - case VME_AM_A32: - ctl = 0x00000002; - break; - } - - switch (vam & VME_AM_Mxx) { - case VME_AM_DATA: - ctl |= 0x00000000; - break; - case VME_AM_PROG: - ctl |= 0x00000010; - break; - } - - if (vam & VME_AM_SUP) - ctl |= 0x00000020; - - switch (vdw & VME_FLAG_Dxx) { - case VME_FLAG_D16: - ctl |= 0x00000000; - break; - case VME_FLAG_D32: - ctl |= 0x00000040; - break; - } - - ctl |= 0x80040000; /* enable, no prefetch */ - - __raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat); - - debug("Tsi148: window-addr =%p\n", - &dev->uregs->outbound[i].otsau); - debug("Tsi148: pci slave window[%d] attr =%08x\n", - i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat))); - debug("Tsi148: pci slave window[%d] start =%08x\n", - i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal))); - debug("Tsi148: pci slave window[%d] end =%08x\n", - i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal))); - debug("Tsi148: pci slave window[%d] offset=%08x\n", - i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl))); - - return 0; - - exit_10: - return -result; -} - -unsigned int tsi148_eval_vam(int vam) -{ - unsigned int ctl = 0; - - switch (vam & VME_AM_Axx) { - case VME_AM_A16: - ctl = 0x00000000; - break; - case VME_AM_A24: - ctl = 0x00000010; - break; - case VME_AM_A32: - ctl = 0x00000020; - break; - } - switch (vam & VME_AM_Mxx) { - case VME_AM_DATA: - ctl |= 0x00000001; - break; - case VME_AM_PROG: - ctl |= 0x00000002; - break; - case (VME_AM_PROG | VME_AM_DATA): - ctl |= 0x00000003; - break; - } - - if (vam & VME_AM_SUP) - ctl |= 0x00000008; - if (vam & VME_AM_USR) - ctl |= 0x00000004; - - return ctl; -} - -/* - * Create vme slave window (access: vme -> pci) - */ -int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, - int size, int vam) -{ - int result, i; - unsigned int ctl = 0; - - if (NULL == dev) { - result = -1; - goto exit_10; - } - - for (i = 0; i < 8; i++) { - if (0x00000000 == readl(&dev->uregs->inbound[i].itat)) - break; - } - - if (i > 7) { - printf("Tsi148: No Image available\n"); - result = -1; - goto exit_10; - } - - debug("Tsi148: Using image %d\n", i); - - __raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal); - __raw_writel(0x00000000, &dev->uregs->inbound[i].itsau); - __raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal); - __raw_writel(0x00000000, &dev->uregs->inbound[i].iteau); - __raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl); - if (vmeAddr > pciAddr) - __raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu); - else - __raw_writel(0x00000000, &dev->uregs->inbound[i].itofu); - - ctl = tsi148_eval_vam(vam); - ctl |= 0x80000000; /* enable */ - __raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat); - - debug("Tsi148: window-addr =%p\n", - &dev->uregs->inbound[i].itsau); - debug("Tsi148: vme slave window[%d] attr =%08x\n", - i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat))); - debug("Tsi148: vme slave window[%d] start =%08x\n", - i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal))); - debug("Tsi148: vme slave window[%d] end =%08x\n", - i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal))); - debug("Tsi148: vme slave window[%d] offset=%08x\n", - i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl))); - - return 0; - - exit_10: - return -result; -} - -/* - * Create vme slave window (access: vme -> gcsr) - */ -int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam) -{ - int result; - unsigned int ctl; - - result = 0; - - if (NULL == dev) { - result = 1; - } else { - __raw_writel(htonl(vmeAddr), &dev->uregs->gbal); - __raw_writel(0x00000000, &dev->uregs->gbau); - - ctl = tsi148_eval_vam(vam); - ctl |= 0x00000080; /* enable */ - __raw_writel(htonl(ctl), &dev->uregs->gcsrat); - } - - return result; -} - -/* - * Create vme slave window (access: vme -> crcsr) - */ -int tsi148_vme_crcsr_window(unsigned int vmeAddr) -{ - int result; - unsigned int ctl; - - result = 0; - - if (NULL == dev) { - result = 1; - } else { - __raw_writel(htonl(vmeAddr), &dev->uregs->crol); - __raw_writel(0x00000000, &dev->uregs->crou); - - ctl = 0x00000080; /* enable */ - __raw_writel(htonl(ctl), &dev->uregs->crat); - } - - return result; -} - -/* - * Create vme slave window (access: vme -> crg) - */ -int tsi148_vme_crg_window(unsigned int vmeAddr, int vam) -{ - int result; - unsigned int ctl; - - result = 0; - - if (NULL == dev) { - result = 1; - } else { - __raw_writel(htonl(vmeAddr), &dev->uregs->cbal); - __raw_writel(0x00000000, &dev->uregs->cbau); - - ctl = tsi148_eval_vam(vam); - ctl |= 0x00000080; /* enable */ - __raw_writel(htonl(ctl), &dev->uregs->crgat); - } - - return result; -} - -/* - * Tundra Tsi148 configuration - */ -int do_tsi148(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0; - char cmd = 'x'; - - /* get parameter */ - if (argc > 1) - cmd = argv[1][0]; - if (argc > 2) - addr1 = hextoul(argv[2], NULL); - if (argc > 3) - addr2 = hextoul(argv[3], NULL); - if (argc > 4) - size = hextoul(argv[4], NULL); - if (argc > 5) - vam = hextoul(argv[5], NULL); - if (argc > 6) - vdw = hextoul(argv[6], NULL); - - switch (cmd) { - case 'c': - if (strcmp(argv[1], "crg") == 0) { - vam = addr2; - printf("Tsi148: Configuring VME CRG Window " - "(VME->CRG):\n"); - printf(" vme=%08lx vam=%02lx\n", addr1, vam); - tsi148_vme_crg_window(addr1, vam); - } else { - printf("Tsi148: Configuring VME CR/CSR Window " - "(VME->CR/CSR):\n"); - printf(" pci=%08lx\n", addr1); - tsi148_vme_crcsr_window(addr1); - } - break; - case 'i': /* init */ - tsi148_init(); - break; - case 'g': - vam = addr2; - printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n"); - printf(" vme=%08lx vam=%02lx\n", addr1, vam); - tsi148_vme_gcsr_window(addr1, vam); - break; - case 'v': /* vme */ - printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n"); - printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx\n", - addr1, addr2, size, vam); - tsi148_vme_slave_window(addr1, addr2, size, vam); - break; - case 'p': /* pci */ - printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n"); - printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n", - addr1, addr2, size, vam, vdw); - tsi148_pci_slave_window(addr1, addr2, size, vam, vdw); - break; - default: - printf("Tsi148: Command %s not supported!\n", argv[1]); - } - - return 0; -} - -U_BOOT_CMD( - tsi148, 7, 1, do_tsi148, - "initialize and configure Turndra Tsi148\n", - "init\n" - " - initialize tsi148\n" - "tsi148 vme [vme_addr] [pci_addr] [size] [vam]\n" - " - create vme slave window (access: vme->pci)\n" - "tsi148 pci [pci_addr] [vme_addr] [size] [vam] [vdw]\n" - " - create pci slave window (access: pci->vme)\n" - "tsi148 crg [vme_addr] [vam]\n" - " - create vme slave window: (access vme->CRG\n" - "tsi148 crcsr [pci_addr]\n" - " - create vme slave window: (access vme->CR/CSR\n" - "tsi148 gcsr [vme_addr] [vam]\n" - " - create vme slave window: (access vme->GCSR\n" - " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n" - " 02 -> A24 Address Space\n" - " 03 -> A32 Address Space\n" - " 04 -> Usr AM Code\n" - " 08 -> Supervisor AM Code\n" - " 10 -> Data AM Code\n" - " 20 -> Program AM Code\n" - " [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n" - " 03 -> D32 Data Width\n" -); diff --git a/cmd/ufetch.c b/cmd/ufetch.c index 46bd16824e6..bc5db08eee1 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -93,7 +93,7 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, const char *model, *compatible; char *ipaddr; int n_cmds, n_cpus = 0, compatlen; - size_t size; + size_t size = 0; ofnode np; bool skip_ascii = false; diff --git a/cmd/universe.c b/cmd/universe.c deleted file mode 100644 index 1445d5301f2..00000000000 --- a/cmd/universe.c +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com - */ - -#include <command.h> -#include <malloc.h> -#include <vsprintf.h> -#include <asm/io.h> -#include <pci.h> - -#include <universe.h> - -#define PCI_VENDOR PCI_VENDOR_ID_TUNDRA -#define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_CA91C042 - -typedef struct _UNI_DEV UNI_DEV; - -struct _UNI_DEV { - int bus; - pci_dev_t busdevfn; - UNIVERSE *uregs; - unsigned int pci_bs; -}; - -static UNI_DEV *dev; - -int universe_init(void) -{ - int j, result; - pci_dev_t busdevfn; - unsigned int val; - - busdevfn = pci_find_device(PCI_VENDOR, PCI_DEVICE, 0); - if (busdevfn == -1) { - puts("No Tundra Universe found!\n"); - return -1; - } - - /* Lets turn Latency off */ - pci_write_config_dword(busdevfn, 0x0c, 0); - - dev = malloc(sizeof(*dev)); - if (NULL == dev) { - puts("UNIVERSE: No memory!\n"); - result = -1; - goto break_20; - } - - memset(dev, 0, sizeof(*dev)); - dev->busdevfn = busdevfn; - - pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_1, &val); - if (val & 1) { - pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val); - } - val &= ~0xf; - dev->uregs = (UNIVERSE *)val; - - debug ("UNIVERSE-Base : %p\n", dev->uregs); - - /* check mapping */ - debug (" Read via mapping, PCI_ID = %08X\n", readl(&dev->uregs->pci_id)); - if (((PCI_DEVICE <<16) | PCI_VENDOR) != readl(&dev->uregs->pci_id)) { - printf ("UNIVERSE: Cannot read PCI-ID via Mapping: %08x\n", - readl(&dev->uregs->pci_id)); - result = -1; - goto break_30; - } - - debug ("PCI_BS = %08X\n", readl(&dev->uregs->pci_bs)); - - dev->pci_bs = readl(&dev->uregs->pci_bs); - - /* turn off windows */ - for (j=0; j <4; j ++) { - writel(0x00800000, &dev->uregs->lsi[j].ctl); - writel(0x00800000, &dev->uregs->vsi[j].ctl); - } - - /* - * Write to Misc Register - * Set VME Bus Time-out - * Arbitration Mode - * DTACK Enable - */ - writel(0x15040000 | (readl(&dev->uregs->misc_ctl) & 0x00020000), &dev->uregs->misc_ctl); - - if (readl(&dev->uregs->misc_ctl) & 0x00020000) { - debug ("System Controller!\n"); /* test-only */ - } else { - debug ("Not System Controller!\n"); /* test-only */ - } - - /* - * Lets turn off interrupts - */ - writel(0x00000000,&dev->uregs->lint_en); /* Disable interrupts in the Universe first */ - writel(0x0000FFFF,&dev->uregs->lint_stat); /* Clear Any Pending Interrupts */ - eieio(); - writel(0x0000, &dev->uregs->lint_map0); /* Map all ints to 0 */ - writel(0x0000, &dev->uregs->lint_map1); /* Map all ints to 0 */ - eieio(); - - return 0; - - break_30: - free(dev); - break_20: - return result; -} - -/* - * Create pci slave window (access: pci -> vme) - */ -int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int size, int vam, int pms, int vdw) -{ - int result, i; - unsigned int ctl = 0; - - if (NULL == dev) { - result = -1; - goto exit_10; - } - - for (i = 0; i < 4; i++) { - if (0x00800000 == readl(&dev->uregs->lsi[i].ctl)) - break; - } - - if (i == 4) { - printf ("universe: No Image available\n"); - result = -1; - goto exit_10; - } - - debug ("universe: Using image %d\n", i); - - writel(pciAddr , &dev->uregs->lsi[i].bs); - writel((pciAddr + size), &dev->uregs->lsi[i].bd); - writel((vmeAddr - pciAddr), &dev->uregs->lsi[i].to); - - switch (vam & VME_AM_Axx) { - case VME_AM_A16: - ctl = 0x00000000; - break; - case VME_AM_A24: - ctl = 0x00010000; - break; - case VME_AM_A32: - ctl = 0x00020000; - break; - } - - switch (vam & VME_AM_Mxx) { - case VME_AM_DATA: - ctl |= 0x00000000; - break; - case VME_AM_PROG: - ctl |= 0x00008000; - break; - } - - if (vam & VME_AM_SUP) { - ctl |= 0x00001000; - - } - - switch (vdw & VME_FLAG_Dxx) { - case VME_FLAG_D8: - ctl |= 0x00000000; - break; - case VME_FLAG_D16: - ctl |= 0x00400000; - break; - case VME_FLAG_D32: - ctl |= 0x00800000; - break; - } - - switch (pms & PCI_MS_Mxx) { - case PCI_MS_MEM: - ctl |= 0x00000000; - break; - case PCI_MS_IO: - ctl |= 0x00000001; - break; - case PCI_MS_CONFIG: - ctl |= 0x00000002; - break; - } - - ctl |= 0x80000000; /* enable */ - - writel(ctl, &dev->uregs->lsi[i].ctl); - - debug ("universe: window-addr=%p\n", &dev->uregs->lsi[i].ctl); - debug ("universe: pci slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->lsi[i].ctl)); - debug ("universe: pci slave window[%d] bs=%08x\n", i, readl(&dev->uregs->lsi[i].bs)); - debug ("universe: pci slave window[%d] bd=%08x\n", i, readl(&dev->uregs->lsi[i].bd)); - debug ("universe: pci slave window[%d] to=%08x\n", i, readl(&dev->uregs->lsi[i].to)); - - return 0; - - exit_10: - return -result; -} - -/* - * Create vme slave window (access: vme -> pci) - */ -int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int size, int vam, int pms) -{ - int result, i; - unsigned int ctl = 0; - - if (NULL == dev) { - result = -1; - goto exit_10; - } - - for (i = 0; i < 4; i++) { - if (0x00800000 == readl(&dev->uregs->vsi[i].ctl)) - break; - } - - if (i == 4) { - printf ("universe: No Image available\n"); - result = -1; - goto exit_10; - } - - debug ("universe: Using image %d\n", i); - - writel(vmeAddr , &dev->uregs->vsi[i].bs); - writel((vmeAddr + size), &dev->uregs->vsi[i].bd); - writel((pciAddr - vmeAddr), &dev->uregs->vsi[i].to); - - switch (vam & VME_AM_Axx) { - case VME_AM_A16: - ctl = 0x00000000; - break; - case VME_AM_A24: - ctl = 0x00010000; - break; - case VME_AM_A32: - ctl = 0x00020000; - break; - } - - switch (vam & VME_AM_Mxx) { - case VME_AM_DATA: - ctl |= 0x00000000; - break; - case VME_AM_PROG: - ctl |= 0x00800000; - break; - } - - if (vam & VME_AM_SUP) { - ctl |= 0x00100000; - - } - - switch (pms & PCI_MS_Mxx) { - case PCI_MS_MEM: - ctl |= 0x00000000; - break; - case PCI_MS_IO: - ctl |= 0x00000001; - break; - case PCI_MS_CONFIG: - ctl |= 0x00000002; - break; - } - - ctl |= 0x80f00000; /* enable */ - - writel(ctl, &dev->uregs->vsi[i].ctl); - - debug ("universe: window-addr=%p\n", &dev->uregs->vsi[i].ctl); - debug ("universe: vme slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->vsi[i].ctl)); - debug ("universe: vme slave window[%d] bs=%08x\n", i, readl(&dev->uregs->vsi[i].bs)); - debug ("universe: vme slave window[%d] bd=%08x\n", i, readl(&dev->uregs->vsi[i].bd)); - debug ("universe: vme slave window[%d] to=%08x\n", i, readl(&dev->uregs->vsi[i].to)); - - return 0; - - exit_10: - return -result; -} - -/* - * Tundra Universe configuration - */ -int do_universe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, pms = 0, vdw = 0; - char cmd = 'x'; - - /* get parameter */ - if (argc > 1) - cmd = argv[1][0]; - if (argc > 2) - addr1 = hextoul(argv[2], NULL); - if (argc > 3) - addr2 = hextoul(argv[3], NULL); - if (argc > 4) - size = hextoul(argv[4], NULL); - if (argc > 5) - vam = hextoul(argv[5], NULL); - if (argc > 6) - pms = hextoul(argv[6], NULL); - if (argc > 7) - vdw = hextoul(argv[7], NULL); - - switch (cmd) { - case 'i': /* init */ - universe_init(); - break; - case 'v': /* vme */ - printf("Configuring Universe VME Slave Window (VME->PCI):\n"); - printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx pms=%02lx\n", - addr1, addr2, size, vam, pms); - universe_vme_slave_window(addr1, addr2, size, vam, pms); - break; - case 'p': /* pci */ - printf("Configuring Universe PCI Slave Window (PCI->VME):\n"); - printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx pms=%02lx vdw=%02lx\n", - addr1, addr2, size, vam, pms, vdw); - universe_pci_slave_window(addr1, addr2, size, vam, pms, vdw); - break; - default: - printf("Universe command %s not supported!\n", argv[1]); - } - - return 0; -} - -U_BOOT_CMD( - universe, 8, 1, do_universe, - "initialize and configure Turndra Universe", - "init\n" - " - initialize universe\n" - "universe vme [vme_addr] [pci_addr] [size] [vam] [pms]\n" - " - create vme slave window (access: vme->pci)\n" - "universe pci [pci_addr] [vme_addr] [size] [vam] [pms] [vdw]\n" - " - create pci slave window (access: pci->vme)\n" - " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n" - " 02 -> A24 Address Space\n" - " 03 -> A32 Address Space\n" - " 04 -> Supervisor AM Code\n" - " 10 -> Data AM Code\n" - " 20 -> Program AM Code\n" - " [pms] = PCI Memory Space: 01 -> Memory Space\n" - " 02 -> I/O Space\n" - " 03 -> Configuration Space\n" - " [vdw] = VMEbus Maximum Datawidth: 01 -> D8 Data Width\n" - " 02 -> D16 Data Width\n" - " 03 -> D32 Data Width" -); diff --git a/common/Kconfig b/common/Kconfig index 17539079f90..a2f653f7e72 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -704,8 +704,9 @@ config ARCH_EARLY_INIT_R enabled. This can be used to set up architecture-specific devices. config ARCH_MISC_INIT - bool "Call arch-specific init after relocation, when console is ready" + bool help + Call arch-specific init after relocation, when console is ready. With this option U-Boot will call arch_misc_init() after relocation to allow miscellaneous arch-dependent initialisation to be performed. This function should be defined by the board diff --git a/common/autoboot.c b/common/autoboot.c index 0a254498d40..e39f4a32f95 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -410,7 +410,7 @@ static int abortboot_single_key(int bootdelay) udelay(10000); } while (!abort && get_timer(ts) < 1000); - printf("\b\b\b%2d ", bootdelay); + printf("\rHit any key to stop autoboot: %1d\033[K", bootdelay); } putc('\n'); diff --git a/common/log_syslog.c b/common/log_syslog.c index 0dcb5f7cdea..73bd3aca07e 100644 --- a/common/log_syslog.c +++ b/common/log_syslog.c @@ -5,6 +5,7 @@ * Copyright (c) 2020, Heinrich Schuchardt <xypron.glpk@gmx.de> */ +#include <env.h> #include <log.h> #include <net.h> #include <asm/global_data.h> diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 9a17ccb2d3d..f69eff21107 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -132,6 +132,7 @@ config SPL_BSS_START_ADDR choice prompt "Enforce SPL BSS limit" depends on !PPC + default SPL_NO_BSS_LIMIT if COMPILE_TEST default SPL_BSS_LIMIT help In some platforms we only want to enforce a limit on the size of the @@ -1598,7 +1599,7 @@ config SPL_OPENSBI_SCRATCH_OPTIONS config SPL_TARGET string "Addtional build targets for 'make'" default "spl/u-boot-spl.srec" if RCAR_GEN2 - default "spl/u-boot-spl.scif" if RCAR_GEN3 + default "spl/u-boot-spl.scif" if RCAR_64 default "" help On some platforms we need to have 'make' run additional build target diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index f61e701e3c9..05853317fea 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index a184989ea50..099a4828a7f 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_BEAGLEPLAY=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 2c04d32195d..4da668396d0 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 162be534ce4..ba6396c9dfc 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index dfd586b1c14..da0d51a844b 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_CMD_CPU=y @@ -46,6 +47,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y @@ -66,11 +68,11 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y +CONFIG_FSL_CAAM=y CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_MISC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -88,6 +90,7 @@ CONFIG_IMX8_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index de30fa1b961..846c7bde234 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -27,7 +27,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index e9c9cfe940e..57e1eb733a8 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -22,7 +22,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 431987d3f90..6880caf9208 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Colibri iMX8X # " CONFIG_CMD_CPU=y @@ -47,6 +48,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y @@ -67,12 +69,12 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y +CONFIG_FSL_CAAM=y CONFIG_GPIO_HOG=y CONFIG_FXL6408_GPIO=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_MISC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -89,6 +91,7 @@ CONFIG_IMX8_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index c8a17cd40a2..02e33ba5e3c 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -20,7 +20,7 @@ CONFIG_SYS_PBSIZE=1055 CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 8d7a6bf7060..63b695c1e54 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -21,7 +21,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/genmai_defconfig b/configs/genmai_defconfig new file mode 100644 index 00000000000..d3407f671e2 --- /dev/null +++ b/configs/genmai_defconfig @@ -0,0 +1,17 @@ +#include <configs/renesas_rza1.config> + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-genmai" +CONFIG_TARGET_GENMAI=y + +CONFIG_ENV_IS_IN_MTD=y +CONFIG_ENV_MTD_DEV="nor0" +CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_MTD=y +CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 0f141b6f0a2..110af10860b 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -1,69 +1,18 @@ +#include <configs/renesas_rza1.config> + CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x18000000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-gr-peach" -CONFIG_RZA1=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_MONITOR_LEN=524288 -CONFIG_SYS_LOAD_ADDR=0x20400000 -CONFIG_SYS_CLK_FREQ=66666666 -# CONFIG_EFI_LOADER is not set -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="ignore_loglevel" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_BOARD_EARLY_INIT_F is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_ELF is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_USB=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MAC_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y +CONFIG_TARGET_GRPEACH=y + +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_MAX_HZ=50000000 +CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_RZA1_GPIO=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -# CONFIG_MMC is not set +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_BITBANGMII=y -CONFIG_PHY_SMSC=y -CONFIG_DM_ETH_PHY=y -CONFIG_SH_ETHER=y -CONFIG_PINCTRL=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SCIF_CONSOLE=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_RENESAS_RPC_SPI=y -CONFIG_TIMER=y -CONFIG_RENESAS_OSTM_TIMER=y -CONFIG_USB=y -CONFIG_USB_R8A66597_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/imx6ulz_smm_m2b_defconfig b/configs/imx6ulz_smm_m2b_defconfig index c0eb1093d8b..36f5922ea10 100644 --- a/configs/imx6ulz_smm_m2b_defconfig +++ b/configs/imx6ulz_smm_m2b_defconfig @@ -44,6 +44,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX6UL=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_FLASH=y @@ -65,6 +67,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -76,3 +80,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x877fffc0 CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 910a41fa052..92a159e7466 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_A53=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 546cee09575..73517e04d0a 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_R5=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 84cc4cf82d8..b9ba7a677d9 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/renesas_rza1.config b/configs/renesas_rza1.config new file mode 100644 index 00000000000..10d817f03a7 --- /dev/null +++ b/configs/renesas_rza1.config @@ -0,0 +1,55 @@ +CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x400 +# CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_CMD_ELF is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_MMC is not set +CONFIG_BITBANGMII=y +CONFIG_BOOTARGS="ignore_loglevel" +CONFIG_BOOTDELAY=3 +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_USB=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 +CONFIG_DM_ETH_PHY=y +CONFIG_DM_GPIO=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SPI=y +CONFIG_ENV_OVERWRITE=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MAC_PARTITION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PHY_SMSC=y +CONFIG_PINCTRL=y +CONFIG_RENESAS_OSTM_TIMER=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_RZA1=y +CONFIG_RZA1_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SH_ETHER=y +CONFIG_SPI=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_CLK_FREQ=66666666 +CONFIG_SYS_LOAD_ADDR=0x20400000 +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SYS_PBSIZE=256 +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_USB_R8A66597_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USE_BOOTARGS=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 1cefaa0a138..374dcb1d5ba 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -136,6 +136,8 @@ CONFIG_CLK_K210=y CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y +CONFIG_DM_AES=y +CONFIG_AES_SOFTWARE=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index d6768e291d0..2eba02e1f07 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -185,6 +185,8 @@ CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CLK_SCMI=y CONFIG_CPU=y +CONFIG_DM_AES=y +CONFIG_AES_SOFTWARE=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index f0a69a414db..e81941fb14f 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -74,6 +74,7 @@ CONFIG_CMD_QFW=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_AES=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y @@ -114,6 +115,8 @@ CONFIG_CLK_K210=y CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y +CONFIG_DM_AES=y +CONFIG_AES_SOFTWARE=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index 3e7e4264b12..0489f444115 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -154,6 +154,7 @@ CONFIG_DM_REGULATOR_PCA9450=y CONFIG_SPL_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 584c416bd83..e36b55faec1 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_VERDIN_AM62_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -169,6 +170,7 @@ CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -176,6 +178,8 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y @@ -194,3 +198,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_HEXDUMP=y +# CONFIG_OPTEE_LIB is not set diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index c3a2a582f86..5cc7d050c33 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_VERDIN_AM62_R5=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig index 28f48ba773e..7e6132cde53 100644 --- a/configs/verdin-am62p_a53_defconfig +++ b/configs/verdin-am62p_a53_defconfig @@ -169,6 +169,7 @@ CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_RESET_TI_SCI=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -176,6 +177,8 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y @@ -194,3 +197,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_HEXDUMP=y +# CONFIG_OPTEE_LIB is not set diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 7db6e81ee6d..ea085acd28f 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -76,6 +76,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -99,6 +100,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x44200000 CONFIG_FASTBOOT_FLASH=y @@ -108,7 +110,6 @@ CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y @@ -139,6 +140,7 @@ CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y @@ -161,4 +163,5 @@ CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y +# CONFIG_SPL_SHA_HW_ACCEL is not set CONFIG_HEXDUMP=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 4cc69de041b..065520071d1 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -162,6 +162,7 @@ CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/disk/part_dos.c b/disk/part_dos.c index 5c77225cef9..18dd35c9b98 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -421,7 +421,7 @@ int write_mbr_partitions(struct blk_desc *dev, /* write EBR */ if (blk_dwrite(dev, ext_part_sect, 1, buffer) != 1) { - printf("%s: failed writing 'EBR' (1 blks at 0x%lx)\n", + printf("%s: failed writing 'EBR' (1 blks at 0x" LBAF ")\n", __func__, ext_part_sect); return -1; } diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 37235f557a3..2b45f9e5eba 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -18,7 +18,7 @@ config SPL_ADC config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" - depends on ADC + depends on ADC && ARCH_EXYNOS5 help This enables basic driver for Exynos ADC compatible with Exynos54xx. It provides: @@ -49,7 +49,7 @@ config SARADC_MESON config SARADC_ROCKCHIP bool "Enable Rockchip SARADC driver" - depends on ADC + depends on ADC && ARCH_ROCKCHIP help This enables driver for Rockchip SARADC. It provides: diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 29ceab849c0..da9c72a99d0 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -131,6 +131,7 @@ config FSL_SATA_V2 config SATA_MV bool "Enable Marvell SATA controller driver support" + depends on ARCH_KIRKWOOD || ARCH_MVEBU select AHCI select LIBATA help @@ -148,7 +149,7 @@ config SATA_SIL config SYS_SATA_MAX_DEVICE int "Maximum number of SATA devices" - depends on !AHCI || FSL_SATA || SATA_MV + depends on !AHCI || FSL_SATA || SATA_MV || API help Sets the maximum number of SATA devices which can be supported by U-Boot. diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 6c74d66037e..9cb27561a97 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; static unsigned long host_block_read(struct udevice *dev, - unsigned long start, lbaint_t blkcnt, + lbaint_t start, lbaint_t blkcnt, void *buffer) { struct blk_desc *desc = dev_get_uclass_plat(dev); @@ -26,7 +26,7 @@ static unsigned long host_block_read(struct udevice *dev, struct host_sb_plat *plat = dev_get_plat(host_dev); if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { - printf("ERROR: Invalid block %lx\n", start); + printf("ERROR: Invalid block " LBAF "\n", start); return -1; } ssize_t len = os_read(plat->fd, buffer, blkcnt * desc->blksz); @@ -37,7 +37,7 @@ static unsigned long host_block_read(struct udevice *dev, } static unsigned long host_block_write(struct udevice *dev, - unsigned long start, lbaint_t blkcnt, + lbaint_t start, lbaint_t blkcnt, const void *buffer) { struct blk_desc *desc = dev_get_uclass_plat(dev); @@ -45,7 +45,7 @@ static unsigned long host_block_write(struct udevice *dev, struct host_sb_plat *plat = dev_get_plat(host_dev); if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { - printf("ERROR: Invalid block %lx\n", start); + printf("ERROR: Invalid block " LBAF "\n", start); return -1; } ssize_t len = os_write(plat->fd, buffer, blkcnt * desc->blksz); diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 364454644a6..7c49e99c005 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -193,6 +193,7 @@ static const struct gate_clk sm8650_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x39088, BIT(0)), }; static int sm8650_enable(struct clk *clk) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 26e014d5c53..e040e3f2806 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1961,6 +1961,12 @@ int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset, ofnode uboot; *bootscr_flash_offset = 0; + + if (!bootscr_flash_size) { + dm_warn("bootscr-flash-size is zero. Ignoring properties!\n"); + return -EINVAL; + } + *bootscr_flash_size = 0; uboot = ofnode_path("/options/u-boot"); @@ -1979,12 +1985,6 @@ int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset, if (ret) return -EINVAL; - if (!bootscr_flash_size) { - dm_warn("bootscr-flash-size is zero. Ignoring properties!\n"); - *bootscr_flash_offset = 0; - return -EINVAL; - } - return 0; } diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 8b49997030b..d26f87364f9 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -2,6 +2,8 @@ menu "Hardware crypto devices" source "drivers/crypto/hash/Kconfig" +source "drivers/crypto/aes/Kconfig" + source "drivers/crypto/fsl/Kconfig" source "drivers/crypto/aspeed/Kconfig" diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index b9105186097..2bd99fc2763 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -4,6 +4,7 @@ # http://www.samsung.com obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-y += aes/ obj-y += rsa_mod_exp/ obj-y += fsl/ obj-y += hash/ diff --git a/drivers/crypto/aes/Kconfig b/drivers/crypto/aes/Kconfig new file mode 100644 index 00000000000..7e1b1b2875d --- /dev/null +++ b/drivers/crypto/aes/Kconfig @@ -0,0 +1,12 @@ +config DM_AES + bool "Enable Driver Model for AES crypto operations" + depends on DM + help + If you want to use driver model for AES crypto operations, say Y. + +config AES_SOFTWARE + bool "Enable driver for AES in software" + depends on DM_AES && AES + help + Enable driver for AES crypto operations in software. Uses U-Boot + AES library. diff --git a/drivers/crypto/aes/Makefile b/drivers/crypto/aes/Makefile new file mode 100644 index 00000000000..d38a2e1526d --- /dev/null +++ b/drivers/crypto/aes/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_$(PHASE_)DM_AES) += aes-uclass.o +obj-$(CONFIG_$(PHASE_)AES_SOFTWARE) += aes-sw.o diff --git a/drivers/crypto/aes/aes-sw.c b/drivers/crypto/aes/aes-sw.c new file mode 100644 index 00000000000..a65200fb79b --- /dev/null +++ b/drivers/crypto/aes/aes-sw.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <config.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <uboot_aes.h> + +#define SW_KEY_SLOTS 2 + +struct sw_aes_priv { + u8 key_slots[SW_KEY_SLOTS][AES256_KEY_LENGTH]; + u8 key_schedule[AES256_EXPAND_KEY_LENGTH]; + u8 selected_slot; + u32 selected_key_size; + bool key_expanded; +}; + +static int prepare_aes(struct sw_aes_priv *priv) +{ + if (!priv->selected_key_size) { + log_debug("%s: AES key size not set, setup a slot first\n", __func__); + return 1; + } + + if (priv->key_expanded) + return 0; + + priv->key_expanded = 1; + + aes_expand_key(priv->key_slots[priv->selected_slot], priv->selected_key_size, + priv->key_schedule); + + return 0; +} + +static int sw_aes_ops_available_key_slots(struct udevice *dev) +{ + return SW_KEY_SLOTS; +} + +static int sw_aes_ops_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + + if (slot >= SW_KEY_SLOTS) + return 1; + + priv->selected_slot = slot; + priv->selected_key_size = key_size; + priv->key_expanded = 0; + + return 0; +} + +static int sw_aes_ops_set_key_for_key_slot(struct udevice *dev, u32 key_size, + u8 *key, u8 slot) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + + if (slot >= SW_KEY_SLOTS) + return 1; + + memcpy(priv->key_slots[slot], key, key_size / 8); + + if (priv->selected_slot == slot) + priv->selected_key_size = key_size; + + priv->key_expanded = 0; + + return 0; +} + +static int sw_aes_ops_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + while (num_aes_blocks > 0) { + aes_encrypt(priv->selected_key_size, src, priv->key_schedule, dst); + num_aes_blocks -= 1; + src += AES_BLOCK_LENGTH; + dst += AES_BLOCK_LENGTH; + } + + return 0; +} + +static int sw_aes_ops_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + while (num_aes_blocks > 0) { + aes_decrypt(priv->selected_key_size, src, priv->key_schedule, dst); + num_aes_blocks -= 1; + src += AES_BLOCK_LENGTH; + dst += AES_BLOCK_LENGTH; + } + + return 0; +} + +static int sw_aes_ops_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + aes_cbc_encrypt_blocks(priv->selected_key_size, priv->key_schedule, iv, + src, dst, num_aes_blocks); + + return 0; +} + +static int sw_aes_ops_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + aes_cbc_decrypt_blocks(priv->selected_key_size, priv->key_schedule, + iv, src, dst, num_aes_blocks); + + return 0; +} + +static const struct aes_ops aes_ops_sw = { + .available_key_slots = sw_aes_ops_available_key_slots, + .select_key_slot = sw_aes_ops_select_key_slot, + .set_key_for_key_slot = sw_aes_ops_set_key_for_key_slot, + .aes_ecb_encrypt = sw_aes_ops_aes_ecb_encrypt, + .aes_ecb_decrypt = sw_aes_ops_aes_ecb_decrypt, + .aes_cbc_encrypt = sw_aes_ops_aes_cbc_encrypt, + .aes_cbc_decrypt = sw_aes_ops_aes_cbc_decrypt, +}; + +static const struct udevice_id sw_aes_ids[] = { + { .compatible = "software-aes-engine" }, + { } +}; + +U_BOOT_DRIVER(aes_sw) = { + .name = "aes_sw", + .id = UCLASS_AES, + .of_match = sw_aes_ids, + .ops = &aes_ops_sw, + .priv_auto = sizeof(struct sw_aes_priv), +}; diff --git a/drivers/crypto/aes/aes-uclass.c b/drivers/crypto/aes/aes-uclass.c new file mode 100644 index 00000000000..745c6ce57a9 --- /dev/null +++ b/drivers/crypto/aes/aes-uclass.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY UCLASS_AES + +#include <dm.h> +#include <malloc.h> +#include <log.h> +#include <uboot_aes.h> +#include <linux/string.h> + +int dm_aes_get_available_key_slots(struct udevice *dev) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->available_key_slots) + return -ENOSYS; + + return ops->available_key_slots(dev); +} + +int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->select_key_slot) + return -ENOSYS; + + return ops->select_key_slot(dev, key_size, slot); +} + +int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, u8 slot) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->set_key_for_key_slot) + return -ENOSYS; + + return ops->set_key_for_key_slot(dev, key_size, key, slot); +} + +int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_ecb_encrypt) + return -ENOSYS; + + return ops->aes_ecb_encrypt(dev, src, dst, num_aes_blocks); +} + +int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_ecb_decrypt) + return -ENOSYS; + + return ops->aes_ecb_decrypt(dev, src, dst, num_aes_blocks); +} + +int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_cbc_encrypt) + return -ENOSYS; + + return ops->aes_cbc_encrypt(dev, iv, src, dst, num_aes_blocks); +} + +int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_cbc_decrypt) + return -ENOSYS; + + return ops->aes_cbc_decrypt(dev, iv, src, dst, num_aes_blocks); +} + +static void left_shift_vector(u8 *in, u8 *out, int size) +{ + int carry = 0; + int i; + + for (i = size - 1; i >= 0; i--) { + out[i] = (in[i] << 1) | carry; + carry = in[i] >> 7; /* get most significant bit */ + } +} + +int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const u8 AES_CMAC_CONST_RB = 0x87; /* from RFC 4493, Figure 2.2 */ + const u32 TMP_BUFFER_LEN = 128; + u8 tmp_block[AES128_KEY_LENGTH] = { }; + u8 k1[AES128_KEY_LENGTH]; + u8 *tmp_buffer; + int ret; + + log_debug("%s: 0x%p -> %p blocks %d\n", __func__, src, dst, num_aes_blocks); + + if (!num_aes_blocks) { + log_debug("%s: called with 0 blocks!\n", __func__); + return -1; + } + + /* Compute K1 constant needed by AES-CMAC calculation */ + ret = dm_aes_cbc_encrypt(dev, (u8 *)AES_ZERO_BLOCK, (u8 *)AES_ZERO_BLOCK, tmp_block, 1); + if (ret) + return -1; + + left_shift_vector(tmp_block, k1, AES_BLOCK_LENGTH); + + if ((tmp_block[0] >> 7) != 0) /* get MSB of L */ + k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB; + + /* Set what will be the initial IV as zero */ + memset(tmp_block, 0, AES_BLOCK_LENGTH); + + /* Process all blocks except last by calling engine several times per dma buffer size */ + if (num_aes_blocks > 1) { + tmp_buffer = malloc(AES_BLOCK_LENGTH * min(num_aes_blocks - 1, TMP_BUFFER_LEN)); + while (num_aes_blocks > 1) { + u32 blocks = min(num_aes_blocks - 1, TMP_BUFFER_LEN); + + /* Encrypt the current remaining set of blocks that fits in tmp buffer */ + ret = dm_aes_cbc_encrypt(dev, tmp_block, src, tmp_buffer, blocks); + if (ret) + return -1; + + num_aes_blocks -= blocks; + src += blocks * AES_BLOCK_LENGTH; + + /* Copy the last encrypted block to tmp_block as IV */ + memcpy(tmp_block, tmp_buffer + ((blocks - 1) * AES_BLOCK_LENGTH), + AES_BLOCK_LENGTH); + } + free(tmp_buffer); + } + + if (num_aes_blocks != 1) { + log_debug("%s: left with %d blocks! must be 1\n", __func__, num_aes_blocks); + return -1; + } + + /* XOR last IV with K1 */ + aes_apply_cbc_chain_data(tmp_block, k1, tmp_block); + + /* Encrypt the last src block already with tmp_block as IV and output to dst */ + return dm_aes_cbc_encrypt(dev, tmp_block, src, dst, 1); +} + +UCLASS_DRIVER(aes) = { + .id = UCLASS_AES, + .name = "aes", +}; diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 6efcd7da738..401225b8528 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -1,3 +1,5 @@ +if ARCH_ASPEED + config ASPEED_HACE bool "ASPEED Hash and Crypto Engine" depends on DM_HASH @@ -38,3 +40,5 @@ config ASPEED_CPTRA_ECDSA Enabling this allows the use of ECDSA384 signature verification in hardware. Note that only ECDSA384 is supported by Caliptra. + +endif diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 9ed56632fcd..fe694f6022c 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -1,3 +1,5 @@ +if ARM || PPC + config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL @@ -95,3 +97,5 @@ config FSL_DCP_RNG module of the DCP. It uses the True Random Number Generator (TRNG) and a Pseudo-Random Number Generator (PRNG) to achieve a true randomness and cryptographic strength. + +endif diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig index aa355c44be8..72b955ac791 100644 --- a/drivers/crypto/hash/Kconfig +++ b/drivers/crypto/hash/Kconfig @@ -18,7 +18,7 @@ config HASH_SOFTWARE config HASH_ASPEED bool "Enable Hash with ASPEED hash accelerator" - depends on DM_HASH + depends on DM_HASH && ARCH_ASPEED select ASPEED_HACE help Enable this to support HW-assisted hashing operations using ASPEED Hash diff --git a/drivers/crypto/nuvoton/Kconfig b/drivers/crypto/nuvoton/Kconfig index 034fcadfcc8..0eb4396816e 100644 --- a/drivers/crypto/nuvoton/Kconfig +++ b/drivers/crypto/nuvoton/Kconfig @@ -1,5 +1,6 @@ config NPCM_AES bool "Support the NPCM AES algorithm" + depends on (ARM && ARCH_NPCM) select NPCM_OTP help This provides a means to encrypt and decrypt data using the NPCM diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 4b47be6b016..1fccbc96f07 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -35,18 +35,9 @@ config BCM6348_IUDMA This driver support data transfer from devices to memory and from memory to devices. -config DMA_LPC32XX - bool "LPC32XX DMA driver" - select DMA_LEGACY - help - Enable some legacy DMA code for lpc32xx. It provides some direct - functions likes lpc32xx_dma_wait_status() which can be called from - other code. - - This should be converted to use driver model and UCLASS_DMA. - config TI_EDMA3 bool "TI EDMA3 driver" + depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE select DMA_LEGACY help Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 00d765864cd..fde26c2a886 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_FSL_DMA) += fsl_dma.o obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o -obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o obj-$(CONFIG_XILINX_DPDMA) += xilinx_dpdma.o obj-$(CONFIG_ADI_DMA) += adi_dma.o diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c deleted file mode 100644 index f15b67546a9..00000000000 --- a/drivers/dma/lpc32xx_dma.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 by NXP Semiconductors - * @Author: Kevin Wells - * @Descr: LPC3250 DMA controller interface support functions - * - * Copyright (c) 2015 Tyco Fire Protection Products. - */ - -#include <errno.h> -#include <init.h> -#include <time.h> -#include <asm/arch/dma.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clk.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/printk.h> - -/* DMA controller channel register structure */ -struct dmac_chan_reg { - u32 src_addr; - u32 dest_addr; - u32 lli; - u32 control; - u32 config_ch; - u32 reserved[3]; -}; - -/* DMA controller register structures */ -struct dma_reg { - u32 int_stat; - u32 int_tc_stat; - u32 int_tc_clear; - u32 int_err_stat; - u32 int_err_clear; - u32 raw_tc_stat; - u32 raw_err_stat; - u32 chan_enable; - u32 sw_burst_req; - u32 sw_single_req; - u32 sw_last_burst_req; - u32 sw_last_single_req; - u32 config; - u32 sync; - u32 reserved[50]; - struct dmac_chan_reg dma_chan[8]; -}; - -#define DMA_NO_OF_CHANNELS 8 - -/* config register definitions */ -#define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */ - -static u32 alloc_ch; - -static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; - -int lpc32xx_dma_get_channel(void) -{ - int i; - - if (!alloc_ch) { /* First time caller */ - /* - * DMA clock are enable by "lpc32xx_dma_init()" and should - * be call by board "board_early_init_f()" function. - */ - - /* - * Make sure DMA controller and all channels are disabled. - * Controller is in little-endian mode. Disable sync signals. - */ - writel(0, &dma->config); - writel(0, &dma->sync); - - /* Clear interrupt and error statuses */ - writel(0xFF, &dma->int_tc_clear); - writel(0xFF, &dma->raw_tc_stat); - writel(0xFF, &dma->int_err_clear); - writel(0xFF, &dma->raw_err_stat); - - /* Enable DMA controller */ - writel(DMAC_CTRL_ENABLE, &dma->config); - } - - i = ffz(alloc_ch); - - /* Check if all the available channels are busy */ - if (unlikely(i == DMA_NO_OF_CHANNELS)) - return -1; - alloc_ch |= BIT_MASK(i); - return i; -} - -int lpc32xx_dma_start_xfer(unsigned int channel, - const struct lpc32xx_dmac_ll *desc, u32 config) -{ - if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) || - (channel >= DMA_NO_OF_CHANNELS))) { - pr_err("Request for xfer on unallocated channel %d", channel); - return -1; - } - writel(BIT_MASK(channel), &dma->int_tc_clear); - writel(BIT_MASK(channel), &dma->int_err_clear); - writel(desc->dma_src, &dma->dma_chan[channel].src_addr); - writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr); - writel(desc->next_lli, &dma->dma_chan[channel].lli); - writel(desc->next_ctrl, &dma->dma_chan[channel].control); - writel(config, &dma->dma_chan[channel].config_ch); - - return 0; -} - -int lpc32xx_dma_wait_status(unsigned int channel) -{ - unsigned long start; - u32 reg; - - /* Check if given channel is valid */ - if (unlikely(channel >= DMA_NO_OF_CHANNELS)) { - pr_err("Request for status on unallocated channel %d", channel); - return -1; - } - - start = get_timer(0); - while (1) { - reg = readl(&dma->raw_tc_stat); - reg |= readl(dma->raw_err_stat); - if (reg & BIT_MASK(channel)) - break; - - if (get_timer(start) > CONFIG_SYS_HZ) { - pr_err("DMA status timeout channel %d\n", channel); - return -ETIMEDOUT; - } - udelay(1); - } - - if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) { - setbits_le32(&dma->int_err_clear, BIT_MASK(channel)); - setbits_le32(&dma->raw_err_stat, BIT_MASK(channel)); - pr_err("DMA error on channel %d\n", channel); - return -1; - } - setbits_le32(&dma->int_tc_clear, BIT_MASK(channel)); - setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel)); - return 0; -} diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e11109fb56d..c7da1f8a52a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -88,7 +88,7 @@ config DM_GPIO_LOOKUP_LABEL for the same functionality in board code. config SPL_DM_GPIO_LOOKUP_LABEL - bool "Enable searching for gpio labelnames" + bool "Enable searching for gpio labelnames in SPL" depends on SPL_DM_GPIO help This option enables searching for gpio names in @@ -115,7 +115,7 @@ config ALTERA_PIO config BCM2835_GPIO bool "BCM2835 GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_BCM283X config BCM6345_GPIO bool "BCM6345 GPIO driver" @@ -140,6 +140,7 @@ config DWAPB_GPIO config AT91_GPIO bool "AT91 PIO GPIO driver" + depends on ARCH_AT91 help Say yes here to select AT91 PIO GPIO driver. AT91 PIO controller manages up to 32 fully programmable input/output @@ -151,7 +152,7 @@ config AT91_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_AT91 help Say yes here to support the Atmel PIO4 driver. The PIO4 is new version of Atmel PIO controller, which manages @@ -194,11 +195,11 @@ config FXL6408_GPIO config HIKEY_GPIO bool "HI6220 GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && TARGET_HIKEY config INTEL_BROADWELL_GPIO bool "Intel Broadwell GPIO driver" - depends on DM + depends on DM_GPIO && X86 help This driver supports Broadwell U devices which have an expanded GPIO feature set. The difference is large enough to merit a separate @@ -207,7 +208,7 @@ config INTEL_BROADWELL_GPIO config INTEL_GPIO bool "Intel generic GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && X86 help Say yes here to select Intel generic GPIO driver. This controller supports recent chips (e.g. Apollo Lake). It permits basic GPIO @@ -216,13 +217,13 @@ config INTEL_GPIO config INTEL_ICH6_GPIO bool "Intel ICH6 compatible legacy GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && X86 help Say yes here to select Intel ICH6 compatible legacy GPIO driver. config IMX_RGPIO2P bool "i.MX7ULP RGPIO2P driver" - depends on DM + depends on DM && (ARCH_MX7ULP || ARCH_IMX8ULP || ARCH_IMX9) help This driver supports i.MX7ULP Rapid GPIO2P controller. @@ -244,12 +245,13 @@ config HSDK_CREG_GPIO config KIRKWOOD_GPIO bool "Kirkwood GPIO driver" + depends on ARCH_KIRKWOOD help This drdiver supports GPIOs on Kirkwood platforms config LPC32XX_GPIO bool "LPC32XX GPIO driver" - depends on DM + depends on DM && ARCH_LPC32XX help Support for the LPC32XX GPIO driver. @@ -296,7 +298,7 @@ config MSCC_SGPIO config MSM_GPIO bool "Qualcomm GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_SNAPDRAGON help Support GPIO controllers on Qualcomm Snapdragon family of SoCs. This controller have single bank (default name "soc"), every @@ -309,24 +311,26 @@ config MSM_GPIO config MXC_GPIO bool "Freescale/NXP MXC GPIO driver" + depends on MACH_IMX help Support GPIO controllers on various i.MX platforms config MXS_GPIO bool "Freescale/NXP MXS GPIO driver" + depends on ARCH_MX23 || ARCH_MX28 help Support GPIO controllers on i.MX23 and i.MX28 platforms config NPCM_GPIO bool "Nuvoton NPCM GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_NPCM help Support GPIO controllers on Nuvovon NPCM SoCs. NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins. config NPCM_SGPIO bool "Nuvoton NPCM SGPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_NPCM help Support Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver support. Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595) @@ -380,7 +384,7 @@ config RZA1_GPIO config ROCKCHIP_GPIO bool "Rockchip GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_ROCKCHIP help Support GPIO access on Rockchip SoCs. The GPIOs are arranged into a number of banks (different for each SoC type) each with 32 GPIOs. @@ -428,23 +432,9 @@ config XILINX_GPIO help This config enable the Xilinx GPIO driver for Microblaze. -config TCA642X - bool "TCA642x legacy GPIO driver" - -config CMD_TCA642X - bool "tca642x - Command to access tca642x state" - depends on TCA642X - default y - help - DEPRECATED - This needs conversion to driver model - - This provides a way to looking at the pin state of this device. - This mirrors the 'gpio' command and that should be used in preference - to custom code. - config TEGRA_GPIO bool "Tegra20..210 GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_TEGRA help Support for the GPIO controller contained in NVIDIA Tegra20 through Tegra210. @@ -465,7 +455,7 @@ config GPIO_UNIPHIER config VYBRID_GPIO bool "Vybrid GPIO driver" - depends on DM + depends on DM && MACH_IMX help Say yes here to support Vybrid vf610 GPIOs. @@ -504,7 +494,7 @@ config STM32_GPIO config SIFIVE_GPIO bool "SiFive GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && RISCV help Device model driver for GPIO controller present in SiFive FU540 SoC. This driver enables GPIO interface on HiFive Unleashed A00 board. @@ -591,7 +581,7 @@ config PCA953X config MPC8XXX_GPIO bool "Freescale MPC8XXX GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) help This driver supports the built-in GPIO controller of MPC8XXX CPUs. Each GPIO bank is identified by its own entry in the device tree, @@ -632,7 +622,7 @@ config QE_GPIO config MPC8XX_GPIO bool "Freescale MPC8XX GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && PPC help This driver supports parallel IO ports from MPC8XX CPUs. Each GPIO bank is identified by its own entry in the device tree. @@ -699,7 +689,7 @@ config SL28CPLD_GPIO config SLG7XL45106_I2C_GPO bool "slg7xl45106 i2c gpo expander" - depends on DM_GPIO + depends on DM_GPIO && ARCH_ZYNQMP help Support for slg7xl45106 i2c gpo expander. It is an i2c based 8-bit gpo expander, all gpo lines are controlled by writing diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d64c14db5cf..a5ef1c9e0d8 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o -obj-$(CONFIG_TCA642X) += tca642x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o @@ -65,7 +64,7 @@ obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(PHASE_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o +obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o qcom_spmi_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index cd9f3926ac4..4458c55cd3d 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -69,17 +69,6 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) -/** - * pmic_gpio_match_data - platform specific configuration - * - * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. - * This is a workaround for an unknown bug on some platforms where trying to write the - * GPIO configuration registers causes the board to hang. - */ -enum pmic_gpio_quirks { - QCOM_PMIC_QUIRK_READONLY = (1 << 0), -}; - struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ @@ -128,13 +117,8 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); uint32_t gpio_base = plat->pid + REG_OFFSET(offset); - ulong quirks = dev_get_driver_data(dev); int ret = 0; - /* Some PMICs don't like their GPIOs being configured */ - if (quirks & QCOM_PMIC_QUIRK_READONLY) - return 0; - /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, REG_EN_CTL_ENABLE, 0); @@ -278,7 +262,6 @@ static int qcom_gpio_bind(struct udevice *dev) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); - ulong quirks = dev_get_driver_data(dev); struct udevice *child; struct driver *drv; int ret; @@ -292,7 +275,7 @@ static int qcom_gpio_bind(struct udevice *dev) /* Bind the GPIO driver as a child of the PMIC. */ ret = device_bind_with_driver_data(dev, drv, dev->name, - quirks, dev_ofnode(dev), &child); + 0, dev_ofnode(dev), &child); if (ret) return log_msg_ret("bind", ret); @@ -365,7 +348,6 @@ static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pms405-gpio" }, { .compatible = "qcom,pm6125-gpio" }, { .compatible = "qcom,pm8150-gpio" }, - { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, { } }; diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c new file mode 100644 index 00000000000..22c8072534e --- /dev/null +++ b/drivers/gpio/qcom_spmi_gpio.c @@ -0,0 +1,1035 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm generic pmic gpio driver + * + * Based on the original qcom_spmi_pmic_gpio driver from: + * Copyright (c) 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + * + * Updated from the Linux pinctrl-spmi-gpio driver from: + * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <dm/device_compat.h> +#include <log.h> +#include <power/pmic.h> +#include <spmi/spmi.h> +#include <asm/io.h> +#include <stdlib.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +#define PMIC_MAX_GPIOS 36 + +#define PMIC_GPIO_ADDRESS_RANGE 0x100 + +/* type and subtype registers base address offsets */ +#define PMIC_GPIO_REG_TYPE 0x4 +#define PMIC_GPIO_REG_SUBTYPE 0x5 + +/* GPIO peripheral type and subtype out_values */ +#define PMIC_GPIO_TYPE 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 +#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 +#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 +#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd +#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 +#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12 +#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13 + +#define PMIC_MPP_REG_RT_STS 0x10 +#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 + +/* control register base address offsets */ +#define PMIC_GPIO_REG_MODE_CTL 0x40 +#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 +#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 +#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 + #define PMIC_GPIO_REG_DIG_IN_CTL 0x43 +#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 +#define PMIC_GPIO_REG_EN_CTL 0x46 + #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A + +/* PMIC_GPIO_REG_MODE_CTL */ +#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 +#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 +#define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 +#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 +#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 + +#define PMIC_GPIO_MODE_DIGITAL_INPUT 0 +#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 +#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 +#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 +#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 + +/* PMIC_GPIO_REG_DIG_VIN_CTL */ +#define PMIC_GPIO_REG_VIN_SHIFT 0 +#define PMIC_GPIO_REG_VIN_MASK 0x7 + +/* PMIC_GPIO_REG_DIG_PULL_CTL */ +#define PMIC_GPIO_REG_PULL_SHIFT 0 +#define PMIC_GPIO_REG_PULL_MASK 0x7 + +#define PMIC_GPIO_PULL_DOWN 4 +#define PMIC_GPIO_PULL_DISABLE 5 + +/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 +#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF + +/* PMIC_GPIO_REG_DIG_IN_CTL */ +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 +#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf + +/* PMIC_GPIO_REG_DIG_OUT_CTL */ +#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 +#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 +#define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 +#define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 + +/* + * Output type - indicates pin should be configured as push-pull, + * open drain or open source. + */ +#define PMIC_GPIO_OUT_BUF_CMOS 0 +#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 +#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 + +#define PMIC_GPIO_OUT_STRENGTH_LOW 1 +#define PMIC_GPIO_OUT_STRENGTH_HIGH 3 + +/* PMIC_GPIO_REG_EN_CTL */ +#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 + +#define PMIC_GPIO_PHYSICAL_OFFSET 1 + +/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ +#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 + +/* The index of each function in spmi_pmic_gpio_functions[] array */ +enum spmi_pmic_gpio_func_index { + PMIC_GPIO_FUNC_INDEX_NORMAL, + PMIC_GPIO_FUNC_INDEX_PAIRED, + PMIC_GPIO_FUNC_INDEX_FUNC1, + PMIC_GPIO_FUNC_INDEX_FUNC2, + PMIC_GPIO_FUNC_INDEX_FUNC3, + PMIC_GPIO_FUNC_INDEX_FUNC4, + PMIC_GPIO_FUNC_INDEX_DTEST1, + PMIC_GPIO_FUNC_INDEX_DTEST2, + PMIC_GPIO_FUNC_INDEX_DTEST3, + PMIC_GPIO_FUNC_INDEX_DTEST4, +}; + +static const char *const spmi_pmic_gpio_functions[] = { + [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, + [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, + [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, + [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, + [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, + [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, + [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, + [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, + [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, + [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, +}; + +/** + * struct spmi_pmic_gpio_pad - keep current GPIO settings + * @base: Address base in SPMI device. + * @is_enabled: Set to false when GPIO should be put in high Z state. + * @out_value: Cached pin output value + * @have_buffer: Set to true if GPIO output could be configured in push-pull, + * open-drain or open-source mode. + * @output_enabled: Set to true if GPIO output logic is enabled. + * @input_enabled: Set to true if GPIO input buffer logic is enabled. + * @analog_pass: Set to true if GPIO is in analog-pass-through mode. + * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). + * @num_sources: Number of power-sources supported by this GPIO. + * @power_source: Current power-source used. + * @buffer_type: Push-pull, open-drain or open-source. + * @pullup: Constant current which flow trough GPIO output buffer. + * @strength: No, Low, Medium, High + * @function: See spmi_pmic_gpio_functions[] + * @atest: the ATEST selection for GPIO analog-pass-through mode + * @dtest_buffer: the DTEST buffer selection for digital input mode. + */ +struct spmi_pmic_gpio_pad { + u16 base; + bool is_enabled; + bool out_value; + bool have_buffer; + bool output_enabled; + bool input_enabled; + bool analog_pass; + bool lv_mv_type; + unsigned int num_sources; + unsigned int power_source; + unsigned int buffer_type; + unsigned int pullup; + unsigned int strength; + unsigned int function; + unsigned int atest; + unsigned int dtest_buffer; +}; + +struct qcom_spmi_pmic_gpio_data { + struct udevice *dev; + u32 pid; /* Peripheral ID on SPMI bus */ + struct udevice *pmic; /* Reference to pmic device for read/write */ + u32 pin_count; + struct spmi_pmic_gpio_pad *pads; +}; + +static int qcom_spmi_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector, + unsigned int param, unsigned int arg); + +static int spmi_pmic_gpio_read(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad, + unsigned int addr) +{ + return pmic_reg_read(plat->pmic, pad->base + addr); +} + +static int spmi_pmic_gpio_write(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad, + unsigned int addr, unsigned int val) +{ + return pmic_reg_write(plat->pmic, pad->base + addr, val); +} + +static void spmi_pmic_gpio_get_state(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad, + char *buf, int size) +{ + int ret, val, function, cnt; + + static const char *const biases[] = { + "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", + "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" + }; + static const char *const buffer_types[] = { + "push-pull", "open-drain", "open-source" + }; + static const char *const strengths[] = { + "no", "low", "medium", "high" + }; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_EN_CTL); + + if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { + cnt = snprintf(buf, size, "disabled"); + } else { + if (pad->input_enabled) { + ret = spmi_pmic_gpio_read(plat, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return; + + ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; + pad->out_value = ret; + } + /* + * For the non-LV/MV subtypes only 2 special functions are + * available, offsetting the dtest function values by 2. + */ + function = pad->function; + if (!pad->lv_mv_type && + pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) + function += PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3; + + if (pad->analog_pass) + cnt = snprintf(buf, size, "analog-pass"); + else + cnt = snprintf(buf, size, "%-4s", + pad->output_enabled ? "out" : "in"); + buf += cnt; + size -= cnt; + + snprintf(buf, size, " %-4s %-7s vin-%d %-27s %-10s %-7s atest-%d dtest-%d", + pad->out_value ? "high" : "low", + spmi_pmic_gpio_functions[function], + pad->power_source, + biases[pad->pullup], + buffer_types[pad->buffer_type], + strengths[pad->strength], + pad->atest, + pad->dtest_buffer); + } +} + +static int qcom_spmi_pmic_gpio_set(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad) +{ + unsigned int val; + int ret; + + val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); + if (ret < 0) + return ret; + + val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); + if (ret < 0) + return ret; + + val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; + val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); + if (ret < 0) + return ret; + + if (pad->dtest_buffer == 0) { + val = 0; + } else { + if (pad->lv_mv_type) { + val = pad->dtest_buffer - 1; + val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; + } else { + val = BIT(pad->dtest_buffer - 1); + } + } + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); + if (ret < 0) + return ret; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; + + if (pad->lv_mv_type) { + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->atest - 1; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, + val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, + val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); + if (ret) + return ret; + + return 0; +} + +static int spmi_pmic_gpio_populate(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad) +{ + int type, subtype, val, dir; + + type = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_TYPE); + if (type < 0) + return type; + + if (type != PMIC_GPIO_TYPE) { + dev_err(plat->dev, "incorrect block type 0x%x at 0x%x\n", + type, pad->base); + return -ENODEV; + } + + subtype = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_SUBTYPE); + if (subtype < 0) + return subtype; + + switch (subtype) { + case PMIC_GPIO_SUBTYPE_GPIO_4CH: + pad->have_buffer = true; + fallthrough; + case PMIC_GPIO_SUBTYPE_GPIOC_4CH: + pad->num_sources = 4; + break; + case PMIC_GPIO_SUBTYPE_GPIO_8CH: + pad->have_buffer = true; + fallthrough; + case PMIC_GPIO_SUBTYPE_GPIOC_8CH: + pad->num_sources = 8; + break; + case PMIC_GPIO_SUBTYPE_GPIO_LV: + pad->num_sources = 1; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3: + pad->num_sources = 3; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + default: + dev_err(plat->dev, "unknown GPIO type 0x%x\n", subtype); + return -ENODEV; + } + + if (pad->lv_mv_type) { + val = spmi_pmic_gpio_read(plat, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); + if (val < 0) + return val; + + pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); + pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; + } else { + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; + dir &= PMIC_GPIO_REG_MODE_DIR_MASK; + pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; + } + + switch (dir) { + case PMIC_GPIO_MODE_DIGITAL_INPUT: + pad->input_enabled = true; + pad->output_enabled = false; + break; + case PMIC_GPIO_MODE_DIGITAL_OUTPUT: + pad->input_enabled = false; + pad->output_enabled = true; + break; + case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: + pad->input_enabled = true; + pad->output_enabled = true; + break; + case PMIC_GPIO_MODE_ANALOG_PASS_THRU: + if (!pad->lv_mv_type) + return -ENODEV; + pad->analog_pass = true; + break; + default: + dev_err(plat->dev, "unknown GPIO direction\n"); + return -ENODEV; + } + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_VIN_CTL); + if (val < 0) + return val; + + pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; + pad->power_source &= PMIC_GPIO_REG_VIN_MASK; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_PULL_CTL); + if (val < 0) + return val; + + pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; + pad->pullup &= PMIC_GPIO_REG_PULL_MASK; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_IN_CTL); + if (val < 0) + return val; + + if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) + pad->dtest_buffer = + (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; + else if (!pad->lv_mv_type) + pad->dtest_buffer = ffs(val); + else + pad->dtest_buffer = 0; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_OUT_CTL); + if (val < 0) + return val; + + pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; + pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; + + pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; + pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; + + if (pad->lv_mv_type) { + val = spmi_pmic_gpio_read(plat, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); + if (val < 0) + return val; + + pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; + } + + /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ + pad->is_enabled = true; + return 0; +} + +static int qcom_spmi_pmic_gpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + + if (offset >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[offset]; + + pad->input_enabled = flags & GPIOD_IS_IN; + pad->output_enabled = flags & GPIOD_IS_OUT; + + if (pad->output_enabled) { + pad->out_value = flags & GPIOD_IS_OUT_ACTIVE; + + if ((flags & GPIOD_OPEN_DRAIN) && pad->have_buffer) + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; + else if ((flags & GPIOD_OPEN_SOURCE) && pad->have_buffer) + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; + else + pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; + } + + if (flags & GPIOD_PULL_UP) + pad->pullup = PMIC_GPIO_PULL_UP_30; + else if (flags & GPIOD_PULL_DOWN) + pad->pullup = PMIC_GPIO_PULL_DOWN; + + return qcom_spmi_pmic_gpio_set(plat, pad); +} + +static int qcom_spmi_pmic_gpio_get_flags(struct udevice *dev, unsigned int offset, + ulong *flagsp) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + ulong flags = 0; + + if (offset >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[offset]; + + if (pad->input_enabled) + flags |= GPIOD_IS_IN; + + if (pad->output_enabled) { + flags |= GPIOD_IS_OUT; + + if (pad->out_value) + flags |= GPIOD_IS_OUT_ACTIVE; + + switch (pad->buffer_type) { + case PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS: + flags |= GPIOD_OPEN_DRAIN; + break; + case PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS: + flags |= GPIOD_OPEN_SOURCE; + break; + } + } + + if (pad->pullup == PMIC_GPIO_PULL_DOWN) + flags |= GPIOD_PULL_DOWN; + else if (pad->pullup != PMIC_GPIO_PULL_DISABLE) + flags |= GPIOD_PULL_UP; + + if (pad->analog_pass) + flags |= GPIOD_IS_AF; + + *flagsp = flags; + + return 0; +} + +static int qcom_spmi_pmic_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + int ret; + + if (offset >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[offset]; + + if (!pad->is_enabled) + return -EINVAL; + + if (pad->input_enabled) { + ret = spmi_pmic_gpio_read(plat, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return ret; + + pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; + } + + return !!pad->out_value; +} + +static int qcom_spmi_pmic_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + int val; + + if (offset >= plat->pin_count) + return GPIOF_UNKNOWN; + + pad = &plat->pads[offset]; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_EN_CTL); + if (!(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) + return GPIOF_UNKNOWN; + else if (pad->analog_pass) + return GPIOF_FUNC; + else if (pad->output_enabled) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static int qcom_spmi_pmic_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + if (args->args_count < 1) + return -EINVAL; + + /* GPIOs in DT are 1-based */ + desc->offset = args->args[0] - 1; + if (desc->offset >= uc_priv->gpio_count) + return -EINVAL; + + if (args->args_count < 2) + return 0; + + desc->flags = gpio_flags_xlate(args->args[1]); + + return 0; +} + +static const struct dm_gpio_ops qcom_spmi_pmic_gpio_ops = { + .set_flags = qcom_spmi_pmic_gpio_set_flags, + .get_flags = qcom_spmi_pmic_gpio_get_flags, + .get_value = qcom_spmi_pmic_gpio_get_value, + .get_function = qcom_spmi_pmic_gpio_get_function, + .xlate = qcom_spmi_pmic_gpio_xlate, +}; + +static int qcom_spmi_pmic_gpio_bind(struct udevice *dev) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct udevice *child; + struct driver *drv; + int ret; + + drv = lists_driver_lookup_name("qcom_spmi_pmic_pinctrl"); + if (!drv) { + log_warning("Cannot find driver '%s'\n", "qcom_spmi_pmic_pinctrl"); + return -ENOENT; + } + + /* Bind the GPIO driver as a child of the PMIC. */ + ret = device_bind_with_driver_data(dev, drv, + dev->name, + 0, dev_ofnode(dev), &child); + if (ret) + return log_msg_ret("bind", ret); + + dev_set_plat(child, plat); + + return 0; +} + +static int qcom_spmi_pmic_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct ofnode_phandle_args args; + int i, ret; + u64 pid; + + plat->dev = dev; + plat->pmic = dev->parent; + + pid = dev_read_addr(dev); + if (pid == FDT_ADDR_T_NONE) + return log_msg_ret("bad address", -EINVAL); + + plat->pid = pid; + + /* + * Parse basic GPIO count specified via the gpio-ranges property + * as specified in upstream devicetrees + */ + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", + NULL, 3, 0, &args); + if (ret) + return log_msg_ret("gpio-ranges", ret); + + plat->pin_count = min_t(u32, args.args[2], PMIC_MAX_GPIOS); + + uc_priv->gpio_count = plat->pin_count; + + uc_priv->bank_name = strchr(dev_read_string(dev, "compatible"), ','); + if (uc_priv->bank_name) + uc_priv->bank_name += 1; /* skip the , */ + else + uc_priv->bank_name = dev->name; + + plat->pads = calloc(plat->pin_count, sizeof(struct spmi_pmic_gpio_pad)); + if (!plat->pads) + return -ENOMEM; + + for (i = 0; i < plat->pin_count; ++i) { + struct spmi_pmic_gpio_pad *pad = &plat->pads[i]; + + pad->base = plat->pid + i * PMIC_GPIO_ADDRESS_RANGE; + + ret = spmi_pmic_gpio_populate(plat, pad); + if (ret < 0) + return ret; + } + + return 0; +} + +static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = { + { .compatible = "qcom,pm8550-gpio" }, + { .compatible = "qcom,pm8550b-gpio" }, + { .compatible = "qcom,pm8550ve-gpio" }, + { .compatible = "qcom,pm8550vs-gpio" }, + { .compatible = "qcom,pmk8550-gpio" }, + { .compatible = "qcom,pmr735d-gpio" }, + { } +}; + +U_BOOT_DRIVER(qcom_spmi_pmic_gpio) = { + .name = "qcom_spmi_pmic_gpio", + .id = UCLASS_GPIO, + .of_match = qcom_spmi_pmic_gpio_ids, + .bind = qcom_spmi_pmic_gpio_bind, + .probe = qcom_spmi_pmic_gpio_probe, + .ops = &qcom_spmi_pmic_gpio_ops, + .plat_auto = sizeof(struct qcom_spmi_pmic_gpio_data), + .flags = DM_FLAG_ALLOC_PDATA, +}; + +/* Qualcomm specific pin configurations */ +#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) +#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) +#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) +#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) +#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) + +static const struct pinconf_param qcom_spmi_pmic_pinctrl_conf_params[] = { + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, PMIC_GPIO_PULL_UP_30 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_UP, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "output-high", PIN_CONFIG_OUTPUT, 1 }, + { "output-low", PIN_CONFIG_OUTPUT, 0 }, + { "qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, + { "qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, + { "qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, + { "qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, + { "qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, +}; + +static int qcom_spmi_pmic_pinctrl_get_pins_count(struct udevice *dev) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + + return plat->pin_count; +} + +static const char *qcom_spmi_pmic_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static char name[8]; + + /* DT indexes from 1 */ + snprintf(name, sizeof(name), "gpio%u", selector + 1); + + return name; +} + +static int qcom_spmi_pmic_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, int size) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + + if (selector >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[selector]; + + spmi_pmic_gpio_get_state(plat, pad, buf, size); + + return 0; +} + +static int qcom_spmi_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector, + unsigned int param, unsigned int arg) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + + if (selector >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[selector]; + pad->is_enabled = true; + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!pad->have_buffer) + return -EINVAL; + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; + break; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + if (!pad->have_buffer) + return -EINVAL; + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; + break; + case PIN_CONFIG_BIAS_DISABLE: + pad->pullup = PMIC_GPIO_PULL_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + pad->pullup = PMIC_GPIO_PULL_UP_30; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg) + pad->pullup = PMIC_GPIO_PULL_DOWN; + else + pad->pullup = PMIC_GPIO_PULL_DISABLE; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pad->is_enabled = false; + break; + case PIN_CONFIG_POWER_SOURCE: + if (arg >= pad->num_sources) + return -EINVAL; + pad->power_source = arg; + break; + case PIN_CONFIG_INPUT_ENABLE: + pad->input_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + pad->output_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT: + pad->output_enabled = true; + pad->out_value = arg; + break; + case PMIC_GPIO_CONF_PULL_UP: + if (arg > PMIC_GPIO_PULL_UP_1P5_30) + return -EINVAL; + pad->pullup = arg; + break; + case PMIC_GPIO_CONF_STRENGTH: + if (arg > PMIC_GPIO_STRENGTH_LOW) + return -EINVAL; + switch (arg) { + case PMIC_GPIO_STRENGTH_HIGH: + pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH; + break; + case PMIC_GPIO_STRENGTH_LOW: + pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW; + break; + default: + pad->strength = arg; + break; + } + break; + case PMIC_GPIO_CONF_ATEST: + if (!pad->lv_mv_type || arg > 4) + return -EINVAL; + pad->atest = arg; + break; + case PMIC_GPIO_CONF_ANALOG_PASS: + if (!pad->lv_mv_type) + return -EINVAL; + pad->analog_pass = true; + break; + case PMIC_GPIO_CONF_DTEST_BUFFER: + if (arg > 4) + return -EINVAL; + pad->dtest_buffer = arg; + break; + default: + return -EINVAL; + } + + return qcom_spmi_pmic_gpio_set(plat, pad); +} + +static const char *qcom_spmi_pmic_pinctrl_get_function_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= ARRAY_SIZE(spmi_pmic_gpio_functions)) + return NULL; + + return spmi_pmic_gpio_functions[selector]; +} + +static int qcom_spmi_pmic_pinctrl_get_functions_count(struct udevice *dev) +{ + return ARRAY_SIZE(spmi_pmic_gpio_functions); +} + +static int qcom_spmi_pmic_pinctrl_pinmux_set_mux(struct udevice *dev, unsigned int selector, + unsigned int function) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + unsigned int val; + int ret; + + if (selector >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[selector]; + + /* + * Non-LV/MV subtypes only support 2 special functions, + * offsetting the dtestx function values by 2 + */ + if (!pad->lv_mv_type) { + if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || + function == PMIC_GPIO_FUNC_INDEX_FUNC4) { + pr_err("LV/MV subtype doesn't have func3/func4\n"); + return -EINVAL; + } + if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) + function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3); + } + + pad->function = function; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; + + if (pad->lv_mv_type) { + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->atest - 1; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, + val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, + val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + return spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); +} + +struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { + .get_pins_count = qcom_spmi_pmic_pinctrl_get_pins_count, + .get_pin_name = qcom_spmi_pmic_pinctrl_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinconf_num_params = ARRAY_SIZE(qcom_spmi_pmic_pinctrl_conf_params), + .pinconf_params = qcom_spmi_pmic_pinctrl_conf_params, + .pinconf_set = qcom_spmi_pmic_pinctrl_pinconf_set, + .get_function_name = qcom_spmi_pmic_pinctrl_get_function_name, + .get_functions_count = qcom_spmi_pmic_pinctrl_get_functions_count, + .pinmux_set = qcom_spmi_pmic_pinctrl_pinmux_set_mux, + .get_pin_muxing = qcom_spmi_pmic_pinctrl_get_pin_muxing, +}; + +U_BOOT_DRIVER(qcom_spmi_pmic_pinctrl) = { + .name = "qcom_spmi_pmic_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &qcom_spmi_pmic_pinctrl_ops, +}; diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c deleted file mode 100644 index 8307a07e14e..00000000000 --- a/drivers/gpio/tca642x.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright 2013 Texas Instruments, Inc. - * Author: Dan Murphy <dmurphy@ti.com> - * - * Derived work from the pca953x.c driver - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <command.h> -#include <i2c.h> -#include <tca642x.h> - -/* tca642x register address definitions */ -struct tca642x_bank_info tca642x_regs[] = { - { .input_reg = 0x00, - .output_reg = 0x04, - .polarity_reg = 0x08, - .configuration_reg = 0x0c }, - { .input_reg = 0x01, - .output_reg = 0x05, - .polarity_reg = 0x09, - .configuration_reg = 0x0d }, - { .input_reg = 0x02, - .output_reg = 0x06, - .polarity_reg = 0x0a, - .configuration_reg = 0x0e }, -}; - -/* - * Modify masked bits in register - */ -static int tca642x_reg_write(uchar chip, uint8_t addr, - uint8_t reg_bit, uint8_t data) -{ - uint8_t valw; - int org_bus_num; - int ret; - - org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); - - if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) { - printf("Could not read before writing\n"); - ret = -1; - goto error; - } - valw &= ~reg_bit; - valw |= data; - - ret = i2c_write(chip, addr, 1, (u8 *)&valw, 1); - -error: - i2c_set_bus_num(org_bus_num); - return ret; -} - -static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data) -{ - uint8_t valw; - int org_bus_num; - int ret = 0; - - org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); - if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) { - ret = -1; - goto error; - } - - *data = valw; - -error: - i2c_set_bus_num(org_bus_num); - return ret; -} - -/* - * Set output value of IO pins in 'reg_bit' to corresponding value in 'data' - * 0 = low, 1 = high - */ -int tca642x_set_val(uchar chip, uint8_t gpio_bank, - uint8_t reg_bit, uint8_t data) -{ - uint8_t out_reg = tca642x_regs[gpio_bank].output_reg; - - return tca642x_reg_write(chip, out_reg, reg_bit, data); -} - -/* - * Set read polarity of IO pins in 'reg_bit' to corresponding value in 'data' - * 0 = read pin value, 1 = read inverted pin value - */ -int tca642x_set_pol(uchar chip, uint8_t gpio_bank, - uint8_t reg_bit, uint8_t data) -{ - uint8_t pol_reg = tca642x_regs[gpio_bank].polarity_reg; - - return tca642x_reg_write(chip, pol_reg, reg_bit, data); -} - -/* - * Set direction of IO pins in 'reg_bit' to corresponding value in 'data' - * 0 = output, 1 = input - */ -int tca642x_set_dir(uchar chip, uint8_t gpio_bank, - uint8_t reg_bit, uint8_t data) -{ - uint8_t config_reg = tca642x_regs[gpio_bank].configuration_reg; - - return tca642x_reg_write(chip, config_reg, reg_bit, data); -} - -/* - * Read current logic level of all IO pins - */ -int tca642x_get_val(uchar chip, uint8_t gpio_bank) -{ - uint8_t val; - uint8_t in_reg = tca642x_regs[gpio_bank].input_reg; - - if (tca642x_reg_read(chip, in_reg, &val) < 0) - return -1; - - return (int)val; -} - -/* - * Set the inital register states for the tca642x gpio expander - */ -int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]) -{ - int i, ret; - uint8_t config_reg; - uint8_t polarity_reg; - uint8_t output_reg; - - for (i = 0; i < 3; i++) { - config_reg = tca642x_regs[i].configuration_reg; - ret = tca642x_reg_write(chip, config_reg, 0xff, - init_data[i].configuration_reg); - polarity_reg = tca642x_regs[i].polarity_reg; - ret = tca642x_reg_write(chip, polarity_reg, 0xff, - init_data[i].polarity_reg); - output_reg = tca642x_regs[i].output_reg; - ret = tca642x_reg_write(chip, output_reg, 0xff, - init_data[i].output_reg); - } - - return ret; -} - -#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_XPL_BUILD) -/* - * Display tca642x information - */ -static int tca642x_info(uchar chip) -{ - int i, j; - uint8_t data; - - printf("tca642x@ 0x%x (%d pins):\n", chip, 24); - for (i = 0; i < 3; i++) { - printf("Bank %i\n", i); - if (tca642x_reg_read(chip, - tca642x_regs[i].configuration_reg, - &data) < 0) - return -1; - printf("\tConfiguration: "); - for (j = 7; j >= 0; j--) - printf("%c", data & (1 << j) ? 'i' : 'o'); - printf("\n"); - - if (tca642x_reg_read(chip, - tca642x_regs[i].polarity_reg, &data) < 0) - return -1; - printf("\tPolarity: "); - for (j = 7; j >= 0; j--) - printf("%c", data & (1 << j) ? '1' : '0'); - printf("\n"); - - if (tca642x_reg_read(chip, - tca642x_regs[i].input_reg, &data) < 0) - return -1; - printf("\tInput value: "); - for (j = 7; j >= 0; j--) - printf("%c", data & (1 << j) ? '1' : '0'); - printf("\n"); - - if (tca642x_reg_read(chip, - tca642x_regs[i].output_reg, &data) < 0) - return -1; - printf("\tOutput value: "); - for (j = 7; j >= 0; j--) - printf("%c", data & (1 << j) ? '1' : '0'); - printf("\n"); - } - - return 0; -} - -static int tca642x_get_bank(int pin) -{ - int gpio_bank; - - if (pin <= 7) { - gpio_bank = 0; - } else if ((pin >= 10) && (pin <= 17)) { - gpio_bank = 1; - } else if ((pin >= 20) && (pin <= 27)) { - gpio_bank = 2; - } else { - printf("Requested pin is not available\n"); - gpio_bank = -1; - } - - return gpio_bank; -} - -static struct cmd_tbl cmd_tca642x[] = { - U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""), - U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""), - U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""), - U_BOOT_CMD_MKENT(invert, 4, 0, (void *)TCA642X_CMD_INVERT, "", ""), - U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""), -}; - -static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - static uchar chip = CFG_SYS_I2C_TCA642X_ADDR; - int ret = CMD_RET_USAGE, val; - int gpio_bank = 0; - uint8_t bank_shift; - ulong ul_arg2 = 0; - ulong ul_arg3 = 0; - struct cmd_tbl *c; - - c = find_cmd_tbl(argv[1], cmd_tca642x, ARRAY_SIZE(cmd_tca642x)); - - /* All commands but "device" require 'maxargs' arguments */ - if (!c || - !((argc == (c->maxargs)) || - (((int)c->cmd == TCA642X_CMD_DEVICE) && - (argc == (c->maxargs - 1))))) { - return CMD_RET_USAGE; - } - - /* arg2 used as chip number or pin number */ - if (argc > 2) - ul_arg2 = dectoul(argv[2], NULL); - - /* arg3 used as pin or invert value */ - if (argc > 3) - ul_arg3 = dectoul(argv[3], NULL) & 0x1; - - switch ((int)c->cmd) { - case TCA642X_CMD_INFO: - ret = tca642x_info(chip); - if (ret) - ret = CMD_RET_FAILURE; - break; - - case TCA642X_CMD_DEVICE: - if (argc == 3) - chip = (uint8_t)ul_arg2; - printf("Current device address: 0x%x\n", chip); - ret = CMD_RET_SUCCESS; - break; - - case TCA642X_CMD_INPUT: - gpio_bank = tca642x_get_bank(ul_arg2); - if (gpio_bank < 0) { - ret = CMD_RET_FAILURE; - goto error; - } - bank_shift = ul_arg2 - (gpio_bank * 10); - ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), - TCA642X_DIR_IN << bank_shift); - val = (tca642x_get_val(chip, gpio_bank) & - (1 << bank_shift)) != 0; - - if (ret) - ret = CMD_RET_FAILURE; - else - printf("chip 0x%02x, pin 0x%lx = %d\n", chip, - ul_arg2, val); - break; - - case TCA642X_CMD_OUTPUT: - gpio_bank = tca642x_get_bank(ul_arg2); - if (gpio_bank < 0) { - ret = CMD_RET_FAILURE; - goto error; - } - bank_shift = ul_arg2 - (gpio_bank * 10); - ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), - (TCA642X_DIR_OUT << bank_shift)); - if (!ret) - ret = tca642x_set_val(chip, - gpio_bank, (1 << bank_shift), - (ul_arg3 << bank_shift)); - if (ret) - ret = CMD_RET_FAILURE; - break; - - case TCA642X_CMD_INVERT: - gpio_bank = tca642x_get_bank(ul_arg2); - if (gpio_bank < 0) { - ret = CMD_RET_FAILURE; - goto error; - } - bank_shift = ul_arg2 - (gpio_bank * 10); - ret = tca642x_set_pol(chip, gpio_bank, (1 << bank_shift), - (ul_arg3 << bank_shift)); - if (ret) - ret = CMD_RET_FAILURE; - break; - } -error: - if (ret == CMD_RET_FAILURE) - eprintf("Error talking to chip at 0x%x\n", chip); - - return ret; -} - -U_BOOT_CMD( - tca642x, 5, 1, do_tca642x, - "tca642x gpio access", - "device [dev]\n" - " - show or set current device address\n" - "tca642x info\n" - " - display info for current chip\n" - "tca642x output pin 0|1\n" - " - set pin as output and drive low or high\n" - "tca642x invert pin 0|1\n" - " - disable/enable polarity inversion for reads\n" - "tca642x input pin\n" - " - set pin as input and read value" -); - -#endif /* CONFIG_CMD_TCA642X */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 146bc621c7e..775b2b4e9af 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -615,6 +615,7 @@ endif config SYS_I2C_SOFT bool "Legacy software I2C interface" + depends on !COMPILE_TEST help Enable the legacy software defined I2C interface diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 8b8f6309ada..515d3668395 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -300,7 +300,7 @@ config DS4510 config FSL_IIM bool "Enable FSL IC Identification Module (IIM) driver" - depends on ARCH_MX31 || ARCH_MX5 + depends on ARCH_MX5 config FSL_SEC_MON bool "Enable FSL SEC_MON Driver" diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 3ac690a3733..432b1fbb0c4 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -540,7 +540,7 @@ static int process_cmd(struct ec_state *ec, const struct ec_params_vstore_write *req = req_data; struct vstore_slot *slot; - if (req->slot >= EC_VSTORE_SLOT_MAX) + if (req->slot >= VSTORE_SLOT_COUNT) return -EINVAL; slot = &ec->slot[req->slot]; slot->locked = true; @@ -553,7 +553,7 @@ static int process_cmd(struct ec_state *ec, struct ec_response_vstore_read *resp = resp_data; struct vstore_slot *slot; - if (req->slot >= EC_VSTORE_SLOT_MAX) + if (req->slot >= VSTORE_SLOT_COUNT) return -EINVAL; slot = &ec->slot[req->slot]; memcpy(resp->data, slot->data, EC_VSTORE_SLOT_SIZE); diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c index 25a98e0f935..a2589a2ad31 100644 --- a/drivers/net/mtk_eth/an8855.c +++ b/drivers/net/mtk_eth/an8855.c @@ -909,7 +909,7 @@ static void an8855_port_isolation(struct an8855_switch_priv *priv) /* Set port mode to user port */ an8855_reg_write(priv, AN8855_PVC(i), - (0x8100 << AN8855_STAG_VPID_S) | + (0x9100 << AN8855_STAG_VPID_S) | (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S)); } } diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index ee8eae1efd9..a02dbe900b8 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -7,6 +7,7 @@ * (C) 2012 NetModule AG, David Andrey, added KSZ9031 * (C) Copyright 2017 Adaptrum, Inc. * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc. + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include <dm.h> #include <env.h> @@ -110,6 +111,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, { struct udevice *dev = phydev->dev; struct phy_driver *drv = phydev->drv; + struct ofnode_phandle_args phandle; int val[4]; int i, changed = 0, offset, max; u16 regval = 0; @@ -126,8 +128,14 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, } if (!ofnode_valid(node)) { - /* No node found, look in the Ethernet node */ - node = dev_ofnode(dev); + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle)) { + /* No phy-handle found, look in the Ethernet node */ + node = dev_ofnode(dev); + } else { + /* phy-handle found */ + node = phandle.node; + } } for (i = 0; i < ofcfg->grpsz; i++) { diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index f695a3a41d2..1160c1d6cfa 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -29,45 +29,30 @@ #include "sh_eth.h" -#ifndef CFG_SH_ETHER_USE_PORT -# error "Please define CFG_SH_ETHER_USE_PORT" -#endif -#ifndef CFG_SH_ETHER_PHY_ADDR -# error "Please define CFG_SH_ETHER_PHY_ADDR" -#endif +static void flush_cache_wback(void *addr, unsigned long len) +{ + flush_dcache_range((unsigned long)addr, + (unsigned long)(addr + ALIGN(len, SH_ETHER_ALIGN_SIZE))); +} -#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ - !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#define flush_cache_wback(addr, len) \ - flush_dcache_range((unsigned long)addr, \ - (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE))) -#else -#define flush_cache_wback(...) -#endif +static void invalidate_cache(void *addr, unsigned long len) +{ + unsigned long line_size = SH_ETHER_ALIGN_SIZE; + unsigned long start, end; -#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) -#define invalidate_cache(addr, len) \ - { \ - unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ - unsigned long start, end; \ - \ - start = (unsigned long)addr; \ - end = start + len; \ - start &= ~(line_size - 1); \ - end = ((end + line_size - 1) & ~(line_size - 1)); \ - \ - invalidate_dcache_range(start, end); \ - } -#else -#define invalidate_cache(...) -#endif + start = (unsigned long)addr; + end = start + len; + start &= ~(line_size - 1); + end = (end + line_size - 1) & ~(line_size - 1); + + invalidate_dcache_range(start, end); +} #define TIMEOUT_CNT 1000 -static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) +static int sh_eth_send_common(struct sh_eth_info *port_info, void *packet, int len) { int ret = 0, timeout; - struct sh_eth_info *port_info = ð->port_info[eth->port]; if (!packet || len > 0xffff) { printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); @@ -121,10 +106,8 @@ err: return ret; } -static int sh_eth_recv_start(struct sh_eth_dev *eth) +static int sh_eth_recv_start(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - /* Check if the rx descriptor is ready */ invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (port_info->rx_desc_cur->rd0 & RD_RACT) @@ -137,11 +120,9 @@ static int sh_eth_recv_start(struct sh_eth_dev *eth) return port_info->rx_desc_cur->rd1 & 0xffff; } -static void sh_eth_recv_finish(struct sh_eth_dev *eth) +static void sh_eth_recv_finish(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); + invalidate_cache((void *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); /* Make current descriptor available again */ if (port_info->rx_desc_cur->rd0 & RD_RDLE) @@ -159,9 +140,8 @@ static void sh_eth_recv_finish(struct sh_eth_dev *eth) port_info->rx_desc_cur = port_info->rx_desc_base; } -static int sh_eth_reset(struct sh_eth_dev *eth) +static int sh_eth_reset(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; @@ -192,12 +172,11 @@ static int sh_eth_reset(struct sh_eth_dev *eth) #endif } -static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) +static int sh_eth_tx_desc_init(struct sh_eth_info *port_info) { - int i, ret = 0; u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct tx_desc_s *cur_tx_desc; + int i, ret = 0; /* * Allocate rx descriptors. They must be aligned to size of struct @@ -244,11 +223,10 @@ err: return ret; } -static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) +static int sh_eth_rx_desc_init(struct sh_eth_info *port_info) { int i, ret = 0; u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct rx_desc_s *cur_rx_desc; u8 *rx_buf; @@ -318,20 +296,16 @@ err: return ret; } -static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) +static void sh_eth_tx_desc_free(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - if (port_info->tx_desc_alloc) { free(port_info->tx_desc_alloc); port_info->tx_desc_alloc = NULL; } } -static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) +static void sh_eth_rx_desc_free(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - if (port_info->rx_desc_alloc) { free(port_info->rx_desc_alloc); port_info->rx_desc_alloc = NULL; @@ -343,21 +317,21 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) } } -static int sh_eth_desc_init(struct sh_eth_dev *eth) +static int sh_eth_desc_init(struct sh_eth_info *port_info) { int ret = 0; - ret = sh_eth_tx_desc_init(eth); + ret = sh_eth_tx_desc_init(port_info); if (ret) goto err_tx_init; - ret = sh_eth_rx_desc_init(eth); + ret = sh_eth_rx_desc_init(port_info); if (ret) goto err_rx_init; return ret; err_rx_init: - sh_eth_tx_desc_free(eth); + sh_eth_tx_desc_free(port_info); err_tx_init: return ret; @@ -375,9 +349,8 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, sh_eth_write(port_info, val, MALR); } -static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) +static void sh_eth_mac_regs_config(struct sh_eth_info *port_info, unsigned char *mac) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; unsigned long edmr; /* Configure e-dmac registers */ @@ -422,9 +395,8 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) #endif } -static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) +static int sh_eth_phy_regs_config(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct phy_device *phy = port_info->phydev; int ret = 0; u32 val = 0; @@ -470,10 +442,8 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) return ret; } -static void sh_eth_start(struct sh_eth_dev *eth) +static void sh_eth_start(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - /* * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit @@ -481,33 +451,30 @@ static void sh_eth_start(struct sh_eth_dev *eth) sh_eth_write(port_info, EDRRR_R, EDRRR); } -static void sh_eth_stop(struct sh_eth_dev *eth) +static void sh_eth_stop(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - sh_eth_write(port_info, ~EDRRR_R, EDRRR); } -static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac) +static int sh_eth_init_common(struct sh_eth_info *port_info, unsigned char *mac) { int ret = 0; - ret = sh_eth_reset(eth); + ret = sh_eth_reset(port_info); if (ret) return ret; - ret = sh_eth_desc_init(eth); + ret = sh_eth_desc_init(port_info); if (ret) return ret; - sh_eth_mac_regs_config(eth, mac); + sh_eth_mac_regs_config(port_info, mac); return 0; } -static int sh_eth_start_common(struct sh_eth_dev *eth) +static int sh_eth_start_common(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; int ret; ret = phy_startup(port_info->phydev); @@ -516,17 +483,17 @@ static int sh_eth_start_common(struct sh_eth_dev *eth) return ret; } - ret = sh_eth_phy_regs_config(eth); + ret = sh_eth_phy_regs_config(port_info); if (ret) return ret; - sh_eth_start(eth); + sh_eth_start(port_info); return 0; } struct sh_ether_priv { - struct sh_eth_dev shdev; + struct sh_eth_info port_info; struct mii_dev *bus; phys_addr_t iobase; @@ -536,20 +503,19 @@ struct sh_ether_priv { static int sh_ether_send(struct udevice *dev, void *packet, int len) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; - return sh_eth_send_common(eth, packet, len); + return sh_eth_send_common(port_info, packet, len); } static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2); int len; - len = sh_eth_recv_start(eth); + len = sh_eth_recv_start(port_info); if (len > 0) { invalidate_cache(packet, len); *packetp = packet; @@ -567,10 +533,9 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; - sh_eth_recv_finish(eth); + sh_eth_recv_finish(port_info); /* Restart the receiver if disabled */ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) @@ -582,8 +547,7 @@ static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) static int sh_ether_write_hwaddr(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; struct eth_pdata *pdata = dev_get_plat(dev); sh_eth_write_hwaddr(port_info, pdata->enetaddr); @@ -595,10 +559,9 @@ static int sh_eth_phy_config(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct sh_eth_dev *eth = &priv->shdev; - int ret = 0; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; struct phy_device *phydev; + int ret = 0; phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface); if (!phydev) @@ -614,40 +577,38 @@ static int sh_ether_start(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; int ret; - ret = sh_eth_init_common(eth, pdata->enetaddr); + ret = sh_eth_init_common(port_info, pdata->enetaddr); if (ret) return ret; - ret = sh_eth_start_common(eth); + ret = sh_eth_start_common(port_info); if (ret) goto err_start; return 0; err_start: - sh_eth_tx_desc_free(eth); - sh_eth_rx_desc_free(eth); + sh_eth_tx_desc_free(port_info); + sh_eth_rx_desc_free(port_info); return ret; } static void sh_ether_stop(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; phy_shutdown(port_info->phydev); - sh_eth_stop(&priv->shdev); + sh_eth_stop(port_info); } /******* for bb_miiphy *******/ static int sh_eth_bb_mdio_active(struct mii_dev *miidev) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); @@ -656,8 +617,7 @@ static int sh_eth_bb_mdio_active(struct mii_dev *miidev) static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); @@ -666,8 +626,7 @@ static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev) static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; if (v) sh_eth_write(port_info, @@ -681,8 +640,7 @@ static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v) static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; @@ -691,8 +649,7 @@ static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v) static int sh_eth_bb_set_mdc(struct mii_dev *miidev, int v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; if (v) sh_eth_write(port_info, @@ -738,7 +695,7 @@ static int sh_ether_probe(struct udevice *udev) { struct eth_pdata *pdata = dev_get_plat(udev); struct sh_ether_priv *priv = dev_get_priv(udev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; struct mii_dev *mdiodev; int ret; @@ -757,7 +714,7 @@ static int sh_ether_probe(struct udevice *udev) mdiodev->read = sh_eth_bb_miiphy_read; mdiodev->write = sh_eth_bb_miiphy_write; - mdiodev->priv = eth; + mdiodev->priv = port_info; snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name); ret = mdio_register(mdiodev); @@ -766,10 +723,7 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = mdiodev; - eth->port = CFG_SH_ETHER_USE_PORT; - eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; - eth->port_info[eth->port].iobase = - (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); + port_info->iobase = (void __iomem *)(uintptr_t)BASE_IO_ADDR; #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&priv->clk); @@ -777,7 +731,7 @@ static int sh_ether_probe(struct udevice *udev) goto err_mdio_register; #endif - ret = sh_eth_init_common(eth, pdata->enetaddr); + ret = sh_eth_init_common(port_info, pdata->enetaddr); if (ret) goto err_phy_config; @@ -801,8 +755,7 @@ err_mdio_register: static int sh_ether_remove(struct udevice *udev) { struct sh_ether_priv *priv = dev_get_priv(udev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; #if CONFIG_IS_ENABLED(CLK) clk_disable(&priv->clk); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index ecf4a697e27..c395e6e8fc7 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -19,23 +19,17 @@ /* The ethernet controller needs to use physical addresses */ #define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000) +#define SH_ETHER_ALIGN_SIZE 16 #elif defined(CONFIG_ARM) #ifndef inl #define inl readl #define outl writel +#define SH_ETHER_ALIGN_SIZE 64 #endif #define ADDR_TO_PHY(addr) ((uintptr_t)(addr)) #define ADDR_TO_P2(addr) (addr) #endif /* defined(CONFIG_SH) */ -/* base padding size is 16 */ -#ifndef CFG_SH_ETHER_ALIGNE_SIZE -#define CFG_SH_ETHER_ALIGNE_SIZE 16 -#endif - -/* Number of supported ports */ -#define MAX_PORT_NUM 2 - /* Buffers must be big enough to hold the largest ethernet frame. Also, rx buffers must be a multiple of 32 bytes */ #define MAX_BUF_SIZE (48 * 32) @@ -47,7 +41,7 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) +#define TX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { @@ -62,9 +56,9 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) +#define RX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12) /* aligned cache line size */ -#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) +#define RX_BUF_ALIGNE_SIZE (SH_ETHER_ALIGN_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { @@ -84,17 +78,11 @@ struct sh_eth_info { u8 *rx_buf_alloc; u8 *rx_buf_base; u8 mac_addr[6]; - u8 phy_addr; struct eth_device *dev; struct phy_device *phydev; void __iomem *iobase; }; -struct sh_eth_dev { - int port; - struct sh_eth_info port_info[MAX_PORT_NUM]; -}; - /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ enum { /* E-DMAC registers */ @@ -388,11 +376,11 @@ enum DMAC_M_BIT { #endif }; -#if CFG_SH_ETHER_ALIGNE_SIZE == 64 +#if SH_ETHER_ALIGN_SIZE == 64 # define EMDR_DESC EDMR_DL1 -#elif CFG_SH_ETHER_ALIGNE_SIZE == 32 +#elif SH_ETHER_ALIGN_SIZE == 32 # define EMDR_DESC EDMR_DL0 -#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +#elif SH_ETHER_ALIGN_SIZE == 16 /* Default */ # define EMDR_DESC 0 #endif diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c index 2639f960631..d8df3c9afb0 100644 --- a/drivers/net/ti/icssg_prueth.c +++ b/drivers/net/ti/icssg_prueth.c @@ -63,6 +63,7 @@ /* Number of PRU Cores per Slice */ #define ICSSG_NUM_PRU_CORES 3 +#define ICSSG_NUM_FIRMWARES 6 static int icssg_gmii_select(struct prueth_priv *priv) { @@ -192,25 +193,6 @@ static int icssg_update_link(struct prueth_priv *priv) return phy->link; } -struct icssg_firmwares { - char *pru; - char *rtu; - char *txpru; -}; - -static struct icssg_firmwares icssg_emac_firmwares[] = { - { - .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru0-prueth-fw.elf", - .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", - .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", - }, - { - .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru1-prueth-fw.elf", - .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", - .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", - } -}; - static int icssg_start_pru_cores(struct udevice *dev) { struct prueth_priv *priv = dev_get_priv(dev); @@ -223,7 +205,7 @@ static int icssg_start_pru_cores(struct udevice *dev) slice = priv->port_id; index = slice * ICSSG_NUM_PRU_CORES; - firmwares = icssg_emac_firmwares; + firmwares = prueth->firmwares; ofnode_read_u32_index(dev_ofnode(prueth->dev), "ti,prus", index, &phandle); ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); @@ -476,6 +458,24 @@ static const struct eth_ops prueth_ops = { .stop = prueth_stop, }; +static char *prepend_fw_path(const char *fw_name) +{ + static const char fw_dir[] = "/lib/firmware/"; + char *result; + int len; + + if (!fw_name) + return NULL; + + len = strlen(fw_dir) + strlen(fw_name) + 1; + result = malloc(len); + if (!result) + return NULL; + + sprintf(result, "%s%s", fw_dir, fw_name); + return result; +} + static int icssg_ofdata_parse_phy(struct udevice *dev) { struct prueth_priv *priv = dev_get_priv(dev); @@ -534,6 +534,8 @@ static int prueth_probe(struct udevice *dev) struct udevice **prussdev = NULL; ofnode eth_ports_node, eth_node; struct udevice *port_dev; + const char **fw_names; + int fw_count, i; int ret = 0; prueth->dev = dev; @@ -659,6 +661,18 @@ static int prueth_probe(struct udevice *dev) } } + /* Parse firmware-name property from DT */ + fw_count = dev_read_string_list(dev, "firmware-name", &fw_names); + if (fw_count != ICSSG_NUM_FIRMWARES) { + dev_err(dev, "Expected %d firmware names, got %d\n", ICSSG_NUM_FIRMWARES, fw_count); + return -EINVAL; + } + for (i = 0; i < 2; i++) { + prueth->firmwares[i].pru = prepend_fw_path(fw_names[i * 3 + 0]); + prueth->firmwares[i].rtu = prepend_fw_path(fw_names[i * 3 + 1]); + prueth->firmwares[i].txpru = prepend_fw_path(fw_names[i * 3 + 2]); + } + return 0; out: clk_disable(&prueth->mdiofck); diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h index c69cfd4f162..d88b6fa88e7 100644 --- a/drivers/net/ti/icssg_prueth.h +++ b/drivers/net/ti/icssg_prueth.h @@ -38,6 +38,12 @@ enum prueth_port { PRUETH_PORT_MII1, /* physical port MII 1 */ }; +struct icssg_firmwares { + char *pru; + char *rtu; + char *txpru; +}; + struct prueth { struct udevice *dev; struct udevice *pruss; @@ -66,6 +72,7 @@ struct prueth { u8 rtu_core_id; u8 txpru_core_id; u8 icssg_hwcmdseq; + struct icssg_firmwares firmwares[PRUETH_NUM_MACS]; }; struct prueth_priv { diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 7c58ceb78f5..2b14437f69c 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -912,8 +912,10 @@ int nvme_init(struct udevice *udev) goto free_id; ret = bootdev_setup_for_sibling_blk(ns_udev, "nvme_bootdev"); - if (ret) - return log_msg_ret("bootdev", ret); + if (ret) { + log_err("bootdev: returning err=%d\n", ret); + goto free_id; + } ret = blk_probe_or_unbind(ns_udev); if (ret) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 59894d2430b..c370f8c6400 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -385,8 +385,10 @@ static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, int ret; ret = pci_get_bus(PCI_BUS(bdf), &bus); - if (ret) + if (ret) { + *valuep = 0xffffffff; return ret; + } return pci_bus_read_config(bus, bdf, offset, valuep, size); } @@ -408,8 +410,10 @@ int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) int ret; ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); - if (ret) + if (ret) { + *valuep = 0xffffffff; return ret; + } *valuep = value; return 0; @@ -421,8 +425,10 @@ int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) int ret; ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); - if (ret) + if (ret) { + *valuep = 0xffff; return ret; + } *valuep = value; return 0; @@ -434,8 +440,10 @@ int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) int ret; ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); - if (ret) + if (ret) { + *valuep = 0xff; return ret; + } *valuep = value; return 0; @@ -447,8 +455,10 @@ int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep) int ret; ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8); - if (ret) + if (ret) { + *valuep = 0xff; return ret; + } *valuep = value; return 0; @@ -460,8 +470,10 @@ int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep) int ret; ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16); - if (ret) + if (ret) { + *valuep = 0xffff; return ret; + } *valuep = value; return 0; @@ -473,8 +485,10 @@ int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep) int ret; ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); - if (ret) + if (ret) { + *valuep = 0xffffffff; return ret; + } *valuep = value; return 0; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index d9c76898a96..58e070bfe1e 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -317,8 +317,7 @@ int pinctrl_select_state(struct udevice *dev, const char *statename) if (!dev_has_ofnode(dev)) return 0; /* - * Try full-implemented pinctrl first. - * If it fails or is not implemented, try simple one. + * If full-implemented pinctrl is not implemented, try simple one. */ if (CONFIG_IS_ENABLED(PINCTRL_FULL)) return pinctrl_select_state_full(dev, statename); diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 7d022ce718a..78efed6b66a 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -39,7 +39,7 @@ static void scsi_print_error(struct scsi_cmd *pccb) #ifdef CONFIG_SYS_64BIT_LBA void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, - unsigned long blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_READ16; pccb->cmd[1] = 0; @@ -83,7 +83,7 @@ static void scsi_setup_inquiry(struct scsi_cmd *pccb) } static void scsi_setup_sync_cache(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_SYNC_CACHE; pccb->cmd[1] = 0; @@ -100,7 +100,7 @@ static void scsi_setup_sync_cache(struct scsi_cmd *pccb, lbaint_t start, } static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_READ10; pccb->cmd[1] = 0; @@ -121,7 +121,7 @@ static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, } static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_WRITE10; pccb->cmd[1] = 0; @@ -143,7 +143,7 @@ static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, } static void scsi_setup_erase_ext(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { u8 *param = tempbuff; const u8 param_size = 24; @@ -193,9 +193,8 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, struct blk_desc *block_dev = dev_get_uclass_plat(dev); struct udevice *bdev = dev->parent; struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev); - lbaint_t start, blks, max_blks; + lbaint_t start, blks, max_blks, blocks; uintptr_t buf_addr; - unsigned short smallblks = 0; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; /* Setup device */ @@ -217,7 +216,6 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, pccb->dma_dir = DMA_FROM_DEVICE; #ifdef CONFIG_SYS_64BIT_LBA if (start > SCSI_LBA48_READ) { - unsigned long blocks; blocks = min_t(lbaint_t, blks, max_blks); pccb->datalen = block_dev->blksz * blocks; scsi_setup_read16(pccb, start, blocks); @@ -227,20 +225,20 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, #endif if (blks > max_blks) { pccb->datalen = block_dev->blksz * max_blks; - smallblks = max_blks; - scsi_setup_read_ext(pccb, start, smallblks); + blocks = max_blks; + scsi_setup_read_ext(pccb, start, blocks); start += max_blks; blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; - smallblks = (unsigned short)blks; - scsi_setup_read_ext(pccb, start, smallblks); + blocks = blks; + scsi_setup_read_ext(pccb, start, blocks); start += blks; blks = 0; } debug("scsi_read_ext: startblk " LBAF - ", blccnt %x buffer %lX\n", - start, smallblks, buf_addr); + ", blccnt " LBAF " buffer %lX\n", + start, blocks, buf_addr); if (scsi_exec(bdev, pccb)) { scsi_print_error(pccb); blkcnt -= blks; @@ -249,7 +247,7 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, buf_addr += pccb->datalen; } while (blks != 0); debug("scsi_read_ext: end startblk " LBAF - ", blccnt %x buffer %lX\n", start, smallblks, buf_addr); + ", blccnt " LBAF " buffer %lX\n", start, blocks, buf_addr); return blkcnt; } @@ -263,9 +261,8 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, struct blk_desc *block_dev = dev_get_uclass_plat(dev); struct udevice *bdev = dev->parent; struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev); - lbaint_t start, blks, max_blks; + lbaint_t start, blks, max_blks, blocks; uintptr_t buf_addr; - unsigned short smallblks; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; /* Setup device */ @@ -286,19 +283,19 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, pccb->dma_dir = DMA_TO_DEVICE; if (blks > max_blks) { pccb->datalen = block_dev->blksz * max_blks; - smallblks = max_blks; - scsi_setup_write_ext(pccb, start, smallblks); + blocks = max_blks; + scsi_setup_write_ext(pccb, start, blocks); start += max_blks; blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; - smallblks = (unsigned short)blks; - scsi_setup_write_ext(pccb, start, smallblks); + blocks = blks; + scsi_setup_write_ext(pccb, start, blocks); start += blks; blks = 0; } - debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n", - __func__, start, smallblks, buf_addr); + debug("%s: startblk " LBAF ", blccnt " LBAF " buffer %lx\n", + __func__, start, blocks, buf_addr); if (scsi_exec(bdev, pccb)) { scsi_print_error(pccb); blkcnt -= blks; @@ -312,8 +309,8 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, if (scsi_exec(bdev, pccb)) scsi_print_error(pccb); - debug("%s: end startblk " LBAF ", blccnt %x buffer %lX\n", - __func__, start, smallblks, buf_addr); + debug("%s: end startblk " LBAF ", blccnt " LBAF " buffer %lX\n", + __func__, start, blocks, buf_addr); return blkcnt; } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 589b526381f..1f2f2468eb0 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -762,7 +762,7 @@ config MCFUART config MXC_UART bool "IMX serial port support" - depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M + depends on MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index 0ffc1b6444b..9e52ba8905c 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -20,7 +20,7 @@ config W1_GPIO config W1_MXC bool "Enable 1-wire controller on i.MX processors" - depends on ARCH_MX31 || ARCH_MX5 + depends on ARCH_MX5 help Support the one wire controller found in some members of the NXP i.MX SoC family. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 45eb9b4d3f9..e9ea874d0e3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -27,7 +27,7 @@ config WATCHDOG_AUTOSTART config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" - default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 + default 128000 if ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SNAPDRAGON default 30000 if ARCH_SOCFPGA diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index adbb5aacdc3..4b972cff72c 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -63,10 +63,7 @@ int qcom_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) writel(bark_timeout_s, wdt_addr(wdt, WDT_BARK_TIME)); writel(bite_timeout_s, wdt_addr(wdt, WDT_BITE_TIME)); writel(BIT(0), wdt_addr(wdt, WDT_EN)); - if (readl(wdt_addr(wdt, WDT_EN)) != 1) { - dev_err(dev, "Failed to enable Qualcomm watchdog!\n"); - return -EIO; - } + return 0; } diff --git a/env/Kconfig b/env/Kconfig index c30785de48b..c667e8f2da1 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -759,6 +759,7 @@ config SCSI_ENV_PART_UUID config ENV_USE_DEFAULT_ENV_TEXT_FILE bool "Create default environment from file" + depends on !COMPILE_TEST help Normally, the default environment is automatically generated based on the settings of various CONFIG_* options, as well diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 5726981b19c..71b0b55b9c6 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -972,12 +972,10 @@ int __btrfs_map_block(struct btrfs_fs_info *fs_info, int rw, again: ce = search_cache_extent(&map_tree->cache_tree, logical); if (!ce) { - kfree(multi); *length = (u64)-1; return -ENOENT; } if (ce->start > logical) { - kfree(multi); *length = ce->start - logical; return -ENOENT; } diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c index dcdc883e34c..db86928511e 100644 --- a/fs/erofs/fs.c +++ b/fs/erofs/fs.c @@ -11,12 +11,15 @@ static struct erofs_ctxt { int erofs_dev_read(int device_id, void *buf, u64 offset, size_t len) { - lbaint_t sect = offset >> ctxt.cur_dev->log2blksz; - int off = offset & (ctxt.cur_dev->blksz - 1); + lbaint_t sect; + int off; if (!ctxt.cur_dev) return -EIO; + sect = offset >> ctxt.cur_dev->log2blksz; + off = offset & (ctxt.cur_dev->blksz - 1); + if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect, off, len, buf)) return 0; diff --git a/fs/exfat/io.c b/fs/exfat/io.c index 77cd2dfb6dc..6c86688cd6c 100644 --- a/fs/exfat/io.c +++ b/fs/exfat/io.c @@ -442,12 +442,15 @@ off_t exfat_get_size(const struct exfat_dev* dev) ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size, off_t offset) { - lbaint_t sect = offset >> ctxt.cur_dev->log2blksz; - int off = offset & (ctxt.cur_dev->blksz - 1); + lbaint_t sect; + int off; if (!ctxt.cur_dev) return -EIO; + sect = offset >> ctxt.cur_dev->log2blksz; + off = offset & (ctxt.cur_dev->blksz - 1); + if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect, off, size, buffer)) return 0; @@ -457,12 +460,15 @@ ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size, ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size, off_t offset) { - lbaint_t sect = offset >> ctxt.cur_dev->log2blksz; - int off = offset & (ctxt.cur_dev->blksz - 1); + lbaint_t sect; + int off; if (!ctxt.cur_dev) return -EIO; + sect = offset >> ctxt.cur_dev->log2blksz; + off = offset & (ctxt.cur_dev->blksz - 1); + if (fs_devwrite(ctxt.cur_dev, &ctxt.cur_part_info, sect, off, size, buffer)) return 0; @@ -473,43 +479,40 @@ ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size, ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node, void* buffer, size_t size, off_t offset) { - uint64_t uoffset = offset; cluster_t cluster; char* bufp = buffer; off_t lsize, loffset, remainder; - if (offset < 0) - return -EINVAL; - if (uoffset >= node->size) + if (offset >= node->size) return 0; if (size == 0) return 0; - if (uoffset + size > node->valid_size) + if (offset + size > node->valid_size) { ssize_t bytes = 0; - if (uoffset < node->valid_size) + if (offset < node->valid_size) { bytes = exfat_generic_pread(ef, node, buffer, - node->valid_size - uoffset, offset); - if (bytes < 0 || (size_t) bytes < node->valid_size - uoffset) + node->valid_size - offset, offset); + if (bytes < 0 || (size_t)bytes < node->valid_size - offset) return bytes; } memset(buffer + bytes, 0, MIN(size - bytes, node->size - node->valid_size)); - return MIN(size, node->size - uoffset); + return MIN(size, node->size - offset); } - cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb)); + cluster = exfat_advance_cluster(ef, node, offset / CLUSTER_SIZE(*ef->sb)); if (CLUSTER_INVALID(*ef->sb, cluster)) { exfat_error("invalid cluster 0x%x while reading", cluster); return -EIO; } - loffset = uoffset % CLUSTER_SIZE(*ef->sb); - remainder = MIN(size, node->size - uoffset); + loffset = offset % CLUSTER_SIZE(*ef->sb); + remainder = MIN(size, node->size - offset); while (remainder > 0) { if (CLUSTER_INVALID(*ef->sb, cluster)) @@ -531,43 +534,40 @@ ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node, } if (!(node->attrib & EXFAT_ATTRIB_DIR) && !ef->ro && !ef->noatime) exfat_update_atime(node); - return MIN(size, node->size - uoffset) - remainder; + return MIN(size, node->size - offset) - remainder; } ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node, const void* buffer, size_t size, off_t offset) { - uint64_t uoffset = offset; int rc; cluster_t cluster; const char* bufp = buffer; off_t lsize, loffset, remainder; - if (offset < 0) - return -EINVAL; - if (uoffset > node->size) + if (offset > node->size) { - rc = exfat_truncate(ef, node, uoffset, true); + rc = exfat_truncate(ef, node, offset, true); if (rc != 0) return rc; } - if (uoffset + size > node->size) + if (offset + size > node->size) { - rc = exfat_truncate(ef, node, uoffset + size, false); + rc = exfat_truncate(ef, node, offset + size, false); if (rc != 0) return rc; } if (size == 0) return 0; - cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb)); + cluster = exfat_advance_cluster(ef, node, offset / CLUSTER_SIZE(*ef->sb)); if (CLUSTER_INVALID(*ef->sb, cluster)) { exfat_error("invalid cluster 0x%x while writing", cluster); return -EIO; } - loffset = uoffset % CLUSTER_SIZE(*ef->sb); + loffset = offset % CLUSTER_SIZE(*ef->sb); remainder = size; while (remainder > 0) { @@ -586,7 +586,7 @@ ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node, bufp += lsize; loffset = 0; remainder -= lsize; - node->valid_size = MAX(node->valid_size, uoffset + size - remainder); + node->valid_size = MAX(node->valid_size, offset + size - remainder); cluster = exfat_next_cluster(ef, node, cluster); } if (!(node->attrib & EXFAT_ATTRIB_DIR)) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index cc150cf824f..8e6531fa3f0 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -198,16 +198,18 @@ void put_ext4(uint64_t off, const void *buf, uint32_t size) uint64_t remainder; unsigned char *temp_ptr = NULL; struct ext_filesystem *fs = get_fs(); - int log2blksz = fs->dev_desc->log2blksz; + int log2blksz; + + if (!fs->dev_desc) + return; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, fs->dev_desc->blksz); + log2blksz = fs->dev_desc->log2blksz; startblock = off >> log2blksz; startblock += part_offset; remainder = off & (uint64_t)(fs->dev_desc->blksz - 1); - if (fs->dev_desc == NULL) - return; - if ((startblock + (size >> log2blksz)) > (part_offset + fs->total_sect)) { printf("part_offset is " LBAFU "\n", part_offset); diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index d109ed6e90d..dd8ed40f888 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -877,19 +877,19 @@ int ext4fs_write(const char *fname, const char *buffer, if (ext4fs_init() != 0) { printf("error in File System init\n"); - return -1; + goto fail; } missing_feat = le32_to_cpu(fs->sb->feature_incompat) & ~EXT4_FEATURE_INCOMPAT_SUPP; if (missing_feat) { log_err("Unsupported features found %08x, not writing.\n", missing_feat); - return -1; + goto fail; } missing_feat = le32_to_cpu(fs->sb->feature_ro_compat) & ~EXT4_FEATURE_RO_COMPAT_SUPP; if (missing_feat) { log_err("Unsupported RO compat features found %08x, not writing.\n", missing_feat); - return -1; + goto fail; } inodes_per_block = fs->blksz / fs->inodesz; diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 9be99594f50..3c79a889bc2 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -277,7 +277,7 @@ int ext4fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) sizeof(struct ext2_dirent), (char *)&dirent, &actread); if (ret < 0) - return -ret; + return ret; if (!dirent.direntlen) return -EIO; diff --git a/include/configs/alt.h b/include/configs/alt.h index 8f03762583e..4c5d2de2bdf 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -20,16 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" diff --git a/include/configs/blanche.h b/include/configs/blanche.h index d4e0f677e67..46521aa16bf 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -29,8 +29,4 @@ #define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif -/* Board Clock */ - -/* ENV setting */ - #endif /* __BLANCHE_H */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 50c8d173383..b340800cc11 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -11,17 +11,4 @@ #include "rcar-gen3-common.h" -/* Environment compatibility */ - -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - #endif /* __CONDOR_H */ diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index ad5944230a6..707e7c28d55 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -9,8 +9,6 @@ #ifndef __EBISU_H #define __EBISU_H -#undef DEBUG - #include "rcar-gen3-common.h" /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 0b62ff9fbe1..e1cace73550 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,7 +11,4 @@ #include "rcar-gen4-common.h" -/* Board Clock */ -/* XTAL_CLK : 16.66MHz */ - #endif /* __FALCON_H */ diff --git a/include/configs/genmai.h b/include/configs/genmai.h new file mode 100644 index 00000000000..1d43f8e06af --- /dev/null +++ b/include/configs/genmai.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Renesas GENMAI board + * + * Copyright (C) 2017-2019 Renesas Electronics + */ + +#ifndef __GENMAI_H +#define __GENMAI_H + +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) + +#endif /* __GENAMI_H */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 7ae0726518d..4a5954af76f 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -19,16 +19,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 8de4a36e931..e4564b67a79 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -8,20 +8,8 @@ #ifndef __GRPEACH_H #define __GRPEACH_H -/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ - -/* Miscellaneous */ - /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) -/* Network interface */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index d47d70178cc..c2713b77e0a 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -19,19 +19,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __KOELSCH_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 2577c7a7da6..13f327fabf2 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -20,19 +20,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __LAGER_H */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 2cb430be8b0..4612845db19 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -21,19 +21,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __PORTER_H */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 7bed32d8553..09ef2a848bd 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -21,19 +21,7 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __SILK_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h index 1278ba63f4f..f98ebb324f3 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -25,19 +25,7 @@ /* SCIF */ #define CFG_SCIF_A -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __STOUT_H */ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index 58c2e88c0b7..3298e627e53 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -12,17 +12,4 @@ #include "rcar-gen3-common.h" -/* Environment compatibility */ - -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x0 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - #endif /* __V3HSK_H */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 270088ad94f..5c0fd6d171b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -38,6 +38,7 @@ enum uclass_id { /* U-Boot uclasses start here - in alphabetical order */ UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */ UCLASS_ADC, /* Analog-to-digital converter */ + UCLASS_AES, /* AES cryptographic engine */ UCLASS_AHCI, /* SATA disk controller */ UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */ UCLASS_AXI, /* AXI bus */ diff --git a/include/limits.h b/include/limits.h index 1d0bbf69be7..a032bc5b84d 100644 --- a/include/limits.h +++ b/include/limits.h @@ -3,11 +3,61 @@ #ifndef _LIMITS_H #define _LIMITS_H -#define INT_MAX 0x7fffffff -#define UINT_MAX 0xffffffffU +#define SCHAR_MAX __SCHAR_MAX__ +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define UCHAR_MAX (SCHAR_MAX * 2 + 1) + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MAX UCHAR_MAX +#define CHAR_MIN 0 +#else +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#endif + +#define SHRT_MAX __SHRT_MAX__ +#define SHRT_MIN (-SHRT_MAX - 1) +#define USHRT_MAX (SHRT_MAX * 2 + 1) + +#define INT_MAX __INT_MAX__ +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (INT_MAX * 2U + 1U) + +#define LONG_MAX __LONG_MAX__ +#define LONG_MIN (-LONG_MAX - 1L) +#define ULONG_MAX (LONG_MAX * 2UL + 1UL) + +#define LLONG_MAX __LONG_LONG_MAX__ +#define LLONG_MIN (-LLONG_MAX - 1LL) +#define ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) + +#define U8_MAX UCHAR_MAX +#define S8_MAX SCHAR_MAX +#define S8_MIN SCHAR_MIN +#define U16_MAX USHRT_MAX +#define S16_MAX SHRT_MAX +#define S16_MIN SHRT_MIN +#define U32_MAX UINT_MAX +#define S32_MAX INT_MAX +#define S32_MIN INT_MIN +#define U64_MAX ULLONG_MAX +#define S64_MAX LLONG_MAX +#define S64_MIN LLONG_MIN + +#define UINT8_MAX U8_MAX +#define INT8_MAX S8_MAX +#define INT8_MIN S8_MIN +#define UINT16_MAX U16_MAX +#define INT16_MAX S16_MAX +#define INT16_MIN S16_MIN +#define UINT32_MAX U32_MAX +#define INT32_MAX S32_MAX +#define INT32_MIN S32_MIN +#define UINT64_MAX U64_MAX +#define INT64_MAX S64_MAX +#define INT64_MIN S64_MIN + #define CHAR_BIT 8 -#define UINT32_MAX 0xffffffffU -#define UINT64_MAX 0xffffffffffffffffULL #if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD)) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9467edd65ab..e0443ecac84 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -5,32 +5,6 @@ #include <linux/printk.h> /* for printf/pr_* utilities */ #include <limits.h> -#define USHRT_MAX ((u16)(~0U)) -#define SHRT_MAX ((s16)(USHRT_MAX>>1)) -#define SHRT_MIN ((s16)(-SHRT_MAX - 1)) -#define INT_MIN (-INT_MAX - 1) -#define LONG_MAX ((long)(~0UL>>1)) -#define LONG_MIN (-LONG_MAX - 1) -#define ULONG_MAX (~0UL) -#define LLONG_MAX ((long long)(~0ULL>>1)) -#define LLONG_MIN (-LLONG_MAX - 1) -#define ULLONG_MAX (~0ULL) - -#define U8_MAX ((u8)~0U) -#define S8_MAX ((s8)(U8_MAX>>1)) -#define S8_MIN ((s8)(-S8_MAX - 1)) -#define U16_MAX ((u16)~0U) -#define S16_MAX ((s16)(U16_MAX>>1)) -#define S16_MIN ((s16)(-S16_MAX - 1)) -#define U32_MAX ((u32)~0U) -#define S32_MAX ((s32)(U32_MAX>>1)) -#define S32_MIN ((s32)(-S32_MAX - 1)) -#define U64_MAX ((u64)~0ULL) -#define S64_MAX ((s64)(U64_MAX>>1)) -#define S64_MIN ((s64)(-S64_MAX - 1)) - -#define INT32_MAX S32_MAX - #define STACK_MAGIC 0xdeadbeef #define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) diff --git a/include/stdint.h b/include/stdint.h index dea83c8226a..90fd2bdee08 100644 --- a/include/stdint.h +++ b/include/stdint.h @@ -9,6 +9,6 @@ #ifndef __UB_STDINT_H #define __UB_STDINT_H -#define UINT8_MAX 0xff +#include <limits.h> #endif diff --git a/include/tca642x.h b/include/tca642x.h deleted file mode 100644 index c0a3cef5bd5..00000000000 --- a/include/tca642x.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright 2013 Texas Instruments, Inc. - * Author: Dan Murphy <dmurphy@ti.com> - * - * Derived work from the pca953x.c driver - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __TCA642X_H_ -#define __TCA642X_H_ - -#ifdef CONFIG_CMD_TCA642X -enum { - TCA642X_CMD_INFO, - TCA642X_CMD_DEVICE, - TCA642X_CMD_OUTPUT, - TCA642X_CMD_INPUT, - TCA642X_CMD_INVERT, -}; -#endif - -#define TCA642X_OUT_LOW 0 -#define TCA642X_OUT_HIGH 1 -#define TCA642X_POL_NORMAL 0 -#define TCA642X_POL_INVERT 1 -#define TCA642X_DIR_OUT 0 -#define TCA642X_DIR_IN 1 - -/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CFG_SYS_I2C_TCA642X_ADDR -#define CFG_SYS_I2C_TCA642X_ADDR (~0) -#endif - -/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM -#define CFG_SYS_I2C_TCA642X_BUS_NUM (0) -#endif - -struct tca642x_bank_info { - uint8_t input_reg; - uint8_t output_reg; - uint8_t polarity_reg; - uint8_t configuration_reg; -}; - -int tca642x_set_val(uchar chip, uint8_t gpio_bank, - uint8_t reg_bit, uint8_t data); -int tca642x_set_pol(uchar chip, uint8_t gpio_bank, - uint8_t reg_bit, uint8_t data); -int tca642x_set_dir(uchar chip, uint8_t gpio_bank, - uint8_t reg_bit, uint8_t data); -int tca642x_get_val(uchar chip, uint8_t gpio_bank); -int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]); - -#endif /* __TCA642X_H_ */ diff --git a/include/tsi148.h b/include/tsi148.h deleted file mode 100644 index a9f353b9080..00000000000 --- a/include/tsi148.h +++ /dev/null @@ -1,201 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com - * - * base on universe.h by - * - * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com - */ - -#ifndef _tsi148_h -#define _tsi148_h - -#ifndef PCI_DEVICE_ID_TUNDRA_TSI148 -#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148 -#endif - -typedef struct _TSI148 TSI148; -typedef struct _OUTBOUND OUTBOUND; -typedef struct _INBOUND INBOUND; -typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; - -struct _OUTBOUND { - unsigned int otsau; /* 0x000 Outbound start upper */ - unsigned int otsal; /* 0x004 Outbouud start lower */ - unsigned int oteau; /* 0x008 Outbound end upper */ - unsigned int oteal; /* 0x00c Outbound end lower */ - unsigned int otofu; /* 0x010 Outbound translation upper */ - unsigned int otofl; /* 0x014 Outbound translation lower */ - unsigned int otbs; /* 0x018 Outbound translation 2eSST */ - unsigned int otat; /* 0x01c Outbound translation attr */ -}; - -struct _INBOUND { - unsigned int itsau; /* 0x000 inbound start upper */ - unsigned int itsal; /* 0x004 inbouud start lower */ - unsigned int iteau; /* 0x008 inbound end upper */ - unsigned int iteal; /* 0x00c inbound end lower */ - unsigned int itofu; /* 0x010 inbound translation upper */ - unsigned int itofl; /* 0x014 inbound translation lower */ - unsigned int itat; /* 0x018 inbound translation attr */ - unsigned int spare; /* 0x01c not used */ -}; - -struct _TSI148 { - unsigned int pci_id; /* 0x000 */ - unsigned int pci_csr; /* 0x004 */ - unsigned int pci_class; /* 0x008 */ - unsigned int pci_misc0; /* 0x00c */ - unsigned int pci_mbarl; /* 0x010 */ - unsigned int pci_mbarh; /* 0x014 */ - unsigned int spare0[(0x03c-0x018)/4]; /* 0x018 */ - unsigned int pci_misc1; /* 0x03c */ - unsigned int pci_pcixcap; /* 0x040 */ - unsigned int pci_pcixstat; /* 0x044 */ - unsigned int spare1[(0x100-0x048)/4]; /* 0x048 */ - OUTBOUND outbound[8]; /* 0x100 */ - unsigned int viack[8]; /* 0x204 */ - unsigned int rmwau; /* 0x220 */ - unsigned int rmwal; /* 0x224 */ - unsigned int rmwen; /* 0x228 */ - unsigned int rmwc; /* 0x22c */ - unsigned int rmws; /* 0x230 */ - unsigned int vmctrl; /* 0x234 */ - unsigned int vctrl; /* 0x238 */ - unsigned int vstat; /* 0x23c */ - unsigned int pcsr; /* 0x240 */ - unsigned int spare2[3]; /* 0x244 - 0x24c */ - unsigned int vmefl; /* 0x250 */ - unsigned int spare3[3]; /* 0x254 - 0x25c */ - unsigned int veau; /* 0x260 */ - unsigned int veal; /* 0x264 */ - unsigned int veat; /* 0x268 */ - unsigned int spare4[1]; /* 0x26c */ - unsigned int edpau; /* 0x270 */ - unsigned int edpal; /* 0x274 */ - unsigned int edpxa; /* 0x278 */ - unsigned int edpxs; /* 0x27c */ - unsigned int edpat; /* 0x280 */ - unsigned int spare5[31]; /* 0x284 - 0x2fc */ - INBOUND inbound[8]; /* 0x100 */ - unsigned int gbau; /* 0x400 */ - unsigned int gbal; /* 0x404 */ - unsigned int gcsrat; /* 0x408 */ - unsigned int cbau; /* 0x40c */ - unsigned int cbal; /* 0x410 */ - unsigned int crgat; /* 0x414 */ - unsigned int crou; /* 0x418 */ - unsigned int crol; /* 0x41c */ - unsigned int crat; /* 0x420 */ - unsigned int lmbau; /* 0x424 */ - unsigned int lmbal; /* 0x428 */ - unsigned int lmat; /* 0x42c */ - unsigned int r64bcu; /* 0x430 */ - unsigned int r64bcl; /* 0x434 */ - unsigned int bpgtr; /* 0x438 */ - unsigned int bpctr; /* 0x43c */ - unsigned int vicr; /* 0x440 */ - unsigned int spare6[1]; /* 0x444 */ - unsigned int inten; /* 0x448 */ - unsigned int inteo; /* 0x44c */ - unsigned int ints; /* 0x450 */ - unsigned int intc; /* 0x454 */ - unsigned int intm1; /* 0x458 */ - unsigned int intm2; /* 0x45c */ - unsigned int spare7[40]; /* 0x460 - 0x4fc */ - unsigned int dctl0; /* 0x500 */ - unsigned int dsta0; /* 0x504 */ - unsigned int dcsau0; /* 0x508 */ - unsigned int dcsal0; /* 0x50c */ - unsigned int dcdau0; /* 0x510 */ - unsigned int dcdal0; /* 0x514 */ - unsigned int dclau0; /* 0x518 */ - unsigned int dclal0; /* 0x51c */ - unsigned int dsau0; /* 0x520 */ - unsigned int dsal0; /* 0x524 */ - unsigned int ddau0; /* 0x528 */ - unsigned int ddal0; /* 0x52c */ - unsigned int dsat0; /* 0x530 */ - unsigned int ddat0; /* 0x534 */ - unsigned int dnlau0; /* 0x538 */ - unsigned int dnlal0; /* 0x53c */ - unsigned int dcnt0; /* 0x540 */ - unsigned int ddbs0; /* 0x544 */ - unsigned int r20[14]; /* 0x548 - 0x57c */ - unsigned int dctl1; /* 0x580 */ - unsigned int dsta1; /* 0x584 */ - unsigned int dcsau1; /* 0x588 */ - unsigned int dcsal1; /* 0x58c */ - unsigned int dcdau1; /* 0x590 */ - unsigned int dcdal1; /* 0x594 */ - unsigned int dclau1; /* 0x598 */ - unsigned int dclal1; /* 0x59c */ - unsigned int dsau1; /* 0x5a0 */ - unsigned int dsal1; /* 0x5a4 */ - unsigned int ddau1; /* 0x5a8 */ - unsigned int ddal1; /* 0x5ac */ - unsigned int dsat1; /* 0x5b0 */ - unsigned int ddat1; /* 0x5b4 */ - unsigned int dnlau1; /* 0x5b8 */ - unsigned int dnlal1; /* 0x5bc */ - unsigned int dcnt1; /* 0x5c0 */ - unsigned int ddbs1; /* 0x5c4 */ - unsigned int r21[14]; /* 0x5c8 - 0x5fc */ - unsigned int devi_veni_2; /* 0x600 */ - unsigned int gctrl_ga_revid; /* 0x604 */ - unsigned int semaphore0_1_2_3; /* 0x608 */ - unsigned int semaphore4_5_6_7; /* 0x60c */ - unsigned int mbox0; /* 0x610 */ - unsigned int mbox1; /* 0x614 */ - unsigned int mbox2; /* 0x618 */ - unsigned int mbox3; /* 0x61c */ - unsigned int r22[629]; /* 0x620 - 0xff0 */ - unsigned int csrbcr; /* 0xff4 */ - unsigned int csrbsr; /* 0xff8 */ - unsigned int cbar; /* 0xffc */ -}; - -#define IRQ_VOWN 0x0001 -#define IRQ_VIRQ1 0x0002 -#define IRQ_VIRQ2 0x0004 -#define IRQ_VIRQ3 0x0008 -#define IRQ_VIRQ4 0x0010 -#define IRQ_VIRQ5 0x0020 -#define IRQ_VIRQ6 0x0040 -#define IRQ_VIRQ7 0x0080 -#define IRQ_DMA 0x0100 -#define IRQ_LERR 0x0200 -#define IRQ_VERR 0x0400 -#define IRQ_res 0x0800 -#define IRQ_IACK 0x1000 -#define IRQ_SWINT 0x2000 -#define IRQ_SYSFAIL 0x4000 -#define IRQ_ACFAIL 0x8000 - -struct _TDMA_CMD_PACKET { - unsigned int dctl; /* DMA Control */ - unsigned int dtbc; /* Transfer Byte Count */ - unsigned int dlv; /* PCI Address */ - unsigned int res1; /* Reserved */ - unsigned int dva; /* Vme Address */ - unsigned int res2; /* Reserved */ - unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ - unsigned int res3; /* Reserved */ -}; - -#define VME_AM_A16 0x01 -#define VME_AM_A24 0x02 -#define VME_AM_A32 0x03 -#define VME_AM_Axx 0x03 -#define VME_AM_USR 0x04 -#define VME_AM_SUP 0x08 -#define VME_AM_DATA 0x10 -#define VME_AM_PROG 0x20 -#define VME_AM_Mxx (VME_AM_DATA | VME_AM_PROG) - -#define VME_FLAG_D8 0x01 -#define VME_FLAG_D16 0x02 -#define VME_FLAG_D32 0x03 -#define VME_FLAG_Dxx 0x03 - -#endif diff --git a/include/uboot_aes.h b/include/uboot_aes.h index d2583bed992..592b7dbee43 100644 --- a/include/uboot_aes.h +++ b/include/uboot_aes.h @@ -7,6 +7,8 @@ #ifndef _AES_REF_H_ #define _AES_REF_H_ +#include <errno.h> + #ifdef USE_HOSTCC /* Define compat stuff for use in fw_* tools. */ typedef unsigned char u8; @@ -107,4 +109,253 @@ void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst, void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks); +/* An AES block filled with zeros */ +static const u8 AES_ZERO_BLOCK[AES_BLOCK_LENGTH] = { 0 }; +struct udevice; + +/** + * struct struct aes_ops - Driver model for AES related operations + * + * The uclass interface is implemented by AES crypto devices which use driver model. + * + * Some AES crypto devices use key slots to store the key for the encrypt/decrypt + * operations, while others may simply pass the key on each operation. + * + * In case the device does not implement hardware slots, driver can emulate or simply + * store one active key slot at 0 in the driver state and pass it on each underlying + * hw calls for AES operations. + * + * Note that some devices like Tegra AES engine may contain preloaded keys by bootrom, + * thus in those cases the set_key_for_key_slot() may be skipped. + * + * Sequence for a series of AES CBC encryption, one decryption and a CMAC hash example + * with 128bits key at slot 0 would be as follow: + * + * set_key_for_key_slot(DEV, 128, KEY, 0); + * select_key_slot(DEV, 128, 0); + * aes_cbc_encrypt(DEV, IV1, SRC1, DST1, LEN1); + * aes_cbc_encrypt(DEV, IV2, SRC2, DST2, LEN2); + * aes_cbc_decrypt(DEV, IV3, SRC3, DST3, LEN3); + */ +struct aes_ops { + /** + * available_key_slots() - How many key slots this AES device has + * + * @dev The AES udevice + * @return Available slots to use, 0 for none + */ + int (*available_key_slots)(struct udevice *dev); + + /** + * select_key_slot() - Selects the AES key slot to use for following operations + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @slot The key slot to set as selected + * @return 0 on success, negative value on failure + */ + int (*select_key_slot)(struct udevice *dev, u32 key_size, u8 slot); + + /** + * set_key_for_key_slot() - Sets the AES key to use for specified key slot + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @key An AES key to set + * @slot The slot to load the key at + * @return 0 on success, negative value on failure + */ + int (*set_key_for_key_slot)(struct udevice *dev, u32 key_size, u8 *key, + u8 slot); + + /** + * aes_ecb_encrypt() - Encrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_ecb_encrypt)(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + + /** + * aes_ecb_decrypt() - Decrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_ecb_decrypt)(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + + /** + * aes_cbc_encrypt() - Encrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_cbc_encrypt)(struct udevice *dev, u8 *iv, + u8 *src, u8 *dst, u32 num_aes_blocks); + + /** + * aes_cbc_decrypt() - Decrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_cbc_decrypt)(struct udevice *dev, u8 *iv, + u8 *src, u8 *dst, u32 num_aes_blocks); +}; + +#define aes_get_ops(dev) ((struct aes_ops *)(dev)->driver->ops) + +#if CONFIG_IS_ENABLED(DM_AES) + +/** + * dm_aes_get_available_key_slots - How many key slots this AES device has + * + * @dev The AES udevice + * Return: Available slots to use, 0 for none, -ve on failure + */ +int dm_aes_get_available_key_slots(struct udevice *dev); + +/** + * dm_aes_select_key_slot - Selects the AES key slot to use for following operations + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @slot The key slot to set as selected + * Return: 0 on success, -ve on failure + */ +int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot); + +/** + * dm_aes_set_key_for_key_slot - Sets the AES key to use for specified key slot + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @key An AES key to set + * @slot The slot to load the key at + * Return: 0 on success, negative value on failure + */ +int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, u8 slot); + +/** + * dm_aes_ecb_encrypt - Encrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_ecb_decrypt - Decrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_cbc_encrypt - Encrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_cbc_decrypt - Decrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_cmac - Hashes the input data with AES-CMAC, putting the result into dst. + * The key slot must be selected already. + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination for hash result + * @num_aes_blocks Number of AES blocks to encrypt + * Return: 0 on success, negative value on failure. + */ +int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + +#else + +static inline int dm_aes_get_available_key_slots(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + return -ENOSYS; +} + +static inline int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, + u8 slot) +{ + return -ENOSYS; +} + +static inline int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + return -ENOSYS; +} + +#endif /* CONFIG_DM_AES */ + #endif /* _AES_REF_H_ */ diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c index 7415d685ee1..c4bfb2cec61 100644 --- a/lib/ecdsa/ecdsa-libcrypto.c +++ b/lib/ecdsa/ecdsa-libcrypto.c @@ -519,10 +519,12 @@ static int do_add(struct signer *ctx, void *fdt, const char *key_node_name, if (ret < 0) return ret; - ret = fdt_setprop_string(fdt, key_node, FIT_KEY_REQUIRED, - info->require_keys); - if (ret < 0) - return ret; + if (info->require_keys) { + ret = fdt_setprop_string(fdt, key_node, FIT_KEY_REQUIRED, + info->require_keys); + if (ret < 0) + return ret; + } return key_node; } diff --git a/lib/lmb.c b/lib/lmb.c index 45b26512a5b..e5a0677e3f9 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -762,6 +762,7 @@ int lmb_alloc_mem(enum lmb_mem_type type, u64 align, phys_addr_t *addr, switch (type) { case LMB_MEM_ALLOC_ANY: *addr = LMB_ALLOC_ANYWHERE; + fallthrough; case LMB_MEM_ALLOC_MAX: ret = _lmb_alloc_base(size, align, addr, flags); break; diff --git a/test/Kconfig b/test/Kconfig index 31016eedbf8..77e7cad3984 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -122,6 +122,7 @@ endif # UNIT_TEST config POST bool "Power On Self Test support" + depends on ARM || PPC help See doc/README.POST for more details diff --git a/test/dm/Makefile b/test/dm/Makefile index 917dafe7d22..d15859eca30 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -29,6 +29,7 @@ obj-(CONFIG_DM_GPIO) += gpio.o obj-y += irq.o endif obj-$(CONFIG_ADC) += adc.o +obj-$(CONFIG_AES_SOFTWARE) += aes.o obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_AXI) += axi.o obj-$(CONFIG_BLK) += blk.o diff --git a/test/dm/aes.c b/test/dm/aes.c new file mode 100644 index 00000000000..702e4db2b35 --- /dev/null +++ b/test/dm/aes.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for the driver model AES API + * + * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/test.h> +#include <uboot_aes.h> +#include <test/test.h> +#include <test/ut.h> + +#define AES128_KEYSIZE 128 + +static int dm_test_aes(struct unit_test_state *uts) +{ + struct udevice *dev; + u8 test_key[AES128_KEY_LENGTH] = { 0x63, 0x68, 0x69, 0x63, 0x6b, 0x65, 0x6e, 0x20, + 0x74, 0x65, 0x72, 0x69, 0x79, 0x61, 0x6b, 0x69 }; + u8 test_iv[AES128_KEY_LENGTH] = { 0 }; + + u8 test_input[AES_BLOCK_LENGTH] = { 0x49, 0x20, 0x77, 0x6f, 0x75, 0x6c, 0x64, 0x20, + 0x6c, 0x69, 0x6b, 0x65, 0x20, 0x74, 0x68, 0x65 }; + u8 exp_output[AES_BLOCK_LENGTH] = { 0x97, 0x68, 0x72, 0x68, 0xd6, 0xec, 0xcc, 0xc0, + 0xc0, 0x7b, 0x25, 0xe2, 0x5e, 0xcf, 0xe5, 0x84 }; + u8 exp_cmac[AES_BLOCK_LENGTH] = { 0xfc, 0x89, 0x20, 0xc8, 0x46, 0x97, 0xb1, 0x3d, + 0x31, 0x2c, 0xc2, 0x49, 0x5c, 0x5a, 0x0b, 0x9f }; + u8 test_output[AES_BLOCK_LENGTH]; + + ut_assertok(uclass_first_device_err(UCLASS_AES, &dev)); + + /* software AES exposes 2 key slots */ + ut_asserteq(2, dm_aes_get_available_key_slots(dev)); + + ut_assertok(dm_aes_select_key_slot(dev, AES128_KEYSIZE, 0)); + ut_assertok(dm_aes_set_key_for_key_slot(dev, AES128_KEYSIZE, test_key, 0)); + + ut_assertok(dm_aes_ecb_encrypt(dev, test_input, test_output, 1)); + ut_assertok(memcmp(exp_output, test_output, 16)); + + ut_assertok(dm_aes_ecb_decrypt(dev, test_output, test_output, 1)); + ut_assertok(memcmp(test_input, test_output, 16)); + + ut_assertok(dm_aes_cbc_encrypt(dev, test_iv, test_input, test_output, 1)); + ut_assertok(memcmp(exp_output, test_output, 16)); + + ut_assertok(dm_aes_cbc_decrypt(dev, test_iv, test_output, test_output, 1)); + ut_assertok(memcmp(test_input, test_output, 16)); + + ut_assertok(dm_aes_cmac(dev, test_input, test_output, 1)); + ut_assertok(memcmp(exp_cmac, test_output, 16)); + + return 0; +} + +DM_TEST(dm_test_aes, UTF_SCAN_FDT); diff --git a/tools/binman/control.py b/tools/binman/control.py index af447d792a7..1307222591d 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -8,12 +8,11 @@ from collections import OrderedDict import glob try: - import importlib.resources + import importlib.resources as importlib_resources except ImportError: # pragma: no cover # for Python 3.6 import importlib_resources import os -import pkg_resources import re import sys @@ -96,7 +95,7 @@ def _ReadMissingBlobHelp(): msg = '' return tag, msg - my_data = pkg_resources.resource_string(__name__, 'missing-blob-help') + my_data = importlib_resources.files(__package__).joinpath('missing-blob-help').read_bytes() re_tag = re.compile(r"^([-\.a-z0-9]+):$") result = {} tag = None @@ -151,8 +150,9 @@ def GetEntryModules(include_testing=True): Returns: Set of paths to entry class filenames """ - glob_list = pkg_resources.resource_listdir(__name__, 'etype') - glob_list = [fname for fname in glob_list if fname.endswith('.py')] + entries = importlib_resources.files(__package__).joinpath('etype') + glob_list = [entry.name for entry in entries.iterdir() + if entry.name.endswith('.py') and entry.is_file()] return set([os.path.splitext(os.path.basename(item))[0] for item in glob_list if include_testing or '_testing' not in item]) @@ -831,7 +831,7 @@ def Binman(args): global state if args.full_help: - with importlib.resources.path('binman', 'README.rst') as readme: + with importlib_resources.path('binman', 'README.rst') as readme: tools.print_full_help(str(readme)) return 0 diff --git a/tools/binman/etype/renesas_rcar4_sa0.py b/tools/binman/etype/renesas_rcar4_sa0.py new file mode 100644 index 00000000000..3a7c0988fdc --- /dev/null +++ b/tools/binman/etype/renesas_rcar4_sa0.py @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> +# +# Entry-type module for generating the Renesas R-Car Gen4 SA0 header. +# + +import os +import struct + +from binman.etype.section import Entry_section +from dtoc import fdt_util +from u_boot_pylib import tools + +RCAR_GEN4_SF_HEADER_SIZE = 0x40000 +RCAR_GEN4_SF_MAX_LOAD_SIZE = 0xec000 + +class Entry_renesas_rcar4_sa0(Entry_section): + """Renesas R-Car Gen4 SA0 generator""" + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.required_props = ['renesas,loader-address'] + + def ReadNode(self): + self.loader_address = fdt_util.GetInt(self._node, 'renesas,loader-address') + super().ReadNode() + + def BuildSectionData(self, required): + data = super().BuildSectionData(required)[RCAR_GEN4_SF_HEADER_SIZE:] + + # Offset 0x0000 / Value 0x00000000 + header = struct.pack('<I', 0) + header += tools.get_bytes(0xff, 0x3008) + # Offset 0x300c / Value 0x00000000 + header += struct.pack('<I', 0) + header += tools.get_bytes(0xff, 0x144) + # Offset 0x3154 / Value (payload load address) + header += struct.pack('<I', self.loader_address) + header += tools.get_bytes(0xff, 0x10c) + # Offset 0x3264 / Value (payload size in 4-byte words, aligned to 4k) + header += struct.pack('<I', int(tools.align(len(data), 0x1000) / 4)) + header += tools.get_bytes(0xff, 0x3cd98) + if len(data) > RCAR_GEN4_SF_MAX_LOAD_SIZE: + self.Raise(f'SRAM data longer than {RCAR_GEN4_SF_MAX_LOAD_SIZE} Bytes') + + return header + data diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 8225216fbec..a90db3c9351 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -5586,6 +5586,17 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFile('347_bl1.dts') self.assertEqual(ATF_BL1_DATA, data[:len(ATF_BL1_DATA)]) + def testRenesasRCarGen4SA0Image(self): + """Test that binman can produce an Renesas R-Car Gen4 SA0 image""" + self._DoTestFile('348_renesas_rcar4_sa0.dts') + + def testRenesasRCarGen4SA0ImageSize(self): + """Test that binman can not produce large Renesas R-Car Gen4 SA0 image""" + with self.assertRaises(ValueError) as exc: + self._DoTestFile('349_renesas_rcar4_sa0_size.dts') + self.assertIn("Node '/binman/renesas-rcar4-sa0': SRAM data longer than 966656 Bytes", + str(exc.exception)) + def testFitFdtOper(self): """Check handling of a specified FIT operation""" entry_args = { diff --git a/tools/binman/test/348_renesas_rcar4_sa0.dts b/tools/binman/test/348_renesas_rcar4_sa0.dts new file mode 100644 index 00000000000..4a8717520f2 --- /dev/null +++ b/tools/binman/test/348_renesas_rcar4_sa0.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + renesas-rcar4-sa0 { + filename = "sa0.bin"; + renesas,loader-address = <0x10>; + }; + }; +}; diff --git a/tools/binman/test/349_renesas_rcar4_sa0_size.dts b/tools/binman/test/349_renesas_rcar4_sa0_size.dts new file mode 100644 index 00000000000..eaf4507260b --- /dev/null +++ b/tools/binman/test/349_renesas_rcar4_sa0_size.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + renesas-rcar4-sa0 { + filename = "sa0.bin"; + renesas,loader-address = <0x10>; + + fill { /* Oversize fill to cover size check */ + size = <0x140000>; + fill-byte = [ff]; + }; + }; + }; +}; diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c index 74fcadca63e..40213b7887f 100644 --- a/tools/bmp_logo.c +++ b/tools/bmp_logo.c @@ -15,7 +15,7 @@ typedef struct bitmap_s { /* bitmap description */ #define DEFAULT_CMAP_SIZE 16 /* size of default color map */ -void usage(const char *prog) +static void usage(const char *prog) { fprintf(stderr, "Usage: %s [--gen-info|--gen-data|--gen-bmp] file\n", prog); @@ -24,7 +24,7 @@ void usage(const char *prog) /* * Neutralize little endians. */ -uint16_t le_short(uint16_t x) +static uint16_t le_short(uint16_t x) { uint16_t val; uint8_t *p = (uint8_t *)(&x); @@ -35,14 +35,14 @@ uint16_t le_short(uint16_t x) return val; } -void skip_bytes (FILE *fp, int n) +static void skip_bytes(FILE *fp, int n) { while (n-- > 0) fgetc (fp); } __attribute__ ((__noreturn__)) -int error (char * msg, FILE *fp) +static int error(char *msg, FILE *fp) { fprintf (stderr, "ERROR: %s\n", msg); @@ -51,7 +51,7 @@ int error (char * msg, FILE *fp) exit (EXIT_FAILURE); } -void gen_info(bitmap_t *b, uint16_t n_colors) +static void gen_info(bitmap_t *b, uint16_t n_colors) { printf("/*\n" " * Automatically generated by \"tools/bmp_logo\"\n" diff --git a/tools/fit_image.c b/tools/fit_image.c index 8717dc9a3b1..ad0ffa39c6a 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -846,7 +846,7 @@ static int fit_handle_file(struct image_tool_params *params) char tmpfile[MKIMAGE_MAX_TMPFILE_LEN]; char bakfile[MKIMAGE_MAX_TMPFILE_LEN + 4] = {0}; char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN]; - size_t size_inc; + int size_inc; int ret = EXIT_FAILURE; /* Flattened Image Tree (FIT) format handling */ diff --git a/tools/gen_ethaddr_crc.c b/tools/gen_ethaddr_crc.c index e73d0429a04..27717207580 100644 --- a/tools/gen_ethaddr_crc.c +++ b/tools/gen_ethaddr_crc.c @@ -16,12 +16,12 @@ #define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1) /* with separators */ #define ARP_HLEN_LAZY (ARP_HLEN * 2) /* separatorless hardware address length */ -uint8_t nibble_to_hex(const char *nibble, bool lo) +static uint8_t nibble_to_hex(const char *nibble, bool lo) { return (strtol(nibble, NULL, 16) << (lo ? 0 : 4)) & (lo ? 0x0f : 0xf0); } -int process_mac(const char *mac_address) +static int process_mac(const char *mac_address) { uint8_t ethaddr[ARP_HLEN + 1] = { 0x00 }; uint_fast8_t i = 0; @@ -45,7 +45,7 @@ int process_mac(const char *mac_address) return 0; } -void print_usage(char *cmdname) +static void print_usage(char *cmdname) { printf("Usage: %s <mac_address>\n", cmdname); puts("<mac_address> may be with or without separators."); diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index 885cdb1390e..944ec82e761 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -47,7 +47,7 @@ static void usage(const char *exec_name) exec_name); } -long int xstrtol(const char *s) +static long int xstrtol(const char *s) { long int tmp; diff --git a/tools/ublimage.c b/tools/ublimage.c index a1bd807bfa0..8926d5b178b 100644 --- a/tools/ublimage.c +++ b/tools/ublimage.c @@ -219,7 +219,7 @@ static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd, parse_cfg_file(ublhdr, params->imagename); } -int ublimage_check_params(struct image_tool_params *params) +static int ublimage_check_params(struct image_tool_params *params) { if (!params) return CFG_INVALID; |