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-rw-r--r--arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi122
-rw-r--r--arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi (renamed from arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi)371
-rw-r--r--arch/arm/dts/k3-am642-r5-sk.dts2
-rw-r--r--arch/arm/mach-k3/am642_init.c1
-rw-r--r--arch/arm/mach-k3/common.c4
-rw-r--r--arch/arm/mach-k3/include/mach/am62_hardware.h17
-rw-r--r--arch/arm/mach-k3/include/mach/am64_hardware.h26
-rw-r--r--arch/arm/mach-k3/include/mach/am6_hardware.h25
-rw-r--r--arch/arm/mach-k3/include/mach/hardware.h19
-rw-r--r--arch/arm/mach-k3/include/mach/j721e_hardware.h25
-rw-r--r--arch/arm/mach-k3/include/mach/j721s2_hardware.h25
-rw-r--r--arch/arm/mach-k3/security.c14
-rw-r--r--board/nokia/rx51/lowlevel_init.S4
-rw-r--r--drivers/dma/dma-uclass.c17
-rw-r--r--drivers/dma/sandbox-dma-test.c4
-rw-r--r--drivers/dma/ti-edma3.c33
-rw-r--r--drivers/dma/ti/k3-udma.c4
-rw-r--r--drivers/phy/ti/phy-j721e-wiz.c75
-rw-r--r--drivers/watchdog/omap_wdt.c2
-rw-r--r--include/dma-uclass.h4
20 files changed, 410 insertions, 384 deletions
diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
index 9a008df7506..491412119b1 100644
--- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
@@ -1,8 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * This file was generated by the AM64x_DDR4_RegConfig_Tool, Revision: 0.6.0
- * This file was generated on Oct 26 2020
- * DDR4 Frequency = 800MHz (1600MTs)
+ * This file was generated with the
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
+ * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
+ * DDR Type: DDR4
+ * Frequency = 800MHz (1600MTs)
* Density: 16Gb
* Number of Ranks: 1
*/
@@ -49,11 +51,11 @@
#define DDRSS_CTL_35_DATA 0x00000000
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
-#define DDRSS_CTL_38_DATA 0x04000918
+#define DDRSS_CTL_38_DATA 0x0400091C
#define DDRSS_CTL_39_DATA 0x1C1C1C1C
-#define DDRSS_CTL_40_DATA 0x04000918
+#define DDRSS_CTL_40_DATA 0x0400091C
#define DDRSS_CTL_41_DATA 0x1C1C1C1C
-#define DDRSS_CTL_42_DATA 0x04000918
+#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002706
@@ -215,22 +217,22 @@
#define DDRSS_CTL_201_DATA 0x00000000
#define DDRSS_CTL_202_DATA 0x00000000
#define DDRSS_CTL_203_DATA 0x00000000
-#define DDRSS_CTL_204_DATA 0x00041400
+#define DDRSS_CTL_204_DATA 0x00042400
#define DDRSS_CTL_205_DATA 0x00000301
#define DDRSS_CTL_206_DATA 0x00000000
-#define DDRSS_CTL_207_DATA 0x00000414
+#define DDRSS_CTL_207_DATA 0x00000424
#define DDRSS_CTL_208_DATA 0x00000301
#define DDRSS_CTL_209_DATA 0x00000000
-#define DDRSS_CTL_210_DATA 0x00000414
+#define DDRSS_CTL_210_DATA 0x00000424
#define DDRSS_CTL_211_DATA 0x00000301
#define DDRSS_CTL_212_DATA 0x00000000
-#define DDRSS_CTL_213_DATA 0x00000414
+#define DDRSS_CTL_213_DATA 0x00000424
#define DDRSS_CTL_214_DATA 0x00000301
#define DDRSS_CTL_215_DATA 0x00000000
-#define DDRSS_CTL_216_DATA 0x00000414
+#define DDRSS_CTL_216_DATA 0x00000424
#define DDRSS_CTL_217_DATA 0x00000301
#define DDRSS_CTL_218_DATA 0x00000000
-#define DDRSS_CTL_219_DATA 0x00000414
+#define DDRSS_CTL_219_DATA 0x00000424
#define DDRSS_CTL_220_DATA 0x00000301
#define DDRSS_CTL_221_DATA 0x00000000
#define DDRSS_CTL_222_DATA 0x00000000
@@ -247,12 +249,12 @@
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
-#define DDRSS_CTL_236_DATA 0x00000401
-#define DDRSS_CTL_237_DATA 0x00000401
-#define DDRSS_CTL_238_DATA 0x00000401
-#define DDRSS_CTL_239_DATA 0x00000401
-#define DDRSS_CTL_240_DATA 0x00000401
-#define DDRSS_CTL_241_DATA 0x00000401
+#define DDRSS_CTL_236_DATA 0x00001401
+#define DDRSS_CTL_237_DATA 0x00001401
+#define DDRSS_CTL_238_DATA 0x00001401
+#define DDRSS_CTL_239_DATA 0x00001401
+#define DDRSS_CTL_240_DATA 0x00001401
+#define DDRSS_CTL_241_DATA 0x00001401
#define DDRSS_CTL_242_DATA 0x00000493
#define DDRSS_CTL_243_DATA 0x00000493
#define DDRSS_CTL_244_DATA 0x00000493
@@ -341,9 +343,9 @@
#define DDRSS_CTL_327_DATA 0x00000C01
#define DDRSS_CTL_328_DATA 0x00000000
#define DDRSS_CTL_329_DATA 0x00000000
-#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_330_DATA 0x00000000
#define DDRSS_CTL_331_DATA 0x01000000
-#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_332_DATA 0x00000100
#define DDRSS_CTL_333_DATA 0x00010000
#define DDRSS_CTL_334_DATA 0x00000000
#define DDRSS_CTL_335_DATA 0x00000000
@@ -386,8 +388,8 @@
#define DDRSS_CTL_372_DATA 0x06060C06
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x02000000
-#define DDRSS_CTL_375_DATA 0x03020101
-#define DDRSS_CTL_376_DATA 0x00000303
+#define DDRSS_CTL_375_DATA 0x05020101
+#define DDRSS_CTL_376_DATA 0x00000505
#define DDRSS_CTL_377_DATA 0x02020200
#define DDRSS_CTL_378_DATA 0x02020202
#define DDRSS_CTL_379_DATA 0x02020202
@@ -403,7 +405,7 @@
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
-#define DDRSS_CTL_392_DATA 0x0A0B0302
+#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_395_DATA 0x00000200
@@ -412,7 +414,7 @@
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
-#define DDRSS_CTL_401_DATA 0x0A0B0302
+#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_404_DATA 0x00000200
@@ -421,7 +423,7 @@
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
-#define DDRSS_CTL_410_DATA 0x0A0B0302
+#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
@@ -601,14 +603,14 @@
#define DDRSS_PI_164_DATA 0x00007800
#define DDRSS_PI_165_DATA 0x00780078
#define DDRSS_PI_166_DATA 0x00141414
-#define DDRSS_PI_167_DATA 0x00000038
-#define DDRSS_PI_168_DATA 0x00000038
-#define DDRSS_PI_169_DATA 0x00040038
+#define DDRSS_PI_167_DATA 0x0000003A
+#define DDRSS_PI_168_DATA 0x0000003A
+#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0xC8040009
-#define DDRSS_PI_172_DATA 0x04000918
-#define DDRSS_PI_173_DATA 0x000918C8
-#define DDRSS_PI_174_DATA 0x0018C804
+#define DDRSS_PI_172_DATA 0x0400091C
+#define DDRSS_PI_173_DATA 0x00091CC8
+#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_177_DATA 0x00000118
@@ -621,14 +623,14 @@
#define DDRSS_PI_184_DATA 0x010C010C
#define DDRSS_PI_185_DATA 0x0000010C
#define DDRSS_PI_186_DATA 0x00000000
-#define DDRSS_PI_187_DATA 0x03000000
-#define DDRSS_PI_188_DATA 0x01010303
+#define DDRSS_PI_187_DATA 0x05000000
+#define DDRSS_PI_188_DATA 0x01010505
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x00181818
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
-#define DDRSS_PI_193_DATA 0x0B000000
-#define DDRSS_PI_194_DATA 0x0A0A0B0B
+#define DDRSS_PI_193_DATA 0x0D000000
+#define DDRSS_PI_194_DATA 0x0A0A0D0D
#define DDRSS_PI_195_DATA 0x0303030A
#define DDRSS_PI_196_DATA 0x00000000
#define DDRSS_PI_197_DATA 0x00000000
@@ -656,15 +658,15 @@
#define DDRSS_PI_219_DATA 0x001600C8
#define DDRSS_PI_220_DATA 0x010100C8
#define DDRSS_PI_221_DATA 0x00001B01
-#define DDRSS_PI_222_DATA 0x1F0F0051
-#define DDRSS_PI_223_DATA 0x03000001
-#define DDRSS_PI_224_DATA 0x001B0A0B
-#define DDRSS_PI_225_DATA 0x1F0F0051
-#define DDRSS_PI_226_DATA 0x03000001
-#define DDRSS_PI_227_DATA 0x001B0A0B
-#define DDRSS_PI_228_DATA 0x1F0F0051
-#define DDRSS_PI_229_DATA 0x03000001
-#define DDRSS_PI_230_DATA 0x00000A0B
+#define DDRSS_PI_222_DATA 0x1F0F0053
+#define DDRSS_PI_223_DATA 0x05000001
+#define DDRSS_PI_224_DATA 0x001B0A0D
+#define DDRSS_PI_225_DATA 0x1F0F0053
+#define DDRSS_PI_226_DATA 0x05000001
+#define DDRSS_PI_227_DATA 0x001B0A0D
+#define DDRSS_PI_228_DATA 0x1F0F0053
+#define DDRSS_PI_229_DATA 0x05000001
+#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
@@ -731,52 +733,52 @@
#define DDRSS_PI_294_DATA 0x01000000
#define DDRSS_PI_295_DATA 0x00020201
#define DDRSS_PI_296_DATA 0x00000000
-#define DDRSS_PI_297_DATA 0x00000414
+#define DDRSS_PI_297_DATA 0x00000424
#define DDRSS_PI_298_DATA 0x00000301
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
-#define DDRSS_PI_302_DATA 0x00000401
+#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
-#define DDRSS_PI_305_DATA 0x00000414
+#define DDRSS_PI_305_DATA 0x00000424
#define DDRSS_PI_306_DATA 0x00000301
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
-#define DDRSS_PI_310_DATA 0x00000401
+#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
-#define DDRSS_PI_313_DATA 0x00000414
+#define DDRSS_PI_313_DATA 0x00000424
#define DDRSS_PI_314_DATA 0x00000301
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
-#define DDRSS_PI_318_DATA 0x00000401
+#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
-#define DDRSS_PI_321_DATA 0x00000414
+#define DDRSS_PI_321_DATA 0x00000424
#define DDRSS_PI_322_DATA 0x00000301
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
-#define DDRSS_PI_326_DATA 0x00000401
+#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
-#define DDRSS_PI_329_DATA 0x00000414
+#define DDRSS_PI_329_DATA 0x00000424
#define DDRSS_PI_330_DATA 0x00000301
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
-#define DDRSS_PI_334_DATA 0x00000401
+#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
-#define DDRSS_PI_337_DATA 0x00000414
+#define DDRSS_PI_337_DATA 0x00000424
#define DDRSS_PI_338_DATA 0x00000301
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
-#define DDRSS_PI_342_DATA 0x00000401
+#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
#define DDRSS_PHY_0_DATA 0x04C00000
@@ -871,7 +873,7 @@
#define DDRSS_PHY_89_DATA 0x31804000
#define DDRSS_PHY_90_DATA 0x04BF0340
#define DDRSS_PHY_91_DATA 0x01008080
-#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_92_DATA 0x04050001
#define DDRSS_PHY_93_DATA 0x00000504
#define DDRSS_PHY_94_DATA 0x42100010
#define DDRSS_PHY_95_DATA 0x010C053E
@@ -1127,7 +1129,7 @@
#define DDRSS_PHY_345_DATA 0x31804000
#define DDRSS_PHY_346_DATA 0x04BF0340
#define DDRSS_PHY_347_DATA 0x01008080
-#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_348_DATA 0x04050001
#define DDRSS_PHY_349_DATA 0x00000504
#define DDRSS_PHY_350_DATA 0x42100010
#define DDRSS_PHY_351_DATA 0x010C053E
@@ -2113,7 +2115,7 @@
#define DDRSS_PHY_1331_DATA 0x00004410
#define DDRSS_PHY_1332_DATA 0x00000000
#define DDRSS_PHY_1333_DATA 0x00000046
-#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1334_DATA 0x00000400
#define DDRSS_PHY_1335_DATA 0x00000008
#define DDRSS_PHY_1336_DATA 0x00000000
#define DDRSS_PHY_1337_DATA 0x00000000
@@ -2184,4 +2186,4 @@
#define DDRSS_PHY_1402_DATA 0x01990000
#define DDRSS_PHY_1403_DATA 0x300D3F11
#define DDRSS_PHY_1404_DATA 0x01990000
-#define DDRSS_PHY_1405_DATA 0x20040001
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi
index dde5ab150da..f225c1f0674 100644
--- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
+++ b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi
@@ -1,18 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated with the
- * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00
- * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time)
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
+ * Wed Feb 02 2022 16:59:34 GMT-0600 (Central Standard Time)
* DDR Type: LPDDR4
- * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz
+ * F0 = 50MHz F1 = 800MHz F2 = 800MHz
* Density (per channel): 16Gb
* Number of Ranks: 1
-*/
+ */
#define DDRSS_PLL_FHS_CNT 6
-#define DDRSS_PLL_FREQUENCY_1 333350000
-#define DDRSS_PLL_FREQUENCY_2 333350000
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -25,14 +24,14 @@
#define DDRSS_CTL_8_DATA 0x000186A0
#define DDRSS_CTL_9_DATA 0x00000005
#define DDRSS_CTL_10_DATA 0x00000064
-#define DDRSS_CTL_11_DATA 0x000208D6
-#define DDRSS_CTL_12_DATA 0x00145856
+#define DDRSS_CTL_11_DATA 0x00027100
+#define DDRSS_CTL_12_DATA 0x00186A00
#define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000536
-#define DDRSS_CTL_15_DATA 0x000208D6
-#define DDRSS_CTL_16_DATA 0x00145856
+#define DDRSS_CTL_14_DATA 0x00000640
+#define DDRSS_CTL_15_DATA 0x00027100
+#define DDRSS_CTL_16_DATA 0x00186A00
#define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000536
+#define DDRSS_CTL_18_DATA 0x00000640
#define DDRSS_CTL_19_DATA 0x01010100
#define DDRSS_CTL_20_DATA 0x01010100
#define DDRSS_CTL_21_DATA 0x01000110
@@ -48,8 +47,8 @@
#define DDRSS_CTL_31_DATA 0x00000000
#define DDRSS_CTL_32_DATA 0x00000000
#define DDRSS_CTL_33_DATA 0x00000000
-#define DDRSS_CTL_34_DATA 0x02000010
-#define DDRSS_CTL_35_DATA 0x00001B1B
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00002020
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0000040C
@@ -62,64 +61,64 @@
#define DDRSS_CTL_45_DATA 0x00000700
#define DDRSS_CTL_46_DATA 0x09090004
#define DDRSS_CTL_47_DATA 0x00000203
-#define DDRSS_CTL_48_DATA 0x00290006
-#define DDRSS_CTL_49_DATA 0x0909001D
-#define DDRSS_CTL_50_DATA 0x0000150C
-#define DDRSS_CTL_51_DATA 0x00290006
-#define DDRSS_CTL_52_DATA 0x0909001D
-#define DDRSS_CTL_53_DATA 0x0900150C
+#define DDRSS_CTL_48_DATA 0x00320007
+#define DDRSS_CTL_49_DATA 0x09090023
+#define DDRSS_CTL_50_DATA 0x0000190F
+#define DDRSS_CTL_51_DATA 0x00320007
+#define DDRSS_CTL_52_DATA 0x09090023
+#define DDRSS_CTL_53_DATA 0x0900190F
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x040006DB
#define DDRSS_CTL_56_DATA 0x09092004
-#define DDRSS_CTL_57_DATA 0x00000A0A
-#define DDRSS_CTL_58_DATA 0x05005B68
-#define DDRSS_CTL_59_DATA 0x09092005
-#define DDRSS_CTL_60_DATA 0x00000A0A
-#define DDRSS_CTL_61_DATA 0x05005B68
-#define DDRSS_CTL_62_DATA 0x03042005
+#define DDRSS_CTL_57_DATA 0x00000C0A
+#define DDRSS_CTL_58_DATA 0x06006DB0
+#define DDRSS_CTL_59_DATA 0x09092006
+#define DDRSS_CTL_60_DATA 0x00000C0A
+#define DDRSS_CTL_61_DATA 0x06006DB0
+#define DDRSS_CTL_62_DATA 0x03042006
#define DDRSS_CTL_63_DATA 0x04050002
-#define DDRSS_CTL_64_DATA 0x0E0D0E0D
+#define DDRSS_CTL_64_DATA 0x100F100F
#define DDRSS_CTL_65_DATA 0x01010008
-#define DDRSS_CTL_66_DATA 0x041A1A07
-#define DDRSS_CTL_67_DATA 0x030E0E03
-#define DDRSS_CTL_68_DATA 0x00000E0E
+#define DDRSS_CTL_66_DATA 0x041F1F07
+#define DDRSS_CTL_67_DATA 0x03111103
+#define DDRSS_CTL_68_DATA 0x00001111
#define DDRSS_CTL_69_DATA 0x00000101
#define DDRSS_CTL_70_DATA 0x00000000
#define DDRSS_CTL_71_DATA 0x01000000
#define DDRSS_CTL_72_DATA 0x00130803
#define DDRSS_CTL_73_DATA 0x000000BB
-#define DDRSS_CTL_74_DATA 0x000000FE
-#define DDRSS_CTL_75_DATA 0x00000A20
-#define DDRSS_CTL_76_DATA 0x000000FE
-#define DDRSS_CTL_77_DATA 0x00000A20
+#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_75_DATA 0x00000C28
+#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_77_DATA 0x00000C28
#define DDRSS_CTL_78_DATA 0x00000005
#define DDRSS_CTL_79_DATA 0x0000000A
#define DDRSS_CTL_80_DATA 0x00000010
-#define DDRSS_CTL_81_DATA 0x0000007F
-#define DDRSS_CTL_82_DATA 0x0000013D
-#define DDRSS_CTL_83_DATA 0x0000007F
-#define DDRSS_CTL_84_DATA 0x0000013D
+#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_82_DATA 0x0000017E
+#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_84_DATA 0x0000017E
#define DDRSS_CTL_85_DATA 0x03004000
#define DDRSS_CTL_86_DATA 0x00001201
-#define DDRSS_CTL_87_DATA 0x00050005
-#define DDRSS_CTL_88_DATA 0x00000005
+#define DDRSS_CTL_87_DATA 0x00060005
+#define DDRSS_CTL_88_DATA 0x00000006
#define DDRSS_CTL_89_DATA 0x00000000
-#define DDRSS_CTL_90_DATA 0x05101008
+#define DDRSS_CTL_90_DATA 0x05121208
#define DDRSS_CTL_91_DATA 0x05030A05
-#define DDRSS_CTL_92_DATA 0x05030A05
-#define DDRSS_CTL_93_DATA 0x01030A05
+#define DDRSS_CTL_92_DATA 0x05030C06
+#define DDRSS_CTL_93_DATA 0x01030C06
#define DDRSS_CTL_94_DATA 0x02010201
#define DDRSS_CTL_95_DATA 0x00001401
-#define DDRSS_CTL_96_DATA 0x01030014
-#define DDRSS_CTL_97_DATA 0x01030103
-#define DDRSS_CTL_98_DATA 0x00000103
+#define DDRSS_CTL_96_DATA 0x01360014
+#define DDRSS_CTL_97_DATA 0x01360136
+#define DDRSS_CTL_98_DATA 0x00000136
#define DDRSS_CTL_99_DATA 0x00000000
#define DDRSS_CTL_100_DATA 0x05010303
-#define DDRSS_CTL_101_DATA 0x0A040505
-#define DDRSS_CTL_102_DATA 0x05050203
-#define DDRSS_CTL_103_DATA 0x030A0505
-#define DDRSS_CTL_104_DATA 0x05050502
-#define DDRSS_CTL_105_DATA 0x03030305
+#define DDRSS_CTL_101_DATA 0x0C040505
+#define DDRSS_CTL_102_DATA 0x06050203
+#define DDRSS_CTL_103_DATA 0x030C0605
+#define DDRSS_CTL_104_DATA 0x05060502
+#define DDRSS_CTL_105_DATA 0x03030306
#define DDRSS_CTL_106_DATA 0x03010000
#define DDRSS_CTL_107_DATA 0x00010000
#define DDRSS_CTL_108_DATA 0x00000000
@@ -140,20 +139,20 @@
#define DDRSS_CTL_123_DATA 0x00002EC0
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x0000051D
-#define DDRSS_CTL_126_DATA 0x00028800
-#define DDRSS_CTL_127_DATA 0x00028800
-#define DDRSS_CTL_128_DATA 0x00028800
-#define DDRSS_CTL_129_DATA 0x00028800
-#define DDRSS_CTL_130_DATA 0x00028800
+#define DDRSS_CTL_126_DATA 0x00030A00
+#define DDRSS_CTL_127_DATA 0x00030A00
+#define DDRSS_CTL_128_DATA 0x00030A00
+#define DDRSS_CTL_129_DATA 0x00030A00
+#define DDRSS_CTL_130_DATA 0x00030A00
#define DDRSS_CTL_131_DATA 0x00000000
-#define DDRSS_CTL_132_DATA 0x000046E0
-#define DDRSS_CTL_133_DATA 0x00028800
-#define DDRSS_CTL_134_DATA 0x00028800
-#define DDRSS_CTL_135_DATA 0x00028800
-#define DDRSS_CTL_136_DATA 0x00028800
-#define DDRSS_CTL_137_DATA 0x00028800
+#define DDRSS_CTL_132_DATA 0x00005518
+#define DDRSS_CTL_133_DATA 0x00030A00
+#define DDRSS_CTL_134_DATA 0x00030A00
+#define DDRSS_CTL_135_DATA 0x00030A00
+#define DDRSS_CTL_136_DATA 0x00030A00
+#define DDRSS_CTL_137_DATA 0x00030A00
#define DDRSS_CTL_138_DATA 0x00000000
-#define DDRSS_CTL_139_DATA 0x000046E0
+#define DDRSS_CTL_139_DATA 0x00005518
#define DDRSS_CTL_140_DATA 0x00000000
#define DDRSS_CTL_141_DATA 0x00000000
#define DDRSS_CTL_142_DATA 0x00000000
@@ -209,12 +208,12 @@
#define DDRSS_CTL_192_DATA 0x0005000A
#define DDRSS_CTL_193_DATA 0x0404000D
#define DDRSS_CTL_194_DATA 0x0000000D
-#define DDRSS_CTL_195_DATA 0x00430086
-#define DDRSS_CTL_196_DATA 0x050500A7
-#define DDRSS_CTL_197_DATA 0x000000A7
-#define DDRSS_CTL_198_DATA 0x00430086
-#define DDRSS_CTL_199_DATA 0x050500A7
-#define DDRSS_CTL_200_DATA 0x000000A7
+#define DDRSS_CTL_195_DATA 0x005000A0
+#define DDRSS_CTL_196_DATA 0x060600C8
+#define DDRSS_CTL_197_DATA 0x000000C8
+#define DDRSS_CTL_198_DATA 0x005000A0
+#define DDRSS_CTL_199_DATA 0x060600C8
+#define DDRSS_CTL_200_DATA 0x000000C8
#define DDRSS_CTL_201_DATA 0x00000000
#define DDRSS_CTL_202_DATA 0x00000000
#define DDRSS_CTL_203_DATA 0x00000000
@@ -239,11 +238,11 @@
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000031
-#define DDRSS_CTL_225_DATA 0x00000031
-#define DDRSS_CTL_226_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x000000B1
+#define DDRSS_CTL_226_DATA 0x000000B1
#define DDRSS_CTL_227_DATA 0x00000031
-#define DDRSS_CTL_228_DATA 0x00000031
-#define DDRSS_CTL_229_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
#define DDRSS_CTL_230_DATA 0x00000000
#define DDRSS_CTL_231_DATA 0x00000000
#define DDRSS_CTL_232_DATA 0x00000000
@@ -323,12 +322,12 @@
#define DDRSS_CTL_306_DATA 0x00400100
#define DDRSS_CTL_307_DATA 0x00080032
#define DDRSS_CTL_308_DATA 0x01000200
-#define DDRSS_CTL_309_DATA 0x029B0040
-#define DDRSS_CTL_310_DATA 0x00020014
+#define DDRSS_CTL_309_DATA 0x03200040
+#define DDRSS_CTL_310_DATA 0x00020018
#define DDRSS_CTL_311_DATA 0x00400100
-#define DDRSS_CTL_312_DATA 0x0014029B
+#define DDRSS_CTL_312_DATA 0x00180320
#define DDRSS_CTL_313_DATA 0x00030000
-#define DDRSS_CTL_314_DATA 0x00220022
+#define DDRSS_CTL_314_DATA 0x00280028
#define DDRSS_CTL_315_DATA 0x00000100
#define DDRSS_CTL_316_DATA 0x01010000
#define DDRSS_CTL_317_DATA 0x00000000
@@ -344,9 +343,9 @@
#define DDRSS_CTL_327_DATA 0x00000C01
#define DDRSS_CTL_328_DATA 0x01000100
#define DDRSS_CTL_329_DATA 0x00000000
-#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_330_DATA 0x00000000
#define DDRSS_CTL_331_DATA 0x01030303
-#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_332_DATA 0x00000001
#define DDRSS_CTL_333_DATA 0x00000000
#define DDRSS_CTL_334_DATA 0x00000000
#define DDRSS_CTL_335_DATA 0x00000000
@@ -390,14 +389,14 @@
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x01050503
#define DDRSS_CTL_375_DATA 0x05020201
-#define DDRSS_CTL_376_DATA 0x08080B0B
+#define DDRSS_CTL_376_DATA 0x08080C0C
#define DDRSS_CTL_377_DATA 0x00080308
-#define DDRSS_CTL_378_DATA 0x000C030E
-#define DDRSS_CTL_379_DATA 0x000C0310
-#define DDRSS_CTL_380_DATA 0x0C0C0810
+#define DDRSS_CTL_378_DATA 0x000B030E
+#define DDRSS_CTL_379_DATA 0x000B0310
+#define DDRSS_CTL_380_DATA 0x0B0B0810
#define DDRSS_CTL_381_DATA 0x01000000
-#define DDRSS_CTL_382_DATA 0x03010301
-#define DDRSS_CTL_383_DATA 0x04000101
+#define DDRSS_CTL_382_DATA 0x03020301
+#define DDRSS_CTL_383_DATA 0x04000102
#define DDRSS_CTL_384_DATA 0x1B000004
#define DDRSS_CTL_385_DATA 0x00000176
#define DDRSS_CTL_386_DATA 0x00000200
@@ -407,24 +406,24 @@
#define DDRSS_CTL_390_DATA 0x00000693
#define DDRSS_CTL_391_DATA 0x00000E9C
#define DDRSS_CTL_392_DATA 0x03050202
-#define DDRSS_CTL_393_DATA 0x00240201
-#define DDRSS_CTL_394_DATA 0x00001440
+#define DDRSS_CTL_393_DATA 0x00250201
+#define DDRSS_CTL_394_DATA 0x00001850
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
#define DDRSS_CTL_397_DATA 0x00000200
#define DDRSS_CTL_398_DATA 0x00000200
-#define DDRSS_CTL_399_DATA 0x00005B20
-#define DDRSS_CTL_400_DATA 0x0000CA80
-#define DDRSS_CTL_401_DATA 0x080D0402
-#define DDRSS_CTL_402_DATA 0x00240405
-#define DDRSS_CTL_403_DATA 0x00001440
+#define DDRSS_CTL_399_DATA 0x00006D68
+#define DDRSS_CTL_400_DATA 0x0000F320
+#define DDRSS_CTL_401_DATA 0x070D0402
+#define DDRSS_CTL_402_DATA 0x00250405
+#define DDRSS_CTL_403_DATA 0x00001850
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
-#define DDRSS_CTL_408_DATA 0x00005B20
-#define DDRSS_CTL_409_DATA 0x0000CA80
-#define DDRSS_CTL_410_DATA 0x080D0402
+#define DDRSS_CTL_408_DATA 0x00006D68
+#define DDRSS_CTL_409_DATA 0x0000F320
+#define DDRSS_CTL_410_DATA 0x070D0402
#define DDRSS_CTL_411_DATA 0x00000405
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
@@ -483,7 +482,7 @@
#define DDRSS_PI_43_DATA 0x00000000
#define DDRSS_PI_44_DATA 0x00000000
#define DDRSS_PI_45_DATA 0x00010100
-#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_46_DATA 0x00000015
#define DDRSS_PI_47_DATA 0x000007D0
#define DDRSS_PI_48_DATA 0x00000300
#define DDRSS_PI_49_DATA 0x00000000
@@ -602,8 +601,8 @@
#define DDRSS_PI_162_DATA 0x00000000
#define DDRSS_PI_163_DATA 0x00000000
#define DDRSS_PI_164_DATA 0x00000800
-#define DDRSS_PI_165_DATA 0x00640064
-#define DDRSS_PI_166_DATA 0x000E0E01
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00101001
#define DDRSS_PI_167_DATA 0x00000034
#define DDRSS_PI_168_DATA 0x00000042
#define DDRSS_PI_169_DATA 0x00020042
@@ -614,84 +613,84 @@
#define DDRSS_PI_174_DATA 0x001C0000
#define DDRSS_PI_175_DATA 0x00000013
#define DDRSS_PI_176_DATA 0x000000BB
-#define DDRSS_PI_177_DATA 0x000000FE
-#define DDRSS_PI_178_DATA 0x00000A20
-#define DDRSS_PI_179_DATA 0x000000FE
-#define DDRSS_PI_180_DATA 0x04000A20
+#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_178_DATA 0x00000C28
+#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_180_DATA 0x04000C28
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001501
-#define DDRSS_PI_183_DATA 0x001B001B
+#define DDRSS_PI_183_DATA 0x001D001D
#define DDRSS_PI_184_DATA 0x01000100
#define DDRSS_PI_185_DATA 0x00000100
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05050503
-#define DDRSS_PI_188_DATA 0x01010B0B
+#define DDRSS_PI_188_DATA 0x01010C0C
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x000C0C0A
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x04000000
-#define DDRSS_PI_194_DATA 0x04020909
+#define DDRSS_PI_194_DATA 0x04020808
#define DDRSS_PI_195_DATA 0x04040204
#define DDRSS_PI_196_DATA 0x00090031
-#define DDRSS_PI_197_DATA 0x000F0037
-#define DDRSS_PI_198_DATA 0x000F0037
+#define DDRSS_PI_197_DATA 0x00110039
+#define DDRSS_PI_198_DATA 0x00110039
#define DDRSS_PI_199_DATA 0x01010101
-#define DDRSS_PI_200_DATA 0x0001000D
-#define DDRSS_PI_201_DATA 0x000100A7
-#define DDRSS_PI_202_DATA 0x010000A7
+#define DDRSS_PI_200_DATA 0x0002000D
+#define DDRSS_PI_201_DATA 0x000200C8
+#define DDRSS_PI_202_DATA 0x010000C8
#define DDRSS_PI_203_DATA 0x000E000E
-#define DDRSS_PI_204_DATA 0x00A80100
-#define DDRSS_PI_205_DATA 0x010000A8
-#define DDRSS_PI_206_DATA 0x00A800A8
+#define DDRSS_PI_204_DATA 0x00C90100
+#define DDRSS_PI_205_DATA 0x010000C9
+#define DDRSS_PI_206_DATA 0x00C900C9
#define DDRSS_PI_207_DATA 0x32103200
#define DDRSS_PI_208_DATA 0x01013210
#define DDRSS_PI_209_DATA 0x0A070601
-#define DDRSS_PI_210_DATA 0x0B08070D
-#define DDRSS_PI_211_DATA 0x0B08070D
+#define DDRSS_PI_210_DATA 0x0D09070D
+#define DDRSS_PI_211_DATA 0x0D09070D
#define DDRSS_PI_212_DATA 0x000C000D
#define DDRSS_PI_213_DATA 0x00001000
#define DDRSS_PI_214_DATA 0x00000C00
#define DDRSS_PI_215_DATA 0x00001000
#define DDRSS_PI_216_DATA 0x00000C00
#define DDRSS_PI_217_DATA 0x02001000
-#define DDRSS_PI_218_DATA 0x0015000D
-#define DDRSS_PI_219_DATA 0x001500A7
-#define DDRSS_PI_220_DATA 0x000000A7
+#define DDRSS_PI_218_DATA 0x0016000D
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x000000C8
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000101
#define DDRSS_PI_224_DATA 0x001D0204
-#define DDRSS_PI_225_DATA 0x32120059
+#define DDRSS_PI_225_DATA 0x32120058
#define DDRSS_PI_226_DATA 0x05000101
-#define DDRSS_PI_227_DATA 0x001D0409
-#define DDRSS_PI_228_DATA 0x32120059
+#define DDRSS_PI_227_DATA 0x001D0408
+#define DDRSS_PI_228_DATA 0x32120058
#define DDRSS_PI_229_DATA 0x05000101
-#define DDRSS_PI_230_DATA 0x00000409
+#define DDRSS_PI_230_DATA 0x00000408
#define DDRSS_PI_231_DATA 0x05030900
#define DDRSS_PI_232_DATA 0x00040900
#define DDRSS_PI_233_DATA 0x0000062B
#define DDRSS_PI_234_DATA 0x20010004
#define DDRSS_PI_235_DATA 0x0A0A0A03
-#define DDRSS_PI_236_DATA 0x0E090000
-#define DDRSS_PI_237_DATA 0x0E09000D
-#define DDRSS_PI_238_DATA 0x00005244
-#define DDRSS_PI_239_DATA 0x2003001D
-#define DDRSS_PI_240_DATA 0x0A0A0A0A
-#define DDRSS_PI_241_DATA 0x0E090000
-#define DDRSS_PI_242_DATA 0x0E09000D
-#define DDRSS_PI_243_DATA 0x00005244
-#define DDRSS_PI_244_DATA 0x2003001D
-#define DDRSS_PI_245_DATA 0x0A0A0A0A
+#define DDRSS_PI_236_DATA 0x11090000
+#define DDRSS_PI_237_DATA 0x1009000F
+#define DDRSS_PI_238_DATA 0x000062B8
+#define DDRSS_PI_239_DATA 0x20030023
+#define DDRSS_PI_240_DATA 0x0C0A0C0C
+#define DDRSS_PI_241_DATA 0x11090000
+#define DDRSS_PI_242_DATA 0x1009000F
+#define DDRSS_PI_243_DATA 0x000062B8
+#define DDRSS_PI_244_DATA 0x20030023
+#define DDRSS_PI_245_DATA 0x0C0A0C0C
#define DDRSS_PI_246_DATA 0x00000000
#define DDRSS_PI_247_DATA 0x00000176
#define DDRSS_PI_248_DATA 0x00000E9C
-#define DDRSS_PI_249_DATA 0x00001440
-#define DDRSS_PI_250_DATA 0x0000CA80
-#define DDRSS_PI_251_DATA 0x00001440
-#define DDRSS_PI_252_DATA 0x0000CA80
-#define DDRSS_PI_253_DATA 0x01030014
-#define DDRSS_PI_254_DATA 0x03030103
+#define DDRSS_PI_249_DATA 0x00001850
+#define DDRSS_PI_250_DATA 0x0000F320
+#define DDRSS_PI_251_DATA 0x00001850
+#define DDRSS_PI_252_DATA 0x0000F320
+#define DDRSS_PI_253_DATA 0x01360014
+#define DDRSS_PI_254_DATA 0x03030136
#define DDRSS_PI_255_DATA 0x00000003
#define DDRSS_PI_256_DATA 0x00000000
#define DDRSS_PI_257_DATA 0x05030503
@@ -701,23 +700,23 @@
#define DDRSS_PI_261_DATA 0x00000005
#define DDRSS_PI_262_DATA 0x00000064
#define DDRSS_PI_263_DATA 0x00000014
-#define DDRSS_PI_264_DATA 0x000208D6
+#define DDRSS_PI_264_DATA 0x00027100
#define DDRSS_PI_265_DATA 0x000186A0
#define DDRSS_PI_266_DATA 0x00000005
-#define DDRSS_PI_267_DATA 0x00000536
-#define DDRSS_PI_268_DATA 0x00000103
-#define DDRSS_PI_269_DATA 0x000208D6
+#define DDRSS_PI_267_DATA 0x00000640
+#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_269_DATA 0x00027100
#define DDRSS_PI_270_DATA 0x000186A0
#define DDRSS_PI_271_DATA 0x00000005
-#define DDRSS_PI_272_DATA 0x00000536
-#define DDRSS_PI_273_DATA 0x01000103
+#define DDRSS_PI_272_DATA 0x00000640
+#define DDRSS_PI_273_DATA 0x01000136
#define DDRSS_PI_274_DATA 0x00320040
#define DDRSS_PI_275_DATA 0x00010008
-#define DDRSS_PI_276_DATA 0x029B0040
-#define DDRSS_PI_277_DATA 0x00010014
-#define DDRSS_PI_278_DATA 0x029B0040
-#define DDRSS_PI_279_DATA 0x00000314
-#define DDRSS_PI_280_DATA 0x00280021
+#define DDRSS_PI_276_DATA 0x03200040
+#define DDRSS_PI_277_DATA 0x00010018
+#define DDRSS_PI_278_DATA 0x03200040
+#define DDRSS_PI_279_DATA 0x00000318
+#define DDRSS_PI_280_DATA 0x00280028
#define DDRSS_PI_281_DATA 0x03040404
#define DDRSS_PI_282_DATA 0x00000303
#define DDRSS_PI_283_DATA 0x02020101
@@ -745,7 +744,7 @@
#define DDRSS_PI_305_DATA 0x00000000
#define DDRSS_PI_306_DATA 0x00000024
#define DDRSS_PI_307_DATA 0x00000012
-#define DDRSS_PI_308_DATA 0x00000031
+#define DDRSS_PI_308_DATA 0x000000B1
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
#define DDRSS_PI_311_DATA 0x46000000
@@ -753,7 +752,7 @@
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
#define DDRSS_PI_315_DATA 0x00000012
-#define DDRSS_PI_316_DATA 0x00000031
+#define DDRSS_PI_316_DATA 0x000000B1
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
#define DDRSS_PI_319_DATA 0x46000000
@@ -769,7 +768,7 @@
#define DDRSS_PI_329_DATA 0x00000000
#define DDRSS_PI_330_DATA 0x00000024
#define DDRSS_PI_331_DATA 0x00000012
-#define DDRSS_PI_332_DATA 0x00000031
+#define DDRSS_PI_332_DATA 0x000000B1
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
#define DDRSS_PI_335_DATA 0x46000000
@@ -777,7 +776,7 @@
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
#define DDRSS_PI_339_DATA 0x00000012
-#define DDRSS_PI_340_DATA 0x00000031
+#define DDRSS_PI_340_DATA 0x000000B1
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
#define DDRSS_PI_343_DATA 0x46000000
@@ -869,29 +868,29 @@
#define DDRSS_PHY_84_DATA 0x00100010
#define DDRSS_PHY_85_DATA 0x00100010
#define DDRSS_PHY_86_DATA 0x00100010
-#define DDRSS_PHY_87_DATA 0x02000010
+#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
#define DDRSS_PHY_90_DATA 0x07AB0340
#define DDRSS_PHY_91_DATA 0x0000C0C0
-#define DDRSS_PHY_92_DATA 0x03040000
-#define DDRSS_PHY_93_DATA 0x00000403
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
#define DDRSS_PHY_94_DATA 0x42100010
#define DDRSS_PHY_95_DATA 0x010C053E
-#define DDRSS_PHY_96_DATA 0x000F0C1A
+#define DDRSS_PHY_96_DATA 0x000F0C1D
#define DDRSS_PHY_97_DATA 0x01000140
-#define DDRSS_PHY_98_DATA 0x00660120
+#define DDRSS_PHY_98_DATA 0x007A0120
#define DDRSS_PHY_99_DATA 0x00000C00
-#define DDRSS_PHY_100_DATA 0x000001AA
+#define DDRSS_PHY_100_DATA 0x000001CC
#define DDRSS_PHY_101_DATA 0x20100200
-#define DDRSS_PHY_102_DATA 0x00000004
+#define DDRSS_PHY_102_DATA 0x00000005
#define DDRSS_PHY_103_DATA 0x76543210
#define DDRSS_PHY_104_DATA 0x00000008
-#define DDRSS_PHY_105_DATA 0x032A032A
-#define DDRSS_PHY_106_DATA 0x032A032A
-#define DDRSS_PHY_107_DATA 0x032A032A
-#define DDRSS_PHY_108_DATA 0x032A032A
-#define DDRSS_PHY_109_DATA 0x0000032A
+#define DDRSS_PHY_105_DATA 0x034C034C
+#define DDRSS_PHY_106_DATA 0x034C034C
+#define DDRSS_PHY_107_DATA 0x034C034C
+#define DDRSS_PHY_108_DATA 0x034C034C
+#define DDRSS_PHY_109_DATA 0x0000034C
#define DDRSS_PHY_110_DATA 0x00008000
#define DDRSS_PHY_111_DATA 0x00800080
#define DDRSS_PHY_112_DATA 0x00800080
@@ -901,7 +900,7 @@
#define DDRSS_PHY_116_DATA 0x00800080
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
-#define DDRSS_PHY_119_DATA 0x01190080
+#define DDRSS_PHY_119_DATA 0x01800080
#define DDRSS_PHY_120_DATA 0x01A00001
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
@@ -1125,29 +1124,29 @@
#define DDRSS_PHY_340_DATA 0x00100010
#define DDRSS_PHY_341_DATA 0x00100010
#define DDRSS_PHY_342_DATA 0x00100010
-#define DDRSS_PHY_343_DATA 0x02000010
+#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
#define DDRSS_PHY_346_DATA 0x07AB0340
#define DDRSS_PHY_347_DATA 0x0000C0C0
-#define DDRSS_PHY_348_DATA 0x03040000
-#define DDRSS_PHY_349_DATA 0x00000403
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
#define DDRSS_PHY_350_DATA 0x42100010
#define DDRSS_PHY_351_DATA 0x010C053E
-#define DDRSS_PHY_352_DATA 0x000F0C1A
+#define DDRSS_PHY_352_DATA 0x000F0C1D
#define DDRSS_PHY_353_DATA 0x01000140
-#define DDRSS_PHY_354_DATA 0x00660120
+#define DDRSS_PHY_354_DATA 0x007A0120
#define DDRSS_PHY_355_DATA 0x00000C00
-#define DDRSS_PHY_356_DATA 0x000001AA
+#define DDRSS_PHY_356_DATA 0x000001CC
#define DDRSS_PHY_357_DATA 0x20100200
-#define DDRSS_PHY_358_DATA 0x00000004
+#define DDRSS_PHY_358_DATA 0x00000005
#define DDRSS_PHY_359_DATA 0x76543210
#define DDRSS_PHY_360_DATA 0x00000008
-#define DDRSS_PHY_361_DATA 0x032A032A
-#define DDRSS_PHY_362_DATA 0x032A032A
-#define DDRSS_PHY_363_DATA 0x032A032A
-#define DDRSS_PHY_364_DATA 0x032A032A
-#define DDRSS_PHY_365_DATA 0x0000032A
+#define DDRSS_PHY_361_DATA 0x034C034C
+#define DDRSS_PHY_362_DATA 0x034C034C
+#define DDRSS_PHY_363_DATA 0x034C034C
+#define DDRSS_PHY_364_DATA 0x034C034C
+#define DDRSS_PHY_365_DATA 0x0000034C
#define DDRSS_PHY_366_DATA 0x00008000
#define DDRSS_PHY_367_DATA 0x00800080
#define DDRSS_PHY_368_DATA 0x00800080
@@ -1157,7 +1156,7 @@
#define DDRSS_PHY_372_DATA 0x00800080
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
-#define DDRSS_PHY_375_DATA 0x01190080
+#define DDRSS_PHY_375_DATA 0x01800080
#define DDRSS_PHY_376_DATA 0x01A00001
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
@@ -1326,7 +1325,7 @@
#define DDRSS_PHY_541_DATA 0x003F0000
#define DDRSS_PHY_542_DATA 0x000F013F
#define DDRSS_PHY_543_DATA 0x0000000F
-#define DDRSS_PHY_544_DATA 0x000002CC
+#define DDRSS_PHY_544_DATA 0x020002CC
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
@@ -1582,7 +1581,7 @@
#define DDRSS_PHY_797_DATA 0x00000000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
-#define DDRSS_PHY_800_DATA 0x000002CC
+#define DDRSS_PHY_800_DATA 0x020002CC
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
@@ -1838,7 +1837,7 @@
#define DDRSS_PHY_1053_DATA 0x10000000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
-#define DDRSS_PHY_1056_DATA 0x000002CC
+#define DDRSS_PHY_1056_DATA 0x020002CC
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
@@ -2116,7 +2115,7 @@
#define DDRSS_PHY_1331_DATA 0x00004410
#define DDRSS_PHY_1332_DATA 0x00000000
#define DDRSS_PHY_1333_DATA 0x00000076
-#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1334_DATA 0x00000400
#define DDRSS_PHY_1335_DATA 0x00000008
#define DDRSS_PHY_1336_DATA 0x00000000
#define DDRSS_PHY_1337_DATA 0x00000000
@@ -2154,7 +2153,7 @@
#define DDRSS_PHY_1369_DATA 0x00000000
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
-#define DDRSS_PHY_1372_DATA 0x00000002
+#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
#define DDRSS_PHY_1375_DATA 0x03020000
@@ -2187,4 +2186,4 @@
#define DDRSS_PHY_1402_DATA 0x019900E0
#define DDRSS_PHY_1403_DATA 0x00018011
#define DDRSS_PHY_1404_DATA 0x0089FF00
-#define DDRSS_PHY_1405_DATA 0x20040001
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index cf3ba0e209c..97f44e220a3 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -9,7 +9,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
-#include "k3-am64-sk-lp4-1333MTs.dtsi"
+#include "k3-am64-sk-lp4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
/ {
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 8428322ed9a..0e30cc47f54 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -23,7 +23,6 @@
#include <mmc.h>
#include <dm/root.h>
-#define MCU_CTRL_MMR0_BASE 0x04500000
#define CTRLMMR_MCU_RST_CTRL 0x04518170
static void ctrl_mmr_unlock(void)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 14c37acbce7..227706e8dca 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -606,5 +606,9 @@ int misc_init_r(void)
printf("Failed to probe am65_cpsw_nuss driver\n");
}
+ /* Default FIT boot on non-GP devices */
+ if (get_device_type() != K3_DEVICE_TYPE_GP)
+ env_set("boot_fit", "1");
+
return 0;
}
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 9118d052042..278beb587f1 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -44,23 +44,6 @@
/* Backup Bootmode USB Config macros */
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
-/*
- * The CTRL_MMR0 memory space is divided into several equally-spaced
- * partitions, so defining the partition size allows us to determine
- * register addresses common to those partitions.
- */
-#define CTRL_MMR0_PARTITION_SIZE 0x4000
-
-/*
- * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
- * shared register definitions. The same registers are also used for
- * PADCFG_MMR lock/kick-mechanism.
- */
-#define CTRLMMR_LOCK_KICK0 0x1008
-#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
-#define CTRLMMR_LOCK_KICK1 0x100c
-#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
-
#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index e06e1f9532f..6c9332e2bd9 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -7,12 +7,13 @@
#ifndef __ASM_ARCH_AM64_HARDWARE_H
#define __ASM_ARCH_AM64_HARDWARE_H
+#define PADCFG_MMR1_BASE 0x000f0000
+#define MCU_PADCFG_MMR1_BASE 0x04080000
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x04500000
#define CTRL_MMR0_BASE 0x43000000
-#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
-
-#define PADCFG_MMR1_BASE 0xf0000
-#define MCU_PADCFG_MMR1_BASE 0x04080000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
@@ -35,23 +36,6 @@
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
-/*
- * The CTRL_MMR and PADCFG_MMR memory space is divided into several
- * equally-spaced partitions, so defining the partition size allows us to
- * determine register addresses common to those partitions.
- */
-#define CTRL_MMR0_PARTITION_SIZE 0x4000
-
-/*
- * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
- */
-#define CTRLMMR_LOCK_KICK0 0x01008
-#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
-#define CTRLMMR_LOCK_KICK1 0x0100c
-#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
-
#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
/* Use Last 2K as Scratch pad */
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index f533e22e061..f9f32918f7c 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -13,8 +13,10 @@
#endif
#define CTRL_MMR0_BASE 0x00100000
-#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x40f00000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0)
#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0
#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4)
@@ -28,27 +30,6 @@
#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9
#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9)
-#define WKUP_CTRL_MMR0_BASE 0x43000000
-#define MCU_CTRL_MMR0_BASE 0x40f00000
-
-/*
- * The CTRL_MMR0 memory space is divided into several equally-spaced
- * partitions, so defining the partition size allows us to determine
- * register addresses common to those partitions.
- */
-#define CTRL_MMR0_PARTITION_SIZE 0x4000
-
-/*
- * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
- * shared register definitions.
- */
-#define CTRLMMR_LOCK_KICK0 0x01008
-#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
-#define CTRLMMR_LOCK_KICK1 0x0100c
-#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
-
/* MCU SCRATCHPAD usage */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 028482b3b6d..d6d2cf6dc26 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -27,7 +27,7 @@
#endif
/* Assuming these addresses and definitions stay common across K3 devices */
-#define CTRLMMR_WKUP_JTAG_ID 0x43000014
+#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
#define JTAG_ID_PARTNO_SHIFT 12
@@ -43,6 +43,23 @@
#define SYS_STATUS_SUB_TYPE_MASK (0xf << 8)
#define SYS_STATUS_SUB_TYPE_VAL_FS 0xa
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
+ * shared register definitions. The same registers are also used for
+ * PADCFG_MMR lock/kick-mechanism.
+ */
+#define CTRLMMR_LOCK_KICK0 0x1008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK1 0x100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
#define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT"
struct rom_extended_boot_data {
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index b98f0a82f19..032cb2657ae 100644
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -12,9 +12,11 @@
#include <linux/bitops.h>
#endif
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x40f00000
#define CTRL_MMR0_BASE 0x00100000
-#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
@@ -24,33 +26,12 @@
#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
-#define WKUP_CTRL_MMR0_BASE 0x43000000
-#define MCU_CTRL_MMR0_BASE 0x40f00000
-
#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
-/*
- * The CTRL_MMR0 memory space is divided into several equally-spaced
- * partitions, so defining the partition size allows us to determine
- * register addresses common to those partitions.
- */
-#define CTRL_MMR0_PARTITION_SIZE 0x4000
-
-/*
- * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
- * shared register definitions.
- */
-#define CTRLMMR_LOCK_KICK0 0x01008
-#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
-#define CTRLMMR_LOCK_KICK1 0x0100c
-#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
-
/* ROM HANDOFF Structure location */
#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00
diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
index 23dfe2e9e9d..e47f40eac25 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
@@ -12,9 +12,11 @@
#include <linux/bitops.h>
#endif
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x40f00000
#define CTRL_MMR0_BASE 0x00100000
-#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
@@ -24,33 +26,12 @@
#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
-#define WKUP_CTRL_MMR0_BASE 0x43000000
-#define MCU_CTRL_MMR0_BASE 0x40f00000
-
#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
-/*
- * The CTRL_MMR0 memory space is divided into several equally-spaced
- * partitions, so defining the partition size allows us to determine
- * register addresses common to those partitions.
- */
-#define CTRL_MMR0_PARTITION_SIZE 0x4000
-
-/*
- * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
- * shared register definitions.
- */
-#define CTRLMMR_LOCK_KICK0 0x01008
-#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
-#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
-#define CTRLMMR_LOCK_KICK1 0x0100c
-#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
-
/* ROM HANDOFF Structure location */
#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index d8d41ec5154..092588f4b5e 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,6 +18,7 @@
#include <mach/spl.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
+#include <linux/dma-mapping.h>
#include "common.h"
@@ -47,7 +48,6 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
u32 image_size;
int ret;
- image_addr = (uintptr_t)*p_image;
image_size = *p_size;
if (!image_size)
@@ -80,13 +80,12 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
return;
}
+ /* Clean out image so it can be seen by system firmware */
+ image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL);
+
debug("Authenticating image at address 0x%016llx\n", image_addr);
debug("Authenticating image of size %d bytes\n", image_size);
- flush_dcache_range((unsigned long)image_addr,
- ALIGN((unsigned long)image_addr + image_size,
- ARCH_DMA_MINALIGN));
-
/* Authenticate image */
ret = proc_ops->proc_auth_boot_image(ti_sci, &image_addr, &image_size);
if (ret) {
@@ -94,10 +93,9 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
hang();
}
+ /* Invalidate any stale lines over data written by system firmware */
if (image_size)
- invalidate_dcache_range((unsigned long)image_addr,
- ALIGN((unsigned long)image_addr +
- image_size, ARCH_DMA_MINALIGN));
+ dma_unmap_single(image_addr, image_size, DMA_BIDIRECTIONAL);
/*
* The image_size returned may be 0 when the authentication process has
diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S
index 1cf8f8d8b2f..4b66e0a8614 100644
--- a/board/nokia/rx51/lowlevel_init.S
+++ b/board/nokia/rx51/lowlevel_init.S
@@ -7,7 +7,7 @@
#include <config.h>
kernoffs: /* offset of kernel image from this address */
- .word KERNEL_OFFSET - (. - CONFIG_SYS_TEXT_BASE)
+ .word . - CONFIG_SYS_TEXT_BASE - KERNEL_OFFSET
kernaddr: /* address of kernel after copying */
.word KERNEL_ADDRESS
@@ -49,7 +49,7 @@ save_boot_params:
/* r0 - start of kernel before */
adr r0, kernoffs /* r0 - current address of kernoffs section */
ldr r1, kernoffs /* r1 - offset of kernel image from kernoffs section */
- add r0, r0, r1
+ sub r0, r0, r1
/* r3 - start of kernel after */
ldr r3, kernaddr
diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index 012609bb537..81dbb4da107 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -19,6 +19,7 @@
#include <asm/cache.h>
#include <dm/read.h>
#include <dma-uclass.h>
+#include <linux/dma-mapping.h>
#include <dt-structs.h>
#include <errno.h>
@@ -235,6 +236,8 @@ int dma_memcpy(void *dst, void *src, size_t len)
{
struct udevice *dev;
const struct dma_ops *ops;
+ dma_addr_t destination;
+ dma_addr_t source;
int ret;
ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev);
@@ -245,11 +248,17 @@ int dma_memcpy(void *dst, void *src, size_t len)
if (!ops->transfer)
return -ENOSYS;
- /* Invalidate the area, so no writeback into the RAM races with DMA */
- invalidate_dcache_range((unsigned long)dst, (unsigned long)dst +
- roundup(len, ARCH_DMA_MINALIGN));
+ /* Clean the areas, so no writeback into the RAM races with DMA */
+ destination = dma_map_single(dst, len, DMA_FROM_DEVICE);
+ source = dma_map_single(src, len, DMA_TO_DEVICE);
- return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len);
+ ret = ops->transfer(dev, DMA_MEM_TO_MEM, destination, source, len);
+
+ /* Clean+Invalidate the areas after, so we can see DMA'd data */
+ dma_unmap_single(destination, len, DMA_FROM_DEVICE);
+ dma_unmap_single(source, len, DMA_TO_DEVICE);
+
+ return ret;
}
UCLASS_DRIVER(dma) = {
diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c
index aebf3eef966..2b8259a35b4 100644
--- a/drivers/dma/sandbox-dma-test.c
+++ b/drivers/dma/sandbox-dma-test.c
@@ -39,9 +39,9 @@ struct sandbox_dma_dev {
};
static int sandbox_dma_transfer(struct udevice *dev, int direction,
- void *dst, void *src, size_t len)
+ dma_addr_t dst, dma_addr_t src, size_t len)
{
- memcpy(dst, src, len);
+ memcpy((void *)dst, (void *)src, len);
return 0;
}
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index ec3dc62d2f3..1ad3b92dbf4 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <dm.h>
#include <dma-uclass.h>
+#include <linux/dma-mapping.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
@@ -395,7 +396,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
}
void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, void *src, size_t len, size_t s_len)
+ dma_addr_t dst, dma_addr_t src, size_t len, size_t s_len)
{
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
@@ -483,12 +484,14 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
}
void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, u8 val, size_t len)
+ dma_addr_t dst, u8 val, size_t len)
{
int xfer_len;
int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535;
+ dma_addr_t source;
memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer));
+ source = dma_map_single(edma_fill_buffer, len, DMA_TO_DEVICE);
while (len) {
xfer_len = len;
@@ -496,11 +499,13 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
xfer_len = max_xfer;
__edma3_transfer(edma3_base_addr, edma_slot_num, dst,
- edma_fill_buffer, xfer_len,
+ source, xfer_len,
EDMA_FILL_BUFFER_SIZE);
len -= xfer_len;
dst += xfer_len;
}
+
+ dma_unmap_single(source, len, DMA_FROM_DEVICE);
}
#ifndef CONFIG_DMA
@@ -508,19 +513,33 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, void *src, size_t len)
{
- __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len);
+ /* Clean the areas, so no writeback into the RAM races with DMA */
+ dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE);
+ dma_addr_t source = dma_map_single(src, len, DMA_TO_DEVICE);
+
+ __edma3_transfer(edma3_base_addr, edma_slot_num, destination, source, len, len);
+
+ /* Clean+Invalidate the areas after, so we can see DMA'd data */
+ dma_unmap_single(destination, len, DMA_FROM_DEVICE);
+ dma_unmap_single(source, len, DMA_TO_DEVICE);
}
void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, u8 val, size_t len)
{
- __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len);
+ /* Clean the area, so no writeback into the RAM races with DMA */
+ dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE);
+
+ __edma3_fill(edma3_base_addr, edma_slot_num, destination, val, len);
+
+ /* Clean+Invalidate the area after, so we can see DMA'd data */
+ dma_unmap_single(destination, len, DMA_FROM_DEVICE);
}
#else
-static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst,
- void *src, size_t len)
+static int ti_edma3_transfer(struct udevice *dev, int direction,
+ dma_addr_t dst, dma_addr_t src, size_t len)
{
struct ti_edma3_priv *priv = dev_get_priv(dev);
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 1a9197bfc82..d92b9644369 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -2305,7 +2305,7 @@ err_res_free:
}
static int udma_transfer(struct udevice *dev, int direction,
- void *dst, void *src, size_t len)
+ dma_addr_t dst, dma_addr_t src, size_t len)
{
struct udma_dev *ud = dev_get_priv(dev);
/* Channel0 is reserved for memcpy */
@@ -2326,7 +2326,7 @@ static int udma_transfer(struct udevice *dev, int direction,
if (ret)
return ret;
- udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
+ udma_prep_dma_memcpy(uc, dst, src, len);
udma_start(uc);
udma_poll_completion(uc, &paddr);
udma_stop(uc);
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index fb6b6cf3fff..6646b15d410 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -69,14 +69,20 @@ static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
static const struct reg_field pll1_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 29, 29);
+static const struct reg_field pll1_refclk_mux_sel_2 =
+ REG_FIELD(WIZ_SERDES_RST, 22, 23);
static const struct reg_field pll0_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 28, 28);
+static const struct reg_field pll0_refclk_mux_sel_2 =
+ REG_FIELD(WIZ_SERDES_RST, 28, 29);
static const struct reg_field refclk_dig_sel_16g =
REG_FIELD(WIZ_SERDES_RST, 24, 25);
static const struct reg_field refclk_dig_sel_10g =
REG_FIELD(WIZ_SERDES_RST, 24, 24);
static const struct reg_field pma_cmn_refclk_int_mode =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
+static const struct reg_field pma_cmn_refclk1_int_mode =
+ REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
static const struct reg_field pma_cmn_refclk_mode =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
static const struct reg_field pma_cmn_refclk_dig_div =
@@ -204,6 +210,27 @@ static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
},
};
+static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll0-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll1-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "refclk-dig",
+ },
+};
+
static struct wiz_clk_div_sel clk_div_sel[] = {
{
.div_sel = CMN_REFCLK,
@@ -219,6 +246,7 @@ enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G,
AM64_WIZ_10G,
+ J784S4_WIZ_10G,
};
struct wiz_data {
@@ -227,6 +255,7 @@ struct wiz_data {
const struct reg_field *pll1_refclk_mux_sel;
const struct reg_field *refclk_dig_sel;
const struct reg_field *pma_cmn_refclk1_dig_div;
+ const struct reg_field *pma_cmn_refclk1_int_mode;
const struct wiz_clk_mux_sel *clk_mux_sel;
unsigned int clk_div_sel_num;
};
@@ -259,6 +288,16 @@ static struct wiz_data am64_10g_data = {
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j784s4_wiz_10g = {
+ .type = J784S4_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
+ .refclk_dig_sel = &refclk_dig_sel_16g,
+ .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
+ .clk_mux_sel = clk_mux_sel_10g_2_refclk,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
@@ -279,6 +318,7 @@ struct wiz {
struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
+ struct regmap_field *pma_cmn_refclk1_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
struct regmap_field *pma_cmn_refclk1_dig_div;
@@ -729,6 +769,15 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
}
+ if (data->pma_cmn_refclk1_int_mode) {
+ wiz->pma_cmn_refclk1_int_mode =
+ devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_int_mode);
+ if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
+ dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
+ return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
+ }
+ }
+
wiz->pma_cmn_refclk_mode =
devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
@@ -844,8 +893,6 @@ static int wiz_clock_init(struct wiz *wiz)
return ret;
}
wiz->input_clks[WIZ_CORE_REFCLK] = clk;
- /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
- wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
rate = clk_get_rate(clk);
if (rate >= 100000000)
@@ -853,6 +900,25 @@ static int wiz_clock_init(struct wiz *wiz)
else
regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
+ if (wiz->data->pma_cmn_refclk1_int_mode) {
+ clk = devm_clk_get(dev, "core_ref1_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "core_ref1_clk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+
+ rate = clk_get_rate(clk);
+ if (rate >= 100000000)
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
+ else
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
+ } else {
+ /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
+ wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+ }
+
clk = devm_clk_get(dev, "ext_ref_clk");
if (IS_ERR(clk)) {
dev_err(dev, "ext_ref_clk clock not found\n");
@@ -933,7 +999,7 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
ofnode node;
int i, rc;
- if (type == AM64_WIZ_10G)
+ if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
return j721e_wiz_bind_clocks(wiz);
div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
@@ -1173,6 +1239,9 @@ static const struct udevice_id j721e_wiz_ids[] = {
{
.compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
},
+ {
+ .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
+ },
{}
};
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index ca2bc7cfb59..f0e57b4f728 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -39,7 +39,7 @@
#include <common.h>
#include <log.h>
#include <watchdog.h>
-#include <asm/arch/hardware.h>
+#include <asm/ti-common/omap_wdt.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/cpu.h>
diff --git a/include/dma-uclass.h b/include/dma-uclass.h
index 340437acc13..ea721baae69 100644
--- a/include/dma-uclass.h
+++ b/include/dma-uclass.h
@@ -132,8 +132,8 @@ struct dma_ops {
* @len: Length of the data to be copied (number of bytes).
* @return zero on success, or -ve error code.
*/
- int (*transfer)(struct udevice *dev, int direction, void *dst,
- void *src, size_t len);
+ int (*transfer)(struct udevice *dev, int direction, dma_addr_t dst,
+ dma_addr_t src, size_t len);
};
#endif /* _DMA_UCLASS_H */
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 12:05:33 +0000