diff options
98 files changed, 1434 insertions, 433 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4fabb75eda3..8a4c5d4eabd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12,13 +12,8 @@ Descriptions of section entries: S: Status, one of the following: Supported: Someone is actually paid to look after this. Maintained: Someone actually looks after it. - Odd Fixes: It has a maintainer but they don't have time to do - much other than throw the odd patch in. See below.. Orphan: No current maintainer [but maybe you could take the role as you write your new code]. - Obsolete: Old code. Something tagged obsolete generally means - it has been replaced by a better system and you - should be using that. F: Files and directories with wildcard patterns. A trailing slash includes all files and subdirectory files. F: drivers/net/ all files in and below drivers/net @@ -166,16 +161,19 @@ S: Maintained F: arch/arm/cpu/armv8/hisilicon F: arch/arm/include/asm/arch-hi6220/ -ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX -M: Prafulla Wadaskar <prafulla@marvell.com> -M: Luka Perkov <luka.perkov@sartura.hr> +ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese <sr@denx.de> S: Maintained T: git git://git.denx.de/u-boot-marvell.git F: arch/arm/mach-kirkwood/ F: arch/arm/mach-mvebu/ F: drivers/ata/ahci_mvebu.c -F: drivers/phy/marvell/ +F: drivers/ddr/marvell/ +F: drivers/gpio/mvebu_gpio.c +F: drivers/spi/kirkwood_spi.c +F: drivers/pci/pci_mvebu.c +F: drivers/pci/pcie_dw_mvebu.c +F: drivers/watchdog/orion_wdt.c ARM MARVELL PXA M: Marek Vasut <marex@denx.de> @@ -3,7 +3,7 @@ VERSION = 2019 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 5d6a711c140..94fa68250dd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -4,6 +4,7 @@ config ARCH_LS1021A select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 @@ -63,6 +64,11 @@ config SYS_CCI400_OFFSET Offset for CCI400 base. CCI400 base addr = CCSRBAR + CCI400_OFFSET +config SYS_FSL_ERRATUM_A008850 + bool + help + Workaround for DDR erratum A008850 + config SYS_FSL_ERRATUM_A008997 bool help diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 448d951c367..a779d337399 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -11,6 +11,7 @@ #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_stream_id.h> #include <fsl_csu.h> +#include <fsl_ddr_sdram.h> struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), @@ -103,6 +104,41 @@ static void erratum_a009007(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ } +static void erratum_a008850_early(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + +void erratum_a008850_post(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = in_be32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + out_be32(&ddr->eor, tmp); +#endif +} + void s_init(void) { } @@ -163,13 +199,6 @@ int arch_soc_init(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); } /* Enable all the snoop signal for various masters */ @@ -191,6 +220,7 @@ int arch_soc_init(void) out_be32(&scfg->eddrtqcfg, 0x63b20042); /* Erratum */ + erratum_a008850_early(); erratum_a009008(); erratum_a009798(); erratum_a008997(); diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts index d4d127fa024..c9ccbb57fff 100644 --- a/arch/arm/dts/armada-385-amc.dts +++ b/arch/arm/dts/armada-385-amc.dts @@ -133,7 +133,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie@1,0 { /* Port 0, Lane 0 */ diff --git a/arch/arm/dts/armada-385-turris-omnia.dts b/arch/arm/dts/armada-385-turris-omnia.dts index 28eede180e4..5511c84849e 100644 --- a/arch/arm/dts/armada-385-turris-omnia.dts +++ b/arch/arm/dts/armada-385-turris-omnia.dts @@ -96,7 +96,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie@1,0 { diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index a3493ddd4d4..4ddeaa02f12 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -124,7 +124,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible through diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts index 7bc878f5a92..d5ad2fd7e22 100644 --- a/arch/arm/dts/armada-388-gp.dts +++ b/arch/arm/dts/armada-388-gp.dts @@ -234,7 +234,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible through diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts index ffbd0dcaae4..bad7c60f19c 100644 --- a/arch/arm/dts/armada-38x-controlcenterdc.dts +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -243,7 +243,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible through diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index e859dd1b981..6df6be91814 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -32,6 +32,7 @@ adc@12D10000 { u-boot,dm-pre-reloc; + vdd-supply = <&ldo4_reg>; status = "okay"; }; @@ -44,6 +45,7 @@ regulator-name = "vdd_ldo1"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -51,18 +53,21 @@ regulator-name = "vddq_mmc0"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; }; ldo4_reg: LDO4 { regulator-name = "vdd_adc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; }; ldo5_reg: LDO5 { regulator-name = "vdd_ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -70,6 +75,7 @@ regulator-name = "vdd_ldo6"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -77,6 +83,7 @@ regulator-name = "vdd_ldo7"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -84,6 +91,7 @@ regulator-name = "vdd_ldo8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -91,6 +99,7 @@ regulator-name = "vdd_ldo9"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -98,6 +107,7 @@ regulator-name = "vdd_ldo10"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -105,6 +115,7 @@ regulator-name = "vdd_ldo11"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -112,6 +123,7 @@ regulator-name = "vdd_ldo12"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -119,12 +131,14 @@ regulator-name = "vddq_mmc2"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12000>; }; ldo15_reg: LDO15 { regulator-name = "vdd_ldo15"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -132,6 +146,7 @@ regulator-name = "vdd_ldo16"; regulator-min-microvolt = <2200000>; regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -139,6 +154,7 @@ regulator-name = "vdd_ldo17"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -146,18 +162,21 @@ regulator-name = "vdd_emmc_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12000>; }; ldo19_reg: LDO19 { regulator-name = "vdd_sd"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12000>; }; ldo24_reg: LDO24 { regulator-name = "tsp_io"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -165,6 +184,7 @@ regulator-name = "vdd_ldo26"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; + regulator-ramp-delay = <12000>; regulator-always-on; }; @@ -256,7 +276,7 @@ }; serial@12C20000 { - status="okay"; + status = "okay"; }; mmc@12200000 { diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi index 45ae2fad0b2..0aa29e38b83 100644 --- a/arch/arm/dts/imx6qdl-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-u-boot.dtsi @@ -9,6 +9,9 @@ aips-bus@2000000 { u-boot,dm-spl; + spba-bus@2000000 { + u-boot,dm-spl; + }; }; aips-bus@2100000 { diff --git a/arch/arm/dts/imx6ul-pico-hobbit.dts b/arch/arm/dts/imx6ul-pico-hobbit.dts new file mode 100644 index 00000000000..39eeeddac39 --- /dev/null +++ b/arch/arm/dts/imx6ul-pico-hobbit.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; + compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + status = "okay"; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-pico-pi.dts b/arch/arm/dts/imx6ul-pico-pi.dts new file mode 100644 index 00000000000..de07357b27f --- /dev/null +++ b/arch/arm/dts/imx6ul-pico-pi.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and PI baseboard"; + compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-pico.dtsi b/arch/arm/dts/imx6ul-pico.dtsi new file mode 100644 index 00000000000..de9f83189ba --- /dev/null +++ b/arch/arm/dts/imx6ul-pico.dtsi @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + /* Will be filled by the bootloader */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + chosen { + stdout-path = &uart6; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 6 0>; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + /* VDD_ARM_SOC_IN*/ + sw1b_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* DRAM */ + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + /* DRAM */ + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <33200000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <46>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { /* Wifi SDIO */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_brcm>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ + MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* LCD reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/dts/kirkwood-dreamplug.dts b/arch/arm/dts/kirkwood-dreamplug.dts index a647a65c20a..ccd74dd7fb3 100644 --- a/arch/arm/dts/kirkwood-dreamplug.dts +++ b/arch/arm/dts/kirkwood-dreamplug.dts @@ -18,6 +18,10 @@ stdout-path = &uart0; }; + aliases { + spi0 = &spi0; + }; + ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_led_bluetooth: pmx-led-bluetooth { diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ccd3f32301e..ee93725d648 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -95,6 +95,7 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; status = "disabled"; }; @@ -106,6 +107,7 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; status = "disabled"; }; @@ -117,6 +119,7 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; status = "disabled"; }; diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h index 05e8b49c2d1..1fde8bce5d5 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -10,6 +10,8 @@ unsigned int get_soc_major_rev(void); int arch_soc_init(void); int ls102xa_smmu_stream_id_init(void); +void erratum_a008850_post(void); + #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 void erratum_a010315(void); #endif diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 7539e456522..4bbc956f9db 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -616,26 +616,32 @@ static const struct udevice_id cpu_imx8_ids[] = { { } }; +static ulong imx8_get_cpu_rate(void) +{ + ulong rate; + int ret; + + ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU, + (sc_pm_clock_rate_t *)&rate); + if (ret) { + printf("Could not read CPU frequency: %d\n", ret); + return 0; + } + + return rate; +} + static int imx8_cpu_probe(struct udevice *dev) { struct cpu_imx_platdata *plat = dev_get_platdata(dev); - struct clk cpu_clk; u32 cpurev; - int ret; cpurev = get_cpu_rev(); plat->cpurev = cpurev; plat->name = get_core_name(); plat->rev = get_imx8_rev(cpurev & 0xFFF); plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); - - ret = clk_get_by_index(dev, 0, &cpu_clk); - if (ret) { - debug("%s: Failed to get CPU clk: %d\n", __func__, ret); - return 0; - } - - plat->freq_mhz = clk_get_rate(&cpu_clk) / 1000000; + plat->freq_mhz = imx8_get_cpu_rate() / 1000000; return 0; } diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d0cee514a27..e782859b1e6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -403,7 +403,9 @@ config TARGET_OT1200 config TARGET_PICO_IMX6UL bool "PICO-IMX6UL-EMMC" select MX6UL + select DM select SUPPORT_SPL + imply CMD_DM config TARGET_LITEBOARD bool "Grinn liteBoard (i.MX6UL)" diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index fcd903887bf..aea60688c2d 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -26,6 +26,12 @@ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ +/* + * Disable the dcache. Currently the network driver (mvgbe.c) and USB + * EHCI driver (ehci-marvell.c) and possibly others rely on the data + * cache being disabled. + */ +#define CONFIG_SYS_DCACHE_OFF /* * By default kwbimage.cfg from board specific folder is used diff --git a/board/boundary/nitrogen6x/README.mx6qsabrelite b/board/boundary/nitrogen6x/README.mx6qsabrelite index 12a9c856cff..6283c9575eb 100644 --- a/board/boundary/nitrogen6x/README.mx6qsabrelite +++ b/board/boundary/nitrogen6x/README.mx6qsabrelite @@ -1,72 +1,119 @@ U-Boot for the Freescale i.MX6q SabreLite board +=============================================== This file contains information for the port of U-Boot to the Freescale i.MX6q SabreLite board. -1. Boot source, boot from SD card ---------------------------------- -The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports -boot from SD card only. However, by default, the SabreLite -boards boot from the SPI NOR flash. These boards need to be reflashed with -a small SD card loader to support boot from SD card. This small SD card loader -will be flashed into the SPI NOR. The board will still boot from SPI NOR, but -the loader will in turn request the BootROM to load the U-Boot from SD card. +1. Build +-------- + +To build U-Boot for the SabreLite board: + + make mx6qsabrelite_config + make + + +2. Boot from SD card +-------------------- + +The SabreLite boards boot from the SPI NOR flash. These boards need their SPI +to be reflashed with a small SD card loader to support boot from SD card. The +board will still boot from SPI NOR, but the loader will in turn request the +BootROM to load the U-Boot from SD card. The SD card loader is available from https://wiki.linaro.org/Boards/MX6QSabreLite -under a open-source 3-clause BSD license. +This is provided under a open-source 3-clause BSD license. -To update the SPI-NOR on the SabreLite board without the Freescale -manufacturing tool use the following procedure: +To following procedure can be used to update the SPI-NOR on the SabreLite +board: 1. Write this SD card loader onto a large SD card using: - sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx + sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx -Note: Replace sXx with the device representing the SD card in your system. + Note: Replace sXx with the device representing the SD card in your system. -Note: This writes SD card loader at address 0 + Note: This writes SD card loader at address 0 2. Put this SD card into the slot for the large SD card (SD3 on the bottom of -the board). Make sure SW1 switch is at position "00", so that it can boot -from the fuses. + the board). Make sure SW1 switch is at position "00", so that it can boot + from the fuses. 3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot -(the default one the board is shipped with, starting from the SPI NOR) and -enter the following commands: + (the default one the board is shipped with, starting from the SPI NOR) and + enter the following commands: + + MX6Q SABRELITE U-Boot > mmc dev 0 + MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 + MX6Q SABRELITE U-Boot > sf probe + MX6Q SABRELITE U-Boot > sf erase 0 0x40000 + MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 - MX6Q SABRELITE U-Boot > mmc dev 0 - MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 - MX6Q SABRELITE U-Boot > sf probe - MX6Q SABRELITE U-Boot > sf erase 0 0x40000 - MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 +4. Write the u-boot.imx produced during the U-Boot build to the SD card: -4. done. + sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2 && sudo sync -In case you somehow do not succeed with this procedure you will have to use -the Freescale manufacturing tool in order to reflash the SPI-NOR. + Note: Replace sXx with the device representing the SD card in your system. + +5. Re-insert the SD card back in the slot for the large SD card and power-cycle + the board. Note: The board now boots from full size SD3 on the bottom of the board. NOT the micro SD4/BOOT slot on the top of the board. I.e. you have to use full size SD cards. -This information is taken from +This information originally taken from: -https://wiki.linaro.org/Boards/MX6QSabreLite + https://wiki.linaro.org/Boards/MX6QSabreLite -2. Build --------- -To build U-Boot for the SabreLite board: +3. Boot from SPI NOR +-------------------- - make mx6qsabrelite_config - make +The SabreLite board can also boot U-Boot directly from the SPI NOR flash: + +1. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot + and enter the following commands: + + => mmc dev 0 + => mmc read 0x10800000 0x400 0x80000 + => sf probe 0 + => sf erase 0 0xc0000 + => sf write 0x10800000 0x400 0x80000 + +Note: This procedure assumes you have booted using the desired U-Boot from an + SD card as prepared in the previous section. Alternative mechanisms, such + as using tftpboot to copy an alternative U-Boot image into memory can + also be used. + + +4. Recovering SPI-NOR +--------------------- + +In case you somehow do not succeed with this procedure you can upload U-Boot +via USB: + +1. Download and install the imx_loader following the instructions provided: + + https://github.com/boundarydevices/imx_usb_loader + +2. Connect the board to USB via the USB OTG port. + +3. Make sure SW1 switch is at position "01", so that it can boot from USB OTG. + +4. Power-up the SabreLite and run the imx_loader to upload the U-Boot image: + + sudo imx_usb u-boot.imx + +Note: This will upload and run the U-Boot image in memory, the SPI will not be + reprogrammed and this procedure will need to be repeated if the board is + reset. -To copy the resulting u-boot.imx to the SD card: +5. Use one of previous descriptions to re-flash the SPI-NOR as required. - sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync +6. Ensure SW1 is returned to "00" to boot from the fuses once done. -Note: Replace sXx with the device representing the SD card in your system. diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index 5dccb17cb27..7486f0ac2d9 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -8,6 +8,7 @@ #include <common.h> #include <mmc.h> #include <asm/arch/sys_proto.h> +#include <watchdog.h> #include "board.h" @@ -88,6 +89,10 @@ int board_late_init(void) setenv_fdt_file(); +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + return 0; } diff --git a/board/freescale/imx8mq_evk/MAINTAINERS b/board/freescale/imx8mq_evk/MAINTAINERS index a2e320cb100..a00bb4ef786 100644 --- a/board/freescale/imx8mq_evk/MAINTAINERS +++ b/board/freescale/imx8mq_evk/MAINTAINERS @@ -1,5 +1,6 @@ i.MX8MQ EVK BOARD M: Peng Fan <peng.fan@nxp.com> +M: Fabio Estevam <festevam@gmail.com> S: Maintained F: board/freescale/imx8mq_evk/ F: include/configs/imx8mq_evk.h diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README index 1da6eaf2427..2529f7da3d9 100644 --- a/board/freescale/imx8mq_evk/README +++ b/board/freescale/imx8mq_evk/README @@ -18,8 +18,9 @@ Get the ddr and hdmi firmware Note: srctree is U-Boot source directory $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin $ chmod +x firmware-imx-7.9.bin +$ ./firmware-imx-7.9.bin $ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree) -$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee) +$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee) Build U-Boot ==================== diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index fb05b55b5c5..70992a5ce4e 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -97,6 +97,8 @@ int dram_init(void) ddrmc_init(); #endif + erratum_a008850_post(); + gd->ram_size = DDR_SIZE; return 0; } diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 98faf9389e4..d3e2e533217 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -179,6 +179,8 @@ int fsl_initdram(void) fsl_dp_resume(); #endif + erratum_a008850_post(); + gd->ram_size = dram_size; return 0; diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index ff1fe8e2ec6..58a88384367 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -5,6 +5,9 @@ #ifndef __DDR_H__ #define __DDR_H__ + +void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index c08be1ee461..2ca2bd99093 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -200,10 +200,6 @@ int board_early_init_f(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - unsigned int major; - #ifdef CONFIG_NAND_BOOT struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; u32 porsr1, pinctl; @@ -240,10 +236,6 @@ void board_init_f(ulong dummy) i2c_init_all(); #endif - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - timer_init(); dram_init(); @@ -420,22 +412,12 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - unsigned int major; - #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 erratum_a009942_check_cpo(); #endif - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* Set CCI-400 control override register to - * enable barrier transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - } select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -456,18 +438,6 @@ int board_init(void) #if defined(CONFIG_DEEP_SLEEP) void board_sleep_prepare(void) { - struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - unsigned int major; - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* Set CCI-400 control override register to - * enable barrier transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - } - - #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index beb82cebb62..01ba1bc9621 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -222,6 +222,8 @@ int dram_init(void) ddrmc_init(); #endif + erratum_a008850_post(); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 1e98d0c1f98..f6e22d7337b 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -628,8 +628,9 @@ int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) { char mdio_ioslot_str[] = "mdio@00"; - char mdio_mux_str[] = "mdio-mux-0"; struct lx2160a_qds_mdio *priv; + u64 reg; + u32 phandle; int offset, mux_val; /*Test if the MDIO bus is real mdio bus or muxing front end ?*/ @@ -643,15 +644,32 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) debug("real_bus_num = %d, ioslot = %d\n", priv->realbusnum, priv->ioslot); - sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum); - offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str); + if (priv->realbusnum == EMI1) + reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + else + reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + + offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); + if (offset < 0) { + printf("mdio@%llx node not found in device tree\n", reg); + return offset; + } + + phandle = fdt_get_phandle(fdt, offset); + phandle = cpu_to_fdt32(phandle); + offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus", + &phandle, 4); if (offset < 0) { - printf("%s node not found under node %s in device tree\n", - mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL)); + printf("mdio-mux-%d node not found in device tree\n", + priv->realbusnum == EMI1 ? 1 : 2); return offset; } mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + if (priv->realbusnum == EMI1) + mux_val >>= BRDCFG4_EMI1SEL_SHIFT; + else + mux_val >>= BRDCFG4_EMI2SEL_SHIFT; sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val); offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str); @@ -675,7 +693,9 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset, *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name); if (*subnodeoffset <= 0) { - printf("Could not add subnode %s\n", phy_node_name); + printf("Could not add subnode %s inside node %s err = %s\n", + phy_node_name, fdt_get_name(fdt, offset, NULL), + fdt_strerror(*subnodeoffset)); return *subnodeoffset; } @@ -779,7 +799,6 @@ int fdt_fixup_board_phy(void *fdt) } if (dpmac_id == NUM_WRIOP_PORTS) continue; - ret = fdt_create_phy_node(fdt, offset, i, &subnodeoffset, phy_dev, phandle); @@ -792,6 +811,11 @@ int fdt_fixup_board_phy(void *fdt) fdt_del_node(fdt, subnodeoffset); break; } + /* calculate offset again as new node addition may have + * changed offset; + */ + offset = fdt_get_ioslot_offset(fdt, mii_dev, + fpga_offset); phandle++; } diff --git a/board/freescale/mx6sabreauto/README b/board/freescale/mx6sabreauto/README index e8c589b92aa..4c0fda1a2de 100644 --- a/board/freescale/mx6sabreauto/README +++ b/board/freescale/mx6sabreauto/README @@ -9,15 +9,15 @@ $ make mx6sabreauto_defconfig $ make -This will generate the SPL and u-boot.img binaries. +This will generate the SPL and u-boot-dtb.img binaries. - Flash the SPL binary into the SD card: $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync -- Flash the u-boot.img binary into the SD card: +- Flash the u-boot-dtb.img binary into the SD card: -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync Booting via Falcon mode ----------------------- @@ -32,15 +32,15 @@ $ make mx6sabreauto_defconfig $ make -This will generate the SPL image called SPL and the u-boot.img. +This will generate the SPL image called SPL and the u-boot-dtb.img. - Flash the SPL image into the SD card: $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync -- Flash the u-boot.img image into the SD card: +- Flash the u-boot-dtb.img image into the SD card: -$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1K seek=69 && sync Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there: diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README index 4b4df063300..4ea4454b9f9 100644 --- a/board/freescale/mx6sabresd/README +++ b/board/freescale/mx6sabresd/README @@ -21,15 +21,15 @@ $ make mx6sabresd_defconfig $ make -This will generate the SPL and u-boot.img binaries. +This will generate the SPL and u-boot-dtb.img binaries. - Flash the SPL binary into the SD card: $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync -- Flash the u-boot.img binary into the SD card: +- Flash the u-boot-dtb.img binary into the SD card: -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync 2. Booting from eMMC @@ -39,7 +39,7 @@ $ make mx6sabresd_defconfig $ make -This will generate the SPL and u-boot.img binaries. +This will generate the SPL and u-boot-dtb.img binaries. - Boot first from SD card as shown in the previous section @@ -51,10 +51,10 @@ Mount the eMMC in the host PC: => ums 0 mmc 2 -- Flash SPL and u-boot.img binaries into the eMMC: +- Flash SPL and u-boot-dtb.img binaries into the eMMC: $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync Set SW6 to eMMC 8-bit boot: 11010110 @@ -65,15 +65,15 @@ Set SW6 to eMMC 8-bit boot: 11010110 $ make mx6sabresd_defconfig $ make -This will generate the SPL image called SPL and the u-boot.img. +This will generate the SPL image called SPL and the u-boot-dtb.img. - Flash the SPL image into the SD card: $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync -- Flash the u-boot.img image into the SD card: +- Flash the u-boot-dtb.img image into the SD card: -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync Create a partition for root file system and extract it there: diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 595ad76bbec..636c008993b 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -86,16 +86,13 @@ int power_init_board(void) pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); /* SW1B step ramp up time from 2us to 4us/25mV */ - reg = 0x40; - pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); /* SW1B mode to APS/PFM */ - reg = 0xc; - pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); /* SW1B standby voltage set to 0.975V */ - reg = 0xb; - pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); return 0; } diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index ee227320c05..5e9cf115752 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -6,6 +6,7 @@ #include <common.h> #include <errno.h> +#include <hexdump.h> #include <i2c.h> #include <malloc.h> #include <asm/bitops.h> @@ -46,6 +47,8 @@ read_eeprom(int bus, struct ventana_board_info *info) /* sanity checks */ if (info->model[0] != 'G' || info->model[1] != 'W') { puts("EEPROM: Invalid Model in EEPROM\n"); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, + sizeof(*info)); return GW_UNKNOWN; } @@ -55,6 +58,8 @@ read_eeprom(int bus, struct ventana_board_info *info) if ((info->chksum[0] != chksum>>8) || (info->chksum[1] != (chksum&0xff))) { puts("EEPROM: Failed EEPROM checksum\n"); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, + sizeof(*info)); return GW_UNKNOWN; } @@ -116,6 +121,11 @@ read_eeprom(int bus, struct ventana_board_info *info) else if (info->model[4] == '0' && info->model[5] == '9') type = GW5909; break; + default: + printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, + sizeof(*info)); + break; } return type; } diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 27f3774140e..eaf7aa9ecad 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -540,6 +540,11 @@ static void spl_dram_init(int width, int size_mb, int board_model) else calib = &mx6sdl_256x16_mmdc_calib; debug("4gB density\n"); + } else if (width == 16 && size_mb == 1024) { + mem = &mt41k512m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_512x32_mmdc_calib; + debug("8gB density\n"); } else if (width == 32 && size_mb == 256) { /* Same calib as width==16, size==128 */ mem = &mt41k64m16jt_125; diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index 18d152a3819..80910e4713c 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -24,8 +24,6 @@ #include <mmc.h> #include <netdev.h> #include <spl.h> -#include <usb.h> -#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; @@ -63,26 +61,6 @@ static iomux_v3_cfg_t const sd_pads[] = { MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -#ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), - MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); -} -#endif - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -180,13 +158,6 @@ void board_late_mmc_init(void) #endif #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - setup_iomux_fec(); - - return fecmxc_initialize(bis); -} - static int setup_fec(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -207,13 +178,6 @@ static int setup_fec(void) } #endif -#ifdef CONFIG_USB_EHCI_MX6 -int board_usb_phy_mode(int port) -{ - return USB_INIT_HOST; -} -#endif - int board_early_init_f(void) { setup_iomux_uart(); diff --git a/board/samsung/arndale/MAINTAINERS b/board/samsung/arndale/MAINTAINERS index 7dc17854d1b..aa64c7a1874 100644 --- a/board/samsung/arndale/MAINTAINERS +++ b/board/samsung/arndale/MAINTAINERS @@ -1,5 +1,5 @@ ARNDALE BOARD -M: Chander Kashyap <k.chander@samsung.com> +M: Krzysztof Kozlowski <krzk@kernel.org> S: Maintained F: board/samsung/arndale/ F: include/configs/arndale.h diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 96228a86a11..9adbd1e2cf9 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -249,11 +249,22 @@ int board_eth_init(bd_t *bis) return 0; } -#ifdef CONFIG_DISPLAY_BOARDINFO +#if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE) int checkboard(void) { if (IS_ENABLED(CONFIG_BOARD_TYPES)) { - const char *board_info = get_board_type(); + const char *board_info; + + if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) { + /* + * Printing type requires having revision, although + * this will succeed only if done late. + * Otherwise revision will be set in misc_init_r(). + */ + set_board_revision(); + } + + board_info = get_board_type(); if (board_info) printf("Type: %s\n", board_info); @@ -287,6 +298,16 @@ int board_late_init(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { + if (IS_ENABLED(CONFIG_BOARD_TYPES) && + !IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) { + /* + * If revision was not set by late display boardinfo, + * set it here. At this point regulators should be already + * available. + */ + set_board_revision(); + } + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_info(); #endif diff --git a/board/samsung/common/bootscripts/autoboot.cmd b/board/samsung/common/bootscripts/autoboot.cmd index 11c724c4e09..d66bcccf5d1 100644 --- a/board/samsung/common/bootscripts/autoboot.cmd +++ b/board/samsung/common/bootscripts/autoboot.cmd @@ -3,7 +3,7 @@ # ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr # # It requires a list of environment variables to be defined before load: -# platform dependent: boardname, fdtfile, console +# platform dependent: board_name, fdtfile, console # system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype # setenv fdtaddr "40800000" @@ -35,17 +35,17 @@ else setenv initrd_addr -; fi;" -#### Routine: boot_fit - check that env $boardname is set and boot proper config of ITB image +#### Routine: boot_fit - check that env $board_name is set and boot proper config of ITB image setenv setboot_fit " -if test -e '${boardname}'; then +if test -e '${board_name}'; then setenv fdt_addr ; setenv initrd_addr ; setenv kerneladdr 0x42000000; setenv kernelname Image.itb; - setenv itbcfg "\"#${boardname}\""; + setenv itbcfg "\"#${board_name}\""; setenv imgbootcmd bootm; else - echo Warning! Variable: \$boardname is undefined!; + echo Warning! Variable: \$board_name is undefined!; fi" #### Routine: setboot_uimg - prepare env to boot uImage diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 7a86e918776..516c32923e4 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -57,12 +57,48 @@ static unsigned int odroid_get_rev(void) return 0; } +/* + * Read ADC at least twice and check the resuls. If regulator providing voltage + * on to measured point was just turned on, first reads might require time + * to stabilize. + */ +static int odroid_get_adc_val(unsigned int *adcval) +{ + unsigned int adcval_prev = 0; + int ret, retries = 20; + + ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN, + &adcval_prev); + if (ret) + return ret; + + while (retries--) { + mdelay(5); + + ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN, + adcval); + if (ret) + return ret; + + /* + * If difference between ADC reads is less than 3%, + * accept the result + */ + if ((100 * abs(*adcval - adcval_prev) / adcval_prev) < 3) + return ret; + + adcval_prev = *adcval; + } + + return ret; +} + static int odroid_get_board_type(void) { unsigned int adcval; int ret, i; - ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN, &adcval); + ret = odroid_get_adc_val(&adcval); if (ret) goto rev_default; @@ -192,8 +228,11 @@ const char *get_board_type(void) /** * set_board_type() - set board type in gd->board_type. - * As default type set EXYNOS5_BOARD_GENERIC, if detect Odroid, - * then set its proper type. + * As default type set EXYNOS5_BOARD_GENERIC. If Odroid is detected, + * set its proper type based on device tree. + * + * This might be called early when some more specific ways to detect revision + * are not yet available. */ void set_board_type(void) { @@ -211,8 +250,15 @@ void set_board_type(void) gd->board_type = of_match->data; break; } +} - /* If Odroid, then check its revision */ +/** + * set_board_revision() - set detailed board type in gd->board_type. + * Should be called when resources (e.g. regulators) are available + * so ADC can be used to detect the specific revision of a board. + */ +void set_board_revision(void) +{ if (board_is_odroidxu3()) gd->board_type = odroid_get_board_type(); } diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 05243fc8965..53cd1b29070 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -101,7 +101,7 @@ void set_board_info(void) bdtype = ""; sprintf(info, "%s%s", bdname, bdtype); - env_set("boardname", info); + env_set("board_name", info); #endif snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb", CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype); diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 552333fe869..3e594fd8501 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -54,6 +54,14 @@ void set_board_type(void) gd->board_type = ODROID_TYPE_U3; } +void set_board_revision(void) +{ + /* + * Revision already set by set_board_type() because it can be + * executed early. + */ +} + const char *get_board_type(void) { const char *board_type[] = {"u3", "x2"}; @@ -462,18 +470,33 @@ struct dwc2_plat_otg_data s5pc210_otg_data = { #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB) +static void set_usb3503_ref_clk(void) +{ +#ifdef CONFIG_BOARD_TYPES + /* + * gpx3-0 chooses primary (low) or secondary (high) reference clock + * frequencies table. The choice of clock is done through hard-wired + * REF_SEL pins. + * The Odroid Us have reference clock at 24 MHz (00 entry from secondary + * table) and Odroid Xs have it at 26 MHz (01 entry from primary table). + */ + if (gd->board_type == ODROID_TYPE_U3) + gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); + else + gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); +#else + /* Choose Odroid Xs frequency without board types */ + gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); +#endif /* CONFIG_BOARD_TYPES */ +} + int board_usb_init(int index, enum usb_init_type init) { #ifdef CONFIG_CMD_USB struct udevice *dev; int ret; - /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/ - /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */ - if (gd->board_type == ODROID_TYPE_U3) - gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); - else - gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); + set_usb3503_ref_clk(); /* Disconnect, Reset, Connect */ gpio_direction_output(EXYNOS4X12_GPIO_X34, 0); diff --git a/board/technexion/pico-imx6ul/README b/board/technexion/pico-imx6ul/README index 1cabd90759d..bb8ee3f4634 100644 --- a/board/technexion/pico-imx6ul/README +++ b/board/technexion/pico-imx6ul/README @@ -13,7 +13,7 @@ $ make mrproper $ make pico-imx6ul_defconfig $ make -This generates the SPL and u-boot.img binaries. +This generates the SPL and u-boot-dtb.img binaries. 1. Loading U-Boot via USB Serial Download Protocol @@ -31,15 +31,15 @@ Connect a USB cable between the OTG pico port and the host PC. Open a terminal program such as minicom. -Copy SPL and u-boot.img to the imx_usb_loader folder. +Copy SPL and u-boot-dtb.img to the imx_usb_loader folder. Load the SPL binary via USB: $ sudo ./imx_usb SPL -Load the u-boot.img binary via USB: +Load the u-boot-dtb.img binary via USB: -$ sudo ./imx_usb u-boot.img +$ sudo ./imx_usb u-boot-dtb.img Then U-Boot starts and its messages appear in the console program. @@ -54,11 +54,11 @@ Run the DFU agent so we can flash the new images using dfu-util tool: => dfu 0 mmc 0 -Flash SPL and u-boot.img into the eMMC running the following commands on a PC: +Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC: $ sudo dfu-util -D SPL -a spl -$ sudo dfu-util -D u-boot.img -a u-boot +$ sudo dfu-util -D u-boot-dtb.img -a u-boot Remove power from the pico board. @@ -142,7 +142,7 @@ Launch UMS: Flash the new binaries: $ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync -$ sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=69; sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync And then SPL binary will load and jump directly to the kernel: diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 8c767782760..95b482a602f 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -13,13 +13,10 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> #include <common.h> #include <miiphy.h> #include <netdev.h> -#include <fsl_esdhc.h> -#include <i2c.h> #include <linux/sizes.h> #include <usb.h> #include <power/pmic.h> @@ -32,15 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -56,23 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; #define RMII_PHY_RESET IMX_GPIO_NR(1, 28) -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C2 for PMIC */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, - .gp = IMX_GPIO_NR(1, 2), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3), - }, -}; -#endif - static iomux_v3_cfg_t const fec_pads[] = { MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), @@ -96,6 +67,7 @@ int board_eth_init(bd_t *bis) { setup_iomux_fec(); + gpio_request(RMII_PHY_RESET, "enet_phy_reset"); gpio_direction_output(RMII_PHY_RESET, 0); /* * According to KSZ8081MNX-RNB manual: @@ -155,19 +127,6 @@ static iomux_v3_cfg_t const uart6_pads[] = { MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) @@ -185,22 +144,6 @@ static void setup_usb(void) imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -208,38 +151,33 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_POWER -#define I2C_PMIC 0 -static struct pmic *pfuze; +#ifdef CONFIG_DM_PMIC int power_init_board(void) { - int ret; - unsigned int reg, rev_id; + struct udevice *dev; + int ret, dev_id, rev_id; - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) return ret; - pfuze = pmic_get("PFUZE3000"); - ret = pmic_probe(pfuze); - if (ret) - return ret; - - pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); - pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); + pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1); /* SW1B step ramp up time from 2us to 4us/25mV */ - pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40); + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); /* SW1B mode to APS/PFM */ - pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); /* SW1B standby voltage set to 0.975V */ - pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); return 0; } @@ -274,10 +212,6 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - #ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - #endif - setup_fec(); setup_usb(); diff --git a/board/warp7/README b/board/warp7/README index 60339da5437..579bb2de38a 100644 --- a/board/warp7/README +++ b/board/warp7/README @@ -17,7 +17,7 @@ $ make mrproper $ make warp7_config $ make -This will generate the U-Boot binary called u-boot.imx. +This will generate the U-Boot binary called u-boot-dtb.imx. Put warp7 board in USB download mode: @@ -28,11 +28,11 @@ Connect a USB to serial adapter between the host PC and warp7 Connect a USB cable between the OTG warp7 port and the host PC -Copy u-boot.imx to the imx_usb_loader folder. +Copy u-boot-dtb.imx to the imx_usb_loader folder. -Load u-boot.imx via USB: +Load u-boot-dtb.imx via USB: -$ sudo ./imx_usb u-boot.imx +$ sudo ./imx_usb u-boot-dtb.imx Then U-Boot should start and its messages will appear in the console program. @@ -46,9 +46,9 @@ Use the default environment variables: Run the DFU command: => dfu 0 mmc 0 -Transfer u-boot.imx that will be flashed into the eMMC: +Transfer u-boot-dtb.imx that will be flashed into the eMMC: -$ sudo dfu-util -D u-boot.imx -a boot +$ sudo dfu-util -D u-boot-dtb.imx -a boot Then on the U-Boot prompt the following message should be seen after a successful upgrade: diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 6ebeb08e331..2882dc98707 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -11,12 +11,8 @@ #include <asm/gpio.h> #include <asm/mach-imx/hab.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> #include <common.h> -#include <fsl_esdhc.h> -#include <i2c.h> -#include <mmc.h> #include <asm/arch/crm_regs.h> #include <usb.h> #include <netdev.h> @@ -81,7 +77,7 @@ int power_init_board(void) printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* disable Low Power Mode during standby mode */ - pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1); return 0; } diff --git a/cmd/fastboot.c b/cmd/fastboot.c index 0be83b78ac1..1b4215114d7 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -13,6 +13,7 @@ #include <fastboot.h> #include <net.h> #include <usb.h> +#include <watchdog.h> static int do_fastboot_udp(int argc, char *const argv[], uintptr_t buf_addr, size_t buf_size) @@ -74,6 +75,7 @@ static int do_fastboot_usb(int argc, char *const argv[], break; if (ctrlc()) break; + WATCHDOG_RESET(); usb_gadget_handle_interrupts(controller_index); } diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index ee848776541..526c14a3947 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y @@ -48,8 +49,9 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 3e1b404408a..319d9dbd9c3 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_DB_88F6820_AMC=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y @@ -52,6 +53,7 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_NAND=y CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_MARVELL=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index f95957adabe..07171c70099 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -85,5 +85,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 219d31a9a18..0ed2209e3b7 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -89,5 +89,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 466a7752ad8..57e4a999aba 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -88,5 +88,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 5017e5831b0..8a875a8716b 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y @@ -58,8 +59,10 @@ CONFIG_PCF8575_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index f22e5ea8199..68ad1c6d202 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -12,6 +12,13 @@ CONFIG_DEBUG_UART_BASE=0x021f0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_CMD_BOOTCOUNT=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 +CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 +CONFIG_IMX_WATCHDOG=y CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 53025e45bc9..46100b67196 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_ENV_IS_IN_MMC=y CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 CONFIG_DM_GPIO=y CONFIG_DM_I2C=y @@ -29,6 +30,7 @@ CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 61ba4ea2df6..e4a2fcc7fbe 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -30,10 +30,20 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y +CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index e35f8d6dde7..887522a59b9 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -10,6 +10,8 @@ CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_BOARD_TYPES=y CONFIG_SYS_PROMPT="ODROID-XU3 # " @@ -33,6 +35,7 @@ CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y CONFIG_MMC_DW=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index e6454e5fce7..4cfef86882e 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -17,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -33,6 +32,8 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit" CONFIG_ENV_IS_IN_MMC=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -40,14 +41,24 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index a740016d9e9..edbca4ee14c 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -17,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -35,6 +34,8 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit" CONFIG_ENV_IS_IN_MMC=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -42,14 +43,24 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 09deca40640..18abf838060 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -17,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb" CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -33,6 +32,8 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi" CONFIG_ENV_IS_IN_MMC=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -40,14 +41,24 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_OF_LIBFDT=y diff --git a/doc/device-tree-bindings/regulator/regulator.txt b/doc/device-tree-bindings/regulator/regulator.txt index 65b69c42789..4ba642b7c77 100644 --- a/doc/device-tree-bindings/regulator/regulator.txt +++ b/doc/device-tree-bindings/regulator/regulator.txt @@ -35,6 +35,7 @@ Optional properties: - regulator-max-microamp: a maximum allowed Current value - regulator-always-on: regulator should never be disabled - regulator-boot-on: enabled by bootloader/firmware +- regulator-ramp-delay: ramp delay for regulator (in uV/us) Note The "regulator-name" constraint is used for setting the device's uclass @@ -60,4 +61,5 @@ ldo0 { regulator-max-microamp = <100000>; regulator-always-on; regulator-boot-on; + regulator-ramp-delay = <12000>; }; diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c index d33e3d632af..12c49fc8cef 100644 --- a/drivers/adc/exynos-adc.c +++ b/drivers/adc/exynos-adc.c @@ -62,7 +62,7 @@ int exynos_adc_stop(struct udevice *dev) /* Stop conversion */ cfg = readl(®s->con1); - cfg |= ~ADC_V2_CON1_STC_EN; + cfg &= ~ADC_V2_CON1_STC_EN; writel(cfg, ®s->con1); diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index 111a8586c6e..b2f11a83996 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -420,13 +420,13 @@ unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_dd result = speed_bin_table_t_rcd_t_rp[index]; break; case SPEED_BIN_TRAS: - if (index < SPEED_BIN_DDR_1066G) + if (index <= SPEED_BIN_DDR_1066G) result = 37500; - else if (index < SPEED_BIN_DDR_1333J) + else if (index <= SPEED_BIN_DDR_1333J) result = 36000; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 35000; - else if (index < SPEED_BIN_DDR_1866M) + else if (index <= SPEED_BIN_DDR_1866M) result = 34000; else result = 33000; diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index db0f8ad7fb5..df832ac6dce 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -50,6 +50,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) int max_phase = MIN_VALUE, current_phase; enum hws_access_type access_type = ACCESS_TYPE_UNICAST; u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); + unsigned int max_cs = mv_ddr_cs_num_get(); CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, @@ -59,7 +60,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) data_read, MASK_ALL_BITS)); val = data_read[if_id]; - for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) { + for (cs_num = 0; cs_num < max_cs; cs_num++) { read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num); /* find maximum of read_samples */ diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index c6e06aab7aa..17eca73be02 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -119,7 +119,7 @@ void fastboot_boot(void) if (s) { run_command(s, CMD_FLAG_ENV); } else { - static char boot_addr_start[12]; + static char boot_addr_start[20]; static char *const bootm_args[] = { "bootm", boot_addr_start, NULL }; diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index ba85baac603..ee7d9cb9571 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -174,11 +174,11 @@ static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) } /* setup mtd and nand structs and init mxs_nand driver */ -static int mxs_nand_init(void) +void nand_init(void) { /* return if already initalized */ if (nand_chip.numchips) - return 0; + return; /* init mxs nand driver */ mxs_nand_init_spl(&nand_chip); @@ -191,7 +191,8 @@ static int mxs_nand_init(void) /* identify flash device */ if (mxs_flash_ident(mtd)) { printf("Failed to identify\n"); - return -1; + nand_chip.numchips = 0; /* If fail, don't use nand */ + return; } /* allocate and initialize buffers */ @@ -202,8 +203,6 @@ static int mxs_nand_init(void) mtd->size = nand_chip.chipsize; nand_chip.scan_bbt(mtd); mxs_nand_setup_ecc(mtd); - - return 0; } int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) @@ -213,9 +212,9 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) unsigned int nand_page_per_block; unsigned int sz = 0; - if (mxs_nand_init()) - return -ENODEV; chip = mtd_to_nand(mtd); + if (!chip->numchips) + return -ENODEV; page = offs >> chip->page_shift; nand_page_per_block = mtd->erasesize / mtd->writesize; @@ -256,10 +255,6 @@ int nand_default_bbt(struct mtd_info *mtd) return 0; } -void nand_init(void) -{ -} - void nand_deselect(void) { } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index a14fe43a5b0..f991b40b385 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1284,22 +1284,16 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { struct phy_device *phydev; int addr; - int mask = 0xffffffff; addr = device_get_phy_addr(dev); - if (addr >= 0) - mask = 1 << addr; - #ifdef CONFIG_FEC_MXC_PHYADDR - mask = 1 << CONFIG_FEC_MXC_PHYADDR; + addr = CONFIG_FEC_MXC_PHYADDR; #endif - phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + phydev = phy_connect(priv->bus, addr, dev, priv->interface); if (!phydev) return -ENODEV; - phy_connect_dev(phydev, dev); - priv->phydev = phydev; phy_config(phydev); diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index a51b8a46254..cc59b21f9f4 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -28,6 +28,7 @@ #define MC_MEM_SIZE_ENV_VAR "mcmemsize" #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout" #define MC_BOOT_ENV_VAR "mcinitcmd" +#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024) DECLARE_GLOBAL_DATA_PTR; static int mc_memset_resv_ram; @@ -421,9 +422,11 @@ static int mc_fixup_dpc(u64 dpc_addr) /* fixup MAC addresses for dpmac ports */ nodeoffset = fdt_path_offset(blob, "/board_info/ports"); if (nodeoffset < 0) - return 0; + goto out; err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC); + +out: flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); return err; @@ -680,7 +683,8 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t mc_ram_size = mc_get_dram_block_size(); mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; - if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) { + + if (mc_ram_num_256mb_blocks >= 0xff) { error = -EINVAL; printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", mc_ram_size); @@ -688,6 +692,12 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) } /* + * To support 128 MB DDR Size for MC + */ + if (mc_ram_num_256mb_blocks == 0) + mc_ram_num_256mb_blocks = 0xFF; + + /* * Management Complex cores should be held at reset out of POR. * U-Boot should be the first software to touch MC. To be safe, * we reset all cores again by setting GCR1 to 0. It doesn't do @@ -727,8 +737,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Tell MC what is the address range of the DRAM block assigned to it: */ - reg_mcfbalr = (u32)mc_ram_addr | - (mc_ram_num_256mb_blocks - 1); + if (mc_ram_num_256mb_blocks < 0xFF) { + reg_mcfbalr = (u32)mc_ram_addr | + (mc_ram_num_256mb_blocks - 1); + } else { + reg_mcfbalr = (u32)mc_ram_addr | + (mc_ram_num_256mb_blocks); + } + out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)(mc_ram_addr >> 32)); @@ -878,7 +894,7 @@ unsigned long mc_get_dram_block_size(void) "\' environment variable: %lu\n", dram_block_size); - dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE; } } diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 43210532ba4..c3260d318cc 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -93,7 +93,7 @@ void fsl_rgmii_init(void) u32 ec; #ifdef CONFIG_SYS_FSL_EC1 - ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR]) & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK; ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT; @@ -102,7 +102,7 @@ void fsl_rgmii_init(void) #endif #ifdef CONFIG_SYS_FSL_EC2 - ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR]) & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK; ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT; diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index 7dd46c04f62..1fbeb0d14b6 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -91,7 +91,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; - if (!ec) + if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV)) wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); #endif @@ -100,7 +100,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; - if (!ec) + if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV)) wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); #endif } diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 6026fa67f92..e21dc10c2fa 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -369,6 +369,12 @@ static int mvebu_get_tgt_attr(ofnode node, int devfn, if (!range) return -EINVAL; + /* + * Linux uses of_n_addr_cells() to get the number of address cells + * here. Currently this function is only available in U-Boot when + * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in + * general, lets't hardcode the "pna" value in the U-Boot code. + */ pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */ rangesz = pna + na + ns; nranges = rlen / sizeof(__be32) / rangesz; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index f1d5a5c50d3..61f93be42d2 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -75,6 +75,20 @@ config PINCTRL_IMX8 only parses the 'fsl,pins' property and configures related registers. +config PINCTRL_IMX8M + bool "IMX8M pinctrl driver" + depends on ARCH_IMX8M && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx8m pinctrl driver + + This provides a simple pinctrl driver for i.MX8M SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configure related + registers. + config PINCTRL_VYBRID bool "Vybrid (vf610) pinctrl driver" depends on ARCH_VF610 && PINCTRL_FULL diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 891ee6e4774..b340d9448aa 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o +obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c new file mode 100644 index 00000000000..8bb03b7a62b --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info; + +static int imx8mq_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx8m_pinctrl_match[] = { + { .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, + { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx8mq_pinctrl) = { + .name = "imx8mq-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx8m_pinctrl_match), + .probe = imx8mq_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 6f355b969a6..9118b8eb39e 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -35,10 +35,22 @@ int regulator_get_value(struct udevice *dev) return ops->get_value(dev); } +static void regulator_set_value_ramp_delay(struct udevice *dev, int old_uV, + int new_uV, unsigned int ramp_delay) +{ + int delay = DIV_ROUND_UP(abs(new_uV - old_uV), ramp_delay); + + debug("regulator %s: delay %u us (%d uV -> %d uV)\n", dev->name, delay, + old_uV, new_uV); + + udelay(delay); +} + int regulator_set_value(struct udevice *dev, int uV) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); struct dm_regulator_uclass_platdata *uc_pdata; + int ret, old_uV = uV, is_enabled = 0; uc_pdata = dev_get_uclass_platdata(dev); if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV) @@ -49,7 +61,20 @@ int regulator_set_value(struct udevice *dev, int uV) if (!ops || !ops->set_value) return -ENOSYS; - return ops->set_value(dev, uV); + if (uc_pdata->ramp_delay) { + is_enabled = regulator_get_enable(dev); + old_uV = regulator_get_value(dev); + } + + ret = ops->set_value(dev, uV); + + if (!ret) { + if (uc_pdata->ramp_delay && old_uV > 0 && is_enabled) + regulator_set_value_ramp_delay(dev, old_uV, uV, + uc_pdata->ramp_delay); + } + + return ret; } /* @@ -107,6 +132,7 @@ int regulator_set_enable(struct udevice *dev, bool enable) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); struct dm_regulator_uclass_platdata *uc_pdata; + int ret, old_enable = 0; if (!ops || !ops->set_enable) return -ENOSYS; @@ -115,7 +141,22 @@ int regulator_set_enable(struct udevice *dev, bool enable) if (!enable && uc_pdata->always_on) return -EACCES; - return ops->set_enable(dev, enable); + if (uc_pdata->ramp_delay) + old_enable = regulator_get_enable(dev); + + ret = ops->set_enable(dev, enable); + if (!ret) { + if (uc_pdata->ramp_delay && !old_enable && enable) { + int uV = regulator_get_value(dev); + + if (uV > 0) { + regulator_set_value_ramp_delay(dev, 0, uV, + uc_pdata->ramp_delay); + } + } + } + + return ret; } int regulator_set_enable_if_allowed(struct udevice *dev, bool enable) @@ -335,6 +376,8 @@ static int regulator_pre_probe(struct udevice *dev) -ENODATA); uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); + uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", + 0); /* Those values are optional (-ENODATA if unset) */ if ((uc_pdata->min_uV != -ENODATA) && diff --git a/drivers/power/regulator/s2mps11_regulator.c b/drivers/power/regulator/s2mps11_regulator.c index ced504eb147..67d1f9689de 100644 --- a/drivers/power/regulator/s2mps11_regulator.c +++ b/drivers/power/regulator/s2mps11_regulator.c @@ -346,6 +346,8 @@ static int s2mps11_ldo_hex2volt(int ldo, int hex) case 11: case 22: case 23: + case 27: + case 35: uV = hex * S2MPS11_LDO_STEP + S2MPS11_LDO_UV_MIN; break; default: @@ -366,6 +368,8 @@ static int s2mps11_ldo_volt2hex(int ldo, int uV) case 11: case 22: case 23: + case 27: + case 35: hex = (uV - S2MPS11_LDO_UV_MIN) / S2MPS11_LDO_STEP; break; default: @@ -547,7 +551,16 @@ static int ldo_get_enable(struct udevice *dev) static int ldo_set_enable(struct udevice *dev, bool enable) { - return s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable); + int ret; + + ret = s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable); + if (ret) + return ret; + + /* Wait the "enable delay" for voltage to start to rise */ + udelay(15); + + return 0; } static int ldo_get_mode(struct udevice *dev) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index df35ac9114e..476df258059 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -178,7 +178,7 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk, writel(UCR1_UARTEN, &base->cr1); } -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) #ifndef CONFIG_MXC_UART_BASE #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" @@ -260,7 +260,7 @@ __weak struct serial_device *default_serial_console(void) } #endif -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) int mxc_serial_setbrg(struct udevice *dev, int baudrate) { diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index 20b958cfd41..009f3766027 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -10,8 +10,10 @@ #include <sysreset.h> #include <asm/io.h> #include <asm/processor.h> +#include <efi_loader.h> -static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) +static __efi_runtime int x86_sysreset_request(struct udevice *dev, + enum sysreset_t type) { int value; @@ -31,6 +33,25 @@ static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EINPROGRESS; } +#ifdef CONFIG_EFI_LOADER +void __efi_runtime EFIAPI efi_reset_system( + enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, void *reset_data) +{ + if (reset_type == EFI_RESET_COLD || + reset_type == EFI_RESET_PLATFORM_SPECIFIC) + x86_sysreset_request(NULL, SYSRESET_COLD); + else if (reset_type == EFI_RESET_WARM) + x86_sysreset_request(NULL, SYSRESET_WARM); + + /* TODO EFI_RESET_SHUTDOWN */ + + while (1) { } +} +#endif + + static const struct udevice_id x86_sysreset_ids[] = { { .compatible = "x86,reset" }, { } diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index 8d7864797a7..3053ccf7d97 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -23,8 +23,11 @@ int usb_gadget_initialize(int index) return 0; ret = uclass_get_device_by_seq(UCLASS_USB_GADGET_GENERIC, index, &dev); if (!dev || ret) { - pr_err("No USB device found\n"); - return -ENODEV; + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, &dev); + if (!dev || ret) { + pr_err("No USB device found\n"); + return -ENODEV; + } } dev_array[index] = dev; return 0; @@ -81,40 +81,6 @@ static int setup_flash_device(void) return 0; } -static int is_end(const char *addr, size_t size) -{ - /* The end of env variables is marked by '\0\0' */ - int i = 0; - - for (i = 0; i < size - 1; ++i) - if (addr[i] == 0x0 && addr[i + 1] == 0x0) - return 1; - return 0; -} - -static int spi_flash_read_env(struct spi_flash *flash, u32 offset, size_t len, - void *buf) -{ - u32 addr = 0; - u32 page_size = flash->page_size; - - memset(buf, 0x0, len); - for (int i = 0; i < len / page_size; ++i) { - int ret = spi_flash_read(flash, offset, page_size, - &((char *)buf)[addr]); - - if (ret < 0) - return ret; - - if (is_end(&((char *)buf)[addr], page_size)) - return 0; - - addr += page_size; - offset += page_size; - } - return 0; -} - #if defined(CONFIG_ENV_OFFSET_REDUND) #ifdef CMD_SAVEENV static int env_sf_save(void) @@ -150,8 +116,8 @@ static int env_sf_save(void) ret = -ENOMEM; goto done; } - ret = spi_flash_read_env(env_flash, saved_offset, - saved_size, saved_buffer); + ret = spi_flash_read(env_flash, saved_offset, + saved_size, saved_buffer); if (ret) goto done; } @@ -217,10 +183,10 @@ static int env_sf_load(void) if (ret) goto out; - read1_fail = spi_flash_read_env(env_flash, CONFIG_ENV_OFFSET, - CONFIG_ENV_SIZE, tmp_env1); - read2_fail = spi_flash_read_env(env_flash, CONFIG_ENV_OFFSET_REDUND, - CONFIG_ENV_SIZE, tmp_env2); + read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET, + CONFIG_ENV_SIZE, tmp_env1); + read2_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET_REDUND, + CONFIG_ENV_SIZE, tmp_env2); ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2, read2_fail); @@ -254,8 +220,8 @@ static int env_sf_save(void) if (!saved_buffer) goto done; - ret = spi_flash_read_env(env_flash, saved_offset, - saved_size, saved_buffer); + ret = spi_flash_read(env_flash, saved_offset, + saved_size, saved_buffer); if (ret) goto done; } @@ -311,10 +277,10 @@ static int env_sf_load(void) if (ret) goto out; - ret = spi_flash_read_env(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - buf); + ret = spi_flash_read(env_flash, + CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, buf); if (ret) { - set_default_env("spi_flash_read_env() failed", 0); + set_default_env("spi_flash_read() failed", 0); goto err_read; } diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index 4e3b26c25cd..5aeb009f030 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -21,8 +21,6 @@ /* select serial console configuration */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 7baa265934f..571852d803a 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -43,19 +43,30 @@ "fdt_addr=" FDT_ADDR "\0" \ "boot_fdt=try\0" \ "mmcpart=1\0" \ + "recovery_device=0\0" \ + "recovery_part=2\0" \ + "recovery_root=/dev/mmcblk0p2 rootwait rw\0" \ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ + "recovery_mmcargs= setenv bootargs console=${console},${baudrate} "\ + "root=${recovery_root}\0" \ "ubiargs=setenv bootargs console=${console},${baudrate} " \ "ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ + "recovery_loadimage=ext2load mmc ${recovery_device}:${recovery_part} ${loadaddr} ${image}\0" \ + "recovery_loadfdt=ext2load mmc ${recovery_device}:${recovery_part} ${fdt_addr} ${fdt_file}\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \ + "altbootcmd=run recovery_boot\0"\ + "recovery_boot=echo Recovery Boot from mmc ...; " \ + "run recovery_loadimage ; run recovery_loadfdt; run recovery_mmcargs; "\ + "bootm ${loadaddr} - ${fdt_addr}\0" \ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 70cc63fc1b9..a121064e373 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -68,8 +68,8 @@ "nandboot=echo Booting from nand ...; " \ " run nandargs;" \ " nand read ${loadaddr} kernel ${kernelsize};" \ - " nand read ${fdt_addr} dtb;" \ - " bootz ${loadaddr} - ${fdt_addr}\0" \ + " nand read ${fdt_addr_r} dtb;" \ + " bootz ${loadaddr} - ${fdt_addr_r}\0" \ "nandramboot=echo Booting RAMdisk from nand ...; " \ " nand read ${ramdisk_addr_r} fs ${ramdisksize};" \ " nand read ${loadaddr} kernel ${kernelsize};" \ @@ -88,8 +88,8 @@ "fi; " \ "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ + "if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ "else " \ "if test ${boot_fdt} = try; then " \ "bootz; " \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index f0430224cb8..a9e38a70e60 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -187,7 +187,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OFFSET (64 * SZ_64K) #define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 6be8df109bd..4af3988886a 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -85,6 +85,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + /* * Serial Port */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 4b6760b600d..da55bf2f43b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -104,6 +104,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ !defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FMAN_FW_IN_NOR diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index a80ce928811..50c18f15425 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -147,7 +147,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Command line configuration */ #define CONFIG_CMD_CACHE diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 60a0b425035..454c9e94b66 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -152,7 +152,7 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Command line configuration */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 4b5608b5a3e..637619cb555 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -100,7 +100,7 @@ * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #endif /* I2C bus multiplexer */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b8809c8dcc7..9f2d43e3fa3 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -132,7 +132,7 @@ "setenv kernelname Image.itb;" \ "run loadkernel;" \ "run kernel_args;" \ - "bootm ${kernel_addr_r}#${boardname}\0" \ + "bootm ${kernel_addr_r}#${board_name}\0" \ "boot_uimg=" \ "setenv kernelname uImage;" \ "run check_dtb;" \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index f178549a722..af6004eaf51 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -7,7 +7,7 @@ #ifndef __CONFIG_ODROID_XU3_H #define __CONFIG_ODROID_XU3_H -#include "exynos5420-common.h" +#include <configs/exynos5420-common.h> #include <configs/exynos5-common.h> #define CONFIG_BOARD_COMMON @@ -18,7 +18,7 @@ #define TZPC_BASE_OFFSET 0x10000 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ /* Reserve the last 22 MiB for the secure firmware */ #define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL) #define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE @@ -28,7 +28,7 @@ #define CONFIG_ENV_SIZE (SZ_1K * 16) #define CONFIG_ENV_OFFSET (SZ_1K * 3136) /* ~3 MiB offset */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" @@ -38,7 +38,7 @@ /* DFU */ #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define DFU_MANIFEST_POLL_TIMEOUT 25000 +#define DFU_MANIFEST_POLL_TIMEOUT 25000 /* THOR */ #define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_USB_GADGET_VENDOR_NUM @@ -84,12 +84,16 @@ #define CONFIG_SET_DFU_ALT_INFO #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) -/* Set soc_rev, soc_id, board_rev, boardname, fdtfile */ -#define CONFIG_ODROID_REV_AIN 9 +/* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ +#define CONFIG_ODROID_REV_AIN 9 #define CONFIG_REVISION_TAG +/* + * Need to override existing one (smdk5420) with odroid so set_board_info will + * use proper prefix when creating full board_name (SYS_BOARD + type) + */ #undef CONFIG_SYS_BOARD -#define CONFIG_SYS_BOARD "odroid" +#define CONFIG_SYS_BOARD "odroid" /* Define new extra env settings, including DFU settings */ #undef CONFIG_EXTRA_ENV_SETTINGS @@ -101,7 +105,7 @@ "rootfstype=ext4\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ "fdtfile=exynos5422-odroidxu3.dtb\0" \ - "boardname=odroidxu3\0" \ + "board_name=odroidxu3\0" \ "mmcbootdev=0\0" \ "mmcrootdev=0\0" \ "mmcbootpart=1\0" \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8082b74c9c5..050f69801b4 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -128,17 +128,9 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 #define CONFIG_SYS_I2C_SPEED 100000 -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - /* environment organization */ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_OFFSET (8 * SZ_64K) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 181af9b646a..191204b27be 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -248,8 +248,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * 0xFFEz_zzzz ...... Malloc area (grows up to top) * 0xFFE3_FFFF ...... End of SRAM (top) */ +#ifndef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#endif #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) /* SPL memory allocation configuration, this is for FAT implementation */ diff --git a/include/power/regulator.h b/include/power/regulator.h index 314160a894b..6c6e2cd4f99 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -150,6 +150,7 @@ enum regulator_flag { * @always_on* - bool type, true or false * @boot_on* - bool type, true or false * TODO(sjg@chromium.org): Consider putting the above two into @flags + * @ramp_delay - Time to settle down after voltage change (unit: uV/us) * @flags: - flags value (see REGULATOR_FLAG_...) * @name** - fdt regulator name - should be taken from the device tree * ctrl_reg: - Control register offset used to enable/disable regulator @@ -169,6 +170,7 @@ struct dm_regulator_uclass_platdata { int max_uV; int min_uA; int max_uA; + unsigned int ramp_delay; bool always_on; bool boot_on; const char *name; diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 017560c2566..4ff28a1df0e 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -33,6 +33,7 @@ char *get_dfu_alt_system(char *interface, char *devstr); char *get_dfu_alt_boot(char *interface, char *devstr); #endif void set_board_type(void); +void set_board_revision(void); const char *get_board_type(void); #endif /* __SAMSUNG_MISC_COMMON_H__ */ diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 66c33a551d5..8e0965bfc89 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -62,6 +62,21 @@ static struct simple_text_output_mode efi_con_mode = { .cursor_visible = 1, }; +static int term_get_char(s32 *c) +{ + u64 timeout; + + /* Wait up to 100 ms for a character */ + timeout = timer_get_us() + 100000; + + while (!tstc()) + if (timer_get_us() > timeout) + return 1; + + *c = getc(); + return 0; +} + /* * Receive and parse a reply from the terminal. * @@ -72,34 +87,36 @@ static struct simple_text_output_mode efi_con_mode = { */ static int term_read_reply(int *n, int num, char end_char) { - char c; + s32 c; int i = 0; - c = getc(); - if (c != cESC) + if (term_get_char(&c) || c != cESC) return -1; - c = getc(); - if (c != '[') + + if (term_get_char(&c) || c != '[') return -1; n[0] = 0; while (1) { - c = getc(); - if (c == ';') { - i++; - if (i >= num) + if (!term_get_char(&c)) { + if (c == ';') { + i++; + if (i >= num) + return -1; + n[i] = 0; + continue; + } else if (c == end_char) { + break; + } else if (c > '9' || c < '0') { return -1; - n[i] = 0; - continue; - } else if (c == end_char) { - break; - } else if (c > '9' || c < '0') { + } + + /* Read one more decimal position */ + n[i] *= 10; + n[i] += c - '0'; + } else { return -1; } - - /* Read one more decimal position */ - n[i] *= 10; - n[i] += c - '0'; } if (i != num - 1) return -1; @@ -196,7 +213,6 @@ static int query_console_serial(int *rows, int *cols) { int ret = 0; int n[2]; - u64 timeout; /* Empty input buffer */ while (tstc()) @@ -216,14 +232,6 @@ static int query_console_serial(int *rows, int *cols) ESC "[999;999H" /* Move to bottom right corner */ ESC "[6n"); /* Query cursor position */ - /* Allow up to one second for a response */ - timeout = timer_get_us() + 1000000; - while (!tstc()) - if (timer_get_us() > timeout) { - ret = -1; - goto out; - } - /* Read {rows,cols} */ if (term_read_reply(n, 2, 'R')) { ret = 1; diff --git a/lib/efi_selftest/efi_freestanding.c b/lib/efi_selftest/efi_freestanding.c new file mode 100644 index 00000000000..4b6c27e99fb --- /dev/null +++ b/lib/efi_selftest/efi_freestanding.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Library for freestanding binary + * + * Copyright 2019, Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * GCC requires that freestanding programs provide memcpy(), memmove(), + * memset(), and memcmp(). + */ + +#include "../efi_loader/efi_freestanding.c" diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index ec5c41ec561..70de9bb13a6 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -390,7 +390,7 @@ $(obj)/efi_reloc.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_RELOC:.o=.c) $(recordmcoun $(call cmd,force_checksrc) $(call if_changed_rule,cc_o_c) -$(obj)/%_efi.so: $(obj)/%.o $(obj)/efi_crt0.o $(obj)/efi_reloc.o $(obj)/../efi_loader/efi_freestanding.o +$(obj)/%_efi.so: $(obj)/%.o $(obj)/efi_crt0.o $(obj)/efi_reloc.o $(obj)/efi_freestanding.o $(call cmd,efi_ld) # ACPI |