diff options
692 files changed, 13585 insertions, 5194 deletions
@@ -208,7 +208,8 @@ config SYS_EXTRA_OPTIONS new boards should not use this option. config SYS_TEXT_BASE - depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP + depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \ + (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE depends on !EFI_APP hex "Text Base" help diff --git a/MAINTAINERS b/MAINTAINERS index 607bc9cbdbd..b3872071c5f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -93,12 +93,14 @@ F: arch/arm/include/asm/arch-mx*/ F: arch/arm/include/asm/arch-vf610/ F: arch/arm/include/asm/imx-common/ -ARM MARVELL KIRKWOOD +ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X M: Prafulla Wadaskar <prafulla@marvell.com> M: Luka Perkov <luka.perkov@sartura.hr> +M: Stefan Roese <sr@denx.de> S: Maintained T: git git://git.denx.de/u-boot-marvell.git F: arch/arm/mach-kirkwood/ +F: arch/arm/mach-mvebu/ ARM MARVELL PXA M: Marek Vasut <marex@denx.de> @@ -107,6 +109,12 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM ROCKCHIP +M: Simon Glass <sjg@chromium.org> +S: Maintained +T: git git://git.denx.de/u-boot-rockchip.git +F: arch/arm/mach-rockchip/ + ARM SAMSUNG M: Minkyu Kang <mk7.kang@samsung.com> S: Maintained @@ -591,12 +591,6 @@ endif # Prohibit date/time macros, which would make the build non-deterministic KBUILD_CFLAGS += $(call cc-option,-Werror=date-time) -ifneq ($(CONFIG_SYS_TEXT_BASE),) -KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -endif - -export CONFIG_SYS_TEXT_BASE - include scripts/Makefile.extrawarn # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments @@ -915,18 +909,8 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) -# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU -# SoC's, the SPL U-Boot returns to the BootROM after it completes -# the SDRAM setup. The BootROM expects no U-Boot header in the main -# U-Boot image. So we need to combine SPL and u-boot.bin instead of -# u-boot.img in this case. -ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT -u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE - $(call if_changed,mkimage) -else u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) -endif MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) @@ -890,15 +890,6 @@ The following options need to be configured: 'Sane' compilers will generate smaller code if CONFIG_PRE_CON_BUF_SZ is a power of 2 -- Safe printf() functions - Define CONFIG_SYS_VSNPRINTF to compile in safe versions of - the printf() functions. These are defined in - include/vsprintf.h and include snprintf(), vsnprintf() and - so on. Code size increase is approximately 300-500 bytes. - If this option is not given then these functions will - silently discard their buffer size argument - this means - you are not getting any overflow checking in this case. - - Boot Delay: CONFIG_BOOTDELAY - in seconds Delay before automatically booting the default image; set to -1 to disable autoboot. @@ -5118,14 +5109,11 @@ If the system board that you have is not listed, then you will need to port U-Boot to your hardware platform. To do this, follow these steps: -1. Add a new configuration option for your board to the toplevel - "boards.cfg" file, using the existing entries as examples. - Follow the instructions there to keep the boards in order. -2. Create a new directory to hold your board specific code. Add any +1. Create a new directory to hold your board specific code. Add any files you need. In your board directory, you will need at least - the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds". -3. Create a new configuration file "include/configs/<board>.h" for - your board + the "Makefile" and a "<board>.c". +2. Create a new configuration file "include/configs/<board>.h" for + your board. 3. If you're porting U-Boot to a new CPU, then also create a new directory to hold your CPU specific code. Add any files you need. 4. Run "make <board>_defconfig" with your new name. diff --git a/api/api_storage.c b/api/api_storage.c index ec92ae48d1c..bc2b4d6b8cc 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -345,19 +345,6 @@ int dev_close_stor(void *cookie) } -static int dev_stor_index(block_dev_desc_t *dd) -{ - int i, type; - - type = dev_stor_type(dd); - for (i = 0; i < specs[type].max_dev; i++) - if (dd == get_dev(specs[type].name, i)) - return i; - - return (specs[type].max_dev); -} - - lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start) { int type; @@ -374,5 +361,5 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start return 0; } - return (dd->block_read(dev_stor_index(dd), start, len, buf)); + return dd->block_read(dd, start, len, buf); } diff --git a/arch/Kconfig b/arch/Kconfig index 1709d40e97e..ec120139cba 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -55,6 +55,7 @@ config MIPS select HAVE_PRIVATE_LIBGCC select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD + select SUPPORT_OF_CONTROL config NDS32 bool "NDS32 architecture" diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 26a59341893..90ee7e0fe40 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -50,18 +50,20 @@ ENTRY(_start) 1: #endif - /* Setup stack- and frame-pointers */ + /* Establish C runtime stack and frame */ mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp - /* Allocate and zero GD, update SP */ + /* Allocate reserved area from current top of stack */ mov %r0, %sp - bl board_init_f_mem - - /* Update stack- and frame-pointers */ + bl board_init_f_alloc_reserve + /* Set stack below reserved area, adjust frame pointer accordingly */ mov %sp, %r0 mov %fp, %sp + /* Initialize reserved area - note: r0 already contains address */ + bl board_init_f_init_reserve + /* Zero the one and only argument of "board_init_f" */ mov_s %r0, 0 j board_init_f diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9bd6cf1d807..876a620cf19 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -117,7 +117,14 @@ config ARCH_MVEBU select OF_CONTROL select OF_SEPARATE select DM + select DM_ETH select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_OF_CONTROL + select SPL_SIMPLE_BUS config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -695,8 +702,8 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) -config TARGET_STM32F429_DISCOVERY - bool "Support STM32F429 Discovery" +config STM32 + bool "Support STM32" select CPU_V7M select DM select DM_SERIAL @@ -709,6 +716,10 @@ config ARCH_ROCKCHIP select CPU_V7 select DM +config TARGET_THUNDERX_88XX + bool "Support ThunderX 88xx" + select OF_CONTROL + endchoice source "arch/arm/mach-at91/Kconfig" @@ -751,6 +762,8 @@ source "arch/arm/mach-s5pc1xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig" +source "arch/arm/mach-stm32/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-uniphier/Kconfig" @@ -769,8 +782,6 @@ source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" -source "board/Marvell/db-88f6820-gp/Kconfig" -source "board/Marvell/db-mv784mp-gp/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" @@ -779,6 +790,7 @@ source "board/bluegiga/apx4devkit/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" +source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" @@ -809,7 +821,6 @@ source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" -source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" @@ -827,7 +838,6 @@ source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" -source "board/st/stm32f429-discovery/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/zmx25/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 18283d1d359..cd7d8803f3b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -49,13 +49,14 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood -machine-$(CONFIG_ARMADA_XP) += mvebu +machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip +machine-$(CONFIG_STM32) += stm32 machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b1c3f8f4ad8..b6db23e981f 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -5,12 +5,14 @@ */ #include <common.h> -#include <asm/arch/cpu.h> +#include <dm.h> +#include <ns16550.h> +#include <dm/platform_data/lpc32xx_hsuart.h> + #include <asm/arch/clk.h> #include <asm/arch/uart.h> #include <asm/arch/mux.h> #include <asm/io.h> -#include <dm.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; @@ -41,6 +43,37 @@ void lpc32xx_uart_init(unsigned int uart_id) &clk->u3clk + (uart_id - 3)); } +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct ns16550_platdata lpc32xx_uart[] = { + { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK }, +}; + +#if defined(CONFIG_LPC32XX_HSUART) +static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = { + { HS_UART1_BASE, }, + { HS_UART2_BASE, }, + { HS_UART7_BASE, }, +}; +#endif + +U_BOOT_DEVICES(lpc32xx_uarts) = { +#if defined(CONFIG_LPC32XX_HSUART) + { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, + { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, +#endif + { "ns16550_serial", &lpc32xx_uart[0], }, + { "ns16550_serial", &lpc32xx_uart[1], }, + { "ns16550_serial", &lpc32xx_uart[2], }, + { "ns16550_serial", &lpc32xx_uart[3], }, +#if defined(CONFIG_LPC32XX_HSUART) + { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, +#endif +}; +#endif + void lpc32xx_dma_init(void) { /* Enable DMA interface */ diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c index 602d993e393..52ea7342dfb 100644 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ b/arch/arm/cpu/armv7/omap-common/utils.c @@ -108,6 +108,6 @@ void omap_die_id_display(void) omap_die_id(die_id); - printf("OMAP die ID: %08x%08x%08x%08x", die_id[0], die_id[1], die_id[2], - die_id[3]); + printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1], + die_id[2], die_id[3]); } diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 4501884e1c2..1da5455c9ad 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -77,6 +77,16 @@ int clock_twi_onoff(int port, int state) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (port == 5) { + if (state) + prcm_apb0_enable( + PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); + else + prcm_apb0_disable( + PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); + return 0; + } + /* set the apb clock gate for twi */ if (state) setbits_le32(&ccm->apb2_gate, diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c index 19b4938dc97..e1d091fd577 100644 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -33,3 +33,15 @@ void prcm_apb0_enable(u32 flags) /* deassert reset for module */ setbits_le32(&prcm->apb0_reset, flags); } + +void prcm_apb0_disable(u32 flags) +{ + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* assert reset for module */ + clrbits_le32(&prcm->apb0_reset, flags); + + /* close the clock for module */ + clrbits_le32(&prcm->apb0_gate, flags); +} diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 93a19566f51..aff60e8102e 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -7,6 +7,3 @@ extra-y := start.o obj-y += cpu.o - -obj-$(CONFIG_STM32F1) += stm32f1/ -obj-$(CONFIG_STM32F4) += stm32f4/ diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 48c041bb9b3..1c85aa924db 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,6 +14,7 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-y += fwcall.o obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 53bac3b4495..71f0020c7f9 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,69 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_SYS_FULL_VA +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{ + u64 *pgd = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = ptl2_entry | PTL1_TYPE_TABLE; + pgd[index] = value; +} + +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs) +{ + u64 *pmd = (u64 *)ptl1; + u64 value; + + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF; + value |= memory_attrs; + pmd[bfn] = value; +} + +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP; + +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES + +static void setup_pgtables(void) +{ + int l1_e, l2_e; + unsigned long pmd = 0; + unsigned long address; + + /* Setup the PMD pointers */ + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) { + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr + + PTL1_ENTRIES * sizeof(u64); + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e; + gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e], + 0x10000UL); + } + + /* Setup the page tables */ + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) { + if (mem_map[pmd].base == + (uintptr_t)l1_e << PTL2_BITS) { + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]); + + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) { + address = mem_map[pmd].base + + (uintptr_t)l2_e * BLOCK_SIZE; + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e, + address, mem_map[pmd].attrs); + } + + pmd++; + } else { + set_ptl1_entry(l1_e, 0); + } + } +} + +#else + inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, u64 attribute) { @@ -30,14 +93,24 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) value = (u64)table_addr | PMD_TYPE_TABLE; page_table[index] = value; } +#endif /* to activate the MMU we need to set up virtual memory */ __weak void mmu_setup(void) { +#ifndef CONFIG_SYS_FULL_VA bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; +#endif int el; +#ifdef CONFIG_SYS_FULL_VA + unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK; + + /* Set up page tables only on BSP */ + if (coreid == BSP_COREID) + setup_pgtables(); +#else /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, @@ -55,6 +128,7 @@ __weak void mmu_setup(void) } } +#endif /* load TTBR0 */ el = current_el(); if (el == 1) { @@ -154,6 +228,7 @@ u64 *__weak arch_get_page_table(void) { return NULL; } +#ifndef CONFIG_SYS_FULL_VA void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { @@ -179,6 +254,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(start, end); asm volatile("dsb sy"); } +#endif + #else /* CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c new file mode 100644 index 00000000000..9efcc5ada91 --- /dev/null +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,75 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <asm-offsets.h> +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/system.h> + +/* + * Issue the hypervisor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ +void hvc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "ldr x7, %7\n" + "hvc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]), "m" (args->regs[7]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} + +/* + * void smc_call(arg0, arg1...arg7) + * + * issue the secure monitor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ + +void smc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "smc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index da45d984d01..2ee60d60f12 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -43,6 +43,9 @@ _bss_end_ofs: .quad __bss_end - _start reset: +#ifdef CONFIG_SYS_RESET_SCTRL + bl reset_sctrl +#endif /* * Could be EL3/EL2/EL1, Initial State: * Little Endian, MMU Disabled, i/dCache Disabled @@ -99,6 +102,39 @@ master_cpu: bl _main +#ifdef CONFIG_SYS_RESET_SCTRL +reset_sctrl: + switch_el x1, 3f, 2f, 1f +3: + mrs x0, sctlr_el3 + b 0f +2: + mrs x0, sctlr_el2 + b 0f +1: + mrs x0, sctlr_el1 + +0: + ldr x1, =0xfdfffffa + and x0, x0, x1 + + switch_el x1, 6f, 5f, 4f +6: + msr sctlr_el3, x0 + b 7f +5: + msr sctlr_el2, x0 + b 7f +4: + msr sctlr_el1, x0 + +7: + dsb sy + isb + b __asm_invalidate_tlb_all + ret +#endif + /*-----------------------------------------------------------------------*/ WEAK(apply_core_errata) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bcd3163756..e4f8aaef55f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -48,8 +48,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-388-clearfog.dtb \ armada-388-gp.dtb \ - armada-xp-gp.dtb + armada-xp-gp.dtb \ + armada-xp-maxbcm.dtb \ + armada-xp-synology-ds414.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ @@ -74,6 +77,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb +dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 3fffe1eec3e..c95d1d3b35d 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -25,6 +25,7 @@ serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + spi0 = &qspi; }; cpus { @@ -908,7 +909,9 @@ qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts index 3f9d8080910..89feaf3eb71 100644 --- a/arch/arm/dts/am437x-sk-evm.dts +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -567,7 +567,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "mx66l51235l"; + compatible = "mx66l51235l","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi index a718866ba52..0b2a78d3930 100644 --- a/arch/arm/dts/armada-370-xp.dtsi +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -141,6 +141,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + u-boot,dm-pre-reloc; rtc@10300 { compatible = "marvell,orion-rtc"; diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts new file mode 100644 index 00000000000..b2dfd564352 --- /dev/null +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -0,0 +1,509 @@ +/* + * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2015 Russell King + * + * This board is in development; the contents of this file work with + * the A1 rev 2.0 of the board, which does not represent final + * production board. Things will change, don't expect this file to + * remain compatible info the future. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-388.dtsi" + +/ { + model = "SolidRun Clearfog A1"; + compatible = "solidrun,clearfog-a1", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + ethernet2 = ð1; + ethernet3 = ð2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; + + internal-regs { + ethernet@30000 { + mac-address = [00 50 43 02 02 02]; + phy-mode = "sgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@34000 { + mac-address = [00 50 43 02 02 03]; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; + }; + + ethernet@70000 { + mac-address = [00 50 43 02 02 01]; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy_dedicated>; + phy-mode = "rgmii-id"; + status = "okay"; + }; + + i2c@11000 { + /* Is there anything on this? */ + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-CON3 CLKREQ# + * 1-CON3 PERST# + * 2-CON2 PERST# + * 3-CON3 W_DISABLE + * 4-CON2 CLKREQ# + * 5-USB3 overcurrent + * 6-USB3 power + * 7-CON2 W_DISABLE + * 8-JP4 P1 + * 9-JP4 P4 + * 10-JP4 P5 + * 11-m.2 DEVSLP + * 12-SFP_LOS + * 13-SFP_TX_FAULT + * 14-SFP_TX_DISABLE + * 15-SFP_MOD_DEF0 + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + pcie1_0_clkreq { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie1.0-clkreq"; + }; + pcie1_0_w_disable { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie1.0-w-disable"; + }; + pcie2_0_clkreq { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie2.0-clkreq"; + }; + pcie2_0_w_disable { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie2.0-w-disable"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + input; + line-name = "usb3-current-limit"; + }; + usb3_power { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb3-power"; + }; + m2_devslp { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2 devslp"; + }; + }; + + /* The MCP3021 is 100kHz clock only */ + mikrobus_adc: mcp3021@4c { + compatible = "microchip,mcp3021"; + reg = <0x4c>; + }; + + /* Also something at 0x64 */ + }; + + i2c@11100 { + /* + * Routed to SFP, mikrobus, and PCIe. + * SFP limits this to 100kHz, and requires + * an AT24C01A/02/04 with address pins tied + * low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C + * bus being present. + * PCIe uses ARP to assign addresses, or + * 0x63-0x64. + */ + clock-frequency = <100000>; + pinctrl-0 = <&clearfog_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + mdio@72004 { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy_dedicated: ethernet-phy@0 { + /* + * Annoyingly, the marvell phy driver + * configures the LED register, rather + * than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x101e>; + reg = <0>; + }; + }; + + pinctrl@18000 { + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + clearfog_dsa0_pins: clearfog-dsa0-pins { + marvell,pins = "mpp23", "mpp41"; + marvell,function = "gpio"; + }; + clearfog_i2c1_pins: i2c1-pins { + /* SFP, PCIe, mSATA, mikrobus */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + clearfog_sdhci_pins: clearfog-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + clearfog_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp55"; + marvell,function = "spi1"; + }; + mikro_pins: mikro-pins { + /* int: mpp22 rst: mpp29 */ + marvell,pins = "mpp22", "mpp29"; + marvell,function = "gpio"; + }; + mikro_spi_pins: mikro-spi-pins { + marvell,pins = "mpp43"; + marvell,function = "spi1"; + }; + mikro_uart_pins: mikro-uart-pins { + marvell,pins = "mpp24", "mpp25"; + marvell,function = "ua1"; + }; + rear_button_pins: rear-button-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + }; + + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" + * twice in u-boot. + */ + status = "okay"; + }; + + sata@a8000 { + /* pinctrl? */ + status = "okay"; + }; + + sata@e0000 { + /* pinctrl? */ + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&clearfog_sdhci_pins + &clearfog_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + serial@12100 { + /* mikrobus uart */ + pinctrl-0 = <&mikro_uart_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + spi@10680 { + /* + * We don't seem to have the W25Q32 on the + * A1 Rev 2.0 boards, so disable SPI. + * CS0: W25Q32 (doesn't appear to be present) + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "disabled"; + }; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * the mini-PCIe connectors on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0. CONN3, nearest power. */ + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0. CONN2, nearest CPU. */ + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; + sfp,ethernet = <ð2>; + tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + }; + + dsa@0 { + compatible = "marvell,dsa"; + dsa,ethernet = <ð1>; + dsa,mii-bus = <&mdio>; + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; + pinctrl-names = "default"; + #address-cells = <2>; + #size-cells = <0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4 0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + + port@6 { + /* 88E1512 external phy */ + reg = <6>; + label = "lan6"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button_0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_0>; + }; + }; +}; + +/* ++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 +MPP18: gpio ? (pca9655 int?) +MPP19: gpio ? (clkreq?) +MPP20: gpio ? (sd0 detect) +MPP21: sd0:cmd x sd0 +MPP22: gpio x mikro int +MPP23: gpio x switch irq ++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 +MPP24: ua1:rxd x mikro rx +MPP25: ua1:txd x mikro tx +MPP26: i2c1:sck x mikro sck +MPP27: i2c1:sda x mikro sda +MPP28: sd0:clk x sd0 +MPP29: gpio x mikro rst +MPP30: ge1:txd2 ? (config) +MPP31: ge1:txd3 ? (config) ++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 +MPP32: ge1:txctl ? (unused) +MPP33: gpio ? (pic_com0) +MPP34: gpio x rear button (pic_com1) +MPP35: gpio ? (pic_com2) +MPP36: gpio ? (unused) +MPP37: sd0:d3 x sd0 +MPP38: sd0:d0 x sd0 +MPP39: sd0:d1 x sd0 ++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 +MPP40: sd0:d2 x sd0 +MPP41: gpio x switch reset +MPP42: gpio ? sw1-1 +MPP43: spi1:cs2 x mikro cs +MPP44: sata3:prsnt ? (unused) +MPP45: ref:clk_out0 ? +MPP46: ref:clk_out1 x switch clk +MPP47: 4 ? (unused) ++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 +MPP48: tdm:pclk +MPP49: tdm:fsync +MPP50: tdm:drx +MPP51: tdm:dtx +MPP52: tdm:int +MPP53: tdm:rst +MPP54: gpio ? (pwm) +MPP55: spi1:cs1 x slic ++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 +MPP56: spi1:mosi x mikro mosi +MPP57: spi1:sck x mikro sck +MPP58: spi1:miso x mikro miso +MPP59: spi1:cs0 x w25q32 +*/ diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts index fd4f6fd8a2e..7bc878f5a92 100644 --- a/arch/arm/dts/armada-388-gp.dts +++ b/arch/arm/dts/armada-388-gp.dts @@ -51,6 +51,12 @@ stdout-path = "serial0:115200n8"; }; + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + spi0 = &spi0; + }; + memory { device_type = "memory"; reg = <0x00000000 0x80000000>; /* 2 GB */ @@ -65,8 +71,10 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "okay"; + u-boot,dm-pre-reloc; spi-flash@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; @@ -122,6 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; + u-boot,dm-pre-reloc; }; /* GE1 CON15 */ diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 04ecfe6e2bc..dc8a1a66c1f 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -70,6 +70,7 @@ soc { compatible = "marvell,armada380-mbus", "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; @@ -134,6 +135,7 @@ internal-regs { compatible = "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts index bf724ca96a3..27799d1254e 100644 --- a/arch/arm/dts/armada-xp-gp.dts +++ b/arch/arm/dts/armada-xp-gp.dts @@ -68,6 +68,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory { device_type = "memory"; /* @@ -148,6 +152,7 @@ internal-regs { serial@12000 { status = "okay"; + u-boot,dm-pre-reloc; }; serial@12100 { status = "okay"; @@ -223,8 +228,10 @@ spi0: spi@10600 { status = "okay"; + u-boot,dm-pre-reloc; spi-flash@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts new file mode 100644 index 00000000000..d7d7f65c85f --- /dev/null +++ b/arch/arm/dts/armada-xp-maxbcm.dts @@ -0,0 +1,249 @@ +/* + * Device Tree file for Marvell Armada XP maxbcm board + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP MAXBCM"; + compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + /* + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). + */ + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, + <0x00000001 0x00000000 0x00000001 0x00000000>; + }; + + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; + + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts new file mode 100644 index 00000000000..0a60ddfa414 --- /dev/null +++ b/arch/arm/dts/armada-xp-synology-ds414.dts @@ -0,0 +1,337 @@ +/* + * Device Tree file for Synology DS414 + * + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Synology DS414"; + compatible = "synology,ds414", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + + /* RTC is provided by Seiko S-35390A below */ + rtc@10300 { + status = "disabled"; + }; + + spi0: spi@10600 { + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB. This + * provides the main console for the device. + * + * Warning: the device may not boot with a 3.3V + * USB-serial converter connected when the power + * button is pressed. The converter needs to be + * connected a few seconds after pressing the + * power button. This is possibly due to UART0_TXD + * pin being sampled at reset (bit 0 of SAR). + */ + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + /* Connected to a Microchip PIC16F883 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin + &sata3_pwr_pin &sata4_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + sata3_regulator: sata3-regulator { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + sata4_regulator: sata4-regulator { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata3_pwr_pin: sata3-pwr-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + sata4_pwr_pin: sata4-pwr-pin { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + fan1_alarm_pin: fan1-alarm-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + fan2_alarm_pin: fan2-alarm-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi index 3de9b761cc1..3fac39e41d7 100644 --- a/arch/arm/dts/armada-xp.dtsi +++ b/arch/arm/dts/armada-xp.dtsi @@ -63,6 +63,7 @@ soc { compatible = "marvell,armadaxp-mbus", "simple-bus"; + u-boot,dm-pre-reloc; bootrom { compatible = "marvell,bootrom"; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index e4daa991e95..797d411d6f7 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -487,7 +487,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index feb3708dc62..e7fecf76564 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -41,6 +41,7 @@ ethernet1 = &cpsw_emac1; d_can0 = &dcan1; d_can1 = &dcan2; + spi0 = &qspi; }; timer { @@ -1113,8 +1114,11 @@ qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>; - reg-names = "qspi_base"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>, + <0x4a002558 0x4>; + reg-names = "qspi_base", "qspi_mmap", + "qspi_ctrlmod"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index efb544c6bb6..a62550f0e02 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -604,7 +604,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/thunderx-88xx.dts b/arch/arm/dts/thunderx-88xx.dts new file mode 100644 index 00000000000..08f267879f9 --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dts @@ -0,0 +1,31 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/dts-v1/; + +/include/ "thunderx-88xx.dtsi" + +/ { + model = "Cavium ThunderX CN88XX board"; + compatible = "cavium,thunder-88xx"; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + }; + + chosen { + stdout-path = &uaa0; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; +}; diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi new file mode 100644 index 00000000000..6e9230b0352 --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dtsi @@ -0,0 +1,363 @@ +/* + * Cavium Thunder DTS file - Thunder SoC description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/ { + compatible = "cavium,thunder-88xx"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + }; + cpu@001 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + }; + cpu@002 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + }; + cpu@003 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + }; + cpu@004 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x004>; + enable-method = "psci"; + }; + cpu@005 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x005>; + enable-method = "psci"; + }; + cpu@006 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x006>; + enable-method = "psci"; + }; + cpu@007 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x007>; + enable-method = "psci"; + }; + cpu@008 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x008>; + enable-method = "psci"; + }; + cpu@009 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x009>; + enable-method = "psci"; + }; + cpu@00a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00a>; + enable-method = "psci"; + }; + cpu@00b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00b>; + enable-method = "psci"; + }; + cpu@00c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00c>; + enable-method = "psci"; + }; + cpu@00d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00d>; + enable-method = "psci"; + }; + cpu@00e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00e>; + enable-method = "psci"; + }; + cpu@00f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00f>; + enable-method = "psci"; + }; + cpu@100 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + cpu@101 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + cpu@102 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + cpu@103 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + cpu@104 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x104>; + enable-method = "psci"; + }; + cpu@105 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x105>; + enable-method = "psci"; + }; + cpu@106 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x106>; + enable-method = "psci"; + }; + cpu@107 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x107>; + enable-method = "psci"; + }; + cpu@108 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x108>; + enable-method = "psci"; + }; + cpu@109 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x109>; + enable-method = "psci"; + }; + cpu@10a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10a>; + enable-method = "psci"; + }; + cpu@10b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10b>; + enable-method = "psci"; + }; + cpu@10c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10c>; + enable-method = "psci"; + }; + cpu@10d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10d>; + enable-method = "psci"; + }; + cpu@10e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10e>; + enable-method = "psci"; + }; + cpu@10f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10f>; + enable-method = "psci"; + }; + cpu@200 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + cpu@201 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + }; + cpu@202 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x202>; + enable-method = "psci"; + }; + cpu@203 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x203>; + enable-method = "psci"; + }; + cpu@204 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x204>; + enable-method = "psci"; + }; + cpu@205 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x205>; + enable-method = "psci"; + }; + cpu@206 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x206>; + enable-method = "psci"; + }; + cpu@207 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x207>; + enable-method = "psci"; + }; + cpu@208 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x208>; + enable-method = "psci"; + }; + cpu@209 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x209>; + enable-method = "psci"; + }; + cpu@20a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20a>; + enable-method = "psci"; + }; + cpu@20b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20b>; + enable-method = "psci"; + }; + cpu@20c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20c>; + enable-method = "psci"; + }; + cpu@20d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20d>; + enable-method = "psci"; + }; + cpu@20e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20e>; + enable-method = "psci"; + }; + cpu@20f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20f>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + + gic0: interrupt-controller@8010,00000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ + <0x8010 0x80000000 0x0 0x600000>; /* GICR */ + interrupts = <1 9 0xf04>; + }; + + uaa0: serial@87e0,24000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + uboot,skip-init; + }; + + uaa1: serial@87e0,25000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + uboot,skip-init; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d76514e4cb7..3b7f6bdb720 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -16,35 +16,21 @@ #define CONFIG_NR_DRAM_BANKS_MAX 2 /* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) -#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ +#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ (CONFIG_SYS_LPC32XX_UART == 7) +#if !defined(CONFIG_LPC32XX_HSUART) #define CONFIG_LPC32XX_HSUART -#else -#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" #endif - -#if defined(CONFIG_SYS_NS16550_SERIAL) - -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_NS16550_COM1 UART3_BASE -#define CONFIG_SYS_NS16550_COM2 UART4_BASE -#define CONFIG_SYS_NS16550_COM3 UART5_BASE -#define CONFIG_SYS_NS16550_COM4 UART6_BASE #endif -#if defined(CONFIG_LPC32XX_HSUART) -#if CONFIG_SYS_LPC32XX_UART == 1 -#define HS_UART_BASE HS_UART1_BASE -#elif CONFIG_SYS_LPC32XX_UART == 2 -#define HS_UART_BASE HS_UART2_BASE -#else /* CONFIG_SYS_LPC32XX_UART == 7 */ -#define HS_UART_BASE HS_UART7_BASE +#if !defined(CONFIG_SYS_NS16550_CLK) +#define CONFIG_SYS_NS16550_CLK 13000000 #endif + +#if !defined(CONFIG_LPC32XX_HSUART) +#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) +#else +#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART #endif #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h index 984c8b9f7f5..48ba622ed19 100644 --- a/arch/arm/include/asm/arch-omap4/ehci.h +++ b/arch/arm/include/asm/arch-omap4/ehci.h @@ -6,17 +6,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com * Author: Govindraj R <govindraj.raja@ti.com> * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _OMAP4_EHCI_H_ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h index 9d447abb969..28f483c4593 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h @@ -2,18 +2,7 @@ * Copyright (C) 2011 Renesas Solutions Corp. * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_R8A7740_H__ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h index 8f179505d06..989da337fec 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7740.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7740.h @@ -1,19 +1,7 @@ /* * Copyright (C) 2012 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_R8A7740_H diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 63b161ab032..0cdefdcdf4a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -134,6 +134,7 @@ #define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 #define SUN6I_CPUCFG_BASE 0x01f01c00 +#define SUNXI_R_TWI_BASE 0x01f02400 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 #define SUN6I_P2WI_BASE 0x01f03400 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index a2a9a38dbe7..649f6cd840f 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -199,6 +199,8 @@ enum sunxi_gpio_number { #define SUN6I_GPL1_R_P2WI_SDA 3 #define SUN8I_GPL_R_RSB 2 +#define SUN8I_H3_GPL_R_TWI 2 +#define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2 #define SUN9I_GPN_R_RSB 3 diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 561cd2be164..4dfd313f1ad 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -23,6 +23,9 @@ #ifdef CONFIG_I2C4_ENABLE #define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE #endif +#ifdef CONFIG_R_I2C_ENABLE +#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE +#endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000 diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 82ed541e91e..556c1af6005 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -236,5 +236,7 @@ struct sunxi_prcm_reg { }; void prcm_apb0_enable(u32 flags); +void prcm_apb0_disable(u32 flags); + #endif /* __ASSEMBLY__ */ #endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h index f101e5ef6ab..d9bcf605c78 100644 --- a/arch/arm/include/asm/arch-tegra/funcmux.h +++ b/arch/arm/include/asm/arch-tegra/funcmux.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index eeeb247d5d5..341df74d777 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -3,23 +3,7 @@ * * Copyright 2010-2011 NVIDIA Corporation * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA_I2C_H_ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index 3f910f5ae8b..d4511817fa3 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 clock PLL tables */ diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h index 9bee3977874..4d58bf18421 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/include/asm/arch-tegra114/clock.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 clock control functions */ diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h index c7eb051c777..2e4045fc72d 100644 --- a/arch/arm/include/asm/arch-tegra114/flow.h +++ b/arch/arm/include/asm/arch-tegra114/flow.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_FLOW_H_ diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h index 7f48f2510f2..9c62cc39d5e 100644 --- a/arch/arm/include/asm/arch-tegra114/funcmux.h +++ b/arch/arm/include/asm/arch-tegra114/funcmux.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index 41ce6778075..21fa4f2d423 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_GP_PADCTRL_H_ diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h index 21853b6eb58..d6eaa1bd40e 100644 --- a/arch/arm/include/asm/arch-tegra114/gpio.h +++ b/arch/arm/include/asm/arch-tegra114/gpio.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_GPIO_H_ diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h index c6e23810118..3104a1b855b 100644 --- a/arch/arm/include/asm/arch-tegra114/pmu.h +++ b/arch/arm/include/asm/arch-tegra114/pmu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_PMU_H_ diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h index c05e2c3281b..38220aac8ee 100644 --- a/arch/arm/include/asm/arch-tegra114/sysctr.h +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_SYSCTR_H_ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index c3d061ec586..f8407d178bc 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_H_ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index 37998a4d606..d97b2c87c63 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA124_MC_H_ diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h index f7c7af80faa..16b4b963305 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 clock PLL tables */ diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h index 410c3528997..46cd7d8e01b 100644 --- a/arch/arm/include/asm/arch-tegra30/clock.h +++ b/arch/arm/include/asm/arch-tegra30/clock.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 clock control functions */ diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h index f5966a8074b..73cb0eecdcd 100644 --- a/arch/arm/include/asm/arch-tegra30/flow.h +++ b/arch/arm/include/asm/arch-tegra30/flow.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_FLOW_H_ diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h index 24b2bca03a0..ae6236273fd 100644 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ b/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h index 23d184f2dd8..1c5017686ce 100644 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_GP_PADCTRL_H_ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h index f1c89f5a869..d2c6c78e08b 100644 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ b/arch/arm/include/asm/arch-tegra30/gpio.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_GPIO_H_ diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h index 52bea29bbc0..f01c37ed673 100644 --- a/arch/arm/include/asm/arch-tegra30/pmu.h +++ b/arch/arm/include/asm/arch-tegra30/pmu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_PMU_H_ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index 93671793a9f..280245e98e8 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_H_ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 2e2a3a8226d..897f010207d 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -21,7 +21,13 @@ * The following definitions are related each other, shoud be * calculated specifically. */ + +#ifndef CONFIG_SYS_FULL_VA #define VA_BITS (42) /* 42 bits virtual address */ +#else +#define VA_BITS CONFIG_SYS_VA_BITS +#define PTL2_BITS CONFIG_SYS_PTL2_BITS +#endif /* PAGE_SHIFT determines the page size */ #undef PAGE_SIZE @@ -30,11 +36,18 @@ #define PAGE_MASK (~(PAGE_SIZE-1)) /* - * section address mask and size definitions. + * block/section address mask and size definitions. */ +#ifndef CONFIG_SYS_FULL_VA #define SECTION_SHIFT 29 #define SECTION_SIZE (UL(1) << SECTION_SHIFT) #define SECTION_MASK (~(SECTION_SIZE-1)) +#else +#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT +#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT) +#define BLOCK_MASK (~(BLOCK_SIZE-1)) +#endif + /***************************************************************/ /* @@ -46,15 +59,54 @@ #define MT_NORMAL_NC 3 #define MT_NORMAL 4 -#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ - (0x04 << (MT_DEVICE_NGNRE*8)) | \ - (0x0c << (MT_DEVICE_GRE*8)) | \ - (0x44 << (MT_NORMAL_NC*8)) | \ - (UL(0xff) << (MT_NORMAL*8))) +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ + (0x04 << (MT_DEVICE_NGNRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8))) /* * Hardware page table definitions. * + */ + +#ifdef CONFIG_SYS_FULL_VA +/* + * Level 1 descriptor (PGD). + */ + +#define PTL1_TYPE_MASK (3 << 0) +#define PTL1_TYPE_TABLE (3 << 0) + +#define PTL1_TABLE_PXN (1UL << 59) +#define PTL1_TABLE_XN (1UL << 60) +#define PTL1_TABLE_AP (1UL << 61) +#define PTL1_TABLE_NS (1UL << 63) + + +/* + * Level 2 descriptor (PMD). + */ + +#define PTL2_TYPE_MASK (3 << 0) +#define PTL2_TYPE_FAULT (0 << 0) +#define PTL2_TYPE_TABLE (3 << 0) +#define PTL2_TYPE_BLOCK (1 << 0) + +/* + * Block + */ +#define PTL2_MEMTYPE(x) ((x) << 2) +#define PTL2_BLOCK_NON_SHARE (0 << 8) +#define PTL2_BLOCK_OUTER_SHARE (2 << 8) +#define PTL2_BLOCK_INNER_SHARE (3 << 8) +#define PTL2_BLOCK_AF (1 << 10) +#define PTL2_BLOCK_NG (1 << 11) +#define PTL2_BLOCK_PXN (UL(1) << 53) +#define PTL2_BLOCK_UXN (UL(1) << 54) + +#else +/* * Level 2 descriptor (PMD). */ #define PMD_TYPE_MASK (3 << 0) @@ -74,6 +126,8 @@ #define PMD_SECT_PXN (UL(1) << 53) #define PMD_SECT_UXN (UL(1) << 54) +#endif + /* * AttrIndx[2:0] */ @@ -100,9 +154,16 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) + +#ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#else +#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS +#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS +#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS +#endif /* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ @@ -116,6 +177,7 @@ #define TCR_EL3_RSVD (1 << 31 | 1 << 23) #ifndef __ASSEMBLY__ +#ifndef CONFIG_SYS_FULL_VA void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, @@ -123,6 +185,7 @@ void set_pgtable_section(u64 *page_table, u64 index, void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr); +#endif static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -143,5 +206,12 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } + +struct mm_region { + u64 base; + u64 size; + u64 attrs; +}; #endif + #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 34c07fe5005..9b79506b594 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -32,7 +32,7 @@ typedef struct { volatile int counter; } atomic_t; static inline void atomic_add(int i, volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter += i; @@ -41,7 +41,7 @@ static inline void atomic_add(int i, volatile atomic_t *v) static inline void atomic_sub(int i, volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter -= i; @@ -50,7 +50,7 @@ static inline void atomic_sub(int i, volatile atomic_t *v) static inline void atomic_inc(volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter += 1; @@ -59,7 +59,7 @@ static inline void atomic_inc(volatile atomic_t *v) static inline void atomic_dec(volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter -= 1; @@ -68,7 +68,7 @@ static inline void atomic_dec(volatile atomic_t *v) static inline int atomic_dec_and_test(volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; int val; local_irq_save(flags); @@ -81,7 +81,7 @@ static inline int atomic_dec_and_test(volatile atomic_t *v) static inline int atomic_add_negative(int i, volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; int val; local_irq_save(flags); @@ -94,7 +94,7 @@ static inline int atomic_add_negative(int i, volatile atomic_t *v) static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); *addr &= ~mask; diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index d479a382918..f33efeb33ee 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -51,7 +51,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) static inline int test_and_set_bit(int nr, volatile void * addr) { - unsigned long flags; + unsigned long flags = 0; int out; local_irq_save(flags); @@ -73,7 +73,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) static inline int test_and_clear_bit(int nr, volatile void * addr) { - unsigned long flags; + unsigned long flags = 0; int out; local_irq_save(flags); diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index c7bca05682a..5a53e403a60 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -6,17 +6,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* * Author: Govindraj R <govindraj.raja@ti.com> * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _OMAP_COMMON_EHCI_H_ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index bd27281e79a..dcfa0985b5b 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -38,6 +38,9 @@ struct arch_global_data { unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; +#if defined(CONFIG_SYS_FULL_VA) + unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES]; +#endif unsigned long tlb_size; #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 71b31085b41..67cbbc26106 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H +#include <common.h> +#include <linux/compiler.h> + #ifdef CONFIG_ARM64 /* @@ -14,7 +17,12 @@ #define CR_WXN (1 << 19) /* Write Permision Imply XN */ #define CR_EE (1 << 25) /* Exception (Big) Endian */ +#ifndef CONFIG_SYS_FULL_VA #define PGTABLE_SIZE (0x10000) +#else +#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE +#endif + /* 2MB granularity */ #define MMU_SECTION_SHIFT 21 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) @@ -72,6 +80,17 @@ static inline void set_sctlr(unsigned int val) asm volatile("isb"); } +static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile("mrs %0, mpidr_el1" : "=r" (val)); + + return val; +} + +#define BSP_COREID 0 + void __asm_flush_dcache_all(void); void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); @@ -89,6 +108,24 @@ void smp_kick_all_cpus(void); void flush_l3_cache(void); +/* + *Issue a hypervisor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void hvc_call(struct pt_regs *args); + +/* + *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void smc_call(struct pt_regs *args); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ @@ -137,7 +174,9 @@ void flush_l3_cache(void); #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */ +#ifndef PGTABLE_SIZE #define PGTABLE_SIZE (4096 * 4) +#endif /* * This is used to ensure the compiler did actually allocate the register we diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 80548ebbf6d..2f4c14e96bf 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -83,8 +83,11 @@ ENTRY(_main) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #endif mov r0, sp - bl board_init_f_mem + bl board_init_f_alloc_reserve mov sp, r0 + /* set up gd here, outside any C code */ + mov r9, r0 + bl board_init_f_init_reserve mov r0, #0 bl board_init_f @@ -133,6 +136,7 @@ here: bl spl_relocate_stack_gd cmp r0, #0 movne sp, r0 + movne r9, r0 # endif ldr r0, =__bss_start /* this is auto-relocated! */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index cef1c7171c6..cad22c7b41f 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -75,8 +75,12 @@ ENTRY(_main) ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - bl board_init_f_mem + mov x0, sp + bl board_init_f_alloc_reserve mov sp, x0 + /* set up gd here, outside any C code */ + mov x18, x0 + bl board_init_f_init_reserve mov x0, #0 bl board_init_f diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index e90d3bba1f9..d2d366ba4f1 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-bcm283x/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S index c7b0843281e..965de1dc7cc 100644 --- a/arch/arm/mach-bcm283x/lowlevel_init.S +++ b/arch/arm/mach-bcm283x/lowlevel_init.S @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ .globl lowlevel_init diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index 8c37ad9fd46..72cdc31d870 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index d0493950363..0c4309ff007 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -135,4 +135,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +/* Use common timer */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK + #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 79ff0e82786..b9628462eab 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,31 +1,74 @@ if ARCH_MVEBU +config ARMADA_38X + bool + +config ARMADA_XP + bool + +config MV78230 + bool + select ARMADA_XP + +config MV78260 + bool + select ARMADA_XP + +config MV78460 + bool + select ARMADA_XP + +config DB_88F6820_GP + bool + select ARMADA_38X + choice prompt "Marvell MVEBU (Armada XP/38x) board select" optional +config TARGET_CLEARFOG + bool "Support ClearFog" + select DB_88F6820_GP + config TARGET_DB_88F6820_GP bool "Support DB-88F6820-GP" + select DB_88F6820_GP config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" + select MV78460 + +config TARGET_DS414 + bool "Support Synology DS414" + select MV78230 config TARGET_MAXBCM bool "Support maxbcm" + select MV78460 endchoice -config SYS_SOC - default "mvebu" +config SYS_BOARD + default "clearfog" if TARGET_CLEARFOG + default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP + default "ds414" if TARGET_DS414 + default "maxbcm" if TARGET_MAXBCM -config MVEBU_BOOTROM_UARTBOOT - bool "Use kwboot to boot via BootROM xmodem protocol" - help - This option provides support for booting via the Marvell - xmodem protocol, used by the kwboot tool. +config SYS_CONFIG_NAME + default "clearfog" if TARGET_CLEARFOG + default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP + default "ds414" if TARGET_DS414 + default "maxbcm" if TARGET_MAXBCM - Please don't forget to configure the boot device in - the board specific kwbimage.cfg file this way: - BOOT_FROM uart +config SYS_VENDOR + default "Marvell" if TARGET_DB_MV784MP_GP + default "Marvell" if TARGET_DB_88F6820_GP + default "solidrun" if TARGET_CLEARFOG + default "Synology" if TARGET_DS414 + +config SYS_SOC + default "mvebu" endif diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 21c56a4d969..b96b81bd393 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -15,8 +15,8 @@ else obj-y = cpu.o obj-y += dram.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o +obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o endif obj-y += gpio.o obj-y += mbus.o @@ -24,7 +24,7 @@ obj-y += timer.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/ -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/ +obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ +obj-$(CONFIG_ARMADA_XP) += serdes/axp/ endif diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 895ad929b10..30b175c6465 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <netdev.h> #include <ahci.h> #include <linux/mbus.h> #include <asm/io.h> @@ -50,25 +49,106 @@ int mvebu_soc_family(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; - if (devid == SOC_MV78460_ID) + switch (devid) { + case SOC_MV78230_ID: + case SOC_MV78260_ID: + case SOC_MV78460_ID: return MVEBU_SOC_AXP; - - if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || - devid == SOC_88F6828_ID) + case SOC_88F6810_ID: + case SOC_88F6820_ID: + case SOC_88F6828_ID: return MVEBU_SOC_A38X; - + } return MVEBU_SOC_UNKNOWN; } #if defined(CONFIG_DISPLAY_CPUINFO) + +#if defined(CONFIG_ARMADA_38X) +/* SAR frequency values for Armada 38x */ +static const struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 666, 333, 333 }, + { 0x2, 0x0, 800, 400, 400 }, + { 0x4, 0x0, 1066, 533, 533 }, + { 0x6, 0x0, 1200, 600, 600 }, + { 0x8, 0x0, 1332, 666, 666 }, + { 0xc, 0x0, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#else +/* SAR frequency values for Armada XP */ +static const struct sar_freq_modes sar_freq_tab[] = { + { 0xa, 0x5, 800, 400, 400 }, + { 0x1, 0x5, 1066, 533, 533 }, + { 0x2, 0x5, 1200, 600, 600 }, + { 0x2, 0x9, 1200, 600, 400 }, + { 0x3, 0x5, 1333, 667, 667 }, + { 0x4, 0x5, 1500, 750, 750 }, + { 0x4, 0x9, 1500, 750, 500 }, + { 0xb, 0x9, 1600, 800, 533 }, + { 0xb, 0xa, 1600, 800, 640 }, + { 0xb, 0x5, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#endif + +void get_sar_freq(struct sar_freq_modes *sar_freq) +{ + u32 val; + u32 freq; + int i; + + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; +#if !defined(CONFIG_ARMADA_38X) + /* + * Shift CPU0 clock frequency select bit from SAR2 register + * into correct position + */ + freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + >> SAR2_CPU_FREQ_OFFS) << 3; +#endif + for (i = 0; sar_freq_tab[i].val != 0xff; i++) { + if (sar_freq_tab[i].val == freq) { +#if defined(CONFIG_ARMADA_38X) + *sar_freq = sar_freq_tab[i]; + return; +#else + int k; + u8 ffc; + + ffc = (val & SAR_FFC_FREQ_MASK) >> + SAR_FFC_FREQ_OFFS; + for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { + if (sar_freq_tab[k].ffc == ffc) { + *sar_freq = sar_freq_tab[k]; + return; + } + } + i = k; +#endif + } + } + + /* SAR value not found, return 0 for frequencies */ + *sar_freq = sar_freq_tab[i - 1]; +} + int print_cpuinfo(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + struct sar_freq_modes sar_freq; puts("SoC: "); switch (devid) { + case SOC_MV78230_ID: + puts("MV78230-"); + break; + case SOC_MV78260_ID: + puts("MV78260-"); + break; case SOC_MV78460_ID: puts("MV78460-"); break; @@ -89,13 +169,13 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_AXP) { switch (revid) { case 1: - puts("A0\n"); + puts("A0"); break; case 2: - puts("B0\n"); + puts("B0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } @@ -103,17 +183,20 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) { switch (revid) { case MV_88F68XX_Z1_ID: - puts("Z1\n"); + puts("Z1"); break; case MV_88F68XX_A0_ID: - puts("A0\n"); + puts("A0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } + get_sar_freq(&sar_freq); + printf(" at %d MHz\n", sar_freq.p_clk); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -199,10 +282,10 @@ static void setup_usb_phys(void) clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); /* Power up PLL and PHY channel */ - clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9)); + setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); /* Assert VCOCAL_START */ - clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21)); + setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); mdelay(1); @@ -211,18 +294,20 @@ static void setup_usb_phys(void) */ for (dev = 0; dev < 3; dev++) { - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15)); + setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); /* Assert REG_RCAL_START in channel REG 1 */ - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12)); + setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); udelay(40); - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0); + clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); } } +/* + * This function is not called from the SPL U-Boot version + */ int arch_cpu_init(void) { -#if !defined(CONFIG_SPL_BUILD) struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -233,27 +318,26 @@ int arch_cpu_init(void) * still locked to cache. */ mmu_disable(); -#endif /* Linux expects the internal registers to be at 0xf1000000 */ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); set_cbar(SOC_REGS_PHY_BASE + 0xC000); -#if !defined(CONFIG_SPL_BUILD) /* * From this stage on, the SoC detection is working. As we have * configured the internal register base to the value used * in the macros / defines in the U-Boot header (soc.h). */ - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -#endif + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + /* + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. + */ + icache_disable(); + dcache_disable(); + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } /* * We need to call mvebu_mbus_probe() before calling @@ -326,30 +410,6 @@ int arch_misc_init(void) } #endif /* CONFIG_ARCH_MISC_INIT */ -#ifdef CONFIG_MVNETA -int cpu_eth_init(bd_t *bis) -{ - u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, - MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; - u8 phy_addr[] = CONFIG_PHY_ADDR; - int i; - - /* - * Only Armada XP supports all 4 ethernet interfaces. A38x has - * slightly different base addresses for its 2-3 interfaces. - */ - if (mvebu_soc_family() != MVEBU_SOC_AXP) { - enet_base[1] = MVEBU_EGIGA2_BASE; - enet_base[2] = MVEBU_EGIGA3_BASE; - } - - for (i = 0; i < ARRAY_SIZE(phy_addr); i++) - mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); - - return 0; -} -#endif - #ifdef CONFIG_MV_SDHCI int board_mmc_init(bd_t *bis) { @@ -413,20 +473,43 @@ void scsi_init(void) } #endif -#ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - /* First disable L2 cache - may still be enable from BootROM */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - /* Avoid problem with e.g. neta ethernet driver */ invalidate_dcache_all(); /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -#endif + +void v7_outer_cache_enable(void) +{ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + u32 u; + + /* The L2 cache is already disabled at this point */ + + /* + * For Aurora cache in no outer mode, enable via the CP15 + * coprocessor broadcasting of cache commands to L2. + */ + asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); + u |= BIT(8); /* Set the FW bit */ + asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); + + isb(); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index ddc5b7ee3ea..a8ec5ea21b6 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -12,11 +12,8 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#ifdef CONFIG_SYS_MVEBU_DDR_A38X -#include "../../../drivers/ddr/marvell/axp/xor.h" -#include "../../../drivers/ddr/marvell/axp/xor_regs.h" -#endif -#ifdef CONFIG_SYS_MVEBU_DDR_AXP +#if defined(CONFIG_ARCH_MVEBU) +/* Use common XOR definitions for A3x and AXP */ #include "../../../drivers/ddr/marvell/axp/xor.h" #include "../../../drivers/ddr/marvell/axp/xor_regs.h" #endif @@ -112,7 +109,7 @@ void mvebu_sdram_size_adjust(enum memory_bank bank) mvebu_sdram_bs_set(bank, size); } -#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP) +#if defined(CONFIG_ARCH_MVEBU) static u32 xor_ctrl_save; static u32 xor_base_save; static u32 xor_mask_save; @@ -292,11 +289,18 @@ void dram_init_banksize(void) } } +#if defined(CONFIG_ARCH_MVEBU) void board_add_ram_info(int use_default) { + struct sar_freq_modes sar_freq; + + get_sar_freq(&sar_freq); + printf(" (%d MHz, ", sar_freq.d_clk); + if (ecc_enabled()) - printf(" (ECC"); + printf("ECC"); else - printf(" (ECC not"); + printf("ECC not"); printf(" enabled)"); } +#endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 1d49cab7fd8..cc1fc5f9d4b 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -17,12 +17,22 @@ #include <asm/arch/soc.h> -#if defined(CONFIG_ARMADA_XP) +#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X) +/* + * Set this for the common xor register definitions needed in dram.c + * for A38x as well here. + */ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#endif + /* * By default kwbimage.cfg from board specific folder is used * If for some board, different configuration file need to be used, @@ -47,8 +57,7 @@ * SPI Flash configuration */ #ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_KIRKWOOD_SPI #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 #endif @@ -60,6 +69,9 @@ #endif #endif +/* Needed for SPI NOR booting in SPL */ +#define CONFIG_DM_SEQ_ALIAS 1 + /* * Ethernet Driver configuration */ @@ -85,9 +97,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif -/* Common SPL configuration */ -#ifndef CONFIG_SPL_LDSCRIPT -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds" -#endif +/* Use common timer */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CONFIG_SYS_TIMER_RATE 25000000 #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 5e8bf0c4ce0..47f45c1512a 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -106,6 +106,14 @@ struct kwgpio_registers { u32 irq_level; }; +struct sar_freq_modes { + u8 val; + u8 ffc; /* Fabric Frequency Configuration */ + u32 p_clk; + u32 nb_clk; + u32 d_clk; +}; + /* Needed for dynamic (board-specific) mbus configuration */ extern struct mvebu_mbus_state mbus_state; @@ -123,6 +131,8 @@ void return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); +void get_sar_freq(struct sar_freq_modes *sar_freq); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 22abde080e1..cb216bc2cc6 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -11,6 +11,8 @@ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H +#define SOC_MV78230_ID 0x7823 +#define SOC_MV78260_ID 0x7826 #define SOC_MV78460_ID 0x7846 #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 @@ -33,10 +35,11 @@ #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) #if defined(CONFIG_SPL_BUILD) /* - * On A38x switching the regs base address without running from - * SDRAM doesn't seem to work. So let the SPL still use the - * default base address and switch to the new address in the - * main u-boot later. + * The SPL U-Boot version still runs with the default + * address for the internal registers, configured by + * the BootROM. Only the main U-Boot version uses the + * new internal register base address, that also is + * required for the Linux kernel. */ #define SOC_REGS_PHY_BASE 0xd0000000 #else @@ -47,10 +50,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE -#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) -#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) -#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) @@ -60,13 +60,9 @@ #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) -#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) -#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) -#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) -#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) @@ -101,4 +97,49 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) + +/* BootROM error register (also includes some status infos) */ +#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) +#define BOOTROM_ERR_MODE_OFFS 28 +#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) +#define BOOTROM_ERR_MODE_UART 0x6 + +#if defined(CONFIG_ARMADA_38X) +/* SAR values for Armada 38x */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) + +#define SAR_CPU_FREQ_OFFS 10 +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 4 +#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 4 +#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x28 +#define BOOT_FROM_SPI 0x32 +#define BOOT_FROM_MMC 0x30 +#define BOOT_FROM_MMC_ALT 0x31 +#else +/* SAR values for Armada XP */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) + +#define SAR_CPU_FREQ_OFFS 21 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_FFC_FREQ_OFFS 24 +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) +#define SAR2_CPU_FREQ_OFFS 20 +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 5 +#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 5 +#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 +#endif + #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S index 2e2181ecea5..49e0b906d58 100644 --- a/arch/arm/mach-mvebu/lowlevel_spl.S +++ b/arch/arm/mach-mvebu/lowlevel_spl.S @@ -5,7 +5,6 @@ #include <config.h> #include <linux/linkage.h> -#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT ENTRY(save_boot_params) stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */ ldr r12, =CONFIG_SPL_BOOTROM_SAVE @@ -19,11 +18,6 @@ ENTRY(return_to_bootrom) mov r0, #0x0 /* @ return value: 0x0 NO_ERR */ ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */ ENDPROC(return_to_bootrom) -#else -ENTRY(save_boot_params) - b save_boot_params_ret -ENDPROC(save_boot_params) -#endif /* * cache_inv - invalidate Cache line diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 346278e1bee..df263bc3b39 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -491,7 +491,7 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count) #if defined(CONFIG_KIRKWOOD) mbus_state.soc = &kirkwood_mbus_data; #endif -#if defined(CONFIG_ARMADA_XP) +#if defined(CONFIG_ARCH_MVEBU) mbus_state.soc = &armada_370_xp_mbus_data; #endif diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h index 36e0ed80f0d..c8d9485b7bb 100644 --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h @@ -32,7 +32,7 @@ #define BOARD_ID_BASE 0x0 /* New board ID numbers */ -#define DB_88F78XX0_BP_ID (BOARD_ID_BASE) +#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1) #define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1) #define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1) #define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1) @@ -44,7 +44,7 @@ #define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) #define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1) #define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) -#define INVALID_BAORD_ID 0xFFFFFFFF +#define INVALID_BOARD_ID 0xFFFFFFFF /* Sample at Reset */ #define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 702273aee12..afc0cefda3c 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -75,16 +75,24 @@ static u32 board_id_get(void) #endif } -static u8 board_sat_r_get(u8 dev_num, u8 reg) +__weak u8 board_sat_r_get(u8 dev_num, u8 reg) { u8 data; u8 *dev; u32 board_id = board_id_get(); int ret; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - switch (board_id) { + case DB_78X60_AMC_ID: + case DB_78X60_PCAC_REV2_ID: + case RD_78460_CUSTOMER_ID: + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: + case DB_78X60_PCAC_ID: + return (0x1 << 1) | 1; + case FPGA_88F78XX0_ID: + case RD_78460_NAS_ID: + return (0x0 << 1) | 1; case DB_784MP_GP_ID: dev = rd78460gp_twsi_dev; @@ -94,15 +102,12 @@ static u8 board_sat_r_get(u8 dev_num, u8 reg) dev = db88f78xx0rev2_twsi_dev; break; - case DB_78X60_PCAC_ID: - case FPGA_88F78XX0_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_SERVER_REV2_ID: default: return 0; } /* Read MPP module ID */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1); if (ret) return MV_ERROR; @@ -190,8 +195,17 @@ __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) u16 ctrl_model_get(void) { - /* Right now only MV78460 supported */ + /* + * SoC version can't be autodetected. So we need to rely on a define + * from the config system here. + */ +#if defined(CONFIG_MV78230) + return MV_78230_DEV_ID; +#elif defined(CONFIG_MV78260) + return MV_78260_DEV_ID; +#else return MV_78460_DEV_ID; +#endif } u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) @@ -202,6 +216,20 @@ u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; } +static int serdes_max_lines_get(void) +{ + switch (ctrl_model_get()) { + case MV_78230_DEV_ID: + return 7; + case MV_78260_DEV_ID: + return 12; + case MV_78460_DEV_ID: + return 16; + } + + return 0; +} + int serdes_phy_config(void) { int status = MV_OK; @@ -221,39 +249,19 @@ int serdes_phy_config(void) u8 device_rev; u32 rx_high_imp_mode; u16 ctrl_mode; - u32 board_id = board_id_get(); u32 pex_if; u32 pex_if_num; /* - * TODO: - * Right now we only support the MV78460 with 16 serdes lines + * Get max. serdes lines count */ - max_serdes_lines = 16; + max_serdes_lines = serdes_max_lines_get(); if (max_serdes_lines == 0) return MV_OK; - switch (board_id) { - case DB_78X60_AMC_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_CUSTOMER_ID: - case RD_78460_SERVER_ID: - case RD_78460_SERVER_REV2_ID: - case DB_78X60_PCAC_ID: - satr11 = (0x1 << 1) | 1; - break; - case FPGA_88F78XX0_ID: - case RD_78460_NAS_ID: - satr11 = (0x0 << 1) | 1; - break; - case DB_88F78XX0_BP_REV2_ID: - case DB_784MP_GP_ID: - case DB_88F78XX0_BP_ID: - satr11 = board_sat_r_get(1, 1); - if ((u8) MV_ERROR == (u8) satr11) - return MV_ERROR; - break; - } + satr11 = board_sat_r_get(1, 1); + if ((u8) MV_ERROR == (u8) satr11) + return MV_ERROR; board_modules_scan(); memset(addr, 0, sizeof(addr)); @@ -1356,19 +1364,19 @@ int serdes_phy_config(void) pex_if, PEX_DEVICE_AND_VENDOR_ID)); devId &= 0xFFFF; devId |= ((ctrl_mode << 16) & 0xffff0000); - DEBUG_INIT_S("Update Device ID PEX"); - DEBUG_INIT_D(pex_if, 1); - DEBUG_INIT_D(devId, 8); - DEBUG_INIT_S("\n"); + DEBUG_INIT_FULL_S("Update Device ID PEX"); + DEBUG_INIT_FULL_D(pex_if, 1); + DEBUG_INIT_FULL_D(devId, 8); + DEBUG_INIT_FULL_S("\n"); reg_write(PEX_CFG_DIRECT_ACCESS (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId); if ((pex_if < 8) && (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)) pex_if += 3; } - DEBUG_INIT_S("Update PEX Device ID 0x"); - DEBUG_INIT_D(ctrl_mode, 4); - DEBUG_INIT_S("0\n"); + DEBUG_INIT_FULL_S("Update PEX Device ID 0x"); + DEBUG_INIT_FULL_D(ctrl_mode, 4); + DEBUG_INIT_FULL_S("0\n"); } tmp = reg_read(PEX_DBG_STATUS_REG(0)); DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp); diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 0ab729aa5d8..0879873b972 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -1,10 +1,13 @@ /* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <debug_uart.h> +#include <fdtdec.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -12,14 +15,45 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) +static u32 get_boot_device(void) { -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) - return BOOT_DEVICE_SPI; -#endif -#if defined(CONFIG_SPL_MMC_SUPPORT) - return BOOT_DEVICE_MMC1; + u32 val; + u32 boot_device; + + /* + * First check, if UART boot-mode is active. This can only + * be done, via the bootrom error register. Here the + * MSB marks if the UART mode is active. + */ + val = readl(CONFIG_BOOTROM_ERR_REG); + boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; + debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); + if (boot_device == BOOTROM_ERR_MODE_UART) + return BOOT_DEVICE_UART; + + /* + * Now check the SAR register for the strapped boot-device + */ + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; + debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); + switch (boot_device) { +#ifdef CONFIG_SPL_MMC_SUPPORT + case BOOT_FROM_MMC: + case BOOT_FROM_MMC_ALT: + return BOOT_DEVICE_MMC1; #endif + case BOOT_FROM_UART: + return BOOT_DEVICE_UART; + case BOOT_FROM_SPI: + default: + return BOOT_DEVICE_SPI; + }; +} + +u32 spl_boot_device(void) +{ + return get_boot_device(); } #ifdef CONFIG_SPL_MMC_SUPPORT @@ -31,18 +65,7 @@ u32 spl_boot_mode(void) void board_init_f(ulong dummy) { -#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT - /* - * Only call arch_cpu_init() when not returning to the - * Marvell BootROM, which is done when booting via - * the xmodem protocol (kwboot tool). Otherwise the - * internal register will get remapped and the BootROM - * can't continue to run correctly. - */ - - /* Linux expects the internal registers to be at 0xf1000000 */ - arch_cpu_init(); -#endif + int ret; /* * Pin muxing needs to be done before UART output, since @@ -51,6 +74,27 @@ void board_init_f(ulong dummy) */ board_early_init_f(); + /* Example code showing how to enable the debug UART on MVEBU */ +#ifdef EARLY_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ +#endif + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + /* Use special translation offset for SPL */ + dm_set_translation_offset(0xd0000000 - 0xf1000000); + preloader_console_init(); timer_init(); @@ -61,7 +105,6 @@ void board_init_f(ulong dummy) /* Setup DDR */ ddr3_init(); -#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool. @@ -73,6 +116,6 @@ void board_init_f(ulong dummy) * need to return to the BootROM to enable this xmodem * UART download. */ - return_to_bootrom(); -#endif + if (get_boot_device() == BOOT_DEVICE_UART) + return_to_bootrom(); } diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index 5449a8926c5..f5c2eaa808a 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -2,6 +2,8 @@ * Copyright (C) Marvell International Ltd. and its affiliates * Written-by: Prafulla Wadaskar <prafulla@marvell.com> * + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,108 +11,14 @@ #include <asm/io.h> #include <asm/arch/soc.h> -#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */ - -/* - * ARM Timers Registers Map - */ -#define CNTMR_CTRL_REG &tmr_regs->ctrl -#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload -#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val - -/* - * ARM Timers Control Register - * CPU_TIMERS_CTRL_REG (CTCR) - */ -#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) - -#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) - -/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */ -#if defined(CONFIG_ARMADA_XP) -#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11) -#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr)) -#else -#define CTCR_ARM_TIMER_25MHZ(cntr) 0 -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static int init_done __attribute__((section(".data"))) = 0; - -/* Timer reload and current value registers */ -struct kwtmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct kwtmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct kwtmr_val tmr[4]; - u32 wdt_reload; - u32 wdt_val; -}; - DECLARE_GLOBAL_DATA_PTR; -static struct kwtmr_registers *tmr_regs = - (struct kwtmr_registers *)MVEBU_TIMER_BASE; - -static inline ulong read_timer(void) -{ - return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000); -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; - } - lastdec = now; +#define TIMER_LOAD_VAL 0xffffffff - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - uint current; - ulong delayticks; - - current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); - - if (current < delayticks) { - delayticks -= current; - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; - while ((TIMER_LOAD_VAL - delayticks) < - readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; - } else { - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > - (current - delayticks)) ; - } -} +static int init_done __attribute__((section(".data"))) = 0; /* - * init the counter + * Timer initialization */ int timer_init(void) { @@ -120,35 +28,15 @@ int timer_init(void) init_done = 1; /* load value into timer */ - writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); - writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10); + writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14); +#if defined(CONFIG_ARCH_MVEBU) + /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */ + setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11)); +#endif /* enable timer in auto reload mode */ - clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR), - CTCR_ARM_TIMER_EN(UBOOT_CNTR) | - CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR)); - - /* init the timestamp and lastdec value */ - lastdec = read_timer(); - timestamp = 0; + setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3); return 0; } - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/mach-mvebu/u-boot-spl.lds b/arch/arm/mach-mvebu/u-boot-spl.lds deleted file mode 100644 index eee1db49eed..00000000000 --- a/arch/arm/mach-mvebu/u-boot-spl.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - *(.vectors) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*_i2c_*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh index c1640bc32a9..1adfbf7384c 100755 --- a/arch/arm/mach-socfpga/qts-filter.sh +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -3,13 +3,15 @@ # # Process iocsr_config_*.[ch] # $1: SoC type -# $2: Input directory -# $3: Output directory +# $2: Input handoff directory +# $3: Input BSP Generated directory +# $4: Output directory # process_iocsr_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -26,13 +28,13 @@ EOF # Retrieve the scan chain lengths grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \ - ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()" + ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()" echo "" # Retrieve the scan chain config and zap the ad-hoc length encoding sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \ - ${in_dir}/generated/iocsr_config_${soc}.c + ${in_bsp_dir}/generated/iocsr_config_${soc}.c cat << EOF @@ -49,8 +51,9 @@ EOF # process_pinmux_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -67,7 +70,7 @@ EOF # Retrieve the pinmux config and zap the ad-hoc length encoding sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \ - ${in_dir}/generated/pinmux_config_${soc}.c + ${in_bsp_dir}/generated/pinmux_config_${soc}.c cat << EOF @@ -84,8 +87,9 @@ EOF # process_pll_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -102,7 +106,7 @@ EOF # Retrieve the pll config and zap parenthesis sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \ - ${in_dir}/generated/pll_config.h + ${in_bsp_dir}/generated/pll_config.h cat << EOF @@ -126,8 +130,9 @@ grep_sdram_config() { # process_sdram_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -144,29 +149,32 @@ EOF echo "/* SDRAM configuration */" # Retrieve the sdram config, zap broken lines and zap parenthesis - sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h | + sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \ + ${in_bsp_dir}/generated/sdram/sdram_config.h | sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' | sort -u | grep_sdram_config echo "" echo "/* Sequencer auto configuration */" sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ - ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h | + sort -u | grep_sdram_config echo "" echo "/* Sequencer defines configuration */" sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ - ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config + ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h | + sort -u | grep_sdram_config echo "" echo "/* Sequencer ac_rom_init configuration */" sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ - ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c echo "" echo "/* Sequencer inst_rom_init configuration */" sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ - ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c cat << EOF @@ -176,30 +184,36 @@ EOF } usage() { - echo "$0 [soc_type] [input_dir] [output_dir]" + echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]" echo "Process QTS-generated headers into U-Boot compatible ones." echo "" - echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5'," - echo " input_dir\t\tDirectory with the QTS project." - echo " output_dir\t\tDirectory to store the U-Boot compatible headers." + echo -e " soc_type\t-\tType of SoC, either 'cyclone5' or 'arria5'." + echo -e " input_qts_dir\t-\tDirectory with compiled Quartus project" + echo -e "\t\t\t\tand containing the Quartus project file (QPF)." + echo -e " input_bsp_dir\t-\tDirectory with generated bsp containing" + echo -e "\t\t\t\tthe settings.bsp file." + echo -e " output_dir\t-\tDirectory to store the U-Boot compatible" + echo -e "\t\t\t\theaders." echo "" } soc="$1" -in_dir="$2" -out_dir="$3" +in_qts_dir="$2" +in_bsp_dir="$3" +out_dir="$4" -if [ "$#" -ne 3 ] ; then +if [ "$#" -ne 4 ] ; then usage exit 1 fi -if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then +if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \ + ! -d "${out_dir}" -o -z "${soc}" ] ; then usage exit 3 fi -process_iocsr_config "${soc}" "${in_dir}" "${out_dir}" -process_pinmux_config "${soc}" "${in_dir}" "${out_dir}" -process_pll_config "${soc}" "${in_dir}" "${out_dir}" -process_sdram_config "${soc}" "${in_dir}" "${out_dir}" +process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" +process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" +process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" +process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig new file mode 100644 index 00000000000..7dbeb040d53 --- /dev/null +++ b/arch/arm/mach-stm32/Kconfig @@ -0,0 +1,12 @@ +if STM32 + +config STM32F4 + bool "stm32f4 family" + +config STM32F1 + bool "stm32f1 family" + +source "arch/arm/mach-stm32/stm32f4/Kconfig" +source "arch/arm/mach-stm32/stm32f1/Kconfig" + +endif diff --git a/arch/mips/mach-au1x00/config.mk b/arch/arm/mach-stm32/Makefile index 5c89129d8cf..ea06034e103 100644 --- a/arch/mips/mach-au1x00/config.mk +++ b/arch/arm/mach-stm32/Makefile @@ -1,8 +1,9 @@ # -# (C) Copyright 2011 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -mtune=4kc +obj-$(CONFIG_STM32F1) += stm32f1/ +obj-$(CONFIG_STM32F4) += stm32f4/ diff --git a/arch/arm/mach-stm32/stm32f1/Kconfig b/arch/arm/mach-stm32/stm32f1/Kconfig new file mode 100644 index 00000000000..f627fd25416 --- /dev/null +++ b/arch/arm/mach-stm32/stm32f1/Kconfig @@ -0,0 +1,3 @@ +if STM32F1 + +endif diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile b/arch/arm/mach-stm32/stm32f1/Makefile index e2081dbf9ed..e2081dbf9ed 100644 --- a/arch/arm/cpu/armv7m/stm32f1/Makefile +++ b/arch/arm/mach-stm32/stm32f1/Makefile diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c b/arch/arm/mach-stm32/stm32f1/clock.c index 28208485d4b..28208485d4b 100644 --- a/arch/arm/cpu/armv7m/stm32f1/clock.c +++ b/arch/arm/mach-stm32/stm32f1/clock.c diff --git a/arch/arm/cpu/armv7m/stm32f1/flash.c b/arch/arm/mach-stm32/stm32f1/flash.c index 7d41f63733d..7d41f63733d 100644 --- a/arch/arm/cpu/armv7m/stm32f1/flash.c +++ b/arch/arm/mach-stm32/stm32f1/flash.c diff --git a/arch/arm/cpu/armv7m/stm32f1/soc.c b/arch/arm/mach-stm32/stm32f1/soc.c index 4438621b9ab..4438621b9ab 100644 --- a/arch/arm/cpu/armv7m/stm32f1/soc.c +++ b/arch/arm/mach-stm32/stm32f1/soc.c diff --git a/arch/arm/cpu/armv7m/stm32f1/timer.c b/arch/arm/mach-stm32/stm32f1/timer.c index 6a261986e97..6a261986e97 100644 --- a/arch/arm/cpu/armv7m/stm32f1/timer.c +++ b/arch/arm/mach-stm32/stm32f1/timer.c diff --git a/arch/arm/mach-stm32/stm32f4/Kconfig b/arch/arm/mach-stm32/stm32f4/Kconfig new file mode 100644 index 00000000000..a63619e07fd --- /dev/null +++ b/arch/arm/mach-stm32/stm32f4/Kconfig @@ -0,0 +1,8 @@ +if STM32F4 + +config TARGET_STM32F429_DISCOVERY + bool "STM32F429 Discovery board" + +source "board/st/stm32f429-discovery/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile index 42d01db14d6..42d01db14d6 100644 --- a/arch/arm/cpu/armv7m/stm32f4/Makefile +++ b/arch/arm/mach-stm32/stm32f4/Makefile diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 3deb17aa833..3deb17aa833 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/mach-stm32/stm32f4/flash.c index a379f477df5..a379f477df5 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/mach-stm32/stm32f4/flash.c diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c index b5d06dbe833..b5d06dbe833 100644 --- a/arch/arm/cpu/armv7m/stm32f4/soc.c +++ b/arch/arm/mach-stm32/stm32f4/soc.c diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c index 1dee190766b..1dee190766b 100644 --- a/arch/arm/cpu/armv7m/stm32f4/timer.c +++ b/arch/arm/mach-stm32/stm32f4/timer.c diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 0e9cb97832d..6dad40325d2 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra cache routines */ diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f75c6c664a2..c50d56dc888 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra SoC common clock control functions */ diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index ba04a56be76..a3ebb57f20b 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index c7d705d8efe..0dbddd45d41 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra vpr routines */ diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c index 52441c71e65..ca9d970abc8 100644 --- a/arch/arm/mach-tegra/tegra114/funcmux.c +++ b/arch/arm/mach-tegra/tegra114/funcmux.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 high-level function multiplexing */ diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index 67f49d77561..7fbc2e28655 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index c76e74c65f6..66b021b8245 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c index 409335ce1d1..8c683390437 100644 --- a/arch/arm/mach-tegra/tegra30/funcmux.c +++ b/arch/arm/mach-tegra/tegra30/funcmux.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 high-level function multiplexing */ diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index b4ca8b69341..43981146585 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -11,6 +11,12 @@ #include "ssc-regs.h" #ifdef CONFIG_UNIPHIER_L2CACHE_ON +static void uniphier_cache_sync(void) +{ + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + static void uniphier_cache_maint_all(u32 operation) { /* try until the command is successfully set */ @@ -25,8 +31,7 @@ static void uniphier_cache_maint_all(u32 operation) /* clear the complete notification flag */ writel(SSCOLPQS_EF, SSCOLPQS); - writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ - readl(SSCOPE); /* need a read back to confirm */ + uniphier_cache_sync(); } void v7_outer_cache_flush_all(void) @@ -67,7 +72,9 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) */ start = start & ~(SSC_LINE_SIZE - 1); - if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) { + size = end - start; + + if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) { /* this means cache operation for all range */ uniphier_cache_maint_all(operation); return; @@ -77,7 +84,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) * If end address is not aligned to cache-line, * do cache operation for the last cache-line */ - size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1); + size = ALIGN(size, SSC_LINE_SIZE); while (size) { u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? @@ -88,8 +95,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) size -= chunk_size; } - writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ - readl(SSCOPE); /* need a read back to confirm */ + uniphier_cache_sync(); } void v7_outer_cache_flush_range(u32 start, u32 end) @@ -99,12 +105,37 @@ void v7_outer_cache_flush_range(u32 start, u32 end) void v7_outer_cache_inval_range(u32 start, u32 end) { + if (start & (SSC_LINE_SIZE - 1)) { + start &= ~(SSC_LINE_SIZE - 1); + __uniphier_cache_maint_range(start, SSC_LINE_SIZE, + SSCOQM_CM_WB_INV); + start += SSC_LINE_SIZE; + } + + if (start >= end) { + uniphier_cache_sync(); + return; + } + + if (end & (SSC_LINE_SIZE - 1)) { + end &= ~(SSC_LINE_SIZE - 1); + __uniphier_cache_maint_range(end, SSC_LINE_SIZE, + SSCOQM_CM_WB_INV); + } + + if (start >= end) { + uniphier_cache_sync(); + return; + } + uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); } void v7_outer_cache_enable(void) { u32 tmp; + + writel(U32_MAX, SSCLPDAWCR); /* activate all ways */ tmp = readl(SSCC); tmp |= SSCC_ON; writel(tmp, SSCC); diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index 2c8cbc25798..9fb34f79a78 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -40,18 +40,12 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) writel(0x0000040B, &phy->dcr); if (freq == 1333) { writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x1a8363c0, &phy->dtpr[1]); writel(0x5002c200, &phy->dtpr[2]); writel(0x00000b51, &phy->mr0); } else { writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); + writel(0x1a878400, &phy->dtpr[1]); writel(0xa00214f8, &phy->dtpr[2]); writel(0x00000d71, &phy->mr0); } diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 63a84e68c0b..bb7acdee1eb 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -16,54 +16,7 @@ #include "../init.h" #include "../soc-info.h" #include "ddrmphy-regs.h" - -/* UM registers */ -#define UMC_MBUS0 0x00080004 -#define UMC_MBUS1 0x00081004 -#define UMC_MBUS2 0x00082004 -#define UMC_MBUS3 0x00083004 - -/* UD registers */ -#define UMC_BITPERPIXELMODE_D0 0x010 -#define UMC_PAIR1DOFF_D0 0x054 - -/* DC registers */ -#define UMC_INITSET 0x014 -#define UMC_INITSTAT 0x018 -#define UMC_CMDCTLA 0x000 -#define UMC_CMDCTLB 0x004 -#define UMC_SPCCTLA 0x030 -#define UMC_SPCCTLB 0x034 -#define UMC_SPCSETB 0x03c -#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ -#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ -#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ -#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ -#define UMC_ACSSETA 0x060 -#define UMC_FLOWCTLA 0x400 -#define UMC_FLOWCTLB 0x404 -#define UMC_FLOWCTLC 0x408 -#define UMC_FLOWCTLG 0x508 -#define UMC_FLOWCTLOB0 0x520 -#define UMC_FLOWCTLOB1 0x524 -#define UMC_RDATACTL_D0 0x600 -#define UMC_RDATACTL_RADLTY_SHIFT 4 -#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) -#define UMC_RDATACTL_RAD2LTY_SHIFT 8 -#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) -#define UMC_WDATACTL_D0 0x604 -#define UMC_RDATACTL_D1 0x608 -#define UMC_WDATACTL_D1 0x60c -#define UMC_DATASET 0x610 -#define UMC_RESPCTL 0x624 -#define UMC_DCCGCTL 0x720 -#define UMC_ERRMASKA 0x958 -#define UMC_ERRMASKB 0x95c -#define UMC_BSICMAPSET 0x988 -#define UMC_DIOCTLA 0xc00 -#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ -#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ -#define UMC_DFICUPDCTLA 0xc20 +#include "umc-regs.h" enum dram_freq { FREQ_1866M, diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index 6159281fd37..a6957a4a51c 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -69,6 +69,10 @@ #define UMC_SPCCTLB 0x00000034 #define UMC_SPCSETA 0x00000038 #define UMC_SPCSETB 0x0000003C +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ #define UMC_SPCSETC 0x00000040 #define UMC_SPCSETD 0x00000044 #define UMC_SPCSTATA 0x00000050 @@ -79,17 +83,39 @@ #define UMC_FLOWCTLB 0x00000404 #define UMC_FLOWCTLC 0x00000408 #define UMC_FLOWCTLG 0x00000508 +#define UMC_FLOWCTLOB0 0x00000520 +#define UMC_FLOWCTLOB1 0x00000524 #define UMC_RDATACTL_D0 0x00000600 +#define UMC_RDATACTL_RADLTY_SHIFT 4 +#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) +#define UMC_RDATACTL_RAD2LTY_SHIFT 8 +#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) #define UMC_WDATACTL_D0 0x00000604 #define UMC_RDATACTL_D1 0x00000608 #define UMC_WDATACTL_D1 0x0000060C #define UMC_DATASET 0x00000610 +#define UMC_RESPCTL 0x00000624 #define UMC_DCCGCTL 0x00000720 #define UMC_DICGCTLA 0x00000724 #define UMC_DICGCTLB 0x00000728 +#define UMC_ERRMASKA 0x00000958 +#define UMC_ERRMASKB 0x0000095c +#define UMC_BSICMAPSET 0x00000988 #define UMC_DIOCTLA 0x00000C00 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ #define UMC_DFICUPDCTLA 0x00000C20 +/* UM registers */ +#define UMC_MBUS0 0x00080004 +#define UMC_MBUS1 0x00081004 +#define UMC_MBUS2 0x00082004 +#define UMC_MBUS3 0x00083004 + +/* UD registers */ +#define UMC_BITPERPIXELMODE_D0 0x010 +#define UMC_PAIR1DOFF_D0 0x054 + #ifndef __ASSEMBLY__ #include <linux/types.h> diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile deleted file mode 100644 index de243feaab5..00000000000 --- a/arch/arm/mvebu-common/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = dram.o -obj-y += gpio.o -obj-$(CONFIG_ARMADA_XP) += mbus.o -obj-y += timer.o - -obj-y += serdes/ diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 979eb5a765a..ae261b11329 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -34,7 +34,7 @@ #if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE) +#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) #endif @@ -490,7 +490,7 @@ asm_dspi_rd_status: /* copy 4 boot pages to dram as soon as possible */ /* each page is 996 bytes (1056 total with 60 ECC bytes */ move.l #0x00000000, %a1 /* src */ - move.l #TEXT_BASE, %a2 /* dst */ + move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */ move.l #0x3E0, %d0 /* sz in long */ asm_boot_nand_copy: @@ -571,7 +571,7 @@ asm_nand_init: move.l #4, %d2 /* start at 4 */ move.l #0xFC0FFF04, %a0 /* cmd2 */ move.l #0xFC0FFF0C, %a1 /* rar */ - move.l #(TEXT_BASE + 0xF80), %a2 /* dst */ + move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2 /* dst */ asm_nand_read: move.l #0x11000000, %d0 /* rar */ @@ -609,7 +609,7 @@ asm_nand_copy: bgt asm_nand_read /* jump to memory and execute */ - move.l #(TEXT_BASE + 0x400), %a0 + move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0 jmp (%a0) #endif /* CONFIG_SYS_NAND_BOOT */ diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h index 2bc9bf434e1..1b1c25ef899 100644 --- a/arch/m68k/include/asm/fsl_i2c.h +++ b/arch/m68k/include/asm/fsl_i2c.h @@ -8,23 +8,7 @@ * and Jeff Brown. * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FSL_I2C_H_ diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 14f46a8f046..206be3e3ee5 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -25,7 +25,7 @@ _start: addi r8, r0, __end mts rslr, r8 - /* TODO: Redo this code to call board_init_f_mem() */ + /* TODO: Redo this code to call board_init_f_*() */ #if defined(CONFIG_SPL_BUILD) addi r1, r0, CONFIG_SPL_STACK_ADDR mts rshr, r1 @@ -142,7 +142,7 @@ _start: ori r12, r12, 0x1a0 mts rmsr, r12 - /* TODO: Redo this code to call board_init_f_mem() */ + /* TODO: Redo this code to call board_init_f_*() */ clear_bss: /* clear BSS segments */ addi r5, r0, __bss_start diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7f7e258a801..1b39c4c0c65 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -28,6 +28,7 @@ config TARGET_MALTA select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SWAP_IO_SPACE + select MIPS_L1_CACHE_SHIFT_6 config TARGET_VCT bool "Support vct" @@ -43,6 +44,7 @@ config TARGET_DBAU1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select MIPS_TUNE_4KC config TARGET_PB1X00 bool "Support pb1x00" @@ -50,7 +52,7 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD - + select MIPS_TUNE_4KC endchoice @@ -174,6 +176,15 @@ config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 +config MIPS_TUNE_4KC + bool + +config MIPS_TUNE_14KC + bool + +config MIPS_TUNE_24KC + bool + config 32BIT bool @@ -186,6 +197,26 @@ config SWAP_IO_SPACE config SYS_MIPS_CACHE_INIT_RAM_LOAD bool +config MIPS_L1_CACHE_SHIFT_4 + bool + +config MIPS_L1_CACHE_SHIFT_5 + bool + +config MIPS_L1_CACHE_SHIFT_6 + bool + +config MIPS_L1_CACHE_SHIFT_7 + bool + +config MIPS_L1_CACHE_SHIFT + int + default "7" if MIPS_L1_CACHE_SHIFT_7 + default "6" if MIPS_L1_CACHE_SHIFT_6 + default "5" if MIPS_L1_CACHE_SHIFT_5 + default "4" if MIPS_L1_CACHE_SHIFT_4 + default "5" + endif endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 43f0f5c5046..2133e7e065d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -7,4 +7,25 @@ head-y := arch/mips/cpu/start.o libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ -libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ +machine-$(CONFIG_SOC_AU1X00) += au1x00 + +machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) +libs-y += $(machdirs) + +PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) + +# Optimize for MIPS architectures +arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 +arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 +arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 +arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 + +# Allow extra optimization for specific CPUs/SoCs +tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc +tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc +tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc + +# Include default header files +cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic + +PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 52e28f2ca5c..609a998f3b6 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -35,12 +35,6 @@ PLATFORM_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) endif -cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 -cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 -cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 -cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 -PLATFORM_CPPFLAGS += $(cpuflags-y) - PLATFORM_CPPFLAGS += -D__MIPS__ # @@ -63,10 +57,21 @@ PLATFORM_CPPFLAGS += -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic +ifdef CONFIG_SPL_BUILD +PF_ABICALLS := -mno-abicalls +PF_PIC := -fno-pic +PF_PIE := +else +PF_ABICALLS := -mabicalls +PF_PIC := -fpic +PF_PIE := -pie +PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding +PF_OBJCOPY += -j .dtb.init.rodata +endif + +PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC) PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -LDFLAGS_FINAL += --gc-sections -pie -OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got -OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding +LDFLAGS_FINAL += --gc-sections $(PF_PIE) +OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 3b5b622abed..e95cdca61eb 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -56,9 +56,7 @@ .set noreorder - .globl _start - .text -_start: +ENTRY(_start) /* U-boot entry point */ b reset nop @@ -192,6 +190,8 @@ reset: jr t9 move ra, zero + END(_start) + /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -202,9 +202,7 @@ reset: * a1 = gd * a2 = destination address */ - .globl relocate_code - .ent relocate_code -relocate_code: +ENTRY(relocate_code) move sp, a0 # set new stack pointer move fp, sp @@ -317,4 +315,4 @@ in_ram: jr t9 move ra, zero - .end relocate_code + END(relocate_code) diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore new file mode 100644 index 00000000000..b60ed208c77 --- /dev/null +++ b/arch/mips/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile new file mode 100644 index 00000000000..47b6eb50c35 --- /dev/null +++ b/arch/mips/dts/Makefile @@ -0,0 +1,16 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-y += + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings new file mode 120000 index 00000000000..0cecb3d0805 --- /dev/null +++ b/arch/mips/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings
\ No newline at end of file diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi new file mode 100644 index 00000000000..24ee6c3e731 --- /dev/null +++ b/arch/mips/dts/skeleton.dtsi @@ -0,0 +1,23 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + chosen { + }; + + aliases { + }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index b768bb5081c..0994e9670b1 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -1,15 +1,15 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 99 Ralf Baechle * Copyright (C) 2000, 2002 Maciej W. Rozycki * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ADDRSPACE_H #define _ASM_ADDRSPACE_H +#include <spaces.h> + /* * Configure language */ @@ -50,7 +50,7 @@ */ #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) #define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) + _CONST64_(0x0000ffffffffffff)) #ifdef CONFIG_64BIT diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 933ccb1b786..44694a3fb83 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -1,8 +1,4 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 1999 by Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. @@ -13,6 +9,8 @@ * Some of the routines below contain useless nops that will be optimized * away by gas in -O mode. These nops are however required to fill delay * slots in noreorder mode. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ASM_H #define __ASM_ASM_H @@ -33,50 +31,58 @@ * Not used for the kernel but here seems to be the right place. */ #ifdef __PIC__ -#define CPRESTORE(register) \ +#define CPRESTORE(register) \ .cprestore register -#define CPADD(register) \ +#define CPADD(register) \ .cpadd register -#define CPLOAD(register) \ - .cpload register +#define CPLOAD(register) \ + .cpload register #else #define CPRESTORE(register) #define CPADD(register) #define CPLOAD(register) #endif +#define ENTRY(symbol) \ + .globl symbol; \ + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: + /* * LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ + .section .text.symbol, "x"; \ symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ + .section .text.symbol, "x"; \ symbol: .frame sp, framesize, rpc /* * END - mark end of function */ -#define END(function) \ - .end function; \ +#define END(function) \ + .end function; \ .size function, .-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* @@ -90,16 +96,16 @@ symbol: /* * ABS - export absolute symbol */ -#define ABS(symbol,value) \ - .globl symbol; \ +#define ABS(symbol,value) \ + .globl symbol; \ symbol = value -#define PANIC(msg) \ +#define PANIC(msg) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal panic; \ -9: b 9b; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal panic; \ +9: b 9b; \ .set pop; \ TEXT(msg) @@ -107,31 +113,31 @@ symbol = value * Print formatted string */ #ifdef CONFIG_PRINTK -#define PRINT(string) \ +#define PRINT(string) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal printk; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal printk; \ .set pop; \ TEXT(string) #else #define PRINT(string) #endif -#define TEXT(msg) \ +#define TEXT(msg) \ .pushsection .data; \ -8: .asciiz msg; \ +8: .asciiz msg; \ .popsection; /* * Build text tables */ -#define TTABLE(string) \ +#define TTABLE(string) \ .pushsection .text; \ - .word 1f; \ + .word 1f; \ .popsection \ .pushsection .data; \ -1: .asciiz string; \ +1: .asciiz string; \ .popsection /* @@ -143,21 +149,29 @@ symbol = value */ #ifdef CONFIG_CPU_HAS_PREFETCH -#define PREF(hint,addr) \ +#define PREF(hint, addr) \ .set push; \ - .set mips4; \ + .set arch=r5000; \ pref hint, addr; \ .set pop -#define PREFX(hint,addr) \ +#define PREFE(hint, addr) \ + .set push; \ + .set mips0; \ + .set eva; \ + prefe hint, addr; \ + .set pop + +#define PREFX(hint, addr) \ .set push; \ - .set mips4; \ + .set arch=r5000; \ prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ #define PREF(hint, addr) +#define PREFE(hint, addr) #define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ @@ -166,42 +180,42 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt, 9f; \ - move rd, rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt, 9f; \ - move rd, rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt, 9f; \ - move rd, rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt, 9f; \ - move rd, rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ movn rd, rs, rt -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ @@ -296,6 +310,7 @@ symbol = value #define LONG_SUBU subu #define LONG_L lw #define LONG_S sw +#define LONG_SP swp #define LONG_SLL sll #define LONG_SLLV sllv #define LONG_SRL srl @@ -318,6 +333,7 @@ symbol = value #define LONG_SUBU dsubu #define LONG_L ld #define LONG_S sd +#define LONG_SP sdp #define LONG_SLL dsll #define LONG_SLLV dsllv #define LONG_SRL dsrl diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index c31ff6efb44..cce6995c749 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) * Copyright (c) 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_BITOPS_H #define _ASM_BITOPS_H diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index b5e685feb62..67fdf713018 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 99, 2003 by Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_BYTEORDER_H #define _ASM_BYTEORDER_H diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 0dfb54ef4dd..806bd26ba98 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -7,15 +7,9 @@ #ifndef __MIPS_CACHE_H__ #define __MIPS_CACHE_H__ -/* - * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use - * that as a default for aligning DMA buffers unless the board config has - * specified another cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 128 -#endif +#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) #endif /* __MIPS_CACHE_H__ */ diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h index f3ce721861d..5e77dfa0293 100644 --- a/arch/mips/include/asm/cachectl.h +++ b/arch/mips/include/asm/cachectl.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_CACHECTL #define _ASM_CACHECTL diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index af2adc701ed..a3b07c6ad0d 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -1,12 +1,10 @@ /* * Cache operations for the cache instruction. * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h new file mode 100644 index 00000000000..f600e7a5b75 --- /dev/null +++ b/arch/mips/include/asm/const.h @@ -0,0 +1,31 @@ +/* + * const.h: Macros for dealing with constants. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _LINUX_CONST_H +#define _LINUX_CONST_H + +/* Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLY__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* !(_LINUX_CONST_H) */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h new file mode 100644 index 00000000000..a6e9d940190 --- /dev/null +++ b/arch/mips/include/asm/cpu-features.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include <cpu-feature-overrides.h> + +#ifdef CONFIG_32BIT +# ifndef cpu_has_64bits +# define cpu_has_64bits 0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +#endif + +#ifdef CONFIG_64BIT +# ifndef cpu_has_64bits +# define cpu_has_64bits 1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +#endif + +#endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h new file mode 100644 index 00000000000..306ab4c9f2a --- /dev/null +++ b/arch/mips/include/asm/gpio.h @@ -0,0 +1 @@ +#include <asm-generic/gpio.h> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index a7ab087c0d4..b8ac5a5ac54 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -1,21 +1,28 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995 Waldorf GmbH - * Copyright (C) 1994 - 2000 Ralf Baechle + * Copyright (C) 1994 - 2000, 06 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 FSMLabs, Inc. + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki <macro@mips.com> + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_IO_H #define _ASM_IO_H -#if 0 -#include <linux/pagemap.h> -#endif +#include <linux/compiler.h> +#include <linux/types.h> + #include <asm/addrspace.h> #include <asm/byteorder.h> +#include <asm/cpu-features.h> +#include <asm/pgtable-bits.h> +#include <asm/processor.h> +#include <asm/string.h> + +#include <ioremap.h> +#include <mangle-port.h> +#include <spaces.h> /* * Slowdown I/O port space accesses for antique hardware. @@ -23,44 +30,20 @@ #undef CONF_SLOWDOWN_IO /* - * Sane hardware offers swapping of I/O space accesses in hardware; less - * sane hardware forces software to fiddle with this ... + * Raw operations are never swapped in software. OTOH values that raw + * operations are working on may or may not have been swapped by the bus + * hardware. An example use would be for flash memory that's used for + * execute in place. */ -#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) +# define __raw_ioswabb(a, x) (x) +# define __raw_ioswabw(a, x) (x) +# define __raw_ioswabl(a, x) (x) +# define __raw_ioswabq(a, x) (x) +# define ____raw_ioswabq(a, x) (x) -#define __ioswab8(x) (x) -#define __ioswab16(x) swab16(x) -#define __ioswab32(x) swab32(x) +/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ -#else - -#define __ioswab8(x) (x) -#define __ioswab16(x) (x) -#define __ioswab32(x) (x) - -#endif - -/* - * This file contains the definitions for the MIPS counterpart of the - * x86 in/out instructions. This heap of macros and C results in much - * better code than the approach of doing it in plain C. The macros - * result in code that is to fast for certain hardware. On the other - * side the performance of the string functions should be improved for - * sake of certain devices like EIDE disks that do highspeed polled I/O. - * - * Ralf - * - * This file contains the definitions for the x86 IO instructions - * inb/inw/inl/outb/outw/outl and the "string versions" of the same - * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" - * versions of the single-IO instructions (inb_p/inw_p/..). - * - * This file is not meant to be obfuscating: it's just complicated - * to (a) handle it all in a way that makes gcc able to optimize it - * as well as possible and (b) trying to avoid writing the same thing - * over and over again with slight variations and possibly making a - * mistake somewhere. - */ +#define IO_SPACE_LIMIT 0xffff /* * On MIPS I/O ports are memory mapped, so we access them using normal @@ -84,6 +67,7 @@ extern const unsigned long mips_io_port_base; static inline void set_io_port_base(unsigned long base) { * (unsigned long *) &mips_io_port_base = base; + barrier(); } /* @@ -114,378 +98,429 @@ static inline void set_io_port_base(unsigned long base) #endif /* - * Change virtual addresses to physical addresses and vv. - * These are trivial on the 1:1 Linux/MIPS mapping + * virt_to_phys - map virtual addresses to physical + * @address: address to remap + * + * The returned physical address is the physical (CPU) mapping for + * the memory address given. It is only valid to use this function on + * addresses directly mapped or allocated via kmalloc. + * + * This function does not give bus mappings for DMA transfers. In + * almost all conceivable cases a device driver should not be using + * this function */ -static inline phys_addr_t virt_to_phys(volatile void * address) +static inline unsigned long virt_to_phys(volatile const void *address) { -#ifndef CONFIG_64BIT - return CPHYSADDR(address); + unsigned long addr = (unsigned long)address; + + /* this corresponds to kernel implementation of __pa() */ +#ifdef CONFIG_64BIT + if (addr < CKSEG0) + return XPHYSADDR(addr); + + return CPHYSADDR(addr); #else - return XPHYSADDR(address); + return addr - PAGE_OFFSET + PHYS_OFFSET; #endif } -static inline void * phys_to_virt(unsigned long address) +/* + * phys_to_virt - map physical address to virtual + * @address: address to remap + * + * The returned virtual address is a current CPU mapping for + * the memory address given. It is only valid to use this function on + * addresses that have a kernel mapping + * + * This function does not handle bus mappings for DMA transfers. In + * almost all conceivable cases a device driver should not be using + * this function + */ +static inline void *phys_to_virt(unsigned long address) { -#ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -#else - return (void *)CKSEG0ADDR(address); -#endif + return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); } /* - * IO bus memory addresses are also 1:1 with the physical address + * ISA I/O bus memory addresses are 1:1 with the physical address. */ -static inline unsigned long virt_to_bus(volatile void * address) +static inline unsigned long isa_virt_to_bus(volatile void *address) { -#ifndef CONFIG_64BIT - return CPHYSADDR(address); -#else - return XPHYSADDR(address); -#endif + return (unsigned long)address - PAGE_OFFSET; } -static inline void * bus_to_virt(unsigned long address) +static inline void *isa_bus_to_virt(unsigned long address) { -#ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -#else - return (void *)CKSEG0ADDR(address); -#endif + return (void *)(address + PAGE_OFFSET); } +#define isa_page_to_bus page_to_phys + /* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. + * However PCI ones are not necessarily 1:1 and therefore these interfaces + * are forbidden in portable PCI drivers. + * + * Allow them for x86 for legacy drivers, though. */ -extern unsigned long isa_slot_offset; +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt -extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); - -#if 0 -static inline void *ioremap(unsigned long offset, unsigned long size) +static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size, + unsigned long flags) { - return __ioremap(offset, size, _CACHE_UNCACHED); -} + void __iomem *addr; + phys_addr_t phys_addr; -static inline void *ioremap_nocache(unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, _CACHE_UNCACHED); -} + addr = plat_ioremap(offset, size, flags); + if (addr) + return addr; -extern void iounmap(void *addr); -#endif + phys_addr = fixup_bigphys_addr(offset, size); + return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); +} /* - * XXX We need system specific versions of these to handle EISA address bits - * 24-31 on SNI. - * XXX more SNI hacks. + * ioremap - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. */ -#define __raw_readb(addr) (*(volatile unsigned char *)(addr)) -#define __raw_readw(addr) (*(volatile unsigned short *)(addr)) -#define __raw_readl(addr) (*(volatile unsigned int *)(addr)) -#define readb(addr) __raw_readb((addr)) -#define readw(addr) __ioswab16(__raw_readw((addr))) -#define readl(addr) __ioswab32(__raw_readl((addr))) - -#define __raw_writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b) -#define __raw_writew(b, addr) (*(volatile unsigned short *)(addr)) = (b) -#define __raw_writel(b, addr) (*(volatile unsigned int *)(addr)) = (b) -#define writeb(b, addr) __raw_writeb((b), (addr)) -#define writew(b, addr) __raw_writew(__ioswab16(b), (addr)) -#define writel(b, addr) __raw_writel(__ioswab32(b), (addr)) - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -/* END SNI HACKS ... */ +#define ioremap(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_UNCACHED) /* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): + * ioremap_nocache - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked uncachable + * on the CPU as well as honouring existing caching rules from things like + * the PCI bus. Note that there are other caches and buffers on many + * busses. In particular driver authors should read up on PCI writes + * + * It's useful if some control registers are in such an area and + * write combining or read caching is not desirable: */ -#define __ISA_IO_base ((char *)(PAGE_OFFSET)) +#define ioremap_nocache(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_UNCACHED) +#define ioremap_uc ioremap_nocache -#define isa_readb(a) readb(a) -#define isa_readw(a) readw(a) -#define isa_readl(a) readl(a) -#define isa_writeb(b,a) writeb(b,a) -#define isa_writew(w,a) writew(w,a) -#define isa_writel(l,a) writel(l,a) - -#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) +/* + * ioremap_cachable - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked cachable by + * the CPU. Also enables full write-combining. Useful for some + * memory-like regions on I/O busses. + */ +#define ioremap_cachable(offset, size) \ + __ioremap_mode((offset), (size), _page_cachable_default) /* - * We don't have csum_partial_copy_fromio() yet, so we cheat here and - * just copy it. The net code will then do the checksum later. + * These two are MIPS specific ioremap variant. ioremap_cacheable_cow + * requests a cachable mapping, ioremap_uncached_accelerated requests a + * mapping using the uncached accelerated mode which isn't supported on + * all processors. */ -#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) -#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) +#define ioremap_cacheable_cow(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) +#define ioremap_uncached_accelerated(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) -static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) +static inline void iounmap(const volatile void __iomem *addr) { - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; + plat_iounmap(addr); } -#define isa_check_signature(io, s, l) check_signature(i,s,l) -/* - * Talk about misusing macros.. - */ +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define war_octeon_io_reorder_wmb() wmb() +#else +#define war_octeon_io_reorder_wmb() do { } while (0) +#endif -#define __OUT1(s) \ -static inline void __out##s(unsigned int value, unsigned int port) { +#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ + \ +static inline void pfx##write##bwlq(type val, \ + volatile void __iomem *mem) \ +{ \ + volatile type *__mem; \ + type __val; \ + \ + war_octeon_io_reorder_wmb(); \ + \ + __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ + \ + __val = pfx##ioswab##bwlq(__mem, val); \ + \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + *__mem = __val; \ + else if (cpu_has_64bits) { \ + type __tmp; \ + \ + __asm__ __volatile__( \ + ".set arch=r4000" "\t\t# __writeq""\n\t" \ + "dsll32 %L0, %L0, 0" "\n\t" \ + "dsrl32 %L0, %L0, 0" "\n\t" \ + "dsll32 %M0, %M0, 0" "\n\t" \ + "or %L0, %L0, %M0" "\n\t" \ + "sd %L0, %2" "\n\t" \ + ".set mips0" "\n" \ + : "=r" (__tmp) \ + : "0" (__val), "m" (*__mem)); \ + } else \ + BUG(); \ +} \ + \ +static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ +{ \ + volatile type *__mem; \ + type __val; \ + \ + __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ + \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + __val = *__mem; \ + else if (cpu_has_64bits) { \ + __asm__ __volatile__( \ + ".set arch=r4000" "\t\t# __readq" "\n\t" \ + "ld %L0, %1" "\n\t" \ + "dsra32 %M0, %L0, 0" "\n\t" \ + "sll %L0, %L0, 0" "\n\t" \ + ".set mips0" "\n" \ + : "=r" (__val) \ + : "m" (*__mem)); \ + } else { \ + __val = 0; \ + BUG(); \ + } \ + \ + return pfx##ioswab##bwlq(__mem, __val); \ +} -#define __OUT2(m) \ -__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" +#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ + \ +static inline void pfx##out##bwlq##p(type val, unsigned long port) \ +{ \ + volatile type *__addr; \ + type __val; \ + \ + war_octeon_io_reorder_wmb(); \ + \ + __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + \ + __val = pfx##ioswab##bwlq(__addr, val); \ + \ + /* Really, we want this to be atomic */ \ + BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ + \ + *__addr = __val; \ + slow; \ +} \ + \ +static inline type pfx##in##bwlq##p(unsigned long port) \ +{ \ + volatile type *__addr; \ + type __val; \ + \ + __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + \ + BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ + \ + __val = *__addr; \ + slow; \ + \ + return pfx##ioswab##bwlq(__addr, __val); \ +} -#define __OUT(m,s,w) \ -__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ -__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ -__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ - SLOW_DOWN_IO; } \ -__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ - SLOW_DOWN_IO; } +#define __BUILD_MEMORY_PFX(bus, bwlq, type) \ + \ +__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) + +#define BUILDIO_MEM(bwlq, type) \ + \ +__BUILD_MEMORY_PFX(__raw_, bwlq, type) \ +__BUILD_MEMORY_PFX(, bwlq, type) \ +__BUILD_MEMORY_PFX(__mem_, bwlq, type) \ + +BUILDIO_MEM(b, u8) +BUILDIO_MEM(w, u16) +BUILDIO_MEM(l, u32) +BUILDIO_MEM(q, u64) + +#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) + +#define BUILDIO_IOPORT(bwlq, type) \ + __BUILD_IOPORT_PFX(, bwlq, type) \ + __BUILD_IOPORT_PFX(__mem_, bwlq, type) + +BUILDIO_IOPORT(b, u8) +BUILDIO_IOPORT(w, u16) +BUILDIO_IOPORT(l, u32) +#ifdef CONFIG_64BIT +BUILDIO_IOPORT(q, u64) +#endif -#define __IN1(t,s) \ -static inline t __in##s(unsigned int port) { t _v; +#define __BUILDIO(bwlq, type) \ + \ +__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) + +__BUILDIO(q, u64) + +#define readb_relaxed readb +#define readw_relaxed readw +#define readl_relaxed readl +#define readq_relaxed readq + +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq + +#define readb_be(addr) \ + __raw_readb((__force unsigned *)(addr)) +#define readw_be(addr) \ + be16_to_cpu(__raw_readw((__force unsigned *)(addr))) +#define readl_be(addr) \ + be32_to_cpu(__raw_readl((__force unsigned *)(addr))) +#define readq_be(addr) \ + be64_to_cpu(__raw_readq((__force unsigned *)(addr))) + +#define writeb_be(val, addr) \ + __raw_writeb((val), (__force unsigned *)(addr)) +#define writew_be(val, addr) \ + __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) +#define writel_be(val, addr) \ + __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) +#define writeq_be(val, addr) \ + __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) /* - * Required nops will be inserted by the assembler + * Some code tests for these symbols */ -#define __IN2(m) \ -__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" - -#define __IN(t,m,s,w) \ -__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ -__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ -__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ -__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } - -#define __INS1(s) \ -static inline void __ins##s(unsigned int port, void * addr, unsigned long count) { - -#define __INS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,%4(%5)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,(%0)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __INS(m,s,i) \ -__INS1(s) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), \ - "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__INS1(s##c) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), \ - "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -#define __OUTS1(s) \ -static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { - -#define __OUTS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,(%0)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,%4(%5)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __OUTS(m,s,i) \ -__OUTS1(s) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__OUTS1(s##c) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -__IN(unsigned char,b,b,8) -__IN(unsigned short,h,w,16) -__IN(unsigned int,w,l,32) - -__OUT(b,b,8) -__OUT(h,w,16) -__OUT(w,l,32) - -__INS(b,b,1) -__INS(h,w,2) -__INS(w,l,4) - -__OUTS(b,b,1) -__OUTS(h,w,2) -__OUTS(w,l,4) +#define readq readq +#define writeq writeq + +#define __BUILD_MEMORY_STRING(bwlq, type) \ + \ +static inline void writes##bwlq(volatile void __iomem *mem, \ + const void *addr, unsigned int count) \ +{ \ + const volatile type *__addr = addr; \ + \ + while (count--) { \ + __mem_write##bwlq(*__addr, mem); \ + __addr++; \ + } \ +} \ + \ +static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ + unsigned int count) \ +{ \ + volatile type *__addr = addr; \ + \ + while (count--) { \ + *__addr = __mem_read##bwlq(mem); \ + __addr++; \ + } \ +} +#define __BUILD_IOPORT_STRING(bwlq, type) \ + \ +static inline void outs##bwlq(unsigned long port, const void *addr, \ + unsigned int count) \ +{ \ + const volatile type *__addr = addr; \ + \ + while (count--) { \ + __mem_out##bwlq(*__addr, port); \ + __addr++; \ + } \ +} \ + \ +static inline void ins##bwlq(unsigned long port, void *addr, \ + unsigned int count) \ +{ \ + volatile type *__addr = addr; \ + \ + while (count--) { \ + *__addr = __mem_in##bwlq(port); \ + __addr++; \ + } \ +} -/* - * Note that due to the way __builtin_constant_p() works, you - * - can't use it inside an inline function (it will never be true) - * - you don't have to worry about side effects within the __builtin.. - */ -#define outb(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc((val),(port)) : \ - __outb((val),(port))) - -#define inb(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc(port) : \ - __inb(port)) - -#define outb_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc_p((val),(port)) : \ - __outb_p((val),(port))) - -#define inb_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc_p(port) : \ - __inb_p(port)) - -#define outw(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc((val),(port)) : \ - __outw((val),(port))) - -#define inw(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc(port) : \ - __inw(port)) - -#define outw_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc_p((val),(port)) : \ - __outw_p((val),(port))) - -#define inw_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc_p(port) : \ - __inw_p(port)) - -#define outl(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc((val),(port)) : \ - __outl((val),(port))) - -#define inl(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc(port) : \ - __inl(port)) - -#define outl_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc_p((val),(port)) : \ - __outl_p((val),(port))) - -#define inl_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc_p(port) : \ - __inl_p(port)) - - -#define outsb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outsbc((port),(addr),(count)) : \ - __outsb ((port),(addr),(count))) - -#define insb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __insbc((port),(addr),(count)) : \ - __insb((port),(addr),(count))) - -#define outsw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outswc((port),(addr),(count)) : \ - __outsw ((port),(addr),(count))) - -#define insw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inswc((port),(addr),(count)) : \ - __insw((port),(addr),(count))) - -#define outsl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outslc((port),(addr),(count)) : \ - __outsl ((port),(addr),(count))) - -#define insl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inslc((port),(addr),(count)) : \ - __insl((port),(addr),(count))) +#define BUILDSTRING(bwlq, type) \ + \ +__BUILD_MEMORY_STRING(bwlq, type) \ +__BUILD_IOPORT_STRING(bwlq, type) -#define IO_SPACE_LIMIT 0xffff +BUILDSTRING(b, u8) +BUILDSTRING(w, u16) +BUILDSTRING(l, u32) +#ifdef CONFIG_64BIT +BUILDSTRING(q, u64) +#endif -/* - * The caches on some architectures aren't dma-coherent and have need to - * handle this in software. There are three types of operations that - * can be applied to dma buffers. - * - * - dma_cache_wback_inv(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_wback(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_inv(start, size) invalidates the affected parts of the - * caches. Dirty lines of the caches may be written back or simply - * be discarded. This operation is necessary before dma operations - * to the memory. - */ -extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); -extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); -extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); -#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start,size) _dma_cache_wback(start,size) -#define dma_cache_inv(start,size) _dma_cache_inv(start,size) +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define mmiowb() wmb() +#else +/* Depends on MIPS II instruction set */ +#define mmiowb() asm volatile ("sync" ::: "memory") +#endif -static inline void sync(void) +static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) +{ + memset((void __force *)addr, val, count); +} +static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) +{ + memcpy(dst, (void __force *)src, count); +} +static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) { + memcpy((void __force *)dst, src, count); } /* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". + * Read a 32-bit register that requires a 64-bit read cycle on the bus. + * Avoid interrupt mucking, just adjust the address for 4-byte access. + * Assume the addresses are 8-byte aligned. + */ +#ifdef __MIPSEB__ +#define __CSR_32_ADJUST 4 +#else +#define __CSR_32_ADJUST 0 +#endif + +#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) +#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) + +/* + * U-Boot specific */ -#define MAP_NOCACHE (0) +#define sync() mmiowb() + +#define MAP_NOCACHE (1) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) #define MAP_WRTHROUGH (0) @@ -493,6 +528,9 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { + if (flags == MAP_NOCACHE) + return ioremap(paddr, len); + return (void *)paddr; } @@ -501,7 +539,61 @@ map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) */ static inline void unmap_physmem(void *vaddr, unsigned long flags) { +} +#define __BUILD_CLRBITS(bwlq, sfx, end, type) \ + \ +static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \ +{ \ + type __val = __raw_read##bwlq(mem); \ + __val = end##_to_cpu(__val); \ + __val &= ~clr; \ + __val = cpu_to_##end(__val); \ + __raw_write##bwlq(__val, mem); \ } +#define __BUILD_SETBITS(bwlq, sfx, end, type) \ + \ +static inline void setbits_##sfx(volatile void __iomem *mem, type set) \ +{ \ + type __val = __raw_read##bwlq(mem); \ + __val = end##_to_cpu(__val); \ + __val |= set; \ + __val = cpu_to_##end(__val); \ + __raw_write##bwlq(__val, mem); \ +} + +#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \ + \ +static inline void clrsetbits_##sfx(volatile void __iomem *mem, \ + type clr, type set) \ +{ \ + type __val = __raw_read##bwlq(mem); \ + __val = end##_to_cpu(__val); \ + __val &= ~clr; \ + __val |= set; \ + __val = cpu_to_##end(__val); \ + __raw_write##bwlq(__val, mem); \ +} + +#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \ + \ +__BUILD_CLRBITS(bwlq, sfx, end, type) \ +__BUILD_SETBITS(bwlq, sfx, end, type) \ +__BUILD_CLRSETBITS(bwlq, sfx, end, type) + +#define __to_cpu(v) (v) +#define cpu_to__(v) (v) + +BUILD_CLRSETBITS(b, 8, _, u8) +BUILD_CLRSETBITS(w, le16, le16, u16) +BUILD_CLRSETBITS(w, be16, be16, u16) +BUILD_CLRSETBITS(w, 16, _, u16) +BUILD_CLRSETBITS(l, le32, le32, u32) +BUILD_CLRSETBITS(l, be32, be32, u32) +BUILD_CLRSETBITS(l, 32, _, u32) +BUILD_CLRSETBITS(q, le64, le64, u64) +BUILD_CLRSETBITS(q, be64, be64, u64) +BUILD_CLRSETBITS(q, 64, _, u64) + #endif /* _ASM_IO_H */ diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h index 24c6cda7937..3d79ebcf593 100644 --- a/arch/mips/include/asm/isadep.h +++ b/arch/mips/include/asm/isadep.h @@ -4,6 +4,8 @@ * of Coprocessor 0 registers. * * Copyright (c) 1998 Harald Koerfgen + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ISADEP_H @@ -18,7 +20,7 @@ * kernel or user mode? (CP0_STATUS) */ #define KU_MASK 0x08 -#define KU_USER 0x08 +#define KU_USER 0x08 #define KU_KERN 0x00 #else @@ -26,7 +28,7 @@ * kernel or user mode? */ #define KU_MASK 0x18 -#define KU_USER 0x10 +#define KU_USER 0x10 #define KU_KERN 0x00 #endif diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h new file mode 100644 index 00000000000..613f844f08c --- /dev/null +++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2003 Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H + +/* Intentionally empty file ... */ + +#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h new file mode 100644 index 00000000000..6b191d54a69 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/ioremap.h @@ -0,0 +1,32 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_GENERIC_IOREMAP_H +#define __ASM_MACH_GENERIC_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_GENERIC_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h new file mode 100644 index 00000000000..f18e53f7b83 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/mangle-port.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H +#define __ASM_MACH_GENERIC_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +/* + * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; + * less sane hardware forces software to fiddle with this... + * + * Regardless, if the host bus endianness mismatches that of PCI/ISA, then + * you can't have the numerical value of data and byte addresses within + * multibyte quantities both preserved at the same time. Hence two + * variations of functions: non-prefixed ones that preserve the value + * and prefixed ones that preserve byte addresses. The latters are + * typically used for moving raw data between a peripheral and memory (cf. + * string I/O functions), hence the "__mem_" prefix. + */ +#if defined(CONFIG_SWAP_IO_SPACE) + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) le16_to_cpu(x) +# define __mem_ioswabw(a, x) (x) +# define ioswabl(a, x) le32_to_cpu(x) +# define __mem_ioswabl(a, x) (x) +# define ioswabq(a, x) le64_to_cpu(x) +# define __mem_ioswabq(a, x) (x) + +#else + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) + +#endif + +#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h new file mode 100644 index 00000000000..ab06674b144 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _ASM_MACH_GENERIC_SPACES_H +#define _ASM_MACH_GENERIC_SPACES_H + +#include <asm/const.h> + +/* + * This gives the physical RAM offset. + */ +#ifndef PHYS_OFFSET +#define PHYS_OFFSET _AC(0, UL) +#endif + +#ifdef CONFIG_32BIT +#ifdef CONFIG_KVM_GUEST +#define CAC_BASE _AC(0x40000000, UL) +#else +#define CAC_BASE _AC(0x80000000, UL) +#endif +#ifndef IO_BASE +#define IO_BASE _AC(0xa0000000, UL) +#endif +#ifndef UNCAC_BASE +#define UNCAC_BASE _AC(0xa0000000, UL) +#endif + +#ifndef MAP_BASE +#ifdef CONFIG_KVM_GUEST +#define MAP_BASE _AC(0x60000000, UL) +#else +#define MAP_BASE _AC(0xc0000000, UL) +#endif +#endif + +/* + * Memory above this physical address will be considered highmem. + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START _AC(0x20000000, UL) +#endif + +#endif /* CONFIG_32BIT */ + +#ifdef CONFIG_64BIT + +#ifndef CAC_BASE +#ifdef CONFIG_DMA_NONCOHERENT +#define CAC_BASE _AC(0x9800000000000000, UL) +#else +#define CAC_BASE _AC(0xa800000000000000, UL) +#endif +#endif + +#ifndef IO_BASE +#define IO_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef UNCAC_BASE +#define UNCAC_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef MAP_BASE +#define MAP_BASE _AC(0xc000000000000000, UL) +#endif + +/* + * Memory above this physical address will be considered highmem. + * Fixme: 59 bits is a fictive number and makes assumptions about processors + * in the distant future. Nobody will care for a few years :-) + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) +#endif + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) + +#endif /* CONFIG_64BIT */ + +/* + * This handles the memory map. + */ +#ifndef PAGE_OFFSET +#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) +#endif + +#ifndef FIXADDR_TOP +#ifdef CONFIG_KVM_GUEST +#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000) +#else +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) +#endif +#endif + +#endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index c7a08499ff2..3185dc7abf2 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1,22 +1,16 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 07 MIPS Technologies, Inc. * Copyright (C) 2003, 2004 Maciej W. Rozycki + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H -#if 0 -#include <linux/linkage.h> -#endif - /* * The following macros are especially useful for __asm__ * inline assembler. @@ -49,7 +43,9 @@ #define CP0_PAGEMASK $5 #define CP0_WIRED $6 #define CP0_INFO $7 +#define CP0_HWRENA $7, 0 #define CP0_BADVADDR $8 +#define CP0_BADINSTR $8, 1 #define CP0_COUNT $9 #define CP0_ENTRYHI $10 #define CP0_COMPARE $11 @@ -57,7 +53,11 @@ #define CP0_CAUSE $13 #define CP0_EPC $14 #define CP0_PRID $15 +#define CP0_EBASE $15, 1 +#define CP0_CMGCRBASE $15, 3 #define CP0_CONFIG $16 +#define CP0_CONFIG3 $16, 3 +#define CP0_CONFIG5 $16, 5 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 @@ -98,74 +98,36 @@ /* * Coprocessor 0 Set 2 register names */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ /* * Coprocessor 0 Set 3 register names */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ /* * TX39 Series */ #define CP0_TX39_CACHE $7 -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ +/* Generic EntryLo bit definitions */ +#define ENTRYLO_G (_ULCAST_(1) << 0) +#define ENTRYLO_V (_ULCAST_(1) << 1) +#define ENTRYLO_D (_ULCAST_(1) << 2) +#define ENTRYLO_C_SHIFT 3 +#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +/* R3000 EntryLo bit definitions */ +#define R3K_ENTRYLO_G (_ULCAST_(1) << 8) +#define R3K_ENTRYLO_V (_ULCAST_(1) << 9) +#define R3K_ENTRYLO_D (_ULCAST_(1) << 10) +#define R3K_ENTRYLO_N (_ULCAST_(1) << 11) -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit - */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +/* MIPS32/64 EntryLo bit definitions */ +#define MIPS_ENTRYLO_PFN_SHIFT 6 +#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2)) +#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1)) /* * Values for PageMask register @@ -183,14 +145,22 @@ #else #define PM_4K 0x00000000 +#define PM_8K 0x00002000 #define PM_16K 0x00006000 +#define PM_32K 0x0000e000 #define PM_64K 0x0001e000 +#define PM_128K 0x0003e000 #define PM_256K 0x0007e000 +#define PM_512K 0x000fe000 #define PM_1M 0x001fe000 +#define PM_2M 0x003fe000 #define PM_4M 0x007fe000 +#define PM_8M 0x00ffe000 #define PM_16M 0x01ffe000 +#define PM_32M 0x03ffe000 #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 +#define PM_1G 0x7fffe000 #endif @@ -208,10 +178,22 @@ #define PL_256M 28 /* + * PageGrain bits + */ +#define PG_RIE (_ULCAST_(1) << 31) +#define PG_XIE (_ULCAST_(1) << 30) +#define PG_ELPA (_ULCAST_(1) << 29) +#define PG_ESP (_ULCAST_(1) << 28) +#define PG_IEC (_ULCAST_(1) << 27) + +/* MIPS32/64 EntryHI bit definitions */ +#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) + +/* * R4x00 interrupt enable / cause bits */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) #define IE_IRQ0 (_ULCAST_(1) << 10) #define IE_IRQ1 (_ULCAST_(1) << 11) #define IE_IRQ2 (_ULCAST_(1) << 12) @@ -222,8 +204,8 @@ /* * R4x00 interrupt cause bits */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) #define C_IRQ0 (_ULCAST_(1) << 10) #define C_IRQ1 (_ULCAST_(1) << 11) #define C_IRQ2 (_ULCAST_(1) << 12) @@ -271,7 +253,7 @@ /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_UM (_ULCAST_(1) << 4) #define ST0_IL (_ULCAST_(1) << 23) #define ST0_DL (_ULCAST_(1) << 24) @@ -281,75 +263,43 @@ #define ST0_MX 0x01000000 /* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* * Status register bits available in all MIPS CPUs. */ #define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) #define ST0_CH 0x00040000 +#define ST0_NMI 0x00080000 #define ST0_SR 0x00100000 #define ST0_TS 0x00200000 #define ST0_BEV 0x00400000 @@ -363,36 +313,52 @@ #define ST0_XX 0x80000000 /* MIPS IV naming */ /* + * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) + */ +#define INTCTLB_IPFDC 23 +#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) +#define INTCTLB_IPPCI 26 +#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) +#define INTCTLB_IPTI 29 +#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) + +/* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_FDCI 21 +#define CAUSEF_FDCI (_ULCAST_(1) << 21) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_PCI 26 +#define CAUSEF_PCI (_ULCAST_(1) << 26) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_TI 30 +#define CAUSEF_TI (_ULCAST_(1) << 30) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. @@ -410,43 +376,43 @@ #define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) #define CONF_EB (_ULCAST_(1) << 13) #define CONF_EM (_ULCAST_(1) << 14) #define CONF_SM (_ULCAST_(1) << 16) #define CONF_SC (_ULCAST_(1) << 17) #define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EP (_ULCAST_(15) << 24) #define CONF_EC (_ULCAST_(7) << 28) #define CONF_CM (_ULCAST_(1) << 31) -/* Bits specific to the R4xx0. */ +/* Bits specific to the R4xx0. */ #define R4K_CONF_SW (_ULCAST_(1) << 20) #define R4K_CONF_SS (_ULCAST_(1) << 21) #define R4K_CONF_SB (_ULCAST_(3) << 22) -/* Bits specific to the R5000. */ +/* Bits specific to the R5000. */ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) #define RM7K_CONF_TE (_ULCAST_(1) << 12) #define RM7K_CONF_CLK (_ULCAST_(1) << 16) #define RM7K_CONF_TC (_ULCAST_(1) << 17) #define RM7K_CONF_SI (_ULCAST_(3) << 20) #define RM7K_CONF_SC (_ULCAST_(1) << 31) -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15) << 9) #define R10K_CONF_SB (_ULCAST_(1) << 13) #define R10K_CONF_SK (_ULCAST_(1) << 14) #define R10K_CONF_SS (_ULCAST_(7) << 16) @@ -454,14 +420,14 @@ #define R10K_CONF_DC (_ULCAST_(7) << 26) #define R10K_CONF_IC (_ULCAST_(7) << 29) -/* Bits specific to the VR41xx. */ +/* Bits specific to the VR41xx. */ #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_P4K (_ULCAST_(1) << 13) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_AD (_ULCAST_(1) << 23) -/* Bits specific to the R30xx. */ +/* Bits specific to the R30xx. */ #define R30XX_CONF_FDM (_ULCAST_(1) << 19) #define R30XX_CONF_REV (_ULCAST_(1) << 22) #define R30XX_CONF_AC (_ULCAST_(1) << 23) @@ -478,8 +444,10 @@ #define TX49_CONF_HALT (_ULCAST_(1) << 18) #define TX49_CONF_CWFON (_ULCAST_(1) << 27) -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) +#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) #define MIPS_CONF_AR (_ULCAST_(7) << 10) #define MIPS_CONF_AT (_ULCAST_(3) << 13) #define MIPS_CONF_M (_ULCAST_(1) << 31) @@ -487,50 +455,245 @@ /* * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA_SHIFT 7 -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL_SHIFT 10 +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHF 7 +#define MIPS_CONF1_DA_SZ 3 +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHF 10 +#define MIPS_CONF1_DL_SZ 3 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS_SHIFT 13 +#define MIPS_CONF1_DS_SHF 13 +#define MIPS_CONF1_DS_SZ 3 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA_SHIFT 16 +#define MIPS_CONF1_IA_SHF 16 +#define MIPS_CONF1_IA_SZ 3 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL_SHIFT 19 +#define MIPS_CONF1_IL_SHF 19 +#define MIPS_CONF1_IL_SZ 3 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS_SHIFT 22 +#define MIPS_CONF1_IS_SHF 22 +#define MIPS_CONF1_IS_SZ 3 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF1_TLBS_SHIFT (25) +#define MIPS_CONF1_TLBS_SIZE (6) +#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) + +#define MIPS_CONF2_SA (_ULCAST_(15) << 0) +#define MIPS_CONF2_SL (_ULCAST_(15) << 4) +#define MIPS_CONF2_SS (_ULCAST_(15) << 8) +#define MIPS_CONF2_SU (_ULCAST_(15) << 12) +#define MIPS_CONF2_TA (_ULCAST_(15) << 16) +#define MIPS_CONF2_TL (_ULCAST_(15) << 20) +#define MIPS_CONF2_TS (_ULCAST_(15) << 24) #define MIPS_CONF2_TU (_ULCAST_(7) << 28) -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_ITL (_ULCAST_(1) << 8) +#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) +#define MIPS_CONF3_MCU (_ULCAST_(1) << 17) +#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) +#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) +#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) +#define MIPS_CONF3_PW (_ULCAST_(1) << 24) +#define MIPS_CONF3_SC (_ULCAST_(1) << 25) +#define MIPS_CONF3_BI (_ULCAST_(1) << 26) +#define MIPS_CONF3_BP (_ULCAST_(1) << 27) +#define MIPS_CONF3_MSA (_ULCAST_(1) << 28) +#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) +#define MIPS_CONF3_BPG (_ULCAST_(1) << 30) + +#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) +#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) +#define MIPS_CONF4_FTLBSETS_SHIFT (0) +#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) +#define MIPS_CONF4_FTLBWAYS_SHIFT (4) +#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) +#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) +/* bits 10:8 in FTLB-only configurations */ +#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) +/* bits 12:8 in VTLB-FTLB only configurations */ +#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) +#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) +#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) +#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) +#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) +#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) +#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) +#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) +#define MIPS_CONF4_AE (_ULCAST_(1) << 28) +#define MIPS_CONF4_IE (_ULCAST_(3) << 29) +#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) + +#define MIPS_CONF5_NF (_ULCAST_(1) << 0) +#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) +#define MIPS_CONF5_MRP (_ULCAST_(1) << 3) +#define MIPS_CONF5_LLB (_ULCAST_(1) << 4) +#define MIPS_CONF5_MVH (_ULCAST_(1) << 5) +#define MIPS_CONF5_FRE (_ULCAST_(1) << 8) +#define MIPS_CONF5_UFE (_ULCAST_(1) << 9) +#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) +#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) +#define MIPS_CONF5_CV (_ULCAST_(1) << 29) +#define MIPS_CONF5_K (_ULCAST_(1) << 30) + +#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) +/* proAptiv FTLB on/off bit */ +#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) +/* FTLB probability bits */ +#define MIPS_CONF6_FTLBP_SHIFT (16) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) +#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) +#define MIPS_CONF7_AR (_ULCAST_(1) << 16) +/* FTLB probability bits for R6 */ +#define MIPS_CONF7_FTLBP_SHIFT (18) + +/* MAAR bit definitions */ +#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) +#define MIPS_MAAR_ADDR_SHIFT 12 +#define MIPS_MAAR_S (_ULCAST_(1) << 1) +#define MIPS_MAAR_V (_ULCAST_(1) << 0) + +/* CMGCRBase bit definitions */ +#define MIPS_CMGCRB_BASE 11 +#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) + +/* + * Bits in the MIPS32 Memory Segmentation registers. + */ +#define MIPS_SEGCFG_PA_SHIFT 9 +#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) +#define MIPS_SEGCFG_AM_SHIFT 4 +#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) +#define MIPS_SEGCFG_EU_SHIFT 3 +#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) +#define MIPS_SEGCFG_C_SHIFT 0 +#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) + +#define MIPS_SEGCFG_UUSK _ULCAST_(7) +#define MIPS_SEGCFG_USK _ULCAST_(5) +#define MIPS_SEGCFG_MUSUK _ULCAST_(4) +#define MIPS_SEGCFG_MUSK _ULCAST_(3) +#define MIPS_SEGCFG_MSK _ULCAST_(2) +#define MIPS_SEGCFG_MK _ULCAST_(1) +#define MIPS_SEGCFG_UK _ULCAST_(0) + +#define MIPS_PWFIELD_GDI_SHIFT 24 +#define MIPS_PWFIELD_GDI_MASK 0x3f000000 +#define MIPS_PWFIELD_UDI_SHIFT 18 +#define MIPS_PWFIELD_UDI_MASK 0x00fc0000 +#define MIPS_PWFIELD_MDI_SHIFT 12 +#define MIPS_PWFIELD_MDI_MASK 0x0003f000 +#define MIPS_PWFIELD_PTI_SHIFT 6 +#define MIPS_PWFIELD_PTI_MASK 0x00000fc0 +#define MIPS_PWFIELD_PTEI_SHIFT 0 +#define MIPS_PWFIELD_PTEI_MASK 0x0000003f + +#define MIPS_PWSIZE_GDW_SHIFT 24 +#define MIPS_PWSIZE_GDW_MASK 0x3f000000 +#define MIPS_PWSIZE_UDW_SHIFT 18 +#define MIPS_PWSIZE_UDW_MASK 0x00fc0000 +#define MIPS_PWSIZE_MDW_SHIFT 12 +#define MIPS_PWSIZE_MDW_MASK 0x0003f000 +#define MIPS_PWSIZE_PTW_SHIFT 6 +#define MIPS_PWSIZE_PTW_MASK 0x00000fc0 +#define MIPS_PWSIZE_PTEW_SHIFT 0 +#define MIPS_PWSIZE_PTEW_MASK 0x0000003f + +#define MIPS_PWCTL_PWEN_SHIFT 31 +#define MIPS_PWCTL_PWEN_MASK 0x80000000 +#define MIPS_PWCTL_DPH_SHIFT 7 +#define MIPS_PWCTL_DPH_MASK 0x00000080 +#define MIPS_PWCTL_HUGEPG_SHIFT 6 +#define MIPS_PWCTL_HUGEPG_MASK 0x00000060 +#define MIPS_PWCTL_PSN_SHIFT 0 +#define MIPS_PWCTL_PSN_MASK 0x0000003f + +/* CDMMBase register bit definitions */ +#define MIPS_CDMMBASE_SIZE_SHIFT 0 +#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) +#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) +#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) +#define MIPS_CDMMBASE_ADDR_SHIFT 11 +#define MIPS_CDMMBASE_ADDR_START 15 + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Interesting Bits in the R10K CP0 Branch Diagnostic Register + */ +/* Disable Branch Target Address Cache */ +#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) +/* Enable Branch Prediction Global History */ +#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) +/* Disable Branch Return Cache */ +#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_UFR $1 +#define CP1_UNFR $4 +#define CP1_FCCR $25 +#define CP1_FEXR $26 +#define CP1_FENR $28 +#define CP1_STATUS $31 + + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ @@ -541,11 +704,150 @@ #define MIPS_FPIR_W (_ULCAST_(1) << 20) #define MIPS_FPIR_L (_ULCAST_(1) << 21) #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) +#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. + */ +#define MIPS_FCCR_CONDX_S 0 +#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) +#define MIPS_FCCR_COND0_S 0 +#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) +#define MIPS_FCCR_COND1_S 1 +#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) +#define MIPS_FCCR_COND2_S 2 +#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) +#define MIPS_FCCR_COND3_S 3 +#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) +#define MIPS_FCCR_COND4_S 4 +#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) +#define MIPS_FCCR_COND5_S 5 +#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) +#define MIPS_FCCR_COND6_S 6 +#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) +#define MIPS_FCCR_COND7_S 7 +#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. + */ +#define MIPS_FENR_FS_S 2 +#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) + +/* + * FPU Status Register Values + */ +#define FPU_CSR_COND_S 23 /* $fcc0 */ +#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) + +#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ +#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) + +#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ +#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) +#define FPU_CSR_COND1_S 25 /* $fcc1 */ +#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) +#define FPU_CSR_COND2_S 26 /* $fcc2 */ +#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) +#define FPU_CSR_COND3_S 27 /* $fcc3 */ +#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) +#define FPU_CSR_COND4_S 28 /* $fcc4 */ +#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) +#define FPU_CSR_COND5_S 29 /* $fcc5 */ +#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) +#define FPU_CSR_COND6_S 30 /* $fcc6 */ +#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) +#define FPU_CSR_COND7_S 31 /* $fcc7 */ +#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) + +/* + * Bits 22:20 of the FPU Status Register will be read as 0, + * and should be written as zero. + */ +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) + +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + #ifndef __ASSEMBLY__ /* - * Functions to access the R10000 performance counters. These are basically + * Macros for handling the ISA mode bit for MIPS16 and microMIPS. + */ +#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ + defined(CONFIG_SYS_SUPPORTS_MICROMIPS) +#define get_isa16_mode(x) ((x) & 0x1) +#define msk_isa16_mode(x) ((x) & ~0x1) +#define set_isa16_mode(x) do { (x) |= 0x1; } while (0) +#else +#define get_isa16_mode(x) 0 +#define msk_isa16_mode(x) (x) +#define set_isa16_mode(x) do { } while (0) +#endif + +/* + * microMIPS instructions can be 16-bit or 32-bit in length. This + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. + */ +static inline int mm_insn_16bit(u16 insn) +{ + u16 opcode = (insn >> 10) & 0x7; + + return (opcode >= 1 && opcode <= 3) ? 1 : 0; +} + +/* + * TLB Invalidate Flush + */ +static inline void tlbinvf(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".word 0x42000004\n\t" /* tlbinvf */ + ".set pop"); +} + + +/* + * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * performance counter number encoded into bits 1 ... 5 of the instruction. * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware @@ -589,6 +891,7 @@ do { \ : "r" (val), "i" (counter)); \ } while (0) + /* * Macros to access the system control coprocessor */ @@ -705,8 +1008,8 @@ do { \ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ else \ @@ -714,8 +1017,8 @@ do { \ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source ", " #sel "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ local_irq_restore(__flags); \ @@ -751,15 +1054,57 @@ do { \ local_irq_restore(__flags); \ } while (0) +#define __readx_32bit_c0_register(source) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips32r2 \n" \ + " .insn \n" \ + " # mfhc0 $1, %1 \n" \ + " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (source)); \ + __res; \ +}) + +#define __writex_32bit_c0_register(register, value) \ +({ \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips32r2 \n" \ + " move $1, %0 \n" \ + " # mthc0 $1, %1 \n" \ + " .insn \n" \ + " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ + " .set pop \n" \ + : \ + : "r" (value), "i" (register)); \ +}) + #define read_c0_index() __read_32bit_c0_register($0, 0) #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) +#define readx_c0_entrylo0() __readx_32bit_c0_register(2) +#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) + #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) +#define readx_c0_entrylo1() __readx_32bit_c0_register(3) +#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) + #define read_c0_conf() __read_32bit_c0_register($3, 0) #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) @@ -767,17 +1112,20 @@ do { \ #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) #define read_c0_userlocal() __read_ulong_c0_register($4, 2) -#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) +#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) + #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) #define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) @@ -805,19 +1153,8 @@ do { \ #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) #define read_c0_status() __read_32bit_c0_register($12, 0) -#ifdef CONFIG_MIPS_MT_SMTC -#define write_c0_status(val) \ -do { \ - __write_32bit_c0_register($12, 0, val); \ - __ehb(); \ -} while (0) -#else -/* - * Legacy non-SMTC code, which may be hazardous - * but which might not support EHB - */ + #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#endif /* CONFIG_MIPS_MT_SMTC */ #define read_c0_cause() __read_32bit_c0_register($13, 0) #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) @@ -827,6 +1164,8 @@ do { \ #define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) + #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) @@ -844,8 +1183,15 @@ do { \ #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) +#define read_c0_lladdr() __read_ulong_c0_register($17, 0) +#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) +#define read_c0_maar() __read_ulong_c0_register($17, 1) +#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) +#define read_c0_maari() __read_32bit_c0_register($17, 2) +#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) + /* - * The WatchLo register. There may be upto 8 of them. + * The WatchLo register. There may be up to 8 of them. */ #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) @@ -865,7 +1211,7 @@ do { \ #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* - * The WatchHi register. There may be upto 8 of them. + * The WatchHi register. There may be up to 8 of them. */ #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) @@ -892,15 +1238,15 @@ do { \ #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) #define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) - -/* RM9000 PerfControl performance counter control register */ -#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) -#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) #define read_c0_diag() __read_32bit_c0_register($22, 0) #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) +/* R10K CP0 Branch Diagnostic register is 64bits wide */ +#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) +#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) + #define read_c0_diag1() __read_32bit_c0_register($22, 1) #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) @@ -926,36 +1272,40 @@ do { \ * MIPS32 / MIPS64 performance counters */ #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) -#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) +#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) -#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) +#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) -#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) +#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) -#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) +#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) -#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) +#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) -#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) +#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) -#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) +#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) -#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) - -/* RM9000 PerfCount performance counter register */ -#define read_c0_perfcount() __read_64bit_c0_register($25, 0) -#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) +#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) +#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) +#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) #define read_c0_ecc() __read_32bit_c0_register($26, 0) #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) #define read_c0_taglo() __read_32bit_c0_register($28, 0) #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) @@ -963,6 +1313,12 @@ do { \ #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) +#define read_c0_ddatalo() __read_32bit_c0_register($28, 3) +#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) + +#define read_c0_staglo() __read_32bit_c0_register($28, 4) +#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) + #define read_c0_taghi() __read_32bit_c0_register($29, 0) #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) @@ -985,271 +1341,524 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) +#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) +#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) + +/* MIPSR3 */ +#define read_c0_segctl0() __read_32bit_c0_register($5, 2) +#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) + +#define read_c0_segctl1() __read_32bit_c0_register($5, 3) +#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) + +#define read_c0_segctl2() __read_32bit_c0_register($5, 4) +#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) + +/* Hardware Page Table Walker */ +#define read_c0_pwbase() __read_ulong_c0_register($5, 5) +#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) + +#define read_c0_pwfield() __read_ulong_c0_register($5, 6) +#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) + +#define read_c0_pwsize() __read_ulong_c0_register($5, 7) +#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) + +#define read_c0_pwctl() __read_32bit_c0_register($6, 6) +#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) /* - * Macros to access the floating point coprocessor control registers + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) -#define rddsp(mask) \ +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + +/* BMIPS3300 */ +#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) +#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) +#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) +#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) + +/* BMIPS43xx */ +#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) +#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) +#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) +#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) +#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) + +#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) +#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) + +/* BMIPS5000 */ +#define read_c0_brcm_config() __read_32bit_c0_register($22, 0) +#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) +#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_brcm_action() __read_32bit_c0_register($22, 2) +#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) +#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) +#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) +#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) + +/* + * Macros to access the floating point coprocessor control registers + */ +#define _read_32bit_cp1_register(source, gas_hardfloat) \ ({ \ unsigned int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " "STR(gas_hardfloat)" \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ __res; \ }) -#define wrdsp(val, mask) \ -do { \ +#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set reorder \n" \ + " "STR(gas_hardfloat)" \n" \ + " ctc1 %0,"STR(dest)" \n" \ " .set pop \n" \ + : : "r" (val)); \ +}) + +#ifdef GAS_HAS_SET_HARDFLOAT +#define read_32bit_cp1_register(source) \ + _read_32bit_cp1_register(source, .set hardfloat) +#define write_32bit_cp1_register(dest, val) \ + _write_32bit_cp1_register(dest, val, .set hardfloat) +#else +#define read_32bit_cp1_register(source) \ + _read_32bit_cp1_register(source, ) +#define write_32bit_cp1_register(dest, val) \ + _write_32bit_cp1_register(dest, val, ) +#endif + +#ifdef HAVE_AS_DSP +#define rddsp(mask) \ +({ \ + unsigned int __dspctl; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set dsp \n" \ + " rddsp %0, %x1 \n" \ + " .set pop \n" \ + : "=r" (__dspctl) \ + : "i" (mask)); \ + __dspctl; \ +}) + +#define wrdsp(val, mask) \ +({ \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set dsp \n" \ + " wrdsp %0, %x1 \n" \ + " .set pop \n" \ : \ : "r" (val), "i" (mask)); \ -} while (0) +}) + +#define mflo0() \ +({ \ + long mflo0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mflo0)); \ + mflo0; \ +}) + +#define mflo1() \ +({ \ + long mflo1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mflo1)); \ + mflo1; \ +}) + +#define mflo2() \ +({ \ + long mflo2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mflo2)); \ + mflo2; \ +}) + +#define mflo3() \ +({ \ + long mflo3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mflo3)); \ + mflo3; \ +}) #define mfhi0() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mfhi0)); \ + mfhi0; \ }) #define mfhi1() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mfhi1)); \ + mfhi1; \ }) #define mfhi2() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mfhi2)); \ + mfhi2; \ }) #define mfhi3() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mfhi3)); \ + mfhi3; \ }) -#define mflo0() \ + +#define mtlo0(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac0 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo1() \ +#define mtlo1(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo2() \ +#define mtlo2(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo3() \ +#define mtlo3(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) #define mthi0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ - " .set pop \n" \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac0 \n" \ + " .set pop \n" \ : \ : "r" (x)); \ -} while (0) +}) #define mthi1(x) \ -do { \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi2(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi3(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#else + +#ifdef CONFIG_CPU_MICROMIPS +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ + " # rddsp $1, %x1 \n" \ + " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mthi2(x) \ -do { \ +#define wrdsp(val, mask) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ + " # wrdsp $1, %x1 \n" \ + " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (mask)); \ +}) -#define mthi3(x) \ -do { \ +#define _umips_dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo0(x) \ -do { \ +#define _umips_dsp_mtxxx(val, ins) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (ins)); \ +}) -#define mtlo1(x) \ -do { \ +#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) +#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) + +#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) +#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) + +#define mflo0() _umips_dsp_mflo(0) +#define mflo1() _umips_dsp_mflo(1) +#define mflo2() _umips_dsp_mflo(2) +#define mflo3() _umips_dsp_mflo(3) + +#define mfhi0() _umips_dsp_mfhi(0) +#define mfhi1() _umips_dsp_mfhi(1) +#define mfhi2() _umips_dsp_mfhi(2) +#define mfhi3() _umips_dsp_mfhi(3) + +#define mtlo0(x) _umips_dsp_mtlo(x, 0) +#define mtlo1(x) _umips_dsp_mtlo(x, 1) +#define mtlo2(x) _umips_dsp_mtlo(x, 2) +#define mtlo3(x) _umips_dsp_mtlo(x, 3) + +#define mthi0(x) _umips_dsp_mthi(x, 0) +#define mthi1(x) _umips_dsp_mthi(x, 1) +#define mthi2(x) _umips_dsp_mthi(x, 2) +#define mthi3(x) _umips_dsp_mthi(x, 3) + +#else /* !CONFIG_CPU_MICROMIPS */ +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (mask)); \ +}) -#define mtlo2(x) \ -do { \ +#define _dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ + " .word (0x00000810 | %1) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo3(x) \ -do { \ +#define _dsp_mtxxx(val, ins) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ + " .word (0x00200011 | %1) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (ins)); \ +}) + +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) + +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) + +#define mflo0() _dsp_mflo(0) +#define mflo1() _dsp_mflo(1) +#define mflo2() _dsp_mflo(2) +#define mflo3() _dsp_mflo(3) + +#define mfhi0() _dsp_mfhi(0) +#define mfhi1() _dsp_mfhi(1) +#define mfhi2() _dsp_mfhi(2) +#define mfhi3() _dsp_mfhi(3) + +#define mtlo0(x) _dsp_mtlo(x, 0) +#define mtlo1(x) _dsp_mtlo(x, 1) +#define mtlo2(x) _dsp_mtlo(x, 2) +#define mtlo3(x) _dsp_mtlo(x, 3) + +#define mthi0(x) _dsp_mthi(x, 0) +#define mthi1(x) _dsp_mthi(x, 1) +#define mthi2(x) _dsp_mthi(x, 2) +#define mthi3(x) _dsp_mthi(x, 3) + +#endif /* CONFIG_CPU_MICROMIPS */ +#endif /* * TLB operations. @@ -1324,11 +1933,11 @@ static inline void tlb_write_random(void) static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ \ return res; \ } \ @@ -1336,24 +1945,24 @@ set_c0_##name(unsigned int set) \ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int val) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (val & change); \ + write_c0_##name(new); \ \ return res; \ } @@ -1361,9 +1970,27 @@ change_c0_##name(unsigned int change, unsigned int new) \ __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) +__BUILD_SET_C0(config5) __BUILD_SET_C0(intcontrol) __BUILD_SET_C0(intctl) __BUILD_SET_C0(srsmap) +__BUILD_SET_C0(pagegrain) +__BUILD_SET_C0(brcm_config_0) +__BUILD_SET_C0(brcm_bus_pll) +__BUILD_SET_C0(brcm_reset) +__BUILD_SET_C0(brcm_cmt_intr) +__BUILD_SET_C0(brcm_cmt_ctrl) +__BUILD_SET_C0(brcm_config) +__BUILD_SET_C0(brcm_mode) + +/* + * Return low 10 bits of ebase. + * Note that under KVM (MIPSVZ) this returns vcpu id. + */ +static inline unsigned int get_ebase_cpunum(void) +{ + return read_c0_ebase() & 0x3ff; +} #endif /* !__ASSEMBLY__ */ diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h new file mode 100644 index 00000000000..9e5fa98d1c8 --- /dev/null +++ b/arch/mips/include/asm/pgtable-bits.h @@ -0,0 +1,283 @@ +/* + * Copyright (C) 1994 - 2002 by Ralf Baechle + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _ASM_PGTABLE_BITS_H +#define _ASM_PGTABLE_BITS_H + + +/* + * Note that we shift the lower 32bits of each EntryLo[01] entry + * 6 bits to the left. That way we can convert the PFN into the + * physical address by a single 'and' operation and gain 6 additional + * bits for storing information which isn't present in a normal + * MIPS page table. + * + * Similar to the Alpha port, we need to keep track of the ref + * and mod bits in software. We have a software "yeah you can read + * from this page" bit, and a hardware one which actually lets the + * process read from the page. On the same token we have a software + * writable bit and the real hardware one which actually lets the + * process write to the page, this keeps a mod bit via the hardware + * dirty bit. + * + * Certain revisions of the R4000 and R5000 have a bug where if a + * certain sequence occurs in the last 3 instructions of an executable + * page, and the following page is not mapped, the cpu can do + * unpredictable things. The code (when it is written) to deal with + * this problem will be in the update_mmu_cache() code for the r4k. + */ +#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) + +/* + * The following bits are implemented by the TLB hardware + */ +#define _PAGE_NO_EXEC_SHIFT 0 +#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) +#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) +#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_MASK (7 << _CACHE_SHIFT) + +/* + * The following bits are implemented in software + */ +#define _PAGE_PRESENT_SHIFT (24) +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ (1 << _PAGE_READ_SHIFT) +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) + +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) + +/* + * Bits for extended EntryLo0/EntryLo1 registers + */ +#define _PFNX_MASK 0xffffff + +#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +/* + * The following bits are implemented in software + */ +#define _PAGE_PRESENT_SHIFT (0) +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ (1 << _PAGE_READ_SHIFT) +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) + +/* + * The following bits are implemented by the TLB hardware + */ +#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4) +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) +#define _CACHE_MASK _CACHE_UNCACHED + +#define _PFN_SHIFT PAGE_SHIFT + +#else +/* + * Below are the "Normal" R4K cases + */ + +/* + * The following bits are implemented in software + */ +#define _PAGE_PRESENT_SHIFT 0 +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +/* R2 or later cores check for RI/XI support to determine _PAGE_READ */ +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) +#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#else +#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ (1 << _PAGE_READ_SHIFT) +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#endif +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) + +#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) +/* Huge TLB page */ +#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) +#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) +#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) +#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ + +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) +/* XI - page cannot be executed */ +#ifdef _PAGE_SPLITTING_SHIFT +#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) +#else +#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#endif +#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) + +/* RI - page cannot be read */ +#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) +#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) +#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT +#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) +#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */ + +#if defined(_PAGE_NO_READ_SHIFT) +#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) +#elif defined(_PAGE_SPLITTING_SHIFT) +#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) +#else +#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#endif +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) + +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_MASK (7 << _CACHE_SHIFT) + +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) + +#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ + +#ifndef _PAGE_NO_EXEC +#define _PAGE_NO_EXEC 0 +#endif +#ifndef _PAGE_NO_READ +#define _PAGE_NO_READ 0 +#endif + +#define _PAGE_SILENT_READ _PAGE_VALID +#define _PAGE_SILENT_WRITE _PAGE_DIRTY + +#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) + +/* + * The final layouts of the PTE bits are: + * + * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P + * 32-bit, R1 or earler: CCC D V G M A W R P + * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P + * 32-bit, R2 or later: CCC D V G RI/R XI M A W P + */ + + +#ifndef __ASSEMBLY__ +/* + * pte_to_entrylo converts a page table entry (PTE) into a Mips + * entrylo0/1 value. + */ +static inline uint64_t pte_to_entrylo(unsigned long pte_val) +{ +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) + if (cpu_has_rixi) { + int sa; +#ifdef CONFIG_32BIT + sa = 31 - _PAGE_NO_READ_SHIFT; +#else + sa = 63 - _PAGE_NO_READ_SHIFT; +#endif + /* + * C has no way to express that this is a DSRL + * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily + * in the fast path this is done in assembly + */ + return (pte_val >> _PAGE_GLOBAL_SHIFT) | + ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); + } +#endif + + return pte_val >> _PAGE_GLOBAL_SHIFT; +} +#endif + +/* + * Cache attributes + */ +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +#define _CACHE_CACHABLE_NONCOHERENT 0 +#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED + +#elif defined(CONFIG_CPU_SB1) + +/* No penalty for being coherent on the SB1, so just + use it for "noncoherent" spaces, too. Shouldn't hurt. */ + +#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) + +#elif defined(CONFIG_CPU_LOONGSON3) + +/* Using COHERENT flag for NONCOHERENT doesn't hurt. */ + +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ + +#elif defined(CONFIG_MACH_INGENIC) + +/* Ingenic uses the WA bit to achieve write-combine memory writes */ +#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) + +#endif + +#ifndef _CACHE_CACHABLE_NO_WA +#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_WA +#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_UNCACHED +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_NONCOHERENT +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_CE +#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_COW +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_CUW +#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_UNCACHED_ACCELERATED +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) +#endif + +#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) + +#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ + _PFN_MASK | _CACHE_MASK) + +#endif /* _ASM_PGTABLE_BITS_H */ diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 4deac5207aa..90c0affdee3 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -1,10 +1,7 @@ -/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * +/* * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POSIX_TYPES_H #define _ASM_POSIX_TYPES_H diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index ba7f5381a3a..02a3b167f53 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -1,12 +1,10 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994 Waldorf GMBH * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 5659c0c873a..da051f6e10b 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -1,35 +1,27 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ -#define FPR_BASE 32 -#define PC 64 -#define CAUSE 65 -#define BADVADDR 66 -#define MMHI 67 -#define MMLO 68 -#define FPC_CSR 69 -#define FPC_EIR 70 -#define DSP_BASE 71 /* 3 more hi / lo register pairs */ -#define DSP_CONTROL 77 -#define ACX 78 +#include <linux/compiler.h> +#include <linux/types.h> +#include <asm/isadep.h> /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. + * + * If you add a register here, also add it to regoffset_table[] in + * arch/mips/kernel/ptrace.c. */ struct pt_regs { #ifdef CONFIG_32BIT /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[6]; + unsigned long pad0[8]; #endif /* Saved main processor registers. */ @@ -45,34 +37,50 @@ struct pt_regs { unsigned long cp0_badvaddr; unsigned long cp0_cause; unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -} __attribute__ ((aligned (8))); +#ifdef CONFIG_CPU_CAVIUM_OCTEON + unsigned long long mpl[6]; /* MTM{0-5} */ + unsigned long long mtp[6]; /* MTP{0-5} */ +#endif + unsigned long __last[0]; +} __aligned(8); -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -/* #define PTRACE_GETFPXREGS 18 */ -/* #define PTRACE_SETFPXREGS 19 */ +static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +{ + return regs->regs[31]; +} -#define PTRACE_OLDSETOPTIONS 21 +/* + * Don't use asm-generic/ptrace.h it defines FP accessors that don't make + * sense on MIPS. We rather want an error if they get invoked. + */ -#define PTRACE_GET_THREAD_AREA 25 -#define PTRACE_SET_THREAD_AREA 26 +static inline void instruction_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->cp0_epc = val; +} -/* Calls to trace a 64bit program from a 32bit program. */ -#define PTRACE_PEEKTEXT_3264 0xc0 -#define PTRACE_PEEKDATA_3264 0xc1 -#define PTRACE_POKETEXT_3264 0xc2 -#define PTRACE_POKEDATA_3264 0xc3 -#define PTRACE_GET_THREAD_AREA_3264 0xc4 +/* Query offset/name of register from its name/offset */ +extern int regs_query_register_offset(const char *name); +#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last)) -#ifdef __KERNEL__ +/** + * regs_get_register() - get register value from its offset + * @regs: pt_regs from which register value is gotten. + * @offset: offset number of the register. + * + * regs_get_register returns the value of a register. The @offset is the + * offset of the register in struct pt_regs address which specified by @regs. + * If @offset is bigger than MAX_REG_OFFSET, this returns 0. + */ +static inline unsigned long regs_get_register(struct pt_regs *regs, + unsigned int offset) +{ + if (unlikely(offset > MAX_REG_OFFSET)) + return 0; -#include <asm/isadep.h> + return *(unsigned long *)((unsigned long)regs + offset); +} /* * Does the process account for user or for system time? @@ -82,6 +90,17 @@ struct pt_regs { #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) -#endif +/* Helpers for working with the user stack pointer */ + +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->regs[29]; +} + +static inline void user_stack_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->regs[29] = val; +} #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h index 978d2068163..2a6b7244e7e 100644 --- a/arch/mips/include/asm/reboot.h +++ b/arch/mips/include/asm/reboot.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_REBOOT_H #define _ASM_REBOOT_H diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h index fc6bc0c169e..af6fbb469e7 100644 --- a/arch/mips/include/asm/reg.h +++ b/arch/mips/include/asm/reg.h @@ -2,12 +2,10 @@ * Various register offset definitions for debuggers, core file * examiners and whatnot. * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1995, 1999 by Ralf Baechle * Copyright (C) 1995, 1999 Silicon Graphics + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_MIPS_REG_H #define __ASM_MIPS_REG_H diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h index 2e65cc3c438..f1efc457915 100644 --- a/arch/mips/include/asm/regdef.h +++ b/arch/mips/include/asm/regdef.h @@ -1,11 +1,11 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1985 MIPS Computer Systems, Inc. * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. + * Copyright (C) 2011 Wind River Systems, + * written by Ralf Baechle <ralf@linux-mips.org> + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_REGDEF_H #define _ASM_REGDEF_H @@ -30,9 +30,13 @@ #define t2 $10 #define t3 $11 #define t4 $12 +#define ta0 $12 #define t5 $13 +#define ta1 $13 #define t6 $14 +#define ta2 $14 #define t7 $15 +#define ta3 $15 #define s0 $16 /* callee saved */ #define s1 $17 #define s2 $18 diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h index 67f26589583..2a0388652ad 100644 --- a/arch/mips/include/asm/sgidefs.h +++ b/arch/mips/include/asm/sgidefs.h @@ -1,11 +1,9 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 1999, 2001 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SGIDEFS_H #define __ASM_SGIDEFS_H diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h index 579a591e629..1fbe899aaa8 100644 --- a/arch/mips/include/asm/string.h +++ b/arch/mips/include/asm/string.h @@ -1,11 +1,9 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle * Copyright (c) 2000 by Silicon Graphics, Inc. * Copyright (c) 2001 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_STRING_H #define _ASM_STRING_H diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index d56f73b8b8e..e6435cce294 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -1,8 +1,4 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994 - 1999 by Ralf Baechle * Copyright (C) 1996 by Paul M. Antoine * Copyright (C) 1994 - 1999 by Ralf Baechle @@ -12,6 +8,8 @@ * * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SYSTEM_H #define _ASM_SYSTEM_H diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index aebafdbba1b..627440dc24c 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h index c25a8462c72..eebe06a9c91 100644 --- a/arch/mips/include/asm/unaligned.h +++ b/arch/mips/include/asm/unaligned.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_MIPS_UNALIGNED_H #define _ASM_MIPS_UNALIGNED_H diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index e245614d168..bf8ff598acd 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -27,7 +27,7 @@ static inline unsigned long icache_line_size(void) { unsigned long conf1, il; conf1 = read_c0_config1(); - il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT; + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; if (!il) return 0; return 2 << il; @@ -37,7 +37,7 @@ static inline unsigned long dcache_line_size(void) { unsigned long conf1, dl; conf1 = read_c0_config1(); - dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT; + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; if (!dl) return 0; return 2 << dl; diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 137d7283ffe..14cc2c49fda 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -54,24 +54,24 @@ mfc0 $1, CP0_CONFIG, 1 /* detect line size */ - srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT - andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) + srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF + andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF) move \sz, zero beqz \line_sz, 10f li \sz, 2 sllv \line_sz, \sz, \line_sz /* detect associativity */ - srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT - andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) + srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF + andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF) addi \sz, \sz, 1 /* sz *= line_sz */ mul \sz, \sz, \line_sz /* detect log32(sets) */ - srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT - andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) + srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF + andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF) addiu $1, $1, 1 andi $1, $1, 0x7 @@ -103,14 +103,14 @@ LEAF(mips_cache_reset) li t2, CONFIG_SYS_ICACHE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE #else - l1_info t2, t8, MIPS_CONF1_IA_SHIFT + l1_info t2, t8, MIPS_CONF1_IA_SHF #endif #ifdef CONFIG_SYS_DCACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t9, CONFIG_SYS_CACHELINE_SIZE #else - l1_info t3, t9, MIPS_CONF1_DA_SHIFT + l1_info t3, t9, MIPS_CONF1_DA_SHF #endif #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c index d6ebe076434..921686081ff 100644 --- a/arch/mips/mach-au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -43,7 +43,7 @@ #include <net.h> #include <command.h> #include <asm/io.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #if defined(CONFIG_CMD_MII) #include <miiphy.h> @@ -279,7 +279,7 @@ int au1x00_enet_initialize(bd_t *bis){ memset(dev, 0, sizeof *dev); - sprintf(dev->name, "Au1X00 ethernet"); + strcpy(dev->name, "Au1X00 ethernet"); dev->iobase = 0; dev->priv = 0; dev->init = au1x00_init; diff --git a/arch/mips/mach-au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c index 046350826a9..47845049bb9 100644 --- a/arch/mips/mach-au1x00/au1x00_serial.c +++ b/arch/mips/mach-au1x00/au1x00_serial.c @@ -11,7 +11,7 @@ #include <config.h> #include <common.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <serial.h> #include <linux/compiler.h> diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c index 74bdb773032..42484e57121 100644 --- a/arch/mips/mach-au1x00/au1x00_usb_ohci.c +++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.c @@ -23,7 +23,7 @@ #include <common.h> #include <malloc.h> #include <asm/io.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <usb.h> #include "au1x00_usb_ohci.h" diff --git a/arch/mips/include/asm/au1x00.h b/arch/mips/mach-au1x00/include/mach/au1x00.h index f76c4c3160f..f76c4c3160f 100644 --- a/arch/mips/include/asm/au1x00.h +++ b/arch/mips/mach-au1x00/include/mach/au1x00.h diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 54787c53ca7..204d0cd9d4a 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -106,14 +106,18 @@ _reloc: stw r0, 4(sp) mov fp, sp - /* Allocate and zero GD, update SP */ + /* Allocate and initialize reserved area, update SP */ mov r4, sp - movhi r2, %hi(board_init_f_mem@h) - ori r2, r2, %lo(board_init_f_mem@h) + movhi r2, %hi(board_init_f_alloc_reserve@h) + ori r2, r2, %lo(board_init_f_alloc_reserve@h) callr r2 - - /* Update stack- and frame-pointers */ mov sp, r2 + mov r4, sp + movhi r2, %hi(board_init_f_init_reserve@h) + ori r2, r2, %lo(board_init_f_init_reserve@h) + callr r2 + + /* Update frame-pointer */ mov fp, sp /* Call board_init_f -- never returns */ diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c index 5ba8bed20db..fff8f2b8d3e 100644 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ b/arch/powerpc/cpu/mpc8260/ether_scc.c @@ -355,7 +355,7 @@ int mpc82xx_scc_enet_initialize(bd_t *bis) dev = (struct eth_device *) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "SCC"); + strcpy(dev->name, "SCC"); dev->init = sec_init; dev->halt = sec_halt; dev->send = sec_send; diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index 262ae7f711a..997aea488ff 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -1,9 +1,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 26a65c586d5..dd99155a28d 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,9 +1,7 @@ /* * Copyright 2008, 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 2e196033c24..ea4ab3a0423 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -148,7 +148,7 @@ int fec_initialize(bd_t *bis) /* for FEC1 make sure that the name of the interface is the same as the old one for compatibility reasons */ if (i == 0) { - sprintf (dev->name, "FEC"); + strcpy(dev->name, "FEC"); } else { sprintf (dev->name, "FEC%d", ether_fcc_info[i].ether_index + 1); diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 549844032be..3474637fac9 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -77,7 +77,7 @@ int scc_initialize(bd_t *bis) dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "SCC"); + strcpy(dev->name, "SCC"); dev->iobase = 0; dev->priv = 0; dev->init = scc_init; diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 15cee3fd4a1..c35406d37b5 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -981,11 +981,11 @@ static void *video_logo (void) U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info); - sprintf (info, "(C) 2002 DENX Software Engineering"); + strcpy(info, "(C) 2002 DENX Software Engineering"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, info); - sprintf (info, " Wolfgang DENK, wd@denx.de"); + strcpy(info, " Wolfgang DENK, wd@denx.de"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, info); diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index c1fe5790a31..728a35130cf 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -1,9 +1,7 @@ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 3dd0557aa66..137afce37a8 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -762,8 +762,9 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ #ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 - bl board_init_f_mem + bl board_init_f_alloc_reserve mr r1, r3 + bl board_init_f_init_reserve li r0,0 stwu r0, -4(r1) stwu r0, -4(r1) @@ -1038,8 +1039,9 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ #ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 - bl board_init_f_mem + bl board_init_f_alloc_reserve mr r1, r3 + bl board_init_f_init_reserve stwu r0, -4(r1) stwu r0, -4(r1) #endif diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 11641912a65..9e46e22a1bd 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -3,23 +3,7 @@ * * Copyright 2006 Freescale Semiconductor, Inc. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FSL_DMA_H_ diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h index d6537fd6331..cbbc8342735 100644 --- a/arch/powerpc/include/asm/fsl_i2c.h +++ b/arch/powerpc/include/asm/fsl_i2c.h @@ -8,23 +8,7 @@ * and Jeff Brown. * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FSL_I2C_H_ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 8e1d22adef3..2a759c85b85 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _FSL_LAW_H_ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index b0082affd38..c8da8b23479 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -3,23 +3,7 @@ * * Copyright 2008 Qstreams Networks, Inc. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_MPC8XXX_SPI_H_ diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index 528865f5d3f..ab64f6e2109 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -198,7 +198,8 @@ int sandbox_eth_raw_os_send(void *packet, int length, addr.sin_family = AF_INET; addr.sin_port = udph->source; addr.sin_addr.s_addr = iph->saddr; - retval = bind(priv->local_bind_sd, &addr, sizeof(addr)); + retval = bind(priv->local_bind_sd, (struct sockaddr *)&addr, + sizeof(addr)); if (retval < 0) printf("Failed to bind: %d %s\n", errno, strerror(errno)); diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h index 85a530050e6..c0960575479 100644 --- a/arch/sh/include/asm/mmc.h +++ b/arch/sh/include/asm/mmc.h @@ -4,9 +4,7 @@ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * Copyright (C) 2012 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. + * SPDX-License-Identifier: GPL-2.0 * */ #ifndef _SH_MMC_H_ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7e7cb612d7c..f07567c81ac 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -242,6 +242,15 @@ config FSP_SYS_MALLOC_F_LEN help Additional size of malloc() pool before relocation. +config FSP_USE_UPD + bool + depends on HAVE_FSP + default y + help + Most FSPs use UPD data region for some FSP customization. But there + are still some FSPs that might not even have UPD. For such FSPs, + override this to n in their platform Kconfig files. + config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index a72d615f21f..d49b8d27371 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -121,16 +121,23 @@ const struct pch_azalia_config azalia_config = { }; /** - * Override the FSP's UPD. + * Override the FSP's configuration data. * If the device tree does not specify an integer setting, use the default * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. */ -void update_fsp_upd(struct upd_region *fsp_upd) +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) { + struct upd_region *fsp_upd = &config->fsp_upd; struct memory_down_data *mem; const void *blob = gd->fdt_blob; int node; + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 56abd8fae35..1768a26a352 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select HAVE_INTEL_ME select X86_RAMTEST config SMM_TSEG_SIZE diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 4334f5b3e5a..7917350bff2 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -20,8 +20,11 @@ #include <asm/mtrr.h> #include <asm/processor.h> #include <asm/sipi.h> +#include <asm/fw_cfg.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> +#include <dm/lists.h> +#include <dm/root.h> #include <linux/linkage.h> DECLARE_GLOBAL_DATA_PTR; @@ -104,7 +107,7 @@ static void ap_do_flight_plan(struct udevice *cpu) } } -static int find_cpu_by_apid_id(int apic_id, struct udevice **devp) +static int find_cpu_by_apic_id(int apic_id, struct udevice **devp) { struct udevice *dev; @@ -137,7 +140,7 @@ static void ap_init(unsigned int cpu_index) enable_lapic(); apic_id = lapicid(); - ret = find_cpu_by_apid_id(apic_id, &dev); + ret = find_cpu_by_apic_id(apic_id, &dev); if (ret) { debug("Unknown CPU apic_id %x\n", apic_id); goto done; @@ -210,7 +213,7 @@ static int save_bsp_msrs(char *start, int size) return msr_count; } -static int load_sipi_vector(atomic_t **ap_countp) +static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) { struct sipi_params_16bit *params16; struct sipi_params *params; @@ -239,7 +242,7 @@ static int load_sipi_vector(atomic_t **ap_countp) params->idt_ptr = (uint32_t)x86_get_idt(); params->stack_size = CONFIG_AP_STACK_SIZE; - size = params->stack_size * CONFIG_MAX_CPUS; + size = params->stack_size * num_cpus; stack = memalign(size, 4096); if (!stack) return -ENOMEM; @@ -432,7 +435,7 @@ static int init_bsp(struct udevice **devp) lapic_setup(); apic_id = lapicid(); - ret = find_cpu_by_apid_id(apic_id, devp); + ret = find_cpu_by_apic_id(apic_id, devp); if (ret) { printf("Cannot find boot CPU, APIC ID %d\n", apic_id); return ret; @@ -441,6 +444,69 @@ static int init_bsp(struct udevice **devp) return 0; } +#ifdef CONFIG_QEMU +static int qemu_cpu_fixup(void) +{ + int ret; + int cpu_num; + int cpu_online; + struct udevice *dev, *pdev; + struct cpu_platdata *plat; + char *cpu; + + /* first we need to find '/cpus' */ + for (device_find_first_child(dm_root(), &pdev); + pdev; + device_find_next_child(&pdev)) { + if (!strcmp(pdev->name, "cpus")) + break; + } + if (!pdev) { + printf("unable to find cpus device\n"); + return -ENODEV; + } + + /* calculate cpus that are already bound */ + cpu_num = 0; + for (uclass_find_first_device(UCLASS_CPU, &dev); + dev; + uclass_find_next_device(&dev)) { + cpu_num++; + } + + /* get actual cpu number */ + cpu_online = qemu_fwcfg_online_cpus(); + if (cpu_online < 0) { + printf("unable to get online cpu number: %d\n", cpu_online); + return cpu_online; + } + + /* bind addtional cpus */ + dev = NULL; + for (; cpu_num < cpu_online; cpu_num++) { + /* + * allocate device name here as device_bind_driver() does + * not copy device name, 8 bytes are enough for + * sizeof("cpu@") + 3 digits cpu number + '\0' + */ + cpu = malloc(8); + if (!cpu) { + printf("unable to allocate device name\n"); + return -ENOMEM; + } + sprintf(cpu, "cpu@%d", cpu_num); + ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev); + if (ret) { + printf("binding cpu@%d failed: %d\n", cpu_num, ret); + return ret; + } + plat = dev_get_parent_platdata(dev); + plat->cpu_id = cpu_num; + } + return 0; +} +#endif + int mp_init(struct mp_params *p) { int num_aps; @@ -454,6 +520,12 @@ int mp_init(struct mp_params *p) if (ret) return ret; +#ifdef CONFIG_QEMU + ret = qemu_cpu_fixup(); + if (ret) + return ret; +#endif + ret = init_bsp(&cpu); if (ret) { debug("Cannot init boot CPU: err=%d\n", ret); @@ -483,7 +555,7 @@ int mp_init(struct mp_params *p) mp_info.records = p->flight_plan; /* Load the SIPI vector */ - ret = load_sipi_vector(&ap_count); + ret = load_sipi_vector(&ap_count, num_cpus); if (ap_count == NULL) return -1; diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 3f3958aa8e1..176ea54ae4e 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -7,5 +7,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif -obj-y += qemu.o +obj-y += cpu.o fw_cfg.o qemu.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c new file mode 100644 index 00000000000..a1b70c6bde7 --- /dev/null +++ b/arch/x86/cpu/qemu/cpu.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <errno.h> +#include <asm/cpu.h> +#include <asm/fw_cfg.h> + +DECLARE_GLOBAL_DATA_PTR; + +int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size) +{ + if (size < CPU_MAX_NAME_LEN) + return -ENOSPC; + + cpu_get_name(buf); + + return 0; +} + +static int cpu_qemu_get_count(struct udevice *dev) +{ + return qemu_fwcfg_online_cpus(); +} + +static const struct cpu_ops cpu_qemu_ops = { + .get_desc = cpu_qemu_get_desc, + .get_count = cpu_qemu_get_count, +}; + +static const struct udevice_id cpu_qemu_ids[] = { + { .compatible = "cpu-qemu" }, + { } +}; + +U_BOOT_DRIVER(cpu_qemu_drv) = { + .name = "cpu_qemu", + .id = UCLASS_CPU, + .of_match = cpu_qemu_ids, + .ops = &cpu_qemu_ops, +}; diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c new file mode 100644 index 00000000000..05992145cf0 --- /dev/null +++ b/arch/x86/cpu/qemu/fw_cfg.c @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/fw_cfg.h> + +static bool fwcfg_present; +static bool fwcfg_dma_present; + +/* Read configuration item using fw_cfg PIO interface */ +static void qemu_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +/* Read configuration item using fw_cfg DMA interface */ +static void qemu_fwcfg_read_entry_dma(uint16_t entry, + uint32_t size, void *address) +{ + struct fw_cfg_dma_access dma; + + dma.length = cpu_to_be32(size); + dma.address = cpu_to_be64((uintptr_t)address); + dma.control = cpu_to_be32(FW_CFG_DMA_READ); + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); + + barrier(); + + debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", + address, size, be32_to_cpu(dma.control)); + + outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static bool qemu_fwcfg_present(void) +{ + uint32_t qemu; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; +} + +static bool qemu_fwcfg_dma_present(void) +{ + uint8_t dma_enabled; + + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & FW_CFG_DMA_ENABLED) + return true; + + return false; +} + +static void qemu_fwcfg_read_entry(uint16_t entry, + uint32_t length, void *address) +{ + if (fwcfg_dma_present) + qemu_fwcfg_read_entry_dma(entry, length, address); + else + qemu_fwcfg_read_entry_pio(entry, length, address); +} + +int qemu_fwcfg_online_cpus(void) +{ + uint16_t nb_cpus; + + if (!fwcfg_present) + return -ENODEV; + + qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); + + return le16_to_cpu(nb_cpus); +} + +/* + * This function prepares kernel for zboot. It loads kernel data + * to 'load_addr', initrd to 'initrd_addr' and kernel command + * line using qemu fw_cfg interface. + */ +static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) +{ + char *data_addr; + uint32_t setup_size, kernel_size, cmdline_size, initrd_size; + + qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); + qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); + + if (setup_size == 0 || kernel_size == 0) { + printf("warning: no kernel available\n"); + return -1; + } + + data_addr = load_addr; + qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, + le32_to_cpu(setup_size), data_addr); + data_addr += le32_to_cpu(setup_size); + + qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, + le32_to_cpu(kernel_size), data_addr); + data_addr += le32_to_cpu(kernel_size); + + data_addr = initrd_addr; + qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); + if (initrd_size == 0) { + printf("warning: no initrd available\n"); + } else { + qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, + le32_to_cpu(initrd_size), data_addr); + data_addr += le32_to_cpu(initrd_size); + } + + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); + if (cmdline_size) { + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, + le32_to_cpu(cmdline_size), data_addr); + /* + * if kernel cmdline only contains '\0', (e.g. no -append + * when invoking qemu), do not update bootargs + */ + if (*data_addr != '\0') { + if (setenv("bootargs", data_addr) < 0) + printf("warning: unable to change bootargs\n"); + } + } + + printf("loading kernel to address %p size %x", load_addr, + le32_to_cpu(kernel_size)); + if (initrd_size) + printf(" initrd %p size %x\n", + initrd_addr, + le32_to_cpu(initrd_size)); + else + printf("\n"); + + return 0; +} + +static int qemu_fwcfg_list_firmware(void) +{ + int i; + uint32_t count; + struct fw_cfg_files *files; + + qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); + if (!count) + return 0; + + count = be32_to_cpu(count); + files = malloc(count * sizeof(struct fw_cfg_file)); + if (!files) + return -ENOMEM; + + files->count = count; + qemu_fwcfg_read_entry(FW_CFG_INVALID, + count * sizeof(struct fw_cfg_file), + files->files); + + for (i = 0; i < files->count; i++) + printf("%-56s\n", files->files[i].name); + free(files); + return 0; +} + +void qemu_fwcfg_init(void) +{ + fwcfg_present = qemu_fwcfg_present(); + if (fwcfg_present) + fwcfg_dma_present = qemu_fwcfg_dma_present(); +} + +static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + if (qemu_fwcfg_list_firmware() < 0) + return CMD_RET_FAILURE; + + return 0; +} + +static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int ret = qemu_fwcfg_online_cpus(); + if (ret < 0) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_FAILURE; + } + + printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); + + return 0; +} + +static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + char *env; + void *load_addr; + void *initrd_addr; + + env = getenv("loadaddr"); + load_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_LOADADDR; + + env = getenv("ramdiskaddr"); + initrd_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_RAMDISK_ADDR; + + if (argc == 2) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); + } else if (argc == 1) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + } + + return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); +} + +static cmd_tbl_t fwcfg_commands[] = { + U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), + U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), + U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), +}; + +static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + cmd_tbl_t *fwcfg_cmd; + + if (!fwcfg_present) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_USAGE; + } + + fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, + ARRAY_SIZE(fwcfg_commands)); + argc -= 2; + argv += 2; + if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) + return CMD_RET_USAGE; + + ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); + + return cmd_process_error(fwcfg_cmd, ret); +} + +U_BOOT_CMD( + qfw, 4, 1, do_qemu_fw, + "QEMU firmware interface", + "<command>\n" + " - list : print firmware(s) currently loaded\n" + " - cpus : print online cpu number\n" + " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n" +) diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 1f93f72dc8d..46111c9cf05 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> +#include <asm/fw_cfg.h> static bool i440fx; @@ -57,6 +58,8 @@ static void qemu_chipset_init(void) x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, CONFIG_PCIE_ECAM_BASE | BAR_EN); } + + qemu_fwcfg_init(); } int arch_cpu_init(void) diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 37ce3940b08..72c681dceab 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -252,17 +252,6 @@ int arch_cpu_init(void) */ quark_setup_bars(); - /* - * Initialize PCIe controller - * - * Quark SoC holds the PCIe controller in reset following a power on. - * U-Boot needs to release the PCIe controller from reset. The PCIe - * controller (D23:F0/F1) will not be visible in PCI configuration - * space and any access to its PCI configuration registers will cause - * system hang while it is held in reset. - */ - quark_pcie_early_init(); - /* Initialize USB2 PHY */ quark_usb_early_init(); @@ -277,6 +266,22 @@ int arch_cpu_init(void) return 0; } +int arch_cpu_init_dm(void) +{ + /* + * Initialize PCIe controller + * + * Quark SoC holds the PCIe controller in reset following a power on. + * U-Boot needs to release the PCIe controller from reset. The PCIe + * controller (D23:F0/F1) will not be visible in PCI configuration + * space and any access to its PCI configuration registers will cause + * system hang while it is held in reset. + */ + quark_pcie_early_init(); + + return 0; +} + int print_cpuinfo(void) { post_code(POST_CPU_INFO); diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 78bc966bbd0..f83bb5f2214 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -8,13 +8,13 @@ #include <common.h> #include <asm/fsp/fsp_support.h> -void update_fsp_upd(struct upd_region *fsp_upd) +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) { - /* Override any UPD setting if required */ - - /* Uncomment the line below to enable DEBUG message */ - /* fsp_upd->serial_dbgport_type = 1; */ + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; - /* Examples on how to initialize the pointers in UPD region */ - /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */ + /* Override any UPD setting if required */ } diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 5b4ee79d884..485868ff576 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -123,8 +123,9 @@ car_init_ret: #endif /* Set up global data */ mov %esp, %eax - call board_init_f_mem + call board_init_f_alloc_reserve mov %eax, %esp + call board_init_f_init_reserve #ifdef CONFIG_DEBUG_UART call debug_uart_init diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi new file mode 100644 index 00000000000..6b35c39f8fe --- /dev/null +++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi @@ -0,0 +1,554 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x8>; +intel,date-code = <0x5182011>; +intel,processor-signature = <0x306a2>; +intel,checksum = <0xa0e51feb>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x08000000 0x11201805 0xa2060300 + 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000 + 0x00200000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x08000000 + 0x00000000 0x00000000 0x17051120 0xd1070000 + 0x01000000 0xa2060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e + 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi new file mode 100644 index 00000000000..c39fbd3cdf8 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9082011>; +intel,processor-signature = <0x306a4>; +intel,checksum = <0x7e23e5af>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200809 0xa4060300 + 0xafe5237e 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x07091120 0xd1080000 + 0x01000000 0xa4060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d + 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a5_00000007.dtsi new file mode 100644 index 00000000000..de5037252b1 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9092011>; +intel,processor-signature = <0x306a5>; +intel,checksum = <0x8e38731>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200909 0xa5060300 + 0x3187e308 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x08091120 0x71080000 + 0x01000000 0xa5060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631 + 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a8_00000010.dtsi new file mode 100644 index 00000000000..0672ff1af0a --- /dev/null +++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi @@ -0,0 +1,682 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x10>; +intel,date-code = <0x2202012>; +intel,processor-signature = <0x306a8>; +intel,checksum = <0xe44a4ef2>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x10000000 0x12202002 0xa8060300 + 0xf24e4ae4 0x01000000 0x12000000 0xd0270000 + 0x00280000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x10000000 + 0x00000000 0x00000000 0x17021220 0xe1090000 + 0x01000000 0xa8060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6 + 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -32,17 +32,10 @@ cpu@0 { device_type = "cpu"; - compatible = "cpu-x86"; + compatible = "cpu-qemu"; reg = <0>; intel,apic-id = <0>; }; - - cpu@1 { - device_type = "cpu"; - compatible = "cpu-x86"; - reg = <1>; - intel,apic-id = <1>; - }; }; tsc-timer { diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 0b685c8b799..145e8115cec 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -43,17 +43,10 @@ cpu@0 { device_type = "cpu"; - compatible = "cpu-x86"; + compatible = "cpu-qemu"; reg = <0>; intel,apic-id = <0>; }; - - cpu@1 { - device_type = "cpu"; - compatible = "cpu-x86"; - reg = <1>; - intel,apic-id = <1>; - }; }; tsc-timer { diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h new file mode 100644 index 00000000000..e539890c337 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h index fcfc1d54425..0cd7a99e2a6 100644 --- a/arch/x86/include/asm/arch-coreboot/timestamp.h +++ b/arch/x86/include/asm/arch-coreboot/timestamp.h @@ -3,18 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __COREBOOT_TIMESTAMP_H__ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083842c..31437c8618d 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GPIO_ROUT 0xb8 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ +#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ @@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) +#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ +#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ +#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ +#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ +#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ +#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ +#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ +#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h new file mode 100644 index 00000000000..e539890c337 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index 2d34d138abd..afafb30c147 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -11,6 +11,16 @@ #include <linux/linkage.h> /* + * FSP common configuration structure. + * This needs to be included in the platform-specific struct fsp_config_data. + */ +struct fsp_cfg_common { + struct fsp_header *fsp_hdr; + u32 stack_top; + u32 boot_mode; +}; + +/* * FspInit continuation function prototype. * Control will be returned to this callback function after FspInit API call. */ @@ -30,7 +40,7 @@ struct common_buf { * Stack top pointer used by the bootloader. The new stack frame will be * set up at this location after FspInit API call. */ - u32 *stack_top; + u32 stack_top; u32 boot_mode; /* Current system boot mode */ void *upd_data; /* User platform configuraiton data region */ u32 reserved[7]; /* Reserved */ diff --git a/arch/x86/include/asm/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h deleted file mode 100644 index 61286ceb469..00000000000 --- a/arch/x86/include/asm/fsp/fsp_platform.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: Intel - */ - -#ifndef __FSP_PLATFORM_H__ -#define __FSP_PLATFORM_H__ - -struct fspinit_rtbuf { - struct common_buf common; /* FSP common runtime data structure */ -}; - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 7317dda9024..61d811f70e0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -13,16 +13,10 @@ #include "fsp_ffs.h" #include "fsp_api.h" #include "fsp_hob.h" -#include "fsp_platform.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" #include <asm/arch/fsp/fsp_vpd.h> - -struct shared_data { - struct fsp_header *fsp_hdr; - u32 *stack_top; - struct upd_region fsp_upd; -}; +#include <asm/arch/fsp/fsp_configs.h> #define FSP_LOWMEM_BASE 0x100000UL #define FSP_HIGHMEM_BASE 0x100000000ULL @@ -49,14 +43,12 @@ void fsp_init_done(void *hob_list); /** * FSP Continuation function * - * @shared_data: Shared data base before stack migration * @status: Always 0 * @hob_list: HOB list pointer * * @retval: Never returns */ -void fsp_continue(struct shared_data *shared_data, u32 status, - void *hob_list); +void fsp_continue(u32 status, void *hob_list); /** * Find FSP header offset in FSP image @@ -199,13 +191,15 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len); void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); /** - * This function overrides the default configurations in the UPD data region. + * This function overrides the default configurations of FSP. * - * @fsp_upd: A pointer to the upd_region data strcture + * @config: A pointer to the FSP configuration data structure + * @rt_buf: A pointer to the FSP runtime buffer data structure * * @return: None */ -void update_fsp_upd(struct upd_region *fsp_upd); +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf); /** * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h new file mode 100644 index 00000000000..fb110fa8e78 --- /dev/null +++ b/arch/x86/include/asm/fw_cfg.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FW_CFG__ +#define __FW_CFG__ + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +enum qemu_fwcfg_items { + FW_CFG_SIGNATURE = 0x00, + FW_CFG_ID = 0x01, + FW_CFG_UUID = 0x02, + FW_CFG_RAM_SIZE = 0x03, + FW_CFG_NOGRAPHIC = 0x04, + FW_CFG_NB_CPUS = 0x05, + FW_CFG_MACHINE_ID = 0x06, + FW_CFG_KERNEL_ADDR = 0x07, + FW_CFG_KERNEL_SIZE = 0x08, + FW_CFG_KERNEL_CMDLINE = 0x09, + FW_CFG_INITRD_ADDR = 0x0a, + FW_CFG_INITRD_SIZE = 0x0b, + FW_CFG_BOOT_DEVICE = 0x0c, + FW_CFG_NUMA = 0x0d, + FW_CFG_BOOT_MENU = 0x0e, + FW_CFG_MAX_CPUS = 0x0f, + FW_CFG_KERNEL_ENTRY = 0x10, + FW_CFG_KERNEL_DATA = 0x11, + FW_CFG_INITRD_DATA = 0x12, + FW_CFG_CMDLINE_ADDR = 0x13, + FW_CFG_CMDLINE_SIZE = 0x14, + FW_CFG_CMDLINE_DATA = 0x15, + FW_CFG_SETUP_ADDR = 0x16, + FW_CFG_SETUP_SIZE = 0x17, + FW_CFG_SETUP_DATA = 0x18, + FW_CFG_FILE_DIR = 0x19, + FW_CFG_FILE_FIRST = 0x20, + FW_CFG_WRITE_CHANNEL = 0x4000, + FW_CFG_ARCH_LOCAL = 0x8000, + FW_CFG_INVALID = 0xffff, +}; + +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) + +#define FW_CFG_MAX_FILE_PATH 56 + +#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') + +#define FW_CFG_DMA_ERROR (1 << 0) +#define FW_CFG_DMA_READ (1 << 1) +#define FW_CFG_DMA_SKIP (1 << 2) +#define FW_CFG_DMA_SELECT (1 << 3) + +#define FW_CFG_DMA_ENABLED (1 << 1) + +struct fw_cfg_file { + __be32 size; + __be16 select; + __be16 reserved; + char name[FW_CFG_MAX_FILE_PATH]; +}; + +struct fw_cfg_files { + __be32 count; + struct fw_cfg_file files[]; +}; + +struct fw_cfg_dma_access { + __be32 control; + __be32 length; + __be64 address; +}; + +/** + * Initialize QEMU fw_cfg interface + */ +void qemu_fwcfg_init(void); + +/** + * Get system cpu number + * + * @return: cpu number in system + */ +int qemu_fwcfg_online_cpus(void); + +#endif diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c index 4959edf11bb..25546638cf6 100644 --- a/arch/x86/lib/fsp/cmd_fsp.c +++ b/arch/x86/lib/fsp/cmd_fsp.c @@ -69,7 +69,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("---|----------|-----------|------|-"); printf("------------------------------------------\n"); while (!end_of_hob(hdr)) { - printf("%-2d | %08x | ", i, (unsigned int)hdr); + printf("%02x | %08x | ", i, (unsigned int)hdr); type = hdr->type; if (type == HOB_TYPE_UNUSED) desc = "*Unused*"; @@ -79,7 +79,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) desc = hob_type[type]; else desc = "*Invalid*"; - printf("%-9s | %-4d | ", desc, hdr->len); + printf("%-9s | %04x | ", desc, hdr->len); if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || type == HOB_TYPE_GUID_EXT) { diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5276ce6ab1a..8479af1d7e4 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -90,8 +90,8 @@ int x86_fsp_init(void) /* * The second time we enter here, adjust the size of malloc() * pool before relocation. Given gd->malloc_base was adjusted - * after the call to board_init_f_mem() in arch/x86/cpu/start.S, - * we should fix up gd->malloc_limit here. + * after the call to board_init_f_init_reserve() in arch/x86/ + * cpu/start.S, we should fix up gd->malloc_limit here. */ gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; } diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 1d48ff4a8e7..875c96a8f19 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -87,42 +87,28 @@ struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) return (struct fsp_header *)fsp; } -void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list) +void fsp_continue(u32 status, void *hob_list) { - u32 stack_len; - u32 stack_base; - u32 stack_top; - post_code(POST_MRC); assert(status == 0); - /* Get the migrated stack in normal memory */ - stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len); - assert(stack_base != 0); - stack_top = stack_base + stack_len - sizeof(u32); - - /* - * Old stack base is stored at the very end of the stack top, - * use it to calculate the migrated shared data base - */ - shared_data = (struct shared_data *)(stack_base + - ((u32)shared_data - *(u32 *)stack_top)); - /* The boot loader main function entry */ fsp_init_done(hob_list); } void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) { - struct shared_data shared_data; + struct fsp_config_data config_data; fsp_init_f init; struct fsp_init_params params; struct fspinit_rtbuf rt_buf; - struct vpd_region *fsp_vpd; struct fsp_header *fsp_hdr; struct fsp_init_params *params_ptr; +#ifdef CONFIG_FSP_USE_UPD + struct vpd_region *fsp_vpd; struct upd_region *fsp_upd; +#endif #ifdef CONFIG_DEBUG_UART setup_early_uart(); @@ -134,14 +120,11 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) panic("Invalid FSP header"); } - fsp_upd = &shared_data.fsp_upd; - memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); - - /* Reserve a gap in stack top */ - rt_buf.common.stack_top = (u32 *)stack_top - 32; - rt_buf.common.boot_mode = boot_mode; - rt_buf.common.upd_data = fsp_upd; + config_data.common.fsp_hdr = fsp_hdr; + config_data.common.stack_top = stack_top; + config_data.common.boot_mode = boot_mode; +#ifdef CONFIG_FSP_USE_UPD /* Get VPD region start */ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + fsp_hdr->cfg_region_off); @@ -149,15 +132,20 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) /* Verify the VPD data region is valid */ assert(fsp_vpd->sign == VPD_IMAGE_ID); + fsp_upd = &config_data.fsp_upd; + /* Copy default data from Flash */ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), sizeof(struct upd_region)); /* Verify the UPD data region is valid */ assert(fsp_upd->terminator == UPD_TERMINATOR); +#endif - /* Override any UPD setting if required */ - update_fsp_upd(fsp_upd); + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); + + /* Override any configuration if required */ + update_fsp_configs(&config_data, &rt_buf); memset(¶ms, 0, sizeof(struct fsp_init_params)); params.nvs_buf = nvs_buf; @@ -167,28 +155,24 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); params_ptr = ¶ms; - shared_data.fsp_hdr = fsp_hdr; - shared_data.stack_top = (u32 *)stack_top; - post_code(POST_PRE_MRC); /* Load GDT for FSP */ setup_fsp_gdt(); /* - * Use ASM code to ensure the register value in EAX & ECX - * will be passed into BlContinuationFunc + * Use ASM code to ensure the register value in EAX & EDX + * will be passed into fsp_continue */ asm volatile ( "pushl %0;" "call *%%eax;" ".global asm_continuation;" "asm_continuation:;" - "movl %%ebx, %%eax;" /* shared_data */ - "movl 4(%%esp), %%edx;" /* status */ - "movl 8(%%esp), %%ecx;" /* hob_list */ + "movl 4(%%esp), %%eax;" /* status */ + "movl 8(%%esp), %%edx;" /* hob_list */ "jmp fsp_continue;" - : : "m"(params_ptr), "a"(init), "b"(&shared_data) + : : "m"(params_ptr), "a"(init) ); /* diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c index 497ad75b7a4..3c70d790d49 100644 --- a/arch/x86/lib/gcc.c +++ b/arch/x86/lib/gcc.c @@ -3,18 +3,7 @@ * * Copyright (C) 2009 coresystems GmbH * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or later of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifdef __GNUC__ diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig deleted file mode 100644 index f12b96829df..00000000000 --- a/board/Marvell/db-88f6820-gp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_88F6820_GP - -config SYS_BOARD - default "db-88f6820-gp" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "db-88f6820-gp" - -endif diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg index cc057925566..1f748db37c1 100644 --- a/board/Marvell/db-88f6820-gp/kwbimage.cfg +++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl.bin 0000005b 00000068 +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig deleted file mode 100644 index 428a5e15161..00000000000 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_MV784MP_GP - -config SYS_BOARD - default "db-mv784mp-gp" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "db-mv784mp-gp" - -endif diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index d7aa1499adf..93052841170 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -87,40 +87,32 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1545 PHY */ -void reset_phy(void) +int board_phy_config(struct phy_device *phydev) { - u8 phy_addr[] = CONFIG_PHY_ADDR; - u16 devadr = phy_addr[0]; - char *name = "neta0"; u16 reg; - if (miiphy_set_current_dev(name)) - return; - /* Enable QSGMII AN */ /* Set page to 4 */ - miiphy_write(name, devadr, 0x16, 4); + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); /* Enable AN */ - miiphy_write(name, devadr, 0x0, 0x1140); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); /* Set page to 0 */ - miiphy_write(name, devadr, 0x16, 0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); /* Phy C_ANEG */ - miiphy_read(name, devadr, 0x4, ®); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); reg |= 0x1E0; - miiphy_write(name, devadr, 0x4, reg); + phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); /* Soft-Reset */ - miiphy_write(name, devadr, 22, 0x0000); - miiphy_write(name, devadr, 0, 0x9140); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); /* Power up the phy */ - miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); + reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); - miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); + phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); - printf("88E1545 Initialized on %s\n", name); + printf("88E1545 Initialized\n"); + return 0; } -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg index cc057925566..1f748db37c1 100644 --- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl.bin 0000005b 00000068 +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile new file mode 100644 index 00000000000..e66aeb84674 --- /dev/null +++ b/board/Synology/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Phil Sutter <phil@nwl.cc> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cmd_syno.o diff --git a/board/Synology/common/cmd_syno.c b/board/Synology/common/cmd_syno.c new file mode 100644 index 00000000000..20544e29c45 --- /dev/null +++ b/board/Synology/common/cmd_syno.c @@ -0,0 +1,227 @@ +/* + * Commands to deal with Synology specifics. + * + * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <spi.h> +#include <spi_flash.h> +#include <linux/mtd/mtd.h> + +#include <asm/io.h> +#include "../drivers/ddr/marvell/axp/ddr3_init.h" + +#define ETH_ALEN 6 +#define ETHADDR_MAX 4 +#define SYNO_SN_TAG "SN=" +#define SYNO_CHKSUM_TAG "CHK=" + + +static int do_syno_populate(int argc, char * const argv[]) +{ + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + struct spi_flash *flash; + unsigned long addr = 0x80000; /* XXX: parameterize this? */ + loff_t offset = 0x007d0000; + loff_t len = 0x00010000; + char *buf, *bufp; + char var[128]; + char val[128]; + int ret, n; + + /* XXX: arg parsing to select flash here? */ + + flash = spi_flash_probe(bus, cs, speed, mode); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", bus, cs); + return 1; + } + + buf = map_physmem(addr, len, MAP_WRBACK); + if (!buf) { + puts("Failed to map physical memory\n"); + return 1; + } + + ret = spi_flash_read(flash, offset, len, buf); + if (ret) { + puts("Failed to read from SPI flash\n"); + goto out_unmap; + } + + for (n = 0; n < ETHADDR_MAX; n++) { + char ethaddr[ETH_ALEN]; + int i, sum = 0; + unsigned char csum = 0; + + for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) { + sum += bufp[i]; + csum += bufp[i]; + ethaddr[i] = bufp[i]; + } + if (!sum) /* MAC address empty */ + continue; + if (csum != bufp[i]) { /* seventh byte is checksum value */ + printf("Invalid MAC address for interface %d!\n", n); + continue; + } + if (n == 0) + sprintf(var, "ethaddr"); + else + sprintf(var, "eth%daddr", n); + snprintf(val, sizeof(val) - 1, + "%02x:%02x:%02x:%02x:%02x:%02x", + ethaddr[0], ethaddr[1], ethaddr[2], + ethaddr[3], ethaddr[4], ethaddr[5]); + printf("parsed %s = %s\n", var, val); + setenv(var, val); + } + if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) { + char *snp, *csump; + int csum = 0; + unsigned long c; + + snp = bufp = buf + 32 + strlen(SYNO_SN_TAG); + for (n = 0; bufp[n] && bufp[n] != ','; n++) + csum += bufp[n]; + bufp[n] = '\0'; + + /* should come right after, but you never know */ + bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG); + if (!bufp) { + printf("Serial number checksum tag missing!\n"); + goto out_unmap; + } + + csump = bufp += strlen(SYNO_CHKSUM_TAG); + for (n = 0; bufp[n] && bufp[n] != ','; n++) + ; + bufp[n] = '\0'; + + if (strict_strtoul(csump, 10, &c) || c != csum) { + puts("Invalid serial number found!\n"); + ret = 1; + goto out_unmap; + } + printf("parsed SN = %s\n", snp); + setenv("SN", snp); + } else { /* old style format */ + unsigned char csum = 0; + + for (n = 0, bufp = buf + 32; n < 10; n++) + csum += bufp[n]; + + if (csum != bufp[n]) { + puts("Invalid serial number found!\n"); + ret = 1; + goto out_unmap; + } + bufp[n] = '\0'; + printf("parsed SN = %s\n", buf + 32); + setenv("SN", buf + 32); + } +out_unmap: + unmap_physmem(buf, len); + return ret; +} + +/* map bit position to function in POWER_MNG_CTRL_REG */ +static const char * const pwr_mng_bit_func[] = { + "audio", + "ge3", "ge2", "ge1", "ge0", + "pcie00", "pcie01", "pcie02", "pcie03", + "pcie10", "pcie11", "pcie12", "pcie13", + "bp", + "sata0_link", "sata0_core", + "lcd", + "sdio", + "usb0", "usb1", "usb2", + "idma", "xor0", "crypto", + NULL, + "tdm", + "pcie20", "pcie30", + "xor1", + "sata1_link", "sata1_core", + NULL, +}; + +static int do_syno_clk_gate(int argc, char * const argv[]) +{ + u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); + const char *func, *state; + int i, val; + + if (argc < 2) + return -1; + + if (!strcmp(argv[1], "get")) { + puts("Clock Gating:\n"); + for (i = 0; i < 32; i++) { + func = pwr_mng_bit_func[i]; + if (!func) + continue; + state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF"; + printf("%s:\t\t%s\n", func, state); + } + return 0; + } + if (argc < 4) + return -1; + if (!strcmp(argv[1], "set")) { + func = argv[2]; + state = argv[3]; + for (i = 0; i < 32; i++) { + if (!pwr_mng_bit_func[i]) + continue; + if (!strcmp(func, pwr_mng_bit_func[i])) + break; + } + if (i == 32) { + printf("Error: name '%s' not known\n", func); + return -1; + } + val = state[0] != '0'; + pwr_mng_ctrl_reg |= (val << i); + pwr_mng_ctrl_reg &= ~(!val << i); + reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); + } + return 0; +} + +static int do_syno(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + const char *cmd; + int ret = 0; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + --argc; + ++argv; + + if (!strcmp(cmd, "populate_env")) + ret = do_syno_populate(argc, argv); + else if (!strcmp(cmd, "clk_gate")) + ret = do_syno_clk_gate(argc, argv); + + if (ret != -1) + return ret; +usage: + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + syno, 5, 1, do_syno, + "Synology specific commands", + "populate_env - Read vendor data from SPI flash into environment\n" + "clk_gate (get|set name 1|0) - Manage clock gating\n" +); diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile new file mode 100644 index 00000000000..0f4c32d57ca --- /dev/null +++ b/board/Synology/ds414/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Phil Sutter <phil@nwl.cc> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ds414.o diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c new file mode 100644 index 00000000000..d563e896f31 --- /dev/null +++ b/board/Synology/ds414/ds414.c @@ -0,0 +1,185 @@ +/* + * + * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/mbus.h> + +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" +#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */ + +#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30)) +#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15)) +#define DS414_GPP_OUT_VAL_HIGH (0) + +#define DS414_GPP_OUT_POL_LOW (0) +#define DS414_GPP_OUT_POL_MID (0) +#define DS414_GPP_OUT_POL_HIGH (0) + +#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30))) +#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \ + BIT(13) | BIT(14) | BIT(15))) +#define DS414_GPP_OUT_ENA_HIGH (~0) + +static const u32 ds414_mpp_control[] = { + 0x11111111, + 0x22221111, + 0x22222222, + 0x00000000, + 0x11110000, + 0x00004000, + 0x00000000, + 0x00000000, + 0x00000000 +}; + +/* DDR3 static MC configuration */ + +/* 1G_v1 (4x2Gbits) adapted by DS414 */ +MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ + {0x00001404, 0x30000800}, /*Dunit Control Low Register */ + {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */ + + {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */ + + {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ + {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ + {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ + {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */ + {0x00001428, 0x000F8830}, /*Dunit Control High Register */ + {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */ + {0x0000147C, 0x0000C671}, + + {0x000014a0, 0x00000001}, + {0x000014a8, 0x00000100}, /*2:1 */ + {0x00020220, 0x00000006}, + + {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ + {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ + {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */ + + {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */ + {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */ + + {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/ + {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ + + {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ + {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */ + + {0x000015D0, 0x00000650}, /*MR0 */ + {0x000015D4, 0x00000044}, /*MR1 */ + {0x000015D8, 0x00000010}, /*MR2 */ + {0x000015DC, 0x00000000}, /*MR3 */ + + {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ + {0x000015EC, 0xF800A225}, /*DDR PHY */ + + {0x0, 0x0} +}; + +MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +MV_BIN_SERDES_CFG ds414_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000, + { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, + PEX_BUS_DISABLED }, + 0x0040, serdes_change_m_phy + } +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + return &ds414_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &ds414_serdes_cfg[0]; +} + +u8 board_sat_r_get(u8 dev_num, u8 reg) +{ + return (0x1 << 1 | 1); +} + +int board_early_init_f(void) +{ + int i; + + /* Set GPP Out value */ + reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); + reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); + reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); + + /* set GPP polarity */ + reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); + reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); + reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); + + /* Set GPP Out Enable */ + reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); + reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); + reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); + + for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++) + reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); + + return 0; +} + +int board_init(void) +{ + u32 pwr_mng_ctrl_reg; + + /* Adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Gate unused clocks + * + * Note: Disabling unused PCIe lanes will hang PCI bus scan. + * Once this is resolved, bits 10-12, 26 and 27 can be + * unset here as well. + */ + pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); + pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */ + pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */ + pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */ + pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */ + pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */ + pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */ + pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */ + reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); + + return 0; +} + +int checkboard(void) +{ + puts("Board: DS414\n"); + + return 0; +} diff --git a/board/Synology/ds414/kwbimage.cfg b/board/Synology/ds414/kwbimage.cfg new file mode 100644 index 00000000000..1f748db37c1 --- /dev/null +++ b/board/Synology/ds414/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk index 05a4162dbcb..53d3f34692d 100644 --- a/board/amcc/yucca/config.mk +++ b/board/amcc/yucca/config.mk @@ -9,12 +9,6 @@ # AMCC 440SPe Reference Platform (yucca) board # -ifeq ($(ramsym),1) -CONFIG_SYS_TEXT_BASE = 0x07FD0000 -else -CONFIG_SYS_TEXT_BASE = 0xfffb0000 -endif - PLATFORM_CPPFLAGS += -DCONFIG_440=1 ifeq ($(debug),1) diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig new file mode 100644 index 00000000000..927d8765d67 --- /dev/null +++ b/board/cavium/thunderx/Kconfig @@ -0,0 +1,27 @@ +if TARGET_THUNDERX_88XX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "thunderx" + +config SYS_VENDOR + string + default "cavium" + +config SYS_CONFIG_NAME + string + default "thunderx_88xx" + +config CMD_ATF + bool "Enable ATF query commands" + default y + help + Enable vendor specific ATF query commands such as SPI and SD/MMC + devices access, low level environment query, boot device layout + and node count. + +endif diff --git a/board/cavium/thunderx/MAINTAINERS b/board/cavium/thunderx/MAINTAINERS new file mode 100644 index 00000000000..c84d3b553dc --- /dev/null +++ b/board/cavium/thunderx/MAINTAINERS @@ -0,0 +1,6 @@ +THUNDERX BOARD +M: Sergey Temerkhanov <s.temerkhanov@gmail.com> +S: Maintained +F: board/cavium/thunderx/ +F: include/configs/thunderx_88xx.h +F: configs/thunderx_88xx_defconfig diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile new file mode 100644 index 00000000000..c78c414cdfc --- /dev/null +++ b/board/cavium/thunderx/Makefile @@ -0,0 +1,8 @@ +# +# +# (C) Copyright 2014, Cavium Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := thunderx.o atf.o diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c new file mode 100644 index 00000000000..6ab9de944f2 --- /dev/null +++ b/board/cavium/thunderx/atf.c @@ -0,0 +1,312 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <asm/io.h> + +#include <asm/system.h> +#include <cavium/thunderx_svc.h> +#include <cavium/atf.h> +#include <cavium/atf_part.h> + +#include <asm/psci.h> + +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_MMC_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NOR_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_pcount(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_PART_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_part(struct storage_partition *part, unsigned int index) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_GET_PART; + regs.regs[1] = (uintptr_t)part; + regs.regs[2] = index; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_erase_nor(uintptr_t offset, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_ERASE; + regs.regs[1] = offset; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_MMC_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_dram_size(unsigned int node) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_DRAM_SIZE; + regs.regs[1] = node; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_node_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NODE_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_string(size_t index, char *str) +{ + uint64_t *buf = (void *)str; + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_STRING; + regs.regs[1] = index; + + smc_call(®s); + + if (regs.regs > 0) { + buf[0] = regs.regs[0]; + buf[1] = regs.regs[1]; + buf[2] = regs.regs[2]; + buf[3] = regs.regs[3]; + + return 1; + } else { + return regs.regs[0]; + } +} + +#ifdef CONFIG_CMD_ATF + +static void atf_print_ver(void) +{ + struct pt_regs regs; + regs.regs[0] = ARM_STD_SVC_VERSION; + + smc_call(®s); + + printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]); + + regs.regs[0] = THUNDERX_SVC_VERSION; + + smc_call(®s); + + printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]); +} + +static void atf_print_uid(void) +{ +} + +static void atf_print_part_table(void) +{ + size_t pcount; + unsigned long i; + int ret; + char *ptype; + + struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + + pcount = atf_get_pcount(); + + printf("Partition count: %lu\n\n", pcount); + printf("%10s %10s %10s\n", "Type", "Size", "Offset"); + + for (i = 0; i < pcount; i++) { + ret = atf_get_part(part, i); + + if (ret < 0) { + printf("Uknown error while reading partition: %d\n", + ret); + return; + } + + switch (part->type) { + case PARTITION_NBL1FW_REST: + ptype = "NBL1FW"; + break; + case PARTITION_BL2_BL31: + ptype = "BL2_BL31"; + break; + case PARTITION_UBOOT: + ptype = "BOOTLDR"; + break; + case PARTITION_KERNEL: + ptype = "KERNEL"; + break; + case PARTITION_DEVICE_TREE: + ptype = "DEVTREE"; + break; + default: + ptype = "UNKNOWN"; + } + printf("%10s %10d %10lx\n", ptype, part->size, part->offset); + } +} + +int do_atf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ssize_t ret; + size_t size, offset; + void *buffer = 0; + unsigned int index, node; + char str[4 * sizeof(uint64_t)]; + + if ((argc == 5) && !strcmp(argv[1], "readmmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "readnor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_nor(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writemmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writenor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_nor(offset, buffer, size); + } else if ((argc == 2) && !strcmp(argv[1], "part")) { + atf_print_part_table(); + } else if ((argc == 4) && !strcmp(argv[1], "erasenor")) { + offset = simple_strtoul(argv[2], NULL, 10); + size = simple_strtoul(argv[3], NULL, 10); + + ret = atf_erase_nor(offset, size); + } else if ((argc == 2) && !strcmp(argv[1], "envcount")) { + ret = atf_env_count(); + printf("Number of environment strings: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "envstring")) { + index = simple_strtoul(argv[2], NULL, 10); + ret = atf_env_string(index, str); + if (ret > 0) + printf("Environment string %d: %s\n", index, str); + else + printf("Return code: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "dramsize")) { + node = simple_strtoul(argv[2], NULL, 10); + ret = atf_dram_size(node); + printf("DRAM size: %zd Mbytes\n", ret >> 20); + } else if ((argc == 2) && !strcmp(argv[1], "nodes")) { + ret = atf_node_count(); + printf("Nodes count: %zd\n", ret); + } else if ((argc == 2) && !strcmp(argv[1], "ver")) { + atf_print_ver(); + } else if ((argc == 2) && !strcmp(argv[1], "uid")) { + atf_print_uid(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + atf, 10, 1, do_atf, + "issue calls to ATF", + "\t readmmc addr offset size - read MMC card\n" + "\t readnor addr offset size - read NOR flash\n" + "\t writemmc addr offset size - write MMC card\n" + "\t writenor addr offset size - write NOR flash\n" + "\t erasenor offset size - erase NOR flash\n" + "\t nodes - number of nodes\n" + "\t dramsize node - size of DRAM attached to node\n" + "\t envcount - number of environment strings\n" + "\t envstring index - print the environment string\n" + "\t part - print MMC partition table\n" + "\t ver - print ATF call set versions\n" +); + +#endif diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c new file mode 100644 index 00000000000..b9267676dc6 --- /dev/null +++ b/board/cavium/thunderx/thunderx.c @@ -0,0 +1,102 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <linux/compiler.h> + +#include <cavium/atf.h> + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +#include <dm/platdata.h> +#include <dm/platform_data/serial_pl01x.h> + +static const struct pl01x_serial_platdata serial0 = { + .base = CONFIG_SYS_SERIAL0, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static const struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int timer_init(void) +{ + return 0; +} + +int dram_init(void) +{ + ssize_t node_count = atf_node_count(); + ssize_t dram_size; + int node; + + printf("Initializing\nNodes in system: %zd\n", node_count); + + gd->ram_size = 0; + + for (node = 0; node < node_count; node++) { + dram_size = atf_dram_size(node); + printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); + gd->ram_size += dram_size; + } + + gd->ram_size -= MEM_BASE; + + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + puts("DRAM size:"); + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + return rc; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + printf("DEBUG: PCI Init TODO *****\n"); +} +#endif diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk deleted file mode 100644 index 1af25e158a7..00000000000 --- a/board/cobra5272/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 462ab05556c..cd992941aa6 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index bef2570af6e..f69aeb6d13d 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -6,19 +6,7 @@ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk deleted file mode 100644 index b378ac8a60c..00000000000 --- a/board/dbau1x00/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMD development board AMD Alchemy DbAu1x00, MIPS32 core -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xbfc00000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80100000 diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index bd20f6e4b0d..75e6f0ef5ad 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <asm/mipsregs.h> #include <asm/io.h> diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 842fb76e587..409f8ee4770 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -1,8 +1,8 @@ /* Memory sub-system initialization code */ #include <config.h> +#include <mach/au1x00.h> #include <asm/regdef.h> -#include <asm/au1x00.h> #include <asm/mipsregs.h> #define AU1500_SYS_ADDR 0xB1900000 diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 2c17156586d..eb10a6f364a 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index df90476a772..4b2303e8496 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -408,22 +408,22 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, sizeof(f_link)); break; case 0x98: /* XAUI interface */ - sprintf(alias, "phy_xaui_slot1"); + strcpy(alias, "phy_xaui_slot1"); fdt_status_okay_by_alias(fdt, alias); - sprintf(alias, "phy_xaui_slot2"); + strcpy(alias, "phy_xaui_slot2"); fdt_status_okay_by_alias(fdt, alias); break; case 0x9e: /* XAUI interface */ case 0x9a: case 0x93: case 0x91: - sprintf(alias, "phy_xaui_slot1"); + strcpy(alias, "phy_xaui_slot1"); fdt_status_okay_by_alias(fdt, alias); break; case 0x97: /* XAUI interface */ case 0xc3: - sprintf(alias, "phy_xaui_slot2"); + strcpy(alias, "phy_xaui_slot2"); fdt_status_okay_by_alias(fdt, alias); break; default: diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index 022f38b117f..e55a03090ab 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -29,7 +29,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 1; /* read out the first block, get the config data information */ - n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf); + n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); if (!n) { free(tmp_buf); return 1; diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index e7e893a1aec..f3ba41a5fd8 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 172a55b9883..55437e843d6 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -170,7 +170,7 @@ static int hydra_mdio_init(char *realbusname, char *fakebusname) bus->read = hydra_mdio_read; bus->write = hydra_mdio_write; bus->reset = hydra_mdio_reset; - sprintf(bus->name, fakebusname); + strcpy(bus->name, fakebusname); hmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index 62b163580b2..3f11f5f279a 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -175,7 +175,7 @@ static int super_hydra_mdio_init(char *realbusname, char *fakebusname) bus->read = super_hydra_mdio_read; bus->write = super_hydra_mdio_write; bus->reset = super_hydra_mdio_reset; - sprintf(bus->name, fakebusname); + strcpy(bus->name, fakebusname); hmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c index 4dead9c0453..20785b1bb32 100644 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ b/board/freescale/corenet_ds/p3041ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index d572a5fbedf..f470306135a 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c index 9aaf6db9972..9747d904b24 100644 --- a/board/freescale/corenet_ds/p5020ds_ddr.c +++ b/board/freescale/corenet_ds/p5020ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c index 9aaf6db9972..9747d904b24 100644 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c index be351befec0..bf3e08a8cf9 100644 --- a/board/freescale/ls1021aqds/eth.c +++ b/board/freescale/ls1021aqds/eth.c @@ -113,7 +113,7 @@ static int ls1021a_mdio_init(char *realbusname, char *fakebusname) bus->read = ls1021a_mdio_read; bus->write = ls1021a_mdio_write; bus->reset = ls1021a_mdio_reset; - sprintf(bus->name, fakebusname); + strcpy(bus->name, fakebusname); lsmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index b7fc360e2cc..88b10a0f2f1 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -136,7 +136,7 @@ static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) bus->read = ls1043aqds_mdio_read; bus->write = ls1043aqds_mdio_write; bus->reset = ls1043aqds_mdio_reset; - sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 0637ecf2a7f..ebc9d474681 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -412,7 +412,7 @@ static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) bus->read = ls2080a_qds_mdio_read; bus->write = ls2080a_qds_mdio_write; bus->reset = ls2080a_qds_mdio_reset; - sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/m5208evbe/config.mk b/board/freescale/m5208evbe/config.mk deleted file mode 100644 index c15a9cfba6b..00000000000 --- a/board/freescale/m5208evbe/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m5249evb/config.mk b/board/freescale/m5249evb/config.mk deleted file mode 100644 index 1af25e158a7..00000000000 --- a/board/freescale/m5249evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5253demo/config.mk b/board/freescale/m5253demo/config.mk deleted file mode 100644 index 45474652a8b..00000000000 --- a/board/freescale/m5253demo/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFF800000 diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk deleted file mode 100644 index 1af25e158a7..00000000000 --- a/board/freescale/m5253evbe/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5272c3/config.mk b/board/freescale/m5272c3/config.mk deleted file mode 100644 index 1af25e158a7..00000000000 --- a/board/freescale/m5272c3/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5275evb/config.mk b/board/freescale/m5275evb/config.mk deleted file mode 100644 index 1af25e158a7..00000000000 --- a/board/freescale/m5275evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5282evb/config.mk b/board/freescale/m5282evb/config.mk deleted file mode 100644 index e2ac27e86fa..00000000000 --- a/board/freescale/m5282evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFFE00000 diff --git a/board/freescale/m53017evb/config.mk b/board/freescale/m53017evb/config.mk deleted file mode 100644 index c15a9cfba6b..00000000000 --- a/board/freescale/m53017evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk deleted file mode 100644 index c15a9cfba6b..00000000000 --- a/board/freescale/m5329evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m5373evb/config.mk b/board/freescale/m5373evb/config.mk deleted file mode 100644 index c15a9cfba6b..00000000000 --- a/board/freescale/m5373evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk deleted file mode 100644 index 07f52e02556..00000000000 --- a/board/freescale/m54418twr/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2010-2012 Freescale Semiconductor, Inc. -# TsiChung Liew (Tsi-Chung.Liew@freescale.com) -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m547xevb/config.mk b/board/freescale/m547xevb/config.mk deleted file mode 100644 index 45474652a8b..00000000000 --- a/board/freescale/m547xevb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFF800000 diff --git a/board/freescale/m548xevb/config.mk b/board/freescale/m548xevb/config.mk deleted file mode 100644 index 45474652a8b..00000000000 --- a/board/freescale/m548xevb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFF800000 diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index ebe3ba460cc..f269feb08e8 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 41d4cfe7381..10fb2b3d600 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index d2ac6c4ad47..e438737065a 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index aa30cabb030..93c7f4b8c9b 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index b31ea3432e5..0d5783ae04d 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index d2ac6c4ad47..e438737065a 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 41d4cfe7381..10fb2b3d600 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 6db92ef2dab..cb3b707a477 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index ef404b1d6f0..89e92972629 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index 2bfc1a170c6..524ed609031 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index aa30cabb030..93c7f4b8c9b 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 7cd0395651b..00670bc5a70 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008,2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 946d5032e74..1f3793b853e 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index b8bbcdf2a86..b2493e1f618 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c index 99c23f79f47..ca54e2a4f0a 100644 --- a/board/freescale/t102xqds/eth_t102xqds.c +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -148,7 +148,7 @@ static int t1024qds_mdio_init(char *realbusname, u8 muxval) bus->read = t1024qds_mdio_read; bus->write = t1024qds_mdio_write; bus->reset = t1024qds_mdio_reset; - sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 8bf34fa79ac..872e6e8228a 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -162,7 +162,7 @@ static int t1040_qds_mdio_init(char *realbusname, u8 muxval) bus->read = t1040_qds_mdio_read; bus->write = t1040_qds_mdio_write; bus->reset = t1040_qds_mdio_reset; - sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index 3348971b01e..f1aff5481e4 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 1c0ce2492ca..f08cff26546 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -176,7 +176,7 @@ static int t208xqds_mdio_init(char *realbusname, u8 muxval) bus->read = t208xqds_mdio_read; bus->write = t208xqds_mdio_write; bus->reset = t208xqds_mdio_reset; - sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 8a262762735..053f128e5b2 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7abd38def1a..62d58c5b1f1 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2012 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 2dfdcbbd398..83a3a9bba28 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -153,7 +153,7 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval) bus->read = t4240qds_mdio_read; bus->write = t4240qds_mdio_write; bus->reset = t4240qds_mdio_reset; - sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index 1d6eb7bd55f..262ead55164 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -80,7 +80,7 @@ int ihs_mdio_init(struct ihs_mdio_info *info) bus->read = ihs_mdio_read; bus->write = ihs_mdio_write; bus->reset = ihs_mdio_reset; - sprintf(bus->name, info->name); + strcpy(bus->name, info->name); bus->priv = info; diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 11d075c3859..2c6c698fb3a 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -2,20 +2,7 @@ * (C) Copyright 2013 * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0+ */ /* TODO: some more #ifdef's to avoid unneeded code for stage 1 / stage 2 */ @@ -232,7 +219,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) ofs = src % blk_len; if (ofs) { - n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1, + n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1, tmp_buf); if (!n) goto failure; @@ -243,7 +230,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) } cnt = size / blk_len; if (cnt) { - n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no, cnt, + n = mmc->block_dev.block_read(&mmc->block_dev, block_no, cnt, dst); if (n != cnt) goto failure; @@ -253,7 +240,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) block_no += cnt; } if (size) { - n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1, + n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1, tmp_buf); if (!n) goto failure; diff --git a/board/gdsys/p1022/controlcenterd-id.h b/board/gdsys/p1022/controlcenterd-id.h index de4770ac8de..b6f47028fde 100644 --- a/board/gdsys/p1022/controlcenterd-id.h +++ b/board/gdsys/p1022/controlcenterd-id.h @@ -2,20 +2,7 @@ * (C) Copyright 2013 * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONTROLCENTER_ID_H diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c index 7596736bfd4..58f63f3ac35 100644 --- a/board/gdsys/p1022/ddr.c +++ b/board/gdsys/p1022/ddr.c @@ -3,10 +3,7 @@ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/gdsys/p1022/diu.c b/board/gdsys/p1022/diu.c index 52ac1e6ecc1..af0608bdd21 100644 --- a/board/gdsys/p1022/diu.c +++ b/board/gdsys/p1022/diu.c @@ -4,10 +4,7 @@ * * FSL DIU Framebuffer driver * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/gdsys/p1022/law.c b/board/gdsys/p1022/law.c index 96f38f7c6fe..1438d9fb6f4 100644 --- a/board/gdsys/p1022/law.c +++ b/board/gdsys/p1022/law.c @@ -3,10 +3,7 @@ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c index fd0e910d7ba..6a4a6ef6af2 100644 --- a/board/gdsys/p1022/sdhc_boot.c +++ b/board/gdsys/p1022/sdhc_boot.c @@ -43,7 +43,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 1; /* read out the first block, get the config data information */ - n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf); + n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); if (!n) { free(tmp_buf); return 1; diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c index 9cad6927833..aee86a4356d 100644 --- a/board/gdsys/p1022/tlb.c +++ b/board/gdsys/p1022/tlb.c @@ -3,10 +3,7 @@ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 6b139392b56..fa12f338de5 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index ae96d23d030..2af3aa9e74a 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 config SYS_CAR_ADDR diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c index 00153232f6a..1578a33fd1a 100644 --- a/board/highbank/ahci.c +++ b/board/highbank/ahci.c @@ -1,18 +1,7 @@ /* * Copyright 2012 Calxeda, Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 79562f79a80..cae4a21c3d8 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -53,8 +53,9 @@ static void malta_lcd_puts(const char *str) static enum core_card malta_core_card(void) { u32 corid, rev; + const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); - rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); + rev = __raw_readl(reg); corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; switch (corid) { diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 57b89e0ba64..e2fce502080 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -101,6 +101,19 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) #endif #if defined(CONFIG_CMD_NET) + +static void reset_net_chip(int gpio) +{ + if (!gpio_request(gpio, "eth nrst")) { + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + udelay(40); + gpio_set_value(gpio, 1); + mdelay(10); + } +} + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -110,8 +123,8 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); @@ -121,15 +134,7 @@ static void setup_net_chip(void) writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } + reset_net_chip(64); } #else static inline void setup_net_chip(void) {} @@ -200,10 +205,10 @@ void set_muxconf_regs(void) #if defined(CONFIG_CMD_NET) int board_eth_init(bd_t *bis) { - int rc = 0; #ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; #endif - return rc; } #endif diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 8de129dc83f..a42f3eca33b 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -168,7 +168,7 @@ static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, printf("can't get the IVM_Boardid\n"); return 1; } - sprintf((char *)buf, "%s", p); + strcpy((char *)buf, p); setenv("boardid", (char *)buf); printf("set boardid=%s\n", buf); @@ -177,7 +177,7 @@ static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, printf("can't get the IVM_HWKey\n"); return 1; } - sprintf((char *)buf, "%s", p); + strcpy((char *)buf, p); setenv("hwkey", (char *)buf); printf("set hwkey=%s\n", buf); printf("Execute manually saveenv for persistent storage.\n"); diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h index b2a09b3cd04..e5d0774e784 100644 --- a/board/lge/sniper/sniper.h +++ b/board/lge/sniper/sniper.h @@ -51,13 +51,13 @@ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \ /* GPMC */ \ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \ - MUX_VAL(CP(GPMC_A2), (IEN | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \ + MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\ MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\ - MUX_VAL(CP(GPMC_A7), (IEN | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\ + MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\ MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\ MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\ MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\ @@ -129,7 +129,7 @@ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \ MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \ @@ -156,12 +156,12 @@ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \ /* MMC1 */ \ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /* MMC1_CMD */ \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /* MMC1_DAT0 */ \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /* MMC1_DAT1 */ \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /* MMC1_DAT2 */ \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /* MMC1_DAT3 */ \ + MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ @@ -183,15 +183,15 @@ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \ /* UART2 */ \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | DIS | M0)) /* UART2_CTS */ \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTU | DIS | M0)) /* UART2_RTS */ \ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \ /* UART1 */ \ - MUX_VAL(CP(UART1_TX), (IDIS | PTU | DIS | M0)) /* UART1_TX */ \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTU | DIS | M0)) /* UART1_RTS */ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */ \ - MUX_VAL(CP(UART1_RX), (IEN | PTU | DIS | M0)) /* UART1_RX */ \ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \ /* MCBSP4 */ \ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \ @@ -227,11 +227,11 @@ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \ /* I2C2 */ \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /* I2C2_SCL */ \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /* I2C2_SDA */ \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \ /* I2C3 */ \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /* I2C3_SCL */ \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /* I2C3_SDA */ \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \ /* I2C4 */ \ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \ @@ -242,13 +242,13 @@ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT */ \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \ - MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \ + MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \ MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \ - MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \ + MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \ /* SYS */ \ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \ @@ -262,25 +262,25 @@ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \ /* JTAG */ \ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | DIS | M0)) /* JTAG_EMU0 */ \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | DIS | M0)) /* JTAG_EMU1 */ \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \ /* ETK */ \ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \ @@ -330,7 +330,7 @@ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \ MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \ - MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \ + MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \ MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \ MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \ @@ -355,8 +355,8 @@ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \ MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \ MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \ diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig deleted file mode 100644 index 2edccfea535..00000000000 --- a/board/maxbcm/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MAXBCM - -config SYS_BOARD - default "maxbcm" - -config SYS_CONFIG_NAME - default "maxbcm" - -endif diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg index cc057925566..1f748db37c1 100644 --- a/board/maxbcm/kwbimage.cfg +++ b/board/maxbcm/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl.bin 0000005b 00000068 +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index 119ba4c6c8f..db6ad99efea 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -138,17 +138,15 @@ int checkboard(void) return 0; } -#ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E6185 switch */ -void reset_phy(void) +int board_phy_config(struct phy_device *phydev) { - char *name = "neta0"; - - if (miiphy_set_current_dev(name)) - return; - - /* todo: fill this with the real setup / config code */ - - printf("88E6185 Initialized on %s\n", name); + /* + * todo: + * Fill this with the real setup / config code. + * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c + * for details. + */ + printf("88E6185 Initialized\n"); + return 0; } -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk deleted file mode 100644 index 354d918474f..00000000000 --- a/board/micronas/vct/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# vct_xxx boards with MIPS 4Kc CPU core -# - -ifndef CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE = 0x87000000 -endif diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h index 0a1c5fcb829..67da6a8e730 100644 --- a/board/micronas/vct/vct.h +++ b/board/micronas/vct/vct.h @@ -80,12 +80,14 @@ void vct_pin_mux_initialize(void); */ static inline void reg_write(u32 addr, u32 data) { - __raw_writel(data, addr + REG_GLOBAL_START_ADDR); + void *reg = (void *)(addr + REG_GLOBAL_START_ADDR); + __raw_writel(data, reg); } static inline u32 reg_read(u32 addr) { - return __raw_readl(addr + REG_GLOBAL_START_ADDR); + const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR); + return __raw_readl(reg); } #endif /* _VCT_H */ diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 6b96bd526e8..226217570c2 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -698,12 +698,12 @@ void video_get_info_str (int line_number, char *info) s=getenv ("serial#"); #ifdef CONFIG_PIP405 if (!s || strncmp (s, "PIP405", 6)) { - sprintf(buf,"### No HW ID - assuming PIP405"); + strcpy(buf,"### No HW ID - assuming PIP405"); } #endif #ifdef CONFIG_MIP405 if (!s || strncmp (s, "MIP405", 6)) { - sprintf(buf,"### No HW ID - assuming MIP405"); + strcpy(buf,"### No HW ID - assuming MIP405"); } #endif else { @@ -718,7 +718,7 @@ void video_get_info_str (int line_number, char *info) } buf[i++] = *s; } - sprintf(&buf[i]," SN "); + strcpy(&buf[i]," SN "); i+=4; for (; s < e; ++s) { buf[i++] = *s; @@ -744,7 +744,7 @@ void video_get_info_str (int line_number, char *info) ctfb.modeIdent); return; case 1: - sprintf (buf, "%s",CONFIG_IDENT_STRING); + strcpy(buf, CONFIG_IDENT_STRING); sprintf (info, " %s", &buf[1]); return; } diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h index 255e4cd82bd..c21c30c5985 100644 --- a/board/nvidia/cardhu/pinmux-config-cardhu.h +++ b/board/nvidia/cardhu/pinmux-config-cardhu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_CARDHU_H_ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index d7c1a695ff8..e4c4bfbc680 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 891ac07dd90..294731e96cf 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_DALMORE_H_ diff --git a/board/pb1x00/config.mk b/board/pb1x00/config.mk deleted file mode 100644 index 8f133011593..00000000000 --- a/board/pb1x00/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMD development board AMD Alchemy Pb1x00, MIPS32 core -# - -# ROM version -#CONFIG_SYS_TEXT_BASE = 0xbfc00000 - -# SDRAM version -CONFIG_SYS_TEXT_BASE = 0x83800000 diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S index b145e438f07..98d9536a7d7 100644 --- a/board/pb1x00/lowlevel_init.S +++ b/board/pb1x00/lowlevel_init.S @@ -1,8 +1,8 @@ /* Memory sub-system initialization code */ #include <config.h> +#include <mach/au1x00.h> #include <asm/regdef.h> -#include <asm/au1x00.h> #include <asm/mipsregs.h> #define AU1500_SYS_ADDR 0xB1900000 diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 34814c47cb8..eb92914a798 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <asm/mipsregs.h> #include <asm/io.h> diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index c25b486f4a9..426ae14af26 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -355,10 +355,10 @@ int exynos_init(void) } /* Request soft I2C gpios */ - sprintf(buf, "soft_i2c_scl"); + strcpy(buf, "soft_i2c_scl"); gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf); - sprintf(buf, "soft_i2c_sda"); + strcpy(buf, "soft_i2c_sda"); gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf); check_hw_revision(); diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 24cc776a255..2ffafa8582f 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index b31ea3432e5..0d5783ae04d 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index f94e3e5736f..b3c666c054f 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -480,7 +480,7 @@ int board_late_init(void) sprintf(tmp, "%s_%s", factory_dat.asn, factory_dat.comp_version); else - sprintf(tmp, "QMX7.E38_4.0"); + strcpy(tmp, "QMX7.E38_4.0"); ret = setenv("boardid", tmp); if (ret) diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 6bad4da3947..fe8a8bfb696 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS new file mode 100644 index 00000000000..298e5011c79 --- /dev/null +++ b/board/solidrun/clearfog/MAINTAINERS @@ -0,0 +1,6 @@ +CLEARFOG BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/soldrun/clearfog/ +F: include/configs/clearfog.h +F: configs/clearfog_defconfig diff --git a/board/solidrun/clearfog/Makefile b/board/solidrun/clearfog/Makefile new file mode 100644 index 00000000000..1920d6bf6d9 --- /dev/null +++ b/board/solidrun/clearfog/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := clearfog.o diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README new file mode 100644 index 00000000000..2cfa5bfc863 --- /dev/null +++ b/board/solidrun/clearfog/README @@ -0,0 +1,18 @@ +Update from original Marvell U-Boot to mainline U-Boot: +------------------------------------------------------- + +Generate the U-Boot image with these commands: + +$ make clearfog_defconfig +$ make + +The resulting image including the SPL binary with the +full DDR setup is "u-boot-spl.kwb". + +Now all you need to do is copy this image on a SD card. +For example with this command: + +$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 + +Please use the correct device node for your setup instead +of "/dev/sdX" here! diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c new file mode 100644 index 00000000000..2773f5957e6 --- /dev/null +++ b/board/solidrun/clearfog/clearfog.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" +#include <../serdes/a38x/high_speed_env_spec.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-15t1-clearfog" + */ +#define BOARD_GPP_OUT_ENA_LOW 0xffffffff +#define BOARD_GPP_OUT_ENA_MID 0xffffffff + +#define BOARD_GPP_OUT_VAL_LOW 0x0 +#define BOARD_GPP_OUT_VAL_MID 0x0 +#define BOARD_GPP_POL_LOW 0x0 +#define BOARD_GPP_POL_MID 0x0 + +/* IO expander on Marvell GP board includes e.g. fan enabling */ +struct marvell_io_exp { + u8 chip; + u8 addr; + u8 val; +}; + +static struct marvell_io_exp io_exp[] = { + { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */ + { 0x20, 6, 0xf9 }, + { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */ + { 0x20, 6, 0xb9 }, + { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */ + { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */ +}; + +static struct serdes_map board_serdes_map[] = { + {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, +}; + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + *serdes_map_array = board_serdes_map; + *count = ARRAY_SIZE(board_serdes_map); + return 0; +} + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct hws_topology_map board_topology_map = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_LOW} }, /* temperature */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x11111111, MVEBU_MPP_BASE + 0x00); + writel(0x11111111, MVEBU_MPP_BASE + 0x04); + writel(0x10400011, MVEBU_MPP_BASE + 0x08); + writel(0x22043333, MVEBU_MPP_BASE + 0x0c); + writel(0x44400002, MVEBU_MPP_BASE + 0x10); + writel(0x41144004, MVEBU_MPP_BASE + 0x14); + writel(0x40333333, MVEBU_MPP_BASE + 0x18); + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + int i; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Toggle GPIO41 to reset onboard switch and phy */ + clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); + mdelay(1); + setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + mdelay(10); + + /* Init I2C IO expanders */ + for (i = 0; i < ARRAY_SIZE(io_exp); i++) + i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); + + return 0; +} + +int checkboard(void) +{ + puts("Board: SolidRun ClearFog\n"); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} diff --git a/board/solidrun/clearfog/kwbimage.cfg b/board/solidrun/clearfog/kwbimage.cfg new file mode 100644 index 00000000000..c650c2c65eb --- /dev/null +++ b/board/solidrun/clearfog/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM sdio + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 9d67847850f..7c69be918f1 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -363,6 +363,12 @@ config I2C3_ENABLE See I2C0_ENABLE help text. endif +config R_I2C_ENABLE + bool "Enable the PRCM I2C/TWI controller" + default n + ---help--- + Set this to y to enable the I2C controller which is part of the PRCM. + if MACH_SUN7I config I2C4_ENABLE bool "Enable I2C/TWI controller 4" diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 386e2e04c21..1cc39e4d184 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -422,6 +422,12 @@ void i2c_init_board(void) clock_twi_onoff(4, 1); #endif #endif + +#ifdef CONFIG_R_I2C_ENABLE + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); +#endif } #ifdef CONFIG_SPL_BUILD diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk deleted file mode 100644 index d01a8bb567b..00000000000 --- a/board/sysam/amcore/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffc00000 diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index c988d395c19..16d1a64dc2d 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2014, Marcel Ziswiler * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_APALIS_T30_H_ diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index 4e73c0762e0..407c6c36e17 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2013-2014, Stefan Agner * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_COLIBRI_T30_H_ diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 638d14f6d06..ac44e32341f 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -346,7 +346,7 @@ int board_late_init(void) /* get production data */ if (read_eeprom(&header)) { - sprintf(model, "211"); + strcpy(model, "211"); } else { sprintf(model, "%d", header.SystemId); if (header.SystemId == 215) { diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index 5c5eadc93ff..b73dd8100be 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk index 36bdd963434..95ef9c0f069 100644 --- a/board/xilinx/microblaze-generic/config.mk +++ b/board/xilinx/microblaze-generic/config.mk @@ -11,8 +11,6 @@ # the generated file from your Xilinx design flow. # -CONFIG_SYS_TEXT_BASE = 0x29000000 - PLATFORM_CPPFLAGS += -mno-xl-soft-mul PLATFORM_CPPFLAGS += -mno-xl-soft-div PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c index ed758722bbd..eb290023a1e 100644 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h index c61cf2abcc5..bdea5a0443c 100644 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c index ac5e0bcb88d..abfd91187df 100644 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h index 584e1e1d901..16fa8104a41 100644 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c index 98bad67813f..77fd9499df7 100644 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h index 6c94c42cebb..8527eef447e 100644 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c index 34485db9c73..f4f45becd66 100644 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h index cd8ead4c0aa..9b41e286976 100644 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/common/Kconfig b/common/Kconfig index ccf5475bac6..9d446bf86b0 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -184,6 +184,9 @@ config CMD_XIMG help Extract a part of a multi-image. +config CMD_POWEROFF + bool + endmenu menu "Environment commands" diff --git a/common/cli_simple.c b/common/cli_simple.c index 9c3d073d583..bb96aaead60 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -276,7 +276,8 @@ void cli_simple_loop(void) flag = 0; /* assume no special flags for now */ if (len > 0) - strcpy(lastcommand, console_buffer); + strlcpy(lastcommand, console_buffer, + CONFIG_SYS_CBSIZE + 1); else if (len == 0) flag |= CMD_FLAG_REPEAT; #ifdef CONFIG_BOOT_RETRY_TIME diff --git a/common/cmd_boot.c b/common/cmd_boot.c index 8f2e0701b54..72f2cf362d4 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -61,3 +61,11 @@ U_BOOT_CMD( "Perform RESET of the CPU", "" ); + +#ifdef CONFIG_CMD_POWEROFF +U_BOOT_CMD( + poweroff, 1, 0, do_poweroff, + "Perform POWEROFF of the device", + "" +); +#endif diff --git a/common/cmd_disk.c b/common/cmd_disk.c index 8a1fda9f68a..3025225c764 100644 --- a/common/cmd_disk.c +++ b/common/cmd_disk.c @@ -56,7 +56,7 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, ", Block Size: %ld\n", info.start, info.size, info.blksz); - if (dev_desc->block_read(dev, info.start, 1, (ulong *) addr) != 1) { + if (dev_desc->block_read(dev_desc, info.start, 1, (ulong *)addr) != 1) { printf("** Read error on %d:%d\n", dev, part); bootstage_error(BOOTSTAGE_ID_IDE_PART_READ); return 1; @@ -100,8 +100,8 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, cnt /= info.blksz; cnt -= 1; - if (dev_desc->block_read(dev, info.start + 1, cnt, - (ulong *)(addr + info.blksz)) != cnt) { + if (dev_desc->block_read(dev_desc, info.start + 1, cnt, + (ulong *)(addr + info.blksz)) != cnt) { printf("** Read error on %d:%d\n", dev, part); bootstage_error(BOOTSTAGE_ID_IDE_READ); return 1; diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 86e694ac69c..5190cc6c0fe 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -288,9 +288,10 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (size_t)255)); } else { tmp = getenv("bootdev"); - if (tmp) - ptr = sprintf(build_buf, tmp); - else + if (tmp) { + strcpy(build_buf, tmp); + ptr = strlen(tmp); + } else printf("## VxWorks boot device not specified\n"); tmp = getenv("bootfile"); @@ -331,8 +332,10 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ptr += sprintf(build_buf + ptr, "tn=%s ", tmp); tmp = getenv("othbootargs"); - if (tmp) - ptr += sprintf(build_buf + ptr, tmp); + if (tmp) { + strcpy(build_buf + ptr, tmp); + ptr += strlen(tmp); + } memcpy((void *)bootaddr, build_buf, max(strlen(build_buf), (size_t)255)); diff --git a/common/cmd_fs.c b/common/cmd_fs.c index e146254f6d6..8f8f1b2bfcf 100644 --- a/common/cmd_fs.c +++ b/common/cmd_fs.c @@ -3,17 +3,7 @@ * * Inspired by cmd_ext_common.c, cmd_fat.c. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/common/cmd_ide.c b/common/cmd_ide.c index ecd3e9d64f0..f19a7ce42a7 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -79,8 +79,8 @@ static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len #ifdef CONFIG_ATAPI static void atapi_inquiry(block_dev_desc_t *dev_desc); -static ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt, - void *buffer); +static ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer); #endif @@ -187,6 +187,7 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (strcmp(argv[1], "read") == 0) { ulong addr = simple_strtoul(argv[2], NULL, 16); ulong cnt = simple_strtoul(argv[4], NULL, 16); + block_dev_desc_t *dev_desc; ulong n; #ifdef CONFIG_SYS_64BIT_LBA @@ -201,9 +202,9 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) curr_device, blk, cnt); #endif - n = ide_dev_desc[curr_device].block_read(curr_device, - blk, cnt, - (ulong *)addr); + dev_desc = &ide_dev_desc[curr_device]; + n = dev_desc->block_read(dev_desc, blk, cnt, + (ulong *)addr); /* flush cache after read */ flush_cache(addr, cnt * ide_dev_desc[curr_device].blksz); @@ -230,7 +231,8 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) printf("\nIDE write: device %d block # %ld, count %ld ... ", curr_device, blk, cnt); #endif - n = ide_write(curr_device, blk, cnt, (ulong *) addr); + n = ide_write(&ide_dev_desc[curr_device], blk, cnt, + (ulong *)addr); printf("%ld blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); @@ -711,8 +713,10 @@ static void ide_ident(block_dev_desc_t *dev_desc) /* ------------------------------------------------------------------------- */ -ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer) +ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer) { + int device = block_dev->dev; ulong n = 0; unsigned char c; unsigned char pwrsave = 0; /* power save */ @@ -835,8 +839,10 @@ IDE_READ_E: /* ------------------------------------------------------------------------- */ -ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) +ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, + const void *buffer) { + int device = block_dev->dev; ulong n = 0; unsigned char c; @@ -1388,8 +1394,10 @@ static void atapi_inquiry(block_dev_desc_t *dev_desc) #define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */ #define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE) -ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer) +ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer) { + int device = block_dev->dev; ulong n = 0; unsigned char ccb[12]; /* Command descriptor block */ ulong cnt; diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a6b7313e4a4..1c7156f19c5 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -312,20 +312,14 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; } /* Switch to the RPMB partition */ - original_part = mmc->part_num; - if (mmc->part_num != MMC_PART_RPMB) { - if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0) - return CMD_RET_FAILURE; - mmc->part_num = MMC_PART_RPMB; - } + original_part = mmc->block_dev.part_num; + if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0) + return CMD_RET_FAILURE; ret = cp->cmd(cmdtp, flag, argc, argv); /* Return to original partition */ - if (mmc->part_num != original_part) { - if (mmc_switch_part(curr_device, original_part) != 0) - return CMD_RET_FAILURE; - mmc->part_num = original_part; - } + if (mmc_select_hwpart(curr_device, original_part) != 0) + return CMD_RET_FAILURE; return ret; } #endif @@ -351,7 +345,7 @@ static int do_mmc_read(cmd_tbl_t *cmdtp, int flag, printf("\nMMC read: dev # %d, block # %d, count %d ... ", curr_device, blk, cnt); - n = mmc->block_dev.block_read(curr_device, blk, cnt, addr); + n = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); /* FIXME */ printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); @@ -383,7 +377,7 @@ static int do_mmc_write(cmd_tbl_t *cmdtp, int flag, printf("Error: card is write protected!\n"); return CMD_RET_FAILURE; } - n = mmc->block_dev.block_write(curr_device, blk, cnt, addr); + n = mmc->block_dev.block_write(&mmc->block_dev, blk, cnt, addr); printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; @@ -411,7 +405,7 @@ static int do_mmc_erase(cmd_tbl_t *cmdtp, int flag, printf("Error: card is write protected!\n"); return CMD_RET_FAILURE; } - n = mmc->block_dev.block_erase(curr_device, blk, cnt); + n = mmc->block_dev.block_erase(&mmc->block_dev, blk, cnt); printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR"); return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; @@ -483,7 +477,7 @@ static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag, printf("mmc%d is current device\n", curr_device); else printf("mmc%d(part %d) is current device\n", - curr_device, mmc->part_num); + curr_device, mmc->block_dev.hwpart); return CMD_RET_SUCCESS; } diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 422c0695138..dab195841a7 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -1086,7 +1086,7 @@ static int generate_mtdparts(char *buf, u32 buflen) return 0; } - sprintf(p, "mtdparts="); + strcpy(p, "mtdparts="); p += 9; list_for_each(dentry, &devices) { diff --git a/common/cmd_read.c b/common/cmd_read.c index f0fc9bfe17a..87102887817 100644 --- a/common/cmd_read.c +++ b/common/cmd_read.c @@ -66,7 +66,7 @@ int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - if (dev_desc->block_read(dev, offset + blk, cnt, addr) < 0) { + if (dev_desc->block_read(dev_desc, offset + blk, cnt, addr) < 0) { printf("Error reading blocks\n"); return 1; } diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 51f67033ae3..76baceae8c9 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -18,6 +18,18 @@ static int sata_curr_device = -1; block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; +static unsigned long sata_bread(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, void *dst) +{ + return sata_read(block_dev->dev, start, blkcnt, dst); +} + +static unsigned long sata_bwrite(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *buffer) +{ + return sata_write(block_dev->dev, start, blkcnt, buffer); +} + int __sata_initialize(void) { int rc; @@ -32,8 +44,8 @@ int __sata_initialize(void) sata_dev_desc[i].lba = 0; sata_dev_desc[i].blksz = 512; sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz); - sata_dev_desc[i].block_read = sata_read; - sata_dev_desc[i].block_write = sata_write; + sata_dev_desc[i].block_read = sata_bread; + sata_dev_desc[i].block_write = sata_bwrite; rc = init_sata(i); if (!rc) { diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 86954089fe7..bc7d1b6c530 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -66,9 +66,9 @@ void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz); -static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, - void *buffer); -static ulong scsi_write(int device, lbaint_t blknr, +static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer); +static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer); @@ -346,7 +346,8 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ulong n; printf ("\nSCSI read: device %d block # %ld, count %ld ... ", scsi_curr_dev, blk, cnt); - n = scsi_read(scsi_curr_dev, blk, cnt, (ulong *)addr); + n = scsi_read(&scsi_dev_desc[scsi_curr_dev], + blk, cnt, (ulong *)addr); printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR"); return 0; } else if (strcmp(argv[1], "write") == 0) { @@ -357,8 +358,8 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\nSCSI write: device %d block # %ld, " "count %ld ... ", scsi_curr_dev, blk, cnt); - n = scsi_write(scsi_curr_dev, blk, cnt, - (ulong *)addr); + n = scsi_write(&scsi_dev_desc[scsi_curr_dev], + blk, cnt, (ulong *)addr); printf("%ld blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); return 0; @@ -375,9 +376,10 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #define SCSI_MAX_READ_BLK 0xFFFF #define SCSI_LBA48_READ 0xFFFFFFF -static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, - void *buffer) +static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer) { + int device = block_dev->dev; lbaint_t start, blks; uintptr_t buf_addr; unsigned short smallblks = 0; @@ -441,9 +443,10 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, /* Almost the maximum amount of the scsi_ext command.. */ #define SCSI_MAX_WRITE_BLK 0xFFFF -static ulong scsi_write(int device, lbaint_t blknr, +static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) { + int device = block_dev->dev; lbaint_t start, blks; uintptr_t buf_addr; unsigned short smallblks; diff --git a/common/cmd_usb.c b/common/cmd_usb.c index a540b422db3..c7b642c40af 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -759,7 +759,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\nUSB read: device %d block # %ld, count %ld" " ... ", usb_stor_curr_dev, blk, cnt); stor_dev = usb_stor_get_dev(usb_stor_curr_dev); - n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt, + n = stor_dev->block_read(stor_dev, blk, cnt, (ulong *)addr); printf("%ld blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); @@ -781,7 +781,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\nUSB write: device %d block # %ld, count %ld" " ... ", usb_stor_curr_dev, blk, cnt); stor_dev = usb_stor_get_dev(usb_stor_curr_dev); - n = stor_dev->block_write(usb_stor_curr_dev, blk, cnt, + n = stor_dev->block_write(stor_dev, blk, cnt, (ulong *)addr); printf("%ld blocks write: %s\n", n, (n == cnt) ? "OK" : "ERROR"); diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c index 04073891129..041559172d9 100644 --- a/common/cmd_usb_mass_storage.c +++ b/common/cmd_usb_mass_storage.c @@ -2,6 +2,8 @@ * Copyright (C) 2011 Samsung Electronics * Lukasz Majewski <l.majewski@samsung.com> * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,50 +19,107 @@ static int ums_read_sector(struct ums *ums_dev, ulong start, lbaint_t blkcnt, void *buf) { - block_dev_desc_t *block_dev = ums_dev->block_dev; + block_dev_desc_t *block_dev = &ums_dev->block_dev; lbaint_t blkstart = start + ums_dev->start_sector; - int dev_num = block_dev->dev; - return block_dev->block_read(dev_num, blkstart, blkcnt, buf); + return block_dev->block_read(block_dev, blkstart, blkcnt, buf); } static int ums_write_sector(struct ums *ums_dev, ulong start, lbaint_t blkcnt, const void *buf) { - block_dev_desc_t *block_dev = ums_dev->block_dev; + block_dev_desc_t *block_dev = &ums_dev->block_dev; lbaint_t blkstart = start + ums_dev->start_sector; - int dev_num = block_dev->dev; - return block_dev->block_write(dev_num, blkstart, blkcnt, buf); + return block_dev->block_write(block_dev, blkstart, blkcnt, buf); +} + +static struct ums *ums; +static int ums_count; + +static void ums_fini(void) +{ + int i; + + for (i = 0; i < ums_count; i++) + free((void *)ums[i].name); + free(ums); + ums = 0; + ums_count = 0; } -static struct ums ums_dev = { - .read_sector = ums_read_sector, - .write_sector = ums_write_sector, - .name = "UMS disk", -}; +#define UMS_NAME_LEN 16 -struct ums *ums_init(const char *devtype, const char *devnum) +static int ums_init(const char *devtype, const char *devnums) { + char *s, *t, *devnum, *name; block_dev_desc_t *block_dev; int ret; + struct ums *ums_new; - ret = get_device(devtype, devnum, &block_dev); - if (ret < 0) - return NULL; + s = strdup(devnums); + if (!s) + return -1; + + t = s; + ums_count = 0; + + for (;;) { + devnum = strsep(&t, ","); + if (!devnum) + break; + + ret = get_device(devtype, devnum, &block_dev); + if (ret < 0) + goto cleanup; + + /* f_mass_storage.c assumes SECTOR_SIZE sectors */ + if (block_dev->blksz != SECTOR_SIZE) { + ret = -1; + goto cleanup; + } - /* f_mass_storage.c assumes SECTOR_SIZE sectors */ - if (block_dev->blksz != SECTOR_SIZE) - return NULL; + ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums)); + if (!ums_new) { + ret = -1; + goto cleanup; + } + ums = ums_new; + + ums[ums_count].read_sector = ums_read_sector; + ums[ums_count].write_sector = ums_write_sector; + ums[ums_count].start_sector = 0; + ums[ums_count].num_sectors = block_dev->lba; + name = malloc(UMS_NAME_LEN); + if (!name) { + ret = -1; + goto cleanup; + } + snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count); + ums[ums_count].name = name; + ums[ums_count].block_dev = *block_dev; + + printf("UMS: LUN %d, dev %d, hwpart %d, sector %#x, count %#x\n", + ums_count, ums[ums_count].block_dev.dev, + ums[ums_count].block_dev.hwpart, + ums[ums_count].start_sector, + ums[ums_count].num_sectors); + + ums_count++; + } + + if (!ums_count) + ret = -1; + else + ret = 0; - ums_dev.block_dev = block_dev; - ums_dev.start_sector = 0; - ums_dev.num_sectors = block_dev->lba; +cleanup: + free(s); - printf("UMS: disk start sector: %#x, count: %#x\n", - ums_dev.start_sector, ums_dev.num_sectors); + if (ret < 0) + ums_fini(); - return &ums_dev; + return ret; } int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, @@ -69,7 +128,6 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, const char *usb_controller; const char *devtype; const char *devnum; - struct ums *ums; unsigned int controller_index; int rc; int cable_ready_timeout __maybe_unused; @@ -86,27 +144,30 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, devnum = argv[2]; } - ums = ums_init(devtype, devnum); - if (!ums) + rc = ums_init(devtype, devnum); + if (rc < 0) return CMD_RET_FAILURE; controller_index = (unsigned int)(simple_strtoul( usb_controller, NULL, 0)); if (board_usb_init(controller_index, USB_INIT_DEVICE)) { error("Couldn't init USB controller."); - return CMD_RET_FAILURE; + rc = CMD_RET_FAILURE; + goto cleanup_ums_init; } - rc = fsg_init(ums); + rc = fsg_init(ums, ums_count); if (rc) { error("fsg_init failed"); - return CMD_RET_FAILURE; + rc = CMD_RET_FAILURE; + goto cleanup_board; } rc = g_dnl_register("usb_dnl_ums"); if (rc) { error("g_dnl_register failed"); - return CMD_RET_FAILURE; + rc = CMD_RET_FAILURE; + goto cleanup_board; } /* Timeout unit: seconds */ @@ -122,12 +183,14 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, while (!g_dnl_board_usb_cable_connected()) { if (ctrlc()) { puts("\rCTRL+C - Operation aborted.\n"); - goto exit; + rc = CMD_RET_SUCCESS; + goto cleanup_register; } if (!cable_ready_timeout) { puts("\rUSB cable not detected.\n" \ "Command exit.\n"); - goto exit; + rc = CMD_RET_SUCCESS; + goto cleanup_register; } printf("\rAuto exit in: %.2d s.", cable_ready_timeout); @@ -150,13 +213,19 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, if (rc == -EPIPE) printf("\rCTRL+C - Operation aborted\n"); - goto exit; + rc = CMD_RET_SUCCESS; + goto cleanup_register; } } -exit: + +cleanup_register: g_dnl_unregister(); +cleanup_board: board_usb_cleanup(controller_index, USB_INIT_DEVICE); - return CMD_RET_SUCCESS; +cleanup_ums_init: + ums_fini(); + + return rc; } U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage, diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 438e71afd20..0aa1cbf5f1c 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/common/env_flags.c b/common/env_flags.c index 771935508cb..9c3aed15278 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -152,7 +152,7 @@ enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags) { int i; - for (i = 0; i < sizeof(env_flags_varaccess_mask); i++) + for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++) if (env_flags_varaccess_mask[i] == (binflags & ENV_FLAGS_VARACCESS_BIN_MASK)) return (enum env_flags_varaccess)i; diff --git a/common/env_mmc.c b/common/env_mmc.c index 96398224cc8..15aa43d5e16 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -69,6 +69,8 @@ __weak uint mmc_get_env_part(struct mmc *mmc) return CONFIG_SYS_MMC_ENV_PART; } +static unsigned char env_mmc_orig_hwpart; + static int mmc_set_env_part(struct mmc *mmc) { uint part = mmc_get_env_part(mmc); @@ -79,11 +81,10 @@ static int mmc_set_env_part(struct mmc *mmc) dev = 0; #endif - if (part != mmc->part_num) { - ret = mmc_switch_part(dev, part); - if (ret) - puts("MMC partition switch failed\n"); - } + env_mmc_orig_hwpart = mmc->block_dev.hwpart; + ret = mmc_select_hwpart(dev, part); + if (ret) + puts("MMC partition switch failed\n"); return ret; } @@ -113,8 +114,7 @@ static void fini_mmc_for_env(struct mmc *mmc) #ifdef CONFIG_SPL_BUILD dev = 0; #endif - if (mmc_get_env_part(mmc) != mmc->part_num) - mmc_switch_part(dev, mmc->part_num); + mmc_select_hwpart(dev, env_mmc_orig_hwpart); #endif } @@ -127,7 +127,7 @@ static inline int write_env(struct mmc *mmc, unsigned long size, blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len; blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len; - n = mmc->block_dev.block_write(CONFIG_SYS_MMC_ENV_DEV, blk_start, + n = mmc->block_dev.block_write(&mmc->block_dev, blk_start, blk_cnt, (u_char *)buffer); return (n == blk_cnt) ? 0 : -1; @@ -192,16 +192,12 @@ static inline int read_env(struct mmc *mmc, unsigned long size, unsigned long offset, const void *buffer) { uint blk_start, blk_cnt, n; - int dev = CONFIG_SYS_MMC_ENV_DEV; - -#ifdef CONFIG_SPL_BUILD - dev = 0; -#endif blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer); + n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, + (uchar *)buffer); return (n == blk_cnt) ? 0 : -1; } diff --git a/common/fb_mmc.c b/common/fb_mmc.c index b480e76554b..6e742dac56f 100644 --- a/common/fb_mmc.c +++ b/common/fb_mmc.c @@ -58,7 +58,7 @@ static int fb_mmc_sparse_write(struct sparse_storage *storage, block_dev_desc_t *dev_desc = sparse->dev_desc; int ret; - ret = dev_desc->block_write(dev_desc->dev, offset, size, data); + ret = dev_desc->block_write(dev_desc, offset, size, data); if (!ret) return -EIO; @@ -84,8 +84,7 @@ static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, puts("Flashing Raw Image\n"); - blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt, - buffer); + blks = dev_desc->block_write(dev_desc, info->start, blkcnt, buffer); if (blks != blkcnt) { error("failed writing to device %d\n", dev_desc->dev); fastboot_fail(response_str, "failed writing to device"); @@ -206,7 +205,7 @@ void fb_mmc_erase(const char *cmd, char *response) printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", blks_start, blks_start + blks_size); - blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size); + blks = dev_desc->block_erase(dev_desc, blks_start, blks_size); if (blks != blks_size) { error("failed erasing from device %d", dev_desc->dev); fastboot_fail(response_str, "failed erasing from device"); diff --git a/common/fdt_support.c b/common/fdt_support.c index a539389a9e8..09f923716ca 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -482,47 +482,49 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size) void fdt_fixup_ethernet(void *fdt) { int node, i, j; - char enet[16], *tmp, *end; + char *tmp, *end; char mac[16]; const char *path; unsigned char mac_addr[6]; + int offset; node = fdt_path_offset(fdt, "/aliases"); if (node < 0) return; - if (!getenv("ethaddr")) { - if (getenv("usbethaddr")) { - strcpy(mac, "usbethaddr"); - } else { - debug("No ethernet MAC Address defined\n"); - return; - } - } else { - strcpy(mac, "ethaddr"); - } - - i = 0; - while ((tmp = getenv(mac)) != NULL) { - sprintf(enet, "ethernet%d", i); - path = fdt_getprop(fdt, node, enet, NULL); - if (!path) { - debug("No alias for %s\n", enet); - sprintf(mac, "eth%daddr", ++i); - continue; - } + for (offset = fdt_first_property_offset(fdt, node); + offset > 0; + offset = fdt_next_property_offset(fdt, offset)) { + const char *name; + int len = strlen("ethernet"); + + path = fdt_getprop_by_offset(fdt, offset, &name, NULL); + if (!strncmp(name, "ethernet", len)) { + i = trailing_strtol(name); + if (i != -1) { + if (i == 0) + strcpy(mac, "ethaddr"); + else + sprintf(mac, "eth%daddr", i); + } else { + continue; + } + tmp = getenv(mac); + if (!tmp) + continue; + + for (j = 0; j < 6; j++) { + mac_addr[j] = tmp ? + simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end + 1 : end; + } - for (j = 0; j < 6; j++) { - mac_addr[j] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; + do_fixup_by_path(fdt, path, "mac-address", + &mac_addr, 6, 0); + do_fixup_by_path(fdt, path, "local-mac-address", + &mac_addr, 6, 1); } - - do_fixup_by_path(fdt, path, "mac-address", &mac_addr, 6, 0); - do_fixup_by_path(fdt, path, "local-mac-address", - &mac_addr, 6, 1); - - sprintf(mac, "eth%daddr", ++i); } } diff --git a/common/hash.c b/common/hash.c index a1b048204d3..41de4df5368 100644 --- a/common/hash.c +++ b/common/hash.c @@ -247,6 +247,29 @@ int hash_parse_string(const char *algo_name, const char *str, uint8_t *result) return 0; } +int hash_block(const char *algo_name, const void *data, unsigned int len, + uint8_t *output, int *output_size) +{ + struct hash_algo *algo; + int ret; + + ret = hash_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + if (output_size && *output_size < algo->digest_size) { + debug("Output buffer size %d too small (need %d bytes)", + *output_size, algo->digest_size); + return -ENOSPC; + } + if (output_size) + *output_size = algo->digest_size; + algo->hash_func_ws(data, len, output, algo->chunk_size); + + return 0; +} + +#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32) /** * store_result: Store the resulting sum to an address or variable * @@ -359,7 +382,7 @@ static int parse_verify_sum(struct hash_algo *algo, char *verify_str, return 0; } -void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output) +static void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output) { int i; @@ -368,28 +391,6 @@ void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output) printf("%02x", output[i]); } -int hash_block(const char *algo_name, const void *data, unsigned int len, - uint8_t *output, int *output_size) -{ - struct hash_algo *algo; - int ret; - - ret = hash_lookup_algo(algo_name, &algo); - if (ret) - return ret; - - if (output_size && *output_size < algo->digest_size) { - debug("Output buffer size %d too small (need %d bytes)", - *output_size, algo->digest_size); - return -ENOSPC; - } - if (output_size) - *output_size = algo->digest_size; - algo->hash_func_ws(data, len, output, algo->chunk_size); - - return 0; -} - int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -473,3 +474,4 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, return 0; } #endif +#endif diff --git a/common/image.c b/common/image.c index c36927fca8e..f4a1dc8e251 100644 --- a/common/image.c +++ b/common/image.c @@ -472,9 +472,9 @@ phys_size_t getenv_bootm_size(void) #if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS) - return gd->bd->bi_dram[0].size - tmp; + return gd->bd->bi_dram[0].size - (tmp - gd->bd->bi_dram[0].start); #else - return gd->bd->bi_memsize - tmp; + return gd->bd->bi_memsize - (tmp - gd->bd->bi_memstart); #endif } @@ -1113,8 +1113,7 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, if (initrd_high == ~0) initrd_copy_to_ram = 0; } else { - /* not set, no restrictions to load high */ - initrd_high = ~0; + initrd_high = getenv_bootm_mapsize() + getenv_bootm_low(); } diff --git a/common/init/board_init.c b/common/init/board_init.c index 1c6126d8ce5..d17bb298d72 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -21,39 +21,128 @@ DECLARE_GLOBAL_DATA_PTR; #define _USE_MEMCPY #endif -/* Unfortunately x86 can't compile this code as gd cannot be assigned */ -#ifndef CONFIG_X86 +/* Unfortunately x86 or ARM can't compile this code as gd cannot be assigned */ +#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) __weak void arch_setup_gd(struct global_data *gd_ptr) { gd = gd_ptr; } -#endif /* !CONFIG_X86 */ +#endif /* !CONFIG_X86 && !CONFIG_ARM */ -ulong board_init_f_mem(ulong top) +/* + * Allocate reserved space for use as 'globals' from 'top' address and + * return 'bottom' address of allocated space + * + * Notes: + * + * Actual reservation cannot be done from within this function as + * it requires altering the C stack pointer, so this will be done by + * the caller upon return from this function. + * + * IMPORTANT: + * + * Alignment constraints may differ for each 'chunk' allocated. For now: + * + * - GD is aligned down on a 16-byte boundary + * + * - the early malloc arena is not aligned, therefore it follows the stack + * alignment constraint of the architecture for which we are bulding. + * + * - GD is allocated last, so that the return value of this functions is + * both the bottom of the reserved area and the address of GD, should + * the calling context need it. + */ + +ulong board_init_f_alloc_reserve(ulong top) +{ + /* Reserve early malloc arena */ +#if defined(CONFIG_SYS_MALLOC_F) + top -= CONFIG_SYS_MALLOC_F_LEN; +#endif + /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */ + top = rounddown(top-sizeof(struct global_data), 16); + + return top; +} + +/* + * Initialize reserved space (which has been safely allocated on the C + * stack from the C runtime environment handling code). + * + * Notes: + * + * Actual reservation was done by the caller; the locations from base + * to base+size-1 (where 'size' is the value returned by the allocation + * function above) can be accessed freely without risk of corrupting the + * C runtime environment. + * + * IMPORTANT: + * + * Upon return from the allocation function above, on some architectures + * the caller will set gd to the lowest reserved location. Therefore, in + * this initialization function, the global data MUST be placed at base. + * + * ALSO IMPORTANT: + * + * On some architectures, gd will already be good when entering this + * function. On others, it will only be good once arch_setup_gd() returns. + * Therefore, global data accesses must be done: + * + * - through gd_ptr if before the call to arch_setup_gd(); + * + * - through gd once arch_setup_gd() has been called. + * + * Do not use 'gd->' until arch_setup_gd() has been called! + * + * IMPORTANT TOO: + * + * Initialization for each "chunk" (GD, early malloc arena...) ends with + * an incrementation line of the form 'base += <some size>'. The last of + * these incrementations seems useless, as base will not be used any + * more after this incrementation; but if/when a new "chunk" is appended, + * this increment will be essential as it will give base right value for + * this new chunk (which will have to end with its own incrementation + * statement). Besides, the compiler's optimizer will silently detect + * and remove the last base incrementation, therefore leaving that last + * (seemingly useless) incrementation causes no code increase. + */ + +void board_init_f_init_reserve(ulong base) { struct global_data *gd_ptr; #ifndef _USE_MEMCPY int *ptr; #endif - /* Leave space for the stack we are running with now */ - top -= 0x40; + /* + * clear GD entirely and set it up. + * Use gd_ptr, as gd may not be properly set yet. + */ - top -= sizeof(struct global_data); - top = ALIGN(top, 16); - gd_ptr = (struct global_data *)top; + gd_ptr = (struct global_data *)base; + /* zero the area */ #ifdef _USE_MEMCPY memset(gd_ptr, '\0', sizeof(*gd)); #else for (ptr = (int *)gd_ptr; ptr < (int *)(gd_ptr + 1); ) *ptr++ = 0; #endif + /* set GD unless architecture did it already */ +#if !defined(CONFIG_ARM) arch_setup_gd(gd_ptr); +#endif + /* next alloc will be higher by one GD plus 16-byte alignment */ + base += roundup(sizeof(struct global_data), 16); + + /* + * record early malloc arena start. + * Use gd as it is now properly set for all architectures. + */ #if defined(CONFIG_SYS_MALLOC_F) - top -= CONFIG_SYS_MALLOC_F_LEN; - gd->malloc_base = top; + /* go down one 'early malloc arena' */ + gd->malloc_base = base; + /* next alloc will be higher by one 'early malloc arena' size */ + base += CONFIG_SYS_MALLOC_F_LEN; #endif - - return top; } diff --git a/common/spl/spl.c b/common/spl/spl.c index 6e6dee7ec9b..e5167bf73e4 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -431,8 +431,13 @@ void preloader_console_init(void) * more stack space for things like the MMC sub-system. * * This function calculates the stack position, copies the global_data into - * place and returns the new stack position. The caller is responsible for - * setting up the sp register. + * place, sets the new gd (except for ARM, for which setting GD within a C + * function may not always work) and returns the new stack position. The + * caller is responsible for setting up the sp register and, in the case + * of ARM, setting up gd. + * + * All of this is done using the same layout and alignments as done in + * board_init_f_init_reserve() / board_init_f_alloc_reserve(). * * @return new stack location, or 0 to use the same stack */ @@ -440,14 +445,7 @@ ulong spl_relocate_stack_gd(void) { #ifdef CONFIG_SPL_STACK_R gd_t *new_gd; - ulong ptr; - - /* Get stack position: use 8-byte alignment for ABI compliance */ - ptr = CONFIG_SPL_STACK_R_ADDR - sizeof(gd_t); - ptr &= ~7; - new_gd = (gd_t *)ptr; - memcpy(new_gd, (void *)gd, sizeof(gd_t)); - gd = new_gd; + ulong ptr = CONFIG_SPL_STACK_R_ADDR; #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) { @@ -460,7 +458,13 @@ ulong spl_relocate_stack_gd(void) gd->malloc_ptr = 0; } #endif - + /* Get stack position: use 8-byte alignment for ABI compliance */ + ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16); + new_gd = (gd_t *)ptr; + memcpy(new_gd, (void *)gd, sizeof(gd_t)); +#if !defined(CONFIG_ARM) + gd = new_gd; +#endif return ptr; #else return 0; diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index c1c29c02d7e..c3931c6c4d7 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -23,13 +23,12 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) unsigned long count; u32 image_size_sectors; struct image_header *header; - int dev_num = mmc->block_dev.dev; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - sizeof(struct image_header)); /* read image header to find the image size & load address */ - count = mmc->block_dev.block_read(dev_num, sector, 1, header); + count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header); debug("read sector %lx, count=%lu\n", sector, count); if (count == 0) goto end; @@ -46,7 +45,8 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) mmc->read_bl_len; /* Read the header too to avoid extra memcpy */ - count = mmc->block_dev.block_read(dev_num, sector, image_size_sectors, + count = mmc->block_dev.block_read(&mmc->block_dev, sector, + image_size_sectors, (void *)(ulong)spl_image.load_addr); debug("read %x sectors to %x\n", image_size_sectors, spl_image.load_addr); @@ -150,8 +150,7 @@ static int mmc_load_image_raw_os(struct mmc *mmc) { unsigned long count; - count = mmc->block_dev.block_read( - mmc->block_dev.dev, + count = mmc->block_dev.block_read(&mmc->block_dev, CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, (void *) CONFIG_SYS_SPL_ARGS_ADDR); diff --git a/common/usb.c b/common/usb.c index 9f67cc1e8e8..c7b8b0ee5a8 100644 --- a/common/usb.c +++ b/common/usb.c @@ -456,7 +456,7 @@ static int usb_parse_config(struct usb_device *dev, } epno = dev->config.if_desc[ifno].no_of_ep; if_desc = &dev->config.if_desc[ifno]; - if (epno > USB_MAXENDPOINTS) { + if (epno >= USB_MAXENDPOINTS) { printf("Interface %d has too many endpoints!\n", if_desc->desc.bInterfaceNumber); return -EINVAL; diff --git a/common/usb_storage.c b/common/usb_storage.c index e61a8c8adfd..4fdb55f9faf 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -119,10 +119,10 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss); -unsigned long usb_stor_read(int device, lbaint_t blknr, - lbaint_t blkcnt, void *buffer); -unsigned long usb_stor_write(int device, lbaint_t blknr, - lbaint_t blkcnt, const void *buffer); +static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer); +static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, const void *buffer); void uhci_show_temp_int_td(void); #ifdef CONFIG_PARTITIONS @@ -1027,9 +1027,10 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, } #endif /* CONFIG_USB_BIN_FIXUP */ -unsigned long usb_stor_read(int device, lbaint_t blknr, - lbaint_t blkcnt, void *buffer) +static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer) { + int device = block_dev->dev; lbaint_t start, blks; uintptr_t buf_addr; unsigned short smallblks; @@ -1097,9 +1098,10 @@ retry_it: return blkcnt; } -unsigned long usb_stor_write(int device, lbaint_t blknr, - lbaint_t blkcnt, const void *buffer) +static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr, + lbaint_t blkcnt, const void *buffer) { + int device = block_dev->dev; lbaint_t start, blks; uintptr_t buf_addr; unsigned short smallblks; diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index f30a7fbe339..7a125227ca8 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -1,4 +1,5 @@ CONFIG_M68K=y CONFIG_TARGET_M5208EVBE=y +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index b2ad88a66f2..711a411a52e 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M52277EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000" +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index ea393561f1b..05d20d6f02e 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M52277EVB=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000" +CONFIG_SYS_TEXT_BASE=0x43E00000 +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 5f381e230be..b8fb41333e0 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5235EVB=y -CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000" +CONFIG_SYS_TEXT_BASE=0xFFC00000 +CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index a10ae8d4d0d..fdf2dd00c61 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -1,6 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5235EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000" +CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index 1467b1674ac..2358d243da1 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -1,4 +1,5 @@ CONFIG_M68K=y CONFIG_TARGET_M5249EVB=y +CONFIG_SYS_TEXT_BASE=0xffe00000 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 89e7e75b096..c4da196c958 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -1,3 +1,4 @@ CONFIG_M68K=y CONFIG_TARGET_M5253DEMO=y +CONFIG_SYS_TEXT_BASE=0xFF800000 # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig index e337f32ebfa..2e82ccebea1 100644 --- a/configs/M5253EVBE_defconfig +++ b/configs/M5253EVBE_defconfig @@ -1,4 +1,5 @@ CONFIG_M68K=y CONFIG_TARGET_M5253EVBE=y +CONFIG_SYS_TEXT_BASE=0xFFE00000 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 6e9609f54bb..6153a5c817b 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5272C3=y +CONFIG_SYS_TEXT_BASE=0xffe00000 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 5eb237385ab..d70fea1a740 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5275EVB=y +CONFIG_SYS_TEXT_BASE=0xffe00000 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index e0af3883e53..10a3043f0b4 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5282EVB=y +CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index ca538f4b01c..e86fe5bac1d 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -1,4 +1,5 @@ CONFIG_M68K=y CONFIG_TARGET_M53017EVB=y +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index d5c6c7b2f5a..2379a1e68dc 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5329EVB=y +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 35242060bae..38a996b1e15 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5329EVB=y +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 2fdff5bd120..6595feb65c2 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5373EVB=y +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index 7c22abe61b2..62cebda43cb 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index 373845b4a01..de73e305ed5 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index 08c45b21d74..139811ce3e4 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index c5bf10e8230..a3cf48bb56e 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index 9e81827f813..ad29d52759e 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index 7c22abe61b2..62cebda43cb 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index 3b96dfb94c5..a9fe02f9cc6 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54451EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000" +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index 21a2687faa3..f10e86c587e 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54451EVB=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000" +CONFIG_SYS_TEXT_BASE=0x47e00000 +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index e8102732e94..30535140256 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666" +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 3d9cb12d606..9f70f7ed7c9 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333" +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index b5cbfdc4534..8421393339d 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666" +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index 8ed05a6fe1d..c63010884f1 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333" +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index 0a645801105..4e8aee40d46 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333" +CONFIG_SYS_TEXT_BASE=0x4FE00000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig index 11d14e62525..edfb9fc5cb3 100644 --- a/configs/M5475AFE_defconfig +++ b/configs/M5475AFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig index 24f42568ca4..5177eb92212 100644 --- a/configs/M5475BFE_defconfig +++ b/configs/M5475BFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig index a8996014ed3..431a264714c 100644 --- a/configs/M5475CFE_defconfig +++ b/configs/M5475CFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig index 66523cc4863..46d99649da6 100644 --- a/configs/M5475DFE_defconfig +++ b/configs/M5475DFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig index 410e150d5d1..4a2284d0851 100644 --- a/configs/M5475EFE_defconfig +++ b/configs/M5475EFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig index b590fd97633..f8d53beb922 100644 --- a/configs/M5475FFE_defconfig +++ b/configs/M5475FFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig index ea41ec204d8..61a3c56afcf 100644 --- a/configs/M5475GFE_defconfig +++ b/configs/M5475GFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig index e3f2f9e25ac..a8afe71a20e 100644 --- a/configs/M5485AFE_defconfig +++ b/configs/M5485AFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig index b3ec7ae6201..b9bdd4bab60 100644 --- a/configs/M5485BFE_defconfig +++ b/configs/M5485BFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig index 6637fdc5390..c5ec3965586 100644 --- a/configs/M5485CFE_defconfig +++ b/configs/M5485CFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig index 34dd51e957c..6872865f9c0 100644 --- a/configs/M5485DFE_defconfig +++ b/configs/M5485DFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig index 1f5c4ea5fdc..c0d1e068213 100644 --- a/configs/M5485EFE_defconfig +++ b/configs/M5485EFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig index 737411b2fc2..904a639fb24 100644 --- a/configs/M5485FFE_defconfig +++ b/configs/M5485FFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig index 2def6ea9baa..cb6f2c7e86d 100644 --- a/configs/M5485GFE_defconfig +++ b/configs/M5485GFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig index 4263f402469..a3ef2103899 100644 --- a/configs/M5485HFE_defconfig +++ b/configs/M5485HFE_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO" CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index 3030a95594b..8803da5b469 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -4,6 +4,10 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index ad40b077d83..5dcb942f390 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -8,6 +8,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 27cb88154d8..7753ab5d0ae 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -4,6 +4,10 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index a9b6f52117d..8f78eeb8b91 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -18,3 +18,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index ad69f0a23ff..9c8384944f7 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_AMCORE=y +CONFIG_SYS_TEXT_BASE=0xffc00000 CONFIG_SYS_PROMPT="amcore $ " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 38bb9abf233..25e4570b2c8 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index f462e059de2..0879d1e6a96 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -37,4 +37,3 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index dbfbb97d948..baa0ed84be8 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -38,5 +38,4 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y CONFIG_TPM=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index ed4428fe6d0..c368cc06c45 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -33,5 +33,4 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y CONFIG_TPM=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig new file mode 100644 index 00000000000..57d6a64b436 --- /dev/null +++ b/configs/clearfog_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_CLEARFOG=y +CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPI_FLASH=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 5cb6a802ab1..2e845e7e4b4 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_COBRA5272=y +CONFIG_SYS_TEXT_BASE=0xffe00000 CONFIG_SYS_PROMPT="COBRA > " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index cd2be18ac4a..fda0db20236 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -25,5 +25,4 @@ CONFIG_TPM_TIS_LPC=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y CONFIG_TPM=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 932d9ecc447..6bc4b8d0bf4 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -36,4 +36,3 @@ CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index cdcd34cb478..111f3a14216 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_DB_88F6820_GP=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_SPL=y @@ -7,9 +8,14 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_TRANSLATE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 4c4329dc783..6dda2ae32b7 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -1,16 +1,23 @@ CONFIG_ARM=y CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_DB_MV784MP_GP=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_TRANSLATE=y CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 64a0fb01b36..ddf09fe5eb8 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -1,5 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_DEVKIT3250=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DM=y +CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_SPL=y # CONFIG_CMD_FPGA is not set diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig index 3205bd5754b..b57ecca6968 100644 --- a/configs/dra72_evm_defconfig +++ b/configs/dra72_evm_defconfig @@ -20,3 +20,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig index 394edbec2ea..6e5a7051a43 100644 --- a/configs/dra74_evm_defconfig +++ b/configs/dra74_evm_defconfig @@ -19,3 +19,5 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig new file mode 100644 index 00000000000..4c3c1df63da --- /dev/null +++ b/configs/ds414_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_DS414=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 52f4a24063b..1e204bff458 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_EB_CPU5282=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400" +CONFIG_SYS_TEXT_BASE=0xFF000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" CONFIG_SYS_PROMPT="\nEB+CPU5282> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 5af19a0694d..2db895ccf77 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -1,5 +1,6 @@ CONFIG_M68K=y CONFIG_TARGET_EB_CPU5282=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418" +CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 0604aa76a52..925d3eee928 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -28,4 +28,3 @@ CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig index b9e671144c3..a96c1309005 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep0020_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig index 011ebace822..cf3ee7995e8 100644 --- a/configs/igep0020_nand_defconfig +++ b/configs/igep0020_nand_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig index ba160ef13b5..b7f1d610844 100644 --- a/configs/igep0032_defconfig +++ b/configs/igep0032_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 921c6c43670..200c7a04261 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -1,14 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MAXBCM=y -CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_TRANSLATE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 54aa3ef3d26..ed336e6bc44 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -1,6 +1,7 @@ CONFIG_MICROBLAZE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_TARGET_MICROBLAZE_GENERIC=y +CONFIG_SYS_TEXT_BASE=0x29000000 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SPL=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 864fd1b72f9..af6a8ec3f23 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -39,4 +39,3 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 358caa51e7f..ea9ed874e8f 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -12,3 +12,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_R_I2C_ENABLE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 8c86931cf49..b0c935ca22c 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -30,4 +30,3 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 5c9e69af3b7..bd81ee6a1d0 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -6,5 +6,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index b8b267f371c..5d27909ebe7 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -6,5 +6,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set CONFIG_PHYS_TO_BUS=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 731fc258870..caa7336280a 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -76,7 +76,6 @@ CONFIG_USB_EMUL=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL=y -CONFIG_SYS_VSNPRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 68d12df404c..6e8976fcc35 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_SPL=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index accee924a32..e31aa716893 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index b4f41a939d1..59fbb2c3c12 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_SPL=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index fe940f967a6..aaba8cb29d5 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 3d98a636d91..a4f0835e9da 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -6,6 +6,7 @@ CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SR1500=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_SPL=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x00800000 # CONFIG_CMD_IMLS is not set diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 7512457d0bf..fb330e25ae3 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_STM32=y +CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index d59912c47ab..3f08cc1bd70 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -13,3 +13,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig new file mode 100644 index 00000000000..b7078e03906 --- /dev/null +++ b/configs/thunderx_88xx_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_TARGET_THUNDERX_88XX=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" +CONFIG_SYS_EXTRA_OPTIONS="ARM64" +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="ThunderX_88XX> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_DM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_BASE=0x87e024000000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_REGEX=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 1cad3a2d0c4..1a9097a9a68 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -1,5 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_WORK_92105=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DM=y +CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_SPL=y # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index e577c931735..30995babd4b 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 7d52d8e941b..339e399889b 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -8,4 +8,5 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 9d1b40d76ef..065f8551945 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -10,6 +10,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index bba91dfdfa7..1059689aad4 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 96f0a794a38..a9dbda5eaa0 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index b0c535e88e1..6ff00c64b42 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -12,4 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 7fb03eb0491..75d6c5531c9 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -10,4 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 67665127b5b..dd65929958e 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -12,4 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 058bb05ba65..73b17e20b27 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 231483e3dbd..577c5a958e1 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y diff --git a/disk/part.c b/disk/part.c index 909712e5011..1935b288410 100644 --- a/disk/part.c +++ b/disk/part.c @@ -493,6 +493,16 @@ int get_device(const char *ifname, const char *dev_hwpart_str, goto cleanup; } +#ifdef HAVE_BLOCK_DEVICE + /* + * Updates the partition table for the specified hw partition. + * Does not need to be done for hwpart 0 since it is default and + * already loaded. + */ + if(hwpart != 0) + init_part(*dev_desc); +#endif + cleanup: free(dup_str); return dev; diff --git a/disk/part_amiga.c b/disk/part_amiga.c index 260a3d5e87c..57c1b9d055f 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -140,8 +140,7 @@ struct rigid_disk_block *get_rdisk(block_dev_desc_t *dev_desc) for (i=0; i<limit; i++) { - ulong res = dev_desc->block_read(dev_desc->dev, i, 1, - (ulong *)block_buffer); + ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer); if (res == 1) { struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer; @@ -183,7 +182,7 @@ struct bootcode_block *get_bootcode(block_dev_desc_t *dev_desc) for (i = 0; i < limit; i++) { - ulong res = dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)block_buffer); + ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer); if (res == 1) { struct bootcode_block *boot = (struct bootcode_block *)block_buffer; @@ -258,7 +257,7 @@ static struct partition_block *find_partition(block_dev_desc_t *dev_desc, int pa while (block != 0xFFFFFFFF) { - ulong res = dev_desc->block_read(dev_desc->dev, block, 1, + ulong res = dev_desc->block_read(dev_desc, block, 1, (ulong *)block_buffer); if (res == 1) { @@ -354,8 +353,7 @@ void print_part_amiga (block_dev_desc_t *dev_desc) PRINTF("Trying to load block #0x%X\n", block); - res = dev_desc->block_read(dev_desc->dev, block, 1, - (ulong *)block_buffer); + res = dev_desc->block_read(dev_desc, block, 1, (ulong *)block_buffer); if (res == 1) { p = (struct partition_block *)block_buffer; diff --git a/disk/part_dos.c b/disk/part_dos.c index 89263d38aaa..08872d6a03f 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -26,7 +26,7 @@ /* Convert char[4] in little endian format to the host format integer */ -static inline int le32_to_int(unsigned char *le32) +static inline unsigned int le32_to_int(unsigned char *le32) { return ((le32[3] << 24) + (le32[2] << 16) + @@ -47,13 +47,14 @@ static inline int is_bootable(dos_partition_t *p) return p->boot_ind == 0x80; } -static void print_one_part(dos_partition_t *p, int ext_part_sector, +static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector, int part_num, unsigned int disksig) { - int lba_start = ext_part_sector + le32_to_int (p->start4); - int lba_size = le32_to_int (p->size4); + lbaint_t lba_start = ext_part_sector + le32_to_int (p->start4); + lbaint_t lba_size = le32_to_int (p->size4); - printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n", + printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength + "u\t%08x-%02x\t%02x%s%s\n", part_num, lba_start, lba_size, disksig, part_num, p->sys_ind, (is_extended(p->sys_ind) ? " Extd" : ""), (is_bootable(p) ? " Boot" : "")); @@ -90,7 +91,7 @@ int test_part_dos (block_dev_desc_t *dev_desc) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); - if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) + if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)buffer) != 1) return -1; if (test_block_type(buffer) != DOS_MBR) @@ -102,15 +103,17 @@ int test_part_dos (block_dev_desc_t *dev_desc) /* Print a partition that is relative to its Extended partition table */ static void print_partition_extended(block_dev_desc_t *dev_desc, - int ext_part_sector, int relative, + lbaint_t ext_part_sector, + lbaint_t relative, int part_num, unsigned int disksig) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; int i; - if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) { - printf ("** Can't read partition table on %d:%d **\n", + if (dev_desc->block_read(dev_desc, ext_part_sector, 1, + (ulong *)buffer) != 1) { + printf ("** Can't read partition table on %d:" LBAFU " **\n", dev_desc->dev, ext_part_sector); return; } @@ -149,7 +152,8 @@ static void print_partition_extended(block_dev_desc_t *dev_desc, pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); for (i = 0; i < 4; i++, pt++) { if (is_extended (pt->sys_ind)) { - int lba_start = le32_to_int (pt->start4) + relative; + lbaint_t lba_start + = le32_to_int (pt->start4) + relative; print_partition_extended(dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, @@ -163,8 +167,9 @@ static void print_partition_extended(block_dev_desc_t *dev_desc, /* Print a partition that is relative to its Extended partition table */ -static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector, - int relative, int part_num, +static int get_partition_info_extended (block_dev_desc_t *dev_desc, + lbaint_t ext_part_sector, + lbaint_t relative, int part_num, int which_part, disk_partition_t *info, unsigned int disksig) { @@ -173,8 +178,9 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part int i; int dos_type; - if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) { - printf ("** Can't read partition table on %d:%d **\n", + if (dev_desc->block_read(dev_desc, ext_part_sector, 1, + (ulong *)buffer) != 1) { + printf ("** Can't read partition table on %d:" LBAFU " **\n", dev_desc->dev, ext_part_sector); return -1; } @@ -231,7 +237,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part break; } /* sprintf(info->type, "%d, pt->sys_ind); */ - sprintf ((char *)info->type, "U-Boot"); + strcpy((char *)info->type, "U-Boot"); info->bootable = is_bootable(pt); #ifdef CONFIG_PARTITION_UUIDS sprintf(info->uuid, "%08x-%02x", disksig, part_num); @@ -250,7 +256,8 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); for (i = 0; i < 4; i++, pt++) { if (is_extended (pt->sys_ind)) { - int lba_start = le32_to_int (pt->start4) + relative; + lbaint_t lba_start + = le32_to_int (pt->start4) + relative; return get_partition_info_extended (dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, @@ -266,7 +273,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part info->size = dev_desc->lba; info->blksz = DOS_PART_DEFAULT_SECTOR; info->bootable = 0; - sprintf ((char *)info->type, "U-Boot"); + strcpy((char *)info->type, "U-Boot"); #ifdef CONFIG_PARTITION_UUIDS info->uuid[0] = 0; #endif diff --git a/disk/part_efi.c b/disk/part_efi.c index b1e01558a69..e1b58c54b45 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -281,7 +281,7 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->name, "%s", print_efiname(&gpt_pte[part - 1])); - sprintf((char *)info->type, "U-Boot"); + strcpy((char *)info->type, "U-Boot"); info->bootable = is_bootable(&gpt_pte[part - 1]); #ifdef CONFIG_PARTITION_UUIDS uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid, @@ -324,7 +324,7 @@ int test_part_efi(block_dev_desc_t * dev_desc) ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz); /* Read legacy MBR from block 0 and validate it */ - if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)legacymbr) != 1) + if ((dev_desc->block_read(dev_desc, 0, 1, (ulong *)legacymbr) != 1) || (is_pmbr_valid(legacymbr) != 1)) { return -1; } @@ -354,7 +354,7 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc) p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1; /* Write MBR sector to the MMC device */ - if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) { + if (dev_desc->block_write(dev_desc, 0, 1, p_mbr) != 1) { printf("** Can't write to device %d **\n", dev_desc->dev); return -1; @@ -386,22 +386,22 @@ int write_gpt_table(block_dev_desc_t *dev_desc, gpt_h->header_crc32 = cpu_to_le32(calc_crc32); /* Write the First GPT to the block right after the Legacy MBR */ - if (dev_desc->block_write(dev_desc->dev, 1, 1, gpt_h) != 1) + if (dev_desc->block_write(dev_desc, 1, 1, gpt_h) != 1) goto err; - if (dev_desc->block_write(dev_desc->dev, 2, pte_blk_cnt, gpt_e) + if (dev_desc->block_write(dev_desc, 2, pte_blk_cnt, gpt_e) != pte_blk_cnt) goto err; prepare_backup_gpt_header(gpt_h); - if (dev_desc->block_write(dev_desc->dev, + if (dev_desc->block_write(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba) + 1, pte_blk_cnt, gpt_e) != pte_blk_cnt) goto err; - if (dev_desc->block_write(dev_desc->dev, + if (dev_desc->block_write(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1, gpt_h) != 1) goto err; @@ -737,7 +737,7 @@ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) /* write MBR */ lba = 0; /* MBR is always at 0 */ cnt = 1; /* MBR (1 block) */ - if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) { + if (dev_desc->block_write(dev_desc, lba, cnt, buf) != cnt) { printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", __func__, "MBR", cnt, lba); return 1; @@ -746,7 +746,7 @@ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) /* write Primary GPT */ lba = GPT_PRIMARY_PARTITION_TABLE_LBA; cnt = 1; /* GPT Header (1 block) */ - if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) { + if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) { printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", __func__, "Primary GPT Header", cnt, lba); return 1; @@ -754,7 +754,7 @@ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) lba = le64_to_cpu(gpt_h->partition_entry_lba); cnt = gpt_e_blk_cnt; - if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) { + if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) { printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", __func__, "Primary GPT Entries", cnt, lba); return 1; @@ -765,7 +765,7 @@ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) /* write Backup GPT */ lba = le64_to_cpu(gpt_h->partition_entry_lba); cnt = gpt_e_blk_cnt; - if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) { + if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) { printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", __func__, "Backup GPT Entries", cnt, lba); return 1; @@ -773,7 +773,7 @@ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) lba = le64_to_cpu(gpt_h->my_lba); cnt = 1; /* GPT Header (1 block) */ - if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) { + if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) { printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", __func__, "Backup GPT Header", cnt, lba); return 1; @@ -843,8 +843,7 @@ static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba, } /* Read GPT Header from device */ - if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head) - != 1) { + if (dev_desc->block_read(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) { printf("*** ERROR: Can't read GPT header ***\n"); return 0; } @@ -881,6 +880,7 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, gpt_header * pgpt_head) { size_t count = 0, blk_cnt; + lbaint_t blk; gpt_entry *pte = NULL; if (!dev_desc || !pgpt_head) { @@ -909,12 +909,10 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, } /* Read GPT Entries from device */ + blk = le64_to_cpu(pgpt_head->partition_entry_lba); blk_cnt = BLOCK_CNT(count, dev_desc); - if (dev_desc->block_read (dev_desc->dev, - (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba), - (lbaint_t) (blk_cnt), pte) - != blk_cnt) { - + if (dev_desc->block_read(dev_desc, blk, (lbaint_t)blk_cnt, pte) + != blk_cnt) { printf("*** ERROR: Can't read GPT Entries ***\n"); free(pte); return NULL; diff --git a/disk/part_iso.c b/disk/part_iso.c index 2547c703db5..5f4bb182dd2 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -62,8 +62,8 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ /* the first sector (sector 0x10) must be a primary volume desc */ blkaddr=PVD_OFFSET; - if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1) - return (-1); + if (dev_desc->block_read(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1) + return -1; if(ppr->desctype!=0x01) { if(verb) printf ("** First descriptor is NOT a primary desc on %d:%d **\n", @@ -84,8 +84,8 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ PRINTF(" Lastsect:%08lx\n",lastsect); for(i=blkaddr;i<lastsect;i++) { PRINTF("Reading block %d\n", i); - if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1) - return (-1); + if (dev_desc->block_read(dev_desc, i, 1, (ulong *)tmpbuf) != 1) + return -1; if(ppr->desctype==0x00) break; /* boot entry found */ if(ppr->desctype==0xff) { @@ -104,7 +104,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ } bootaddr=le32_to_int(pbr->pointer); PRINTF(" Boot Entry at: %08lX\n",bootaddr); - if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1) { + if (dev_desc->block_read(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) { if(verb) printf ("** Can't read Boot Entry at %lX on %d:%d **\n", bootaddr,dev_desc->dev, part_num); @@ -137,7 +137,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ /* the validation entry seems to be ok, now search the "partition" */ entry_num=0; offset=0x20; - sprintf ((char *)info->type, "U-Boot"); + strcpy((char *)info->type, "U-Boot"); switch(dev_desc->if_type) { case IF_TYPE_IDE: case IF_TYPE_SATA: diff --git a/disk/part_mac.c b/disk/part_mac.c index 099e0a0035b..f3bc8dd5553 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -51,7 +51,8 @@ int test_part_mac (block_dev_desc_t *dev_desc) n = 1; /* assuming at least one partition */ for (i=1; i<=n; ++i) { - if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)mpart) != 1) || + if ((dev_desc->block_read(dev_desc, i, 1, + (ulong *)mpart) != 1) || (mpart->signature != MAC_PARTITION_MAGIC) ) { return (-1); } @@ -104,7 +105,7 @@ void print_part_mac (block_dev_desc_t *dev_desc) char c; printf ("%4ld: ", i); - if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)mpart) != 1) { + if (dev_desc->block_read(dev_desc, i, 1, (ulong *)mpart) != 1) { printf ("** Can't read Partition Map on %d:%ld **\n", dev_desc->dev, i); return; @@ -150,7 +151,7 @@ void print_part_mac (block_dev_desc_t *dev_desc) */ static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p) { - if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)ddb_p) != 1) { + if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)ddb_p) != 1) { printf ("** Can't read Driver Desriptor Block **\n"); return (-1); } @@ -178,7 +179,7 @@ static int part_mac_read_pdb (block_dev_desc_t *dev_desc, int part, mac_partitio * partition 1 first since this is the only way to * know how many partitions we have. */ - if (dev_desc->block_read (dev_desc->dev, n, 1, (ulong *)pdb_p) != 1) { + if (dev_desc->block_read(dev_desc, n, 1, (ulong *)pdb_p) != 1) { printf ("** Can't read Partition Map on %d:%d **\n", dev_desc->dev, n); return (-1); diff --git a/doc/README.arm64 b/doc/README.arm64 index 75586dbaa70..f32108feb77 100644 --- a/doc/README.arm64 +++ b/doc/README.arm64 @@ -36,11 +36,34 @@ Notes 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and aarch32 specific codes. +7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores + supporting 64k pages it allows usage of full 48+ virtual/physical addresses + + Enabling this option requires the following ones to be defined: + - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the + system memory map (start, length, attributes) + - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP + - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries + - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries + for the largest CONFIG_SYS_MEM_MAP entry + - CONFIG_COREID_MASK - the mask value used to get the core from the + MPIDR_EL1 register + - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level + page tables + - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block + entry from L2 page tables + - CONFIG_SYS_PGTABLE_SIZE - total size of the page table + - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3} + + + + Contributor =========== - Tom Rini <trini@ti.com> - Scott Wood <scottwood@freescale.com> - York Sun <yorksun@freescale.com> - Simon Glass <sjg@chromium.org> - Sharma Bhupesh <bhupesh.sharma@freescale.com> - Rob Herring <robherring2@gmail.com> + Tom Rini <trini@ti.com> + Scott Wood <scottwood@freescale.com> + York Sun <yorksun@freescale.com> + Simon Glass <sjg@chromium.org> + Sharma Bhupesh <bhupesh.sharma@freescale.com> + Rob Herring <robherring2@gmail.com> + Sergey Temerkhanov <s.temerkhanov@gmail.com> diff --git a/doc/README.x86 b/doc/README.x86 index 1271e5edea3..36aaef011de 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -295,9 +295,37 @@ show QEMU's VGA console window. Note this will disable QEMU's serial output. If you want to check both consoles, use '-serial stdio'. Multicore is also supported by QEMU via '-smp n' where n is the number of cores -to instantiate. Currently the default U-Boot built for QEMU supports 2 cores. -In order to support more cores, you need add additional cpu nodes in the device -tree and change CONFIG_MAX_CPUS accordingly. +to instantiate. Note, the maximum supported CPU number in QEMU is 255. + +The fw_cfg interface in QEMU also provides information about kernel data, initrd, +command-line arguments and more. U-Boot supports directly accessing these informtion +from fw_cfg interface, this saves the time of loading them from hard disk or +network again, through emulated devices. To use it , simply providing them in +QEMU command line: + +$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage + -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8 + +Note: -initrd and -smp are both optional + +Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel: + + => qfw +qfw - QEMU firmware interface + +Usage: +qfw <command> + - list : print firmware(s) currently loaded + - cpus : print online cpu number + - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot + +=> qfw load +loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50 + +Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot' +can be used to boot the kernel: + +=> zboot 02000000 - 04000000 1b1ab50 CPU Microcode ------------- diff --git a/drivers/Makefile b/drivers/Makefile index c9031f2ce87..00da40b704a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -14,8 +14,8 @@ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ddr/marvell/a38x/ -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ddr/marvell/axp/ +obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ +obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/ obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/ diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f161c01c67d..eb8bda9ab2c 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_MX51_PATA) += mxc_ata.o obj-$(CONFIG_PATA_BFIN) += pata_bfin.o obj-$(CONFIG_SATA_DWC) += sata_dwc.o +obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o obj-$(CONFIG_SATA_SIL) += sata_sil.o obj-$(CONFIG_IDE_SIL680) += sil680.o diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 52c16025f89..2c6d42410cb 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -13,7 +13,7 @@ #include <asm/arch/orion5x.h> #elif defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> -#elif defined(CONFIG_ARMADA_XP) +#elif defined(CONFIG_ARCH_MVEBU) #include <linux/mbus.h> #endif @@ -102,7 +102,7 @@ struct mvsata_port_registers { * Initialize SATA memory windows for Armada XP */ -#ifdef CONFIG_ARMADA_XP +#ifdef CONFIG_ARCH_MVEBU static void mvsata_ide_conf_mbus_windows(void) { const struct mbus_dram_target_info *dram; @@ -174,7 +174,7 @@ int ide_preinit(void) int ret = MVSATA_STATUS_TIMEOUT; int status; -#ifdef CONFIG_ARMADA_XP +#ifdef CONFIG_ARCH_MVEBU mvsata_ide_conf_mbus_windows(); #endif diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 73f4c4a9e98..170f0fa5bf2 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -22,9 +22,11 @@ static struct host_block_dev *find_host_device(int dev) return NULL; } -static unsigned long host_block_read(int dev, unsigned long start, - lbaint_t blkcnt, void *buffer) +static unsigned long host_block_read(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + void *buffer) { + int dev = block_dev->dev; struct host_block_dev *host_dev = find_host_device(dev); if (!host_dev) @@ -42,9 +44,11 @@ static unsigned long host_block_read(int dev, unsigned long start, return -1; } -static unsigned long host_block_write(int dev, unsigned long start, - lbaint_t blkcnt, const void *buffer) +static unsigned long host_block_write(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + const void *buffer) { + int dev = block_dev->dev; struct host_block_dev *host_dev = find_host_device(dev); if (os_lseek(host_dev->fd, start * host_dev->blk_dev.blksz, diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index 9e8b067cdc8..b14985a027d 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -626,7 +626,7 @@ int scan_sata(int dev) if (id[162] & 1) printf("supports DRM functions and may " "not be fully accessable.\n"); - sprintf(revbuf, "%s", "CFA"); + strcpy(revbuf, "CFA"); } else { if (ata_id_has_tpm(id)) printf("supports DRM functions and may " @@ -653,7 +653,7 @@ int scan_sata(int dev) ncq_desc[0] = '\0'; if (ata_dev->horkage & ATA_HORKAGE_NONCQ) - sprintf(ncq_desc, "%s", "NCQ (not used)"); + strcpy(ncq_desc, "NCQ (not used)"); if (ap.flags & ATA_FLAG_NCQ) ata_dev->flags |= ATA_DFLAG_NCQ; diff --git a/drivers/block/sata_mv.c b/drivers/block/sata_mv.c new file mode 100644 index 00000000000..88249341d64 --- /dev/null +++ b/drivers/block/sata_mv.c @@ -0,0 +1,1045 @@ +/* + * Copyright (C) Excito Elektronik i Skåne AB, 2010. + * Author: Tor Krill <tor@excito.com> + * + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This driver supports the SATA controller of some Mavell SoC's. + * Here a (most likely incomplete) list of the supported SoC's: + * - Kirkwood + * - Armada 370 + * - Armada XP + * + * This driver implementation is an alternative to the already available + * driver via the "ide" commands interface (drivers/block/mvsata_ide.c). + * But this driver only supports PIO mode and as this new driver also + * supports transfer via DMA, its much faster. + * + * Please note, that the newer SoC's (e.g. Armada 38x) are not supported + * by this driver. As they have an AHCI compatible SATA controller + * integrated. + */ + +/* + * TODO: + * Better error recovery + * No support for using PRDs (Thus max 64KB transfers) + * No NCQ support + * No port multiplier support + */ + +#include <common.h> +#include <fis.h> +#include <libata.h> +#include <malloc.h> +#include <sata.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <linux/mbus.h> + +#if defined(CONFIG_KIRKWOOD) +#include <asm/arch/kirkwood.h> +#define SATAHC_BASE KW_SATA_BASE +#else +#include <asm/arch/soc.h> +#define SATAHC_BASE MVEBU_AXP_SATA_BASE +#endif + +#define SATA0_BASE (SATAHC_BASE + 0x2000) +#define SATA1_BASE (SATAHC_BASE + 0x4000) + +/* EDMA registers */ +#define EDMA_CFG 0x000 +#define EDMA_CFG_NCQ (1 << 5) +#define EDMA_CFG_EQUE (1 << 9) +#define EDMA_TIMER 0x004 +#define EDMA_IECR 0x008 +#define EDMA_IEMR 0x00c +#define EDMA_RQBA_HI 0x010 +#define EDMA_RQIPR 0x014 +#define EDMA_RQIPR_IPMASK (0x1f << 5) +#define EDMA_RQIPR_IPSHIFT 5 +#define EDMA_RQOPR 0x018 +#define EDMA_RQOPR_OPMASK (0x1f << 5) +#define EDMA_RQOPR_OPSHIFT 5 +#define EDMA_RSBA_HI 0x01c +#define EDMA_RSIPR 0x020 +#define EDMA_RSIPR_IPMASK (0x1f << 3) +#define EDMA_RSIPR_IPSHIFT 3 +#define EDMA_RSOPR 0x024 +#define EDMA_RSOPR_OPMASK (0x1f << 3) +#define EDMA_RSOPR_OPSHIFT 3 +#define EDMA_CMD 0x028 +#define EDMA_CMD_ENEDMA (0x01 << 0) +#define EDMA_CMD_DISEDMA (0x01 << 1) +#define EDMA_CMD_ATARST (0x01 << 2) +#define EDMA_CMD_FREEZE (0x01 << 4) +#define EDMA_TEST_CTL 0x02c +#define EDMA_STATUS 0x030 +#define EDMA_IORTO 0x034 +#define EDMA_CDTR 0x040 +#define EDMA_HLTCND 0x060 +#define EDMA_NTSR 0x094 + +/* Basic DMA registers */ +#define BDMA_CMD 0x224 +#define BDMA_STATUS 0x228 +#define BDMA_DTLB 0x22c +#define BDMA_DTHB 0x230 +#define BDMA_DRL 0x234 +#define BDMA_DRH 0x238 + +/* SATA Interface registers */ +#define SIR_ICFG 0x050 +#define SIR_CFG_GEN2EN (0x1 << 7) +#define SIR_PLL_CFG 0x054 +#define SIR_SSTATUS 0x300 +#define SSTATUS_DET_MASK (0x0f << 0) +#define SIR_SERROR 0x304 +#define SIR_SCONTROL 0x308 +#define SIR_SCONTROL_DETEN (0x01 << 0) +#define SIR_LTMODE 0x30c +#define SIR_LTMODE_NELBE (0x01 << 7) +#define SIR_PHYMODE3 0x310 +#define SIR_PHYMODE4 0x314 +#define SIR_PHYMODE1 0x32c +#define SIR_PHYMODE2 0x330 +#define SIR_BIST_CTRL 0x334 +#define SIR_BIST_DW1 0x338 +#define SIR_BIST_DW2 0x33c +#define SIR_SERR_IRQ_MASK 0x340 +#define SIR_SATA_IFCTRL 0x344 +#define SIR_SATA_TESTCTRL 0x348 +#define SIR_SATA_IFSTATUS 0x34c +#define SIR_VEND_UNIQ 0x35c +#define SIR_FIS_CFG 0x360 +#define SIR_FIS_IRQ_CAUSE 0x364 +#define SIR_FIS_IRQ_MASK 0x368 +#define SIR_FIS_DWORD0 0x370 +#define SIR_FIS_DWORD1 0x374 +#define SIR_FIS_DWORD2 0x378 +#define SIR_FIS_DWORD3 0x37c +#define SIR_FIS_DWORD4 0x380 +#define SIR_FIS_DWORD5 0x384 +#define SIR_FIS_DWORD6 0x388 +#define SIR_PHYM9_GEN2 0x398 +#define SIR_PHYM9_GEN1 0x39c +#define SIR_PHY_CFG 0x3a0 +#define SIR_PHYCTL 0x3a4 +#define SIR_PHYM10 0x3a8 +#define SIR_PHYM12 0x3b0 + +/* Shadow registers */ +#define PIO_DATA 0x100 +#define PIO_ERR_FEATURES 0x104 +#define PIO_SECTOR_COUNT 0x108 +#define PIO_LBA_LOW 0x10c +#define PIO_LBA_MID 0x110 +#define PIO_LBA_HI 0x114 +#define PIO_DEVICE 0x118 +#define PIO_CMD_STATUS 0x11c +#define PIO_STATUS_ERR (0x01 << 0) +#define PIO_STATUS_DRQ (0x01 << 3) +#define PIO_STATUS_DF (0x01 << 5) +#define PIO_STATUS_DRDY (0x01 << 6) +#define PIO_STATUS_BSY (0x01 << 7) +#define PIO_CTRL_ALTSTAT 0x120 + +/* SATAHC arbiter registers */ +#define SATAHC_CFG 0x000 +#define SATAHC_RQOP 0x004 +#define SATAHC_RQIP 0x008 +#define SATAHC_ICT 0x00c +#define SATAHC_ITT 0x010 +#define SATAHC_ICR 0x014 +#define SATAHC_ICR_PORT0 (0x01 << 0) +#define SATAHC_ICR_PORT1 (0x01 << 1) +#define SATAHC_MIC 0x020 +#define SATAHC_MIM 0x024 +#define SATAHC_LED_CFG 0x02c + +#define REQUEST_QUEUE_SIZE 32 +#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE + +struct crqb { + u32 dtb_low; /* DW0 */ + u32 dtb_high; /* DW1 */ + u32 control_flags; /* DW2 */ + u32 drb_count; /* DW3 */ + u32 ata_cmd_feat; /* DW4 */ + u32 ata_addr; /* DW5 */ + u32 ata_addr_exp; /* DW6 */ + u32 ata_sect_count; /* DW7 */ +}; + +#define CRQB_ALIGN 0x400 + +#define CRQB_CNTRLFLAGS_DIR (0x01 << 0) +#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1) +#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1 +#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12) +#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12 +#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16) +#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17) +#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17 + +#define CRQB_CMDFEAT_CMDMASK (0xff << 16) +#define CRQB_CMDFEAT_CMDSHIFT 16 +#define CRQB_CMDFEAT_FEATMASK (0xff << 16) +#define CRQB_CMDFEAT_FEATSHIFT 24 + +#define CRQB_ADDR_LBA_LOWMASK (0xff << 0) +#define CRQB_ADDR_LBA_LOWSHIFT 0 +#define CRQB_ADDR_LBA_MIDMASK (0xff << 8) +#define CRQB_ADDR_LBA_MIDSHIFT 8 +#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16) +#define CRQB_ADDR_LBA_HIGHSHIFT 16 +#define CRQB_ADDR_DEVICE_MASK (0xff << 24) +#define CRQB_ADDR_DEVICE_SHIFT 24 + +#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0) +#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0 +#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8) +#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8 +#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16) +#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16 +#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24) +#define CRQB_ADDR_FEATURE_EXP_SHIFT 24 + +#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0) +#define CRQB_SECTCOUNT_COUNT_SHIFT 0 +#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8) +#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8 + +#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) +#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) + +struct eprd { + u32 phyaddr_low; + u32 bytecount_eot; + u32 phyaddr_hi; + u32 reserved; +}; + +#define EPRD_PHYADDR_MASK 0xfffffffe +#define EPRD_BYTECOUNT_MASK 0x0000ffff +#define EPRD_EOT (0x01 << 31) + +struct crpb { + u32 id; + u32 flags; + u32 timestamp; +}; + +#define CRPB_ALIGN 0x100 + +#define READ_CMD 0 +#define WRITE_CMD 1 + +/* + * Since we don't use PRDs yet max transfer size + * is 64KB + */ +#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE) + +/* Keep track if hw is initialized or not */ +static u32 hw_init; + +struct mv_priv { + char name[12]; + u32 link; + u32 regbase; + u32 queue_depth; + u16 pio; + u16 mwdma; + u16 udma; + + void *crqb_alloc; + struct crqb *request; + + void *crpb_alloc; + struct crpb *response; +}; + +static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec) +{ + ulong start; + + start = get_timer(0); + do { + if ((in_le32(addr) & mask) == val) + return 0; + } while (get_timer(start) < timeout_msec); + + return -ETIMEDOUT; +} + +/* Cut from sata_mv in linux kernel */ +static int mv_stop_edma_engine(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + int i; + + /* Disable eDMA. The disable bit auto clears. */ + out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA); + + /* Wait for the chip to confirm eDMA is off. */ + for (i = 10000; i > 0; i--) { + u32 reg = in_le32(priv->regbase + EDMA_CMD); + if (!(reg & EDMA_CMD_ENEDMA)) { + debug("EDMA stop on port %d succesful\n", port); + return 0; + } + udelay(10); + } + debug("EDMA stop on port %d failed\n", port); + return -1; +} + +static int mv_start_edma_engine(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + /* Check preconditions */ + tmp = in_le32(priv->regbase + SIR_SSTATUS); + if ((tmp & SSTATUS_DET_MASK) != 0x03) { + printf("Device error on port: %d\n", port); + return -1; + } + + tmp = in_le32(priv->regbase + PIO_CMD_STATUS); + if (tmp & (ATA_BUSY | ATA_DRQ)) { + printf("Device not ready on port: %d\n", port); + return -1; + } + + /* Clear interrupt cause */ + out_le32(priv->regbase + EDMA_IECR, 0x0); + + tmp = in_le32(SATAHC_BASE + SATAHC_ICR); + tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1); + out_le32(SATAHC_BASE + SATAHC_ICR, tmp); + + /* Configure edma operation */ + tmp = in_le32(priv->regbase + EDMA_CFG); + tmp &= ~EDMA_CFG_NCQ; /* No NCQ */ + tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */ + out_le32(priv->regbase + EDMA_CFG, tmp); + + out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0); + + /* Configure fis, set all to no-wait for now */ + out_le32(priv->regbase + SIR_FIS_CFG, 0x0); + + /* Setup request queue */ + out_le32(priv->regbase + EDMA_RQBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RQIPR, priv->request); + out_le32(priv->regbase + EDMA_RQOPR, 0x0); + + /* Setup response queue */ + out_le32(priv->regbase + EDMA_RSBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RSOPR, priv->response); + out_le32(priv->regbase + EDMA_RSIPR, 0x0); + + /* Start edma */ + out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA); + + return 0; +} + +static int mv_reset_channel(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + /* Make sure edma is stopped */ + mv_stop_edma_engine(port); + + out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST); + udelay(25); /* allow reset propagation */ + out_le32(priv->regbase + EDMA_CMD, 0); + mdelay(10); + + return 0; +} + +static void mv_reset_port(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + mv_reset_channel(port); + + out_le32(priv->regbase + EDMA_CMD, 0x0); + out_le32(priv->regbase + EDMA_CFG, 0x101f); + out_le32(priv->regbase + EDMA_IECR, 0x0); + out_le32(priv->regbase + EDMA_IEMR, 0x0); + out_le32(priv->regbase + EDMA_RQBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RQIPR, 0x0); + out_le32(priv->regbase + EDMA_RQOPR, 0x0); + out_le32(priv->regbase + EDMA_RSBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RSIPR, 0x0); + out_le32(priv->regbase + EDMA_RSOPR, 0x0); + out_le32(priv->regbase + EDMA_IORTO, 0xfa); +} + +static void mv_reset_one_hc(void) +{ + out_le32(SATAHC_BASE + SATAHC_ICT, 0x00); + out_le32(SATAHC_BASE + SATAHC_ITT, 0x00); + out_le32(SATAHC_BASE + SATAHC_ICR, 0x00); +} + +static int probe_port(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + int tries, tries2, set15 = 0; + u32 tmp; + + debug("Probe port: %d\n", port); + + for (tries = 0; tries < 2; tries++) { + /* Clear SError */ + out_le32(priv->regbase + SIR_SERROR, 0x0); + + /* trigger com-init */ + tmp = in_le32(priv->regbase + SIR_SCONTROL); + tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN; + out_le32(priv->regbase + SIR_SCONTROL, tmp); + + mdelay(1); + + tmp = in_le32(priv->regbase + SIR_SCONTROL); + tries2 = 5; + do { + tmp = (tmp & 0x0f0) | 0x300; + out_le32(priv->regbase + SIR_SCONTROL, tmp); + mdelay(10); + tmp = in_le32(priv->regbase + SIR_SCONTROL); + } while ((tmp & 0xf0f) != 0x300 && tries2--); + + mdelay(10); + + for (tries2 = 0; tries2 < 200; tries2++) { + tmp = in_le32(priv->regbase + SIR_SSTATUS); + if ((tmp & SSTATUS_DET_MASK) == 0x03) { + debug("Found device on port\n"); + return 0; + } + mdelay(1); + } + + if ((tmp & SSTATUS_DET_MASK) == 0) { + debug("No device attached on port %d\n", port); + return -ENODEV; + } + + if (!set15) { + /* Try on 1.5Gb/S */ + debug("Try 1.5Gb link\n"); + set15 = 1; + out_le32(priv->regbase + SIR_SCONTROL, 0x304); + + tmp = in_le32(priv->regbase + SIR_ICFG); + tmp &= ~SIR_CFG_GEN2EN; + out_le32(priv->regbase + SIR_ICFG, tmp); + + mv_reset_channel(port); + } + } + + debug("Failed to probe port\n"); + return -1; +} + +/* Get request queue in pointer */ +static int get_reqip(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK; + tmp = tmp >> EDMA_RQIPR_IPSHIFT; + + return tmp; +} + +static void set_reqip(int port, int reqin) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK; + tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK); + out_le32(priv->regbase + EDMA_RQIPR, tmp); +} + +/* Get next available slot, ignoring possible overwrite */ +static int get_next_reqip(int port) +{ + int slot = get_reqip(port); + slot = (slot + 1) % REQUEST_QUEUE_SIZE; + return slot; +} + +/* Get response queue in pointer */ +static int get_rspip(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK; + tmp = tmp >> EDMA_RSIPR_IPSHIFT; + + return tmp; +} + +/* Get response queue out pointer */ +static int get_rspop(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK; + tmp = tmp >> EDMA_RSOPR_OPSHIFT; + return tmp; +} + +/* Get next response queue pointer */ +static int get_next_rspop(int port) +{ + return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE; +} + +/* Set response queue pointer */ +static void set_rspop(int port, int reqin) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK; + tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK); + + out_le32(priv->regbase + EDMA_RSOPR, tmp); +} + +static int wait_dma_completion(int port, int index, u32 timeout_msec) +{ + u32 tmp, res; + + tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1; + res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp, + tmp, timeout_msec); + if (res) + printf("Failed to wait for completion on port %d\n", port); + + return res; +} + +static void process_responses(int port) +{ +#ifdef DEBUG + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; +#endif + u32 tmp; + u32 outind = get_rspop(port); + + /* Ack interrupts */ + tmp = in_le32(SATAHC_BASE + SATAHC_ICR); + if (port == 0) + tmp &= ~(BIT(0) | BIT(8)); + else + tmp &= ~(BIT(1) | BIT(9)); + tmp &= ~(BIT(4)); + out_le32(SATAHC_BASE + SATAHC_ICR, tmp); + + while (get_rspip(port) != outind) { +#ifdef DEBUG + debug("Response index %d flags %08x on port %d\n", outind, + priv->response[outind].flags, port); +#endif + outind = get_next_rspop(port); + set_rspop(port, outind); + } +} + +static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis, + u8 *buffer, u32 len, u32 iswrite) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + struct crqb *req; + int slot; + + if (len >= 64 * 1024) { + printf("We only support <64K transfers for now\n"); + return -1; + } + + /* Initialize request */ + slot = get_reqip(port); + memset(&priv->request[slot], 0, sizeof(struct crqb)); + req = &priv->request[slot]; + + req->dtb_low = (u32)buffer; + + /* Dont use PRDs */ + req->control_flags = CRQB_CNTRLFLAGS_PRDMODE; + req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR; + req->control_flags |= + ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT) + & CRQB_CNTRLFLAGS_PMPORTMASK); + + req->drb_count = len; + + req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) & + CRQB_CMDFEAT_CMDMASK; + req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) & + CRQB_CMDFEAT_FEATMASK; + + req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) & + CRQB_ADDR_LBA_LOWMASK; + req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) & + CRQB_ADDR_LBA_MIDMASK; + req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) & + CRQB_ADDR_LBA_HIGHMASK; + req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) & + CRQB_ADDR_DEVICE_MASK; + + req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) & + CRQB_ADDR_LBA_LOW_EXP_MASK; + req->ata_addr_exp |= + (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) & + CRQB_ADDR_LBA_MID_EXP_MASK; + req->ata_addr_exp |= + (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) & + CRQB_ADDR_LBA_HIGH_EXP_MASK; + req->ata_addr_exp |= + (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) & + CRQB_ADDR_FEATURE_EXP_MASK; + + req->ata_sect_count = + (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) & + CRQB_SECTCOUNT_COUNT_MASK; + req->ata_sect_count |= + (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) & + CRQB_SECTCOUNT_COUNT_EXP_MASK; + + /* Flush data */ + flush_dcache_range((u32)req, (u32)req + sizeof(*req)); + + /* Trigger operation */ + slot = get_next_reqip(port); + set_reqip(port, slot); + + /* Wait for completion */ + if (wait_dma_completion(port, slot, 10000)) { + printf("ATA operation timed out\n"); + return -1; + } + + process_responses(port); + + /* Invalidate data on read */ + if (buffer && len) + invalidate_dcache_range((u32)buffer, (u32)buffer + len); + + return len; +} + +static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt, + u8 *buffer, int is_write) +{ + struct sata_fis_h2d cfis; + u32 res; + u64 block; + + block = (u64)start; + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; + + cfis.lba_high_exp = (block >> 40) & 0xff; + cfis.lba_mid_exp = (block >> 32) & 0xff; + cfis.lba_low_exp = (block >> 24) & 0xff; + cfis.lba_high = (block >> 16) & 0xff; + cfis.lba_mid = (block >> 8) & 0xff; + cfis.lba_low = block & 0xff; + cfis.device = ATA_LBA; + cfis.sector_count_exp = (blkcnt >> 8) & 0xff; + cfis.sector_count = blkcnt & 0xff; + + res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt, + is_write); + + return res >= 0 ? blkcnt : res; +} + +static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer, + int is_write) +{ + struct sata_fis_h2d cfis; + lbaint_t block; + u32 res; + + block = start; + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; + cfis.device = ATA_LBA; + + cfis.device |= (block >> 24) & 0xf; + cfis.lba_high = (block >> 16) & 0xff; + cfis.lba_mid = (block >> 8) & 0xff; + cfis.lba_low = block & 0xff; + cfis.sector_count = (u8)(blkcnt & 0xff); + + res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt, + is_write); + + return res >= 0 ? blkcnt : res; +} + +static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer, int is_write) +{ + lbaint_t start, blks; + u8 *addr; + int max_blks; + + debug("%s: %ld %ld\n", __func__, blknr, blkcnt); + + start = blknr; + blks = blkcnt; + addr = (u8 *)buffer; + + max_blks = MV_ATA_MAX_SECTORS; + do { + if (blks > max_blks) { + if (sata_dev_desc[dev].lba48) { + mv_sata_rw_cmd_ext(dev, start, max_blks, addr, + is_write); + } else { + mv_sata_rw_cmd(dev, start, max_blks, addr, + is_write); + } + start += max_blks; + blks -= max_blks; + addr += ATA_SECT_SIZE * max_blks; + } else { + if (sata_dev_desc[dev].lba48) { + mv_sata_rw_cmd_ext(dev, start, blks, addr, + is_write); + } else { + mv_sata_rw_cmd(dev, start, blks, addr, + is_write); + } + start += blks; + blks = 0; + addr += ATA_SECT_SIZE * blks; + } + } while (blks != 0); + + return blkcnt; +} + +static int mv_ata_exec_ata_cmd_nondma(int port, + struct sata_fis_h2d *cfis, u8 *buffer, + u32 len, u32 iswrite) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + int i; + u16 *tp; + + debug("%s\n", __func__); + + out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count); + out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high); + out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid); + out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low); + out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features); + out_le32(priv->regbase + PIO_DEVICE, cfis->device); + out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command); + + if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS), + ATA_BUSY, 0x0, 10000)) { + debug("Failed to wait for completion\n"); + return -1; + } + + if (len > 0) { + tp = (u16 *)buffer; + for (i = 0; i < len / 2; i++) { + if (iswrite) + out_le16(priv->regbase + PIO_DATA, *tp++); + else + *tp++ = in_le16(priv->regbase + PIO_DATA); + } + } + + return len; +} + +static int mv_sata_identify(int port, u16 *id) +{ + struct sata_fis_h2d h2d; + + memset(&h2d, 0, sizeof(struct sata_fis_h2d)); + + h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + h2d.command = ATA_CMD_ID_ATA; + + /* Give device time to get operational */ + mdelay(10); + + return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id, + ATA_ID_WORDS * 2, READ_CMD); +} + +static void mv_sata_xfer_mode(int port, u16 *id) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + priv->pio = id[ATA_ID_PIO_MODES]; + priv->mwdma = id[ATA_ID_MWDMA_MODES]; + priv->udma = id[ATA_ID_UDMA_MODES]; + debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma, + priv->udma); +} + +static void mv_sata_set_features(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + struct sata_fis_h2d cfis; + u8 udma_cap; + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = ATA_CMD_SET_FEATURES; + cfis.features = SETFEATURES_XFER; + + /* First check the device capablity */ + udma_cap = (u8) (priv->udma & 0xff); + + if (udma_cap == ATA_UDMA6) + cfis.sector_count = XFER_UDMA_6; + if (udma_cap == ATA_UDMA5) + cfis.sector_count = XFER_UDMA_5; + if (udma_cap == ATA_UDMA4) + cfis.sector_count = XFER_UDMA_4; + if (udma_cap == ATA_UDMA3) + cfis.sector_count = XFER_UDMA_3; + + mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD); +} + +int mv_sata_spin_down(int dev) +{ + struct sata_fis_h2d cfis; + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv; + + if (priv->link == 0) { + debug("No device on port: %d\n", dev); + return 1; + } + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = ATA_CMD_STANDBY; + + return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD); +} + +int mv_sata_spin_up(int dev) +{ + struct sata_fis_h2d cfis; + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv; + + if (priv->link == 0) { + debug("No device on port: %d\n", dev); + return 1; + } + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = ATA_CMD_IDLE; + + return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD); +} + +ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) +{ + return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD); +} + +ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) +{ + return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD); +} + +/* + * Initialize SATA memory windows + */ +static void mvsata_ide_conf_mbus_windows(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + /* Disable windows, Set Size/Base to 0 */ + for (i = 0; i < 4; i++) { + writel(0, MVSATA_WIN_CONTROL(i)); + writel(0, MVSATA_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + MVSATA_WIN_CONTROL(i)); + writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); + } +} + +int init_sata(int dev) +{ + struct mv_priv *priv; + + debug("Initialize sata dev: %d\n", dev); + + if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) { + printf("Invalid sata device %d\n", dev); + return -1; + } + + priv = (struct mv_priv *)malloc(sizeof(struct mv_priv)); + if (!priv) { + printf("Failed to allocate memory for private sata data\n"); + return -ENOMEM; + } + + memset((void *)priv, 0, sizeof(struct mv_priv)); + + /* Allocate and align request buffer */ + priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE + + CRQB_ALIGN); + if (!priv->crqb_alloc) { + printf("Unable to allocate memory for request queue\n"); + return -ENOMEM; + } + memset(priv->crqb_alloc, 0, + sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN); + priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) & + ~(CRQB_ALIGN - 1)); + + /* Allocate and align response buffer */ + priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE + + CRPB_ALIGN); + if (!priv->crpb_alloc) { + printf("Unable to allocate memory for response queue\n"); + return -ENOMEM; + } + memset(priv->crpb_alloc, 0, + sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN); + priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) & + ~(CRPB_ALIGN - 1)); + + sata_dev_desc[dev].priv = (void *)priv; + + sprintf(priv->name, "SATA%d", dev); + + priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE; + + if (!hw_init) { + debug("Initialize sata hw\n"); + hw_init = 1; + mv_reset_one_hc(); + mvsata_ide_conf_mbus_windows(); + } + + mv_reset_port(dev); + + if (probe_port(dev)) { + priv->link = 0; + return -ENODEV; + } + priv->link = 1; + + return 0; +} + +int reset_sata(int dev) +{ + return 0; +} + +int scan_sata(int port) +{ + unsigned char serial[ATA_ID_SERNO_LEN + 1]; + unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; + unsigned char product[ATA_ID_PROD_LEN + 1]; + u64 n_sectors; + u16 *id; + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + if (!priv->link) + return -ENODEV; + + id = (u16 *)malloc(ATA_ID_WORDS * 2); + if (!id) { + printf("Failed to malloc id data\n"); + return -ENOMEM; + } + + mv_sata_identify(port, id); + ata_swap_buf_le16(id, ATA_ID_WORDS); +#ifdef DEBUG + ata_dump_id(id); +#endif + + /* Serial number */ + ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); + memcpy(sata_dev_desc[port].product, serial, sizeof(serial)); + + /* Firmware version */ + ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); + memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware)); + + /* Product model */ + ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); + memcpy(sata_dev_desc[port].vendor, product, sizeof(product)); + + /* Total sectors */ + n_sectors = ata_id_n_sectors(id); + sata_dev_desc[port].lba = n_sectors; + + /* Check if support LBA48 */ + if (ata_id_has_lba48(id)) { + sata_dev_desc[port].lba48 = 1; + debug("Device support LBA48\n"); + } + + /* Get the NCQ queue depth from device */ + priv->queue_depth = ata_id_queue_depth(id); + + /* Get the xfer mode from device */ + mv_sata_xfer_mode(port, id); + + /* Set the xfer mode to highest speed */ + mv_sata_set_features(port); + + /* Start up */ + mv_start_edma_engine(port); + + return 0; +} diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c index fdf75b5abfc..b974e80167e 100644 --- a/drivers/block/systemace.c +++ b/drivers/block/systemace.c @@ -69,8 +69,9 @@ static u16 ace_readw(unsigned off) return in16(base + off); } -static unsigned long systemace_read(int dev, unsigned long start, - lbaint_t blkcnt, void *buffer); +static unsigned long systemace_read(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + void *buffer); static block_dev_desc_t systemace_dev = { 0 }; @@ -136,8 +137,9 @@ block_dev_desc_t *systemace_get_dev(int dev) * the dev_desc) to read blocks of data. The return value is the * number of blocks read. A zero return indicates an error. */ -static unsigned long systemace_read(int dev, unsigned long start, - lbaint_t blkcnt, void *buffer) +static unsigned long systemace_read(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + void *buffer) { int retry; unsigned blk_countdown; diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index f332480e1d8..c5c9d2a42e5 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -60,6 +60,15 @@ config DM_SEQ_ALIAS help Most boards will have a '/aliases' node containing the path to numbered devices (e.g. serial0 = &serial0). This feature can be + disabled if it is not required. + +config SPL_DM_SEQ_ALIAS + bool "Support numbered aliases in device tree in SPL" + depends on DM + default n + help + Most boards will have a '/aliases' node containing the path to + numbered devices (e.g. serial0 = &serial0). This feature can be disabled if it is not required, to save code space in SPL. config REGMAP diff --git a/drivers/core/device.c b/drivers/core/device.c index 7a02a931edf..818d03fac15 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -64,7 +64,7 @@ int device_bind(struct udevice *parent, const struct driver *drv, dev->seq = -1; dev->req_seq = -1; - if (CONFIG_IS_ENABLED(OF_CONTROL) && IS_ENABLED(CONFIG_DM_SEQ_ALIAS)) { + if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) { /* * Some devices, such as a SPI bus, I2C bus and serial ports * are numbered using aliases. @@ -581,17 +581,35 @@ const char *dev_get_uclass_name(struct udevice *dev) return dev->uclass->uc_drv->name; } -fdt_addr_t dev_get_addr(struct udevice *dev) +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) { #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr; if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { const fdt32_t *reg; + int len = 0; + int na, ns; - reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL); - if (!reg) + na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset); + if (na < 1) { + debug("bad #address-cells\n"); return FDT_ADDR_T_NONE; + } + + ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset); + if (ns < 0) { + debug("bad #size-cells\n"); + return FDT_ADDR_T_NONE; + } + + reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) { + debug("Req index out of range\n"); + return FDT_ADDR_T_NONE; + } + + reg += index * (na + ns); /* * Use the full-fledged translate function for complex @@ -607,7 +625,7 @@ fdt_addr_t dev_get_addr(struct udevice *dev) addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev->parent->of_offset, dev->of_offset, "reg", - 0, NULL); + index, NULL); if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) @@ -629,6 +647,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #endif } +fdt_addr_t dev_get_addr(struct udevice *dev) +{ + return dev_get_addr_index(dev, 0); +} + bool device_has_children(struct udevice *dev) { return !list_empty(&dev->child_head); diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 1ed2883d1b8..29969421727 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -218,6 +218,7 @@ static void sdram_dump_protection_config(void) readl(&sdr_ctrl->protport_default)); for (rules = 0; rules < 20; rules++) { + rule.rule = rules; sdram_get_rule(&rule); debug("Rule %d, rules ...\n", rules); debug(" sdram start %x\n", rule.sdram_start); diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c index 7f1c3afcc47..00cdc224080 100644 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index 49cc1a07ffd..59baf6b7a10 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index 69177150ec5..9944dbbf032 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -6,9 +6,7 @@ * from ddr3 spd, please refer to the spec * JEDEC standard No.21-C 4_01_02_11R18.pdf * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index b12eeb9f01c..47ad4e542db 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index c68663220d8..139a3a7f5ad 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index 8dd4a9136cf..c27288dda21 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 988b4a49410..898b0cd33cd 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -1,9 +1,7 @@ /* * Copyright 2008-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 6752d4d29e0..653b7f0c770 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -1,9 +1,7 @@ /* * Copyright 2008-2012 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c index 4551ed87db7..a65eb3144fc 100644 --- a/drivers/ddr/fsl/mpc86xx_ddr.c +++ b/drivers/ddr/fsl/mpc86xx_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 1a49b28f331..99777793a59 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 1d72bc569e4..12b5b04109d 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -165,21 +165,6 @@ int ddr3_tip_init_config_func(u32 dev_num, } /* - * Read training result table - */ -int hws_ddr3_tip_read_training_result( - u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) -{ - dev_num = dev_num; - - if (result == NULL) - return MV_BAD_PARAM; - memcpy(result, training_result, sizeof(result)); - - return MV_OK; -} - -/* * Get training result info pointer */ enum hws_result *ddr3_tip_get_result_ptr(u32 stage) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h index 76a1b6a06d4..ed92873697e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h @@ -171,8 +171,6 @@ int hws_ddr3_tip_load_topology_map(u32 dev_num, struct hws_topology_map *topology); int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type); int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info); -int hws_ddr3_tip_read_training_result(u32 dev_num, - enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]); int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode); u8 ddr3_tip_get_buf_min(u8 *buf_ptr); u8 ddr3_tip_get_buf_max(u8 *buf_ptr); diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index d9e33f7c6e2..75d315a35e0 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -33,7 +33,10 @@ #define SAR1_CPU_CORE_MASK 0x00000018 #define SAR1_CPU_CORE_OFFSET 3 +/* Only enable ECC if the board selects it */ +#ifdef CONFIG_BOARD_ECC_SUPPORT #define ECC_SUPPORT +#endif #define NEW_FABRIC_TWSI_ADDR 0x4E #ifdef CONFIG_DB_784MP_GP #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index a6720442ffa..8549fe8baba 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -44,9 +44,14 @@ * DDR3_TRAINING_DEBUG - Debug prints of internal code */ #define DDR_TARGET_FABRIC 5 +/* Only enable ECC if the board selects it */ +#ifdef CONFIG_BOARD_ECC_SUPPORT #define DRAM_ECC 1 +#else +#define DRAM_ECC 0 +#endif -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT #define BUS_WIDTH 32 #else #define BUS_WIDTH 64 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h index 2c0e9075e96..71794ad312a 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h @@ -8,9 +8,9 @@ #define __AXP_MC_STATIC_H MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /* MV_DDR_64BIT */ +#else /* CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ @@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B040}, /*Dunit Control Low Register */ @@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ #endif diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c index df3a3df4a66..da384f321ca 100644 --- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c @@ -22,6 +22,8 @@ DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n") #ifdef MV_DEBUG_WL +#define DEBUG_WL_S(s) puts(s) +#define DEBUG_WL_D(d, l) printf("%x", d) #define DEBUG_RL_S(s) \ debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s) #define DEBUG_RL_D(d, l) \ @@ -1229,8 +1231,6 @@ static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, DEBUG_WL_FULL_D((u32) phase, 1); DEBUG_WL_FULL_S(", Delay = "); DEBUG_WL_FULL_D((u32) delay, 1); - DEBUG_WL_FULL_S(", Counter = "); - DEBUG_WL_FULL_D((u32) i, 1); DEBUG_WL_FULL_S("\n"); /* Drive DQS high for one cycle - All data PUPs */ diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 5a9fb4a6e24..395d472e0bd 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -20,23 +20,6 @@ static unsigned char *dfu_file_buf; static long dfu_file_buf_len; static long dfu_file_buf_filled; -static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) -{ - int ret; - - if (part == mmc->part_num) - return 0; - - ret = mmc_switch_part(dfu->data.mmc.dev_num, part); - if (ret) { - error("Cannot switch to partition %d\n", part); - return ret; - } - mmc->part_num = part; - - return 0; -} - static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { @@ -66,8 +49,9 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, } if (dfu->data.mmc.hw_partition >= 0) { - part_num_bkp = mmc->part_num; - ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition); + part_num_bkp = mmc->block_dev.hwpart; + ret = mmc_select_hwpart(dfu->data.mmc.dev_num, + dfu->data.mmc.hw_partition); if (ret) return ret; } @@ -77,11 +61,11 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, dfu->data.mmc.dev_num, blk_start, blk_count, buf); switch (op) { case DFU_OP_READ: - n = mmc->block_dev.block_read(dfu->data.mmc.dev_num, blk_start, + n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_count, buf); break; case DFU_OP_WRITE: - n = mmc->block_dev.block_write(dfu->data.mmc.dev_num, blk_start, + n = mmc->block_dev.block_write(&mmc->block_dev, blk_start, blk_count, buf); break; default: @@ -91,12 +75,12 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, if (n != blk_count) { error("MMC operation failed"); if (dfu->data.mmc.hw_partition >= 0) - mmc_access_part(dfu, mmc, part_num_bkp); + mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp); return -EIO; } if (dfu->data.mmc.hw_partition >= 0) { - ret = mmc_access_part(dfu, mmc, part_num_bkp); + ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp); if (ret) return ret; } diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 4448250f5c6..431e159e48c 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -269,7 +269,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, &sysmgr_regs->fpgaintfgrp_gbl); /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index c8c863765b6..932dfe9f34e 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -1,19 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ff7f25a0ef7..b56a1c2541d 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -4,19 +4,7 @@ * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de. * Changes for multibus/multiadapter I2C support. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index f20d1b22915..5f993b99052 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -20,7 +20,7 @@ #if defined(CONFIG_ORION5X) #include <asm/arch/orion5x.h> -#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP)) +#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) #include <asm/arch/soc.h> #elif defined(CONFIG_SUNXI) #include <asm/arch/i2c.h> @@ -73,6 +73,17 @@ struct mvtwsi_registers { #define MVTWSI_CONTROL_INTEN 0x00000080 /* + * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1, + * on other platforms it is a normal r/w bit which is cleared by writing 0. + */ + +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 +#else +#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 +#endif + +/* * Status register values -- only those expected in normal master * operation on non-10-bit-address devices; whatever status we don't * expect in nominal conditions (bus errors, arbitration losses, @@ -117,6 +128,10 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) case 4: return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4; #endif +#ifdef CONFIG_I2C_MVTWSI_BASE5 + case 5: + return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5; +#endif default: printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); break; @@ -189,7 +204,8 @@ static int twsi_start(struct i2c_adapter *adap, int expected_status) /* globally set TWSIEN in case it was not */ twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; /* assert START */ - writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control); + twsi_control_flags |= MVTWSI_CONTROL_START | MVTWSI_CONTROL_CLEAR_IFLG; + writel(twsi_control_flags, &twsi->control); /* wait for controller to process START */ return twsi_wait(adap, expected_status); } @@ -204,7 +220,7 @@ static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status) /* put byte in data register for sending */ writel(byte, &twsi->data); /* clear any pending interrupt -- that'll cause sending */ - writel(twsi_control_flags, &twsi->control); + writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); /* wait for controller to receive byte and check ACK */ return twsi_wait(adap, expected_status); } @@ -224,7 +240,7 @@ static int twsi_recv(struct i2c_adapter *adap, u8 *byte) else expected_status = MVTWSI_STATUS_DATA_R_NAK; /* acknowledge *previous state* and launch receive */ - writel(twsi_control_flags, &twsi->control); + writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); /* wait for controller to receive byte and assert ACK or NAK */ status = twsi_wait(adap, expected_status); /* if we did receive expected byte then store it */ @@ -246,7 +262,7 @@ static int twsi_stop(struct i2c_adapter *adap, int status) /* assert STOP */ control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; - writel(control, &twsi->control); + writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ do { stop_status = readl(&twsi->status); @@ -475,3 +491,10 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) #endif +#ifdef CONFIG_I2C_MVTWSI_BASE5 +U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, + twsi_i2c_read, twsi_i2c_write, + twsi_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) + +#endif diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c index 127121e7971..2703c347540 100644 --- a/drivers/misc/cbmem_console.c +++ b/drivers/misc/cbmem_console.c @@ -1,18 +1,7 @@ /* * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index aa893c35fbb..d7c9bd73c85 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -1,19 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index b1cb4b3534f..301d9b3ab99 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -38,7 +38,8 @@ void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst) blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst); + err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, + vdst); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); hang(); @@ -85,7 +86,8 @@ void __noreturn mmc_boot(void) /* * Read source addr from sd card */ - err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); + err = mmc->block_dev.block_read(&mmc->block_dev, + CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); if (err != 1) { puts("spl: mmc read failed!!\n"); free(tmp_buf); @@ -126,7 +128,7 @@ void __noreturn mmc_boot(void) #endif blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; - err = mmc->block_dev.block_read(0, blk_start, blk_cnt, + err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 3a34028c917..e6028d503f2 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -234,8 +234,11 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, return blkcnt; } -static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) +static ulong mmc_bread(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, void *dst) { + int dev_num = block_dev->dev; + int err; lbaint_t cur, blocks_todo = blkcnt; if (blkcnt == 0) @@ -245,6 +248,10 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) if (!mmc) return 0; + err = mmc_select_hwpart(dev_num, block_dev->hwpart); + if (err < 0) + return 0; + if ((start + blkcnt) > mmc->block_dev.lba) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", @@ -579,7 +586,7 @@ int mmc_select_hwpart(int dev_num, int hwpart) if (!mmc) return -ENODEV; - if (mmc->part_num == hwpart) + if (mmc->block_dev.hwpart == hwpart) return 0; if (mmc->part_config == MMCPART_NOAVAILABLE) { @@ -591,8 +598,6 @@ int mmc_select_hwpart(int dev_num, int hwpart) if (ret) return ret; - mmc->part_num = hwpart; - return 0; } @@ -613,8 +618,10 @@ int mmc_switch_part(int dev_num, unsigned int part_num) * Set the capacity if the switch succeeded or was intended * to return to representing the raw device. */ - if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) + if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { ret = mmc_set_capacity(mmc, part_num); + mmc->block_dev.hwpart = part_num; + } return ret; } @@ -1324,7 +1331,7 @@ static int mmc_startup(struct mmc *mmc) mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; } - err = mmc_set_capacity(mmc, mmc->part_num); + err = mmc_set_capacity(mmc, mmc->block_dev.hwpart); if (err) return err; @@ -1465,6 +1472,7 @@ static int mmc_startup(struct mmc *mmc) /* fill in device description */ mmc->block_dev.lun = 0; + mmc->block_dev.hwpart = 0; mmc->block_dev.type = 0; mmc->block_dev.blksz = mmc->read_bl_len; mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); @@ -1624,7 +1632,7 @@ int mmc_start_init(struct mmc *mmc) return err; /* The internal partition reset to user partition(0) at every CMD0*/ - mmc->part_num = 0; + mmc->block_dev.hwpart = 0; /* Test for SD version 2 */ err = mmc_send_if_cond(mmc); diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 447a7001dbd..6a7063976ce 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -22,23 +22,24 @@ void mmc_adapter_card_type_ident(void); #ifndef CONFIG_SPL_BUILD -extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt); +unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt); -extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, - const void *src); +unsigned long mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *src); #else /* CONFIG_SPL_BUILD */ /* SPL will never write or erase, declare dummies to reduce code size. */ -static inline unsigned long mmc_berase(int dev_num, lbaint_t start, - lbaint_t blkcnt) +static inline unsigned long mmc_berase(block_dev_desc_t *block_dev, + lbaint_t start, lbaint_t blkcnt) { return 0; } -static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, - const void *src) +static inline ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *src) { return 0; } diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index 221bf306cc5..79b8c4d808f 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -65,8 +65,10 @@ err_out: return err; } -unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt) +unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt) { + int dev_num = block_dev->dev; int err = 0; u32 start_rem, blkcnt_rem; struct mmc *mmc = find_mmc_device(dev_num); @@ -76,6 +78,10 @@ unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt) if (!mmc) return -1; + err = mmc_select_hwpart(dev_num, block_dev->hwpart); + if (err < 0) + return -1; + /* * We want to see if the requested start or total block count are * unaligned. We discard the whole numbers and only care about the @@ -165,14 +171,21 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, return blkcnt; } -ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src) +ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt, + const void *src) { + int dev_num = block_dev->dev; lbaint_t cur, blocks_todo = blkcnt; + int err; struct mmc *mmc = find_mmc_device(dev_num); if (!mmc) return 0; + err = mmc_select_hwpart(dev_num, block_dev->hwpart); + if (err < 0) + return 0; + if (mmc_set_blocklen(mmc, mmc->write_bl_len)) return 0; diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index aeaec6c8658..9b4268ecdd9 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,6 +52,8 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) /* use non-removeable as sdcard and emmc as judgement */ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable")) + host->dev_index = 0; + else host->dev_index = 1; return 0; diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index f92cf00cf44..001bf185a72 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -3,9 +3,7 @@ * * Copyright (C) 2011 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. + * SPDX-License-Identifier: GPL-2.0 */ #include <config.h> diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h index 4b6752f7f98..2f65f9d2640 100644 --- a/drivers/mmc/sh_mmcif.h +++ b/drivers/mmc/sh_mmcif.h @@ -3,10 +3,7 @@ * * Copyright (C) 2011 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _SH_MMCIF_H_ diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index e717c442162..7b33094d848 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -454,7 +454,7 @@ int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc) panic("Failed to allocate memory\n"); if (mmc_getcd(mmc) && mmc_init(mmc) == 0 && - mmc->block_dev.block_read(mmc->block_dev.dev, 16, 1, buf) == 1 && + mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 && strncmp(&buf[4], "eGON.BT0", 8) == 0) valid_signature = 1; diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 4cf4c1c7076..8f0a9210ec3 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -3,22 +3,7 @@ * 2N Telekomunikace, a.s. <www.2n.cz> * Ladislav Michl <michl@2n.cz> * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 06266f3cbdb..1faec5e1f23 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -12,10 +12,7 @@ * * Based on original driver mpc5121_nfc.c. * - * This is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * SPDX-License-Identifier: GPL-2.0+ * * Limitations: * - Untested on MPC5125 and M54418. diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 72e0f6b3fb1..19de964e612 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -46,7 +46,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, void spi_flash_free(struct spi_flash *flash) { - spi_flash_remove(flash->spi->dev); + device_remove(flash->spi->dev); } int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, @@ -55,11 +55,17 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, { struct spi_slave *slave; struct udevice *bus; - char name[30], *str; + char *str; int ret; +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_TINY_PRINTF) + str = "spi_flash"; +#else + char name[30]; + snprintf(name, sizeof(name), "spi_flash@%d:%d", busnum, cs); str = strdup(name); +#endif ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode, "spi_flash_std", str, &bus, &slave); if (ret) @@ -69,11 +75,6 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, return 0; } -int spi_flash_remove(struct udevice *dev) -{ - return device_remove(dev); -} - static int spi_flash_post_bind(struct udevice *dev) { #if defined(CONFIG_NEEDS_MANUAL_RELOC) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index ed5c391dc2c..007a5a085ca 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -16,18 +16,18 @@ /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ enum spi_dual_flash { SF_SINGLE_FLASH = 0, - SF_DUAL_STACKED_FLASH = 1 << 0, - SF_DUAL_PARALLEL_FLASH = 1 << 1, + SF_DUAL_STACKED_FLASH = BIT(0), + SF_DUAL_PARALLEL_FLASH = BIT(1), }; /* Enum list - Full read commands */ enum spi_read_cmds { - ARRAY_SLOW = 1 << 0, - ARRAY_FAST = 1 << 1, - DUAL_OUTPUT_FAST = 1 << 2, - DUAL_IO_FAST = 1 << 3, - QUAD_OUTPUT_FAST = 1 << 4, - QUAD_IO_FAST = 1 << 5, + ARRAY_SLOW = BIT(0), + ARRAY_FAST = BIT(1), + DUAL_OUTPUT_FAST = BIT(2), + QUAD_OUTPUT_FAST = BIT(3), + DUAL_IO_FAST = BIT(4), + QUAD_IO_FAST = BIT(5), }; /* Normal - Extended - Full command set */ @@ -37,20 +37,20 @@ enum spi_read_cmds { /* sf param flags */ enum { -#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS - SECT_4K = 1 << 0, +#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS + SECT_4K = 0, #else - SECT_4K = 0 << 0, + SECT_4K = BIT(0), #endif - SECT_32K = 1 << 1, - E_FSR = 1 << 2, - SST_WR = 1 << 3, - WR_QPP = 1 << 4, + SECT_32K = BIT(1), + E_FSR = BIT(2), + SST_WR = BIT(3), + WR_QPP = BIT(4), }; enum spi_nor_option_flags { - SNOR_F_SST_WR = (1 << 0), - SNOR_F_USE_FSR = (1 << 1), + SNOR_F_SST_WR = BIT(0), + SNOR_F_USE_FSR = BIT(1), }; #define SPI_FLASH_3B_ADDR_LEN 3 @@ -75,12 +75,9 @@ enum spi_nor_option_flags { #define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 -#define CMD_READ_STATUS 0x05 -#define CMD_QUAD_PAGE_PROGRAM 0x32 -#define CMD_READ_STATUS1 0x35 #define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_CONFIG 0x35 -#define CMD_FLAG_STATUS 0x70 +#define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -90,6 +87,11 @@ enum spi_nor_option_flags { #define CMD_READ_QUAD_OUTPUT_FAST 0x6b #define CMD_READ_QUAD_IO_FAST 0xeb #define CMD_READ_ID 0x9f +#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS1 0x35 +#define CMD_READ_CONFIG 0x35 +#define CMD_FLAG_STATUS 0x70 +#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -100,10 +102,11 @@ enum spi_nor_option_flags { #endif /* Common status */ -#define STATUS_WIP (1 << 0) -#define STATUS_QEB_WINSPAN (1 << 1) -#define STATUS_QEB_MXIC (1 << 6) -#define STATUS_PEC (1 << 7) +#define STATUS_WIP BIT(0) +#define STATUS_QEB_WINSPAN BIT(1) +#define STATUS_QEB_MXIC BIT(6) +#define STATUS_PEC BIT(7) +#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 0cafc291230..daa1d5b249e 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -128,7 +128,7 @@ static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, #if defined(CONFIG_SPI_FLASH_SST) if (flash->flags & SNOR_F_SST_WR) { - if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + if (flash->spi->mode & SPI_TX_BYTE) return sst_write_bp(flash, offset, len, buf); else return sst_write_wp(flash, offset, len, buf); diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index b7b7f0044e7..a5674146690 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -29,16 +29,6 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -/* Read commands array */ -static u8 spi_read_cmds_array[] = { - CMD_READ_ARRAY_SLOW, - CMD_READ_ARRAY_FAST, - CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_OUTPUT_FAST, - CMD_READ_QUAD_IO_FAST, -}; - static int read_sr(struct spi_flash *flash, u8 *rs) { int ret; @@ -121,6 +111,37 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int read_evcr(struct spi_flash *flash, u8 *evcr) +{ + int ret; + const u8 cmd = CMD_READ_EVCR; + + ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); + if (ret < 0) { + debug("SF: error reading EVCR\n"); + return ret; + } + + return 0; +} + +static int write_evcr(struct spi_flash *flash, u8 evcr) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_EVCR; + ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); + if (ret < 0) { + debug("SF: error while writing EVCR register\n"); + return ret; + } + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) { @@ -149,7 +170,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) int ret; if (flash->size <= SPI_FLASH_16MB_BOUN) - goto bank_end; + goto bar_end; switch (idcode0) { case SPI_FLASH_CFI_MFR_SPANSION: @@ -168,7 +189,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) return ret; } -bank_end: +bar_end: flash->bank_curr = curr_bank; return 0; } @@ -177,13 +198,15 @@ bank_end: #ifdef CONFIG_SF_DUAL_FLASH static void spi_flash_dual(struct spi_flash *flash, u32 *addr) { + struct spi_slave *spi = flash->spi; + switch (flash->dual_flash) { case SF_DUAL_STACKED_FLASH: if (*addr >= (flash->size >> 1)) { *addr -= flash->size >> 1; - flash->spi->flags |= SPI_XFER_U_PAGE; + spi->flags |= SPI_XFER_U_PAGE; } else { - flash->spi->flags &= ~SPI_XFER_U_PAGE; + spi->flags &= ~SPI_XFER_U_PAGE; } break; case SF_DUAL_PARALLEL_FLASH: @@ -268,7 +291,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, if (buf == NULL) timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: unable to claim SPI bus\n"); return ret; @@ -353,6 +376,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { + struct spi_slave *spi = flash->spi; unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; @@ -385,9 +409,9 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, byte_addr = offset % page_size; chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); - if (flash->spi->max_write_size) + if (spi->max_write_size) chunk_len = min(chunk_len, - (size_t)flash->spi->max_write_size); + (size_t)spi->max_write_size); spi_flash_addr(write_addr, cmd); @@ -413,7 +437,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, struct spi_slave *spi = flash->spi; int ret; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: unable to claim SPI bus\n"); return ret; @@ -438,6 +462,7 @@ void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { + struct spi_slave *spi = flash->spi; u8 *cmd, cmdsz; u32 remain_len, read_len, read_addr; int bank_sel = 0; @@ -445,15 +470,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, /* Handle memory-mapped SPI */ if (flash->memory_map) { - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: unable to claim SPI bus\n"); return ret; } - spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); spi_flash_copy_mmap(data, flash->memory_map + offset, len); - spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END); - spi_release_bus(flash->spi); + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); + spi_release_bus(spi); return 0; } @@ -505,6 +530,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, #ifdef CONFIG_SPI_FLASH_SST static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) { + struct spi_slave *spi = flash->spi; int ret; u8 cmd[4] = { CMD_SST_BP, @@ -514,13 +540,13 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) }; debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); + spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); ret = spi_flash_cmd_write_enable(flash); if (ret) return ret; - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); if (ret) return ret; @@ -530,11 +556,12 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { + struct spi_slave *spi = flash->spi; size_t actual, cmd_len; int ret; u8 cmd[4]; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: Unable to claim SPI bus\n"); return ret; @@ -561,10 +588,10 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, for (; actual < len - 1; actual += 2) { debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, + spi_w8r8(spi, CMD_READ_STATUS), buf + actual, cmd[0], offset); - ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf + actual, 2); if (ret) { debug("SF: sst word program failed\n"); @@ -590,17 +617,18 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, debug("SF: sst: program %s %zu bytes @ 0x%zx\n", ret ? "failure" : "success", len, offset - actual); - spi_release_bus(flash->spi); + spi_release_bus(spi); return ret; } int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { + struct spi_slave *spi = flash->spi; size_t actual; int ret; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: Unable to claim SPI bus\n"); return ret; @@ -621,7 +649,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, debug("SF: sst: program %s %zu bytes @ 0x%zx\n", ret ? "failure" : "success", len, offset - actual); - spi_release_bus(flash->spi); + spi_release_bus(spi); return ret; } #endif @@ -803,7 +831,7 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) #ifdef CONFIG_SPI_FLASH_MACRONIX -static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +static int macronix_quad_enable(struct spi_flash *flash) { u8 qeb_status; int ret; @@ -812,12 +840,18 @@ static int spi_flash_set_qeb_mxic(struct spi_flash *flash) if (ret < 0) return ret; - if (qeb_status & STATUS_QEB_MXIC) { - debug("SF: mxic: QEB is already set\n"); - } else { - ret = write_sr(flash, STATUS_QEB_MXIC); - if (ret < 0) - return ret; + if (qeb_status & STATUS_QEB_MXIC) + return 0; + + ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC); + if (ret < 0) + return ret; + + /* read SR and check it */ + ret = read_sr(flash, &qeb_status); + if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) { + printf("SF: Macronix SR Quad bit not clear\n"); + return -EINVAL; } return ret; @@ -825,7 +859,7 @@ static int spi_flash_set_qeb_mxic(struct spi_flash *flash) #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) -static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +static int spansion_quad_enable(struct spi_flash *flash) { u8 qeb_status; int ret; @@ -834,34 +868,67 @@ static int spi_flash_set_qeb_winspan(struct spi_flash *flash) if (ret < 0) return ret; - if (qeb_status & STATUS_QEB_WINSPAN) { - debug("SF: winspan: QEB is already set\n"); - } else { - ret = write_cr(flash, STATUS_QEB_WINSPAN); - if (ret < 0) - return ret; + if (qeb_status & STATUS_QEB_WINSPAN) + return 0; + + ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + + /* read CR and check it */ + ret = read_cr(flash, &qeb_status); + if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) { + printf("SF: Spansion CR Quad bit not clear\n"); + return -EINVAL; + } + + return ret; +} +#endif + +#ifdef CONFIG_SPI_FLASH_STMICRO +static int micron_quad_enable(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (!(qeb_status & STATUS_QEB_MICRON)) + return 0; + + ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); + if (ret < 0) + return ret; + + /* read EVCR and check it */ + ret = read_evcr(flash, &qeb_status); + if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { + printf("SF: Micron EVCR Quad bit not clear\n"); + return -EINVAL; } return ret; } #endif -static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) +static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { #ifdef CONFIG_SPI_FLASH_MACRONIX case SPI_FLASH_CFI_MFR_MACRONIX: - return spi_flash_set_qeb_mxic(flash); + return macronix_quad_enable(flash); #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) case SPI_FLASH_CFI_MFR_SPANSION: case SPI_FLASH_CFI_MFR_WINBOND: - return spi_flash_set_qeb_winspan(flash); + return spansion_quad_enable(flash); #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); @@ -902,9 +969,15 @@ int spi_flash_scan(struct spi_flash *flash) struct spi_slave *spi = flash->spi; const struct spi_flash_params *params; u16 jedec, ext_jedec; - u8 idcode[5]; - u8 cmd; + u8 cmd, idcode[5]; int ret; + static u8 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_ARRAY_FAST, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_IO_FAST }; /* Read the ID codes */ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); @@ -950,7 +1023,7 @@ int spi_flash_scan(struct spi_flash *flash) /* Assign spi data */ flash->name = params->name; flash->memory_map = spi->memory_map; - flash->dual_flash = flash->spi->option; + flash->dual_flash = spi->option; /* Assign spi flash flags */ if (params->flags & SST_WR) @@ -961,7 +1034,7 @@ int spi_flash_scan(struct spi_flash *flash) flash->write = spi_flash_cmd_write_ops; #if defined(CONFIG_SPI_FLASH_SST) if (flash->flags & SNOR_F_SST_WR) { - if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + if (spi->mode & SPI_TX_BYTE) flash->write = sst_write_bp; else flash->write = sst_write_wp; @@ -1025,7 +1098,7 @@ int spi_flash_scan(struct spi_flash *flash) flash->sector_size = flash->erase_size; /* Look for the fastest read cmd */ - cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); + cmd = fls(params->e_rd_cmd & spi->mode_rx); if (cmd) { cmd = spi_read_cmds_array[cmd - 1]; flash->read_cmd = cmd; @@ -1035,7 +1108,7 @@ int spi_flash_scan(struct spi_flash *flash) } /* Not require to look for fastest only two write cmds yet */ - if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; else /* Go for default supported write cmd */ @@ -1045,7 +1118,7 @@ int spi_flash_scan(struct spi_flash *flash) if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { - ret = spi_flash_set_qeb(flash, idcode[0]); + ret = set_quad_mode(flash, idcode[0]); if (ret) { debug("SF: Fail to set QEB for %02x\n", idcode[0]); return -EINVAL; diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index 3eaa2706777..92a1b644958 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -417,7 +417,7 @@ static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) bus->read = tse_mdio_read; bus->write = tse_mdio_write; - snprintf(bus->name, sizeof(bus->name), name); + snprintf(bus->name, sizeof(bus->name), "%s", name); bus->priv = (void *)priv; diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index d51e098c560..26595929c51 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -490,7 +490,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase) memset(emacfix, 0, sizeof(emac_device)); memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "emac"); + strcpy(dev->name, "emac"); dev->iobase = iobase; dev->priv = emacfix; dev->init = at91emac_init; diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c index ded9e064e51..43a67a514bb 100644 --- a/drivers/net/ax88180.c +++ b/drivers/net/ax88180.c @@ -722,7 +722,7 @@ int ax88180_initialize (bd_t * bis) memset (priv, 0, sizeof *priv); - sprintf (dev->name, "ax88180"); + strcpy(dev->name, "ax88180"); dev->iobase = AX88180_BASE; dev->priv = priv; dev->init = ax88180_init; diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 3dff9df3779..71047544634 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -567,7 +567,7 @@ static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) bus->read = cpsw_mdio_read; bus->write = cpsw_mdio_write; - sprintf(bus->name, name); + strcpy(bus->name, name); mdio_register(bus); } diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 04447953c92..92c3dcae3c9 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -777,7 +777,7 @@ int davinci_emac_initialize(void) return -1; memset(dev, 0, sizeof *dev); - sprintf(dev->name, "DaVinci-EMAC"); + strcpy(dev->name, "DaVinci-EMAC"); dev->iobase = 0; dev->init = davinci_eth_open; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 0fccbc0040a..68b6548309e 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -81,7 +81,7 @@ static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) bus->read = dw_mdio_read; bus->write = dw_mdio_write; - snprintf(bus->name, sizeof(bus->name), name); + snprintf(bus->name, sizeof(bus->name), "%s", name); bus->priv = (void *)mac_regs_p; diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 3c41cec3e4d..93c6667bca9 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -630,7 +630,7 @@ int dm9000_initialize(bd_t *bis) dev->halt = dm9000_halt; dev->send = dm9000_send; dev->recv = dm9000_rx; - sprintf(dev->name, "dm9000"); + strcpy(dev->name, "dm9000"); eth_register(dev); diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 027f2bfd11f..70fc02ee5ca 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -551,43 +551,6 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->use_eerd = true; eeprom->use_eewr = false; break; - - /* ich8lan does not support currently. if needed, please - * add corresponding code and functions. - */ -#if 0 - case e1000_ich8lan: - { - int32_t i = 0; - - eeprom->type = e1000_eeprom_ich8; - eeprom->use_eerd = false; - eeprom->use_eewr = false; - eeprom->word_size = E1000_SHADOW_RAM_WORDS; - uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, - ICH_FLASH_GFPREG); - /* Zero the shadow RAM structure. But don't load it from NVM - * so as to save time for driver init */ - if (hw->eeprom_shadow_ram != NULL) { - for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = false; - hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; - } - } - - hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * - ICH_FLASH_SECTOR_SIZE; - - hw->flash_bank_size = ((flash_size >> 16) - & ICH_GFPREG_BASE_MASK) + 1; - hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); - - hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; - - hw->flash_bank_size /= 2 * sizeof(uint16_t); - break; - } -#endif default: break; } @@ -838,14 +801,6 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, if (eeprom->use_eerd == true) return e1000_read_eeprom_eerd(hw, offset, words, data); - /* ich8lan does not support currently. if needed, please - * add corresponding code and functions. - */ -#if 0 - /* ICH EEPROM access is done via the ICH flash controller */ - if (eeprom->type == e1000_eeprom_ich8) - return e1000_read_eeprom_ich8(hw, offset, words, data); -#endif /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have * acquired the EEPROM at this point, so any returns should relase it */ if (eeprom->type == e1000_eeprom_spi) { @@ -1732,17 +1687,7 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) * occuring when accessing our register space */ E1000_WRITE_FLUSH(hw); } -#if 0 - /* Set the PCI priority bit correctly in the CTRL register. This - * determines if the adapter gives priority to receives, or if it - * gives equal priority to transmits and receives. Valid only on - * 82542 and 82543 silicon. - */ - if (hw->dma_fairness && hw->mac_type <= e1000_82543) { - ctrl = E1000_READ_REG(hw, CTRL); - E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); - } -#endif + switch (hw->mac_type) { case e1000_82545_rev_3: case e1000_82546_rev_3: @@ -1842,20 +1787,6 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) break; } -#if 0 - /* Clear all of the statistics registers (clear on read). It is - * important that we do this after we have tried to establish link - * because the symbol error count will increment wildly if there - * is no link. - */ - e1000_clear_hw_cntrs(hw); - - /* ICH8 No-snoop bits are opposite polarity. - * Set to snoop by default after reset. */ - if (hw->mac_type == e1000_ich8lan) - e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); -#endif - if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); @@ -5230,10 +5161,6 @@ _e1000_disable(struct e1000_hw *hw) E1000_WRITE_REG(hw, RDH, 0); E1000_WRITE_REG(hw, RDT, 0); - /* put the card in its initial state */ -#if 0 - E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); -#endif mdelay(10); } @@ -5359,7 +5286,6 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, #ifndef CONFIG_E1000_NO_NVM /* Validate the EEPROM and get chipset information */ -#if !defined(CONFIG_MVBC_1G) if (e1000_init_eeprom_params(hw)) { E1000_ERR(hw, "EEPROM is invalid!\n"); return -EINVAL; @@ -5367,7 +5293,6 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && e1000_validate_eeprom_checksum(hw)) return -ENXIO; -#endif e1000_read_mac_addr(hw, enetaddr); #endif e1000_get_bus_type(hw); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index c851922ae5c..e46edcd4e1d 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1093,11 +1093,6 @@ struct e1000_hw { e1000_media_type media_type; e1000_fc_type fc; e1000_bus_type bus_type; -#if 0 - e1000_bus_speed bus_speed; - e1000_bus_width bus_width; - uint32_t io_base; -#endif uint32_t asf_firmware_present; #ifndef CONFIG_E1000_NO_NVM uint32_t eeprom_semaphore_present; @@ -1116,29 +1111,11 @@ struct e1000_hw { uint32_t original_fc; uint32_t txcw; uint32_t autoneg_failed; -#if 0 - uint32_t max_frame_size; - uint32_t min_frame_size; - uint32_t mc_filter_type; - uint32_t num_mc_addrs; - uint32_t collision_delta; - uint32_t tx_packet_delta; - uint32_t ledctl_default; - uint32_t ledctl_mode1; - uint32_t ledctl_mode2; -#endif uint16_t autoneg_advertised; uint16_t pci_cmd_word; uint16_t fc_high_water; uint16_t fc_low_water; uint16_t fc_pause_time; -#if 0 - uint16_t current_ifs_val; - uint16_t ifs_min_val; - uint16_t ifs_max_val; - uint16_t ifs_step_size; - uint16_t ifs_ratio; -#endif uint16_t device_id; uint16_t vendor_id; uint16_t subsystem_id; @@ -1149,9 +1126,6 @@ struct e1000_hw { uint8_t forced_speed_duplex; uint8_t wait_autoneg_complete; uint8_t dma_fairness; -#if 0 - uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; -#endif bool disable_polarity_correction; bool speed_downgraded; bool get_link_status; @@ -1162,11 +1136,6 @@ struct e1000_hw { bool report_tx_early; bool phy_reset_disable; bool initialize_hw_bits_disable; -#if 0 - bool adaptive_ifs; - bool ifs_params_forced; - bool in_ifs_mode; -#endif e1000_smart_speed smart_speed; e1000_dsp_config dsp_config_state; }; diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index df72375238f..576ddb8b242 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -182,22 +182,21 @@ static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr) * These have been tested to perform correctly, but they are not used by any * of the EEPROM commands at this time. */ -#if 0 -static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr) +static __maybe_unused int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, + bool intr) { u8 op[] = { SPI_EEPROM_DISABLE_WR }; e1000_standby_eeprom(hw); return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); } -static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, - u8 status, bool intr) +static __maybe_unused int e1000_spi_eeprom_write_status(struct e1000_hw *hw, + u8 status, bool intr) { u8 op[] = { SPI_EEPROM_WRITE_STATUS, status }; e1000_standby_eeprom(hw); return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); } -#endif static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr) { diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index df5db723ba2..40fbf19c757 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -395,7 +395,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) printf("\nMMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 4ab78e6c253..50793426826 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -146,7 +146,7 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) bus->read = memac_mdio_read; bus->write = memac_mdio_write; bus->reset = memac_mdio_reset; - sprintf(bus->name, info->name); + strcpy(bus->name, info->name); bus->priv = info->regs; diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index 24cb17b6edd..f038541c8de 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -118,7 +118,7 @@ int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info) bus->read = tgec_mdio_read; bus->write = tgec_mdio_write; bus->reset = tgec_mdio_reset; - sprintf(bus->name, info->name); + strcpy(bus->name, info->name); bus->priv = info->regs; diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index d6b181b3860..f48bbc31239 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -104,7 +104,7 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info) bus->read = tsec_phy_read; bus->write = tsec_phy_write; bus->reset = fsl_pq_mdio_reset; - sprintf(bus->name, info->name); + strcpy(bus->name, info->name); bus->priv = (void *)info->regs; diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 515f0b2746c..5ccc4beda81 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -562,7 +562,7 @@ int ftgmac100_initialize(bd_t *bd) memset(dev, 0, sizeof(*dev)); memset(priv, 0, sizeof(*priv)); - sprintf(dev->name, "FTGMAC100"); + strcpy(dev->name, "FTGMAC100"); dev->iobase = CONFIG_FTGMAC100_BASE; dev->init = ftgmac100_init; dev->halt = ftgmac100_halt; diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index bd94f83f044..1fc7da9a3e7 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -246,7 +246,7 @@ int ftmac100_initialize (bd_t *bd) memset (dev, 0, sizeof (*dev)); memset (priv, 0, sizeof (*priv)); - sprintf (dev->name, "FTMAC100"); + strcpy(dev->name, "FTMAC100"); dev->iobase = CONFIG_FTMAC100_BASE; dev->init = ftmac100_init; dev->halt = ftmac100_halt; diff --git a/drivers/net/greth.c b/drivers/net/greth.c index 088cb229da1..aa5d7114a5b 100644 --- a/drivers/net/greth.c +++ b/drivers/net/greth.c @@ -640,9 +640,9 @@ int greth_initialize(bd_t * bis) /* Make descriptor string */ if (greth->gbit_mac) { - sprintf(dev->name, "GRETH_10/100/GB"); + strcpy(dev->name, "GRETH_10/100/GB"); } else { - sprintf(dev->name, "GRETH_10/100"); + strcpy(dev->name, "GRETH_10/100"); } /* initiate PHY, select speed/duplex depending on connected PHY */ diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 24ca52e2dfb..209fae94a77 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -586,7 +586,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) mdio_bus->write = keystone2_mdio_write; mdio_bus->reset = keystone2_mdio_reset; mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; - sprintf(mdio_bus->name, "ethernet-mdio"); + strcpy(mdio_bus->name, "ethernet-mdio"); res = mdio_register(mdio_bus); if (res) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 69530b11cf1..3857122bd05 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -628,11 +628,11 @@ static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv) #endif memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint)); - sprintf(dpmac_endpoint.type, "dpmac"); + strcpy(dpmac_endpoint.type, "dpmac"); dpmac_endpoint.id = priv->dpmac_id; memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint)); - sprintf(dpni_endpoint.type, "dpni"); + strcpy(dpni_endpoint.type, "dpni"); dpni_endpoint.id = dflt_dpni->dpni_id; err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS, diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index e76e9bc2b5b..6cc273c33c8 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -304,6 +304,13 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; } + /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + ®s->madr); + + /* write data to the MII write register */ + writel(data, ®s->mwtd); + /* wait till the MII is not busy */ timeout = MII_TIMEOUT; do { @@ -319,13 +326,6 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; } - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - ®s->madr); - - /* write data to the MII write register */ - writel(data, ®s->mwtd); - /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, reg_ofs, data);*/ @@ -582,7 +582,7 @@ int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) } bus->read = lpc32xx_eth_phy_read; bus->write = lpc32xx_eth_phy_write; - sprintf(bus->name, dev->name); + strcpy(bus->name, dev->name); ret = mdio_register(bus); if (ret) { diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index 22ea114f01b..e850672a4ff 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -635,7 +635,7 @@ int mpc512x_fec_initialize (bd_t * bis) dev->send = mpc512x_fec_send; dev->recv = mpc512x_fec_recv; - sprintf (dev->name, "FEC"); + strcpy(dev->name, "FEC"); eth_register (dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index 2ebd1761c3e..e13b4cf32b4 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -913,7 +913,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) dev->send = mpc5xxx_fec_send; dev->recv = mpc5xxx_fec_recv; - sprintf(dev->name, "FEC"); + strcpy(dev->name, "FEC"); eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index ab5aa68fc8c..b16be921428 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -675,7 +675,7 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid) } bus->read = mvgbe_phy_read; bus->write = mvgbe_phy_write; - sprintf(bus->name, dev->name); + strcpy(bus->name, dev->name); ret = mdio_register(bus); if (ret) { diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 38ad14eff96..fa20f548e52 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -2,7 +2,7 @@ * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. * * U-Boot version: - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> * * Based on the Linux version which is: * Copyright (C) 2012 Marvell @@ -14,6 +14,7 @@ */ #include <common.h> +#include <dm.h> #include <net.h> #include <netdev.h> #include <config.h> @@ -28,6 +29,8 @@ #include <linux/compat.h> #include <linux/mbus.h> +DECLARE_GLOBAL_DATA_PTR; + #if !defined(CONFIG_PHYLIB) # error Marvell mvneta requires PHYLIB #endif @@ -1115,9 +1118,9 @@ static void mvneta_start_dev(struct mvneta_port *pp) mvneta_port_enable(pp); } -static void mvneta_adjust_link(struct eth_device *dev) +static void mvneta_adjust_link(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); struct phy_device *phydev = pp->phydev; int status_change = 0; @@ -1171,9 +1174,9 @@ static void mvneta_adjust_link(struct eth_device *dev) } } -static int mvneta_open(struct eth_device *dev) +static int mvneta_open(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); int ret; ret = mvneta_setup_rxqs(pp); @@ -1192,7 +1195,7 @@ static int mvneta_open(struct eth_device *dev) } /* Initialize hw */ -static int mvneta_init(struct mvneta_port *pp) +static int mvneta_init2(struct mvneta_port *pp) { int queue; @@ -1314,23 +1317,22 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) } /* Device initialization routine */ -static int mvneta_probe(struct eth_device *dev) +static int mvneta_init(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct mvneta_port *pp = dev_get_priv(dev); int err; pp->tx_ring_size = MVNETA_MAX_TXD; pp->rx_ring_size = MVNETA_MAX_RXD; - err = mvneta_init(pp); + err = mvneta_init2(pp); if (err < 0) { dev_err(&pdev->dev, "can't init eth hal\n"); return err; } - mvneta_conf_mbus_windows(pp); - - mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def); + mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def); err = mvneta_port_power_up(pp, pp->phy_interface); if (err < 0) { @@ -1367,25 +1369,24 @@ static int smi_wait_ready(struct mvneta_port *pp) } /* - * smi_reg_read - miiphy_read callback function. + * mvneta_mdio_read - miiphy_read callback function. * * Returns 16bit phy register value, or 0xffff on error */ -static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct eth_device *dev = eth_get_dev_by_name(devname); - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = bus->priv; u32 smi_reg; u32 timeout; /* check parameters */ - if (phy_adr > MVNETA_PHY_ADDR_MASK) { - printf("Error: Invalid PHY address %d\n", phy_adr); + if (addr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", addr); return -EFAULT; } - if (reg_ofs > MVNETA_PHY_REG_MASK) { - printf("Err: Invalid register offset %d\n", reg_ofs); + if (reg > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg); return -EFAULT; } @@ -1394,14 +1395,14 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) return -EFAULT; /* fill the phy address and regiser offset and read opcode */ - smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) - | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS) + smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg << MVNETA_SMI_REG_ADDR_OFFS) | MVNETA_SMI_OPCODE_READ; /* write the smi register */ mvreg_write(pp, MVNETA_SMI, smi_reg); - /*wait till read value is ready */ + /* wait till read value is ready */ timeout = MVNETA_SMI_TIMEOUT; do { @@ -1417,31 +1418,29 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) ; - *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK); - - return 0; + return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK; } /* - * smi_reg_write - imiiphy_write callback function. + * mvneta_mdio_write - miiphy_write callback function. * * Returns 0 if write succeed, -EINVAL on bad parameters * -ETIME on timeout */ -static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { - struct eth_device *dev = eth_get_dev_by_name(devname); - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = bus->priv; u32 smi_reg; /* check parameters */ - if (phy_adr > MVNETA_PHY_ADDR_MASK) { - printf("Error: Invalid PHY address %d\n", phy_adr); + if (addr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", addr); return -EFAULT; } - if (reg_ofs > MVNETA_PHY_REG_MASK) { - printf("Err: Invalid register offset %d\n", reg_ofs); + if (reg > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg); return -EFAULT; } @@ -1450,9 +1449,9 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; /* fill the phy addr and reg offset and write opcode and data */ - smi_reg = (data << MVNETA_SMI_DATA_OFFS); - smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) - | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS); + smi_reg = value << MVNETA_SMI_DATA_OFFS; + smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg << MVNETA_SMI_REG_ADDR_OFFS); smi_reg &= ~MVNETA_SMI_OPCODE_READ; /* write the smi register */ @@ -1461,9 +1460,9 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return 0; } -static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) +static int mvneta_start(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); struct phy_device *phydev; mvneta_port_power_up(pp, pp->phy_interface); @@ -1483,7 +1482,7 @@ static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) } /* Full init on first call */ - mvneta_probe(dev); + mvneta_init(dev); pp->init = 1; } else { /* Upon all following calls, this is enough */ @@ -1494,9 +1493,9 @@ static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) return 0; } -static int mvneta_send(struct eth_device *dev, void *ptr, int len) +static int mvneta_send(struct udevice *dev, void *packet, int length) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); struct mvneta_tx_queue *txq = &pp->txqs[0]; struct mvneta_tx_desc *tx_desc; int sent_desc; @@ -1505,9 +1504,9 @@ static int mvneta_send(struct eth_device *dev, void *ptr, int len) /* Get a descriptor for the first part of the packet */ tx_desc = mvneta_txq_next_desc_get(txq); - tx_desc->buf_phys_addr = (u32)ptr; - tx_desc->data_size = len; - flush_dcache_range((u32)ptr, (u32)ptr + len); + tx_desc->buf_phys_addr = (u32)packet; + tx_desc->data_size = length; + flush_dcache_range((u32)packet, (u32)packet + length); /* First and Last descriptor */ tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; @@ -1525,28 +1524,25 @@ static int mvneta_send(struct eth_device *dev, void *ptr, int len) /* txDone has increased - hw sent packet */ mvneta_txq_sent_desc_dec(pp, txq, sent_desc); - return 0; return 0; } -static int mvneta_recv(struct eth_device *dev) +static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); int rx_done; - int packets_done; struct mvneta_rx_queue *rxq; + int rx_bytes = 0; /* get rx queue */ rxq = mvneta_rxq_handle_get(pp, rxq_def); rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); - packets_done = rx_done; - while (packets_done--) { + if (rx_done) { struct mvneta_rx_desc *rx_desc; unsigned char *data; u32 rx_status; - int rx_bytes; /* * No cache invalidation needed here, since the desc's are @@ -1559,7 +1555,7 @@ static int mvneta_recv(struct eth_device *dev) (rx_status & MVNETA_RXD_ERR_SUMMARY)) { mvneta_rx_error(pp, rx_desc); /* leave the descriptor untouched */ - continue; + return -EIO; } /* 2 bytes for marvell header. 4 bytes for crc */ @@ -1571,40 +1567,24 @@ static int mvneta_recv(struct eth_device *dev) * No cache invalidation needed here, since the rx_buffer's are * located in a uncached memory region */ - net_process_received_packet(data, rx_bytes); - } + *packetp = data; - /* Update rxq management counters */ - if (rx_done) mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); + } - return 0; -} - -static void mvneta_halt(struct eth_device *dev) -{ - struct mvneta_port *pp = dev->priv; - - mvneta_port_down(pp); - mvneta_port_disable(pp); + return rx_bytes; } -int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) +static int mvneta_probe(struct udevice *dev) { - struct eth_device *dev; - struct mvneta_port *pp; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct mvneta_port *pp = dev_get_priv(dev); + void *blob = (void *)gd->fdt_blob; + int node = dev->of_offset; + struct mii_dev *bus; + unsigned long addr; void *bd_space; - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -ENOMEM; - - pp = calloc(1, sizeof(*pp)); - if (pp == NULL) - return -ENOMEM; - - dev->priv = pp; - /* * Allocate buffer area for descs and rx_buffers. This is only * done once for all interfaces. As only one interface can @@ -1625,28 +1605,82 @@ int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); } - sprintf(dev->name, "neta%d", devnum); + pp->base = (void __iomem *)pdata->iobase; - pp->base = (void __iomem *)base_addr; - dev->iobase = base_addr; - dev->init = mvneta_init_u_boot; - dev->halt = mvneta_halt; - dev->send = mvneta_send; - dev->recv = mvneta_recv; - dev->write_hwaddr = NULL; + /* Configure MBUS address windows */ + mvneta_conf_mbus_windows(pp); - /* - * The PHY interface type is configured via the - * board specific CONFIG_SYS_NETA_INTERFACE_TYPE - * define. - */ - pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE; + /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ + pp->phy_interface = pdata->phy_interface; + + /* Now read phyaddr from DT */ + addr = fdtdec_get_int(blob, node, "phy", 0); + addr = fdt_node_offset_by_phandle(blob, addr); + pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mvneta_mdio_read; + bus->write = mvneta_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)pp; + pp->bus = bus; - eth_register(dev); + return mdio_register(bus); +} - pp->phyaddr = phy_addr; - miiphy_register(dev->name, smi_reg_read, smi_reg_write); - pp->bus = miiphy_get_dev_by_name(dev->name); +static void mvneta_stop(struct udevice *dev) +{ + struct mvneta_port *pp = dev_get_priv(dev); - return 1; + mvneta_port_down(pp); + mvneta_port_disable(pp); } + +static const struct eth_ops mvneta_ops = { + .start = mvneta_start, + .send = mvneta_send, + .recv = mvneta_recv, + .stop = mvneta_stop, +}; + +static int mvneta_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + + pdata->iobase = dev_get_addr(dev); + + /* Get phy-mode / phy_interface from DT */ + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + +static const struct udevice_id mvneta_ids[] = { + { .compatible = "marvell,armada-370-neta" }, + { .compatible = "marvell,armada-xp-neta" }, + { } +}; + +U_BOOT_DRIVER(mvneta) = { + .name = "mvneta", + .id = UCLASS_ETH, + .of_match = mvneta_ids, + .ofdata_to_platdata = mvneta_ofdata_to_platdata, + .probe = mvneta_probe, + .ops = &mvneta_ops, + .priv_auto_alloc_size = sizeof(struct mvneta_port), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index 07a7cec2a85..887cfd957b3 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -794,7 +794,7 @@ int ne2k_register(void) dev->send = ne2k_send; dev->recv = ne2k_recv; - sprintf(dev->name, "NE2000"); + strcpy(dev->name, "NE2000"); return eth_register(dev); } diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 1b4dd56d52b..56d29d47af7 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -386,7 +386,7 @@ static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs) bus->read = pch_gbe_mdio_read; bus->write = pch_gbe_mdio_write; - sprintf(bus->name, name); + strcpy(bus->name, name); bus->priv = (void *)mac_regs; diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index cfcb1b4e233..16a7512b0c5 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -134,8 +134,17 @@ static int pcnet_recv (struct eth_device *dev); static void pcnet_halt (struct eth_device *dev); static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); -#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a)) -#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) +static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev, + void *addr, bool uncached) +{ + pci_dev_t devbusfn = (pci_dev_t)dev->priv; + void *virt_addr = addr; + + if (uncached) + virt_addr = (void *)CKSEG0ADDR(addr); + + return pci_virt_to_mem(devbusfn, virt_addr); +} static struct pci_device_id supported[] = { {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, @@ -352,7 +361,8 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); + addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false); + uc->rx_ring[i].base = cpu_to_le32(addr); uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); uc->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 @@ -383,8 +393,10 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | RX_RING_LEN_BITS); - uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); - uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); + addr = pcnet_virt_to_mem(dev, uc->rx_ring, true); + uc->init_block.rx_ring = cpu_to_le32(addr); + addr = pcnet_virt_to_mem(dev, uc->tx_ring, true); + uc->init_block.tx_ring = cpu_to_le32(addr); PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", uc->init_block.tlen_rlen, @@ -394,7 +406,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) * Tell the controller where the Init Block is located. */ barrier(); - addr = PCI_TO_MEM(dev, &lp->uc->init_block); + addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true); pcnet_write_csr(dev, 1, addr & 0xffff); pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); @@ -424,6 +436,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) { int i, status; + u32 addr; struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, @@ -451,9 +464,10 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) * Setup Tx ring. Caution: the write order is important here, * set the status with the "ownership" bits last. */ + addr = pcnet_virt_to_mem(dev, packet, false); writew(-pkt_len, &entry->length); writel(0, &entry->misc); - writel(PCI_TO_MEM(dev, packet), &entry->base); + writel(addr, &entry->base); writew(0x8300, &entry->status); /* Trigger an immediate send poll. */ diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 3a2b3bba995..447ecfbeb6d 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -174,7 +174,8 @@ void cs4340_upload_firmware(struct phy_device *phydev) printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index a320b4d75b6..443a4da5275 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -560,7 +560,7 @@ int sh_eth_initialize(bd_t *bd) dev->recv = sh_eth_recv; eth->port_info[eth->port].dev = dev; - sprintf(dev->name, SHETHER_NAME); + strcpy(dev->name, SHETHER_NAME); /* Register Device to EtherNet subsystem */ eth_register(dev); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 4bdc188c8f3..9b09caf8c83 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -632,7 +632,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; - sprintf(dev->name, tsec_info->devname); + strcpy(dev->name, tsec_info->devname); priv->interface = tsec_info->interface; priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); dev->iobase = 0; diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 842eafc4f8f..5cfa135ba6e 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -375,6 +375,7 @@ int dm_pciauto_config_device(struct udevice *dev) case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ debug("PCI AutoConfig: Found PowerPC device\n"); + /* fall through */ default: dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io, diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 9126f78b890..edc9a7b3c17 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -101,11 +101,11 @@ void pciauto_setup_device(struct pci_controller *hose, bar_res = prefetch; else bar_res = mem; -#endif debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", bar_nr, bar_res == prefetch ? "Prf" : "Mem", (unsigned long long)bar_size); +#endif } #ifndef CONFIG_PCI_ENUM_ONLY diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index fd2744dbd4e..4eedfe1cbb5 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -155,6 +155,14 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, } #endif +static int mvebu_pex_unit_is_x4(int pex_idx) +{ + int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3; + u32 mask = (0x0f << (pex_unit * 8)); + + return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask; +} + static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) { u32 val; @@ -419,5 +427,11 @@ void pci_init_board(void) writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); bus = hose->last_busno + 1; + + /* need to skip more for X4 links, otherwise scan will hang */ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + if (mvebu_pex_unit_is_x4(i)) + i += 3; + } } } diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 2cb81b66b70..ed2f61dfc33 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -129,14 +129,26 @@ static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp) return 0; } -int pci_rom_load(struct pci_rom_header *rom_header, - struct pci_rom_header **ram_headerp) +/** + * pci_rom_load() - Load a ROM image and return a pointer to it + * + * @rom_header: Pointer to ROM image + * @ram_headerp: Returns a pointer to the image in RAM + * @allocedp: Returns true if @ram_headerp was allocated and needs + * to be freed + * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of + * the error state. Even if this function returns an error, it may have + * allocated memory. + */ +static int pci_rom_load(struct pci_rom_header *rom_header, + struct pci_rom_header **ram_headerp, bool *allocedp) { struct pci_rom_data *rom_data; unsigned int rom_size; unsigned int image_size = 0; void *target; + *allocedp = false; do { /* Get next image, until we see an x86 version */ rom_header = (struct pci_rom_header *)((void *)rom_header + @@ -159,6 +171,7 @@ int pci_rom_load(struct pci_rom_header *rom_header, target = (void *)malloc(rom_size); if (!target) return -ENOMEM; + *allocedp = true; #endif if (target != rom_header) { ulong start = get_timer(0); @@ -253,9 +266,9 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), int exec_method) { struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); - struct pci_rom_header *rom, *ram; + struct pci_rom_header *rom, *ram = NULL; int vesa_mode = -1; - bool emulate; + bool emulate, alloced; int ret; /* Only execute VGA ROMs */ @@ -272,12 +285,14 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), if (ret) return ret; - ret = pci_rom_load(rom, &ram); + ret = pci_rom_load(rom, &ram, &alloced); if (ret) - return ret; + goto err; - if (!board_should_run_oprom(dev)) - return -ENXIO; + if (!board_should_run_oprom(dev)) { + ret = -ENXIO; + goto err; + } #if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \ defined(CONFIG_FRAMEBUFFER_VESA_MODE) @@ -291,7 +306,8 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #else if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) { printf("BIOS native execution is only available on x86\n"); - return -ENOSYS; + ret = -ENOSYS; + goto err; } emulate = true; #endif @@ -301,7 +317,8 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #else if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) { printf("BIOS emulation not available - see CONFIG_BIOSEMU\n"); - return -ENOSYS; + ret = -ENOSYS; + goto err; } emulate = false; #endif @@ -313,12 +330,12 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), ret = biosemu_setup(dm_pci_get_bdf(dev), &info); if (ret) - return ret; + goto err; biosemu_set_interrupt_handler(0x15, int15_handler); ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16, info, true, vesa_mode, &mode_info); if (ret) - return ret; + goto err; #endif } else { #ifdef CONFIG_X86 @@ -329,6 +346,10 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #endif } debug("Final vesa mode %#x\n", mode_info.video_mode); + ret = 0; - return 0; +err: + if (alloced) + free(ram); + return ret; } diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c index 71678b60d3e..7479af734ad 100644 --- a/drivers/power/regulator/max77686.c +++ b/drivers/power/regulator/max77686.c @@ -515,25 +515,19 @@ static int max77686_ldo_enable(struct udevice *dev, int op, bool *enable) switch (on_off) { case OPMODE_OFF: - *enable = 0; + *enable = false; break; case OPMODE_ON: - *enable = 1; + *enable = true; break; default: return -EINVAL; } } else if (op == PMIC_OP_SET) { - switch (*enable) { - case 0: - on_off = OPMODE_OFF; - break; - case 1: + if (*enable) on_off = OPMODE_ON; - break; - default: - return -EINVAL; - } + else + on_off = OPMODE_OFF; ret = max77686_ldo_mode(dev, op, &on_off); if (ret) @@ -651,16 +645,10 @@ static int max77686_buck_enable(struct udevice *dev, int op, bool *enable) return -EINVAL; } } else if (op == PMIC_OP_SET) { - switch (*enable) { - case 0: - on_off = OPMODE_OFF; - break; - case 1: + if (*enable) on_off = OPMODE_ON; - break; - default: - return -EINVAL; - } + else + on_off = OPMODE_OFF; ret = max77686_buck_mode(dev, op, &on_off); if (ret) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 04541c9ff33..92084a2908a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -127,6 +127,22 @@ config DEBUG_UART_APBUART will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_PL010 + bool "pl010" + help + Select this to enable a debug UART using the pl01x driver with the + PL010 UART type. You will need to provide parameters to make this + work. The driver will be available until the real driver model + serial is running. + +config DEBUG_UART_PL011 + bool "pl011" + help + Select this to enable a debug UART using the pl01x driver with the + PL011 UART type. You will need to provide parameters to make this + work. The driver will be available until the real driver model + serial is running. + endchoice config DEBUG_UART_BASE @@ -180,6 +196,12 @@ config DEBUG_UART_ANNOUNCE debug_uart_init()). This can be useful just as a check that everything is working. +config DEBUG_UART_SKIP_INIT + bool "Skip UART initialization" + help + Select this if the UART you want to use for debug output is already + initialized by the time U-Boot starts its execution. + config ALTERA_JTAG_UART bool "Altera JTAG UART support" depends on DM_SERIAL diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index df7eb05e824..4624666e8a2 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -2,18 +2,7 @@ * Copyright (C) 2004-2007 ARM Limited. * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * As a special exception, if other files instantiate templates or use macros * or inline functions from this file, or you compile this file and link it diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c index c8926a8945a..b42537529de 100644 --- a/drivers/serial/lpc32xx_hsuart.c +++ b/drivers/serial/lpc32xx_hsuart.c @@ -1,89 +1,114 @@ /* - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clk.h> -#include <asm/arch/uart.h> -#include <asm/io.h> +#include <dm.h> #include <serial.h> +#include <dm/platform_data/lpc32xx_hsuart.h> + +#include <asm/arch/uart.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; -static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE; +struct lpc32xx_hsuart_priv { + struct hsuart_regs *hsuart; +}; -static void lpc32xx_serial_setbrg(void) +static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate) { + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; u32 div; /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */ - div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1; + div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1; if (div > 255) div = 255; writel(div, &hsuart->rate); + + return 0; } -static int lpc32xx_serial_getc(void) +static int lpc32xx_serial_getc(struct udevice *dev) { - while (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) - /* NOP */; + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; + + if (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) + return -EAGAIN; return readl(&hsuart->rx) & HSUART_RX_DATA; } -static void lpc32xx_serial_putc(const char c) +static int lpc32xx_serial_putc(struct udevice *dev, const char c) { - if (c == '\n') - serial_putc('\r'); + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; + + /* Wait for empty FIFO */ + if (readl(&hsuart->level) & HSUART_LEVEL_TX) + return -EAGAIN; writel(c, &hsuart->tx); - /* Wait for character to be sent */ - while (readl(&hsuart->level) & HSUART_LEVEL_TX) - /* NOP */; + return 0; } -static int lpc32xx_serial_tstc(void) +static int lpc32xx_serial_pending(struct udevice *dev, bool input) { - if (readl(&hsuart->level) & HSUART_LEVEL_RX) - return 1; + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; + + if (input) { + if (readl(&hsuart->level) & HSUART_LEVEL_RX) + return 1; + } else { + if (readl(&hsuart->level) & HSUART_LEVEL_TX) + return 1; + } return 0; } -static int lpc32xx_serial_init(void) +static int lpc32xx_serial_init(struct hsuart_regs *hsuart) { - lpc32xx_serial_setbrg(); - /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */ writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) | HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0, &hsuart->ctrl); + return 0; } -static struct serial_device lpc32xx_serial_drv = { - .name = "lpc32xx_serial", - .start = lpc32xx_serial_init, - .stop = NULL, +static int lpc32xx_hsuart_probe(struct udevice *dev) +{ + struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev); + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + + priv->hsuart = (struct hsuart_regs *)platdata->base; + + lpc32xx_serial_init(priv->hsuart); + + return 0; +} + +static const struct dm_serial_ops lpc32xx_hsuart_ops = { .setbrg = lpc32xx_serial_setbrg, - .putc = lpc32xx_serial_putc, - .puts = default_serial_puts, .getc = lpc32xx_serial_getc, - .tstc = lpc32xx_serial_tstc, + .putc = lpc32xx_serial_putc, + .pending = lpc32xx_serial_pending, }; -void lpc32xx_serial_initialize(void) -{ - serial_register(&lpc32xx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &lpc32xx_serial_drv; -} +U_BOOT_DRIVER(lpc32xx_hsuart) = { + .name = "lpc32xx_hsuart", + .id = UCLASS_SERIAL, + .probe = lpc32xx_hsuart_probe, + .ops = &lpc32xx_hsuart_ops, + .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 3a5c1d0eaab..552c945264c 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -367,3 +367,31 @@ U_BOOT_DRIVER(serial_pl01x) = { }; #endif + +#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) + +#include <debug_uart.h> + +static void _debug_uart_init(void) +{ +#ifndef CONFIG_DEBUG_UART_SKIP_INIT + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? + TYPE_PL011 : TYPE_PL010; + + pl01x_generic_serial_init(regs, type); + pl01x_generic_setbrg(regs, type, + CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +#endif +} + +static inline void _debug_uart_putc(int ch) +{ + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + + pl01x_putc(regs, ch); +} + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f85af9c9fb9..59eaaea6939 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -752,8 +752,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * and byte program command for SST flash */ if (plat->ich_version == 7) { - slave->op_mode_rx = SPI_OPM_RX_AS; - slave->op_mode_tx = SPI_OPM_TX_BP; + slave->mode_rx = SPI_RX_SLOW; + slave->mode = SPI_TX_BYTE; } return 0; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index e7b0982fb65..7890796b36b 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <malloc.h> #include <spi.h> #include <asm/io.h> @@ -18,6 +19,83 @@ #endif #include <asm/arch-mvebu/spi.h> +static void _spi_cs_activate(struct kwspi_registers *reg) +{ + setbits_le32(®->ctrl, KWSPI_CSN_ACT); +} + +static void _spi_cs_deactivate(struct kwspi_registers *reg) +{ + clrbits_le32(®->ctrl, KWSPI_CSN_ACT); +} + +static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + unsigned int tmpdout, tmpdin; + int tm, isread = 0; + + debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen); + + if (flags & SPI_XFER_BEGIN) + _spi_cs_activate(reg); + + /* + * handle data in 8-bit chunks + * TBD: 2byte xfer mode to be enabled + */ + clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); + + while (bitlen > 4) { + debug("loopstart bitlen %d\n", bitlen); + tmpdout = 0; + + /* Shift data so it's msb-justified */ + if (dout) + tmpdout = *(u32 *)dout & 0xff; + + clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ); + writel(tmpdout, ®->dout); /* Write the data out */ + debug("*** spi_xfer: ... %08x written, bitlen %d\n", + tmpdout, bitlen); + + /* + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * The NE event must be read and cleared first + */ + for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { + if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) { + isread = 1; + tmpdin = readl(®->din); + debug("spi_xfer: din %p..%08x read\n", + din, tmpdin); + + if (din) { + *((u8 *)din) = (u8)tmpdin; + din += 1; + } + if (dout) + dout += 1; + bitlen -= 8; + } + if (isread) + break; + } + if (tm >= KWSPI_TIMEOUT) + printf("*** spi_xfer: Time out during SPI transfer\n"); + + debug("loopend bitlen %d\n", bitlen); + } + + if (flags & SPI_XFER_END) + _spi_cs_deactivate(reg); + + return 0; +} + +#ifndef CONFIG_DM_SPI + static struct kwspi_registers *spireg = (struct kwspi_registers *)MVEBU_SPI_BASE; @@ -147,76 +225,109 @@ void spi_init(void) void spi_cs_activate(struct spi_slave *slave) { - setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT); + _spi_cs_activate(spireg); } void spi_cs_deactivate(struct spi_slave *slave) { - clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT); + _spi_cs_deactivate(spireg); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - unsigned int tmpdout, tmpdin; - int tm, isread = 0; + return _spi_xfer(spireg, bitlen, dout, din, flags); +} - debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", - slave->bus, slave->cs, dout, din, bitlen); +#else - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); +/* Here now the DM part */ - /* - * handle data in 8-bit chunks - * TBD: 2byte xfer mode to be enabled - */ - clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); +struct mvebu_spi_platdata { + struct kwspi_registers *spireg; +}; - while (bitlen > 4) { - debug("loopstart bitlen %d\n", bitlen); - tmpdout = 0; +struct mvebu_spi_priv { + struct kwspi_registers *spireg; +}; - /* Shift data so it's msb-justified */ - if (dout) - tmpdout = *(u32 *)dout & 0xff; +static int mvebu_spi_set_speed(struct udevice *bus, uint hz) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + u32 data; - clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ); - writel(tmpdout, &spireg->dout); /* Write the data out */ - debug("*** spi_xfer: ... %08x written, bitlen %d\n", - tmpdout, bitlen); + /* calculate spi clock prescaller using max_hz */ + data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10; + data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; + data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; - /* - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * The NE event must be read and cleared first - */ - for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { - if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) { - isread = 1; - tmpdin = readl(&spireg->din); - debug("spi_xfer: din %p..%08x read\n", - din, tmpdin); + /* program spi clock prescaler using max_hz */ + writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg); + debug("data = 0x%08x\n", data); - if (din) { - *((u8 *)din) = (u8)tmpdin; - din += 1; - } - if (dout) - dout += 1; - bitlen -= 8; - } - if (isread) - break; - } - if (tm >= KWSPI_TIMEOUT) - printf("*** spi_xfer: Time out during SPI transfer\n"); + return 0; +} - debug("loopend bitlen %d\n", bitlen); - } +static int mvebu_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); +static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + + return _spi_xfer(plat->spireg, bitlen, dout, din, flags); +} + +static int mvebu_spi_probe(struct udevice *bus) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + + writel(KWSPI_SMEMRDY, ®->ctrl); + writel(KWSPI_SMEMRDIRQ, ®->irq_cause); + writel(KWSPI_IRQMASK, ®->irq_mask); + + return 0; +} + +static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + + plat->spireg = (struct kwspi_registers *)dev_get_addr(bus); return 0; } + +static const struct dm_spi_ops mvebu_spi_ops = { + .xfer = mvebu_spi_xfer, + .set_speed = mvebu_spi_set_speed, + .set_mode = mvebu_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id mvebu_spi_ids[] = { + { .compatible = "marvell,armada-380-spi" }, + { .compatible = "marvell,armada-xp-spi" }, + { } +}; + +U_BOOT_DRIVER(mvebu_spi) = { + .name = "mvebu_spi", + .id = UCLASS_SPI, + .of_match = mvebu_spi_ids, + .ops = &mvebu_spi_ops, + .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata), + .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv), + .probe = mvebu_spi_probe, +}; +#endif diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 5e0c6ad278f..242a83bdd82 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -135,7 +135,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) 50000000); plat->deactivate_delay_us = fdtdec_get_int(blob, node, "spi-deactivate-delay", 0); - debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + debug("%s: base=%lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", __func__, plat->base, plat->periph_id, plat->frequency, plat->deactivate_delay_us); diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index 1384385e05b..fe394e33608 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -3,19 +3,7 @@ * * Copyright (C) 2011-2012 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h index 96b4b685018..a0e949fa927 100644 --- a/drivers/spi/sh_spi.h +++ b/drivers/spi/sh_spi.h @@ -3,19 +3,7 @@ * * Copyright (C) 2011 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __SH_SPI_H__ diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index e0f6b25f30a..677c020b110 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -157,6 +157,7 @@ static int spi_child_pre_probe(struct udevice *dev) slave->max_hz = plat->max_hz; slave->mode = plat->mode; + slave->mode_rx = plat->mode_rx; return 0; } @@ -368,7 +369,8 @@ void spi_free_slave(struct spi_slave *slave) int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { - int mode = 0; + int mode = 0, mode_rx = 0; + int value; plat->cs = fdtdec_get_int(blob, node, "reg", -1); plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0); @@ -382,8 +384,42 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_3WIRE; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE; + + /* Device DUAL/QUAD mode */ + value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_TX_DUAL; + break; + case 4: + mode |= SPI_TX_QUAD; + break; + default: + error("spi-tx-bus-width %d not supported\n", value); + break; + } + plat->mode = mode; + value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode_rx |= SPI_RX_DUAL; + break; + case 4: + mode_rx |= SPI_RX_QUAD; + break; + default: + error("spi-rx-bus-width %d not supported\n", value); + break; + } + + plat->mode_rx = mode_rx; + return 0; } diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 98a062c63d4..509afba0a29 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -3,22 +3,7 @@ * * Copyright (c) 2010-2013 NVIDIA Corporation * - * See file CREDITS for list of people who contributed to this - * project. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index 43054f1a644..238edec23ba 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -3,22 +3,7 @@ * * Copyright (c) 2010-2013 NVIDIA Corporation * - * See file CREDITS for list of people who contributed to this - * project. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5747ed1fa97..b5c974ce383 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -11,11 +11,14 @@ #include <asm/arch/omap.h> #include <malloc.h> #include <spi.h> +#include <dm.h> #include <asm/gpio.h> #include <asm/omap_gpio.h> #include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> +DECLARE_GLOBAL_DATA_PTR; + /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 #define QSPI_FCLK 192000000 @@ -41,21 +44,23 @@ #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC #define MM_SWITCH 0x01 -#define MEM_CS 0x100 +#define MEM_CS(cs) ((cs + 1) << 8) #define MEM_CS_UNSELECT 0xfffff0ff #define MMAP_START_ADDR_DRA 0x5c000000 #define MMAP_START_ADDR_AM43x 0x30000000 #define CORE_CTRL_IO 0x4a002558 #define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_DUAL (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0) #define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8) #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) +#define QSPI_SETUP0_READ_DUAL (0x1 << 12) #define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16) #define QSPI_NUM_DUMMY_BITS (0x0 << 24) /* ti qspi register set */ @@ -85,50 +90,24 @@ struct ti_qspi_regs { u32 data3; }; -/* ti qspi slave */ -struct ti_qspi_slave { +/* ti qspi priv */ +struct ti_qspi_priv { +#ifndef CONFIG_DM_SPI struct spi_slave slave; +#else + void *memory_map; + uint max_hz; + u32 num_cs; +#endif struct ti_qspi_regs *base; + void *ctrl_mod_mmap; unsigned int mode; u32 cmd; u32 dc; }; -static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave) -{ - return container_of(slave, struct ti_qspi_slave, slave); -} - -static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) +static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) { - struct spi_slave *slave = &qslave->slave; - u32 memval = 0; - -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - slave->memory_map = (void *)MMAP_START_ADDR_DRA; -#else - slave->memory_map = (void *)MMAP_START_ADDR_AM43x; -#endif - -#ifdef CONFIG_QSPI_QUAD_SUPPORT - memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_8_BITS | - QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS); - slave->op_mode_rx = SPI_OPM_RX_QOF; -#else - memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_NO_BITS | - QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS; -#endif - - writel(memval, &qslave->base->setup0); -} - -static void ti_spi_set_speed(struct spi_slave *slave, uint hz) -{ - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); uint clk_div; debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); @@ -139,8 +118,8 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) clk_div = (QSPI_FCLK / hz) - 1; /* disable SCLK */ - writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN, - &qslave->base->clk_ctrl); + writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, + &priv->base->clk_ctrl); /* assign clk_div values */ if (clk_div < 0) @@ -149,135 +128,80 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) clk_div = QSPI_CLK_DIV_MAX; /* enable SCLK */ - writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return 1; + writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); } -void spi_cs_activate(struct spi_slave *slave) +static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) { - /* CS handled in xfer */ - return; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - - debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); - - writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); + writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); /* dummy readl to ensure bus sync */ - readl(&qslave->base->cmd); + readl(&priv->base->cmd); } -void spi_init(void) +static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) { - /* nothing to do */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ti_qspi_slave *qslave; - -#ifdef CONFIG_AM43XX - gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); - gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); -#endif - - qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); - if (!qslave) { - printf("SPI_error: Fail to allocate ti_qspi_slave\n"); - return NULL; - } - - qslave->base = (struct ti_qspi_regs *)QSPI_BASE; - qslave->mode = mode; - - ti_spi_set_speed(&qslave->slave, max_hz); + priv->dc = 0; + if (mode & SPI_CPHA) + priv->dc |= QSPI_CKPHA(0); + if (mode & SPI_CPOL) + priv->dc |= QSPI_CKPOL(0); + if (mode & SPI_CS_HIGH) + priv->dc |= QSPI_CSPOL(0); -#ifdef CONFIG_TI_SPI_MMAP - ti_spi_setup_spi_register(qslave); -#endif - - return &qslave->slave; + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - free(qslave); -} + writel(priv->dc, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); -int spi_claim_bus(struct spi_slave *slave) -{ - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - - debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); - - qslave->dc = 0; - if (qslave->mode & SPI_CPHA) - qslave->dc |= QSPI_CKPHA(slave->cs); - if (qslave->mode & SPI_CPOL) - qslave->dc |= QSPI_CKPOL(slave->cs); - if (qslave->mode & SPI_CS_HIGH) - qslave->dc |= QSPI_CSPOL(slave->cs); - - writel(qslave->dc, &qslave->base->dc); - writel(0, &qslave->base->cmd); - writel(0, &qslave->base->data); + priv->dc <<= cs * 8; + writel(priv->dc, &priv->base->dc); return 0; } -void spi_release_bus(struct spi_slave *slave) +static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + writel(0, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); +} - debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); +static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) +{ + u32 val; - writel(0, &qslave->base->dc); - writel(0, &qslave->base->cmd); - writel(0, &qslave->base->data); + val = readl(ctrl_mod_mmap); + if (enable) + val |= MEM_CS(cs); + else + val &= MEM_CS_UNSELECT; + writel(val, ctrl_mod_mmap); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, + const void *dout, void *din, unsigned long flags, + u32 cs) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); uint words = bitlen >> 3; /* fixed 8-bit word length */ const uchar *txp = dout; uchar *rxp = din; uint status; int timeout; -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - int val; -#endif - - debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", - slave->bus, slave->cs, bitlen, words, flags); - /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { - writel(MM_SWITCH, &qslave->base->memswitch); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - val = readl(CORE_CTRL_IO); - val |= MEM_CS; - writel(val, CORE_CTRL_IO); -#endif + writel(MM_SWITCH, &priv->base->memswitch); + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); return 0; } else if (flags & SPI_XFER_MMAP_END) { - writel(~MM_SWITCH, &qslave->base->memswitch); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - val = readl(CORE_CTRL_IO); - val &= MEM_CS_UNSELECT; - writel(val, CORE_CTRL_IO); -#endif + writel(~MM_SWITCH, &priv->base->memswitch); + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); return 0; } @@ -290,12 +214,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* Setup command reg */ - qslave->cmd = 0; - qslave->cmd |= QSPI_WLEN(8); - qslave->cmd |= QSPI_EN_CS(slave->cs); - if (qslave->mode & SPI_3WIRE) - qslave->cmd |= QSPI_3_PIN; - qslave->cmd |= 0xfff; + priv->cmd = 0; + priv->cmd |= QSPI_WLEN(8); + priv->cmd |= QSPI_EN_CS(cs); + if (priv->mode & SPI_3WIRE) + priv->cmd |= QSPI_3_PIN; + priv->cmd |= 0xfff; /* FIXME: This delay is required for successfull * completion of read/write/erase. Once its root @@ -307,39 +231,39 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, while (words--) { if (txp) { debug("tx cmd %08x dc %08x data %02x\n", - qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); - writel(*txp++, &qslave->base->data); - writel(qslave->cmd | QSPI_WR_SNGL, - &qslave->base->cmd); - status = readl(&qslave->base->status); + priv->cmd | QSPI_WR_SNGL, priv->dc, *txp); + writel(*txp++, &priv->base->data); + writel(priv->cmd | QSPI_WR_SNGL, + &priv->base->cmd); + status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { if (--timeout < 0) { printf("spi_xfer: TX timeout!\n"); return -1; } - status = readl(&qslave->base->status); + status = readl(&priv->base->status); } debug("tx done, status %08x\n", status); } if (rxp) { - qslave->cmd |= QSPI_RD_SNGL; + priv->cmd |= QSPI_RD_SNGL; debug("rx cmd %08x dc %08x\n", - qslave->cmd, qslave->dc); + priv->cmd, priv->dc); #ifdef CONFIG_DRA7XX udelay(500); #endif - writel(qslave->cmd, &qslave->base->cmd); - status = readl(&qslave->base->status); + writel(priv->cmd, &priv->base->cmd); + status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { if (--timeout < 0) { printf("spi_xfer: RX timeout!\n"); return -1; } - status = readl(&qslave->base->status); + status = readl(&priv->base->status); } - *rxp++ = readl(&qslave->base->data); + *rxp++ = readl(&priv->base->data); debug("rx done, status %08x, read %02x\n", status, *(rxp-1)); } @@ -347,7 +271,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Terminate frame */ if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + ti_qspi_cs_deactivate(priv); return 0; } @@ -374,3 +298,293 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len) *((unsigned int *)offset) += len; } #endif + +#ifndef CONFIG_DM_SPI + +static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) +{ + return container_of(slave, struct ti_qspi_priv, slave); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + ti_qspi_cs_deactivate(priv); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) +{ + u32 memval = 0; + +#ifdef CONFIG_QSPI_QUAD_SUPPORT + struct spi_slave *slave = &priv->slave; + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); + slave->mode_rx = SPI_RX_QUAD; +#else + memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_NO_BITS | + QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS; +#endif + + writel(memval, &priv->base->setup0); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ti_qspi_priv *priv; + +#ifdef CONFIG_AM43XX + gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); + gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); +#endif + + priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); + if (!priv) { + printf("SPI_error: Fail to allocate ti_qspi_priv\n"); + return NULL; + } + + priv->base = (struct ti_qspi_regs *)QSPI_BASE; + priv->mode = mode; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; + priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; +#else + priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; +#endif + + ti_spi_set_speed(priv, max_hz); + +#ifdef CONFIG_TI_SPI_MMAP + ti_spi_setup_spi_register(priv); +#endif + + return &priv->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + free(priv); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); + __ti_qspi_set_mode(priv, priv->mode); + return __ti_qspi_claim_bus(priv, priv->slave.cs); +} +void spi_release_bus(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); + __ti_qspi_release_bus(priv); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n", + priv->slave.bus, priv->slave.cs, bitlen, flags); + return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); +} + +#else /* CONFIG_DM_SPI */ + +static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, + struct spi_slave *slave, + bool enable) +{ + u32 memval; + u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL); + + if (!enable) { + writel(0, &priv->base->setup0); + return; + } + + memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; + + switch (mode) { + case SPI_RX_QUAD: + memval |= QSPI_CMD_READ_QUAD; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_QUAD; + slave->mode_rx = SPI_RX_QUAD; + break; + case SPI_RX_DUAL: + memval |= QSPI_CMD_READ_DUAL; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_DUAL; + break; + default: + memval |= QSPI_CMD_READ; + memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; + memval |= QSPI_SETUP0_READ_NORMAL; + break; + } + + writel(memval, &priv->base->setup0); +} + + +static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + + ti_spi_set_speed(priv, max_hz); + + return 0; +} + +static int ti_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + return __ti_qspi_set_mode(priv, mode); +} + +static int ti_qspi_claim_bus(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave_plat->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + __ti_qspi_setup_memorymap(priv, slave, true); + + return __ti_qspi_claim_bus(priv, slave_plat->cs); +} + +static int ti_qspi_release_bus(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + __ti_qspi_setup_memorymap(priv, slave, false); + __ti_qspi_release_bus(priv); + + return 0; +} + +static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); +} + +static int ti_qspi_probe(struct udevice *bus) +{ + /* Nothing to do in probe */ + return 0; +} + +static int ti_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + fdt_addr_t addr; + + priv->base = (struct ti_qspi_regs *)dev_get_addr(bus); + priv->memory_map = (void *)dev_get_addr_index(bus, 1); + addr = dev_get_addr_index(bus, 2); + priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr; + + priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); + if (priv->max_hz < 0) { + debug("Error: Max frequency missing\n"); + return -ENODEV; + } + priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + + debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__, + (int)priv->base, priv->max_hz); + + return 0; +} + +static int ti_qspi_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct udevice *bus = dev_get_parent(dev); + struct ti_qspi_priv *priv = dev_get_priv(bus); + + slave->memory_map = priv->memory_map; + return 0; +} + +static const struct dm_spi_ops ti_qspi_ops = { + .claim_bus = ti_qspi_claim_bus, + .release_bus = ti_qspi_release_bus, + .xfer = ti_qspi_xfer, + .set_speed = ti_qspi_set_speed, + .set_mode = ti_qspi_set_mode, +}; + +static const struct udevice_id ti_qspi_ids[] = { + { .compatible = "ti,dra7xxx-qspi" }, + { .compatible = "ti,am4372-qspi" }, + { } +}; + +U_BOOT_DRIVER(ti_qspi) = { + .name = "ti_qspi", + .id = UCLASS_SPI, + .of_match = ti_qspi_ids, + .ops = &ti_qspi_ops, + .ofdata_to_platdata = ti_qspi_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct ti_qspi_priv), + .probe = ti_qspi_probe, + .child_pre_probe = ti_qspi_child_pre_probe, +}; +#endif /* CONFIG_DM_SPI */ diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h index 3d8752e1063..240bc14a0b6 100644 --- a/drivers/usb/gadget/at91_udc.h +++ b/drivers/usb/gadget/at91_udc.h @@ -3,10 +3,7 @@ * Copyright (C) 2005 by Ivan Kokshaysky * Copyright (C) 2006 by SAN People * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef AT91_UDC_H diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 1ba5054965f..d36bcf64675 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -1018,18 +1018,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) return ret; ret = ci_udc_probe(); -#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) - /* - * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all - * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection - */ - if (!ret) { - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + if (ret) { + DBG("udc probe failed, returned %d\n", ret); + return ret; } -#endif ret = driver->bind(&controller.gadget); if (ret) { diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 20b6c18b9cf..87e54ebec76 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -477,7 +477,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) req->complete = rx_handler_command; req->length = EP_BUFFER_SIZE; - sprintf(response, "OKAY"); + strcpy(response, "OKAY"); fastboot_tx_write_str(response); printf("\ndownloading of %d bytes finished\n", download_bytes); @@ -506,10 +506,10 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) printf("Starting download of %d bytes\n", download_size); if (0 == download_size) { - sprintf(response, "FAILdata invalid size"); + strcpy(response, "FAILdata invalid size"); } else if (download_size > CONFIG_FASTBOOT_BUF_SIZE) { download_size = 0; - sprintf(response, "FAILdata too large"); + strcpy(response, "FAILdata too large"); } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index ec1f23a0cf3..1ecb92ac6b8 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -444,8 +444,9 @@ static void set_bulk_out_req_length(struct fsg_common *common, /*-------------------------------------------------------------------------*/ -struct ums *ums; -struct fsg_common *the_fsg_common; +static struct ums *ums; +static int ums_count; +static struct fsg_common *the_fsg_common; static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) { @@ -772,7 +773,7 @@ static int do_read(struct fsg_common *common) } /* Perform the read */ - rc = ums->read_sector(ums, + rc = ums[common->lun].read_sector(&ums[common->lun], file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); @@ -946,7 +947,7 @@ static int do_write(struct fsg_common *common) amount = bh->outreq->actual; /* Perform the write */ - rc = ums->write_sector(ums, + rc = ums[common->lun].write_sector(&ums[common->lun], file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); @@ -1062,7 +1063,7 @@ static int do_verify(struct fsg_common *common) } /* Perform the read */ - rc = ums->read_sector(ums, + rc = ums[common->lun].read_sector(&ums[common->lun], file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); @@ -1117,7 +1118,7 @@ static int do_inquiry(struct fsg_common *common, struct fsg_buffhd *bh) buf[4] = 31; /* Additional length */ /* No special options */ sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id , - ums->name, (u16) 0xffff); + ums[common->lun].name, (u16) 0xffff); return 36; } @@ -2456,7 +2457,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, int nluns, i, rc; /* Find out how many LUNs there should be */ - nluns = 1; + nluns = ums_count; if (nluns < 1 || nluns > FSG_MAX_LUNS) { printf("invalid number of LUNs: %u\n", nluns); return ERR_PTR(-EINVAL); @@ -2501,7 +2502,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, for (i = 0; i < nluns; i++) { common->luns[i].removable = 1; - rc = fsg_lun_open(&common->luns[i], ""); + rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, ""); if (rc) goto error_luns; } @@ -2775,9 +2776,10 @@ int fsg_add(struct usb_configuration *c) return fsg_bind_config(c->cdev, c, fsg_common); } -int fsg_init(struct ums *ums_dev) +int fsg_init(struct ums *ums_devs, int count) { - ums = ums_dev; + ums = ums_devs; + ums_count = count; return 0; } diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index 62c9b2ead74..48463db0b2f 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -4,10 +4,6 @@ * Authors: Benedikt Spranger, Pengutronix * Robert Schwebel, Pengutronix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * * This software was originally developed in conformance with * Microsoft's Remote NDIS Specification License Agreement. * @@ -19,6 +15,8 @@ * * Copyright (C) 2004 by David Brownell * updates to merge with Linux 2.6, better match RNDIS spec + * + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/usb/gadget/rndis.h b/drivers/usb/gadget/rndis.h index d9e3a752872..7a389a580ab 100644 --- a/drivers/usb/gadget/rndis.h +++ b/drivers/usb/gadget/rndis.h @@ -4,12 +4,10 @@ * Authors: Benedikt Spranger, Pengutronix * Robert Schwebel, Pengutronix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * * This software was originally developed in conformance with * Microsoft's Remote NDIS Specification License Agreement. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _USBGADGET_RNDIS_H diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index b55e40bbda9..b6df130a140 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -564,7 +564,8 @@ static struct usb_gadget_strings fsg_stringtab = { * the caller must own fsg->filesem for writing. */ -static int fsg_lun_open(struct fsg_lun *curlun, const char *filename) +static int fsg_lun_open(struct fsg_lun *curlun, unsigned int num_sectors, + const char *filename) { int ro; @@ -572,8 +573,8 @@ static int fsg_lun_open(struct fsg_lun *curlun, const char *filename) ro = curlun->initially_ro; curlun->ro = ro; - curlun->file_length = ums->num_sectors << 9; - curlun->num_sectors = ums->num_sectors; + curlun->file_length = num_sectors << 9; + curlun->num_sectors = num_sectors; debug("open backing file: %s\n", filename); return 0; diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 98e0fc6ca66..335e303c2aa 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -121,6 +121,11 @@ static void usb_oc_config(int index) setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); } +int __weak board_usb_phy_mode(int port) +{ + return 0; +} + int __weak board_ehci_hcd_init(int port) { return 0; @@ -130,15 +135,11 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci; + enum usb_init_type type; if (index >= ARRAY_SIZE(nc_reg_bases)) return -EINVAL; - if (init == USB_INIT_DEVICE && index == 1) - return -ENODEV; - if (init == USB_INIT_HOST && index == 0) - return -ENODEV; - ehci = (struct usb_ehci *)nc_reg_bases[index]; /* Do board specific initialisation */ @@ -153,6 +154,10 @@ int ehci_hcd_init(int index, enum usb_init_type init, *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + type = board_usb_phy_mode(index); + if (type != init) + return -ENODEV; + if (init == USB_INIT_DEVICE) { setbits_le32(&ehci->usbmode, CM_DEVICE); writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c index d158454a086..b8791ddd5c1 100644 --- a/drivers/usb/musb-new/am35x.c +++ b/drivers/usb/musb-new/am35x.c @@ -8,21 +8,7 @@ * * This file is part of the Inventra Controller Driver for Linux. * - * The Inventra Controller Driver for Linux is free software; you - * can redistribute it and/or modify it under the terms of the GNU - * General Public License version 2 as published by the Free Software - * Foundation. - * - * The Inventra Controller Driver for Linux is distributed in - * the hope that it will be useful, but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with The Inventra Controller Driver for Linux ; if not, - * write to the Free Software Foundation, Inc., 59 Temple Place, - * Suite 330, Boston, MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * */ diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index d1b6d15c8e6..a6d6af60e7c 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h index c8180404811..2fe4ed51b37 100644 --- a/drivers/usb/musb-new/musb_core.h +++ b/drivers/usb/musb-new/musb_core.h @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_CORE_H__ diff --git a/drivers/usb/musb-new/musb_debug.h b/drivers/usb/musb-new/musb_debug.h index 27ba8f79946..3befaa28f4f 100644 --- a/drivers/usb/musb-new/musb_debug.h +++ b/drivers/usb/musb-new/musb_debug.h @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_LINUX_DEBUG_H__ diff --git a/drivers/usb/musb-new/musb_dma.h b/drivers/usb/musb-new/musb_dma.h index 17fe89fdcbf..30e39f5ed2b 100644 --- a/drivers/usb/musb-new/musb_dma.h +++ b/drivers/usb/musb-new/musb_dma.h @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_DMA_H__ diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index 895939773a7..bb7c9522927 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -7,21 +7,7 @@ * * This file is part of the Inventra Controller Driver for Linux. * - * The Inventra Controller Driver for Linux is free software; you - * can redistribute it and/or modify it under the terms of the GNU - * General Public License version 2 as published by the Free Software - * Foundation. - * - * The Inventra Controller Driver for Linux is distributed in - * the hope that it will be useful, but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with The Inventra Controller Driver for Linux ; if not, - * write to the Free Software Foundation, Inc., 59 Temple Place, - * Suite 330, Boston, MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * musb_dsps.c will be a common file for all the TI DSPS platforms * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x. diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index 309dc7f93f6..c704e6f2663 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -6,31 +6,7 @@ * Copyright (C) 2006-2007 Nokia Corporation * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __UBOOT__ diff --git a/drivers/usb/musb-new/musb_gadget.h b/drivers/usb/musb-new/musb_gadget.h index 392f701a878..ddd567bbb5c 100644 --- a/drivers/usb/musb-new/musb_gadget.h +++ b/drivers/usb/musb-new/musb_gadget.h @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_GADGET_H diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 415a9f21a9c..3cfcb2205ab 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -6,31 +6,7 @@ * Copyright (C) 2006-2007 Nokia Corporation * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __UBOOT__ diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index 25154473086..ce5b6a75074 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -6,31 +6,7 @@ * Copyright (C) 2006-2007 Nokia Corporation * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __UBOOT__ diff --git a/drivers/usb/musb-new/musb_host.h b/drivers/usb/musb-new/musb_host.h index 546b4a2715f..c1cee8b18ac 100644 --- a/drivers/usb/musb-new/musb_host.h +++ b/drivers/usb/musb-new/musb_host.h @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _MUSB_HOST_H diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h index 51730aee521..ea8efb32a70 100644 --- a/drivers/usb/musb-new/musb_io.h +++ b/drivers/usb/musb-new/musb_io.h @@ -9,27 +9,7 @@ * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_LINUX_PLATFORM_ARCH_H__ diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 90288c46949..4dc9abbe02c 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -5,31 +5,7 @@ * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_REGS_H__ diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 77273a49a31..9f307e991b2 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -7,22 +7,7 @@ * * This file is part of the Inventra Controller Driver for Linux. * - * The Inventra Controller Driver for Linux is free software; you - * can redistribute it and/or modify it under the terms of the GNU - * General Public License version 2 as published by the Free Software - * Foundation. - * - * The Inventra Controller Driver for Linux is distributed in - * the hope that it will be useful, but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with The Inventra Controller Driver for Linux ; if not, - * write to the Free Software Foundation, Inc., 59 Temple Place, - * Suite 330, Boston, MA 02111-1307 USA - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __UBOOT__ #include <linux/module.h> diff --git a/drivers/usb/musb-new/omap2430.h b/drivers/usb/musb-new/omap2430.h index 3b795c248d1..56998c794f2 100644 --- a/drivers/usb/musb-new/omap2430.h +++ b/drivers/usb/musb-new/omap2430.h @@ -1,10 +1,7 @@ /* * Copyright (C) 2005-2006 by Texas Instruments * - * The Inventra Controller Driver for Linux is free software; you - * can redistribute it and/or modify it under the terms of the GNU - * General Public License version 2 as published by the Free Software - * Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MUSB_OMAP243X_H__ diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 5eb8d19b740..be1d2ec8e41 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -14,11 +14,7 @@ * * This file is part of the Inventra Controller Driver for Linux. * - * The Inventra Controller Driver for Linux is free software; you - * can redistribute it and/or modify it under the terms of the GNU - * General Public License version 2 as published by the Free Software - * Foundation. - * + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> #include <asm/arch/cpu.h> diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index ec8a038c74c..dc863bdd280 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -4,31 +4,7 @@ * * This file is part of the Inventra Controller Driver for Linux. * - * The Inventra Controller Driver for Linux is free software; you - * can redistribute it and/or modify it under the terms of the GNU - * General Public License version 2 as published by the Free Software - * Foundation. - * - * The Inventra Controller Driver for Linux is distributed in - * the hope that it will be useful, but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with The Inventra Controller Driver for Linux ; if not, - * write to the Free Software Foundation, Inc., 59 Temple Place, - * Suite 330, Boston, MA 02111-1307 USA - * - * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION - * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE - * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS - * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. - * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES - * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT - * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR - * GRAPHICS SUPPORT CUSTOMER. + * SPDX-License-Identifier: GPL-2.0 ******************************************************************/ #ifndef __MUSB_HDRC_DEFS_H__ diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c index 4db7fa43ce1..63151aa8e92 100644 --- a/drivers/usb/ulpi/omap-ulpi-viewport.c +++ b/drivers/usb/ulpi/omap-ulpi-viewport.c @@ -5,17 +5,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com * Author: Govindraj R <govindraj.raja@ti.com> * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c index b4974ed2a6c..72a06de9106 100644 --- a/drivers/usb/ulpi/ulpi-viewport.c +++ b/drivers/usb/ulpi/ulpi-viewport.c @@ -11,15 +11,7 @@ * Original Copyright follow: * Copyright (C) 2011 Google, Inc. * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index e2b2144d880..468f385d8d4 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -379,7 +379,7 @@ static void lcd_cfg_ac_bias(int period, int transitions_per_int) { u32 reg; - /* Set the AC Bias Period and Number of Transisitons per Interrupt */ + /* Set the AC Bias Period and Number of Transitions per Interrupt */ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; reg |= LCD_AC_BIAS_FREQUENCY(period) | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); @@ -487,7 +487,7 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, /* Pixels per line = (PPL + 1)*16 */ if (lcd_revision == LCD_VERSION_1) { /* - * 0x3F in bits 4..9 gives max horisontal resolution = 1024 + * 0x3F in bits 4..9 gives max horizontal resolution = 1024 * pixels */ width &= 0x3f0; @@ -695,7 +695,7 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); - /* Configure for disply */ + /* Configure for display */ ret = lcd_cfg_display(cfg); if (ret < 0) return ret; @@ -761,7 +761,7 @@ static u32 lcdc_irq_handler_rev01(void) lcdc_write(stat, &da8xx_fb_reg_base->stat); - /* Disable PL completion inerrupt */ + /* Disable PL completion interrupt */ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); reg_ras &= ~LCD_V1_PL_INT_ENA; lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); @@ -810,7 +810,7 @@ static u32 lcdc_irq_handler_rev02(void) lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); - /* Disable PL completion inerrupt */ + /* Disable PL completion interrupt */ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | (LCD_V2_PL_INT_ENA); lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos_dp.c index 5b6fc140e0e..0d5d090d0ee 100644 --- a/drivers/video/exynos_dp.c +++ b/drivers/video/exynos_dp.c @@ -207,7 +207,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info) return -EINVAL; } - /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */ + /* Refer VESA Display Port Standard Ver1.1a Page 120 */ if (edp_info->dpcd_rev == DP_DPCD_REV_11) { temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; if (buf[DPCD_MAX_LANE_COUNT] & 0x80) @@ -270,7 +270,7 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info) return ret; } - /* Set link rate and count as you want to establish*/ + /* Set link rate and count as you want to establish */ exynos_dp_set_link_bandwidth(edp_info->lane_bw); exynos_dp_set_lane_count(edp_info->lane_cnt); @@ -322,7 +322,7 @@ static unsigned int exynos_dp_training_pattern_dis(void) ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, DPCD_TRAINING_PATTERN_DISABLED); if (ret != EXYNOS_DP_SUCCESS) { - printf("DP requst_link_traninig_req failed\n"); + printf("DP request_link_training_req failed\n"); return -EAGAIN; } @@ -412,7 +412,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num, unsigned int dpcd_addr; unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; - /*lane_num value is used as arry index, so this range 0 ~ 3 */ + /* lane_num value is used as array index, so this range 0 ~ 3 */ dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf); @@ -433,7 +433,7 @@ static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info) ret = exynos_dp_training_pattern_dis(); if (ret != EXYNOS_DP_SUCCESS) { - printf("DP training_patter_disable() failed\n"); + printf("DP training_pattern_disable() failed\n"); edp_info->lt_info.lt_status = DP_LT_FAIL; } @@ -523,7 +523,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info ret = exynos_dp_write_bytes_to_dpcd( DPCD_TRAINING_PATTERN_SET, 5, buf); if (ret != EXYNOS_DP_SUCCESS) { - printf("DP write traning pattern1 failed\n"); + printf("DP write training pattern1 failed\n"); edp_info->lt_info.lt_status = DP_LT_FAIL; return ret; } else @@ -567,7 +567,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info ret = exynos_dp_write_bytes_to_dpcd( DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); if (ret != EXYNOS_DP_SUCCESS) { - printf("DP write traning pattern2 failed\n"); + printf("DP write training pattern2 failed\n"); edp_info->lt_info.lt_status = DP_LT_FAIL; return ret; } @@ -738,7 +738,7 @@ static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info) ret = exynos_dp_sw_link_training(edp_info); if (ret != EXYNOS_DP_SUCCESS) - printf("DP dp_sw_link_traning() failed\n"); + printf("DP dp_sw_link_training() failed\n"); return ret; } diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos_dp_lowlevel.c index e9b461a99a9..acb5bc8eb7b 100644 --- a/drivers/video/exynos_dp_lowlevel.c +++ b/drivers/video/exynos_dp_lowlevel.c @@ -44,7 +44,7 @@ static void exynos_dp_enable_video_input(unsigned int enable) reg = readl(&dp_regs->video_ctl1); reg &= ~VIDEO_EN_MASK; - /* enable video input*/ + /* enable video input */ if (enable) reg |= VIDEO_EN_MASK; @@ -55,13 +55,13 @@ static void exynos_dp_enable_video_input(unsigned int enable) void exynos_dp_enable_video_bist(unsigned int enable) { - /*enable video bist*/ + /* enable video bist */ unsigned int reg; reg = readl(&dp_regs->video_ctl4); reg &= ~VIDEO_BIST_MASK; - /*enable video bist*/ + /* enable video bist */ if (enable) reg |= VIDEO_BIST_MASK; @@ -112,7 +112,7 @@ static void exynos_dp_init_analog_param(void) /* * Set AUX TX terminal resistor to 102 ohm * Set AUX channel amplitude control - */ + */ reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA; writel(reg, &dp_regs->pll_filter_ctl1); @@ -146,7 +146,7 @@ static void exynos_dp_init_interrupt(void) */ writel(INT_POL, &dp_regs->int_ctl); - /* Clear pending regisers */ + /* Clear pending registers */ writel(0xff, &dp_regs->common_int_sta1); writel(0xff, &dp_regs->common_int_sta2); writel(0xff, &dp_regs->common_int_sta3); @@ -165,7 +165,7 @@ void exynos_dp_reset(void) { unsigned int reg_func_1; - /*dp tx sw reset*/ + /* dp tx sw reset */ writel(RESET_DP_TX, &dp_regs->tx_sw_reset); exynos_dp_enable_video_input(DP_DISABLE); @@ -287,7 +287,7 @@ int exynos_dp_init_analog_func(void) unsigned int retry_cnt = 10; unsigned int reg; - /*Power On All Analog block */ + /* Power On All Analog block */ exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); reg = PLL_LOCK_CHG; @@ -297,14 +297,14 @@ int exynos_dp_init_analog_func(void) reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); writel(reg, &dp_regs->debug_ctl); - /*Assert DP PLL Reset*/ + /* Assert DP PLL Reset */ reg = readl(&dp_regs->pll_ctl); reg |= DP_PLL_RESET; writel(reg, &dp_regs->pll_ctl); mdelay(1); - /*Deassert DP PLL Reset*/ + /* Deassert DP PLL Reset */ reg = readl(&dp_regs->pll_ctl); reg &= ~(DP_PLL_RESET); writel(reg, &dp_regs->pll_ctl); @@ -336,7 +336,7 @@ void exynos_dp_init_hpd(void) { unsigned int reg; - /* Clear interrupts releated to Hot Plug Dectect */ + /* Clear interrupts related to Hot Plug Detect */ reg = HOTPLUG_CHG | HPD_LOST | PLUG; writel(reg, &dp_regs->common_int_sta4); @@ -366,7 +366,7 @@ void exynos_dp_init_aux(void) { unsigned int reg; - /* Clear inerrupts related to AUX channel */ + /* Clear interrupts related to AUX channel */ reg = RPLY_RECEIV | AUX_ERR; writel(reg, &dp_regs->int_sta); @@ -377,7 +377,7 @@ void exynos_dp_init_aux(void) AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; writel(reg, &dp_regs->aux_hw_retry_ctl); - /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */ reg = DEFER_CTRL_EN | DEFER_COUNT(1); writel(reg, &dp_regs->aux_ch_defer_ctl); @@ -1040,7 +1040,7 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT); writel(reg, &dp_regs->video_ctl10); - /*Set video mode to slave mode */ + /* Set video mode to slave mode */ reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; writel(reg, &dp_regs->soc_general_ctl); } diff --git a/dts/Makefile b/dts/Makefile index d3122aa3b96..c4ac153ef36 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb clean-files := dt.dtb.S # Let clean descend into dts directories -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c index 20f52566f09..9fd10de0776 100644 --- a/fs/ext4/dev.c +++ b/fs/ext4/dev.c @@ -76,10 +76,10 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) if (byte_offset != 0) { int readlen; /* read first part which isn't aligned with start of sector */ - if (ext4fs_block_dev_desc-> - block_read(ext4fs_block_dev_desc->dev, - part_info->start + sector, 1, - (unsigned long *) sec_buf) != 1) { + if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc, + part_info->start + sector, + 1, (void *)sec_buf) + != 1) { printf(" ** ext2fs_devread() read error **\n"); return 0; } @@ -101,18 +101,18 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_block_dev_desc->blksz); block_len = ext4fs_block_dev_desc->blksz; - ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev, + ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc, part_info->start + sector, - 1, (unsigned long *)p); + 1, (void *)p); memcpy(buf, p, byte_len); return 1; } - if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev, - part_info->start + sector, - block_len >> log2blksz, - (unsigned long *) buf) != - block_len >> log2blksz) { + if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc, + part_info->start + sector, + block_len >> log2blksz, + (void *)buf) != + block_len >> log2blksz) { printf(" ** %s read error - block\n", __func__); return 0; } @@ -123,10 +123,10 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) if (byte_len != 0) { /* read rest of data which are not in whole sector */ - if (ext4fs_block_dev_desc-> - block_read(ext4fs_block_dev_desc->dev, - part_info->start + sector, 1, - (unsigned long *) sec_buf) != 1) { + if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc, + part_info->start + sector, + 1, (void *)sec_buf) + != 1) { printf("* %s read error - last part\n", __func__); return 0; } diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index e73223ac22c..294a46eadfd 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -82,26 +82,26 @@ void put_ext4(uint64_t off, void *buf, uint32_t size) if (remainder) { if (fs->dev_desc->block_read) { - fs->dev_desc->block_read(fs->dev_desc->dev, + fs->dev_desc->block_read(fs->dev_desc, startblock, 1, sec_buf); temp_ptr = sec_buf; memcpy((temp_ptr + remainder), (unsigned char *)buf, size); - fs->dev_desc->block_write(fs->dev_desc->dev, + fs->dev_desc->block_write(fs->dev_desc, startblock, 1, sec_buf); } } else { if (size >> log2blksz != 0) { - fs->dev_desc->block_write(fs->dev_desc->dev, + fs->dev_desc->block_write(fs->dev_desc, startblock, size >> log2blksz, (unsigned long *)buf); } else { - fs->dev_desc->block_read(fs->dev_desc->dev, + fs->dev_desc->block_read(fs->dev_desc, startblock, 1, sec_buf); temp_ptr = sec_buf; memcpy(temp_ptr, buf, size); - fs->dev_desc->block_write(fs->dev_desc->dev, + fs->dev_desc->block_write(fs->dev_desc, startblock, 1, (unsigned long *)sec_buf); } @@ -1287,11 +1287,11 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, ti_gp_blockno = ext4fs_get_new_blk_no(); if (ti_gp_blockno == -1) { printf("no block left to assign\n"); - goto fail; + return; } ti_gp_buff = zalloc(fs->blksz); if (!ti_gp_buff) - goto fail; + return; ti_gp_buff_start_addr = ti_gp_buff; (*no_blks_reqd)++; @@ -1321,11 +1321,11 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, ti_child_blockno = ext4fs_get_new_blk_no(); if (ti_child_blockno == -1) { printf("no block left assign\n"); - goto fail; + goto fail1; } ti_child_buff = zalloc(fs->blksz); if (!ti_child_buff) - goto fail; + goto fail1; ti_cbuff_start_addr = ti_child_buff; *ti_parent_buff = ti_child_blockno; @@ -1341,7 +1341,8 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, ext4fs_get_new_blk_no(); if (actual_block_no == -1) { printf("no block left\n"); - goto fail; + free(ti_cbuff_start_addr); + goto fail1; } *ti_child_buff = actual_block_no; debug("TIAB %ld: %u\n", actual_block_no, @@ -1373,7 +1374,11 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)), ti_gp_buff_start_addr, fs->blksz); file_inode->b.blocks.triple_indir_block = ti_gp_blockno; + free(ti_gp_buff_start_addr); + return; } +fail1: + free(ti_pbuff_start_addr); fail: free(ti_gp_buff_start_addr); } diff --git a/fs/fat/fat.c b/fs/fat/fat.c index f939bc5deed..472a63e8bb0 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -51,8 +51,8 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf) if (!cur_dev || !cur_dev->block_read) return -1; - ret = cur_dev->block_read(cur_dev->dev, - cur_part_info.start + block, nr_blocks, buf); + ret = cur_dev->block_read(cur_dev, cur_part_info.start + block, + nr_blocks, buf); if (nr_blocks && ret == 0) return -1; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index af828d07bd0..5ed324ce1a0 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -41,8 +41,7 @@ static int disk_write(__u32 block, __u32 nr_blocks, void *buf) return -1; } - ret = cur_dev->block_write(cur_dev->dev, - cur_part_info.start + block, + ret = cur_dev->block_write(cur_dev, cur_part_info.start + block, nr_blocks, buf); if (nr_blocks && ret == 0) return -1; @@ -1,17 +1,7 @@ /* * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <config.h> diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c index 68255458d51..7b24d6aa715 100644 --- a/fs/reiserfs/dev.c +++ b/fs/reiserfs/dev.c @@ -59,9 +59,11 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) if (byte_offset != 0) { /* read first part which isn't aligned with start of sector */ - if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, - part_info->start + sector, 1, - (unsigned long *)sec_buf) != 1) { + if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc, + part_info->start + + sector, + 1, (void *)sec_buf) + != 1) { printf (" ** reiserfs_devread() read error\n"); return 0; } @@ -73,9 +75,11 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) /* read sector aligned part */ block_len = byte_len & ~(SECTOR_SIZE-1); - if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, - part_info->start + sector, block_len/SECTOR_SIZE, - (unsigned long *)buf) != block_len/SECTOR_SIZE) { + if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc, + part_info->start + sector, + block_len / SECTOR_SIZE, + (void *)buf) + != block_len/SECTOR_SIZE) { printf (" ** reiserfs_devread() read error - block\n"); return 0; } @@ -85,9 +89,11 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) if ( byte_len != 0 ) { /* read rest of data which are not in whole sector */ - if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, - part_info->start + sector, 1, - (unsigned long *)sec_buf) != 1) { + if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc, + part_info->start + + sector, + 1, (void *)sec_buf) + != 1) { printf (" ** reiserfs_devread() read error - last part\n"); return 0; } diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 50355e988e9..a992a00c8f2 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -6,21 +6,10 @@ * (C) Copyright 2008-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter + * + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/fs/zfs/dev.c b/fs/zfs/dev.c index 3a1fa5685af..67d12652b01 100644 --- a/fs/zfs/dev.c +++ b/fs/zfs/dev.c @@ -55,9 +55,10 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) if (byte_offset != 0) { /* read first part which isn't aligned with start of sector */ - if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev, - part_info->start + sector, 1, - (unsigned long *)sec_buf) != 1) { + if (zfs_block_dev_desc->block_read(zfs_block_dev_desc, + part_info->start + sector, 1, + (void *)sec_buf) + != 1) { printf(" ** zfs_devread() read error **\n"); return 1; } @@ -78,16 +79,18 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) u8 p[SECTOR_SIZE]; block_len = SECTOR_SIZE; - zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev, - part_info->start + sector, - 1, (unsigned long *)p); + zfs_block_dev_desc->block_read(zfs_block_dev_desc, + part_info->start + sector, + 1, (void *)p); memcpy(buf, p, byte_len); return 0; } - if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev, - part_info->start + sector, block_len / SECTOR_SIZE, - (unsigned long *) buf) != block_len / SECTOR_SIZE) { + if (zfs_block_dev_desc->block_read(zfs_block_dev_desc, + part_info->start + sector, + block_len / SECTOR_SIZE, + (void *)buf) + != block_len / SECTOR_SIZE) { printf(" ** zfs_devread() read error - block\n"); return 1; } @@ -99,10 +102,9 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) if (byte_len != 0) { /* read rest of data which are not in whole sector */ - if (zfs_block_dev_desc-> - block_read(zfs_block_dev_desc->dev, - part_info->start + sector, 1, - (unsigned long *) sec_buf) != 1) { + if (zfs_block_dev_desc->block_read(zfs_block_dev_desc, + part_info->start + sector, + 1, (void *)sec_buf) != 1) { printf(" ** zfs_devread() read error - last part\n"); return 1; } diff --git a/include/addr_map.h b/include/addr_map.h index dda4d6e710d..63b24cded01 100644 --- a/include/addr_map.h +++ b/include/addr_map.h @@ -4,19 +4,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <asm/types.h> diff --git a/include/cavium/atf.h b/include/cavium/atf.h new file mode 100644 index 00000000000..0a53c2f1de5 --- /dev/null +++ b/include/cavium/atf.h @@ -0,0 +1,22 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ +#ifndef __ATF_H__ +#define __ATF_H__ +#include <cavium/atf_part.h> + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_get_pcount(void); +ssize_t atf_get_part(struct storage_partition *part, unsigned int index); +ssize_t atf_erase_nor(uintptr_t offset, size_t size); +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_dram_size(unsigned int node); +ssize_t atf_node_count(void); +ssize_t atf_env_count(void); +ssize_t atf_env_string(size_t index, char *str); + +#endif diff --git a/include/cavium/atf_part.h b/include/cavium/atf_part.h new file mode 100644 index 00000000000..182f6f4b883 --- /dev/null +++ b/include/cavium/atf_part.h @@ -0,0 +1,26 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __ATF_PART_H__ +#define __ATF_PART_H__ + +struct storage_partition { + unsigned int type; + unsigned int size; + unsigned long offset; +}; + +enum { + PARTITION_NBL1FW_REST = 0, + PARTITION_BL2_BL31 = 1, + PARTITION_UBOOT = 2, + PARTITION_UEFI = 2, + PARTITION_KERNEL = 3, + PARTITION_DEVICE_TREE = 4, + PARTITION_LAST, +}; + +#endif diff --git a/include/cavium/thunderx_svc.h b/include/cavium/thunderx_svc.h new file mode 100644 index 00000000000..416ce3cfecd --- /dev/null +++ b/include/cavium/thunderx_svc.h @@ -0,0 +1,67 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_SVC_H__ +#define __THUNDERX_SVC_H__ + +/* SMC function IDs for general purpose queries */ + +#define THUNDERX_SVC_CALL_COUNT 0x4300ff00 +#define THUNDERX_SVC_UID 0x4300ff01 + +#define THUNDERX_SVC_VERSION 0x4300ff03 + +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ThunderX Service Calls version numbers */ +#define THUNDERX_VERSION_MAJOR 0x0 +#define THUNDERX_VERSION_MINOR 0x1 + +#define THUNDERX_MMC_READ 0x43000101 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_MMC_WRITE 0x43000102 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ + +#define THUNDERX_NOR_READ 0x43000111 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_WRITE 0x43000112 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_ERASE 0x43000113 +/* x1 - block address + */ + +#define THUNDERX_PART_COUNT 0x43000201 +#define THUNDERX_GET_PART 0x43000202 +/* x1 - pointer to the buffer + * x2 - index + */ + +#define THUNDERX_DRAM_SIZE 0x43000301 +/* x1 - node number + */ + +#define THUNDERX_GTI_SYNC 0x43000401 + +#define THUNDERX_ENV_COUNT 0x43000501 +#define THUNDERX_ENV_STRING 0x43000502 +/* x1 - index + */ + +#define THUNDERX_NODE_COUNT 0x43000601 + +#endif /* __THUNDERX_SVC_H__ */ diff --git a/include/command.h b/include/command.h index 2ae9b6c2e6e..0524c0beb09 100644 --- a/include/command.h +++ b/include/command.h @@ -110,6 +110,7 @@ extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, char *const argv[]); extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* * Error codes that commands return to cmd_process(). We use the standard 0 diff --git a/include/common.h b/include/common.h index 75c78d5ac2f..7bed0cc0d12 100644 --- a/include/common.h +++ b/include/common.h @@ -224,32 +224,26 @@ void board_init_f(ulong); void board_init_r(gd_t *, ulong) __attribute__ ((noreturn)); /** - * board_init_f_mem() - Allocate global data and set stack position + * ulong board_init_f_alloc_reserve - allocate reserved area * * This function is called by each architecture very early in the start-up - * code to set up the environment for board_init_f(). It allocates space for - * global_data (see include/asm-generic/global_data.h) and places the stack - * below this. + * code to allow the C runtime to reserve space on the stack for writable + * 'globals' such as GD and the malloc arena. * - * This function requires a stack[1] Normally this is at @top. The function - * starts allocating space from 64 bytes below @top. First it creates space - * for global_data. Then it calls arch_setup_gd() which sets gd to point to - * the global_data space and can reserve additional bytes of space if - * required). Finally it allocates early malloc() memory - * (CONFIG_SYS_MALLOC_F_LEN). The new top of the stack is just below this, - * and it returned by this function. + * @top: top of the reserve area, growing down. + * @return: bottom of reserved area + */ +ulong board_init_f_alloc_reserve(ulong top); + +/** + * board_init_f_init_reserve - initialize the reserved area(s) * - * [1] Strictly speaking it would be possible to implement this function - * in C on many archs such that it does not require a stack. However this - * does not seem hugely important as only 64 byte are wasted. The 64 bytes - * are used to handle the calling standard which generally requires pushing - * addresses or registers onto the stack. We should be able to get away with - * less if this becomes important. + * This function is called once the C runtime has allocated the reserved + * area on the stack. It must initialize the GD at the base of that area. * - * @top: Top of available memory, also normally the top of the stack - * @return: New stack location + * @base: top from which reservation was done */ -ulong board_init_f_mem(ulong top); +void board_init_f_init_reserve(ulong base); /** * arch_setup_gd() - Set up the global_data pointer diff --git a/include/common_timing_params.h b/include/common_timing_params.h index 821de21de73..b97147db419 100644 --- a/include/common_timing_params.h +++ b/include/common_timing_params.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef COMMON_TIMING_PARAMS_H diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 6e299f69ae4..3b198ae3ced 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -29,7 +29,6 @@ #endif #undef CONFIG_DM_WARN -#undef CONFIG_DM_SEQ_ALIAS #undef CONFIG_DM_STDIO #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 05ba13b96ea..826de5bd3b7 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -267,7 +267,7 @@ #endif #if defined(CONFIG_SERIAL_BOOT) -#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) #else #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #endif diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8160b28f784..f8aef2e8302 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -1,9 +1,7 @@ /* * Copyright 2007-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c51db8c5c33..cf6a6063b5e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,10 +18,6 @@ #include <configs/ti_am335x_common.h> -/* Don't override the distro default bootdelay */ -#undef CONFIG_BOOTDELAY -#include <config_distro_defaults.h> - #ifndef CONFIG_SPL_BUILD #ifndef CONFIG_FIT # define CONFIG_FIT diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index aac550a477a..de7538fc9e6 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -142,6 +142,8 @@ */ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_MMC +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 5b8b22f0e64..bb2abf1a422 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -29,6 +29,9 @@ #define CONFIG_HOSTNAME bamboo #include "amcc-common.h" +/* Reclaim some space. */ +#undef CONFIG_SYS_LONGHELP + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ /* diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 3bed9a4f0ef..89c7446d265 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CONFIG_H diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index c26a25cb228..fc2dc5a67d3 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CONFIG_H diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h new file mode 100644 index 00000000000..f0de827fd26 --- /dev/null +++ b/include/configs/clearfog.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CLEARFOG_H +#define _CONFIG_CLEARFOG_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_MV_SDHCI +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* Partition support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_ENV_MIN_ENTRIES 128 + +/* Environment in MMC */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SECT_SIZE 0x200 +#define CONFIG_ENV_SIZE 0x10000 +/* + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC + * boot image starts @ LBA-0. + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot + * image and environment + */ +#define CONFIG_ENV_OFFSET 0xf0000 +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define SPL_BOOT_SDIO_MMC_CARD 2 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +/* SPL related MMC defines */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\ + + 1) +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_CLEARFOG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 944e82f55f6..fdfda6b9034 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CONFIG_H diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 3673e5e3687..ef14132b89e 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -10,15 +10,7 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_ARMADA_XP /* SOC Family Name */ -#define CONFIG_ARMADA_38X -#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ -#define CONFIG_SYS_L2_PL310 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#endif #define CONFIG_DISPLAY_BOARDINFO_LATE /* @@ -99,16 +91,15 @@ #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ #define CONFIG_PHY_MARVELL /* there is a marvell phy */ -#define CONFIG_PHY_ADDR { 1, 0 } -#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ /* PCIe support */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_PCI #define CONFIG_PCI_MVEBU #define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW -#define CONFIG_E1000 /* enable Intel E1000 support for testing */ +#endif #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST @@ -139,9 +130,9 @@ #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) @@ -158,7 +149,7 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif @@ -176,10 +167,6 @@ #endif #endif -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR_A38X -#define CONFIG_DDR3 - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index ab6e5a5bce1..c8b03441855 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,12 +10,8 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_ARMADA_XP /* SOC Family Name */ #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#endif #define CONFIG_DISPLAY_BOARDINFO_LATE /* @@ -30,13 +26,18 @@ * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_PING +#define CONFIG_CMD_SATA #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT @@ -64,48 +65,29 @@ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ #define CONFIG_PHY_MARVELL /* there is a marvell phy */ -#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 } -#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#define CONFIG_RESET_PHY_R #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST /* SATA support */ -#ifdef CONFIG_CMD_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE - -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO - -#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS - -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 - +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA_MV +#define CONFIG_LIBATA +#define CONFIG_LBA48 +#define CONFIG_EFI_PARTITION #define CONFIG_DOS_PARTITION -#endif /* CONFIG_CMD_IDE */ + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT /* PCIe support */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_PCI #define CONFIG_PCI_MVEBU #define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW -#define CONFIG_E1000 /* enable Intel E1000 support for testing */ +#endif /* NAND */ #define CONFIG_SYS_NAND_USE_FLASH_BBT @@ -139,9 +121,9 @@ #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) @@ -161,7 +143,7 @@ #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_SPD_EEPROM 0x4e +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 3be44d40868..817676f1822 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -147,6 +147,11 @@ #define CONFIG_FLASH_CFI_DRIVER 1 /* The following #defines are needed to get flash environment right */ +/* ROM version */ +#define CONFIG_SYS_TEXT_BASE 0xbfc00000 +/* RAM version */ +/* #define CONFIG_SYS_TEXT_BASE 0x80100000 */ + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index d89e661b6b5..99d91486113 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -33,7 +33,7 @@ #define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_TEXT_BASE 0x83FA0000 +#define CONFIG_SYS_TEXT_BASE 0x83F00000 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) @@ -49,6 +49,13 @@ #define CONFIG_BAUDRATE 115200 /* + * DMA + */ +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_DMA_LPC32XX +#endif + +/* * I2C */ #define CONFIG_SYS_I2C @@ -114,9 +121,19 @@ #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE #define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND /* + * USB + */ +#define CONFIG_USB_OHCI_LPC32XX +#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +/* * U-Boot General Configurations */ #define CONFIG_SYS_LONGHELP diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 81070b1fd0d..9d624210501 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -142,6 +142,11 @@ #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 #define CONFIG_QSPI_QUAD_SUPPORT +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif + /* * Default to using SPI for environment, etc. * 0x000000 - 0x010000 : QSPI.SPL (64KiB) diff --git a/include/configs/ds414.h b/include/configs/ds414.h new file mode 100644 index 00000000000..e3c7087a1fa --- /dev/null +++ b/include/configs/ds414.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_SYNOLOGY_DS414_H +#define _CONFIG_SYNOLOGY_DS414_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME +#define CONFIG_CMD_USB + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_ADDR { 0x1, 0x0 } +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII + +#define CONFIG_SYS_ALT_MEMTEST + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* USB/EHCI/XHCI configuration */ + +#define CONFIG_DM_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* FIXME: broken XHCI support + * Below defines should enable support for the two rear USB3 ports. Sadly, this + * does not work because: + * - xhci-pci seems to not support DM_USB, so with that enabled it is not + * found. + * - USB init fails, controller does not respond in time */ +#if 0 +#undef CONFIG_DM_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_PCI +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if !defined(CONFIG_USB_XHCI) +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MARVELL +#define CONFIG_EHCI_IS_TDI +#endif + +/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */ +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#define CONFIG_SYS_MVFS + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 + +/* DS414 bus width is 32bits */ +#define CONFIG_DDR_32BIT + +/* Use random ethernet address if not configured */ +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +/* Default Environment */ +#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200" +#define CONFIG_LOADADDR 0x80000 +#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */ +#define CONFIG_PREBOOT "usb start; sf probe" + +#endif /* _CONFIG_SYNOLOGY_DS414_H */ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 8663c1772a3..8bc89a05eb8 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -20,6 +20,9 @@ #define CONFIG_IDENT_STRING " iocon 0.06" #include "amcc-common.h" +/* Reclaim some space. */ +#undef CONFIG_SYS_LONGHELP + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_LAST_STAGE_INIT diff --git a/include/configs/malta.h b/include/configs/malta.h index 3faac376326..aecc8cef90a 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -7,9 +7,6 @@ #ifndef _MALTA_CONFIG_H #define _MALTA_CONFIG_H -#include <asm/addrspace.h> -#include <asm/malta.h> - /* * System configuration */ @@ -83,14 +80,14 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (115200 * 16) -#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE) -#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) +#define CONFIG_SYS_NS16550_COM1 0xb80003f8 +#define CONFIG_SYS_NS16550_COM2 0xbb0003f8 #define CONFIG_CONS_INDEX 1 /* * Flash configuration */ -#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE) +#define CONFIG_SYS_FLASH_BASE 0xbe000000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_SYS_FLASH_CFI diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index da49243ebfa..43d7fd03a34 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -10,10 +10,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_ARMADA_XP /* SOC Family Name */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#endif #define CONFIG_DISPLAY_BOARDINFO_LATE /* @@ -55,10 +51,7 @@ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ #define CONFIG_PHY_MARVELL /* there is a marvell phy */ -#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 } -#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#define CONFIG_RESET_PHY_R #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST @@ -91,9 +84,9 @@ #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) @@ -112,7 +105,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 1fd7ce31782..174ea088f3e 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __MX6_COMMON_H diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index cf2bc3e6d58..5da6cfd6f59 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -43,7 +43,7 @@ #else #error "status LED not defined for this machine." #endif -#define RED_LED_DEV 0 +#define RED_LED_DEV 0 #define STATUS_LED_BIT RED_LED_GPIO #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) @@ -56,7 +56,7 @@ #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ /* USB */ -#define CONFIG_USB_MUSB_UDC 1 +#define CONFIG_USB_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 #define CONFIG_TWL4030_USB 1 @@ -75,18 +75,11 @@ #ifdef CONFIG_BOOT_ONENAND #define CONFIG_CMD_ONENAND /* ONENAND support */ #endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ - (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) -#endif #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING -/*#undef CONFIG_ENV_IS_NOWHERE*/ - #ifndef CONFIG_SPL_BUILD -#include <config_distro_defaults.h> - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ @@ -138,7 +131,7 @@ #if defined(CONFIG_CMD_NET) #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 +#define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ /* OneNAND boot config */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 4633fec164d..bce4fad8263 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -5,19 +5,7 @@ * * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CONFIG_H diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 8eac81aa218..d9dd9bdcd4b 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CONFIG_H diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 41b7393c0ef..f490e7911d0 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -81,6 +81,11 @@ #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ /* The following #defines are needed to get flash environment right */ +/* ROM version */ +/* #define CONFIG_SYS_TEXT_BASE 0xbfc00000 */ +/* SDRAM version */ +#define CONFIG_SYS_TEXT_BASE 0x83800000 + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 08046b5e995..a995415432c 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -126,21 +126,9 @@ */ #define CONFIG_PARTITION_UUIDS -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - #define CONFIG_CMD_PART /* - * Filesystems - */ - -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FAT - -/* * SPL */ @@ -257,16 +245,24 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ + "loadaddr=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "fdtaddr=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "scriptaddr=0x80000000\0" \ + "bootm_size=0x10000000\0" \ "boot_mmc_dev=0\0" \ "kernel_mmc_part=3\0" \ "recovery_mmc_part=4\0" \ + "fdtfile=omap3-sniper.dtb\0" \ + "bootfile=/boot/extlinux/extlinux.conf\0" \ "bootargs=console=ttyO2 vram=5M,0x9FA00000 omapfb.vram=0:5M\0" /* - * ATAGs / Device Tree + * ATAGs */ -#define CONFIG_OF_LIBFDT #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG @@ -278,7 +274,6 @@ */ #define CONFIG_SYS_LOAD_ADDR 0x82000000 -#define CONFIG_BOOTDELAY 1 #define CONFIG_ANDROID_BOOT_IMAGE @@ -299,5 +294,6 @@ */ #include <config_defaults.h> +#include <config_distro_defaults.h> #endif diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906a6be..8de0ab90469 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -370,7 +370,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT -#define CONFIG_DM_SEQ_ALIAS 1 #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 3e808613b0c..85d492ddc5f 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_STM32F4 #define CONFIG_SYS_THUMB_BUILD #define CONFIG_STM32F4DISCOVERY diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 790e7047d15..b4dfb3cc47c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -212,7 +212,7 @@ #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ - defined CONFIG_I2C4_ENABLE + defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI #define CONFIG_SYS_I2C_SPEED 400000 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index ec0a812aa12..2d941ca65b0 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -384,7 +384,7 @@ do { \ if (i) \ sprintf(ethname, "eth%daddr", i); \ else \ - sprintf(ethname, "ethaddr"); \ + strcpy(ethname, "ethaddr"); \ printf("Setting %s from EEPROM with %s\n", ethname, buf);\ setenv(ethname, buf); \ } \ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 671071ba981..21454d47cb5 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_COMMON_H_ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h new file mode 100644 index 00000000000..cece4ddbcf2 --- /dev/null +++ b/include/configs/thunderx_88xx.h @@ -0,0 +1,145 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_88XX_H__ +#define __THUNDERX_88XX_H__ + +#define CONFIG_REMAKE_ELF + +#define CONFIG_THUNDERX + +#define CONFIG_SYS_64BIT + +#define CONFIG_SYS_NO_FLASH + + +#define CONFIG_IDENT_STRING \ + " for Cavium Thunder CN88XX ARM v8 Multi-Core" +#define CONFIG_BOOTP_VCI_STRING "Diagnostics" + +#define MEM_BASE 0x00500000 + +#define CONFIG_COREID_MASK 0xffffff + +#define CONFIG_SYS_FULL_VA + +#define CONFIG_SYS_LOWMEM_BASE MEM_BASE + +#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ + PTL2_MEMTYPE(MT_NORMAL) | \ + PTL2_BLOCK_NON_SHARE}, \ + {0x800000000000UL, 0x40000000000UL, \ + PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTL2_BLOCK_NON_SHARE}, \ + {0x840000000000UL, 0x40000000000UL, \ + PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTL2_BLOCK_NON_SHARE}, \ + } + +#define CONFIG_SYS_MEM_MAP_SIZE 3 + +#define CONFIG_SYS_VA_BITS 48 +#define CONFIG_SYS_PTL2_BITS 42 +#define CONFIG_SYS_BLOCK_SHIFT 29 +#define CONFIG_SYS_PTL1_ENTRIES 64 +#define CONFIG_SYS_PTL2_ENTRIES 8192 + +#define CONFIG_SYS_PGTABLE_SIZE \ + ((CONFIG_SYS_PTL1_ENTRIES + \ + CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) +#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) +#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) +#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x00500000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + + +#define CONFIG_SYS_MEMTEST_START MEM_BASE +#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* PL011 Serial Configuration */ + +#define CONFIG_PL01X_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_CONS_INDEX 1 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x801000000000) +#define GICR_BASE (0x801000002000) +#define CONFIG_SYS_SERIAL0 0x87e024000000 +#define CONFIG_SYS_SERIAL1 0x87e025000000 + +#define CONFIG_BAUDRATE 115200 + +/* Command line configuration */ +#define CONFIG_MENU + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ +#define UBOOT_IMG_HEAD_SIZE 0x40 +/* C80000 - 0x40 */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=08007ffc0\0" \ + "fdt_addr=0x94C00000\0" \ + "fdt_high=0x9fffffff\0" + +#define CONFIG_BOOTARGS \ + "console=ttyAMA0,115200n8 " \ + "earlycon=pl011,0x87e024000000 " \ + "debug maxcpus=48 rootwait rw "\ + "root=/dev/sda2 coherent_pool=16M" +#define CONFIG_BOOTDELAY 5 + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_NO_RELOCATION 1 +#define CONFIG_LIB_RAND +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) + +#endif /* __THUNDERX_88XX_H__ */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 2087eb194cf..199612be84b 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -283,5 +283,6 @@ #endif #include <config_distro_defaults.h> +#define CONFIG_CMD_EXT4_WRITE #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 1c71cb636b0..02fdcdca8fd 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -73,7 +73,6 @@ #ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SYS_NAND_BASE 0x30000000 #endif diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 08130ebd1b6..8b6c0658e85 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -82,6 +82,32 @@ /* * Environment setup */ +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; "\ + "setenv bootpart " #instance":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ @@ -120,30 +146,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "fi;" \ - "if test -n ${uenvcmd}; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt;" \ - "run mmcboot; " \ - "fi; " \ - "if run loaduimage; then " \ - "run uimageboot;" \ - "fi; " \ - "fi" + BOOTENV /* * Defines for SPL diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 8ec073d343b..3d0cafa1257 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -96,11 +96,11 @@ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 463c6871c09..599b26959e6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -201,15 +201,18 @@ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ - "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "norboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ + "setexpr kernel_addr $nor_base + $kernel_addr &&" \ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr $nor_base + $fdt_addr &&" \ "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ + "nandboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ + "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ - "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ + "tftpboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ + "tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" @@ -226,6 +229,8 @@ "nand write $loadaddr 0x00010000 0x000f0000\0" \ LINUXBOOT_ENV_SETTINGS +#define CONFIG_SYS_BOOTMAPSZ 0x20000000 + /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT diff --git a/include/configs/vct.h b/include/configs/vct.h index 872f2f0c99f..ea6e3c0d0f0 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -32,6 +32,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ +#define CONFIG_SYS_TEXT_BASE 0x87000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_SYS_MALLOC_LEN (1 << 20) diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 70ec1032fd7..4182a3bf631 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -208,6 +208,7 @@ #define CONFIG_HOSTNAME x86 #define CONFIG_BOOTFILE "bzImage" #define CONFIG_LOADADDR 0x1000000 +#define CONFIG_RAMDISK_ADDR 0x4000000 #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ @@ -215,7 +216,7 @@ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ "othbootargs=acpi=off\0" \ - "ramdiskaddr=0x2000000\0" \ + "ramdiskaddr=0x4000000\0" \ "ramdiskfile=initramfs.gz\0" #define CONFIG_RAMBOOTCOMMAND \ diff --git a/include/ddr_spd.h b/include/ddr_spd.h index cf2aac6ae42..d71cd9ab3c0 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _DDR_SPD_H_ diff --git a/include/dm/device.h b/include/dm/device.h index d9fc7fb953f..1cf81501ed9 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -454,6 +454,17 @@ int device_find_next_child(struct udevice **devp); fdt_addr_t dev_get_addr(struct udevice *dev); /** + * dev_get_addr_index() - Get the indexed reg property of a device + * + * @dev: Pointer to a device + * @index: the 'reg' property can hold a list of <addr, size> pairs + * and @index is used to select which one is required + * + * @return addr + */ +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index); + +/** * device_has_children() - check if a device has any children * * @dev: Device to check diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h new file mode 100644 index 00000000000..fd191b5bd58 --- /dev/null +++ b/include/dm/platform_data/lpc32xx_hsuart.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LPC32XX_HSUART_PLAT_H +#define _LPC32XX_HSUART_PLAT_H + +/** + * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data + * + * @base: Base register address + */ +struct lpc32xx_hsuart_platdata { + unsigned long base; +}; + +#endif diff --git a/include/ds4510.h b/include/ds4510.h index 40480afc965..e54db35265e 100644 --- a/include/ds4510.h +++ b/include/ds4510.h @@ -1,19 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __DS4510_H_ diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h index ebafa498be0..638b114e4f3 100644 --- a/include/dt-bindings/pinctrl/pinctrl-tegra.h +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -5,14 +5,7 @@ * * Author: Laxman Dewangan <ldewangan@nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H diff --git a/include/fdtdec.h b/include/fdtdec.h index 7a1450c5762..27b350e2412 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -170,6 +170,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_COUNT, }; diff --git a/include/fs.h b/include/fs.h index 059a39505d4..2f2aca8378b 100644 --- a/include/fs.h +++ b/include/fs.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _FS_H #define _FS_H diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 9aaf6b334cd..3351acdd7ae 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef FSL_DDR_MAIN_H diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h index 751e9351174..12a19441062 100644 --- a/include/fsl_ddr_dimm_params.h +++ b/include/fsl_ddr_dimm_params.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef DDR2_DIMM_PARAMS_H diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 4b022d46391..9ea8b637790 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef FSL_DDR_MEMCTL_H diff --git a/include/hash.h b/include/hash.h index e6d0f1db92e..d81433772fc 100644 --- a/include/hash.h +++ b/include/hash.h @@ -114,21 +114,6 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, int hash_block(const char *algo_name, const void *data, unsigned int len, uint8_t *output, int *output_size); -/** - * hash_show() - Print out a hash algorithm and value - * - * You will get a message like this (without a newline at the end): - * - * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257" - * - * @algo: Algorithm used for hash - * @addr: Address of data that was hashed - * @len: Length of data that was hashed - * @output: Hash value to display - */ -void hash_show(struct hash_algo *algo, ulong addr, ulong len, - uint8_t *output); - #endif /* !USE_HOSTCC */ /** diff --git a/include/ide.h b/include/ide.h index d5e05e97cb2..f9357bee762 100644 --- a/include/ide.h +++ b/include/ide.h @@ -28,21 +28,23 @@ void ide_led(uchar led, uchar status); #ifdef CONFIG_SYS_64BIT_LBA typedef uint64_t lbaint_t; -#define LBAF "%llx" -#define LBAFU "%llu" +#define LBAFlength "ll" #else typedef ulong lbaint_t; -#define LBAF "%lx" -#define LBAFU "%lu" +#define LBAFlength "l" #endif +#define LBAF "%" LBAFlength "x" +#define LBAFU "%" LBAFlength "u" /* * Function Prototypes */ void ide_init(void); -ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer); -ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt, +typedef struct block_dev_desc block_dev_desc_t; +ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer); +ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer); #ifdef CONFIG_IDE_PREINIT diff --git a/include/linux/bch.h b/include/linux/bch.h index 295b4ef153b..28da402f46d 100644 --- a/include/linux/bch.h +++ b/include/linux/bch.h @@ -1,18 +1,7 @@ /* * Generic binary BCH encoding/decoding library * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: GPL-2.0 * * Copyright © 2011 Parrot S.A. * diff --git a/include/linux/edd.h b/include/linux/edd.h index 4cbd0fe9df0..a83742fc7a7 100644 --- a/include/linux/edd.h +++ b/include/linux/edd.h @@ -17,15 +17,7 @@ * information is used to identify BIOS boot disk. The code in setup.S * is very sensitive to the size of these structures. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2.0 as published by - * the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _LINUX_EDD_H #define _LINUX_EDD_H diff --git a/include/linux/input.h b/include/linux/input.h index 44aec763dcf..3662c9f0a74 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -1,9 +1,7 @@ /* * Copyright (c) 1999-2002 Vojtech Pavlik * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _LINUX_INPUT_H diff --git a/include/linux/psci.h b/include/linux/psci.h new file mode 100644 index 00000000000..310d83e0a91 --- /dev/null +++ b/include/linux/psci.h @@ -0,0 +1,90 @@ +/* + * ARM Power State and Coordination Interface (PSCI) header + * + * This header holds common PSCI defines and macros shared + * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. + * + * Copyright (C) 2014 Linaro Ltd. + * Author: Anup Patel <anup.patel@linaro.org> + */ + +#ifndef _UAPI_LINUX_PSCI_H +#define _UAPI_LINUX_PSCI_H + +/* + * PSCI v0.1 interface + * + * The PSCI v0.1 function numbers are implementation defined. + * + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, + * INVALID_PARAMS, and DENIED defined below are applicable + * to PSCI v0.1. + */ + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x84000000 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x40000000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ +#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff +#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 +#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 +#define PSCI_0_2_POWER_STATE_TYPE_MASK \ + (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) +#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 +#define PSCI_0_2_POWER_STATE_AFFL_MASK \ + (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) + +/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ +#define PSCI_0_2_AFFINITY_LEVEL_ON 0 +#define PSCI_0_2_AFFINITY_LEVEL_OFF 1 +#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 + +/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ +#define PSCI_0_2_TOS_UP_MIGRATE 0 +#define PSCI_0_2_TOS_UP_NO_MIGRATE 1 +#define PSCI_0_2_TOS_MP 2 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK \ + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK +#define PSCI_VERSION_MAJOR(ver) \ + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver) \ + ((ver) & PSCI_VERSION_MINOR_MASK) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS -2 +#define PSCI_RET_DENIED -3 +#define PSCI_RET_ALREADY_ON -4 +#define PSCI_RET_ON_PENDING -5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 + +#endif /* _UAPI_LINUX_PSCI_H */ diff --git a/include/mmc.h b/include/mmc.h index 9254b716b95..465daeb0852 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -364,7 +364,6 @@ struct mmc { u8 part_attr; u8 wr_rel_set; char part_config; - char part_num; uint tran_speed; uint read_bl_len; uint write_bl_len; diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a6d721a89ad..b5a0bbf8478 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1297,7 +1297,6 @@ */ #define SDRAM_INTERVAL_REFINT 0x3FFF0000 #define SDRAM_INTERVAL_REFINT_SHIFT 16 -#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 /* diff --git a/include/nand.h b/include/nand.h index d2a53ab856e..7cbbbd327a6 100644 --- a/include/nand.h +++ b/include/nand.h @@ -3,12 +3,7 @@ * 2N Telekomunikace, a.s. <www.2n.cz> * Ladislav Michl <michl@2n.cz> * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _NAND_H_ diff --git a/include/net.h b/include/net.h index ebed29ad577..ac44d614ca3 100644 --- a/include/net.h +++ b/include/net.h @@ -181,8 +181,7 @@ int eth_unregister(struct eth_device *dev);/* Remove network device */ extern struct eth_device *eth_current; -static inline __attribute__((always_inline)) -struct eth_device *eth_get_dev(void) +static __always_inline struct eth_device *eth_get_dev(void) { return eth_current; } @@ -200,14 +199,14 @@ static inline unsigned char *eth_get_ethaddr(void) /* Used only when NetConsole is enabled */ int eth_is_active(struct eth_device *dev); /* Test device for active state */ /* Set active state */ -static inline __attribute__((always_inline)) int eth_init_state_only(void) +static __always_inline int eth_init_state_only(void) { eth_get_dev()->state = ETH_STATE_ACTIVE; return 0; } /* Set passive state */ -static inline __attribute__((always_inline)) void eth_halt_state_only(void) +static __always_inline void eth_halt_state_only(void) { eth_get_dev()->state = ETH_STATE_PASSIVE; } @@ -657,7 +656,7 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, unsigned src_port, unsigned len); #endif -static inline __attribute__((always_inline)) int eth_is_on_demand_init(void) +static __always_inline int eth_is_on_demand_init(void) { #ifdef CONFIG_NETCONSOLE extern enum proto_t net_loop_last_protocol; diff --git a/include/part.h b/include/part.h index 720a867783c..4d00e220e4c 100644 --- a/include/part.h +++ b/include/part.h @@ -10,12 +10,15 @@ #include <ide.h> #include <common.h> -typedef struct block_dev_desc { +typedef struct block_dev_desc block_dev_desc_t; + +struct block_dev_desc { int if_type; /* type of the interface */ int dev; /* device number */ unsigned char part_type; /* partition type */ unsigned char target; /* target SCSI ID */ unsigned char lun; /* target LUN */ + unsigned char hwpart; /* HW partition, e.g. for eMMC */ unsigned char type; /* device type */ unsigned char removable; /* removable device */ #ifdef CONFIG_LBA48 @@ -27,19 +30,19 @@ typedef struct block_dev_desc { char vendor [40+1]; /* IDE model, SCSI Vendor */ char product[20+1]; /* IDE Serial no, SCSI product */ char revision[8+1]; /* firmware revision */ - unsigned long (*block_read)(int dev, + unsigned long (*block_read)(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt, void *buffer); - unsigned long (*block_write)(int dev, + unsigned long (*block_write)(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt, const void *buffer); - unsigned long (*block_erase)(int dev, + unsigned long (*block_erase)(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt); void *priv; /* driver private struct pointer */ -}block_dev_desc_t; +}; #define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz)) #define PAD_TO_BLOCKSIZE(size, block_dev_desc) \ diff --git a/include/pca953x.h b/include/pca953x.h index 6c2b58c563d..8ed2d1875dd 100644 --- a/include/pca953x.h +++ b/include/pca953x.h @@ -1,19 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __PCA953X_H_ diff --git a/include/power/pmic.h b/include/power/pmic.h index 6ba4b6ecd60..e0b2e129dde 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -12,7 +12,6 @@ #define __CORE_PMIC_H_ #include <i2c.h> -#include <spi.h> #include <linux/list.h> #include <power/power_chrg.h> diff --git a/include/spi.h b/include/spi.h index b4d27232ecb..4b88d3986e7 100644 --- a/include/spi.h +++ b/include/spi.h @@ -11,41 +11,27 @@ #define _SPI_H_ /* SPI mode flags */ -#define SPI_CPHA 0x01 /* clock phase */ -#define SPI_CPOL 0x02 /* clock polarity */ -#define SPI_MODE_0 (0|0) /* (original MicroWire) */ -#define SPI_MODE_1 (0|SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL|0) -#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) -#define SPI_CS_HIGH 0x04 /* CS active high */ -#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ -#define SPI_3WIRE 0x10 /* SI/SO signals shared */ -#define SPI_LOOP 0x20 /* loopback mode */ -#define SPI_SLAVE 0x40 /* slave mode */ -#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */ - -/* SPI transfer flags */ -#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ -#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ -#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ -#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ -#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) -#define SPI_XFER_U_PAGE (1 << 5) - -/* SPI TX operation modes */ -#define SPI_OPM_TX_QPP (1 << 0) -#define SPI_OPM_TX_BP (1 << 1) - -/* SPI RX operation modes */ -#define SPI_OPM_RX_AS (1 << 0) -#define SPI_OPM_RX_AF (1 << 1) -#define SPI_OPM_RX_DOUT (1 << 2) -#define SPI_OPM_RX_DIO (1 << 3) -#define SPI_OPM_RX_QOF (1 << 4) -#define SPI_OPM_RX_QIOF (1 << 5) -#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \ - SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ - SPI_OPM_RX_QIOF) +#define SPI_CPHA BIT(0) /* clock phase */ +#define SPI_CPOL BIT(1) /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH BIT(2) /* CS active high */ +#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */ +#define SPI_3WIRE BIT(4) /* SI/SO signals shared */ +#define SPI_LOOP BIT(5) /* loopback mode */ +#define SPI_SLAVE BIT(6) /* slave mode */ +#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */ +#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */ +#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */ +#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */ + +/* SPI mode_rx flags */ +#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */ +#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */ +#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */ /* SPI bus connection options - see enum spi_dual_flash */ #define SPI_CONN_DUAL_SHARED (1 << 0) @@ -75,11 +61,13 @@ struct dm_spi_bus { * @cs: Chip select number (0..n-1) * @max_hz: Maximum bus speed that this slave can tolerate * @mode: SPI mode to use for this device (see SPI mode flags) + * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags) */ struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode; + u8 mode_rx; }; #endif /* CONFIG_DM_SPI */ @@ -99,15 +87,14 @@ struct dm_spi_slave_platdata { * * @dev: SPI slave device * @max_hz: Maximum speed for this slave - * @mode: SPI mode to use for this slave (see SPI mode flags) * @speed: Current bus speed. This is 0 until the bus is first * claimed. * @bus: ID of the bus that the slave is attached to. For * driver model this is the sequence number of the SPI * bus (bus->seq) so does not need to be stored * @cs: ID of the chip select connected to the slave. - * @op_mode_rx: SPI RX operation mode. - * @op_mode_tx: SPI TX operation mode. + * @mode: SPI mode to use for this slave (see SPI mode flags) + * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags) * @wordlen: Size of SPI word in number of bits * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. @@ -120,18 +107,24 @@ struct spi_slave { struct udevice *dev; /* struct spi_slave is dev->parentdata */ uint max_hz; uint speed; - uint mode; #else unsigned int bus; unsigned int cs; #endif - u8 op_mode_rx; - u8 op_mode_tx; + uint mode; + u8 mode_rx; unsigned int wordlen; unsigned int max_write_size; void *memory_map; u8 option; + u8 flags; +#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ +#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ +#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */ +#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */ +#define SPI_XFER_U_PAGE BIT(4) }; /** diff --git a/include/spi_flash.h b/include/spi_flash.h index f25b3e7819c..d0ce9e721ad 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -4,12 +4,7 @@ * Copyright (C) 2008 Atmel Corporation * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _SPI_FLASH_H_ @@ -170,8 +165,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, /* Compatibility function - this is the old U-Boot API */ void spi_flash_free(struct spi_flash *flash); -int spi_flash_remove(struct udevice *flash); - static inline int spi_flash_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) { diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index da09dab9769..b0d9ce9db9d 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -5,19 +5,7 @@ * * Copyright (C) 2003-2006 Christophe Devine * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License, version 2.1 as published by the Free Software Foundation. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA + * SPDX-License-Identifier: LGPL-2.1 */ /* * The SHA-1 standard was published by NIST in 1993. diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h index 99166c44a08..4fa765baa88 100644 --- a/include/usb/ulpi.h +++ b/include/usb/ulpi.h @@ -13,9 +13,7 @@ * Original Copyrights follow: * Copyright (C) 2010 Nokia Corporation * - * This software is distributed under the terms of the GNU General - * Public License ("GPL") as published by the Free Software Foundation, - * version 2 of that License. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __USB_ULPI_H__ diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index 69b80cd1a36..5804b70c354 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -23,12 +23,10 @@ struct ums { unsigned int start_sector; unsigned int num_sectors; const char *name; - block_dev_desc_t *block_dev; + block_dev_desc_t block_dev; }; -extern struct ums *ums; - -int fsg_init(struct ums *); +int fsg_init(struct ums *ums_devs, int count); void fsg_cleanup(void); int fsg_main_thread(void *); int fsg_add(struct usb_configuration *c); diff --git a/include/vsprintf.h b/include/vsprintf.h index b5bc9c1d95f..376f5dd3249 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -124,7 +124,6 @@ int sprintf(char *buf, const char *fmt, ...) int vsprintf(char *buf, const char *fmt, va_list args); char *simple_itoa(ulong i); -#ifdef CONFIG_SYS_VSNPRINTF /** * Format a string and place it in a buffer * @@ -199,17 +198,6 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); * See the vsprintf() documentation for format string extensions over C99. */ int vscnprintf(char *buf, size_t size, const char *fmt, va_list args); -#else -/* - * Use macros to silently drop the size parameter. Note that the 'cn' - * versions are the same as the 'n' versions since the functions assume - * there is always enough buffer space when !CONFIG_SYS_VSNPRINTF - */ -#define snprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args) -#define scnprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args) -#define vsnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args) -#define vscnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args) -#endif /* CONFIG_SYS_VSNPRINTF */ /** * print_grouped_ull() - print a value with digits grouped by ',' diff --git a/lib/Kconfig b/lib/Kconfig index 9d580e4115e..46d7034397c 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -27,15 +27,6 @@ config SYS_HZ get_timer() must operate in milliseconds and this option must be set to 1000. -config SYS_VSNPRINTF - bool "Enable safe version of sprintf()" - help - Since sprintf() can overflow its buffer, it is common to use - snprintf() instead, which knows the buffer size and can avoid - overflow. However, this does increase code size slightly (for - Thumb-2, about 420 bytes). Enable this option for safety when - using sprintf() with data you do not control. - config USE_TINY_PRINTF bool "Enable tiny printf() version" help diff --git a/lib/addr_map.c b/lib/addr_map.c index 31384d13984..403640b95fc 100644 --- a/lib/addr_map.c +++ b/lib/addr_map.c @@ -1,19 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/lib/bch.c b/lib/bch.c index 7f4ca927085..147715afd06 100644 --- a/lib/bch.c +++ b/lib/bch.c @@ -1,18 +1,7 @@ /* * Generic binary BCH encoding/decoding library * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: GPL-2.0 * * Copyright © 2011 Parrot S.A. * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 1093c305266..b50d1051610 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -75,6 +75,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) diff --git a/lib/gunzip.c b/lib/gunzip.c index bdd85c4c175..80b157f99eb 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -70,6 +70,7 @@ int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) return zunzip(dst, dstlen, src, lenp, 1, i); } +#ifdef CONFIG_CMD_UNZIP __weak void gzwrite_progress_init(u64 expectedsize) { @@ -231,8 +232,7 @@ int gzwrite(unsigned char *src, int len, gzwrite_progress(iteration++, totalfilled, szexpected); - blocks_written = dev->block_write(dev->dev, - outblock, + blocks_written = dev->block_write(dev, outblock, writeblocks, writebuf); outblock += blocks_written; @@ -259,6 +259,7 @@ out: return r; } +#endif /* * Uncompress blocks compressed with zlib without headers diff --git a/lib/sha1.c b/lib/sha1.c index 05b17a259a6..72c5dea14f0 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -5,19 +5,7 @@ * * Copyright (C) 2003-2006 Christophe Devine * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License, version 2.1 as published by the Free Software Foundation. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA + * SPDX-License-Identifier: LGPL-2.1 */ /* * The SHA-1 standard was published by NIST in 1993. diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 24167a135c0..874a2951f70 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -141,7 +141,6 @@ static noinline char *put_dec(char *buf, uint64_t num) #define SMALL 32 /* Must be 32 == 0x20 */ #define SPECIAL 64 /* 0x */ -#ifdef CONFIG_SYS_VSNPRINTF /* * Macro to add a new character to our output string, but only if it will * fit. The macro moves to the next character position in the output string. @@ -151,9 +150,6 @@ static noinline char *put_dec(char *buf, uint64_t num) *(str) = (ch); \ ++str; \ } while (0) -#else -#define ADDCH(str, ch) (*(str)++ = (ch)) -#endif static char *number(char *buf, char *end, u64 num, int base, int size, int precision, int type) @@ -441,13 +437,11 @@ static int vsnprintf_internal(char *buf, size_t size, const char *fmt, /* 't' added for ptrdiff_t */ char *end = buf + size; -#ifdef CONFIG_SYS_VSNPRINTF /* Make sure end is always >= buf - do we want this in U-Boot? */ if (end < buf) { end = ((void *)-1); size = end - buf; } -#endif str = buf; for (; *fmt ; ++fmt) { @@ -609,21 +603,16 @@ repeat: flags); } -#ifdef CONFIG_SYS_VSNPRINTF if (size > 0) { ADDCH(str, '\0'); if (str > end) end[-1] = '\0'; --str; } -#else - *str = '\0'; -#endif /* the trailing null byte doesn't count towards the total */ return str - buf; } -#ifdef CONFIG_SYS_VSNPRINTF int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) { @@ -666,7 +655,6 @@ int scnprintf(char *buf, size_t size, const char *fmt, ...) return i; } -#endif /* CONFIG_SYS_VSNPRINT */ /** * Format a string and place it in a buffer (va_list version) diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index d668982cc1d..01a739d23f7 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -6,6 +6,9 @@ # When our migration to Kconfig is done # (= When we move all CONFIGs from header files to Kconfig) # this makefile can be deleted. +# +# SPDX-License-Identifier: GPL-2.0 +# __all: include/autoconf.mk include/autoconf.mk.dep diff --git a/scripts/Makefile.build b/scripts/Makefile.build index de818aec8c5..06e5c203c1f 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -1,6 +1,9 @@ # ========================================================================== # Building # ========================================================================== +# +# SPDX-License-Identifier: GPL-2.0 +# # Modified for U-Boot prefix := tpl diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean index 4853631b1c8..b69533df806 100644 --- a/scripts/Makefile.clean +++ b/scripts/Makefile.clean @@ -1,6 +1,9 @@ # ========================================================================== # Cleaning up # ========================================================================== +# +# SPDX-License-Identifier: GPL-2.0 +# src := $(obj) diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn index 0ec0d24b1c7..6547e573574 100644 --- a/scripts/Makefile.extrawarn +++ b/scripts/Makefile.extrawarn @@ -9,6 +9,9 @@ # $(call cc-option, -W...) handles gcc -W.. options which # are not supported by all versions of the compiler # ========================================================================== +# +# SPDX-License-Identifier: GPL-2.0 +# ifeq ("$(origin W)", "command line") export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) diff --git a/scripts/Makefile.host b/scripts/Makefile.host index 133edfae5b8..bff8b5bc614 100644 --- a/scripts/Makefile.host +++ b/scripts/Makefile.host @@ -19,6 +19,9 @@ # qconf-objs := menu.o # Will compile qconf as a C++ program, and menu as a C program. # They are linked as C++ code to the executable qconf +# +# SPDX-License-Identifier: GPL-2.0 +# __hostprogs := $(sort $(hostprogs-y) $(hostprogs-m)) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index ed30bf5bb96..1644f8c48d4 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -1,3 +1,6 @@ +# +# SPDX-License-Identifier: GPL-2.0 +# # Backward compatibility asflags-y += $(EXTRA_AFLAGS) ccflags-y += $(EXTRA_CFLAGS) diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index 40035468e76..15d0836b49a 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -1,5 +1,7 @@ # Makefile version of include/config_uncmd_spl.h # +# SPDX-License-Identifier: GPL-2.0+ +# # TODO: Invent a better way ifdef CONFIG_SPL_BUILD diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c index 8d016faa28d..09938ae63a2 100644 --- a/scripts/kconfig/lxdialog/checklist.c +++ b/scripts/kconfig/lxdialog/checklist.c @@ -6,19 +6,7 @@ * Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include "dialog.h" diff --git a/scripts/kconfig/lxdialog/dialog.h b/scripts/kconfig/lxdialog/dialog.h index fcffd5b41fb..cff73a6c6e1 100644 --- a/scripts/kconfig/lxdialog/dialog.h +++ b/scripts/kconfig/lxdialog/dialog.h @@ -3,19 +3,7 @@ * * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include <sys/types.h> diff --git a/scripts/kconfig/lxdialog/inputbox.c b/scripts/kconfig/lxdialog/inputbox.c index d58de1dc536..f8b7ef784bb 100644 --- a/scripts/kconfig/lxdialog/inputbox.c +++ b/scripts/kconfig/lxdialog/inputbox.c @@ -4,19 +4,7 @@ * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include "dialog.h" diff --git a/scripts/kconfig/lxdialog/menubox.c b/scripts/kconfig/lxdialog/menubox.c index 11ae9ad7ac7..99f923ee922 100644 --- a/scripts/kconfig/lxdialog/menubox.c +++ b/scripts/kconfig/lxdialog/menubox.c @@ -4,19 +4,7 @@ * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/scripts/kconfig/lxdialog/textbox.c b/scripts/kconfig/lxdialog/textbox.c index 1773319b95e..d3ad43fd955 100644 --- a/scripts/kconfig/lxdialog/textbox.c +++ b/scripts/kconfig/lxdialog/textbox.c @@ -4,19 +4,7 @@ * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include "dialog.h" diff --git a/scripts/kconfig/lxdialog/util.c b/scripts/kconfig/lxdialog/util.c index f7abdeb92af..a6dec283281 100644 --- a/scripts/kconfig/lxdialog/util.c +++ b/scripts/kconfig/lxdialog/util.c @@ -4,19 +4,7 @@ * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include <stdarg.h> diff --git a/scripts/kconfig/lxdialog/yesno.c b/scripts/kconfig/lxdialog/yesno.c index 676fb2f824a..a732e24712d 100644 --- a/scripts/kconfig/lxdialog/yesno.c +++ b/scripts/kconfig/lxdialog/yesno.c @@ -4,19 +4,7 @@ * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include "dialog.h" diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c index 315ce2c7cb9..953d5c75e5d 100644 --- a/scripts/kconfig/mconf.c +++ b/scripts/kconfig/mconf.c @@ -379,7 +379,7 @@ static void update_text(char *buf, size_t start, size_t end, void *_data) data->targets[k] = pos->target; k++; } else { - sprintf(header, " "); + strcpy(header, " "); } memcpy(buf + pos->offset, header, sizeof(header) - 1); diff --git a/test/dm/usb.c b/test/dm/usb.c index cbc7899ff97..3a2e52b2b57 100644 --- a/test/dm/usb.c +++ b/test/dm/usb.c @@ -50,7 +50,7 @@ static int dm_test_usb_flash(struct unit_test_state *uts) /* Read a few blocks and look for the string we expect */ ut_asserteq(512, dev_desc->blksz); memset(cmp, '\0', sizeof(cmp)); - ut_asserteq(2, dev_desc->block_read(dev_desc->dev, 0, 2, cmp)); + ut_asserteq(2, dev_desc->block_read(dev_desc, 0, 2, cmp)); ut_assertok(strcmp(cmp, "this is a test")); return 0; diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh index fc41c04c15e..043e5d0c0e4 100755 --- a/test/fs/fs-test.sh +++ b/test/fs/fs-test.sh @@ -100,7 +100,7 @@ function compile_sandbox() { # We save time by not deleting and recreating the file system images function prepare_env() { rm -f ${MD5_FILE}.* ${OUT}.* - mkdir ${OUT_DIR} + mkdir -p ${OUT_DIR} } # 1st parameter is the name of the image file to be created @@ -115,11 +115,23 @@ function create_image() { fi if [ ! -f "$1" ]; then fallocate -l 3G "$1" &> /dev/null + if [ $? -ne 0 ]; then + echo fallocate failed - using dd instead + dd if=/dev/zero of=$1 bs=1024 count=$((3 * 1024 * 1024)) + if [ $? -ne 0 ]; then + echo Could not create empty disk image + exit $? + fi + fi mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null if [ $? -ne 0 -a "$2" = "fat" ]; then # If we fail and we did fat, try vfat. mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null fi + if [ $? -ne 0 ]; then + echo Could not create filesystem + exit $? + fi fi } diff --git a/tools/Makefile b/tools/Makefile index d49e40dd561..1382b0562e5 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -156,7 +156,7 @@ ubsha1-objs := os_support.o ubsha1.o lib/sha1.o HOSTCFLAGS_ubsha1.o := -pedantic hostprogs-$(CONFIG_KIRKWOOD) += kwboot -hostprogs-$(CONFIG_ARMADA_XP) += kwboot +hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela diff --git a/tools/kwboot.c b/tools/kwboot.c index c5f4492b5f7..905ade3b012 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -9,10 +9,14 @@ * 2008. Chapter 24.2 "BootROM Firmware". */ +#include "kwbimage.h" +#include "mkimage.h" + #include <stdlib.h> #include <stdio.h> #include <string.h> #include <stdarg.h> +#include <image.h> #include <libgen.h> #include <fcntl.h> #include <errno.h> @@ -22,8 +26,6 @@ #include <sys/mman.h> #include <sys/stat.h> -#include "kwbimage.h" - #ifdef __GNUC__ #define PACKED __attribute((packed)) #else @@ -652,6 +654,14 @@ kwboot_img_patch_hdr(void *img, size_t size) hdr->blockid = IBR_HDR_UART_ID; + /* + * Subtract mkimage header size from destination address + * as this header is not expected by the Marvell BootROM. + * This way, the execution address is identical to the + * one the image is compiled for (TEXT_BASE). + */ + hdr->destaddr = hdr->destaddr - sizeof(struct image_header); + if (image_ver == 0) { struct main_hdr_v0 *hdr_v0 = img; diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py index 71c2e91566b..790c27e4598 100755 --- a/tools/microcode-tool.py +++ b/tools/microcode-tool.py @@ -95,9 +95,23 @@ def ParseHeaderFiles(fname_list): name = os.path.splitext(name)[0] data = [] with open(fname) as fd: + license_start = False + license_end = False for line in fd: line = line.rstrip() + if len(line) >= 2: + if line[0] == '/' and line[1] == '*': + license_start = True + continue + if line[0] == '*' and line[1] == '/': + license_end = True + continue + if license_start and not license_end: + # Ignore blank line + if len(line) > 0: + license_text.append(line) + continue # Omit anything after the last comma words = line.split(',')[:-1] data += [word + ',' for word in words] |