diff options
60 files changed, 1660 insertions, 2750 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6ecc7bbdf25..042282f3723 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -975,9 +975,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ -dtb-$(CONFIG_TARGET_RZG2L) += \ - r9a07g044l2-smarc.dts - ifdef CONFIG_RCAR_64 DTC_FLAGS += -R 4 -p 0x1000 endif diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi new file mode 100644 index 00000000000..dd5a208cc1b --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board + * + * Copyright (C) 2021-2024 Renesas Electronics Corporation + */ + +#include "r8a774a1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi deleted file mode 100644 index 3ad619bdb90..00000000000 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board - * - * Copyright (C) 2021 Renesas Electronics Corporation - */ - -#include "r8a774a1-u-boot.dtsi" - -&gpio3 { - bt_reg_on{ - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "bt-reg-on"; - }; -}; - -&gpio4 { - wlan_reg_on{ - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "wlan-reg-on"; - }; -}; diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi index 38f5bfe85fc..3530eeb2718 100644 --- a/arch/arm/dts/r8a774a1-u-boot.dtsi +++ b/arch/arm/dts/r8a774a1-u-boot.dtsi @@ -10,45 +10,3 @@ &extalr_clk { bootph-all; }; - -/delete-node/ &audma0; -/delete-node/ &audma1; -/delete-node/ &can0; -/delete-node/ &can1; -/delete-node/ &canfd; -/delete-node/ &csi20; -/delete-node/ &csi40; -/delete-node/ &du; -/delete-node/ &fcpf0; -/delete-node/ &fcpvb0; -/delete-node/ &fcpvd0; -/delete-node/ &fcpvd1; -/delete-node/ &fcpvd2; -/delete-node/ &fcpvi0; -/delete-node/ &hdmi0; -/delete-node/ &lvds0; -/delete-node/ &rcar_sound; -/delete-node/ &sound_card; -/delete-node/ &vin0; -/delete-node/ &vin1; -/delete-node/ &vin2; -/delete-node/ &vin3; -/delete-node/ &vin4; -/delete-node/ &vin5; -/delete-node/ &vin6; -/delete-node/ &vin7; -/delete-node/ &vspb; -/delete-node/ &vspd0; -/delete-node/ &vspd1; -/delete-node/ &vspd2; -/delete-node/ &vspi0; - -/ { - /delete-node/ hdmi0-out; -}; - -/ { - soc { - /delete-node/ fdp1@fe940000; - }; -}; diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi new file mode 100644 index 00000000000..b378cabb22c --- /dev/null +++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board + * + * Copyright (C) 2021-2024 Renesas Electronics Corp. + */ + +#include "r8a774b1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi deleted file mode 100644 index 6f2f6c71c2f..00000000000 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include "r8a774b1-u-boot.dtsi" - -&gpio3 { - bt_reg_on{ - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "bt-reg-on"; - }; -}; - -&gpio4 { - wlan_reg_on{ - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "wlan-reg-on"; - }; -}; diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi index d4890ebc298..07aeabc46b4 100644 --- a/arch/arm/dts/r8a774b1-u-boot.dtsi +++ b/arch/arm/dts/r8a774b1-u-boot.dtsi @@ -10,43 +10,3 @@ &extalr_clk { bootph-all; }; - -/delete-node/ &audma0; -/delete-node/ &audma1; -/delete-node/ &can0; -/delete-node/ &can1; -/delete-node/ &canfd; -/delete-node/ &csi20; -/delete-node/ &csi40; -/delete-node/ &du; -/delete-node/ &fcpf0; -/delete-node/ &fcpvb0; -/delete-node/ &fcpvd0; -/delete-node/ &fcpvd1; -/delete-node/ &fcpvi0; -/delete-node/ &hdmi0; -/delete-node/ &lvds0; -/delete-node/ &rcar_sound; -/delete-node/ &sound_card; -/delete-node/ &vin0; -/delete-node/ &vin1; -/delete-node/ &vin2; -/delete-node/ &vin3; -/delete-node/ &vin4; -/delete-node/ &vin5; -/delete-node/ &vin6; -/delete-node/ &vin7; -/delete-node/ &vspb; -/delete-node/ &vspd0; -/delete-node/ &vspd1; -/delete-node/ &vspi0; - -/ { - /delete-node/ hdmi0-out; -}; - -/ { - soc { - /delete-node/ fdp1@fe940000; - }; -}; diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi new file mode 100644 index 00000000000..560bea46ad7 --- /dev/null +++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board + * + * Copyright (C) 2020-2024 Renesas Electronics Corp. + */ + +#include "r8a774e1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi deleted file mode 100644 index 8e57e03c899..00000000000 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774e1-u-boot.dtsi" - -&gpio3 { - bt_reg_on{ - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "bt-reg-on"; - }; -}; - -&gpio4 { - wlan_reg_on{ - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "wlan-reg-on"; - }; -}; diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi index 45ef5b78240..2202731ccb3 100644 --- a/arch/arm/dts/r8a774e1-u-boot.dtsi +++ b/arch/arm/dts/r8a774e1-u-boot.dtsi @@ -10,49 +10,3 @@ &extalr_clk { bootph-all; }; - -/delete-node/ &audma0; -/delete-node/ &audma1; -/delete-node/ &can0; -/delete-node/ &can1; -/delete-node/ &canfd; -/delete-node/ &csi20; -/delete-node/ &csi40; -/delete-node/ &du; -/delete-node/ &fcpf0; -/delete-node/ &fcpf1; -/delete-node/ &fcpvb0; -/delete-node/ &fcpvb1; -/delete-node/ &fcpvd0; -/delete-node/ &fcpvd1; -/delete-node/ &fcpvi0; -/delete-node/ &fcpvi1; -/delete-node/ &hdmi0; -/delete-node/ &lvds0; -/delete-node/ &rcar_sound; -/delete-node/ &sound_card; -/delete-node/ &vin0; -/delete-node/ &vin1; -/delete-node/ &vin2; -/delete-node/ &vin3; -/delete-node/ &vin4; -/delete-node/ &vin5; -/delete-node/ &vin6; -/delete-node/ &vin7; -/delete-node/ &vspbc; -/delete-node/ &vspbd; -/delete-node/ &vspd0; -/delete-node/ &vspd1; -/delete-node/ &vspi0; -/delete-node/ &vspi1; - -/ { - /delete-node/ hdmi0-out; -}; - -/ { - soc { - /delete-node/ fdp1@fe940000; - /delete-node/ fdp1@fe944000; - }; -}; diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi deleted file mode 100644 index 66f68fc2b24..00000000000 --- a/arch/arm/dts/r9a07g044.dtsi +++ /dev/null @@ -1,1273 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/r9a07g044-cpg.h> - -/ { - compatible = "renesas,r9a07g044"; - #address-cells = <2>; - #size-cells = <2>; - - audio_clk1: audio1-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by boards that provide it */ - clock-frequency = <0>; - }; - - audio_clk2: audio2-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by boards that provide it */ - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a55"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - next-level-cache = <&L3_CA55>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@100 { - compatible = "arm,cortex-a55"; - reg = <0x100>; - device_type = "cpu"; - next-level-cache = <&L3_CA55>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; - operating-points-v2 = <&cluster0_opp>; - }; - - L3_CA55: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-size = <0x40000>; - cache-level = <3>; - }; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1100000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <1100000>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1100000>; - }; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <1100000>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1100000>; - }; - - opp-62500000 { - opp-hz = /bits/ 64 <62500000>; - opp-microvolt = <1100000>; - }; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <1100000>; - }; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mtu3: timer@10001200 { - compatible = "renesas,r9a07g044-mtu3", - "renesas,rz-mtu3"; - reg = <0 0x10001200 0 0xb00>; - interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", - "tciv0", "tgie0", "tgif0", - "tgia1", "tgib1", "tciv1", "tciu1", - "tgia2", "tgib2", "tciv2", "tciu2", - "tgia3", "tgib3", "tgic3", "tgid3", - "tciv3", - "tgia4", "tgib4", "tgic4", "tgid4", - "tciv4", - "tgiu5", "tgiv5", "tgiw5", - "tgia6", "tgib6", "tgic6", "tgid6", - "tciv6", - "tgia7", "tgib7", "tgic7", "tgid7", - "tciv7", - "tgia8", "tgib8", "tgic8", "tgid8", - "tciv8", "tciu8"; - clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; - #pwm-cells = <2>; - status = "disabled"; - }; - - ssi0: ssi@10049c00 { - compatible = "renesas,r9a07g044-ssi", - "renesas,rz-ssi"; - reg = <0 0x10049c00 0 0x400>; - interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx"; - clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, - <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, - <&audio_clk1>, <&audio_clk2>; - clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; - resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; - dmas = <&dmac 0x2655>, <&dmac 0x2656>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - ssi1: ssi@1004a000 { - compatible = "renesas,r9a07g044-ssi", - "renesas,rz-ssi"; - reg = <0 0x1004a000 0 0x400>; - interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx"; - clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, - <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, - <&audio_clk1>, <&audio_clk2>; - clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; - resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; - dmas = <&dmac 0x2659>, <&dmac 0x265a>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - ssi2: ssi@1004a400 { - compatible = "renesas,r9a07g044-ssi", - "renesas,rz-ssi"; - reg = <0 0x1004a400 0 0x400>; - interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rt"; - clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, - <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, - <&audio_clk1>, <&audio_clk2>; - clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; - resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; - dmas = <&dmac 0x265f>; - dma-names = "rt"; - power-domains = <&cpg>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - ssi3: ssi@1004a800 { - compatible = "renesas,r9a07g044-ssi", - "renesas,rz-ssi"; - reg = <0 0x1004a800 0 0x400>; - interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx"; - clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, - <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, - <&audio_clk1>, <&audio_clk2>; - clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; - resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; - dmas = <&dmac 0x2661>, <&dmac 0x2662>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1004ac00 { - compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; - reg = <0 0x1004ac00 0 0x400>; - interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; - resets = <&cpg R9A07G044_RSPI0_RST>; - dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@1004b000 { - compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; - reg = <0 0x1004b000 0 0x400>; - interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; - resets = <&cpg R9A07G044_RSPI1_RST>; - dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@1004b400 { - compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; - reg = <0 0x1004b400 0 0x400>; - interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; - resets = <&cpg R9A07G044_RSPI2_RST>; - dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scif0: serial@1004b800 { - compatible = "renesas,scif-r9a07g044"; - reg = <0 0x1004b800 0 0x400>; - interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; - status = "disabled"; - }; - - scif1: serial@1004bc00 { - compatible = "renesas,scif-r9a07g044"; - reg = <0 0x1004bc00 0 0x400>; - interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; - status = "disabled"; - }; - - scif2: serial@1004c000 { - compatible = "renesas,scif-r9a07g044"; - reg = <0 0x1004c000 0 0x400>; - interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; - status = "disabled"; - }; - - scif3: serial@1004c400 { - compatible = "renesas,scif-r9a07g044"; - reg = <0 0x1004c400 0 0x400>; - interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; - status = "disabled"; - }; - - scif4: serial@1004c800 { - compatible = "renesas,scif-r9a07g044"; - reg = <0 0x1004c800 0 0x400>; - interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; - status = "disabled"; - }; - - sci0: serial@1004d000 { - compatible = "renesas,r9a07g044-sci", "renesas,sci"; - reg = <0 0x1004d000 0 0x400>; - interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCI0_RST>; - status = "disabled"; - }; - - sci1: serial@1004d400 { - compatible = "renesas,r9a07g044-sci", "renesas,sci"; - reg = <0 0x1004d400 0 0x400>; - interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCI1_RST>; - status = "disabled"; - }; - - canfd: can@10050000 { - compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; - reg = <0 0x10050000 0 0x8000>; - interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "g_err", "g_recc", - "ch0_err", "ch0_rec", "ch0_trx", - "ch1_err", "ch1_rec", "ch1_trx"; - clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, - <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; - assigned-clock-rates = <50000000>; - resets = <&cpg R9A07G044_CANFD_RSTP_N>, - <&cpg R9A07G044_CANFD_RSTC_N>; - reset-names = "rstp_n", "rstc_n"; - power-domains = <&cpg>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - channel1 { - status = "disabled"; - }; - }; - - i2c0: i2c@10058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; - reg = <0 0x10058000 0 0x400>; - interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; - clock-frequency = <100000>; - resets = <&cpg R9A07G044_I2C0_MRST>; - power-domains = <&cpg>; - status = "disabled"; - }; - - i2c1: i2c@10058400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; - reg = <0 0x10058400 0 0x400>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; - clock-frequency = <100000>; - resets = <&cpg R9A07G044_I2C1_MRST>; - power-domains = <&cpg>; - status = "disabled"; - }; - - i2c2: i2c@10058800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; - reg = <0 0x10058800 0 0x400>; - interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; - clock-frequency = <100000>; - resets = <&cpg R9A07G044_I2C2_MRST>; - power-domains = <&cpg>; - status = "disabled"; - }; - - i2c3: i2c@10058c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; - reg = <0 0x10058c00 0 0x400>; - interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; - clock-frequency = <100000>; - resets = <&cpg R9A07G044_I2C3_MRST>; - power-domains = <&cpg>; - status = "disabled"; - }; - - adc: adc@10059000 { - compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; - reg = <0 0x10059000 0 0x400>; - interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; - clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, - <&cpg CPG_MOD R9A07G044_ADC_PCLK>; - clock-names = "adclk", "pclk"; - resets = <&cpg R9A07G044_ADC_PRESETN>, - <&cpg R9A07G044_ADC_ADRST_N>; - reset-names = "presetn", "adrst-n"; - power-domains = <&cpg>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0>; - }; - channel@1 { - reg = <1>; - }; - channel@2 { - reg = <2>; - }; - channel@3 { - reg = <3>; - }; - channel@4 { - reg = <4>; - }; - channel@5 { - reg = <5>; - }; - channel@6 { - reg = <6>; - }; - channel@7 { - reg = <7>; - }; - }; - - tsu: thermal@10059400 { - compatible = "renesas,r9a07g044-tsu", - "renesas,rzg2l-tsu"; - reg = <0 0x10059400 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; - resets = <&cpg R9A07G044_TSU_PRESETN>; - power-domains = <&cpg>; - #thermal-sensor-cells = <1>; - }; - - sbc: spi@10060000 { - compatible = "renesas,r9a07g044-rpc-if", - "renesas,rzg2l-rpc-if"; - reg = <0 0x10060000 0 0x10000>, - <0 0x20000000 0 0x10000000>, - <0 0x10070000 0 0x10000>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, - <&cpg CPG_MOD R9A07G044_SPI_CLK>; - resets = <&cpg R9A07G044_SPI_RST>; - power-domains = <&cpg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - cru: video@10830000 { - compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; - reg = <0 0x10830000 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, - <&cpg CPG_MOD R9A07G044_CRU_PCLK>, - <&cpg CPG_MOD R9A07G044_CRU_ACLK>; - clock-names = "video", "apb", "axi"; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; - resets = <&cpg R9A07G044_CRU_PRESETN>, - <&cpg R9A07G044_CRU_ARESETN>; - reset-names = "presetn", "aresetn"; - power-domains = <&cpg>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - cruparallel: endpoint@0 { - reg = <0>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - crucsi2: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi2cru>; - }; - }; - }; - }; - - csi2: csi2@10830400 { - compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2"; - reg = <0 0x10830400 0 0xfc00>; - interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>, - <&cpg CPG_MOD R9A07G044_CRU_VCLK>, - <&cpg CPG_MOD R9A07G044_CRU_PCLK>; - clock-names = "system", "video", "apb"; - resets = <&cpg R9A07G044_CRU_PRESETN>, - <&cpg R9A07G044_CRU_CMN_RSTB>; - reset-names = "presetn", "cmn-rstb"; - power-domains = <&cpg>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - csi2cru: endpoint@0 { - reg = <0>; - remote-endpoint = <&crucsi2>; - }; - }; - }; - }; - - dsi: dsi@10850000 { - compatible = "renesas,r9a07g044-mipi-dsi", - "renesas,rzg2l-mipi-dsi"; - reg = <0 0x10850000 0 0x20000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "seq0", "seq1", "vin1", "rcv", - "ferr", "ppi", "debug"; - clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, - <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, - <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, - <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, - <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, - <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; - clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; - resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, - <&cpg R9A07G044_MIPI_DSI_ARESET_N>, - <&cpg R9A07G044_MIPI_DSI_PRESET_N>; - reset-names = "rst", "arst", "prst"; - power-domains = <&cpg>; - status = "disabled"; - }; - - vspd: vsp@10870000 { - compatible = "renesas,r9a07g044-vsp2"; - reg = <0 0x10870000 0 0x10000>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, - <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, - <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; - clock-names = "aclk", "pclk", "vclk"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_LCDC_RESET_N>; - renesas,fcp = <&fcpvd>; - }; - - fcpvd: fcp@10880000 { - compatible = "renesas,r9a07g044-fcpvd", - "renesas,fcpv"; - reg = <0 0x10880000 0 0x10000>; - clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, - <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, - <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; - clock-names = "aclk", "pclk", "vclk"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_LCDC_RESET_N>; - }; - - cpg: clock-controller@11010000 { - compatible = "renesas,r9a07g044-cpg"; - reg = <0 0x11010000 0 0x10000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; - reg = <0 0x11020000 0 0x10000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "lpm_int", "ca55stbydone_int", - "cm33stbyr_int", "ca55_deny"; - status = "disabled"; - }; - - pinctrl: pinctrl@11030000 { - compatible = "renesas,r9a07g044-pinctrl"; - reg = <0 0x11030000 0 0x10000>; - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - interrupt-parent = <&irqc>; - interrupt-controller; - gpio-ranges = <&pinctrl 0 0 392>; - clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_GPIO_RSTN>, - <&cpg R9A07G044_GPIO_PORT_RESETN>, - <&cpg R9A07G044_GPIO_SPARE_RESETN>; - }; - - irqc: interrupt-controller@110a0000 { - compatible = "renesas,r9a07g044-irqc", - "renesas,rzg2l-irqc"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x110a0000 0 0x10000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, - <&cpg CPG_MOD R9A07G044_IA55_PCLK>; - clock-names = "clk", "pclk"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_IA55_RESETN>; - }; - - dmac: dma-controller@11820000 { - compatible = "renesas,r9a07g044-dmac", - "renesas,rz-dmac"; - reg = <0 0x11820000 0 0x10000>, - <0 0x11830000 0 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, - <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; - clock-names = "main", "register"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_DMAC_ARESETN>, - <&cpg R9A07G044_DMAC_RST_ASYNC>; - reset-names = "arst", "rst_async"; - #dma-cells = <1>; - dma-channels = <16>; - }; - - gpu: gpu@11840000 { - compatible = "renesas,r9a07g044-mali", - "arm,mali-bifrost"; - reg = <0x0 0x11840000 0x0 0x10000>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu", "event"; - clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, - <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, - <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; - clock-names = "gpu", "bus", "bus_ace"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_GPU_RESETN>, - <&cpg R9A07G044_GPU_AXI_RESETN>, - <&cpg R9A07G044_GPU_ACE_RESETN>; - reset-names = "rst", "axi_rst", "ace_rst"; - operating-points-v2 = <&gpu_opp_table>; - }; - - gic: interrupt-controller@11900000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; - }; - - sdhi0: mmc@11c00000 { - compatible = "renesas,sdhi-r9a07g044", - "renesas,rcar-gen3-sdhi"; - reg = <0x0 0x11c00000 0 0x10000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, - <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, - <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; - clock-names = "core", "clkh", "cd", "aclk"; - resets = <&cpg R9A07G044_SDHI0_IXRST>; - power-domains = <&cpg>; - status = "disabled"; - }; - - sdhi1: mmc@11c10000 { - compatible = "renesas,sdhi-r9a07g044", - "renesas,rcar-gen3-sdhi"; - reg = <0x0 0x11c10000 0 0x10000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, - <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, - <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; - clock-names = "core", "clkh", "cd", "aclk"; - resets = <&cpg R9A07G044_SDHI1_IXRST>; - power-domains = <&cpg>; - status = "disabled"; - }; - - eth0: ethernet@11c20000 { - compatible = "renesas,r9a07g044-gbeth", - "renesas,rzg2l-gbeth"; - reg = <0 0x11c20000 0 0x10000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mux", "fil", "arp_ns"; - phy-mode = "rgmii"; - clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, - <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, - <&cpg CPG_CORE R9A07G044_CLK_HP>; - clock-names = "axi", "chi", "refclk"; - resets = <&cpg R9A07G044_ETH0_RST_HW_N>; - power-domains = <&cpg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - eth1: ethernet@11c30000 { - compatible = "renesas,r9a07g044-gbeth", - "renesas,rzg2l-gbeth"; - reg = <0 0x11c30000 0 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mux", "fil", "arp_ns"; - phy-mode = "rgmii"; - clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, - <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, - <&cpg CPG_CORE R9A07G044_CLK_HP>; - clock-names = "axi", "chi", "refclk"; - resets = <&cpg R9A07G044_ETH1_RST_HW_N>; - power-domains = <&cpg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - phyrst: usbphy-ctrl@11c40000 { - compatible = "renesas,r9a07g044-usbphy-ctrl", - "renesas,rzg2l-usbphy-ctrl"; - reg = <0 0x11c40000 0 0x10000>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; - resets = <&cpg R9A07G044_USB_PRESETN>; - power-domains = <&cpg>; - #reset-cells = <1>; - status = "disabled"; - }; - - ohci0: usb@11c50000 { - compatible = "generic-ohci"; - reg = <0 0x11c50000 0 0x100>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; - resets = <&phyrst 0>, - <&cpg R9A07G044_USB_U2H0_HRESETN>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ohci1: usb@11c70000 { - compatible = "generic-ohci"; - reg = <0 0x11c70000 0 0x100>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; - resets = <&phyrst 1>, - <&cpg R9A07G044_USB_U2H1_HRESETN>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ehci0: usb@11c50100 { - compatible = "generic-ehci"; - reg = <0 0x11c50100 0 0x100>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; - resets = <&phyrst 0>, - <&cpg R9A07G044_USB_U2H0_HRESETN>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ehci1: usb@11c70100 { - compatible = "generic-ehci"; - reg = <0 0x11c70100 0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; - resets = <&phyrst 1>, - <&cpg R9A07G044_USB_U2H1_HRESETN>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&cpg>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@11c50200 { - compatible = "renesas,usb2-phy-r9a07g044", - "renesas,rzg2l-usb2-phy"; - reg = <0 0x11c50200 0 0x700>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; - resets = <&phyrst 0>; - #phy-cells = <1>; - power-domains = <&cpg>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@11c70200 { - compatible = "renesas,usb2-phy-r9a07g044", - "renesas,rzg2l-usb2-phy"; - reg = <0 0x11c70200 0 0x700>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; - resets = <&phyrst 1>; - #phy-cells = <1>; - power-domains = <&cpg>; - status = "disabled"; - }; - - hsusb: usb@11c60000 { - compatible = "renesas,usbhs-r9a07g044", - "renesas,rza2-usbhs"; - reg = <0 0x11c60000 0 0x10000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, - <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>; - resets = <&phyrst 0>, - <&cpg R9A07G044_USB_U2P_EXL_SYSRST>; - renesas,buswait = <7>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - wdt0: watchdog@12800800 { - compatible = "renesas,r9a07g044-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800800 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, - <&cpg CPG_MOD R9A07G044_WDT0_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G044_WDT0_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - - wdt1: watchdog@12800c00 { - compatible = "renesas,r9a07g044-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, - <&cpg CPG_MOD R9A07G044_WDT1_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G044_WDT1_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm0: timer@12801000 { - compatible = "renesas,r9a07g044-ostm", - "renesas,ostm"; - reg = <0x0 0x12801000 0x0 0x400>; - interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; - clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; - resets = <&cpg R9A07G044_OSTM0_PRESETZ>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm1: timer@12801400 { - compatible = "renesas,r9a07g044-ostm", - "renesas,ostm"; - reg = <0x0 0x12801400 0x0 0x400>; - interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; - clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; - resets = <&cpg R9A07G044_OSTM1_PRESETZ>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm2: timer@12801800 { - compatible = "renesas,r9a07g044-ostm", - "renesas,ostm"; - reg = <0x0 0x12801800 0x0 0x400>; - interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; - clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; - resets = <&cpg R9A07G044_OSTM2_PRESETZ>; - power-domains = <&cpg>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsu 0>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor_crit: sensor-crit { - temperature = <125000>; - hysteresis = <1000>; - type = "critical"; - }; - - target: trip-point { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts b/arch/arm/dts/r9a07g044l2-smarc.dts deleted file mode 100644 index 568d49cfe44..00000000000 --- a/arch/arm/dts/r9a07g044l2-smarc.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2L SMARC EVK board - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; - -/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - -/* - * To enable MTU3a PWM on PMOD0, - * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and - * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. - */ -#define PMOD_MTU3 0 - -#if (PMOD_MTU3 && PMOD1_SER0) -#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " -#endif - -#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 - -#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) -#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" -#endif - -#include "r9a07g044l2.dtsi" -#include "rzg2l-smarc-som.dtsi" -#include "rzg2l-smarc-pinfunction.dtsi" -#include "rz-smarc-common.dtsi" -#include "rzg2l-smarc.dtsi" - -/ { - model = "Renesas SMARC EVK based on r9a07g044l2"; - compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044"; -}; diff --git a/arch/arm/dts/r9a07g044l2.dtsi b/arch/arm/dts/r9a07g044l2.dtsi deleted file mode 100644 index 91dc10b2cdb..00000000000 --- a/arch/arm/dts/r9a07g044l2.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044l2", "renesas,r9a07g044"; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi new file mode 100644 index 00000000000..2ab32cf00a1 --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rk3328-nanopi-r2s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi b/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi new file mode 100644 index 00000000000..19acbceb468 --- /dev/null +++ b/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 Heiko Stuebner <heiko@sntech.de> + */ + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi new file mode 100644 index 00000000000..5a3073d6e7f --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +/* USB A out */ +&usb_host1_xhci { + snps,dis_u3_susphy_quirk; +}; diff --git a/arch/arm/dts/rz-smarc-common.dtsi b/arch/arm/dts/rz-smarc-common.dtsi deleted file mode 100644 index b7a3e6caa38..00000000000 --- a/arch/arm/dts/rz-smarc-common.dtsi +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts - * - * Copyright (C) 2022 Renesas Electronics Corp. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> - -/* - * SSI-WM8978 - * - * This command is required when Playback/Capture - * - * amixer cset name='Left Input Mixer L2 Switch' on - * amixer cset name='Right Input Mixer R2 Switch' on - * amixer cset name='Headphone Playback Volume' 100 - * amixer cset name='PCM Volume' 100% - * amixer cset name='Input PGA Volume' 25 - * - */ - -/ { - aliases { - serial0 = &scif0; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - snd_rzg2l: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&cpu_dai>; - simple-audio-card,frame-master = <&cpu_dai>; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,widgets = "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "L2", "Mic Bias", - "R2", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - cpu_dai: simple-audio-card,cpu { - }; - - codec_dai: simple-audio-card,codec { - clocks = <&versa3 2>; - sound-dai = <&wm8978>; - }; - }; - - usb0_vbus_otg: regulator-usb0-vbus-otg { - compatible = "regulator-fixed"; - - regulator-name = "USB0_VBUS_OTG"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - x1: x1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; -}; - -&audio_clk1 { - clock-frequency = <11289600>; -}; - -&audio_clk2 { - clock-frequency = <12288000>; -}; - -&canfd { - pinctrl-0 = <&can0_pins &can1_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; - - channel1 { - status = "okay"; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&phyrst { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi1>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&spi1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&usb0_vbus_otg>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi deleted file mode 100644 index 18c526c7a4c..00000000000 --- a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> - -&pinctrl { - pinctrl-0 = <&sound_clk_pins>; - pinctrl-names = "default"; - - can0_pins: can0 { - pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */ - <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */ - }; - - /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ - can0-stb-hog { - gpio-hog; - gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>; - output-low; - line-name = "can0_stb"; - }; - - can1_pins: can1 { - pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */ - <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */ - }; - - /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ - can1-stb-hog { - gpio-hog; - gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>; - output-low; - line-name = "can1_stb"; - }; - - i2c0_pins: i2c0 { - pins = "RIIC0_SDA", "RIIC0_SCL"; - input-enable; - }; - - i2c1_pins: i2c1 { - pins = "RIIC1_SDA", "RIIC1_SCL"; - input-enable; - }; - - i2c3_pins: i2c3 { - pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */ - <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ - }; - - mtu3_pins: mtu3 { - mtu3-ext-clk-input-pin { - pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */ - <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */ - }; - - mtu3-pwm { - pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ - <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ - <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ - <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ - }; - -#if MTU3_COUNTER_Z_PHASE_SIGNAL - mtu3-zphase-clk { - pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */ - }; -#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ - }; - - scif0_pins: scif0 { - pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ - <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ - }; - - scif2_pins: scif2 { - pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */ - <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */ - <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */ - <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */ - }; - - sd1-pwr-en-hog { - gpio-hog; - gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "sd1_pwr_en"; - }; - - sdhi1_pins: sd1 { - sd1_data { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; - power-source = <3300>; - }; - - sd1_ctrl { - pins = "SD1_CLK", "SD1_CMD"; - power-source = <3300>; - }; - - sd1_mux { - pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ - }; - }; - - sdhi1_pins_uhs: sd1_uhs { - sd1_data_uhs { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; - power-source = <1800>; - }; - - sd1_ctrl_uhs { - pins = "SD1_CLK", "SD1_CMD"; - power-source = <1800>; - }; - - sd1_mux_uhs { - pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ - }; - }; - - sound_clk_pins: sound_clk { - pins = "AUDIO_CLK1", "AUDIO_CLK2"; - input-enable; - }; - - spi1_pins: spi1 { - pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ - <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ - <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ - <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ - }; - - ssi0_pins: ssi0 { - pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ - <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ - <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */ - <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */ - }; - - usb0_pins: usb0 { - pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */ - <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */ - <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */ - }; - - usb1_pins: usb1 { - pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */ - <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */ - }; -}; - diff --git a/arch/arm/dts/rzg2l-smarc-som.dtsi b/arch/arm/dts/rzg2l-smarc-som.dtsi deleted file mode 100644 index 547859c388c..00000000000 --- a/arch/arm/dts/rzg2l-smarc-som.dtsi +++ /dev/null @@ -1,371 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> -#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> - -/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ -#define EMMC 1 - -/* - * To enable uSD card on CN3, - * SW1[2] should be at position 3/ON. - * Disable eMMC by setting "#define EMMC 0" above. - */ -#define SDHI (!EMMC) - -/ { - aliases { - ethernet0 = ð0; - ethernet1 = ð1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p1v: regulator-vdd-core { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - states = <3300000 1>, <1800000 0>; - regulator-boot-on; - gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - /* 32.768kHz crystal */ - x2: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; -}; - -&adc { - pinctrl-0 = <&adc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /delete-node/ channel@6; - /delete-node/ channel@7; -}; - -ð0 { - pinctrl-0 = <ð0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy0: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; - reg = <7>; - interrupt-parent = <&irqc>; - interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; - rxc-skew-psec = <2400>; - txc-skew-psec = <2400>; - rxdv-skew-psec = <0>; - txen-skew-psec = <0>; - rxd0-skew-psec = <0>; - rxd1-skew-psec = <0>; - rxd2-skew-psec = <0>; - rxd3-skew-psec = <0>; - txd0-skew-psec = <0>; - txd1-skew-psec = <0>; - txd2-skew-psec = <0>; - txd3-skew-psec = <0>; - }; -}; - -ð1 { - pinctrl-0 = <ð1_pins>; - pinctrl-names = "default"; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy1: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; - reg = <7>; - interrupt-parent = <&irqc>; - interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>; - rxc-skew-psec = <2400>; - txc-skew-psec = <2400>; - rxdv-skew-psec = <0>; - txen-skew-psec = <0>; - rxd0-skew-psec = <0>; - rxd1-skew-psec = <0>; - rxd2-skew-psec = <0>; - rxd3-skew-psec = <0>; - txd0-skew-psec = <0>; - txd1-skew-psec = <0>; - txd2-skew-psec = <0>; - txd3-skew-psec = <0>; - }; -}; - -&extal_clk { - clock-frequency = <24000000>; -}; - -&gpu { - mali-supply = <®_1p1v>; -}; - -&i2c3 { - raa215300: pmic@12 { - compatible = "renesas,raa215300"; - reg = <0x12>, <0x6f>; - reg-names = "main", "rtc"; - - clocks = <&x2>; - clock-names = "xin"; - }; -}; - -&ostm1 { - status = "okay"; -}; - -&ostm2 { - status = "okay"; -}; - -&pinctrl { - adc_pins: adc { - pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */ - }; - - eth0_pins: eth0 { - pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ - <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ - <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ - <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ - <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ - <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ - <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ - <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ - <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ - <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ - <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ - <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ - <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ - <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ - <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ - }; - - eth1_pins: eth1 { - pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */ - <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ - <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ - <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */ - <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ - <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ - <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ - <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ - <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ - <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ - <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ - <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ - <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ - <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ - <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ - }; - - gpio-sd0-pwr-en-hog { - gpio-hog; - gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "gpio_sd0_pwr_en"; - }; - - qspi0_pins: qspi0 { - qspi0-data { - pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; - power-source = <1800>; - }; - - qspi0-ctrl { - pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; - power-source = <1800>; - }; - }; - - /* - * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] - * The below switch logic can be used to select the device between - * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. - * SW1[2] should be at position 2/OFF to enable 64 GB eMMC - * SW1[2] should be at position 3/ON to enable uSD card CN3 - */ - sd0-dev-sel-hog { - gpio-hog; - gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "sd0_dev_sel"; - }; - - sdhi0_emmc_pins: sd0emmc { - sd0_emmc_data { - pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", - "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; - power-source = <1800>; - }; - - sd0_emmc_ctrl { - pins = "SD0_CLK", "SD0_CMD"; - power-source = <1800>; - }; - - sd0_emmc_rst { - pins = "SD0_RST#"; - power-source = <1800>; - }; - }; - - sdhi0_pins: sd0 { - sd0_data { - pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; - power-source = <3300>; - }; - - sd0_ctrl { - pins = "SD0_CLK", "SD0_CMD"; - power-source = <3300>; - }; - - sd0_mux { - pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */ - }; - }; - - sdhi0_pins_uhs: sd0_uhs { - sd0_data_uhs { - pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; - power-source = <1800>; - }; - - sd0_ctrl_uhs { - pins = "SD0_CLK", "SD0_CMD"; - power-source = <1800>; - }; - - sd0_mux_uhs { - pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */ - }; - }; -}; - -&sbc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - compatible = "micron,mt25qu512a", "jedec,spi-nor"; - reg = <0>; - m25p,fast-read; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - reg = <0x00000000 0x2000000>; - read-only; - }; - user@2000000 { - reg = <0x2000000 0x2000000>; - }; - }; - }; -}; - -#if SDHI -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; -#endif - -#if EMMC -&sdhi0 { - pinctrl-0 = <&sdhi0_emmc_pins>; - pinctrl-1 = <&sdhi0_emmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; -#endif - -&wdt0 { - status = "okay"; - timeout-sec = <60>; -}; - -&wdt1 { - status = "okay"; - timeout-sec = <60>; -}; diff --git a/arch/arm/dts/rzg2l-smarc.dtsi b/arch/arm/dts/rzg2l-smarc.dtsi deleted file mode 100644 index 37807f1bda4..00000000000 --- a/arch/arm/dts/rzg2l-smarc.dtsi +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> - -/ { - aliases { - serial1 = &scif2; - i2c3 = &i2c3; - }; - - osc1: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "d"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7535_out>; - }; - }; - }; -}; - -&cpu_dai { - sound-dai = <&ssi0>; -}; - -&dsi { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&adv7535_in>; - }; - }; - }; -}; - -&i2c1 { - adv7535: hdmi@3d { - compatible = "adi,adv7535"; - reg = <0x3d>; - - interrupt-parent = <&pinctrl>; - interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>; - clocks = <&osc1>; - clock-names = "cec"; - avdd-supply = <®_1p8v>; - dvdd-supply = <®_1p8v>; - pvdd-supply = <®_1p8v>; - a2vdd-supply = <®_1p8v>; - v3p3-supply = <®_3p3v>; - v1p2-supply = <®_1p8v>; - - adi,dsi-lanes = <4>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7535_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7535_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; - - versa3: clock-generator@68 { - compatible = "renesas,5p35023"; - reg = <0x68>; - #clock-cells = <1>; - clocks = <&x1>; - - renesas,settings = [ - 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf - 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 - 80 b0 45 c4 95 - ]; - - assigned-clocks = <&versa3 0>, <&versa3 1>, - <&versa3 2>, <&versa3 3>, - <&versa3 4>, <&versa3 5>; - assigned-clock-rates = <24000000>, <11289600>, - <11289600>, <12000000>, - <25000000>, <12288000>; - }; -}; - -#if PMOD_MTU3 -&mtu3 { - pinctrl-0 = <&mtu3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -#if MTU3_COUNTER_Z_PHASE_SIGNAL -/* SDHI cd pin is muxed with counter Z phase signal */ -&sdhi1 { - status = "disabled"; -}; -#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ - -&spi1 { - status = "disabled"; -}; -#endif /* PMOD_MTU3 */ - -/* - * To enable SCIF2 (SER0) on PMOD1 (CN7) - * SW1 should be at position 2->3 so that SER0_CTS# line is activated - * SW2 should be at position 2->3 so that SER0_TX line is activated - * SW3 should be at position 2->3 so that SER0_RX line is activated - * SW4 should be at position 2->3 so that SER0_RTS# line is activated - */ -#if PMOD1_SER0 -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; -#endif - -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&vccq_sdhi1 { - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/mach-renesas/include/mach/rzg2l.h b/arch/arm/mach-renesas/include/mach/rzg2l.h index 057df5cb9d4..c49a71a6dd4 100644 --- a/arch/arm/mach-renesas/include/mach/rzg2l.h +++ b/arch/arm/mach-renesas/include/mach/rzg2l.h @@ -8,6 +8,6 @@ #define __ASM_ARCH_RZG2L_H #define GICD_BASE 0x11900000 -#define GICR_BASE 0x11960000 +#define GICR_BASE 0x11940000 #endif /* __ASM_ARCH_RZG2L_H */ diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index edccb2a3980..0c28241c603 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -169,15 +169,36 @@ void board_debug_uart_init(void) } #endif -#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) +#if defined(CONFIG_TPL_BUILD) static void rk3399_force_power_on_reset(void) { + const struct rockchip_cru *cru = rockchip_get_cru(); ofnode node; struct gpio_desc sysreset_gpio; - if (!IS_ENABLED(CONFIG_SPL_GPIO)) { + /* + * The RK3399 resets only 'almost all logic' (see also in the + * TRM "3.9.4 Global software reset"), when issuing a software + * reset. This may cause issues during boot-up for some + * configurations of the application software stack. + * + * To work around this, we test whether the last reset reason + * was a power-on reset and (if not) issue an overtemp-reset to + * reset the entire module. + * + * While this was previously fixed by modifying the various + * places that could generate a software reset (e.g. U-Boot's + * sysreset driver, the ATF or Linux), we now have it here to + * ensure that we no longer have to track this through the + * various components. + */ + if (cru->glb_rst_st == 0) + return; + + if (!IS_ENABLED(CONFIG_TPL_GPIO)) { debug("%s: trying to force a power-on reset but no GPIO " - "support in SPL!\n", __func__); + "support in TPL!\n", __func__); return; } @@ -198,6 +219,11 @@ static void rk3399_force_power_on_reset(void) dm_gpio_set_value(&sysreset_gpio, 1); } +void tpl_board_init(void) +{ + rk3399_force_power_on_reset(); +} +# else void __weak led_setup(void) { } @@ -205,28 +231,6 @@ void __weak led_setup(void) void spl_board_init(void) { led_setup(); - - if (IS_ENABLED(CONFIG_SPL_GPIO)) { - struct rockchip_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the - * TRM "3.9.4 Global software reset"), when issuing a software - * reset. This may cause issues during boot-up for some - * configurations of the application software stack. - * - * To work around this, we test whether the last reset reason - * was a power-on reset and (if not) issue an overtemp-reset to - * reset the entire module. - * - * While this was previously fixed by modifying the various - * places that could generate a software reset (e.g. U-Boot's - * sysreset driver, the ATF or Linux), we now have it here to - * ensure that we no longer have to track this through the - * various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); - } } #endif +#endif diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index e646f714c92..ce327ed6f9e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -32,6 +32,19 @@ config TARGET_POWKIDDY_X55_RK3566 help Powkiddy X55 handheld gaming console with an RK3566 SoC. +config TARGET_QNAP_TS433_RK3568 + bool "QNAP-TS433" + help + Qnap TS433 4-bay NAS with a RK3568 SoC. + + It provides the following featureset: + * 4GB LPDDR4 + * 4GB eMMC + * 2 SATA ports connected to two RK3568's SATA controllers + * 2 SATA ports connected to a JMicron JMB58x AHCI SATA controller + * 1 1G network controller + * 1 2.5G Realtek RTL8125 network controller + config TARGET_QUARTZ64_RK3566 bool "Pine64 Quartz64" help @@ -70,6 +83,7 @@ source "board/hardkernel/odroid_m1/Kconfig" source "board/hardkernel/odroid_m1s/Kconfig" source "board/pine64/quartz64_rk3566/Kconfig" source "board/powkiddy/x55/Kconfig" +source "board/qnap/ts433/Kconfig" source "board/radxa/zero3-rk3566/Kconfig" source "board/xunlong/orangepi-3b-rk3566/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 6f28a313325..b5a0e624a53 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -29,6 +29,24 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GENBOOK_CM5_RK3588 + bool "Cool Pi CM5 GenBook" + select BOARD_LATE_INIT + help + GeenBook is a notebook based on Rockchip RK3588, and works as a carrier + board connect with CM5 SOM. + + Specification: + - Rockchip RK3588 + - LPDDR5X 8/32 GB + - eMMC 64 GB + - HDMI Type A out x 1 + - USB 3.0 Host x 1 + - USB-C 3.0 with DisplayPort AltMode + - PCIE M.2 E Key for RTL8852BE Wireless connection + - PCIE M.2 M Key for NVME connection + - eDP panel with 1920x1080 + config TARGET_JAGUAR_RK3588 bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" select BOARD_LATE_INIT @@ -367,6 +385,7 @@ config TEXT_BASE default 0x00a00000 source "board/armsom/sige7-rk3588/Kconfig" +source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index bbb9329e725..6b880f19f84 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -21,6 +21,10 @@ #include <timestamp.h> #endif +__weak void tpl_board_init(void) +{ +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -54,6 +58,8 @@ void board_init_f(ulong dummy) if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER)) timer_init(); + tpl_board_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { printf("DRAM init failed: %d\n", ret); diff --git a/board/coolpi/genbook_cm5_rk3588/Kconfig b/board/coolpi/genbook_cm5_rk3588/Kconfig new file mode 100644 index 00000000000..67086ea6297 --- /dev/null +++ b/board/coolpi/genbook_cm5_rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENBOOK_CM5_RK3588 + +config SYS_BOARD + default "genbook_cm5_rk3588" + +config SYS_VENDOR + default "coolpi" + +config SYS_CONFIG_NAME + default "genbook-cm5-rk3588" + +endif diff --git a/board/coolpi/genbook_cm5_rk3588/MAINTAINERS b/board/coolpi/genbook_cm5_rk3588/MAINTAINERS new file mode 100644 index 00000000000..0496cc93b59 --- /dev/null +++ b/board/coolpi/genbook_cm5_rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +GENBOOK-CM5-RK3588 +M: Andy Yan <andyshrk@163.com> +S: Maintained +F: board/coolpi/genbook-cm5-rk3588 +F: include/configs/genbook-cm5-rk3588.h +F: configs/coolpi-cm5-genbook-rk3588_defconfig +F: arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 0966e257464..8b635ef71ac 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -96,15 +96,15 @@ static bool is_hoperun_hihope_rzg2_board(const char *board_name) int board_fit_config_name_match(const char *name) { if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") && - !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot")) + !strcmp(name, "r8a774a1-hihope-rzg2m-ex")) return 0; if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") && - !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot")) + !strcmp(name, "r8a774b1-hihope-rzg2n-ex")) return 0; if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") && - !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot")) + !strcmp(name, "r8a774e1-hihope-rzg2h-ex")) return 0; return -1; diff --git a/board/qnap/ts433/Kconfig b/board/qnap/ts433/Kconfig new file mode 100644 index 00000000000..b00e1f9f2ef --- /dev/null +++ b/board/qnap/ts433/Kconfig @@ -0,0 +1,12 @@ +if TARGET_QNAP_TS433_RK3568 + +config SYS_BOARD + default "qnap_ts433" + +config SYS_VENDOR + default "qnap" + +config SYS_CONFIG_NAME + default "qnap_ts433" + +endif diff --git a/board/qnap/ts433/MAINTAINERS b/board/qnap/ts433/MAINTAINERS new file mode 100644 index 00000000000..c2b31ad9794 --- /dev/null +++ b/board/qnap/ts433/MAINTAINERS @@ -0,0 +1,8 @@ +QNAP-TS433 +M: Heiko Stuebner <heiko@sntech.de> +S: Maintained +F: board/qnap/ts433/ +F: doc/board/qnap/ +F: include/configs/qnap_ts433.h +F: configs/qnap-ts433-rk3568_defconfig +F: arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi diff --git a/board/renesas/rzg2l/MAINTAINERS b/board/renesas/rzg2l/MAINTAINERS index 0a51391c1fc..0e656e2ef4f 100644 --- a/board/renesas/rzg2l/MAINTAINERS +++ b/board/renesas/rzg2l/MAINTAINERS @@ -1,6 +1,6 @@ RENESAS RZG2L BOARD FAMILY M: Paul Barker <paul.barker.ct@bp.renesas.com> S: Supported -F: arch/arm/dts/rz-smarc-common.dtsi +N: rz-smarc N: rzg2l N: r9a07g044 diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 8f619e54e0e..5f81be55b8e 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -28,6 +28,12 @@ F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi F: arch/arm/dts/rk3328-nanopi-r2s.dts +NANOPI-R2S-PLUS-RK3328 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/nanopi-r2s-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi + ORANGEPI-R1-PLUS-RK3328 M: Tianling Shen <cnsztl@gmail.com> S: Maintained diff --git a/configs/coolpi-cm5-genbook-rk3588_defconfig b/configs/coolpi-cm5-genbook-rk3588_defconfig new file mode 100644 index 00000000000..3eb5dc968af --- /dev/null +++ b/configs/coolpi-cm5-genbook-rk3588_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-coolpi-cm5-genbook" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_GENBOOK_CM5_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-genbook.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +# CONFIG_CMD_BIND is not set +# CONFIG_CMD_FASTBOOT is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index 1d06f3411fe..f79f0e84400 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -31,6 +30,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index ebe883ed597..51e31dce3a9 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -18,13 +18,13 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 6266f3cbc56..c9753e13657 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -8,23 +8,23 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_TEXT_BASE=0x50000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 -CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m" +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m-ex" CONFIG_TARGET_HIHOPE_RZG2=y # CONFIG_SPL is not set CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000" -CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb" +CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m-ex.dtb; booti 0x48080000 - 0x48000000" +CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m-ex.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_USB=y -CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m renesas/r8a774b1-hihope-rzg2n renesas/r8a774e1-hihope-rzg2h" +CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m-ex renesas/r8a774b1-hihope-rzg2n-ex renesas/r8a774e1-hihope-rzg2h-ex" CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=0 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y diff --git a/configs/nanopi-r2s-plus-rk3328_defconfig b/configs/nanopi-r2s-plus-rk3328_defconfig new file mode 100644 index 00000000000..6e6785fcc88 --- /dev/null +++ b/configs/nanopi-r2s-plus-rk3328_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2s-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 67c0ee72c92..7a180b14130 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set @@ -78,6 +79,8 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_TPL_PINCTRL=y +CONFIG_TPL_PINCTRL_FULL=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_PMIC_RK8XX=y diff --git a/configs/qnap-ts433-rk3568_defconfig b/configs/qnap-ts433-rk3568_defconfig new file mode 100644 index 00000000000..840da7f3759 --- /dev/null +++ b/configs/qnap-ts433-rk3568_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-qnap-ts433" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_QNAP_TS433_RK3568=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-qnap-ts433.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/coolpi/genbook_cm5_rk3588.rst b/doc/board/coolpi/genbook_cm5_rk3588.rst new file mode 100644 index 00000000000..a02e561051a --- /dev/null +++ b/doc/board/coolpi/genbook_cm5_rk3588.rst @@ -0,0 +1,68 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +GenBook +======= +Cool Pi GenBook is a laptop powered by RK3588, it works with a +carrier board connect with CM5. + +Specification: +* Rockchip RK3588 +* LPDDR5X 8/32 GB +* eMMC 64 GB +* SPI Nor 8 MB +* HDMI Type A out x 1 +* USB 3.0 Host x 1 +* USB-C 3.0 with DisplayPort AltMode +* PCIE M.2 E Key for RTL8852BE Wireless connection +* PCIE M.2 M Key for NVME connection +* eDP panel with 1920x1080 + +Here is the step-by-step to compile and boot to U-Boot on GenBook. + +Get the TF-A and DDR init (TPL) binaries +---------------------------------------- + +.. prompt:: bash + + > cd u-boot + > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin + > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf + > make coolpi-genbook-cm5-rk3588_defconfig + > make CROSS_COMPILE=aarch64-linux-gnu- + +This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor. + +Write u-boot to eMMC or SPI Nor from a Linux system on the laptop +----------------------------------------------------------------- + +Copy ``u-boot-rockchip.bin`` and ``u-boot-rockchip-spi.bin`` to the laptop. + +eMMC +~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip.bin of=/dev/mmcblk0 bs=512 seek=64 + +SPI Nor +~~~~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip-spi.bin of=/dev/mtdblock0 + +``upgrade_tool`` allows to flash the on-board SPI Nor via the USB TypeC interface +with help of the Rockchip loader binary. + +To enter the USB flashing mode, connect the laptop and your HOST PC with a USB-C +cable, reset the laptop with ``Loader Key`` pressed. +On your PC, check with ``lsusb -d 2207:350b``). + +To flash U-Boot on the SPI Nor with ``upgrade_tool``: + +.. prompt:: bash + + upgrade_tool db rk3588/MiniLoaderAll.bin + upgrade_tool ssd // Input 5 for SPINOR download mode + upgrade_tool wl 0 u-boot-rockchip-spi.bin + upgrade_tool rd diff --git a/doc/board/coolpi/index.rst b/doc/board/coolpi/index.rst new file mode 100644 index 00000000000..9c9593fd6aa --- /dev/null +++ b/doc/board/coolpi/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Cool Pi +================= + +.. toctree:: + :maxdepth: 2 + + genbook_cm5_rk3588 diff --git a/doc/board/index.rst b/doc/board/index.rst index ca5246e259c..b54c1748d57 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -23,6 +23,7 @@ Board-specific doc bsh/index cloos/index congatec/index + coolpi/index coreboot/index emcraft/index emulation/index @@ -43,6 +44,7 @@ Board-specific doc phytec/index purism/index qualcomm/index + qnap/index renesas/index rockchip/index samsung/index diff --git a/doc/board/qnap/index.rst b/doc/board/qnap/index.rst new file mode 100644 index 00000000000..652ea11a056 --- /dev/null +++ b/doc/board/qnap/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Qnap +==== + +.. toctree:: + :maxdepth: 2 + + ts433.rst diff --git a/doc/board/qnap/ts433.rst b/doc/board/qnap/ts433.rst new file mode 100644 index 00000000000..1e1bfbb9190 --- /dev/null +++ b/doc/board/qnap/ts433.rst @@ -0,0 +1,91 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Qnap TS433 Devices +================================= + +This allows U-Boot to boot the Qnap TS433 NAS + +Preparing the serial +-------------------- + +Qnap devices run their serial console with a 115200 baudrate. As the +binary DDR-init and maskrom-downloader expect a 1500000 rate, it is +necessary to adapt the binaries if their output is needed. + +This can be done with a binary provided in the rkbin repository. +First the ddrbin_param.txt in the rkbin repo needs to be modified: + +.. code-block:: bash + + diff --git a/tools/ddrbin_param.txt b/tools/ddrbin_param.txt + index 0dfdd318..82ade7e7 100644 + --- a/tools/ddrbin_param.txt + +++ b/tools/ddrbin_param.txt + @@ -11,7 +11,7 @@ lp5_freq= + + uart id= + uart iomux= + -uart baudrate= + +uart baudrate=115200 + + sr_idle= + pd_idle= + +And after that the ddrbin_tool binary can be used to modify apply this +modification and also a new maskrom downloader can be build: + +.. code-block:: bash + + $ tools/ddrbin_tool rk3568 tools/ddrbin_param.txt bin/rk35/rk3568_ddr_1560MHz_v1.21.bin + $ tools/boot_merger RKBOOT/RK3568MINIALL.ini + +Building U-Boot +--------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-linux-gnu- + $ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf + $ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin + $ make qnap-ts433-rk3568_defconfig + $ make + +This will build ``u-boot-rockchip.bin`` which can be written to the +on-board eMMC. + +Image installation +------------------ + +The Qnap thankfully provides an easily accessible serial header as well as +a very user-friendly jumper-header to bring the device into maskrom mode. + +To access both, the drive trays need to be removed. Looking at the board, +through the upper cutout of the metal frame the white 4-port serial-header +can be seen next to a barcode sticker. It's pinout is as follows: + +.. code-block:: none + + ,_ _. + |1234| 1=TX 2=VCC + `----' 3=RX 4=GND + + +Directly below it, the mentioned 2-pin jumper header can be seen. + +To write your u-boot to the device, it needs to be powered off first. Then +a jumper or suitable cable needs to be used to connect the two pins of the +maskrom header. Turning on the device now will start it in maskrom mode. + +It is important that the jumper gets removed after that stop and before +actually trying to write to the emmc. + +The front usb-port needs to be connected to the host with an USB-A-to-A +cable to allow flashing. + +The flashing itself is done via rkdeveloptool, which can be found for +example as package of that name in Debian-based distributions: + +.. code-block:: bash + + $ rkdeveloptool db rk356x_spl_loader_v1.21.113.bin + $ rkdeveloptool wl 64 u-boot-rockchip.bin diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 7b11a2e0a35..9bab86d2347 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -65,6 +65,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R2C (nanopi-r2c-rk3328) - FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328) - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328) + - FriendlyElec NanoPi R2S Plus (nanopi-r2s-plus-rk3328) - Pine64 Rock64 (rock64-rk3328) - Radxa ROCK Pi E (rock-pi-e-rk3328) - Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328) @@ -119,6 +120,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568) - Generic RK3566/RK3568 (generic-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - QNAP TS-433 (qnap-ts433-rk3568) - Radxa E25 Carrier Board (radxa-e25-rk3568) - Radxa ROCK 3A (rock-3a-rk3568) - Radxa ROCK 3B (rock-3b-rk3568) @@ -147,6 +149,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) + - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588) * rv1108 - Rockchip Evb-rv1108 (evb-rv1108) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a1d53cfbdbe..6ee7dc1cce8 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -127,6 +127,14 @@ config SPL_PINCTRL_GENERIC This option is an SPL-variant of the PINCTRL_GENERIC option. See the help of PINCTRL_GENERIC for details. +config TPL_PINCTRL_GENERIC + bool "Support generic pin controllers in TPL" + depends on TPL_PINCTRL_FULL + default y + help + This option is a TPL-variant of the PINCTRL_GENERIC option. + See the help of PINCTRL_GENERIC for details. + config SPL_PINMUX bool "Support pin multiplexing controllers in SPL" depends on SPL_PINCTRL_GENERIC diff --git a/drivers/pinctrl/rockchip/Kconfig b/drivers/pinctrl/rockchip/Kconfig index dc4ba34ae5d..8aa9dcac358 100644 --- a/drivers/pinctrl/rockchip/Kconfig +++ b/drivers/pinctrl/rockchip/Kconfig @@ -14,4 +14,11 @@ config SPL_PINCTRL_ROCKCHIP help This option is an SPL-variant of the PINCTRL_ROCKCHIP option. +config TPL_PINCTRL_ROCKCHIP + bool "Support Rockchip pin controllers in TPL" + depends on ARCH_ROCKCHIP && TPL_PINCTRL_GENERIC + default y + help + This option is a TPL-variant of the PINCTRL_ROCKCHIP option. + endif diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 4aad3248d9e..e43dbb40c4a 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -813,7 +813,7 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, priv->is_parallel = false; priv->is_stacked = false; - slave->flags &= ~SPI_XFER_MASK; + slave->flags &= ~SPI_XFER_LOWER; spi_release_bus(slave); return 0; diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 1d19b2606c5..4251bf28cd3 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -870,8 +870,8 @@ static int zynqmp_qspi_exec_op(struct spi_slave *slave, priv->bus = 0; if (priv->is_parallel) { - if (slave->flags & SPI_XFER_MASK) - priv->bus = (slave->flags & SPI_XFER_MASK) >> 8; + if (slave->flags & SPI_XFER_LOWER) + priv->bus = 1; if (zynqmp_qspi_update_stripe(op)) priv->stripe = 1; } @@ -890,7 +890,7 @@ static int zynqmp_qspi_exec_op(struct spi_slave *slave, zynqmp_qspi_chipselect(priv, 0); priv->is_parallel = false; - slave->flags &= ~SPI_XFER_MASK; + slave->flags &= ~SPI_XFER_LOWER; return ret; } diff --git a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s-plus.dts b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s-plus.dts new file mode 100644 index 00000000000..cb81ba3f23f --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s-plus.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3328-nanopi-r2s.dts" + +/ { + compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328"; + model = "FriendlyElec NanoPi R2S Plus"; + + aliases { + mmc1 = &emmc; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-hs200-1_8v; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + supports-emmc; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts index 6a998166003..e601d9271ba 100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -6,12 +6,190 @@ /dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> #include "rk3568.dtsi" / { model = "Qnap TS-433-4G NAS System 4-Bay"; compatible = "qnap,ts433", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdhci; + rtc0 = &rtc_rv8263; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + pinctrl-names = "default"; + + key-copy { + label = "copy"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_COPY>; + }; + + key-reset { + label = "reset"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_led_pin>; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd2_led_pin>; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd3_led_pin>; + }; + + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd4_led_pin>; + }; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_otg: regulator-vcc5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; +}; + +/* connected to usb_host0_xhci */ +&combphy0 { + status = "okay"; +}; + +/* connected to sata1 */ +&combphy1 { + status = "okay"; +}; + +/* connected to sata2 */ +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &gmac0 { @@ -20,35 +198,282 @@ assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus>; - rx_delay = <0x2f>; - tx_delay = <0x3c>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; status = "okay"; }; &i2c0 { + status = "okay"; + pmic@20 { compatible = "rockchip,rk809"; reg = <0x20>; interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + /* + * turning this off, breaks access to both + * PCIe controllers, refclk generator perhaps + */ + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; }; }; &i2c1 { status = "okay"; - rtc@51 { + rtc_rv8263: rtc@51 { compatible = "microcrystal,rv8263"; reg = <0x51>; wakeup-source; }; + + /* eeprom for vital-product-data on the mainboard */ + eeprom@54 { + compatible = "giantec,gt24c04a", "atmel,24c04"; + reg = <0x54>; + label = "VPD_MB"; + num-addresses = <2>; + pagesize = <16>; + read-only; + }; + + /* eeprom for vital-product-data on the backplane */ + eeprom@56 { + compatible = "giantec,gt24c04a", "atmel,24c04"; + reg = <0x56>; + label = "VPD_BP"; + num-addresses = <2>; + pagesize = <16>; + read-only; + }; }; &mdio0 { @@ -59,12 +484,82 @@ }; &pcie30phy { + data-lanes = <1 2>; status = "okay"; }; +/* Connected to a JMicron AHCI SATA controller */ &pcie3x1 { - /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +/* Connected to the 2.5G NIC for the upper network jack */ +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + keys { + copy_button_pin: copy-button-pin { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + hdd1_led_pin: hdd1-led-pin { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd2_led_pin: hdd2-led-pin { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd3_led_pin: hdd3-led-pin { + rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd4_led_pin: hdd4_led-pin { + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio4-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { status = "okay"; }; @@ -75,6 +570,20 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* + * Connected to an MCU, that provides access to more LEDs, + * buzzer, fan control and more. + */ +&uart0 { + status = "okay"; +}; + /* * Pins available on CN3 connector at TTL voltage level (3V3). * ,_ _. @@ -84,3 +593,53 @@ &uart2 { status = "okay"; }; + +&usb2phy0 { + status = "okay"; +}; + +/* connected to usb_host0_xhci */ +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +/* connected to usb_host1_ehci/ohci */ +&usb2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +/* connected to usb_host0_ehci/ohci */ +&usb2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +/* right port backside */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* front port */ +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* left port backside */ +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts new file mode 100644 index 00000000000..6418286efe4 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "rk3588-coolpi-cm5.dtsi" + +/ { + model = "CoolPi CM5 GenBook"; + compatible = "coolpi,pi-cm5-genbook", "coolpi,pi-cm5", "rockchip,rk3588"; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm6 0 25000 0>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <9800000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3000000>; + }; + + charger: dc-charger { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + }; + + leds: leds { + compatible = "gpio-leds"; + + heartbeat_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + wlan_led: led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + + charging_red: led-2 { + function = LED_FUNCTION_CHARGING; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <7000000>; + regulator-max-microvolt = <7000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <7000000>; + regulator-max-microvolt = <7000000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lcd: vcc3v3-lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcdpwr_en>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pwren>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_usb_host0: vcc5v0_usb30_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + cw2015@62 { + compatible = "cellwise,cw2015"; + reg = <0x62>; + + cellwise,battery-profile = /bits/ 8 < + 0x17 0x67 0x69 0x63 0x63 0x62 0x62 0x5F + 0x52 0x73 0x4C 0x5A 0x5B 0x4B 0x42 0x3A + 0x33 0x2D 0x29 0x28 0x2E 0x31 0x3C 0x49 + 0x2C 0x2C 0x0C 0xCD 0x30 0x51 0x50 0x66 + 0x74 0x74 0x75 0x78 0x41 0x1B 0x84 0x5F + 0x0B 0x34 0x1C 0x45 0x89 0x92 0xA0 0x13 + 0x2C 0x55 0xAB 0xCB 0x80 0x5E 0x7B 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x10 0x18 0x21 + >; + + cellwise,monitor-interval-ms = <3000>; + monitored-battery = <&battery>; + power-supplies = <&charger>; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + + touchpad: touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PD6 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0020>; + }; +}; + +&gmac0 { + status = "disabled"; +}; + +/* M.2 E-Key */ +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; + status = "okay"; +}; + +&pcie2x1l2 { + status = "disabled"; +}; + +&pcie30phy { + status = "okay"; +}; + +/* M.2 M-Key ssd */ +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pinctrl { + lcd { + lcdpwr_en: lcdpwr-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bl_en: bl-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_pwren: usb-pwren { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_host_pwren: usb-host-pwren { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + bt_pwron: bt-pwron { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_clkreq: pcie-clkreq { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_rst: pcie-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_pwron: wifi-pwron { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_wake: pcie-wake { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm6 { + pinctrl-0 = <&pwm6m1_pins>; + status = "okay"; +}; + +&sdmmc { + status = "disabled"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb_host0>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +/* For Keypad */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* Type C port */ +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +/* connected to a HUB for camera and BT */ +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* USB A out */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; diff --git a/include/configs/genbook-cm5-rk3588.h b/include/configs/genbook-cm5-rk3588.h new file mode 100644 index 00000000000..194f97469df --- /dev/null +++ b/include/configs/genbook-cm5-rk3588.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __GENBOOK_CM5_RK3588_H +#define __GENBOOK_CM5_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* + * As a laptop, there is no sdmmc, and we want to + * set usb the highest boot priority for third-part + * os installation. + */ +#define BOOT_TARGETS "usb mmc0" + +#include <configs/rk3588_common.h> + +#endif /* __GENBOOK_CM5_RK3588_H */ diff --git a/include/configs/qnap_ts433.h b/include/configs/qnap_ts433.h new file mode 100644 index 00000000000..aee4546bf07 --- /dev/null +++ b/include/configs/qnap_ts433.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __QNAP_TS433_H +#define __QNAP_TS433_H + +#define ROCKCHIP_DEVICE_SETTINGS + +#include <configs/rk3568_common.h> + +#endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9b8ab3cdf20..d5550a46575 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -13,7 +13,9 @@ #ifndef CONFIG_XPL_BUILD +#ifndef BOOT_TARGETS #define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi" +#endif #ifdef CONFIG_ARM64 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h deleted file mode 100644 index 0bb17ff1a01..00000000000 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ -#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* R9A07G044 CPG Core Clocks */ -#define R9A07G044_CLK_I 0 -#define R9A07G044_CLK_I2 1 -#define R9A07G044_CLK_G 2 -#define R9A07G044_CLK_S0 3 -#define R9A07G044_CLK_S1 4 -#define R9A07G044_CLK_SPI0 5 -#define R9A07G044_CLK_SPI1 6 -#define R9A07G044_CLK_SD0 7 -#define R9A07G044_CLK_SD1 8 -#define R9A07G044_CLK_M0 9 -#define R9A07G044_CLK_M1 10 -#define R9A07G044_CLK_M2 11 -#define R9A07G044_CLK_M3 12 -#define R9A07G044_CLK_M4 13 -#define R9A07G044_CLK_HP 14 -#define R9A07G044_CLK_TSU 15 -#define R9A07G044_CLK_ZT 16 -#define R9A07G044_CLK_P0 17 -#define R9A07G044_CLK_P1 18 -#define R9A07G044_CLK_P2 19 -#define R9A07G044_CLK_AT 20 -#define R9A07G044_OSCCLK 21 -#define R9A07G044_CLK_P0_DIV2 22 - -/* R9A07G044 Module Clocks */ -#define R9A07G044_CA55_SCLK 0 -#define R9A07G044_CA55_PCLK 1 -#define R9A07G044_CA55_ATCLK 2 -#define R9A07G044_CA55_GICCLK 3 -#define R9A07G044_CA55_PERICLK 4 -#define R9A07G044_CA55_ACLK 5 -#define R9A07G044_CA55_TSCLK 6 -#define R9A07G044_GIC600_GICCLK 7 -#define R9A07G044_IA55_CLK 8 -#define R9A07G044_IA55_PCLK 9 -#define R9A07G044_MHU_PCLK 10 -#define R9A07G044_SYC_CNT_CLK 11 -#define R9A07G044_DMAC_ACLK 12 -#define R9A07G044_DMAC_PCLK 13 -#define R9A07G044_OSTM0_PCLK 14 -#define R9A07G044_OSTM1_PCLK 15 -#define R9A07G044_OSTM2_PCLK 16 -#define R9A07G044_MTU_X_MCK_MTU3 17 -#define R9A07G044_POE3_CLKM_POE 18 -#define R9A07G044_GPT_PCLK 19 -#define R9A07G044_POEG_A_CLKP 20 -#define R9A07G044_POEG_B_CLKP 21 -#define R9A07G044_POEG_C_CLKP 22 -#define R9A07G044_POEG_D_CLKP 23 -#define R9A07G044_WDT0_PCLK 24 -#define R9A07G044_WDT0_CLK 25 -#define R9A07G044_WDT1_PCLK 26 -#define R9A07G044_WDT1_CLK 27 -#define R9A07G044_WDT2_PCLK 28 -#define R9A07G044_WDT2_CLK 29 -#define R9A07G044_SPI_CLK2 30 -#define R9A07G044_SPI_CLK 31 -#define R9A07G044_SDHI0_IMCLK 32 -#define R9A07G044_SDHI0_IMCLK2 33 -#define R9A07G044_SDHI0_CLK_HS 34 -#define R9A07G044_SDHI0_ACLK 35 -#define R9A07G044_SDHI1_IMCLK 36 -#define R9A07G044_SDHI1_IMCLK2 37 -#define R9A07G044_SDHI1_CLK_HS 38 -#define R9A07G044_SDHI1_ACLK 39 -#define R9A07G044_GPU_CLK 40 -#define R9A07G044_GPU_AXI_CLK 41 -#define R9A07G044_GPU_ACE_CLK 42 -#define R9A07G044_ISU_ACLK 43 -#define R9A07G044_ISU_PCLK 44 -#define R9A07G044_H264_CLK_A 45 -#define R9A07G044_H264_CLK_P 46 -#define R9A07G044_CRU_SYSCLK 47 -#define R9A07G044_CRU_VCLK 48 -#define R9A07G044_CRU_PCLK 49 -#define R9A07G044_CRU_ACLK 50 -#define R9A07G044_MIPI_DSI_PLLCLK 51 -#define R9A07G044_MIPI_DSI_SYSCLK 52 -#define R9A07G044_MIPI_DSI_ACLK 53 -#define R9A07G044_MIPI_DSI_PCLK 54 -#define R9A07G044_MIPI_DSI_VCLK 55 -#define R9A07G044_MIPI_DSI_LPCLK 56 -#define R9A07G044_LCDC_CLK_A 57 -#define R9A07G044_LCDC_CLK_P 58 -#define R9A07G044_LCDC_CLK_D 59 -#define R9A07G044_SSI0_PCLK2 60 -#define R9A07G044_SSI0_PCLK_SFR 61 -#define R9A07G044_SSI1_PCLK2 62 -#define R9A07G044_SSI1_PCLK_SFR 63 -#define R9A07G044_SSI2_PCLK2 64 -#define R9A07G044_SSI2_PCLK_SFR 65 -#define R9A07G044_SSI3_PCLK2 66 -#define R9A07G044_SSI3_PCLK_SFR 67 -#define R9A07G044_SRC_CLKP 68 -#define R9A07G044_USB_U2H0_HCLK 69 -#define R9A07G044_USB_U2H1_HCLK 70 -#define R9A07G044_USB_U2P_EXR_CPUCLK 71 -#define R9A07G044_USB_PCLK 72 -#define R9A07G044_ETH0_CLK_AXI 73 -#define R9A07G044_ETH0_CLK_CHI 74 -#define R9A07G044_ETH1_CLK_AXI 75 -#define R9A07G044_ETH1_CLK_CHI 76 -#define R9A07G044_I2C0_PCLK 77 -#define R9A07G044_I2C1_PCLK 78 -#define R9A07G044_I2C2_PCLK 79 -#define R9A07G044_I2C3_PCLK 80 -#define R9A07G044_SCIF0_CLK_PCK 81 -#define R9A07G044_SCIF1_CLK_PCK 82 -#define R9A07G044_SCIF2_CLK_PCK 83 -#define R9A07G044_SCIF3_CLK_PCK 84 -#define R9A07G044_SCIF4_CLK_PCK 85 -#define R9A07G044_SCI0_CLKP 86 -#define R9A07G044_SCI1_CLKP 87 -#define R9A07G044_IRDA_CLKP 88 -#define R9A07G044_RSPI0_CLKB 89 -#define R9A07G044_RSPI1_CLKB 90 -#define R9A07G044_RSPI2_CLKB 91 -#define R9A07G044_CANFD_PCLK 92 -#define R9A07G044_GPIO_HCLK 93 -#define R9A07G044_ADC_ADCLK 94 -#define R9A07G044_ADC_PCLK 95 -#define R9A07G044_TSU_PCLK 96 - -/* R9A07G044 Resets */ -#define R9A07G044_CA55_RST_1_0 0 -#define R9A07G044_CA55_RST_1_1 1 -#define R9A07G044_CA55_RST_3_0 2 -#define R9A07G044_CA55_RST_3_1 3 -#define R9A07G044_CA55_RST_4 4 -#define R9A07G044_CA55_RST_5 5 -#define R9A07G044_CA55_RST_6 6 -#define R9A07G044_CA55_RST_7 7 -#define R9A07G044_CA55_RST_8 8 -#define R9A07G044_CA55_RST_9 9 -#define R9A07G044_CA55_RST_10 10 -#define R9A07G044_CA55_RST_11 11 -#define R9A07G044_CA55_RST_12 12 -#define R9A07G044_GIC600_GICRESET_N 13 -#define R9A07G044_GIC600_DBG_GICRESET_N 14 -#define R9A07G044_IA55_RESETN 15 -#define R9A07G044_MHU_RESETN 16 -#define R9A07G044_DMAC_ARESETN 17 -#define R9A07G044_DMAC_RST_ASYNC 18 -#define R9A07G044_SYC_RESETN 19 -#define R9A07G044_OSTM0_PRESETZ 20 -#define R9A07G044_OSTM1_PRESETZ 21 -#define R9A07G044_OSTM2_PRESETZ 22 -#define R9A07G044_MTU_X_PRESET_MTU3 23 -#define R9A07G044_POE3_RST_M_REG 24 -#define R9A07G044_GPT_RST_C 25 -#define R9A07G044_POEG_A_RST 26 -#define R9A07G044_POEG_B_RST 27 -#define R9A07G044_POEG_C_RST 28 -#define R9A07G044_POEG_D_RST 29 -#define R9A07G044_WDT0_PRESETN 30 -#define R9A07G044_WDT1_PRESETN 31 -#define R9A07G044_WDT2_PRESETN 32 -#define R9A07G044_SPI_RST 33 -#define R9A07G044_SDHI0_IXRST 34 -#define R9A07G044_SDHI1_IXRST 35 -#define R9A07G044_GPU_RESETN 36 -#define R9A07G044_GPU_AXI_RESETN 37 -#define R9A07G044_GPU_ACE_RESETN 38 -#define R9A07G044_ISU_ARESETN 39 -#define R9A07G044_ISU_PRESETN 40 -#define R9A07G044_H264_X_RESET_VCP 41 -#define R9A07G044_H264_CP_PRESET_P 42 -#define R9A07G044_CRU_CMN_RSTB 43 -#define R9A07G044_CRU_PRESETN 44 -#define R9A07G044_CRU_ARESETN 45 -#define R9A07G044_MIPI_DSI_CMN_RSTB 46 -#define R9A07G044_MIPI_DSI_ARESET_N 47 -#define R9A07G044_MIPI_DSI_PRESET_N 48 -#define R9A07G044_LCDC_RESET_N 49 -#define R9A07G044_SSI0_RST_M2_REG 50 -#define R9A07G044_SSI1_RST_M2_REG 51 -#define R9A07G044_SSI2_RST_M2_REG 52 -#define R9A07G044_SSI3_RST_M2_REG 53 -#define R9A07G044_SRC_RST 54 -#define R9A07G044_USB_U2H0_HRESETN 55 -#define R9A07G044_USB_U2H1_HRESETN 56 -#define R9A07G044_USB_U2P_EXL_SYSRST 57 -#define R9A07G044_USB_PRESETN 58 -#define R9A07G044_ETH0_RST_HW_N 59 -#define R9A07G044_ETH1_RST_HW_N 60 -#define R9A07G044_I2C0_MRST 61 -#define R9A07G044_I2C1_MRST 62 -#define R9A07G044_I2C2_MRST 63 -#define R9A07G044_I2C3_MRST 64 -#define R9A07G044_SCIF0_RST_SYSTEM_N 65 -#define R9A07G044_SCIF1_RST_SYSTEM_N 66 -#define R9A07G044_SCIF2_RST_SYSTEM_N 67 -#define R9A07G044_SCIF3_RST_SYSTEM_N 68 -#define R9A07G044_SCIF4_RST_SYSTEM_N 69 -#define R9A07G044_SCI0_RST 70 -#define R9A07G044_SCI1_RST 71 -#define R9A07G044_IRDA_RST 72 -#define R9A07G044_RSPI0_RST 73 -#define R9A07G044_RSPI1_RST 74 -#define R9A07G044_RSPI2_RST 75 -#define R9A07G044_CANFD_RSTP_N 76 -#define R9A07G044_CANFD_RSTC_N 77 -#define R9A07G044_GPIO_RSTN 78 -#define R9A07G044_GPIO_PORT_RESETN 79 -#define R9A07G044_GPIO_SPARE_RESETN 80 -#define R9A07G044_ADC_PRESETN 81 -#define R9A07G044_ADC_ADRST_N 82 -#define R9A07G044_TSU_PRESETN 83 - -#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h deleted file mode 100644 index 34ce778885a..00000000000 --- a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * This header provides constants for Renesas RZ/G2L family IRQC bindings. - * - * Copyright (C) 2022 Renesas Electronics Corp. - * - */ - -#ifndef __DT_BINDINGS_IRQC_RZG2L_H -#define __DT_BINDINGS_IRQC_RZG2L_H - -/* NMI maps to SPI0 */ -#define RZG2L_NMI 0 - -/* IRQ0-7 map to SPI1-8 */ -#define RZG2L_IRQ0 1 -#define RZG2L_IRQ1 2 -#define RZG2L_IRQ2 3 -#define RZG2L_IRQ3 4 -#define RZG2L_IRQ4 5 -#define RZG2L_IRQ5 6 -#define RZG2L_IRQ6 7 -#define RZG2L_IRQ7 8 - -#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h deleted file mode 100644 index c78ed5e5efb..00000000000 --- a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * This header provides constants for Renesas RZ/G2L family pinctrl bindings. - * - * Copyright (C) 2021 Renesas Electronics Corp. - * - */ - -#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H -#define __DT_BINDINGS_RZG2L_PINCTRL_H - -#define RZG2L_PINS_PER_PORT 8 - -/* - * Create the pin index from its bank and position numbers and store in - * the upper 16 bits the alternate function identifier - */ -#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) - -/* Convert a port and pin label to its global pin index */ -#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) - -#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ diff --git a/include/lmb.h b/include/lmb.h index fa91bf17ade..f221f0cce8f 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -158,7 +158,7 @@ static inline int lmb_read_check(phys_addr_t addr, phys_size_t len) /** * io_lmb_setup() - Initialize LMB struct - * @lmb: IO LMB to initialize + * @io_lmb: IO LMB to initialize * * Returns: 0 on success, negative error code on failure */ @@ -166,7 +166,7 @@ int io_lmb_setup(struct lmb *io_lmb); /** * io_lmb_teardown() - Tear LMB struct down - * @lmb: IO LMB to teardown + * @io_lmb: IO LMB to teardown */ void io_lmb_teardown(struct lmb *io_lmb); diff --git a/include/spi.h b/include/spi.h index 3a92d02f215..6944773b596 100644 --- a/include/spi.h +++ b/include/spi.h @@ -41,12 +41,6 @@ #define SPI_3BYTE_MODE 0x0 #define SPI_4BYTE_MODE 0x1 -/* SPI transfer flags */ -#define SPI_XFER_STRIPE (1 << 6) -#define SPI_XFER_MASK (3 << 8) -#define SPI_XFER_LOWER (1 << 8) -#define SPI_XFER_UPPER (2 << 8) - /* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 2 @@ -169,6 +163,8 @@ struct spi_slave { #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) #define SPI_XFER_U_PAGE BIT(4) #define SPI_XFER_STACKED BIT(5) +#define SPI_XFER_LOWER BIT(6) + /* * Flag indicating that the spi-controller has multi chip select * capability and can assert/de-assert more than one chip select |