diff options
370 files changed, 28191 insertions, 12693 deletions
diff --git a/.gitignore b/.gitignore index 9110eda6468..6bb0adefa7b 100644 --- a/.gitignore +++ b/.gitignore @@ -3,29 +3,31 @@ # subdirectories here. Add them in the ".gitignore" file # in that subdirectory instead. # -# Normal rules +# Normal rules (sorted alphabetically) # .* -*.o -*.o.* *.a -*.s -*.su -*.mod.c +*.bin +*.cfgtmp +*.dtb +*.dtb.S +*.elf +*.exe +*.gcda +*.gcno *.i *.lex.c *.lst +*.mod.c +*.o +*.o.* *.order -*.elf -*.swp -*.bin *.patch -*.cfgtmp +*.s +*.su +*.swp *.tab.[ch] -# host programs on Cygwin -*.exe - # Build tree /build-* @@ -86,7 +88,3 @@ GTAGS *.orig *~ \#*# - -# gcc code coverage files -*.gcda -*.gcno diff --git a/.travis.yml b/.travis.yml index 7e90bc9b367..7b0eb6e4f6b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -157,8 +157,6 @@ matrix: - env: - BUILDMAN="atmel" - env: - - BUILDMAN="aries" - - env: BUILDMAN="boundary engicam toradex" - env: - JOB="Freescale ARM32" @@ -192,7 +190,7 @@ matrix: - BUILDMAN="sun50i" - env: - JOB="Catch-all ARM" - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx" + BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx" - env: - BUILDMAN="sandbox x86" TOOLCHAIN="x86_64" diff --git a/MAINTAINERS b/MAINTAINERS index 642c4480938..b2c9717cb76 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -184,7 +184,7 @@ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ ARM SNAPDRAGON -M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> +M: Ramon Fried <ramon.fried@gmail.com> S: Maintained F: arch/arm/mach-snapdragon/ @@ -3,7 +3,7 @@ VERSION = 2018 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -263,8 +263,9 @@ HOSTCXXFLAGS = -O2 # Some Linux distributions (including RHEL7, SLES13, Debian 8) still # have older compilers as their default, so we make it explicit for # these that our host tools are GNU11 (i.e. C11 w/ GNU extensions). +CSTD_FLAG := -std=gnu11 ifeq ($(HOSTOS),linux) -HOSTCFLAGS += --std=gnu11 +HOSTCFLAGS += $(CSTD_FLAG) endif ifeq ($(HOSTOS),cygwin) @@ -370,7 +371,7 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ -Wno-format-security \ - -fno-builtin -ffreestanding + -fno-builtin -ffreestanding $(CSTD_FLAG) KBUILD_CFLAGS += -fshort-wchar KBUILD_AFLAGS := -D__ASSEMBLY__ @@ -2625,6 +2625,10 @@ FIT uImage format: CONFIG_SPL_NAND_DRIVERS SPL uses normal NAND drivers, not minimal drivers. + CONFIG_SPL_NAND_IDENT + SPL uses the chip ID list to identify the NAND flash. + Requires CONFIG_SPL_NAND_BASE. + CONFIG_SPL_NAND_ECC Include standard software ECC in the SPL diff --git a/arch/arc/dts/.gitignore b/arch/arc/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/arc/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22234cde2ab..00b28480b40 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -108,6 +108,9 @@ config SYS_ARM_MPU # CONFIG_ARM_ERRATA_621766 # CONFIG_ARM_ERRATA_798870 # CONFIG_ARM_ERRATA_801819 +# CONFIG_ARM_CORTEX_A8_CVE_2017_5715 +# CONFIG_ARM_CORTEX_A15_CVE_2017_5715 + config ARM_ERRATA_430973 bool @@ -177,6 +180,12 @@ config ARM_ERRATA_852423 config ARM_ERRATA_855873 bool +config ARM_CORTEX_A8_CVE_2017_5715 + bool + +config ARM_CORTEX_A15_CVE_2017_5715 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 8fef4019af1..7818d729086 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -15,7 +15,7 @@ #include "mxs_init.h" -static uint32_t dram_vals[] = { +__weak uint32_t mxs_dram_vals[] = { /* * i.MX28 DDR2 at 200MHz */ @@ -100,11 +100,11 @@ static void initialize_dram_values(void) int i; debug("SPL: Setting mx28 board specific SDRAM parameters\n"); - mxs_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mxs_dram_vals); debug("SPL: Applying SDRAM parameters\n"); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) + writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } #else static void initialize_dram_values(void) @@ -112,7 +112,7 @@ static void initialize_dram_values(void) int i; debug("SPL: Setting mx23 board specific SDRAM parameters\n"); - mxs_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mxs_dram_vals); /* * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as @@ -124,10 +124,10 @@ static void initialize_dram_values(void) * So skip the initialization of these HW_DRAM_CTL registers. */ debug("SPL: Applying SDRAM parameters\n"); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { + for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) { if (i == 8 || i == 27 || i == 28 || i == 35) continue; - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } /* diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index c996525f861..81edec01bf3 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -241,6 +241,14 @@ skip_errata_798870: skip_errata_801819: #endif +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #1 << 0 @ Enable invalidates of BTB + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through +#endif + #ifdef CONFIG_ARM_ERRATA_454179 mrc p15, 0, r0, c1, c0, 1 @ Read ACR @@ -252,12 +260,15 @@ skip_errata_801819: pop {r1-r5} @ Restore the cpu info - fall through #endif -#ifdef CONFIG_ARM_ERRATA_430973 +#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715) mrc p15, 0, r0, c1, c0, 1 @ Read ACR +#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715 + orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA +#else cmp r2, #0x21 @ Only on < r2p1 orrlt r0, r0, #(0x1 << 6) @ Set IBE bit - +#endif push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index dd89d0a83f8..7627fd13e7d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -191,14 +191,14 @@ int is_core_online(u64 cpu_id) return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { puts("Feature is not implemented.\n"); return 0; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { puts("Feature is not implemented.\n"); @@ -231,7 +231,7 @@ static int core_to_pos(int nr) return i; } -int cpu_status(int nr) +int cpu_status(u32 nr) { u64 *table; int pos; @@ -257,7 +257,7 @@ int cpu_status(int nr) return 0; } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { u64 boot_addr; u64 *table = (u64 *)get_spin_tbl_addr(); diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 7e270a7dc23..2a71870ae7b 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -45,7 +45,7 @@ int is_core_valid(unsigned int core) return 0; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { puts("Feature is not implemented.\n"); return 0; @@ -131,7 +131,7 @@ static void enable_clock_r5(void) udelay(0x500); } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u32 val = readl(&crfapb_base->rst_fpd_apu); @@ -144,7 +144,7 @@ int cpu_disable(int nr) return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); @@ -220,7 +220,7 @@ void initialize_tcm(bool mode) } } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u64 boot_addr = simple_strtoull(argv[0], NULL, 16); diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/arm/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3da8fc7a189..946023093df 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -189,7 +189,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_is1.dtb \ - socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_dbm_soc1.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ @@ -427,7 +426,7 @@ dtb-$(CONFIG_MX6SX) += \ imx6sx-sdb.dtb dtb-$(CONFIG_MX6UL) += \ - imx6ul-geam-kit.dtb \ + imx6ul-geam.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb @@ -513,9 +512,6 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ at91-sama5d3_xplained.dtb -dtb-$(CONFIG_TARGET_MA5D4EK) += \ - at91-sama5d4_ma5d4evk.dts.dtb - dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ at91-sama5d4ek.dtb diff --git a/arch/arm/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/dts/at91-sama5d4_ma5d4.dtsi deleted file mode 100644 index d3e79fbf194..00000000000 --- a/arch/arm/dts/at91-sama5d4_ma5d4.dtsi +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "sama5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4"; - compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - - clk20m: clk20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - }; - - ahb { - apb { - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - broken-cd; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - - can1: can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; - regulator-name = "RST_n MCI0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-boot-on; - }; -}; diff --git a/arch/arm/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/dts/at91-sama5d4_ma5d4evk.dts deleted file mode 100644 index f65a67b7515..00000000000 --- a/arch/arm/dts/at91-sama5d4_ma5d4evk.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "at91-sama5d4_ma5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4EVK"; - compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - ahb { - apb { - hlcdc: hlcdc@f0000000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - usart0: serial@f802c000 { - status = "okay"; - }; - - usart1: serial@f8030000 { - status = "okay"; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - adc0: adc@fc034000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - }; - - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; - }; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - user1 { - label = "user1"; - gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "user2"; - gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user3 { - label = "user3"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - /* Actually Ampire 800480R2 */ - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 17 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - }; -}; diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi index b968f5eb683..3a1ea13ee52 100644 --- a/arch/arm/dts/dragonboard410c-uboot.dtsi +++ b/arch/arm/dts/dragonboard410c-uboot.dtsi @@ -6,10 +6,6 @@ */ / { - config { - u-boot,mmc-env-partition = "boot"; - }; - soc { u-boot,dm-pre-reloc; @@ -21,14 +17,14 @@ }; }; - qcom,gcc@1800000 { - u-boot,dm-pre-reloc; - }; + qcom,gcc@1800000 { + u-boot,dm-pre-reloc; + }; - serial@78b0000 { - u-boot,dm-pre-reloc; + serial@78b0000 { + u-boot,dm-pre-reloc; + }; }; - }; }; diff --git a/arch/arm/dts/imx53-kp.dts b/arch/arm/dts/imx53-kp.dts index fd64a9f2f6d..ca98fb59c61 100644 --- a/arch/arm/dts/imx53-kp.dts +++ b/arch/arm/dts/imx53-kp.dts @@ -86,6 +86,10 @@ MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4 /* BOOSTER_OFF */ MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 + /* LCD BACKLIGHT */ + MX53_PAD_GPIO_1__GPIO1_1 0x1e4 + /* KEY1 GPIO */ + MX53_PAD_EIM_RW__GPIO2_26 0x1e4 >; }; diff --git a/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi b/arch/arm/dts/imx6ul-geam-u-boot.dtsi index 3141a07f048..3141a07f048 100644 --- a/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-geam-u-boot.dtsi diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam.dts index 07c21cb0a2d..07c21cb0a2d 100644 --- a/arch/arm/dts/imx6ul-geam-kit.dts +++ b/arch/arm/dts/imx6ul-geam.dts diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts index a2cade762a1..dca501be25c 100644 --- a/arch/arm/dts/imx7-colibri.dts +++ b/arch/arm/dts/imx7-colibri.dts @@ -16,6 +16,15 @@ }; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; @@ -48,6 +57,25 @@ }; &iomuxc { + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + pinctrl_i2c4: i2c4-grp { fsl,pins = < MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index a7d48e785d3..4d42335c0de 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/clock/imx7d-clock.h> +#include <dt-bindings/power/imx7-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -57,7 +58,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; @@ -115,11 +116,77 @@ clock-output-names = "osc"; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; funnel@30041000 { @@ -259,62 +326,18 @@ }; }; - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - intc: interrupt-controller@31001000 { compatible = "arm,cortex-a7-gic"; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x31001000 0x1000>, <0x31002000 0x2000>, <0x31004000 0x2000>, <0x31006000 0x2000>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -482,20 +505,49 @@ status = "disabled"; }; + kpp: kpp@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_KPP_ROOT_CLK>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx7d-iomuxc"; reg = <0x30330000 0x10000>; }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + compatible = "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; ocotp: ocotp-ctrl@30350000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx7d-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clks IMX7D_OCOTP_CLK>; + + tempmon_calib: calib@3c { + reg = <0x3c 0x4>; + }; + + tempmon_temp_grade: temp-grade@10 { + reg = <0x10 0x4>; + }; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon =<&anatop>; + nvmem-cells = <&tempmon_calib>, + <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; }; anatop: anatop@30360000 { @@ -504,8 +556,11 @@ reg = <0x30360000 0x10000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; - reg_1p0d: regulator-vdd1p0d { + reg_1p0d: regulator-vdd1p0d@30360210 { + reg = <0x30360210>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p0d"; regulator-min-microvolt = <800000>; @@ -516,6 +571,7 @@ anatop-min-bit-val = <8>; anatop-min-voltage = <800000>; anatop-max-voltage = <1200000>; + anatop-enable-bit = <0>; }; }; @@ -529,12 +585,15 @@ offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; snvs_poweroff: snvs-poweroff { compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; + value = <0x60>; mask = <0x60>; }; @@ -558,11 +617,32 @@ }; src: src@30390000 { - compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + compatible = "fsl,imx7d-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + #power-domain-cells = <1>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_pcie_phy: pgc-power-domain@1 { + #power-domain-cells = <0>; + reg = <1>; + power-supply = <®_1p0d>; + }; + }; + }; }; aips2: aips-bus@30400000 { @@ -609,7 +689,7 @@ clocks = <&clks IMX7D_PWM1_ROOT_CLK>, <&clks IMX7D_PWM1_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -620,7 +700,7 @@ clocks = <&clks IMX7D_PWM2_ROOT_CLK>, <&clks IMX7D_PWM2_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -631,7 +711,7 @@ clocks = <&clks IMX7D_PWM3_ROOT_CLK>, <&clks IMX7D_PWM3_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -642,7 +722,7 @@ clocks = <&clks IMX7D_PWM4_ROOT_CLK>, <&clks IMX7D_PWM4_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -664,118 +744,156 @@ reg = <0x30800000 0x400000>; ranges; - ecspi1: ecspi@30820000 { + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; + + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - ecspi2: ecspi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - ecspi3: ecspi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - sai1: sai@308a0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308a0000 0x10000>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SAI1_IPG_CLK>, - <&clks IMX7D_SAI1_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; - status = "disabled"; - }; + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308b0000 0x10000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SAI2_IPG_CLK>, - <&clks IMX7D_SAI2_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; - status = "disabled"; + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; }; - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SAI3_IPG_CLK>, - <&clks IMX7D_SAI3_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; - status = "disabled"; + crypto: caam@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr1@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; }; flexcan1: can@30a00000 { @@ -918,24 +1036,12 @@ reg = <0x30b30200 0x200>; }; - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - }; - usdhc1: usdhc@30b40000 { compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -946,8 +1052,8 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -958,8 +1064,8 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -980,9 +1086,11 @@ fec1: ethernet@30be0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, @@ -995,5 +1103,36 @@ status = "disabled"; }; }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; + }; }; }; diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts index c97d59a5322..dcda98c6ae0 100644 --- a/arch/arm/dts/r8a7790-lager.dts +++ b/arch/arm/dts/r8a7790-lager.dts @@ -48,8 +48,11 @@ serial0 = &scif0; serial1 = &scifa1; i2c8 = &gpioi2c1; + i2c9 = &gpioi2c2; i2c10 = &i2cexio0; i2c11 = &i2cexio1; + i2c12 = &i2chdmi; + i2c13 = &i2cpwr; }; chosen { @@ -241,6 +244,12 @@ }; }; + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -269,9 +278,18 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */ - &gpio1 16 GPIO_ACTIVE_HIGH /* scl */ - >; + scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -306,6 +324,138 @@ #address-cells = <1>; #size-cells = <0>; }; + + /* + * IIC2 and I2C2 may be switched using pinmux. + * A fallback to GPIO is also provided. + */ + i2chdmi: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep0>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + }; + + /* + * IIC3 and I2C3 may be switched using pinmux. + * IIC3/I2C3 does not appear to support fallback to GPIO. + */ + i2cpwr: i2c-13 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic3>, <&i2c3>; + i2c-bus-name = "i2c-pwr"; + #address-cells = <1>; + #size-cells = <0>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + }; }; &du { @@ -314,10 +464,8 @@ status = "okay"; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; ports { port@0 { @@ -325,12 +473,26 @@ remote-endpoint = <&adv7123_in>; }; }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { port@1 { endpoint { remote-endpoint = <&adv7511_in>; }; }; - port@2 { + }; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { lvds_connector: endpoint { }; }; @@ -435,11 +597,21 @@ function = "iic1"; }; + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + iic2_pins: iic2 { groups = "iic2"; function = "iic2"; }; + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + iic3_pins: iic3 { groups = "iic3"; function = "iic3"; @@ -641,124 +813,28 @@ pinctrl-names = "i2c-exio1"; }; -&iic2 { - status = "okay"; - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "default"; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "i2c-hdmi"; clock-frequency = <100000>; +}; - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; +&iic2 { + pinctrl-0 = <&iic2_pins>; + pinctrl-names = "i2c-hdmi"; - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; + clock-frequency = <100000>; +}; - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "i2c-pwr"; }; -&iic3 { - pinctrl-names = "default"; +&iic3 { pinctrl-0 = <&iic3_pins>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; + pinctrl-names = "i2c-pwr"; }; &pci0 { diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi index b4e9e6d3d9e..ed09e56c362 100644 --- a/arch/arm/dts/r8a7790.dtsi +++ b/arch/arm/dts/r8a7790.dtsi @@ -14,7 +14,6 @@ / { compatible = "renesas,r8a7790"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -38,6 +37,35 @@ vin3 = &vin3; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -156,1509 +184,1602 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - apmu@e6152000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 408>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7790"; + reg = <0 0xe6060000 0 0x250>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - renesas,channels-mask = <0x60>; + apmu@e6151000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; - status = "disabled"; - }; + apmu@e6152000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7790-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7790-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7790", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 300>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 305>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 305>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7790"; - reg = <0 0xe6060000 0 0x250>; - }; + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee100000 0 0x328>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>, + <&dmac1 0x69>, <&dmac1 0x6a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee120000 0 0x328>; - interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee140000 0 0x100>; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7790", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee160000 0 0x100>; - interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7790", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7790-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7790-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7790", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e56000 0 64>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790"; - reg = <0 0xee700000 0 0x400>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7790", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e56000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7790", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x2000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7790", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7790", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 205>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 215>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>, + <&dmac1 0x45>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 215>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7790", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7790", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; - vsp@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 130>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 130>; - }; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7790", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7790_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7790"; - reg = <0 0xfeb00000 0 0x70000>, - <0 0xfeb90000 0 0x1c>, - <0 0xfeb94000 0 0x1c>; - reg-names = "du", "lvds.0", "lvds.1"; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>, - <&cpg CPG_MOD 725>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; - port@0 { - reg = <0>; - du_out_rgb: endpoint { + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; }; }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; - }; - can0: can@e6e80000 { - compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7790", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x20800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + usb@2,0 { + reg = <0x21000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7790-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee120000 0 0x328>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7790-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7790-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7790", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7790", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7790", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7790", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x2000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7790", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x2000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 215>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 215>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7790", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7790", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + vsp@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 130>; }; - }; - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x20800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - usb@2,0 { - reg = <0x21000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; - }; - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7790", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7790_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; + du: display@feb00000 { + compatible = "renesas,du-r8a7790"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; }; }; - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; }; - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; + lvds1: lvds@feb94000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb94000 0 0x1c>; + clocks = <&cpg CPG_MOD 725>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 725>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; }; - rcar_sound,src { - src0: src-0 { - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7790-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; }; - }; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7790-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; }; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-sensors = <&thermal>; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; diff --git a/arch/arm/dts/r8a7791-koelsch.dts b/arch/arm/dts/r8a7791-koelsch.dts index 85966fcc1eb..be96bfd4f36 100644 --- a/arch/arm/dts/r8a7791-koelsch.dts +++ b/arch/arm/dts/r8a7791-koelsch.dts @@ -48,7 +48,11 @@ serial0 = &scif0; serial1 = &scif1; i2c9 = &gpioi2c1; + i2c10 = &gpioi2c2; + i2c11 = &gpioi2c4; i2c12 = &i2cexio1; + i2c13 = &i2chdmi; + i2c14 = &i2cexio4; }; chosen { @@ -275,6 +279,12 @@ }; }; + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -303,9 +313,28 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */ - &gpio7 15 GPIO_ACTIVE_HIGH /* scl */ - >; + scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c2: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c4: i2c-11 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -320,6 +349,115 @@ #address-cells = <1>; #size-cells = <0>; }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-13 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-14 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -327,10 +465,9 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; ports { port@0 { @@ -338,6 +475,13 @@ remote-endpoint = <&adv7511_in>; }; }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { port@1 { lvds_connector: endpoint { }; @@ -363,6 +507,11 @@ function = "i2c2"; }; + i2c4_pins: i2c4 { + groups = "i2c4_c"; + function = "i2c4"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; @@ -613,102 +762,14 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <100000>; +}; - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; }; &i2c6 { diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts index b870b185373..f2d5723fbdc 100644 --- a/arch/arm/dts/r8a7791-porter.dts +++ b/arch/arm/dts/r8a7791-porter.dts @@ -26,6 +26,8 @@ aliases { serial0 = &scif0; + i2c9 = &gpioi2c2; + i2c10 = &i2chdmi; }; chosen { @@ -132,6 +134,78 @@ clocks = <&x14_clk>; }; }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4642: codec@12 { + compatible = "asahi-kasei,ak4642"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + }; }; &extal_clk { @@ -293,65 +367,8 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; - clock-frequency = <400000>; - - ak4642: codec@12 { - compatible = "asahi-kasei,ak4642"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; clock-frequency = <400000>; }; @@ -421,13 +438,12 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x3_clk>, <&x16_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; ports { - port@1 { + port@0 { endpoint { remote-endpoint = <&adv7511_in>; }; @@ -435,6 +451,17 @@ }; }; +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + &rcar_sound { pinctrl-0 = <&ssi_pins &audio_clk_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi index dd21fde1936..d728738ba86 100644 --- a/arch/arm/dts/r8a7791.dtsi +++ b/arch/arm/dts/r8a7791.dtsi @@ -14,7 +14,6 @@ / { compatible = "renesas,r8a7791"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -37,6 +36,35 @@ vin2 = &vin2; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -80,1585 +108,1651 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 908>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 907>; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 905>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7791", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 124>; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - renesas,channels-mask = <0x60>; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - status = "disabled"; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7791", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7791"; + reg = <0 0xe6060000 0 0x250>; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7791-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7791", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7791", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7791"; - reg = <0 0xe6060000 0 0x250>; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee100000 0 0x328>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee140000 0 0x100>; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee160000 0 0x100>; - interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7791", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7791", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7791-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; - adc: adc@e6e54000 { - compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; - reg = <0 0xe6e54000 0 64>; - clocks = <&cpg CPG_MOD 901>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 901>; - status = "disabled"; - }; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7791-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7791", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791"; - reg = <0 0xee700000 0 0x400>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7791", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x2000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7791", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; }; - }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7791"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 726>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + }; - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - }; - }; + adc: adc@e6e54000 { + compatible = "renesas,r8a7791-gyroadc", + "renesas,rcar-gyroadc"; + reg = <0 0xe6e54000 0 64>; + clocks = <&cpg CPG_MOD 901>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 901>; + status = "disabled"; }; - }; - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7791", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - can1: can@e6e88000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7791", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7791", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7791_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", "src.9", "src.8", + "src.7", "src.6", "src.5", "src.4", + "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7791-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7791-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7791", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7791", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7791", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; }; - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; }; - }; - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7791", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; }; - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7791", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x2000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; }; - }; - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7791", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x2000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7791", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7791", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7791", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7791_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; + du: display@feb00000 { + compatible = "renesas,du-r8a7791"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7791-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; }; }; - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7791-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; }; - rcar_sound,src { - src0: src-0 { - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7791-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; }; + }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; }; - ssi9: ssi-9 { - interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + cooling-maps { }; }; }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index afadc8fc706..8e26dede308 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -33,6 +33,14 @@ vin5 = &vin5; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -66,6 +74,22 @@ }; }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -74,75 +98,6 @@ #size-cells = <2>; ranges; - apmu@e6152000 { - compatible = "renesas,r8a7792-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7792", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7792-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7792-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7792"; - reg = <0 0xe6060000 0 0x144>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", "renesas,rcar-gen2-gpio"; @@ -323,6 +278,155 @@ resets = <&cpg 913>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7792"; + reg = <0 0xe6060000 0 0x144>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7792-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7792-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7792-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; + + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; @@ -389,6 +493,35 @@ dma-channels = <15>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7792", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7792", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif", "renesas,scif"; @@ -485,161 +618,6 @@ status = "disabled"; }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7792"; - reg = <0 0xee100000 0 0x328>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7792", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7792", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* I2C doesn't need pinmux */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7792", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7792", "renesas,rcar-gen2-msiof"; @@ -672,34 +650,6 @@ status = "disabled"; }; - du: display@feb00000 { - compatible = "renesas,du-r8a7792"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - can0: can@e6e80000 { compatible = "renesas,can-r8a7792", "renesas,rcar-gen2-can"; @@ -792,6 +742,36 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7792", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + clocks = <&cpg CPG_MOD 314>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; @@ -819,38 +799,55 @@ resets = <&cpg 127>; }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7792-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7792", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; - }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + du: display@feb00000 { + compatible = "renesas,du-r8a7792"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/dts/r8a7793-gose.dts b/arch/arm/dts/r8a7793-gose.dts index 068bd291af8..9c893458ce7 100644 --- a/arch/arm/dts/r8a7793-gose.dts +++ b/arch/arm/dts/r8a7793-gose.dts @@ -45,6 +45,10 @@ aliases { serial0 = &scif0; serial1 = &scif1; + i2c9 = &gpioi2c2; + i2c10 = &gpioi2c4; + i2c11 = &i2chdmi; + i2c12 = &i2cexio4; }; chosen { @@ -293,6 +297,146 @@ #clock-cells = <0>; clock-frequency = <148500000>; }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c4: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + remote = <&vin1>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -300,10 +444,9 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; ports { port@0 { @@ -311,6 +454,11 @@ remote-endpoint = <&adv7511_in>; }; }; + }; +}; + +&lvds0 { + ports { port@1 { lvds_connector: endpoint { }; @@ -331,6 +479,11 @@ function = "i2c2"; }; + i2c4_pins: i2c4 { + groups = "i2c4_c"; + function = "i2c4"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; @@ -541,107 +694,11 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; status = "okay"; clock-frequency = <100000>; - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - remote = <&vin1>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - adv7180_out: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; }; &i2c6 { @@ -665,6 +722,11 @@ }; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi index 0fdbb002d7c..8201b4e8d1d 100644 --- a/arch/arm/dts/r8a7793.dtsi +++ b/arch/arm/dts/r8a7793.dtsi @@ -12,7 +12,6 @@ / { compatible = "renesas,r8a7793"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -29,6 +28,35 @@ spi0 = &qspi; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -71,1261 +99,1320 @@ }; }; - apmu@e6152000 { - compatible = "renesas,r8a7793-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7793"; + reg = <0 0xe6060000 0 0x250>; + }; - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7793", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; + /* Special CPG clocks */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; + apmu@e6152000 { + compatible = "renesas,r8a7793-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 124>; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7793-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - renesas,channels-mask = <0x60>; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7793-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - status = "disabled"; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7793", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7793", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7793", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7793"; - reg = <0 0xe6060000 0 0x250>; - }; + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7793"; - reg = <0 0xee100000 0 0x328>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7793"; - reg = <0 0xee140000 0 0x100>; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7793"; - reg = <0 0xee160000 0 0x100>; - interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7793", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793"; - reg = <0 0xee700000 0 0x400>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7793", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7793", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7793", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7793"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 726>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7793", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7793_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; - port@0 { - reg = <0>; - du_out_rgb: endpoint { + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; }; }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; - }; - can0: can@e6e80000 { - compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - can1: can@e6e88000 { - compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7793", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7793", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - /* Special CPG clocks */ - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7793-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7793-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + du: display@feb00000 { + compatible = "renesas,du-r8a7793"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7793-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 726>; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7793-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + status = "disabled"; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7793-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7793-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-sensors = <&thermal>; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7793_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; + cooling-maps { }; }; + }; - rcar_sound,src { - src0: src-0 { - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts index bde6e477b8b..af3c67eb02d 100644 --- a/arch/arm/dts/r8a7794-alt.dts +++ b/arch/arm/dts/r8a7794-alt.dts @@ -15,7 +15,9 @@ aliases { serial0 = &scif2; + i2c9 = &gpioi2c1; i2c10 = &gpioi2c4; + i2c11 = &i2chdmi; i2c12 = &i2cexio4; }; @@ -135,18 +137,50 @@ clock-frequency = <148500000>; }; + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + }; + gpioi2c4: i2c-10 { #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ - &gpio4 8 GPIO_ACTIVE_HIGH /* scl */ - >; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; /* + * A fallback to GPIO is provided for I2C1. + */ + i2chdmi: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + }; + + /* * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). * A fallback to GPIO is provided. */ @@ -322,23 +356,9 @@ &i2c1 { pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <400000>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; }; &i2c4 { diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts index 4316087ce37..50dad43c102 100644 --- a/arch/arm/dts/r8a7794-silk.dts +++ b/arch/arm/dts/r8a7794-silk.dts @@ -21,6 +21,7 @@ /dts-v1/; #include "r8a7794.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "SILK"; @@ -28,6 +29,8 @@ aliases { serial0 = &scif2; + i2c9 = &gpioi2c1; + i2c10 = &i2chdmi; }; chosen { @@ -40,6 +43,60 @@ reg = <0 0x40000000 0 0x40000000>; }; + gpio-keys { + compatible = "gpio-keys"; + + key-3 { + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "SW4"; + wakeup-source; + debounce-interval = <20>; + }; + key-6 { + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_6>; + label = "SW6"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + linux,code = <KEY_A>; + label = "SW12-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_B>; + label = "SW12-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_C>; + label = "SW12-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_D>; + label = "SW12-4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + d3_3v: regulator-d3-3v { compatible = "regulator-fixed"; regulator-name = "D3.3V"; @@ -150,6 +207,84 @@ clocks = <&x9_clk>; }; }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C1. + */ + i2chdmi: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; }; &extal_clk { @@ -265,61 +400,9 @@ &i2c1 { pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <400000>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; }; &mmcif0 { diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi index 649756f4848..0cc07b30d17 100644 --- a/arch/arm/dts/r8a7794.dtsi +++ b/arch/arm/dts/r8a7794.dtsi @@ -13,7 +13,6 @@ / { compatible = "renesas,r8a7794"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -31,9 +30,39 @@ vin1 = &vin1; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -63,1284 +92,1313 @@ }; }; - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 911>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 910>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 124>; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - renesas,channels-mask = <0x60>; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - status = "disabled"; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7794"; + reg = <0 0xe6060000 0 0x11c>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7794", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7794"; - reg = <0 0xe6060000 0 0x11c>; - }; + apmu@e6151000 { + compatible = "renesas,r8a7794-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7794-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7794-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", - "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7794", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 931>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 930>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 929>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 928>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 927>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 925>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + i2c6: i2c@e6500000 { + compatible = "renesas,iic-r8a7794", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 318>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + i2c7: i2c@e6510000 { + compatible = "renesas,iic-r8a7794", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 323>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7794", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7794", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794"; - reg = <0 0xee700000 0 0x400>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7794", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7794", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 931>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7794", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 930>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 929>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 928>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 927>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 925>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; - i2c6: i2c@e6500000 { - compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 318>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; - i2c7: i2c@e6510000 { - compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 323>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee100000 0 0x328>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee140000 0 0x100>; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee160000 0 0x100>; - interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7794", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; }; - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; }; - }; - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; }; - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; }; - }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7794", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7794", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7794", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7794", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7794", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; }; - }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7794", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&cpg CPG_CORE R8A7794_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", + "src.2", "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7794"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; - port@0 { - reg = <0>; - du_out_rgb0: endpoint { + rcar_sound,src { + src-0 { + status = "disabled"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; }; }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - can1: can@e6e88000 { - compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7794", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7794-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7794", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7794-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7794-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7794", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + }; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7794", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7794", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7794_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", "src.2", - "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; + du: display@feb00000 { + compatible = "renesas,du-r8a7794"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; }; }; - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7794-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; }; - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7794-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; }; + }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index 7f8352f7e6e..af77bfe4e4d 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -27,11 +27,6 @@ i2c7 = &i2c_dvfs; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -43,6 +38,9 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_1: cpu@1 { @@ -52,6 +50,9 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_2: cpu@2 { @@ -61,6 +62,9 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_3: cpu@3 { @@ -70,6 +74,9 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a53_0: cpu@100 { @@ -79,6 +86,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@101 { @@ -88,6 +97,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_2: cpu@102 { @@ -97,6 +108,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_3: cpu@103 { @@ -106,6 +119,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA57: cache-controller-0 { @@ -167,15 +182,99 @@ clock-frequency = <0>; }; - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; @@ -217,7 +316,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -232,12 +331,12 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; - gpio-ranges = <&pfc 0 32 28>; + gpio-ranges = <&pfc 0 32 29>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 911>; @@ -247,7 +346,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -262,7 +361,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -277,7 +376,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -292,7 +391,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -307,7 +406,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -322,7 +421,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -335,42 +434,6 @@ resets = <&cpg 905>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, - <&a53_1>, - <&a53_2>, - <&a53_3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -418,6 +481,155 @@ resets = <&cpg 407>; }; + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: mmu@febe0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebe0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vp1: mmu@fe980000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe980000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 17>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vc1: mmu@fe6f0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6f0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 13>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_pv2: mmu@fd960000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd960000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_pv3: mmu@fd970000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd970000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7795_PD_A3IR>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp0: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7795", "renesas,rcar-dmac"; @@ -450,6 +662,14 @@ resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7300000 { @@ -484,6 +704,14 @@ resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; }; dmac2: dma-controller@e7310000 { @@ -518,6 +746,14 @@ resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; audma0: dma-controller@ec700000 { @@ -552,6 +788,14 @@ resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; }; audma1: dma-controller@ec720000 { @@ -586,6 +830,14 @@ resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; }; avb: ethernet@e6800000 { @@ -627,7 +879,8 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -820,8 +1073,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; @@ -837,8 +1091,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; @@ -854,8 +1109,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; @@ -966,8 +1222,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; @@ -982,8 +1239,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; @@ -998,8 +1256,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; @@ -1046,8 +1305,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; @@ -1079,8 +1339,9 @@ clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -1095,8 +1356,9 @@ clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -1111,8 +1373,9 @@ clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -1456,6 +1719,20 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 815>; status = "disabled"; + iommus = <&ipmmu_hc 2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7795-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; }; xhci0: usb@ee000000 { @@ -1468,6 +1745,17 @@ status = "disabled"; }; + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7795-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a7795-usb-dmac", "renesas,usb-dmac"; @@ -1533,7 +1821,8 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7795"; + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 314>; @@ -1544,7 +1833,8 @@ }; sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7795"; + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 313>; @@ -1555,7 +1845,8 @@ }; sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7795"; + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 312>; @@ -1566,7 +1857,8 @@ }; sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7795"; + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 311>; @@ -1867,6 +2159,7 @@ clocks = <&cpg CPG_MOD 606>; power-domains = <&sysc R8A7795_PD_A3VP>; resets = <&cpg 606>; + iommus = <&ipmmu_vp1 7>; }; fcpf0: fcp@fe950000 { @@ -1875,6 +2168,7 @@ clocks = <&cpg CPG_MOD 615>; power-domains = <&sysc R8A7795_PD_A3VP>; resets = <&cpg 615>; + iommus = <&ipmmu_vp0 0>; }; fcpf1: fcp@fe951000 { @@ -1883,6 +2177,7 @@ clocks = <&cpg CPG_MOD 614>; power-domains = <&sysc R8A7795_PD_A3VP>; resets = <&cpg 614>; + iommus = <&ipmmu_vp1 1>; }; vspbd: vsp@fe960000 { @@ -1902,6 +2197,7 @@ clocks = <&cpg CPG_MOD 607>; power-domains = <&sysc R8A7795_PD_A3VP>; resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; }; vspi0: vsp@fe9a0000 { @@ -1921,6 +2217,7 @@ clocks = <&cpg CPG_MOD 611>; power-domains = <&sysc R8A7795_PD_A3VP>; resets = <&cpg 611>; + iommus = <&ipmmu_vp0 8>; }; vspi1: vsp@fe9b0000 { @@ -1940,11 +2237,12 @@ clocks = <&cpg CPG_MOD 610>; power-domains = <&sysc R8A7795_PD_A3VP>; resets = <&cpg 610>; + iommus = <&ipmmu_vp1 9>; }; vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x4000>; + reg = <0 0xfea20000 0 0x8000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -1959,11 +2257,12 @@ clocks = <&cpg CPG_MOD 603>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; }; vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x4000>; + reg = <0 0xfea28000 0 0x8000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -1978,11 +2277,12 @@ clocks = <&cpg CPG_MOD 602>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; }; vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x4000>; + reg = <0 0xfea30000 0 0x8000>; interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -1997,6 +2297,7 @@ clocks = <&cpg CPG_MOD 601>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 601>; + iommus = <&ipmmu_vi1 10>; }; fdp1@fe940000 { @@ -2019,7 +2320,7 @@ renesas,fcp = <&fcpf1>; }; - hdmi0: hdmi0@fead0000 { + hdmi0: hdmi@fead0000 { compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; @@ -2044,7 +2345,7 @@ }; }; - hdmi1: hdmi1@feae0000 { + hdmi1: hdmi@feae0000 { compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfeae0000 0 0x10000>; interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; @@ -2118,9 +2419,9 @@ tsc: thermal@e6198000 { compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x68>, - <0 0xe61a0000 0 0x5c>, - <0 0xe61a8000 0 0x5c>; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; @@ -2130,49 +2431,114 @@ #thermal-sensor-cells = <1>; status = "okay"; }; + }; - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | + IRQ_TYPE_LEVEL_LOW)>; + }; - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_passive: sensor1-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&sensor1_passive>; + cooling-device = <&a57_0 4 4>; }; }; + }; - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; + trips { + sensor2_passive: sensor2-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; }; }; - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; + cooling-maps { + map0 { + trip = <&sensor2_passive>; + cooling-device = <&a57_0 4 4>; + }; + }; + }; - trips { - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_passive: sensor3-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&sensor3_passive>; + cooling-device = <&a57_0 4 4>; }; }; }; }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index db545ec1309..011f0e596a4 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -27,9 +27,34 @@ i2c7 = &i2c_dvfs; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -43,6 +68,9 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_1: cpu@1 { @@ -52,6 +80,9 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a53_0: cpu@100 { @@ -61,6 +92,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@101 { @@ -70,6 +103,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_2: cpu@102 { @@ -79,6 +114,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_3: cpu@103 { @@ -88,6 +125,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA57: cache-controller-0 { @@ -119,45 +158,102 @@ clock-frequency = <0>; }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + turbo-mode; + }; }; - audio_clk_c: audio_clk_c { + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; }; - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; @@ -187,18 +283,6 @@ resets = <&cpg 408>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - wdt0: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; @@ -211,7 +295,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -226,7 +310,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -241,7 +325,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -256,7 +340,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -271,7 +355,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -286,7 +370,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -301,7 +385,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -316,7 +400,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -334,24 +418,98 @@ reg = <0 0xe6060000 0 0x50c>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>; + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7796_PD_A3VC>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7796_PD_A3IR>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; }; - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, - <&a53_1>, - <&a53_2>, - <&a53_3>; + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; cpg: clock-controller@e6150000 { @@ -380,6 +538,22 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + i2c_dvfs: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; @@ -797,7 +971,8 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1082,6 +1257,14 @@ resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7300000 { @@ -1116,6 +1299,14 @@ resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; }; dmac2: dma-controller@e7310000 { @@ -1150,6 +1341,14 @@ resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; audma0: dma-controller@ec700000 { @@ -1184,6 +1383,14 @@ resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; }; audma1: dma-controller@ec720000 { @@ -1218,6 +1425,14 @@ resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; }; usb_dmac0: dma-controller@e65a0000 { @@ -1265,6 +1480,19 @@ status = "disabled"; }; + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7796-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + xhci0: usb@ee000000 { compatible = "renesas,xhci-r8a7796", "renesas,rcar-gen3-xhci"; @@ -1276,6 +1504,17 @@ status = "disabled"; }; + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7796-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; @@ -1358,7 +1597,8 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7796"; + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 314>; @@ -1369,7 +1609,8 @@ }; sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7796"; + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 313>; @@ -1380,7 +1621,8 @@ }; sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7796"; + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 312>; @@ -1391,7 +1633,8 @@ }; sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7796"; + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 311>; @@ -1403,9 +1646,9 @@ tsc: thermal@e6198000 { compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x68>, - <0 0xe61a0000 0 0x5c>, - <0 0xe61a8000 0 0x5c>; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; @@ -1416,50 +1659,6 @@ status = "okay"; }; - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1657,13 +1856,25 @@ }; pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; /* placeholder */ }; pciec1: pcie@ee800000 { + reg = <0 0xee800000 0 0x80000>; /* placeholder */ }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; @@ -1708,11 +1919,12 @@ clocks = <&cpg CPG_MOD 611>; power-domains = <&sysc R8A7796_PD_A3VC>; resets = <&cpg 611>; + iommus = <&ipmmu_vc0 19>; }; vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x4000>; + reg = <0 0xfea20000 0 0x8000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1727,11 +1939,12 @@ clocks = <&cpg CPG_MOD 603>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; }; vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x4000>; + reg = <0 0xfea28000 0 0x8000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1746,11 +1959,12 @@ clocks = <&cpg CPG_MOD 602>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; }; vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x4000>; + reg = <0 0xfea30000 0 0x8000>; interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1765,6 +1979,7 @@ clocks = <&cpg CPG_MOD 601>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 601>; + iommus = <&ipmmu_vi0 10>; }; hdmi0: hdmi@fead0000 { @@ -1852,4 +2067,105 @@ resets = <&cpg 822>; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_passive: sensor1-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&sensor1_passive>; + cooling-device = <&a57_0 5 5>; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_passive: sensor2-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&sensor2_passive>; + cooling-device = <&a57_0 5 5>; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_passive: sensor3-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&sensor3_passive>; + cooling-device = <&a57_0 5 5>; + }; + }; + }; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 3630b52a921..7a5d68be13e 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -18,6 +18,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c7 = &i2c_dvfs; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -47,7 +51,6 @@ L2_CA57: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc 12>; cache-unified; cache-level = <2>; @@ -317,7 +320,19 @@ }; intc_ex: interrupt-controller@e61c0000 { - /* placeholder */ + compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc 32>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -523,56 +538,109 @@ compatible = "renesas,etheravb-r8a77965", "renesas,etheravb-rcar-gen3"; reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc 32>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; csi20: csi2@fea80000 { + reg = <0 0xfea80000 0 0x10000>; /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; csi40: csi2@feaa0000 { + reg = <0 0xfeaa0000 0 0x10000>; /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; vin0: video@e6ef0000 { + reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ }; vin1: video@e6ef1000 { + reg = <0 0xe6ef1000 0 0x1000>; /* placeholder */ }; vin2: video@e6ef2000 { + reg = <0 0xe6ef2000 0 0x1000>; /* placeholder */ }; vin3: video@e6ef3000 { + reg = <0 0xe6ef3000 0 0x1000>; /* placeholder */ }; vin4: video@e6ef4000 { + reg = <0 0xe6ef4000 0 0x1000>; /* placeholder */ }; vin5: video@e6ef5000 { + reg = <0 0xe6ef5000 0 0x1000>; /* placeholder */ }; vin6: video@e6ef6000 { + reg = <0 0xe6ef6000 0 0x1000>; /* placeholder */ }; vin7: video@e6ef7000 { + reg = <0 0xe6ef7000 0 0x1000>; /* placeholder */ }; ohci0: usb@ee080000 { + reg = <0 0xee080000 0 0x100>; /* placeholder */ }; @@ -602,6 +670,7 @@ }; ohci1: usb@ee0a0000 { + reg = <0 0xee0a0000 0 0x100>; /* placeholder */ }; @@ -619,69 +688,107 @@ }; i2c0: i2c@e6500000 { + reg = <0 0xe6500000 0 0x40>; /* placeholder */ }; i2c1: i2c@e6508000 { + reg = <0 0xe6508000 0 0x40>; /* placeholder */ }; i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xe6510000 0 0x40>; /* placeholder */ }; i2c3: i2c@e66d0000 { + reg = <0 0xe66d0000 0 0x40>; /* placeholder */ }; i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xe66d8000 0 0x40>; /* placeholder */ }; i2c5: i2c@e66e0000 { + reg = <0 0xe66e0000 0 0x40>; /* placeholder */ }; i2c6: i2c@e66e8000 { + reg = <0 0xe66e8000 0 0x40>; /* placeholder */ }; i2c_dvfs: i2c@e60b0000 { - /* placeholder */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a77965", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc 32>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; }; pwm0: pwm@e6e30000 { + reg = <0 0xe6e30000 0 8>; /* placeholder */ }; pwm1: pwm@e6e31000 { + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; /* placeholder */ }; pwm2: pwm@e6e32000 { + reg = <0 0xe6e32000 0 8>; /* placeholder */ }; pwm3: pwm@e6e33000 { + reg = <0 0xe6e33000 0 8>; /* placeholder */ }; pwm4: pwm@e6e34000 { + reg = <0 0xe6e34000 0 8>; /* placeholder */ }; pwm5: pwm@e6e35000 { + reg = <0 0xe6e35000 0 8>; /* placeholder */ }; pwm6: pwm@e6e36000 { + reg = <0 0xe6e36000 0 8>; /* placeholder */ }; du: display@feb00000 { + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; /* placeholder */ ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; du_out_rgb: endpoint { @@ -701,18 +808,26 @@ }; hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x100>; /* placeholder */ }; pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; /* placeholder */ }; pciec1: pcie@ee800000 { + reg = <0 0xee800000 0 0x80000>; /* placeholder */ }; rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ /* placeholder */ rcar_sound,dvc { @@ -801,10 +916,13 @@ }; usb3_phy0: usb-phy@e65ee000 { + reg = <0 0xe65ee000 0 0x90>; + #phy-cells = <0>; /* placeholder */ }; usb3_peri0: usb@ee020000 { + reg = <0 0xee020000 0 0x400>; /* placeholder */ }; @@ -820,6 +938,7 @@ }; wdt0: watchdog@e6020000 { + reg = <0 0xe6020000 0 0x0c>; /* placeholder */ }; }; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index 6db229dc230..5dcad634926 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r8a77970.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Renesas Eagle board based on r8a77970"; @@ -31,6 +32,23 @@ }; }; +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -39,23 +57,37 @@ clock-frequency = <32768>; }; -&pfc { - pinctrl-0 = <&scif_clk_pins>; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; + status = "okay"; + clock-frequency = <400000>; + + io_expander: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; }; +}; - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; }; - avb_pins: avb { - groups = "avb0_mdc"; - function = "avb0"; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; }; }; @@ -78,27 +110,14 @@ }; }; -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - +&rwdt { + timeout-sec = <60>; status = "okay"; }; -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -&avb { - pinctrl-0 = <&avb_pins>; +&scif0 { + pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; - renesas,no-ether-link; - phy-handle = <&phy0>; - status = "okay"; - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - }; + status = "okay"; }; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 847f413a799..8dc599edfab 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -6,18 +6,22 @@ * Copyright (C) 2017 Cogent Embedded, Inc. */ -#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/r8a77970-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/r8a77970-sysc.h> / { compatible = "renesas,r8a77970"; #address-cells = <2>; #size-cells = <2>; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; }; cpus { @@ -28,15 +32,15 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0>; - clocks = <&cpg CPG_CORE 0>; - power-domains = <&sysc 5>; + clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; + power-domains = <&sysc R8A77970_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; L2_CA53: cache-controller { compatible = "cache"; - power-domains = <&sysc 21>; + power-domains = <&sysc R8A77970_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; @@ -56,6 +60,11 @@ clock-frequency = <0>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -84,20 +93,18 @@ IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 408>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77970-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; }; cpg: clock-controller@e6150000 { @@ -121,9 +128,142 @@ #power-domain-cells = <1>; }; - pfc: pfc@e6060000 { + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77970_PD_A3IR>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x50c>; + reg = <0 0xe6060000 0 0x504>; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 22>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 6>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; intc_ex: interrupt-controller@e61c0000 { @@ -138,7 +278,7 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 407>; }; @@ -165,10 +305,14 @@ "ch4", "ch5", "ch6", "ch7"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <8>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; }; dmac2: dma-controller@e7310000 { @@ -189,10 +333,99 @@ "ch4", "ch5", "ch6", "ch7"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <8>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac1 0x97>, <&dmac1 0x96>, + <&dmac2 0x97>, <&dmac2 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac1 0x99>, <&dmac1 0x98>, + <&dmac2 0x99>, <&dmac2 0x98>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; hscif0: serial@e6540000 { @@ -202,13 +435,13 @@ reg = <0 0xe6540000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x31>, <&dmac1 0x30>, <&dmac2 0x31>, <&dmac2 0x30>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; }; @@ -220,13 +453,13 @@ reg = <0 0xe6550000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; }; @@ -238,13 +471,13 @@ reg = <0 0xe6560000 0 96>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x35>, <&dmac1 0x34>, <&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; }; @@ -255,13 +488,13 @@ reg = <0 0xe66a0000 0 96>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x37>, <&dmac1 0x36>, <&dmac2 0x37>, <&dmac2 0x36>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 517>; status = "disabled"; }; @@ -273,13 +506,13 @@ reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; }; @@ -291,13 +524,13 @@ reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; }; @@ -309,13 +542,13 @@ reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x57>, <&dmac1 0x56>, <&dmac2 0x57>, <&dmac2 0x56>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 204>; status = "disabled"; }; @@ -326,13 +559,13 @@ reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 9>, + <&cpg CPG_CORE R8A77970_CLK_S2D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x59>, <&dmac1 0x58>, <&dmac2 0x59>, <&dmac2 0x58>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 203>; status = "disabled"; }; @@ -340,7 +573,7 @@ avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77970", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, @@ -374,9 +607,10 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; + iommus = <&ipmmu_rt 3>; #address-cells = <1>; #size-cells = <0>; }; @@ -389,4 +623,12 @@ status = "disabled"; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; }; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 7a09d0524f9..8b0d24bd292 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -28,6 +28,24 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &avb { @@ -52,14 +70,64 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + avb_pins: avb { mux { groups = "avb_link", "avb_mii"; function = "avb"; }; }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi3_pins: sd2 { + groups = "sdhi3_data8", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; + + sdhi3_pins_uhs: sd2_uhs { + groups = "sdhi3_data8", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; +}; + +&sdhi0 { + status = "okay"; +}; + +&sdhi1 { + status = "okay"; +}; + +&sdhi3 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; }; &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index be4f519711a..6d2d5e10689 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -185,6 +185,30 @@ reg = <0 0xe6160000 0 0x0200>; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee100000 0 0x2000>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee120000 0 0x2000>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee160000 0 0x2000>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + status = "disabled"; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a77990-sysc"; reg = <0 0xe6180000 0 0x0400>; @@ -269,6 +293,14 @@ compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; + + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77990", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; }; timer { diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts index eab9497fb5e..711d487a8e6 100644 --- a/arch/arm/dts/r8a77995-draak.dts +++ b/arch/arm/dts/r8a77995-draak.dts @@ -24,11 +24,61 @@ stdout-path = "serial0:115200n8"; }; + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x18000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -43,6 +93,21 @@ }; }; + du_pins: du { + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + pwm0_pins: pwm0 { groups = "pwm0_c"; function = "pwm0"; @@ -58,12 +123,56 @@ function = "scif2"; }; + sdhi2_pins: sd2 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + usb0_pins: usb0 { groups = "usb0"; function = "usb0"; }; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; + &ehci0 { status = "okay"; }; @@ -77,6 +186,7 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { @@ -94,6 +204,20 @@ status = "okay"; }; +&sdhi2 { + /* used for on-board eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index 0328c8acd3f..1d49279ac92 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -48,6 +48,18 @@ clock-frequency = <0>; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + }; + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; @@ -78,18 +90,6 @@ resets = <&cpg 408>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; @@ -100,11 +100,88 @@ status = "disabled"; }; - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + #iommu-cells = <1>; + status = "disabled"; }; + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77995-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -152,6 +229,78 @@ resets = <&cpg 407>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a77995", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77995", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77995", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77995", "renesas,rcar-gen3-gpio", @@ -264,10 +413,67 @@ resets = <&cpg 906>; }; + can0: can@e6c30000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a77995-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77995", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, @@ -303,7 +509,8 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -318,11 +525,81 @@ <&cpg CPG_CORE R8A77995_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; @@ -363,6 +640,18 @@ status = "disabled"; }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77995", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + ehci0: usb@ee080100 { compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; @@ -400,6 +689,98 @@ status = "disabled"; }; + vspbs: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 627>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 627>; + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x8000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 622>; + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77995"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + vsps = <&vspd0 0 &vspd1 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + }; + }; + }; + }; + rpc: rpc@0xee200000 { compatible = "renesas,rpc-r8a77995", "renesas,rpc"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; @@ -408,4 +789,12 @@ status = "disabled"; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; }; diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index 7b19549d38c..a36e0ebca07 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -52,7 +52,7 @@ */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <11289600>; + clock-frequency = <12288000>; }; backlight: backlight { @@ -255,9 +255,8 @@ &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; - renesas,no-ether-link; phy-handle = <&phy0>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { @@ -265,6 +264,7 @@ reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; }; }; @@ -283,6 +283,7 @@ }; &ehci0 { + dr_mode = "otg"; status = "okay"; }; @@ -295,6 +296,7 @@ }; &hsusb { + dr_mode = "otg"; status = "okay"; }; @@ -337,6 +339,13 @@ &i2c4 { status = "okay"; + pca9654: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + csa_vdd: adc@7c { compatible = "maxim,max9611"; reg = <0x7c>; @@ -354,9 +363,34 @@ &i2c_dvfs { status = "okay"; + + pmic: pmic@30 { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + dvfs: dvfs { + regulator-name = "dvfs"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &ohci0 { + dr_mode = "otg"; status = "okay"; }; @@ -382,8 +416,7 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_phy_int", "avb_mdc", - "avb_mii"; + groups = "avb_link", "avb_mdc", "avb_mii"; function = "avb"; }; @@ -409,6 +442,11 @@ function = "i2c2"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + pwm1_pins: pwm1 { groups = "pwm1_a"; function = "pwm1"; @@ -497,6 +535,11 @@ bias-pull-down; }; }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; }; &pwm1 { @@ -576,10 +619,7 @@ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; bus-width = <4>; sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; - - max-frequency = <208000000>; }; &sdhi2 { @@ -591,12 +631,10 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <®_1p8v>; bus-width = <8>; - mmc-ddr-1_8v; mmc-hs200-1_8v; non-removable; + fixed-emmc-driver-type = <1>; status = "okay"; - - max-frequency = <200000000>; }; &sdhi3 { @@ -610,16 +648,17 @@ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; bus-width = <4>; sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; - - max-frequency = <208000000>; }; &ssi1 { shared-pin; }; +&usb_extal_clk { + clock-frequency = <50000000>; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -635,11 +674,29 @@ status = "okay"; }; +&usb3_peri0 { + phys = <&usb3_phy0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3s0_clk { + clock-frequency = <100000000>; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; }; &xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts deleted file mode 100644 index 65bec1536f5..00000000000 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Aries MCVEVK"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - aliases { - ethernet0 = &gmac0; - udc0 = &usb1; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - soc { - u-boot,dm-pre-reloc; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&mmc0 { - status = "okay"; - bus-width = <8>; - u-boot,dm-pre-reloc; -}; - -&usb1 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index d21d78b0dad..f66727ca8e6 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -24,15 +24,6 @@ stdout-path = "serial0:115200n8"; }; - cpld { - compatible = "renesas,ulcb-cpld"; - status = "okay"; - gpio-sck = <&gpio6 8 0>; - gpio-mosi = <&gpio6 7 0>; - gpio-miso = <&gpio6 10 0>; - gpio-sstbz = <&gpio2 3 0>; - }; - audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> @@ -40,7 +31,7 @@ */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <11289600>; + clock-frequency = <12288000>; }; hdmi0-out { @@ -154,9 +145,8 @@ &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; - renesas,no-ether-link; phy-handle = <&phy0>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { @@ -164,9 +154,14 @@ reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; }; }; +&du { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -260,8 +255,7 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_phy_int", "avb_mdc", - "avb_mii"; + groups = "avb_link", "avb_mdc", "avb_mii"; function = "avb"; }; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index e7514f01fa0..3f9237cfa4e 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -124,7 +124,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <58820000>; resets = <&peri_rst 0>; }; @@ -136,7 +135,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <58820000>; resets = <&peri_rst 1>; }; @@ -148,7 +146,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <58820000>; resets = <&peri_rst 2>; }; @@ -160,7 +157,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <58820000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 31bc124dfca..6ffbf18a8c9 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -230,7 +230,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <58820000>; resets = <&peri_rst 0>; }; @@ -242,7 +241,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <58820000>; resets = <&peri_rst 1>; }; @@ -254,7 +252,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <58820000>; resets = <&peri_rst 2>; }; @@ -266,7 +263,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <58820000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index 5e43a9231eb..4545056ba70 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -71,7 +71,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <36864000>; resets = <&peri_rst 0>; }; @@ -83,7 +82,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <36864000>; resets = <&peri_rst 1>; }; @@ -95,7 +93,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <36864000>; resets = <&peri_rst 2>; }; @@ -107,7 +104,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <36864000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 00048635894..8185b54e285 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -79,7 +79,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <73728000>; resets = <&peri_rst 0>; }; @@ -91,7 +90,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <73728000>; resets = <&peri_rst 1>; }; @@ -103,7 +101,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <73728000>; resets = <&peri_rst 2>; }; @@ -115,7 +112,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <73728000>; resets = <&peri_rst 3>; }; @@ -429,7 +425,7 @@ pinctrl-0 = <&pinctrl_ether_rgmii>; clock-names = "gio", "ether", "ether-gb", "ether-phy"; clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, - <&sys_clk 10>; + <&sys_clk 10>; reset-names = "gio", "ether"; resets = <&sys_rst 12>, <&sys_rst 6>; phy-mode = "rgmii"; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 32debf557e4..6aea9af2b6c 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -164,7 +164,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <73728000>; resets = <&peri_rst 0>; }; @@ -176,7 +175,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <73728000>; resets = <&peri_rst 1>; }; @@ -188,7 +186,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <73728000>; resets = <&peri_rst 2>; }; @@ -200,7 +197,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <73728000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 20f39351073..f4101c0aa0c 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -172,7 +172,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <88900000>; resets = <&peri_rst 0>; }; @@ -184,7 +183,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <88900000>; resets = <&peri_rst 1>; }; @@ -196,7 +194,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <88900000>; resets = <&peri_rst 2>; }; @@ -208,7 +205,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <88900000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts index 3b9931a00d4..4fb12b8a675 100644 --- a/arch/arm/dts/uniphier-pxs3-ref.dts +++ b/arch/arm/dts/uniphier-pxs3-ref.dts @@ -75,6 +75,10 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + ð0 { status = "okay"; phy-handle = <ðphy0>; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index ae867cbb0ac..cfeeecdad05 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -152,7 +152,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <58820000>; resets = <&peri_rst 0>; }; @@ -164,7 +163,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <58820000>; resets = <&peri_rst 1>; }; @@ -176,7 +174,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <58820000>; resets = <&peri_rst 2>; }; @@ -188,7 +185,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <58820000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 67d69778a4c..f20926e4a99 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -71,7 +71,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <80000000>; resets = <&peri_rst 0>; }; @@ -83,7 +82,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <80000000>; resets = <&peri_rst 1>; }; @@ -95,7 +93,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <80000000>; resets = <&peri_rst 2>; }; @@ -107,7 +104,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <80000000>; resets = <&peri_rst 3>; }; diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock.h new file mode 100644 index 00000000000..c0ff00fc9a9 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + */ +#ifndef _ARCH_MESON_CLOCK_H_ +#define _ARCH_MESON_CLOCK_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define SCR 0x2C /* 0x0b offset in data sheet */ +#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ + +#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ +#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ +#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ +#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ +#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ +#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ + +#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ +#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ + +#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ +#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ +#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ + +#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ +#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ +#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ +#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ +#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ +#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ +#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ + +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ +#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ +#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ +#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ +#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ +#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ + +#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ +#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ +#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ +#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ +#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ +#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ +#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ + +#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ +#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ +#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ + +#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ +#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ +#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ + +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ +#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ +#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ +#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ +#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ +#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ +#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ +#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ +#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ +#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ + +#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ +#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ +#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ +#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ + +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ +#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ +#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ +#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ +#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ +#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ +#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ +#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ +#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ +#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ + +#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ +#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ + +#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ +#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ +#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ + +ulong meson_measure_clk_rate(unsigned int clk); + +#endif diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 03fb6b03de8..4bc9475d35e 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -56,14 +56,4 @@ /* Ethernet memory power domain */ #define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) -/* Clock gates */ -#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50) -#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51) -#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52) -#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53) -#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54) - -#define GX_GCLK_MPEG_0_I2C BIT(9) -#define GX_GCLK_MPEG_1_ETH BIT(3) - #endif /* __GX_H__ */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 8acf79fbba3..3a59016955c 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -275,20 +275,26 @@ struct sunxi_ccm_reg { * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call * them 0 - 2 like they were called on older SoCs. */ +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 #define AHB_GATE_OFFSET_USB_OHCI0 28 -#define AHB_GATE_OFFSET_USB_EHCI2 27 -#define AHB_GATE_OFFSET_USB_EHCI1 26 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 #elif defined(CONFIG_MACH_SUN50I) -#define AHB_GATE_OFFSET_USB_OHCI0 29 -#define AHB_GATE_OFFSET_USB_EHCI0 25 +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#define AHB_GATE_OFFSET_USB_EHCI1 25 #else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif -#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5) #define AHB_GATE_OFFSET_USB0 23 #elif !defined(CONFIG_MACH_SUN8I_R40) #define AHB_GATE_OFFSET_USB0 24 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index ee648366c74..02ce73954db 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -63,10 +63,11 @@ #ifdef CONFIG_SUNXI_GEN_SUN6I #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE 0x01c1a000 -#define SUNXI_USB1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#define SUNXI_USB3_BASE 0x01c1d000 +#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#define SUNXI_USB3_BASE 0x01c1c000 +#define SUNXI_USB4_BASE 0x01c1d000 #else #define SUNXI_USB0_BASE 0x01c19000 #define SUNXI_USB1_BASE 0x01c1a000 diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1a04e2b8756..699bf44e702 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -26,7 +26,8 @@ struct Image_header { uint32_t res5; }; -int booti_setup(ulong image, ulong *relocated_addr, ulong *size) +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) { struct Image_header *ih; uint64_t dst; @@ -63,7 +64,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size) * images->ep. Otherwise, relocate the image to the base of RAM * since memory below it is not accessible via the linear mapping. */ - if (le64_to_cpu(ih->flags) & BIT(3)) + if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else dst = gd->bd->bi_dram[0].start; diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 79afc27e847..d629cb1dc2d 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -133,7 +133,7 @@ not_used: irq: fiq: 1: - bl 1b /* hang and never return */ + b 1b /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 79c84a5d7b9..ce6be3829af 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -197,14 +197,6 @@ config TARGET_SAMA5D4EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT -config TARGET_MA5D4EVK - bool "Aries MA5D4EVK Evaluation Kit" - select SAMA5D4 - select SUPPORT_SPL - select DM - select DM_SPI - select SPI - config TARGET_MEESC bool "Support meesc" select AT91SAM9263 @@ -263,7 +255,6 @@ endchoice config SYS_SOC default "at91" -source "board/aries/ma5d4evk/Kconfig" source "board/atmel/at91rm9200ek/Kconfig" source "board/atmel/at91sam9260ek/Kconfig" source "board/atmel/at91sam9261ek/Kconfig" diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index f1d4d9e9e04..d4b25c3d60e 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -39,7 +39,7 @@ struct davinci_gpio_bank { unsigned int irq_num; unsigned int irq_mask; unsigned long *in_use; - unsigned long base; + struct davinci_gpio *base; }; #define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) @@ -48,7 +48,9 @@ struct davinci_gpio_bank { #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) #define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8) +#ifndef CONFIG_DM_GPIO #define gpio_status() gpio_info() +#endif #define GPIO_NAME_SIZE 20 #if defined(CONFIG_SOC_DM644X) /* GPIO0 to GPIO53, omit the V3.3 volts one */ @@ -63,4 +65,14 @@ struct davinci_gpio_bank { void gpio_info(void); +#ifdef CONFIG_DM_GPIO + +/* Information about a GPIO bank */ +struct davinci_gpio_platdata { + int bank_index; + ulong base; /* address of registers in physical memory */ + const char *port_name; +}; +#endif + #endif diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index 11f90ed8a21..82257f3280f 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -9,6 +9,34 @@ #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> +static void enable_ca7_smp(void) +{ + u32 val; + + /* Read MIDR */ + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val)); + val = (val >> 4); + val &= 0xf; + + /* Only set the SMP for Cortex A7 */ + if (val == 0x7) { + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + + if (val & (1 << 6)) + return; + + /* Enable SMP */ + val |= (1 << 6); + + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + + DSB; + ISB; + } +} + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { @@ -20,6 +48,9 @@ void enable_caches(void) /* Avoid random hang when download by usb */ invalidate_dcache_all(); + /* Set ACTLR.SMP bit for Cortex-A7 */ + enable_ca7_smp(); + /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); @@ -31,6 +62,17 @@ void enable_caches(void) IRAM_SIZE, option); } +#else +void enable_caches(void) +{ + /* + * Set ACTLR.SMP bit for Cortex-A7, even if the caches are + * disabled by u-boot + */ + enable_ca7_smp(); + + puts("WARNING: Caches not enabled\n"); +} #endif #ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 06322b2aaac..3654670442f 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -8,9 +8,11 @@ config MX5 config MX51 bool select SYS_FSL_ERRATUM_ESDHC_A001 + select ARM_CORTEX_A8_CVE_2017_5715 config MX53 bool + select ARM_CORTEX_A8_CVE_2017_5715 choice prompt "MX5 board select" @@ -27,11 +29,6 @@ config TARGET_KP_IMX53 select DM_GPIO select DM_PMIC -config TARGET_M53EVK - bool "Support m53evk" - select MX53 - select SUPPORT_SPL - config TARGET_MX51EVK bool "Support mx51evk" select BOARD_LATE_INIT @@ -81,7 +78,6 @@ endchoice config SYS_SOC default "mx5" -source "board/aries/m53evk/Kconfig" source "board/beckhoff/mx53cx9020/Kconfig" source "board/freescale/mx51evk/Kconfig" source "board/freescale/mx53ard/Kconfig" diff --git a/arch/arm/mach-imx/mx5/Makefile b/arch/arm/mach-imx/mx5/Makefile index 1fc9c96aaab..40d1998637c 100644 --- a/arch/arm/mach-imx/mx5/Makefile +++ b/arch/arm/mach-imx/mx5/Makefile @@ -9,6 +9,5 @@ obj-y := soc.o clock.o obj-y += lowlevel_init.o # common files for mx53 dram initialization -obj-$(CONFIG_TARGET_M53EVK) += mx53_dram.o obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o obj-$(CONFIG_TARGET_MX53LOCO) += mx53_dram.o diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c index c3806dca3ad..eda168d8671 100644 --- a/arch/arm/mach-imx/mx6/mp.c +++ b/arch/arm/mach-imx/mx6/mp.c @@ -29,20 +29,20 @@ static uint32_t cpu_ctrl_mask[MAX_CPUS] = { SRC_SCR_CORE_3_ENABLE_MASK }; -int cpu_reset(int nr) +int cpu_reset(u32 nr) { /* Software reset of the CPU N */ src->scr |= cpu_reset_mask[nr]; return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr])); return 0; } -int cpu_release(int nr, int argc, char *const argv[]) +int cpu_release(u32 nr, int argc, char *const argv[]) { uint32_t boot_addr; @@ -78,7 +78,7 @@ int is_core_valid(unsigned int core) return 1; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { /* Disable the CPU N */ src->scr &= ~cpu_ctrl_mask[nr]; diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index f1dea66d60d..2aca24bbb0f 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -280,13 +280,6 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { -#if !defined CONFIG_SPL_BUILD - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); -#endif /* clock configuration. */ clock_init(); diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 684d49e5db2..68072d5a1f2 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -50,9 +50,6 @@ config TARGET_APX4DEVKIT config TARGET_BG0900 bool "Support bg0900" -config TARGET_M28EVK - bool "Support m28evk" - config TARGET_MX28EVK bool "Support mx28evk" select BOARD_EARLY_INIT_F @@ -68,7 +65,6 @@ endchoice config SYS_SOC default "mxs" -source "board/aries/m28evk/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" source "board/freescale/mx28evk/Kconfig" source "board/ppcag/bg0900/Kconfig" diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 0350787daa7..9a06ccc8610 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -3,6 +3,7 @@ if ARCH_MESON config MESON_GXBB bool "Support Meson GXBaby" select ARM64 + select CLK select DM select DM_SERIAL help @@ -12,6 +13,7 @@ config MESON_GXBB config MESON_GXL bool "Support Meson GXL" select ARM64 + select CLK select DM select DM_SERIAL help diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c index 061f19a0e31..8b28bc85311 100644 --- a/arch/arm/mach-meson/eth.c +++ b/arch/arm/mach-meson/eth.c @@ -48,7 +48,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) return; } - /* Enable power and clock gate */ - setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH); + /* Enable power gate */ clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3bb1ecb58de..f4babc8d260 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -10,6 +10,7 @@ config OMAP34XX select ARM_ERRATA_454179 select ARM_ERRATA_621766 select ARM_ERRATA_725233 + select ARM_CORTEX_A8_CVE_2017_5715 select USE_TINY_PRINTF imply NAND_OMAP_GPMC imply SPL_EXT_SUPPORT @@ -53,6 +54,7 @@ config OMAP54XX bool "OMAP54XX SoC" select ARM_ERRATA_798870 select SYS_THUMB_BUILD + select ARM_CORTEX_A15_CVE_2017_5715 imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DISPLAY_PRINT @@ -115,6 +117,7 @@ config AM43XX config AM33XX bool "AM33XX SoC" select SPECIFY_CONSOLE_INDEX + select ARM_CORTEX_A8_CVE_2017_5715 imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_NAND_AM33XX_BCH diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index b9d92c62b1b..9a03bfa9d3b 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -750,23 +750,23 @@ void per_clocks_enable(void) setbits_le32(&prcm_base->iclken_per, 0x00000800); #endif -#ifdef CONFIG_OMAP3_GPIO_2 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00002000); setbits_le32(&prcm_base->iclken_per, 0x00002000); #endif -#ifdef CONFIG_OMAP3_GPIO_3 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00004000); setbits_le32(&prcm_base->iclken_per, 0x00004000); #endif -#ifdef CONFIG_OMAP3_GPIO_4 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00008000); setbits_le32(&prcm_base->iclken_per, 0x00008000); #endif -#ifdef CONFIG_OMAP3_GPIO_5 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00010000); setbits_le32(&prcm_base->iclken_per, 0x00010000); #endif -#ifdef CONFIG_OMAP3_GPIO_6 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00020000); setbits_le32(&prcm_base->iclken_per, 0x00020000); #endif diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index b8fc81b20c2..30b475254c4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -36,10 +36,6 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_ARIES_MCVEVK - bool "Aries MCVEVK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 - config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 bool "Devboards DBM-SoC1 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -88,7 +84,6 @@ config SYS_BOARD default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 - default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -98,7 +93,6 @@ config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK - default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA @@ -119,7 +113,6 @@ config SYS_CONFIG_NAME default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "socfpga_is1" if TARGET_SOCFPGA_IS1 - default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 7ac8360c011..58fef05bd73 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -207,9 +207,6 @@ void s_init(void) eth_init_board(); } -#ifdef CONFIG_SPL_BUILD -#endif - /* The sunxi internal brom will try to loader external bootloader * from mmc0, nand flash, mmc2. */ diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 3fafa6ff1a8..4af69190b73 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -11,8 +11,4 @@ n: /* Macros for setting and retrieving special purpose registers */ #define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v)) -#ifndef __ASSEMBLY__ - -#endif /* ifndef ASSEMBLY*/ - #endif /* __ASM_M68K_PROCESSOR_H */ diff --git a/arch/microblaze/dts/.gitignore b/arch/microblaze/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/microblaze/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/mips/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/nios2/dts/.gitignore b/arch/nios2/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/nios2/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 42501ca3cec..b0aa72ed6e0 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -42,7 +42,7 @@ int hold_cores_in_reset(int verbose) return 0; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); @@ -53,7 +53,7 @@ int cpu_reset(int nr) return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { u32 *table, id = get_my_id(); @@ -79,7 +79,7 @@ int cpu_status(int nr) } #ifdef CONFIG_FSL_CORENET -int cpu_disable(int nr) +int cpu_disable(u32 nr) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -95,7 +95,7 @@ int is_core_disabled(int nr) { return (coredisrl & (1 << nr)); } #else -int cpu_disable(int nr) +int cpu_disable(u32 nr) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -137,7 +137,7 @@ static u8 boot_entry_map[4] = { BOOT_ENTRY_R3_LOWER, }; -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; u64 boot_addr; diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 97bd160df8a..ce300eac5b0 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -int cpu_reset(int nr) +int cpu_reset(u32 nr) { /* dummy function so common/cmd_mp.c will build * should be implemented in the future, when cpu_release() @@ -23,13 +23,13 @@ int cpu_reset(int nr) return 1; } -int cpu_status(int nr) +int cpu_status(u32 nr) { /* dummy function so common/cmd_mp.c will build */ return 0; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -66,7 +66,7 @@ int is_core_disabled(int nr) { return 0; } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { /* dummy function so common/cmd_mp.c will build * should be implemented in the future */ diff --git a/arch/sandbox/dts/.gitignore b/arch/sandbox/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/sandbox/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 18c7fb2d496..a1c18d26e1d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -112,6 +112,7 @@ source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" source "arch/x86/cpu/coreboot/Kconfig" source "arch/x86/cpu/ivybridge/Kconfig" +source "arch/x86/cpu/efi/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" @@ -772,6 +773,4 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. -source "arch/x86/lib/efi/Kconfig" - endmenu diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index af9e26caab1..f862d8c071e 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ -obj-$(CONFIG_EFI_APP) += efi/ +obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 022a9f2e51c..d2c3473d6ab 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -4,10 +4,10 @@ config INTEL_BAYTRAIL bool - select HAVE_FSP if !EFI - select ARCH_MISC_INIT if !EFI + select HAVE_FSP + select ARCH_MISC_INIT select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - imply HAVE_INTEL_ME if !EFI + imply HAVE_INTEL_ME imply ENABLE_MRC_CACHE imply AHCI_PCI imply ICH_SPI diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 3194f8c6533..b7d481ac56c 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -17,7 +17,6 @@ #define BYT_TRIG_LVL BIT(24) #define BYT_TRIG_POS BIT(25) -#ifndef CONFIG_EFI_APP int arch_cpu_init(void) { post_code(POST_CPU_INIT); @@ -57,8 +56,6 @@ int arch_misc_init(void) return 0; } -#endif - void reset_cpu(ulong addr) { /* cold reset */ diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index fa3b64f2bb8..392c2589450 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -10,6 +10,7 @@ config SYS_COREBOOT imply MMC_PCI imply MMC_SDHCI imply MMC_SDHCI_SDMA + imply SCSI imply SCSI_AHCI imply SPI_FLASH imply SYS_NS16550 diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index db36553d059..6aefa12a7c5 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -193,7 +193,7 @@ void show_boot_progress(int val) outb(val, POST_PORT); } -#ifndef CONFIG_SYS_COREBOOT +#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) /* * Implement a weak default function for boards that optionally * need to clean up the system before jumping to the kernel. diff --git a/arch/x86/lib/efi/Kconfig b/arch/x86/cpu/efi/Kconfig index e0975d34d36..e0975d34d36 100644 --- a/arch/x86/lib/efi/Kconfig +++ b/arch/x86/cpu/efi/Kconfig diff --git a/arch/x86/cpu/efi/Makefile b/arch/x86/cpu/efi/Makefile index 06d04804408..9716a4ebe08 100644 --- a/arch/x86/cpu/efi/Makefile +++ b/arch/x86/cpu/efi/Makefile @@ -2,5 +2,12 @@ # # Copyright (c) 2015 Google, Inc -obj-y += efi.o +ifdef CONFIG_EFI_APP +obj-y += app.o obj-y += sdram.o +endif + +ifdef CONFIG_EFI_STUB +obj-y += car.o +obj-y += payload.o +endif diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/app.c index cda4fabe15a..ba7c02bd7e8 100644 --- a/arch/x86/cpu/efi/efi.c +++ b/arch/x86/cpu/efi/app.c @@ -9,7 +9,7 @@ int arch_cpu_init(void) { - return 0; + return x86_cpu_init_f(); } int checkcpu(void) diff --git a/arch/x86/lib/efi/car.S b/arch/x86/cpu/efi/car.S index 488dcde66c7..488dcde66c7 100644 --- a/arch/x86/lib/efi/car.S +++ b/arch/x86/cpu/efi/car.S diff --git a/arch/x86/lib/efi/efi.c b/arch/x86/cpu/efi/payload.c index 81fb8b5f72c..4649bfe86eb 100644 --- a/arch/x86/lib/efi/efi.c +++ b/arch/x86/cpu/efi/payload.c @@ -5,11 +5,10 @@ */ #include <common.h> -#include <debug_uart.h> #include <efi.h> #include <errno.h> -#include <linux/err.h> -#include <linux/types.h> +#include <usb.h> +#include <asm/post.h> DECLARE_GLOBAL_DATA_PTR; @@ -110,11 +109,10 @@ int dram_init_banksize(void) desc < end && num_banks < CONFIG_NR_DRAM_BANKS; desc = efi_get_next_mem_desc(map, desc)) { /* - * We only use conventional memory below 4GB, and ignore + * We only use conventional memory and ignore * anything less than 1MB. */ if (desc->type != EFI_CONVENTIONAL_MEMORY || - desc->physical_start >= 1ULL << 32 || (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) continue; gd->bd->bi_dram[num_banks].start = desc->physical_start; @@ -126,6 +124,13 @@ int dram_init_banksize(void) return 0; } +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); + + return x86_cpu_init_f(); +} + int checkcpu(void) { return 0; @@ -155,3 +160,11 @@ int reserve_arch(void) return 0; } + +int last_stage_init(void) +{ + /* start usb so that usb keyboard can be used as input device */ + usb_init(); + + return 0; +} diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index c0fcf0ce78f..bf798c287f3 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o endif obj-y += cpu.o obj-y += lpc.o -ifndef CONFIG_TARGET_EFI +ifndef CONFIG_TARGET_EFI_APP obj-y += microcode.o endif obj-y += pch.o diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index fe8dfbc9ca6..52a77bb2d18 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -239,4 +239,6 @@ _dt_ucode_base_size: .globl ucode_base ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ .long 0 /* microcode size */ diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 11b1ec89553..c7a539d2819 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -43,8 +43,6 @@ static int microcode_decode_node(const void *blob, int node, update->data = fdt_getprop(blob, node, "data", &update->size); if (!update->data) return -ENOENT; - update->data += UCODE_HEADER_LEN; - update->size -= UCODE_HEADER_LEN; update->header_version = fdtdec_get_int(blob, node, "intel,header-version", 0); @@ -124,6 +122,7 @@ static void microcode_read_cpu(struct microcode_update *cpu) int microcode_update_intel(void) { struct microcode_update cpu, update; + ulong address; const void *blob = gd->fdt_blob; int skipped; int count; @@ -167,7 +166,8 @@ int microcode_update_intel(void) skipped++; continue; } - wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0); + address = (ulong)update.data + UCODE_HEADER_LEN; + wrmsr(MSR_IA32_UCODE_WRITE, address, 0); rev = microcode_read_rev(); debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", rev, update.date_code & 0xffff, @@ -178,5 +178,9 @@ int microcode_update_intel(void) return -EFAULT; } count++; + if (!ucode_base) { + ucode_base = (ulong)update.data; + ucode_size = update.size; + } } while (1); } diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index 31428dd0a00..fdf558d6607 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -7,6 +7,7 @@ config QEMU select ARCH_EARLY_INIT_R imply AHCI_PCI imply E1000 + imply SCSI imply SCSI_AHCI imply SYS_NS16550 imply USB diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index e5ea92545e3..b7dd5bd46c7 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -2,8 +2,9 @@ # # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> -ifndef CONFIG_EFI_STUB -obj-y += car.o dram.o +ifndef CONFIG_$(SPL_)X86_64 +obj-y += car.o endif +obj-y += dram.o obj-y += qemu.o obj-$(CONFIG_QFW) += cpu.o e820.o diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 1fdb11cc60c..ca4b3f08335 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -143,10 +143,6 @@ int arch_cpu_init(void) return x86_cpu_init_f(); } -#endif - -#if !CONFIG_IS_ENABLED(EFI_STUB) && \ - !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT) int checkcpu(void) { diff --git a/arch/x86/cpu/x86_64/setjmp.S b/arch/x86/cpu/x86_64/setjmp.S new file mode 100644 index 00000000000..97b812854cc --- /dev/null +++ b/arch/x86/cpu/x86_64/setjmp.S @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Intel Corporation + * + * See arch/x86/include/asm/setjmp.h for jmp_buf format + */ + +#include <linux/linkage.h> + +.text +.align 8 + +ENTRY(setjmp) + + pop %rcx + movq %rcx, (%rdi) /* Return address */ + movq %rsp, 8(%rdi) + movq %rbp, 16(%rdi) + movq %rbx, 24(%rdi) + movq %r12, 32(%rdi) + movq %r13, 40(%rdi) + movq %r14, 48(%rdi) + movq %r15, 56(%rdi) + xorq %rax, %rax /* Direct invocation returns 0 */ + jmpq *%rcx + +ENDPROC(setjmp) + +.align 8 + +ENTRY(longjmp) + + movq (%rdi), %rcx /* Return address */ + movq 8(%rdi), %rsp + movq 16(%rdi), %rbp + movq 24(%rdi), %rbx + movq 32(%rdi), %r12 + movq 40(%rdi), %r13 + movq 48(%rdi), %r14 + movq 56(%rdi), %r15 + + movq %rsi, %rax /* Value to be returned by setjmp() */ + testq %rax, %rax /* cannot be 0 in this case */ + jnz 1f + incq %rax /* Return 1 instead */ +1: + jmpq *%rcx + +ENDPROC(longjmp) diff --git a/arch/x86/cpu/x86_64/setjmp.c b/arch/x86/cpu/x86_64/setjmp.c deleted file mode 100644 index 5d4a74a571a..00000000000 --- a/arch/x86/cpu/x86_64/setjmp.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2016 Google, Inc - */ - -#include <common.h> -#include <asm/setjmp.h> - -int setjmp(struct jmp_buf_data *jmp_buf) -{ - printf("WARNING: setjmp() is not supported\n"); - - return 0; -} - -void longjmp(struct jmp_buf_data *jmp_buf, int val) -{ - printf("WARNING: longjmp() is not supported\n"); -} diff --git a/arch/x86/dts/.gitignore b/arch/x86/dts/.gitignore deleted file mode 100644 index b60ed208c77..00000000000 --- a/arch/x86/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.dtb diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 73797746f83..37e4fdc7601 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -10,7 +10,8 @@ dtb-y += bayleybay.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ edison.dtb \ - efi.dtb \ + efi-x86_app.dtb \ + efi-x86_payload.dtb \ galileo.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index c3a6aad77b2..3e29683bd92 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -75,8 +75,6 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; - #address-cells = <1>; - #size-cells = <1>; irq-router { compatible = "intel,irq-router"; diff --git a/arch/x86/dts/efi.dts b/arch/x86/dts/efi-x86_app.dts index 62ae96a3f3f..e70e3516180 100644 --- a/arch/x86/dts/efi.dts +++ b/arch/x86/dts/efi-x86_app.dts @@ -9,8 +9,8 @@ /include/ "tsc_timer.dtsi" / { - model = "EFI"; - compatible = "efi,app"; + model = "EFI x86 Application"; + compatible = "efi,x86-app"; chosen { stdout-path = &serial; diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts new file mode 100644 index 00000000000..148b5871aa2 --- /dev/null +++ b/arch/x86/dts/efi-x86_payload.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * + * Generic EFI payload device tree for x86 targets + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "EFI x86 Payload"; + compatible = "efi,x86-payload"; + + aliases { + serial0 = &serial; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + }; + + efi-fb { + compatible = "efi-fb"; + }; +}; diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index f7b32a5eb16..4ab75049315 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -10,6 +10,7 @@ /* This is a declaration for ucode_base in start.S */ extern u32 ucode_base; +extern u32 ucode_size; /** * microcode_update_intel() - Apply microcode updates diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 717f6cb8e01..dbcea7f47ff 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h @@ -16,7 +16,8 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; -#if CONFIG_IS_ENABLED(X86_64) +/* checking against __x86_64__ covers both 64-bit EFI stub and 64-bit U-Boot */ +#if defined(__x86_64__) typedef unsigned long __kernel_size_t; typedef long __kernel_ssize_t; #else diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h index f25975fe1d1..49c36c1cc88 100644 --- a/arch/x86/include/asm/setjmp.h +++ b/arch/x86/include/asm/setjmp.h @@ -8,6 +8,21 @@ #ifndef __setjmp_h #define __setjmp_h +#ifdef CONFIG_X86_64 + +struct jmp_buf_data { + unsigned long __rip; + unsigned long __rsp; + unsigned long __rbp; + unsigned long __rbx; + unsigned long __r12; + unsigned long __r13; + unsigned long __r14; + unsigned long __r15; +}; + +#else + struct jmp_buf_data { unsigned int __ebx; unsigned int __esp; @@ -17,6 +32,8 @@ struct jmp_buf_data { unsigned int __eip; }; +#endif + int setjmp(struct jmp_buf_data *jmp_buf); void longjmp(struct jmp_buf_data *jmp_buf, int val); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 0e054da1e9e..ba07ac728f6 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -14,7 +14,6 @@ endif obj-y += cmd_boot.o obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o -obj-$(CONFIG_EFI) += efi/ obj-y += e820.o obj-y += init_helpers.o obj-y += interrupts.o diff --git a/arch/x86/lib/crt0_x86_64_efi.S b/arch/x86/lib/crt0_x86_64_efi.S index 989799fb4a1..bb8d3cf8a9f 100644 --- a/arch/x86/lib/crt0_x86_64_efi.S +++ b/arch/x86/lib/crt0_x86_64_efi.S @@ -3,7 +3,7 @@ * crt0-efi-x86_64.S - x86_64 EFI startup code. * Copyright (C) 1999 Hewlett-Packard Co. * Contributed by David Mosberger <davidm@hpl.hp.com>. - * Copyright (C) 2005 Intel Co. + * Copyright (C) 2005 Intel Corporation * Contributed by Fenghua Yu <fenghua.yu@intel.com>. * * All rights reserved. @@ -14,26 +14,28 @@ .globl _start _start: subq $8, %rsp + pushq %rcx pushq %rdx -0: - lea image_base(%rip), %rdi - lea _DYNAMIC(%rip), %rsi + mov %rcx, %r8 + mov %rdx, %r9 + + lea image_base(%rip), %rcx + lea _DYNAMIC(%rip), %rdx - popq %rcx - popq %rdx - pushq %rcx - pushq %rdx call _relocate - popq %rdi - popq %rsi + popq %rdx + popq %rcx + + testq %rax, %rax + jnz .exit call efi_main +.exit: addq $8, %rsp -.exit: ret /* diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index 9a9ec991ca9..8b34f677d96 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <efi_loader.h> #include <asm/e820.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,3 +35,41 @@ __weak unsigned int install_e820_map(unsigned int max_entries, return 4; } + +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) +void efi_add_known_memory(void) +{ + struct e820_entry e820[E820MAX]; + unsigned int i, num; + u64 start, pages; + int type; + + num = install_e820_map(ARRAY_SIZE(e820), e820); + + for (i = 0; i < num; ++i) { + start = e820[i].addr; + pages = ALIGN(e820[i].size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT; + + switch (e820[i].type) { + case E820_RAM: + type = EFI_CONVENTIONAL_MEMORY; + break; + case E820_RESERVED: + type = EFI_RESERVED_MEMORY_TYPE; + break; + case E820_ACPI: + type = EFI_ACPI_RECLAIM_MEMORY; + break; + case E820_NVS: + type = EFI_ACPI_MEMORY_NVS; + break; + case E820_UNUSABLE: + default: + type = EFI_UNUSABLE_MEMORY; + break; + } + + efi_add_memory_map(start, pages, type, false); + } +} +#endif /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */ diff --git a/arch/x86/lib/efi/Makefile b/arch/x86/lib/efi/Makefile deleted file mode 100644 index f6c65235e25..00000000000 --- a/arch/x86/lib/efi/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-$(CONFIG_EFI_STUB) += car.o -obj-$(CONFIG_EFI_STUB) += efi.o diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S index 549d863070b..48edc8362a7 100644 --- a/arch/x86/lib/fsp/fsp_car.S +++ b/arch/x86/lib/fsp/fsp_car.S @@ -102,8 +102,10 @@ temp_ram_init_params: _dt_ucode_base_size: /* These next two fields are filled in by ifdtool */ .globl ucode_base -ucode_base: /* Declared in micrcode.h */ +ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ .long 0 /* microcode size */ .long CONFIG_SYS_MONITOR_BASE /* code region base */ .long CONFIG_SYS_MONITOR_LEN /* code region size */ diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig index fac562ad4fa..35d58fcd019 100644 --- a/board/advantech/som-db5800-som-6867/Kconfig +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -13,12 +13,11 @@ config SYS_CONFIG_NAME default "som-db5800-som-6867" config SYS_TEXT_BASE - default 0xfff00000 if !EFI_STUB - default 0x01110000 if EFI_STUB + default 0xfff00000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select X86_RESET_VECTOR if !EFI_STUB + select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 select BOARD_EARLY_INIT_F diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c index e89bf773cc7..ccab1272c59 100644 --- a/board/amlogic/libretech-cc/libretech-cc.c +++ b/board/amlogic/libretech-cc/libretech-cc.c @@ -32,10 +32,6 @@ int misc_init_r(void) meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, MESON_GXL_USE_INTERNAL_RMII_PHY); - /* Enable power and clock gate */ - setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH); - clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index 1b7fd8199bb..c47b9ce9cb7 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -30,9 +30,6 @@ int misc_init_r(void) meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - /* Enable power and clock gate */ - setbits_le32(GX_GCLK_MPEG_0, GX_GCLK_MPEG_0_I2C); - /* Reset PHY on GPIOZ_14 */ clrbits_le32(GX_GPIO_EN(3), BIT(14)); clrbits_le32(GX_GPIO_OUT(3), BIT(14)); diff --git a/board/aries/m28evk/Kconfig b/board/aries/m28evk/Kconfig deleted file mode 100644 index ab5577cf742..00000000000 --- a/board/aries/m28evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M28EVK - -config SYS_BOARD - default "m28evk" - -config SYS_VENDOR - default "aries" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "m28evk" - -endif diff --git a/board/aries/m28evk/MAINTAINERS b/board/aries/m28evk/MAINTAINERS deleted file mode 100644 index aad6313dbe9..00000000000 --- a/board/aries/m28evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M28EVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: board/aries/m28evk/ -F: include/configs/m28evk.h -F: configs/m28evk_defconfig diff --git a/board/aries/m28evk/Makefile b/board/aries/m28evk/Makefile deleted file mode 100644 index fc642e08368..00000000000 --- a/board/aries/m28evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := m28evk.o -else -obj-y := spl_boot.o -endif diff --git a/board/aries/m28evk/README b/board/aries/m28evk/README deleted file mode 100644 index 9f0d9954521..00000000000 --- a/board/aries/m28evk/README +++ /dev/null @@ -1,13 +0,0 @@ -Aries M28EVK -============ - -Files of the M28/M28EVK port ----------------------------- - -arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 -arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/aries/m28evk/ - M28EVK board specific files -include/configs/m28evk.h - M28EVK configuration file - -Follow the instructions from doc/README.mxs to generate a bootable SD card or to -boot from NAND flash. diff --git a/board/aries/m28evk/m28evk.c b/board/aries/m28evk/m28evk.c deleted file mode 100644 index ba8cc902178..00000000000 --- a/board/aries/m28evk/m28evk.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Aries M28 module - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | - MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); - gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); - - mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 | - MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); - gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0); -#endif - - return 0; -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int m28_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10); -} - -int board_mmc_init(bd_t *bis) -{ - /* Configure WP as input. */ - gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); - /* Turn on the power to the card. */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET - -#define MII_OPMODE_STRAP_OVERRIDE 0x16 -#define MII_PHY_CTRL1 0x1e -#define MII_PHY_CTRL2 0x1f - -int fecmxc_mii_postcall(int phy) -{ -#if defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10) - /* KZ8031 PHY on old boards. */ - const uint32_t freq = 0x0080; -#else - /* KZ8021 PHY on new boards. */ - const uint32_t freq = 0x0000; -#endif - - miiphy_write("FEC1", phy, MII_BMCR, 0x9000); - miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); - if (phy == 3) - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - if (ret) - return ret; - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, - CLKCTRL_ENET_TIME_SEL_RMII_CLK); - -#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10) - /* Reset the new PHY */ - gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); - udelay(10000); - gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1); - udelay(10000); -#endif - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - printf("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC0 mii postcall\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC1"); - if (!dev) { - printf("FEC MXS: Unable to get FEC1 device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC1 mii postcall\n"); - return ret; - } - - return ret; -} - -#endif diff --git a/board/aries/m28evk/spl_boot.c b/board/aries/m28evk/spl_boot.c deleted file mode 100644 index ddec8dca6e7..00000000000 --- a/board/aries/m28evk/spl_boot.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * ARIES M28 Boot setup - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* LED */ - MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED, - - /* framebuffer */ - MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - - /* UART1 */ -#ifdef CONFIG_ARIES_M28_V10 - MX28_PAD_AUART0_CTS__DUART_RX, - MX28_PAD_AUART0_RTS__DUART_TX, -#else - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, -#endif - MX28_PAD_AUART0_TX__DUART_RTS, - MX28_PAD_AUART0_RX__DUART_CTS, - - /* UART2 */ - MX28_PAD_AUART1_RX__AUART1_RX, - MX28_PAD_AUART1_TX__AUART1_TX, - MX28_PAD_AUART1_RTS__AUART1_RTS, - MX28_PAD_AUART1_CTS__AUART1_CTS, - - /* CAN */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - - /* TSC2007 */ - MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */ - MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */ - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC Ethernet */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, -#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10) - MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */ -#endif - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/aries/m53evk/Kconfig b/board/aries/m53evk/Kconfig deleted file mode 100644 index 2d49b409126..00000000000 --- a/board/aries/m53evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M53EVK - -config SYS_BOARD - default "m53evk" - -config SYS_VENDOR - default "aries" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "m53evk" - -endif diff --git a/board/aries/m53evk/MAINTAINERS b/board/aries/m53evk/MAINTAINERS deleted file mode 100644 index 73a68cf5aa1..00000000000 --- a/board/aries/m53evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M53EVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: board/aries/m53evk/ -F: include/configs/m53evk.h -F: configs/m53evk_defconfig diff --git a/board/aries/m53evk/Makefile b/board/aries/m53evk/Makefile deleted file mode 100644 index c0a400416a8..00000000000 --- a/board/aries/m53evk/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Aries M53EVK -# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - -obj-y := m53evk.o diff --git a/board/aries/m53evk/imximage.cfg b/board/aries/m53evk/imximage.cfg deleted file mode 100644 index 91649ec5d81..00000000000 --- a/board/aries/m53evk/imximage.cfg +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aries M53 DRAM init values - * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <asm/mach-imx/imximage.cfg> - -/* image version */ -IMAGE_VERSION 2 - - -/* Boot Offset 0x400, valid for both SD and NAND boot. */ -BOOT_OFFSET FLASH_OFFSET_STANDARD - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ -DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ -DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ -DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ - -DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ -DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ -DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ - -DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ -DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ -DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ - -DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ -DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ -DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ - -DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ -DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ -DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ - -DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ -DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ - -DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ -DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ -DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ -DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ - -DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ -DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ - -/* ESDCTL */ -DATA 4 0x63fd9088 0x32383535 -DATA 4 0x63fd9090 0x40383538 -DATA 4 0x63fd907c 0x0136014d -DATA 4 0x63fd9080 0x01510141 - -DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0xc3190000 -DATA 4 0x63fd900c 0x555952e3 -DATA 4 0x63fd9010 0xb68e8b63 -DATA 4 0x63fd9014 0x01ff00db -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f0e21 -DATA 4 0x63fd9008 0x12273030 -DATA 4 0x63fd9004 0x0002002d -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 -DATA 4 0x63fd901c 0x04008040 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 -DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 -DATA 4 0x63fd9040 0x04b80003 -DATA 4 0x63fd9058 0x00022227 -DATA 4 0x63fd901c 0x00000000 diff --git a/board/aries/m53evk/m53evk.c b/board/aries/m53evk/m53evk.c deleted file mode 100644 index 77ba69c7056..00000000000 --- a/board/aries/m53evk/m53evk.c +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Aries M53 module - * - * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx53.h> -#include <asm/mach-imx/mx5_video.h> -#include <asm/spl.h> -#include <linux/errno.h> -#include <netdev.h> -#include <i2c.h> -#include <mmc.h> -#include <spl.h> -#include <fsl_esdhc.h> -#include <asm/gpio.h> -#include <usb/ehci-ci.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> - -/* Special MXCFB sync flags are here. */ -#include "../drivers/video/mxcfb.h" - -DECLARE_GLOBAL_DATA_PTR; - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - if (port == 0) { - /* USB OTG PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); - gpio_direction_output(IMX_GPIO_NR(1, 4), 0); - - /* USB OTG Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); - } else if (port == 1) { - /* USB Host PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); - gpio_direction_output(IMX_GPIO_NR(1, 2), 0); - - /* USB Host Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); - } - - return 0; -} -#endif - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - /* MDIO pads */ - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - - /* FEC 0 pads */ - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - - /* FEC 1 pads */ - NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg = { - MMC_SDHC1_BASE_ADDR, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); - gpio_direction_input(IMX_GPIO_NR(1, 1)); - - return !gpio_get_value(IMX_GPIO_NR(1, 1)); -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - - MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */ - }; - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - - /* GPIO 2_31 is SD power */ - gpio_direction_output(IMX_GPIO_NR(2, 31), 0); - - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} -#endif - -#ifdef CONFIG_VIDEO -static struct fb_videomode const ampire_wvga = { - .name = "Ampire", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 29851, /* picosecond (33.5 MHz) */ - .left_margin = 89, - .right_margin = 164, - .upper_margin = 23, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 10, - .sync = FB_SYNC_CLK_LAT_FALL, -}; - -int board_video_skip(void) -{ - int ret; - ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); - if (ret) - printf("Ampire LCD cannot be configured: %d\n", ret); - return ret; -} -#endif - -#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -static void setup_iomux_video(void) -{ - static const iomux_v3_cfg_t lcd_pads[] = { - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, - MX53_PAD_EIM_DA15__IPU_DI1_PIN1, - MX53_PAD_EIM_DA11__IPU_DI1_PIN2, - MX53_PAD_EIM_DA12__IPU_DI1_PIN3, - MX53_PAD_EIM_A25__IPU_DI1_PIN12, - MX53_PAD_EIM_DA10__IPU_DI1_PIN15, - }; - - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); -} - -static void setup_iomux_nand(void) -{ - static const iomux_v3_cfg_t nand_pads[] = { - NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, - PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, - PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); -} - -static void m53_set_clock(void) -{ - int ret; - const uint32_t ref_clk = MXC_HCLK; - const uint32_t dramclk = 400; - uint32_t cpuclk; - - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); - gpio_direction_input(IMX_GPIO_NR(4, 0)); - - /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ - cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; - - ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); - if (ret) - printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); - - ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); - if (ret) { - printf("CPU: Switch peripheral clock to %dMHz failed\n", - dramclk); - } - - ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); - if (ret) - printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); -} - -static void m53_set_nand(void) -{ - u32 i; - - /* NAND flash is muxed on ATA pins */ - setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); - - /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ - for (i = 0x4; i < 0x94; i += 0x18) { - clrbits_le32(WEIM_BASE_ADDR + i, - WEIM_GCR2_MUX16_BYP_GRANT_MASK); - } - - mxc_set_clock(0, 33, MXC_NFC_CLK); - enable_nfc_clk(1); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_fec(); - setup_iomux_i2c(); - setup_iomux_nand(); - setup_iomux_video(); - - m53_set_clock(); - - mxc_set_sata_internal_clock(); - - /* NAND clock @ 33MHz */ - m53_set_nand(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: Aries M53EVK\n"); - - return 0; -} - -/* - * NAND SPL - */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ - setup_iomux_nand(); - m53_set_clock(); - m53_set_nand(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NAND; -} -#endif diff --git a/board/aries/ma5d4evk/Kconfig b/board/aries/ma5d4evk/Kconfig deleted file mode 100644 index 56b4f4a1a8c..00000000000 --- a/board/aries/ma5d4evk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MA5D4EVK - -config SYS_BOARD - default "ma5d4evk" - -config SYS_VENDOR - default "aries" - -config SYS_CONFIG_NAME - default "ma5d4evk" - -endif diff --git a/board/aries/ma5d4evk/MAINTAINERS b/board/aries/ma5d4evk/MAINTAINERS deleted file mode 100644 index a2fab52dfca..00000000000 --- a/board/aries/ma5d4evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -Aries MA5D4EVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: board/aries/ma5d4evk/ -F: include/configs/ma5d4evk.h -F: configs/ma5d4evk_defconfig diff --git a/board/aries/ma5d4evk/Makefile b/board/aries/ma5d4evk/Makefile deleted file mode 100644 index 15fc2946d8c..00000000000 --- a/board/aries/ma5d4evk/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2015 Marek Vasut <marex@denx.de> - -obj-y += ma5d4evk.o diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c deleted file mode 100644 index c2b6845edc9..00000000000 --- a/board/aries/ma5d4evk/ma5d4evk.c +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/atmel_usba_udc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/clk.h> -#include <asm/arch/sama5d3_smc.h> -#include <asm/arch/sama5d4.h> -#include <atmel_hlcdc.h> -#include <atmel_mci.h> -#include <lcd.h> -#include <mmc.h> -#include <net.h> -#include <netdev.h> -#include <spi.h> -#include <spi_flash.h> -#include <spl.h> -#include <version.h> - -DECLARE_GLOBAL_DATA_PTR; - -static u8 boot_mode_sf; - -/* FIXME gpio code here need to handle through DM_GPIO */ -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); -} - -static void ma5d4evk_spi0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ - - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif /* CONFIG_DM_SPI */ - -#ifdef CONFIG_CMD_USB -static void ma5d4evk_usb_hw_init(void) -{ - at91_set_pio_output(AT91_PIO_PORTE, 11, 0); - at91_set_pio_output(AT91_PIO_PORTE, 14, 0); -} -#endif - -#ifdef CONFIG_LCD -vidinfo_t panel_info = { - .vl_col = 800, - .vl_row = 480, - .vl_clk = 33500000, - .vl_bpix = LCD_BPP, - .vl_tft = 1, - .vl_hsync_len = 10, - .vl_left_margin = 89, - .vl_right_margin = 164, - .vl_vsync_len = 10, - .vl_upper_margin = 23, - .vl_lower_margin = 10, - .mmio = ATMEL_BASE_LCDC, -}; - -/* No power up/down pin for the LCD pannel */ -void lcd_enable(void) { /* Empty! */ } -void lcd_disable(void) { /* Empty! */ } - -unsigned int has_lcdc(void) -{ - return 1; -} - -static void ma5d4evk_lcd_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ - - at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_LCDC); -} - -#endif /* CONFIG_LCD */ - -#ifdef CONFIG_GENERIC_ATMEL_MCI -/* On-SoM eMMC */ -void ma5d4evk_mci0_hw_init(void) -{ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the internal pull - * down to save the power. - */ - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI0); -} - -/* On-board MicroSD slot */ -void ma5d4evk_mci1_hw_init(void) -{ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the internal pull - * down to save the power. - */ - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); - - /* Deal with WP pin on the microSD slot. */ - at91_set_pio_output(AT91_PIO_PORTE, 16, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI1); -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - void *mci0 = (void *)ATMEL_BASE_MCI0; - void *mci1 = (void *)ATMEL_BASE_MCI1; - - /* De-assert reset on On-SoM eMMC */ - at91_set_pio_output(AT91_PIO_PORTE, 15, 1); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); - - ret = atmel_mci_init(boot_mode_sf ? mci0 : mci1); - if (ret) /* eMMC init failed, skip it. */ - at91_set_pio_output(AT91_PIO_PORTE, 15, 0); - - /* Enable the power supply to On-board MicroSD */ - at91_set_pio_output(AT91_PIO_PORTE, 17, 0); - ret = atmel_mci_init(boot_mode_sf ? mci1 : mci0); - if (ret) /* uSD init failed, power it down. */ - at91_set_pio_output(AT91_PIO_PORTE, 17, 1); - - return 0; -} -#endif /* CONFIG_GENERIC_ATMEL_MCI */ - -#ifdef CONFIG_MACB -void ma5d4evk_macb0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC0); -} -#endif - -static void ma5d4evk_serial_hw_init(void) -{ - /* USART0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ - at91_periph_clk_enable(ATMEL_ID_USART0); - - /* USART1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ - at91_periph_clk_enable(ATMEL_ID_USART1); -} - -int board_early_init_f(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - - /* Configure LEDs as OFF */ - at91_set_pio_output(AT91_PIO_PORTD, 28, 0); - at91_set_pio_output(AT91_PIO_PORTD, 29, 0); - at91_set_pio_output(AT91_PIO_PORTD, 30, 0); - - ma5d4evk_serial_hw_init(); - - return 0; -} - -static void board_identify(void) -{ - struct spi_flash *sf; - sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); - boot_mode_sf = (sf != NULL); -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifndef CONFIG_DM_SPI - ma5d4evk_spi0_hw_init(); -#endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - ma5d4evk_mci0_hw_init(); - ma5d4evk_mci1_hw_init(); -#endif -#ifdef CONFIG_MACB - ma5d4evk_macb0_hw_init(); -#endif -#ifdef CONFIG_LCD - ma5d4evk_lcd_hw_init(); -#endif -#ifdef CONFIG_CMD_USB - ma5d4evk_usb_hw_init(); -#endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif - - board_identify(); - - /* Reset CAN controllers */ - at91_set_pio_output(AT91_PIO_PORTB, 21, 0); - udelay(100); - at91_set_pio_output(AT91_PIO_PORTB, 21, 1); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); - - return 0; -} - -int board_late_init(void) -{ - env_set("bootmode", boot_mode_sf ? "sf" : "emmc"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - -/* SPL */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ -#ifndef CONFIG_DM_SPI - ma5d4evk_spi0_hw_init(); -#endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - ma5d4evk_mci0_hw_init(); - ma5d4evk_mci1_hw_init(); -#endif - board_identify(); -} - -void board_boot_order(u32 *spl_boot_list) -{ - spl_boot_list[0] = spl_boot_device(); - - switch (spl_boot_list[0]) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - spl_boot_list[0] = BOOT_DEVICE_MMC1; - break; - case BOOT_DEVICE_SPI: - break; - case BOOT_DEVICE_USB: - spl_boot_list[0] = BOOT_DEVICE_MMC2; - break; - } -} - -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_13 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | - ATMEL_MPDDRC_CR_NB_8BANKS | - ATMEL_MPDDRC_CR_NDQS_DISABLED | - ATMEL_MPDDRC_CR_UNAL_SUPPORTED); - - ddr2->rtr = 0x2b0; - - ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | - 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | - 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | - 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | - 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct atmel_mpddrc_config ddr2; - - ddr2_conf(&ddr2); - - /* enable MPDDR clock */ - at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(AT91_PMC_DDR, &pmc->scer); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); -} - -void at91_pmc_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = AT91_PMC_PLLAR_29 | - AT91_PMC_PLLXR_PLLCOUNT(0x3f) | - AT91_PMC_PLLXR_MUL(87) | - AT91_PMC_PLLXR_DIV(1); - at91_plla_init(tmp); - - writel(0x0 << 8, &pmc->pllicpr); - - tmp = AT91_PMC_MCKR_H32MXDIV | - AT91_PMC_MCKR_PLLADIV_2 | - AT91_PMC_MCKR_MDIV_3 | - AT91_PMC_MCKR_CSS_PLLA; - at91_mck_init(tmp); -} -#endif diff --git a/board/aries/mcvevk/MAINTAINERS b/board/aries/mcvevk/MAINTAINERS deleted file mode 100644 index 0b719a154c0..00000000000 --- a/board/aries/mcvevk/MAINTAINERS +++ /dev/null @@ -1,5 +0,0 @@ -Aries MCVEVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: include/configs/socfpga_mcvevk.h -F: configs/socfpga_mcvevk_defconfig diff --git a/board/aries/mcvevk/Makefile b/board/aries/mcvevk/Makefile deleted file mode 100644 index e1c8a6b3c7c..00000000000 --- a/board/aries/mcvevk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> - -obj-y := socfpga.o diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h deleted file mode 100644 index e233d02b97d..00000000000 --- a/board/aries/mcvevk/qts/iocsr_config.h +++ /dev/null @@ -1,659 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA IOCSR configuration - */ - -#ifndef __SOCFPGA_IOCSR_CONFIG_H__ -#define __SOCFPGA_IOCSR_CONFIG_H__ - -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 - -const unsigned long iocsr_scan_chain0_table[] = { - 0x00000000, - 0x00000000, - 0x0FF00000, - 0xC0000000, - 0x0000003F, - 0x00008000, - 0x00000000, - 0x18060000, - 0x00000060, - 0x00000000, - 0x00000000, - 0x00004000, - 0x0C0300C0, - 0x00000000, - 0x0C000000, - 0x0000C030, - 0x0000C030, - 0x00002000, - 0x06018060, - 0x06018000, - 0x06000018, - 0x00006018, - 0x01806018, - 0x00001000, -}; - -const unsigned long iocsr_scan_chain1_table[] = { - 0x000C0300, - 0x300C0000, - 0x300000C0, - 0x000000C0, - 0x000300C0, - 0x00008000, - 0x00060180, - 0x18060000, - 0x18000000, - 0x00000060, - 0x00018060, - 0x00004000, - 0x000300C0, - 0x0C030000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x00018060, - 0x06018000, - 0x01FE0000, - 0xF8000000, - 0x00000007, - 0x00001000, - 0x0300C030, - 0x00000000, - 0x03000000, - 0x0000000C, - 0x00000000, - 0x00000800, - 0x00006018, - 0x01806000, - 0x00000000, - 0x00000000, - 0x00001806, - 0x00000400, - 0x0000300C, - 0x00C03000, - 0x00C00000, - 0x00000003, - 0x00000C03, - 0x00000200, - 0x00001806, - 0x00601800, - 0x80600000, - 0x80000001, - 0x00000601, - 0x00000100, - 0x00001000, - 0x00300C00, - 0xC0300000, - 0xC0000000, - 0x00000300, - 0x00000080, -}; - -const unsigned long iocsr_scan_chain2_table[] = { - 0x300C0300, - 0x00000000, - 0x0FF00000, - 0x00000000, - 0x0C0300C0, - 0x00008000, - 0x00060180, - 0x00000000, - 0x18000000, - 0x00018060, - 0x06018060, - 0x00004000, - 0x200300C0, - 0x0C030000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x00018060, - 0x00000000, - 0x06000000, - 0x00010018, - 0x01806018, - 0x00001000, - 0x0000C030, - 0x00000000, - 0x03000000, - 0x0000000C, - 0x00C0300C, - 0x00000800, -}; - -const unsigned long iocsr_scan_chain3_table[] = { - 0x0C420D80, - 0x0C3000FF, - 0x0A804001, - 0x07900000, - 0x08020000, - 0x00100000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0x20430000, - 0x0C003001, - 0x00C00481, - 0x00000000, - 0x00000021, - 0x82000004, - 0x05400000, - 0x03C80000, - 0x04010000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x90218000, - 0x86001800, - 0x00600240, - 0x80090218, - 0x00000001, - 0x40000002, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x4810C000, - 0x43000C00, - 0x00300120, - 0xC004810C, - 0x12043000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000010, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0xC0680A28, - 0x45034030, - 0x12481A01, - 0x80A280D0, - 0x34030C06, - 0x01A01450, - 0x280D0000, - 0x30C0680A, - 0x02490340, - 0xD000001A, - 0x0680A280, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x18000000, - 0x01800902, - 0x00240860, - 0x007F8006, - 0x00000000, - 0x0A800001, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0x20430000, - 0x0C003001, - 0x00C00481, - 0x00000FF0, - 0x4810C000, - 0x80000C00, - 0x05400000, - 0x02480000, - 0x04000000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x90218000, - 0x86001800, - 0x00600240, - 0x80090218, - 0x24086001, - 0x40000600, - 0x02A00040, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x4810C000, - 0x43000C00, - 0x00300120, - 0xC004810C, - 0x12043000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000010, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0xC0680A28, - 0x49034030, - 0x12481A02, - 0x80A280D0, - 0x34030C06, - 0x01A00040, - 0x280D0002, - 0x30C0680A, - 0x02490340, - 0xD00A281A, - 0x0680A280, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x18000000, - 0x01800902, - 0x00240860, - 0x007F8006, - 0x00000000, - 0x99300001, - 0x34343400, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A890, - 0xAA0D4000, - 0x01C3A800, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x01000000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x2043090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA24, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x18864000, - 0x49247A06, - 0x9A28A3D7, - 0xF511451E, - 0x0356E388, - 0x821A0000, - 0x0000D000, - 0x05140680, - 0xD749247A, - 0x1E9A28A3, - 0x88F51145, - 0x00034EE3, - 0x00080000, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00003FC2, - 0x00820000, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A890, - 0xAA0D4000, - 0x01C3A800, - 0x00040000, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00800000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA24, - 0x2A835000, - 0x0070EA00, - 0x00015000, - 0x0000F200, - 0x00000000, - 0x00000482, - 0x86120800, - 0x00600240, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x18864000, - 0x49247A06, - 0xEBCF23D7, - 0xF611451E, - 0x034E9248, - 0x821A038E, - 0x0000D000, - 0x00000680, - 0xD749247A, - 0x1E9BCF23, - 0x88F61145, - 0x00034EE3, - 0x00080000, - 0x00001000, - 0x00080000, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00000002, - 0x00820004, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A890, - 0xAA0D4000, - 0x01C3A800, - 0x00040000, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00800000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x2043090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010000, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00200000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x18864000, - 0x49247A06, - 0x9A28A3D7, - 0xF431451E, - 0x034E9248, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD749247A, - 0x1E9A28A3, - 0x88F61145, - 0x000356E3, - 0x00080000, - 0x00001000, - 0x00080000, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00000002, - 0x00820004, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0x00040000, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00800000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020000, - 0x00000400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x0000090C, - 0x00001000, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00400000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F1690D, - 0x1A041414, - 0x00D00000, - 0x08864000, - 0x49247A02, - 0xEBCF23DB, - 0xF431451E, - 0x0356E388, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD749247A, - 0x1EEBCF23, - 0x88F43E79, - 0x000356A2, - 0x00080000, - 0x00001000, - 0x00080000, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00000002, - 0x00820004, - 0x00489800, - 0x801A1A1A, - 0x00000200, - 0x80000004, - 0x00000200, - 0x80000004, - 0x00000200, - 0x00000004, - 0x00000200, - 0x00000004, - 0x00040000, - 0x10000000, - 0x00000000, - 0x00004000, - 0x00010000, - 0x40002080, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x00020000, - 0x00000000, - 0x00000008, - 0x00000020, - 0x00008000, - 0x20001040, - 0x00000080, - 0x20000001, - 0x00000080, - 0x20000001, - 0x00000080, - 0x20000001, - 0x00000080, - 0x00000001, - 0x00010000, - 0x04000000, - 0x00FF0000, - 0x00000000, - 0x00004000, - 0x00000800, - 0xC0000001, - 0x00041419, - 0x40000000, - 0x04000816, - 0x000D0000, - 0x00006800, - 0x00000340, - 0xD000001A, - 0x06800000, - 0x00340000, - 0x0001A000, - 0x00000D00, - 0x40000068, - 0x1A000003, - 0x00D00000, - 0x00068000, - 0x00003400, - 0x000001A0, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000401, - 0x80000008, - 0x0000007F, - 0x20000000, - 0x00000000, - 0xE0000080, - 0x0000001F, - 0x00004000, -}; - - -#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/pinmux_config.h b/board/aries/mcvevk/qts/pinmux_config.h deleted file mode 100644 index 85f892ae473..00000000000 --- a/board/aries/mcvevk/qts/pinmux_config.h +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA PinMux configuration - */ - -#ifndef __SOCFPGA_PINMUX_CONFIG_H__ -#define __SOCFPGA_PINMUX_CONFIG_H__ - -const u8 sys_mgr_init_table[] = { - 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ - 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ - 0, /* EMACIO14 */ - 0, /* EMACIO15 */ - 0, /* EMACIO16 */ - 0, /* EMACIO17 */ - 0, /* EMACIO18 */ - 0, /* EMACIO19 */ - 3, /* FLASHIO0 */ - 0, /* FLASHIO1 */ - 3, /* FLASHIO2 */ - 3, /* FLASHIO3 */ - 3, /* FLASHIO4 */ - 3, /* FLASHIO5 */ - 3, /* FLASHIO6 */ - 3, /* FLASHIO7 */ - 0, /* FLASHIO8 */ - 3, /* FLASHIO9 */ - 3, /* FLASHIO10 */ - 3, /* FLASHIO11 */ - 0, /* GENERALIO0 */ - 1, /* GENERALIO1 */ - 1, /* GENERALIO2 */ - 0, /* GENERALIO3 */ - 0, /* GENERALIO4 */ - 1, /* GENERALIO5 */ - 1, /* GENERALIO6 */ - 1, /* GENERALIO7 */ - 1, /* GENERALIO8 */ - 0, /* GENERALIO9 */ - 0, /* GENERALIO10 */ - 0, /* GENERALIO11 */ - 0, /* GENERALIO12 */ - 2, /* GENERALIO13 */ - 2, /* GENERALIO14 */ - 1, /* GENERALIO15 */ - 1, /* GENERALIO16 */ - 1, /* GENERALIO17 */ - 1, /* GENERALIO18 */ - 0, /* GENERALIO19 */ - 0, /* GENERALIO20 */ - 0, /* GENERALIO21 */ - 0, /* GENERALIO22 */ - 0, /* GENERALIO23 */ - 0, /* GENERALIO24 */ - 0, /* GENERALIO25 */ - 0, /* GENERALIO26 */ - 0, /* GENERALIO27 */ - 0, /* GENERALIO28 */ - 0, /* GENERALIO29 */ - 0, /* GENERALIO30 */ - 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ - 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ - 0, /* MIXED1IO21 */ - 0, /* MIXED2IO0 */ - 0, /* MIXED2IO1 */ - 0, /* MIXED2IO2 */ - 0, /* MIXED2IO3 */ - 0, /* MIXED2IO4 */ - 0, /* MIXED2IO5 */ - 0, /* MIXED2IO6 */ - 0, /* MIXED2IO7 */ - 0, /* GPLINMUX48 */ - 0, /* GPLINMUX49 */ - 0, /* GPLINMUX50 */ - 0, /* GPLINMUX51 */ - 0, /* GPLINMUX52 */ - 0, /* GPLINMUX53 */ - 0, /* GPLINMUX54 */ - 0, /* GPLINMUX55 */ - 0, /* GPLINMUX56 */ - 0, /* GPLINMUX57 */ - 0, /* GPLINMUX58 */ - 0, /* GPLINMUX59 */ - 0, /* GPLINMUX60 */ - 0, /* GPLINMUX61 */ - 0, /* GPLINMUX62 */ - 0, /* GPLINMUX63 */ - 0, /* GPLINMUX64 */ - 0, /* GPLINMUX65 */ - 0, /* GPLINMUX66 */ - 0, /* GPLINMUX67 */ - 0, /* GPLINMUX68 */ - 0, /* GPLINMUX69 */ - 0, /* GPLINMUX70 */ - 1, /* GPLMUX0 */ - 1, /* GPLMUX1 */ - 1, /* GPLMUX2 */ - 1, /* GPLMUX3 */ - 1, /* GPLMUX4 */ - 1, /* GPLMUX5 */ - 1, /* GPLMUX6 */ - 1, /* GPLMUX7 */ - 1, /* GPLMUX8 */ - 1, /* GPLMUX9 */ - 1, /* GPLMUX10 */ - 1, /* GPLMUX11 */ - 1, /* GPLMUX12 */ - 1, /* GPLMUX13 */ - 1, /* GPLMUX14 */ - 1, /* GPLMUX15 */ - 1, /* GPLMUX16 */ - 1, /* GPLMUX17 */ - 1, /* GPLMUX18 */ - 1, /* GPLMUX19 */ - 1, /* GPLMUX20 */ - 1, /* GPLMUX21 */ - 1, /* GPLMUX22 */ - 1, /* GPLMUX23 */ - 1, /* GPLMUX24 */ - 1, /* GPLMUX25 */ - 1, /* GPLMUX26 */ - 1, /* GPLMUX27 */ - 1, /* GPLMUX28 */ - 1, /* GPLMUX29 */ - 1, /* GPLMUX30 */ - 1, /* GPLMUX31 */ - 1, /* GPLMUX32 */ - 1, /* GPLMUX33 */ - 1, /* GPLMUX34 */ - 1, /* GPLMUX35 */ - 1, /* GPLMUX36 */ - 1, /* GPLMUX37 */ - 1, /* GPLMUX38 */ - 1, /* GPLMUX39 */ - 1, /* GPLMUX40 */ - 1, /* GPLMUX41 */ - 1, /* GPLMUX42 */ - 1, /* GPLMUX43 */ - 1, /* GPLMUX44 */ - 1, /* GPLMUX45 */ - 1, /* GPLMUX46 */ - 1, /* GPLMUX47 */ - 1, /* GPLMUX48 */ - 1, /* GPLMUX49 */ - 1, /* GPLMUX50 */ - 1, /* GPLMUX51 */ - 1, /* GPLMUX52 */ - 1, /* GPLMUX53 */ - 1, /* GPLMUX54 */ - 1, /* GPLMUX55 */ - 1, /* GPLMUX56 */ - 1, /* GPLMUX57 */ - 1, /* GPLMUX58 */ - 1, /* GPLMUX59 */ - 1, /* GPLMUX60 */ - 1, /* GPLMUX61 */ - 1, /* GPLMUX62 */ - 1, /* GPLMUX63 */ - 1, /* GPLMUX64 */ - 1, /* GPLMUX65 */ - 1, /* GPLMUX66 */ - 1, /* GPLMUX67 */ - 1, /* GPLMUX68 */ - 1, /* GPLMUX69 */ - 1, /* GPLMUX70 */ - 0, /* NANDUSEFPGA */ - 0, /* UART0USEFPGA */ - 0, /* RGMII1USEFPGA */ - 0, /* SPIS0USEFPGA */ - 0, /* CAN0USEFPGA */ - 0, /* I2C0USEFPGA */ - 0, /* SDMMCUSEFPGA */ - 0, /* QSPIUSEFPGA */ - 0, /* SPIS1USEFPGA */ - 0, /* RGMII0USEFPGA */ - 1, /* UART1USEFPGA */ - 0, /* CAN1USEFPGA */ - 0, /* USB1USEFPGA */ - 0, /* I2C3USEFPGA */ - 0, /* I2C2USEFPGA */ - 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ - 0, /* USB0USEFPGA */ - 0 /* SPIM0USEFPGA */ -}; -#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h deleted file mode 100644 index 4fa868e458f..00000000000 --- a/board/aries/mcvevk/qts/pll_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA Clock and PLL configuration - */ - -#ifndef __SOCFPGA_PLL_CONFIG_H__ -#define __SOCFPGA_PLL_CONFIG_H__ - -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 - -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 - -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 - -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 - -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 - -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 - - -#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h deleted file mode 100644 index fd72926a89e..00000000000 --- a/board/aries/mcvevk/qts/sdram_config.h +++ /dev/null @@ -1,343 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA SDRAM configuration - */ - -#ifndef __SOCFPGA_SDRAM_CONFIG_H__ -#define __SOCFPGA_SDRAM_CONFIG_H__ - -/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 - -/* Sequencer auto configuration */ -#define RW_MGR_ACTIVATE_0_AND_1 0x0D -#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E -#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 -#define RW_MGR_ACTIVATE_1 0x0F -#define RW_MGR_CLEAR_DQS_ENABLE 0x49 -#define RW_MGR_GUARANTEED_READ 0x4C -#define RW_MGR_GUARANTEED_READ_CONT 0x54 -#define RW_MGR_GUARANTEED_WRITE 0x18 -#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B -#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F -#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 -#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D -#define RW_MGR_IDLE 0x00 -#define RW_MGR_IDLE_LOOP1 0x7B -#define RW_MGR_IDLE_LOOP2 0x7A -#define RW_MGR_INIT_RESET_0_CKE_0 0x6F -#define RW_MGR_INIT_RESET_1_CKE_0 0x74 -#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 -#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 -#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 -#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 -#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 -#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 -#define RW_MGR_MRS0_DLL_RESET 0x02 -#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 -#define RW_MGR_MRS0_USER 0x07 -#define RW_MGR_MRS0_USER_MIRR 0x0C -#define RW_MGR_MRS1 0x03 -#define RW_MGR_MRS1_MIRR 0x09 -#define RW_MGR_MRS2 0x04 -#define RW_MGR_MRS2_MIRR 0x0A -#define RW_MGR_MRS3 0x05 -#define RW_MGR_MRS3_MIRR 0x0B -#define RW_MGR_PRECHARGE_ALL 0x12 -#define RW_MGR_READ_B2B 0x59 -#define RW_MGR_READ_B2B_WAIT1 0x61 -#define RW_MGR_READ_B2B_WAIT2 0x6B -#define RW_MGR_REFRESH_ALL 0x14 -#define RW_MGR_RETURN 0x01 -#define RW_MGR_SGLE_READ 0x7D -#define RW_MGR_ZQCL 0x06 - -/* Sequencer defines configuration */ -#define AFI_RATE_RATIO 1 -#define CALIB_LFIFO_OFFSET 7 -#define CALIB_VFIFO_OFFSET 5 -#define ENABLE_SUPER_QUICK_CALIBRATION 0 -#define IO_DELAY_PER_DCHAIN_TAP 25 -#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#define IO_DELAY_PER_OPA_TAP 312 -#define IO_DLL_CHAIN_LENGTH 8 -#define IO_DQDQS_OUT_PHASE_MAX 0 -#define IO_DQS_EN_DELAY_MAX 31 -#define IO_DQS_EN_DELAY_OFFSET 0 -#define IO_DQS_EN_PHASE_MAX 7 -#define IO_DQS_IN_DELAY_MAX 31 -#define IO_DQS_IN_RESERVE 4 -#define IO_DQS_OUT_RESERVE 4 -#define IO_IO_IN_DELAY_MAX 31 -#define IO_IO_OUT1_DELAY_MAX 31 -#define IO_IO_OUT2_DELAY_MAX 0 -#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 -#define MAX_LATENCY_COUNT_WIDTH 5 -#define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 -#define RW_MGR_MEM_ADDRESS_MIRRORING 0 -#define RW_MGR_MEM_DATA_MASK_WIDTH 4 -#define RW_MGR_MEM_DATA_WIDTH 32 -#define RW_MGR_MEM_DQ_PER_READ_DQS 8 -#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 -#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 -#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 -#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 -#define RW_MGR_MEM_NUMBER_OF_RANKS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 -#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 -#define TINIT_CNTR0_VAL 99 -#define TINIT_CNTR1_VAL 32 -#define TINIT_CNTR2_VAL 32 -#define TRESET_CNTR0_VAL 99 -#define TRESET_CNTR1_VAL 99 -#define TRESET_CNTR2_VAL 10 - -/* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { - 0x20700000, - 0x20780000, - 0x10080421, - 0x10080520, - 0x10090044, - 0x100a0008, - 0x100b0000, - 0x10380400, - 0x10080441, - 0x100804c0, - 0x100a0024, - 0x10090010, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -}; - -/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0xa680, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x8000, - 0xa000, - 0xc000, - 0x80000, - 0x80, - 0x8080, - 0xa080, - 0xc080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; - -#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/aries/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c deleted file mode 100644 index f173bf84ac6..00000000000 --- a/board/aries/mcvevk/socfpga.c +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ -#include <common.h> diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig index 9e44413c2ce..64692509fd7 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -12,12 +12,11 @@ config SYS_CONFIG_NAME default "theadorable-x86-conga-qa3-e3845" if TARGET_THEADORABLE_X86_CONGA_QA3_E3845 config SYS_TEXT_BASE - default 0xfff00000 if !EFI_STUB - default 0x01110000 if EFI_STUB + default 0xfff00000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select X86_RESET_VECTOR if !EFI_STUB + select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 select BOARD_EARLY_INIT_F diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index c565ba7831c..5583b45792c 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <environment.h> #include <i2c.h> #include <net.h> @@ -24,6 +25,7 @@ #include <linux/errno.h> #include <hwconfig.h> #include <asm/mach-types.h> +#include <asm/gpio.h> #ifdef CONFIG_MMC_DAVINCI #include <mmc.h> diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig index f92f50a4481..50c7b2a2f42 100644 --- a/board/dfi/dfi-bt700/Kconfig +++ b/board/dfi/dfi-bt700/Kconfig @@ -12,12 +12,11 @@ config SYS_CONFIG_NAME default "theadorable-x86-dfi-bt700" if TARGET_THEADORABLE_X86_DFI_BT700 config SYS_TEXT_BASE - default 0xfff00000 if !EFI_STUB - default 0x01110000 if EFI_STUB + default 0xfff00000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select X86_RESET_VECTOR if !EFI_STUB + select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 select BOARD_EARLY_INIT_F diff --git a/board/efi/Kconfig b/board/efi/Kconfig index 6f86a48fa7f..291bd2ca154 100644 --- a/board/efi/Kconfig +++ b/board/efi/Kconfig @@ -4,16 +4,25 @@ choice prompt "Mainboard model" optional -config TARGET_EFI - bool "efi" +config TARGET_EFI_APP + bool "efi application" help This target is used for running U-Boot on top of EFI. In this case EFI does the early initialisation, and U-Boot takes over once the RAM, video and CPU are fully running. U-Boot is loaded as an application from EFI. +config TARGET_EFI_PAYLOAD + bool "efi payload" + help + This target is used for running U-Boot on top of EFI. In + this case EFI does the early initialisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a payload from EFI. + endchoice -source "board/efi/efi-x86/Kconfig" +source "board/efi/efi-x86_app/Kconfig" +source "board/efi/efi-x86_payload/Kconfig" endif diff --git a/board/efi/efi-x86/MAINTAINERS b/board/efi/efi-x86/MAINTAINERS deleted file mode 100644 index a44c7c64be6..00000000000 --- a/board/efi/efi-x86/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EFI-X86 BOARD -M: Simon Glass <sjg@chromium.org> -S: Maintained -F: board/efi/efi-x86/ -F: include/configs/efi-x86.h -F: configs/efi-x86_defconfig diff --git a/board/efi/efi-x86/Kconfig b/board/efi/efi-x86_app/Kconfig index fa609ba5d21..ae87bf34d37 100644 --- a/board/efi/efi-x86/Kconfig +++ b/board/efi/efi-x86_app/Kconfig @@ -1,7 +1,7 @@ -if TARGET_EFI +if TARGET_EFI_APP config SYS_BOARD - default "efi-x86" + default "efi-x86_app" config SYS_VENDOR default "efi" @@ -10,6 +10,6 @@ config SYS_SOC default "efi" config SYS_CONFIG_NAME - default "efi-x86" + default "efi-x86_app" endif diff --git a/board/efi/efi-x86_app/MAINTAINERS b/board/efi/efi-x86_app/MAINTAINERS new file mode 100644 index 00000000000..fb8a6b1c2fa --- /dev/null +++ b/board/efi/efi-x86_app/MAINTAINERS @@ -0,0 +1,6 @@ +EFI-X86_APP BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/efi/efi-x86_app/ +F: include/configs/efi-x86_app.h +F: configs/efi-x86_app_defconfig diff --git a/board/efi/efi-x86/Makefile b/board/efi/efi-x86_app/Makefile index 209728341be..cb48d1ccc20 100644 --- a/board/efi/efi-x86/Makefile +++ b/board/efi/efi-x86_app/Makefile @@ -2,4 +2,4 @@ # # Copyright (c) 2015 Google, Inc -obj-y += efi.o +obj-y += app.o diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86_app/app.c index da3445bb1d5..da3445bb1d5 100644 --- a/board/efi/efi-x86/efi.c +++ b/board/efi/efi-x86_app/app.c diff --git a/board/efi/efi-x86_payload/Kconfig b/board/efi/efi-x86_payload/Kconfig new file mode 100644 index 00000000000..08dd0c2edd7 --- /dev/null +++ b/board/efi/efi-x86_payload/Kconfig @@ -0,0 +1,40 @@ +if TARGET_EFI_PAYLOAD + +config SYS_BOARD + default "efi-x86_payload" + +config SYS_VENDOR + default "efi" + +config SYS_SOC + default "efi" + +config SYS_CONFIG_NAME + default "efi-x86_payload" + +config SYS_TEXT_BASE + default 0x00200000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_EARLY_INIT_R + imply SYS_NS16550 + imply SCSI + imply SCSI_AHCI + imply AHCI_PCI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply USB_STORAGE + imply USB_KEYBOARD + imply VIDEO_EFI + imply E1000 + imply ETH_DESIGNWARE + imply PCH_GBE + imply RTL8169 + +endif diff --git a/board/efi/efi-x86_payload/MAINTAINERS b/board/efi/efi-x86_payload/MAINTAINERS new file mode 100644 index 00000000000..abf3a1574b0 --- /dev/null +++ b/board/efi/efi-x86_payload/MAINTAINERS @@ -0,0 +1,7 @@ +EFI-X86_PAYLOAD BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/efi/efi-x86_payload/ +F: include/configs/efi-x86_payload.h +F: configs/efi-x86_payload32_defconfig +F: configs/efi-x86_payload64_defconfig diff --git a/board/efi/efi-x86_payload/Makefile b/board/efi/efi-x86_payload/Makefile new file mode 100644 index 00000000000..00ef69534d0 --- /dev/null +++ b/board/efi/efi-x86_payload/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + +obj-y += start.o payload.o diff --git a/board/efi/efi-x86_payload/payload.c b/board/efi/efi-x86_payload/payload.c new file mode 100644 index 00000000000..4eeb49a27ac --- /dev/null +++ b/board/efi/efi-x86_payload/payload.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <usb.h> + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers + */ + pci_init(); + + return 0; +} diff --git a/board/efi/efi-x86_payload/start.S b/board/efi/efi-x86_payload/start.S new file mode 100644 index 00000000000..f7eaa7cb12a --- /dev/null +++ b/board/efi/efi-x86_payload/start.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig index a593f8cdc87..41a27dd933b 100644 --- a/board/emulation/qemu-x86/Kconfig +++ b/board/emulation/qemu-x86/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "qemu-x86" config SYS_TEXT_BASE - default 0xfff00000 if !EFI_STUB && !SUPPORT_SPL - default 0x01110000 if EFI_STUB || SUPPORT_SPL + default 0xfff00000 if !SUPPORT_SPL + default 0x01110000 if SUPPORT_SPL config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select X86_RESET_VECTOR if !EFI_STUB + select X86_RESET_VECTOR select QEMU select BOARD_ROMSIZE_KB_1024 diff --git a/board/emulation/qemu-x86/MAINTAINERS b/board/emulation/qemu-x86/MAINTAINERS index 4cf8ac90e7d..9a99d38ca05 100644 --- a/board/emulation/qemu-x86/MAINTAINERS +++ b/board/emulation/qemu-x86/MAINTAINERS @@ -4,8 +4,6 @@ S: Maintained F: board/emulation/qemu-x86/ F: include/configs/qemu-x86.h F: configs/qemu-x86_defconfig -F: configs/qemu-x86_efi_payload32_defconfig -F: configs/qemu-x86_efi_payload64_defconfig QEMU X86 64-bit BOARD M: Bin Meng <bmeng.cn@gmail.com> diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index fb37403aa12..5dccb17cb27 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -50,8 +50,8 @@ static void setenv_fdt_file(void) env_set("fdt_file", "imx6q-icore-rqs.dtb"); else if (is_mx6dl() || is_mx6solo()) env_set("fdt_file", "imx6dl-icore-rqs.dtb"); - } else if (!strcmp(cmp_dtb, "imx6ul-geam-kit")) - env_set("fdt_file", "imx6ul-geam-kit.dtb"); + } else if (!strcmp(cmp_dtb, "imx6ul-geam")) + env_set("fdt_file", "imx6ul-geam.dtb"); else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc")) env_set("fdt_file", "imx6ul-isiot-emmc.dtb"); else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc")) diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 470d96aaedb..1a1fe6c66a4 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -43,10 +43,14 @@ int board_fit_config_name_match(const char *name) return 0; else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) return 0; + else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi")) + return 0; else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) return 0; else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) return 0; + else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi")) + return 0; else return -1; } diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS index 8e6079197f2..a44edd4c893 100644 --- a/board/ge/bx50v3/MAINTAINERS +++ b/board/ge/bx50v3/MAINTAINERS @@ -3,6 +3,7 @@ M: Martin Donnelly <martin.donnelly@ge.com> S: Maintained F: board/ge/bx50v3/ F: include/configs/ge_bx50v3.h +F: configs/ge_bx50v3_defconfig F: configs/ge_b450v3_defconfig F: configs/ge_b650v3_defconfig F: configs/ge_b850v3_defconfig diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index a8668e4efc3..543468cab54 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -13,12 +13,11 @@ config SYS_CONFIG_NAME default "minnowmax" config SYS_TEXT_BASE - default 0xfff00000 if !EFI_STUB - default 0x01110000 if EFI_STUB + default 0xfff00000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select X86_RESET_VECTOR if !EFI_STUB + select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 select SPI_FLASH_STMICRO diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd index eac79dc890f..16b93ebe3f7 100644 --- a/board/k+p/bootscripts/tpcboot.cmd +++ b/board/k+p/bootscripts/tpcboot.cmd @@ -23,6 +23,10 @@ setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw" setenv displayargs "" setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \ ${displayargs}" +setenv miscadj " +if test '${boardsoc}' = 'imx53'; then + setenv bootargs '${bootargs} di=${dig_in} key1=${key1}'; +fi;" setenv boot_fitImage " setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb'; setenv itbcfg "\"#\${fdt_conf}\""; @@ -39,6 +43,7 @@ if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \ ${kernel_file}; then run mmcargs; + run miscadj; run boot_fitImage; fi; fi;" @@ -52,6 +57,7 @@ setenv download_kernel "tftpboot ${loadaddr} ${kernel_file}" setenv boot_tftp_kernel " if run download_kernel; then run mmcargs; + run miscadj; run boot_fitImage; fi" diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index c80eed36c62..becb6a63faa 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -22,6 +22,8 @@ #define VBUS_PWR_EN IMX_GPIO_NR(7, 8) #define PHY_nRST IMX_GPIO_NR(7, 6) #define BOOSTER_OFF IMX_GPIO_NR(2, 23) +#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1) +#define KEY1 IMX_GPIO_NR(2, 26) DECLARE_GLOBAL_DATA_PTR; @@ -43,18 +45,6 @@ int dram_init_banksize(void) return 0; } -u32 get_board_rev(void) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank *bank = &iim->bank[0]; - struct fuse_bank0_regs *fuse = - (struct fuse_bank0_regs *)bank->fuse_regs; - - int rev = readl(&fuse->gp[6]); - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} - #ifdef CONFIG_USB_EHCI_MX5 int board_ehci_hcd_init(int port) { @@ -189,10 +179,28 @@ void eth_phy_reset(void) udelay(50); } +void board_disable_display(void) +{ + gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT"); + gpio_direction_output(LCD_BACKLIGHT, 0); +} + +void board_misc_setup(void) +{ + gpio_request(KEY1, "KEY1_GPIO"); + gpio_direction_input(KEY1); + + if (gpio_get_value(KEY1)) + env_set("key1", "off"); + else + env_set("key1", "on"); +} + int board_late_init(void) { int ret = 0; + board_disable_display(); setup_ups(); if (!power_init()) @@ -207,5 +215,7 @@ int board_late_init(void) show_eeprom(); read_board_id(); + board_misc_setup(); + return ret; } diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c index 26575f73bdc..4eb86d8c5d7 100644 --- a/board/liebherr/display5/common.c +++ b/board/liebherr/display5/common.c @@ -34,6 +34,16 @@ void displ5_set_iomux_uart(void) SETUP_IOMUX_PADS(uart_pads); } +iomux_v3_cfg_t const misc_pads_spl[] = { + /* Emergency recovery pin */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void displ5_set_iomux_misc_spl(void) +{ + SETUP_IOMUX_PADS(misc_pads_spl); +} + #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi_pads[] = { /* SPI3 */ diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h index a507ef9ce83..78c64b02e28 100644 --- a/board/liebherr/display5/common.h +++ b/board/liebherr/display5/common.h @@ -37,5 +37,6 @@ void displ5_set_iomux_ecspi_spl(void); void displ5_set_iomux_ecspi(void); void displ5_set_iomux_usdhc_spl(void); void displ5_set_iomux_usdhc(void); +void displ5_set_iomux_misc_spl(void); #endif /* __DISPL5_COMMON_H_ */ diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index ebc643e7e3f..d8383170d2f 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -25,6 +25,7 @@ #include <miiphy.h> #include <netdev.h> #include <i2c.h> +#include <environment.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> @@ -44,6 +45,7 @@ static bool sw_ids_valid; static u32 cpu_id; static u32 unit_id; +#define EM_PAD IMX_GPIO_NR(3, 29) #define SW0 IMX_GPIO_NR(2, 4) #define SW1 IMX_GPIO_NR(2, 5) #define SW2 IMX_GPIO_NR(2, 6) @@ -179,6 +181,9 @@ iomux_v3_cfg_t const misc_pads[] = { /* XTALOSC */ MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Emergency recovery pin */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; #ifdef CONFIG_FSL_ESDHC @@ -250,6 +255,25 @@ static void setup_iomux_enet(void) gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ } +static int setup_mac_from_fuse(void) +{ + unsigned char enetaddr[6]; + int ret; + + ret = eth_env_get_enetaddr("ethaddr", enetaddr); + if (ret) /* ethaddr is already set */ + return 0; + + imx_get_mac_from_fuse(0, enetaddr); + + if (is_valid_ethaddr(enetaddr)) { + eth_env_set_enetaddr("ethaddr", enetaddr); + return 0; + } + + return 0; +} + int board_eth_init(bd_t *bd) { struct phy_device *phydev; @@ -264,6 +288,8 @@ int board_eth_init(bd_t *bd) if (ret) return ret; + setup_mac_from_fuse(); + bus = fec_get_miibus(IMX_FEC_BASE, -1); if (!bus) return -ENODEV; @@ -369,7 +395,22 @@ static inline void setup_boot_modes(void) {} int misc_init_r(void) { + int ret; + setup_boot_modes(); + + ret = gpio_request(EM_PAD, "Emergency_PAD"); + if (ret) { + printf("Can't request emergency PAD gpio\n"); + return ret; + } + + ret = gpio_direction_input(EM_PAD); + if (ret) { + printf("Can't set emergency PAD direction\n"); + return ret; + } + return 0; } diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 6508e0ffa7d..0c0172e2010 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -16,10 +16,12 @@ #include <asm/arch/imx-regs.h> #include "asm/arch/iomux.h" #include <asm/mach-imx/iomux-v3.h> +#include <asm/gpio.h> #include <environment.h> #include <fsl_esdhc.h> #include <netdev.h> #include <bootcount.h> +#include <watchdog.h> #include "common.h" DECLARE_GLOBAL_DATA_PTR; @@ -115,6 +117,49 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } +#ifdef CONFIG_MX6_DDRCAL +static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + struct mx6_mmdc_calibration calibration = {0}; + + mmdc_read_calibration(sysinfo, &calibration); + + debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); + debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); + debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); + debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); + debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); + debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); + debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); + debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); + debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); + debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); + debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); + debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); +} + +static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret; + + /* Perform DDR DRAM calibration */ + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR: Write level calibration error [%d]\n", ret); + return; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR: DQS calibration error [%d]\n", ret); + return; + } + + spl_dram_print_cal(sysinfo); +} +#endif /* CONFIG_MX6_DDRCAL */ + static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { @@ -141,6 +186,10 @@ static void spl_dram_init(void) mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); + +#ifdef CONFIG_MX6_DDRCAL + spl_dram_perform_cal(&sysinfo); +#endif } #ifdef CONFIG_SPL_SPI_SUPPORT @@ -194,10 +243,28 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + displ5_set_iomux_misc_spl(); + + /* Initialize and reset WDT in SPL */ + hw_watchdog_init(); + WATCHDOG_RESET(); + /* load/boot image from boot device */ board_init_r(NULL, 0); } +#define EM_PAD IMX_GPIO_NR(3, 29) +int board_check_emergency_pad(void) +{ + int ret; + + ret = gpio_direction_input(EM_PAD); + if (ret) + return ret; + + return !gpio_get_value(EM_PAD); +} + void board_boot_order(u32 *spl_boot_list) { /* Default boot sequence SPI -> MMC */ @@ -206,12 +273,19 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_UART; spl_boot_list[3] = BOOT_DEVICE_NONE; + /* + * In case of emergency PAD pressed, we always boot + * to proper u-boot and perform recovery tasks there. + */ + if (board_check_emergency_pad()) + return; + #ifdef CONFIG_SPL_ENV_SUPPORT /* 'fastboot' */ const char *s; - env_init(); - env_load(); + if (env_init() || env_load()) + return; s = env_get("BOOT_FROM"); if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) { diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index 4bf0a202e08..7b89c10cc74 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define CPGWPR 0xE6150900 #define CPGWPCR 0xE6150904 -#define CPGWPR 0xE615090C /* PLL */ #define PLL0CR 0xE61500D8 @@ -54,8 +54,9 @@ void s_init(void) int board_early_init_f(void) { - writel(0xA5A5FFFF, CPGWPCR); - writel(0x5A5A0000, CPGWPR); + /* Unlock CPG access */ + writel(0xA5A5FFFF, CPGWPR); + writel(0x5A5A0000, CPGWPCR); /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 1fb3c69edeb..38d89f0130b 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -57,9 +57,58 @@ DECLARE_GLOBAL_DATA_PTR; #define ETH_PHY_RESET IMX_GPIO_NR(4, 15) #define USB_H1_VBUS IMX_GPIO_NR(1, 0) +enum board_type { + CUBOXI = 0x00, + HUMMINGBOARD = 0x01, + HUMMINGBOARD2 = 0x02, + UNKNOWN = 0x03, +}; + +#define MEM_STRIDE 0x4000000 +static u32 get_ram_size_stride_test(u32 *base, u32 maxsize) +{ + volatile u32 *addr; + u32 save[64]; + u32 cnt; + u32 size; + int i = 0; + + /* First save the data */ + for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) { + addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */ + sync (); + save[i++] = *addr; + sync (); + } + + /* First write a signature */ + * (volatile u32 *)base = 0x12345678; + for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) { + * (volatile u32 *)((u32)base + size) = size; + sync (); + if (* (volatile u32 *)((u32)base) == size) { /* We reached the overlapping address */ + break; + } + } + + /* Restore the data */ + for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) { + addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */ + sync (); + *addr = save[i--]; + sync (); + } + + return (size); +} + int dram_init(void) { - gd->ram_size = imx_ddr_size(); + u32 max_size = imx_ddr_size(); + + gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE, + (u32)max_size); + return 0; } @@ -77,10 +126,17 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; -static iomux_v3_cfg_t const hb_cbi_sense[] = { +static iomux_v3_cfg_t const board_detect[] = { /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const som_rev_detect[] = { + /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ + IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00 | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), }; static iomux_v3_cfg_t const usb_pads[] = { @@ -333,88 +389,110 @@ int board_init(void) return ret; } -static bool is_hummingboard(void) +static enum board_type board_type(void) { - int val1, val2; + int val1, val2, val3; - SETUP_IOMUX_PADS(hb_cbi_sense); - - gpio_direction_input(IMX_GPIO_NR(4, 9)); - gpio_direction_input(IMX_GPIO_NR(3, 4)); - - val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); - val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); + SETUP_IOMUX_PADS(board_detect); /* * Machine selection - - * Machine val1, val2 - * ------------------------- - * HB2 x x - * HB rev 3.x x 0 - * CBi 0 1 - * HB 1 1 + * Machine val1, val2, val3 + * ---------------------------- + * HB2 x x 0 + * HB rev 3.x x 0 x + * CBi 0 1 x + * HB 1 1 x */ - if (val2 == 0) - return true; - else if (val1 == 0) - return false; - else - return true; -} + gpio_direction_input(IMX_GPIO_NR(2, 8)); + val3 = gpio_get_value(IMX_GPIO_NR(2, 8)); -static bool is_hummingboard2(void) -{ - int val1; + if (val3 == 0) + return HUMMINGBOARD2; - SETUP_IOMUX_PADS(hb_cbi_sense); + gpio_direction_input(IMX_GPIO_NR(3, 4)); + val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); - gpio_direction_input(IMX_GPIO_NR(2, 8)); + if (val2 == 0) + return HUMMINGBOARD; - val1 = gpio_get_value(IMX_GPIO_NR(2, 8)); + gpio_direction_input(IMX_GPIO_NR(4, 9)); + val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); - /* - * Machine selection - - * Machine val1 - * ------------------- - * HB2 0 - * HB rev 3.x x - * CBi x - * HB x - */ + if (val1 == 0) { + return CUBOXI; + } else { + return HUMMINGBOARD; + } +} + +static bool is_rev_15_som(void) +{ + int val1, val2; + SETUP_IOMUX_PADS(som_rev_detect); + + val1 = gpio_get_value(IMX_GPIO_NR(6, 0)); + val2 = gpio_get_value(IMX_GPIO_NR(6, 4)); - if (val1 == 0) + if (val1 == 1 && val2 == 0) return true; - else - return false; + + return false; } int checkboard(void) { - if (is_hummingboard2()) - puts("Board: MX6 Hummingboard2\n"); - else if (is_hummingboard()) - puts("Board: MX6 Hummingboard\n"); + switch (board_type()) { + case CUBOXI: + puts("Board: MX6 Cubox-i"); + break; + case HUMMINGBOARD: + puts("Board: MX6 HummingBoard"); + break; + case HUMMINGBOARD2: + puts("Board: MX6 HummingBoard2"); + break; + case UNKNOWN: + default: + puts("Board: Unknown\n"); + goto out; + } + + if (is_rev_15_som()) + puts(" (som rev 1.5)\n"); else - puts("Board: MX6 Cubox-i\n"); + puts("\n"); +out: return 0; } int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_hummingboard2()) - env_set("board_name", "HUMMINGBOARD2"); - else if (is_hummingboard()) + switch (board_type()) { + case CUBOXI: + env_set("board_name", "CUBOXI"); + break; + case HUMMINGBOARD: env_set("board_name", "HUMMINGBOARD"); - else + break; + case HUMMINGBOARD2: + env_set("board_name", "HUMMINGBOARD2"); + break; + case UNKNOWN: + default: env_set("board_name", "CUBOXI"); + } if (is_mx6dq()) env_set("board_rev", "MX6Q"); else env_set("board_rev", "MX6DL"); + + if (is_rev_15_som()) + env_set("som_rev", "V15"); #endif return 0; @@ -590,7 +668,7 @@ static struct mx6_ddr3_cfg mem_ddr_4g = { .density = 4, .width = 16, .banks = 8, - .rowaddr = 15, + .rowaddr = 16, .coladdr = 10, .pagesz = 2, .trcd = 1375, diff --git a/board/synopsys/emdk/README b/board/synopsys/emdk/README new file mode 100644 index 00000000000..706b547a9ed --- /dev/null +++ b/board/synopsys/emdk/README @@ -0,0 +1,82 @@ +================================================================================ +Useful notes on bulding and using of U-Boot on ARC EM Development Kit (AKA EMDK) +================================================================================ + + BOARD OVERVIEW + + The DesignWare ARC EM Development Kit is FPGA-bases platform for rapid + software development on the ARC EM family of processors. + + Since this board is based on FPGA it's possible to load and use different + versions of ARC EM CPUs. U-Boot is built to be run on the simplest + possible configuration which means the same one binary will work on more + advanced configurations as well. + + The board has the following features useful for U-Boot: + * On-board 2-channel FTDI TTL-to-USB converter + - The first channel is used for serial debug port (which makes it possible + to use a serial connection on pretty much any host machine be it + Windows, Linux or Mac). + On Linux machine typucally FTDI serial port would be /dev/ttyUSB0. + There's no HW flow-control and baud-rate is 115200. + + - The second channel is used for built-in Digilent USB JTAG probe. + That means no extra hardware is required to access ARC core from a + debugger on development host. Both proprietary MetaWare debugger and + open source OpenOCD + GDB client are supported. + + - Also with help of this FTDI chip it is possible to reset entire + board with help of a special `rff-ftdi-reset` utility, see: + https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset + + * Micro SD-card slot + - U-Boot expects to see the very first partition on the card formatted as + FAT file-system and uses it for keeping its environment in `uboot.env` + file. Note uboot.env is not just a text file but it is auto-generated + file created by U-Boot on invocation of `saveenv` command. + It contains a checksum which makes this saved environment invalid in + case of maual modification. + + - There might be more useful files on that first FAT partition like + user applications, data files etc. + + * 256 KiB of "ROM" + - This so-called "ROM" is a part of FPGA image and even though it + might be unlocked for writes its initial content will be restored + on the next power-on. + + + BUILDING U-BOOT + + 1. Configure U-Boot: + ------------------------->8---------------------- + make emdk_defconfig + ------------------------->8---------------------- + + 2. To build Elf file (for example to be used with host debugger via JTAG + connection to the target board): + ------------------------->8---------------------- + make mdbtrick + ------------------------->8---------------------- + + This will produce `u-boot` Elf file. + + 3. To build binary image to be put in "ROM": + ------------------------->8---------------------- + make u-boot.bin + ------------------------->8---------------------- + + + EXECUTING U-BOOT + + 1. The EMDK board is supposed to auto-start U-Boot image stored in ROM on + power-on. For that make sure VCCIO DIP-switches are all in "off" state. + + 2. Though it is possible to load U-Boot as a simple Elf file via JTAG right + in "ROM" and start it from the debugger. One important note here we first + need to enable writes into "ROM" by writing 1 to 0xf0001000. + + 2.1. In case of proprietary MetaWare debugger run: + ------------------------->8---------------------- + mdb -dll=opxdarc.so -OK -preloadexec="eval *(int*)0xf0001000=0" u-boot + ------------------------->8---------------------- diff --git a/cmd/Kconfig b/cmd/Kconfig index 1eb55e52508..aec209006db 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1121,6 +1121,16 @@ config BOOTP_HOSTNAME help The name may or may not be qualified with the local domain name. +config BOOTP_PREFER_SERVERIP + bool "serverip variable takes precedent over DHCP server IP." + depends on CMD_BOOTP + help + By default a BOOTP/DHCP reply will overwrite the 'serverip' variable. + + With this option enabled, the 'serverip' variable in the environment + takes precedence over DHCP server IP and will only be set by the DHCP + server if not already set in the environment. + config BOOTP_SUBNETMASK bool "Request & store 'netmask' from BOOTP/DHCP server" default y @@ -1239,6 +1249,11 @@ config CMD_PXE help Boot image via network using PXE protocol +config CMD_WOL + bool "wol" + help + Wait for wake-on-lan Magic Packet + endif menu "Misc commands" @@ -1754,6 +1769,22 @@ config CMD_TRACE for analsys (e.g. using bootchart). See doc/README.trace for full details. +config CMD_AVB + bool "avb - Android Verified Boot 2.0 operations" + depends on LIBAVB + default n + help + Enables a "avb" command to perform verification of partitions using + Android Verified Boot 2.0 functionality. It includes such subcommands: + avb init - initialize avb2 subsystem + avb read_rb - read rollback index + avb write_rb - write rollback index + avb is_unlocked - check device lock state + avb get_uuid - read and print uuid of a partition + avb read_part - read data from partition + avb read_part_hex - read data from partition and output to stdout + avb write_part - write data to partition + avb verify - run full verification chain endmenu config CMD_UBI diff --git a/cmd/Makefile b/cmd/Makefile index e0088df33bd..323f1fd2c77 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_CMD_PCI) += pci.o endif obj-y += pcmcia.o obj-$(CONFIG_CMD_PXE) += pxe.o +obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_CMD_QFW) += qfw.o obj-$(CONFIG_CMD_READ) += read.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o @@ -155,6 +156,9 @@ obj-$(CONFIG_CMD_REGULATOR) += regulator.o obj-$(CONFIG_CMD_BLOB) += blob.o +# Android Verified Boot 2.0 +obj-$(CONFIG_CMD_AVB) += avb.o + obj-$(CONFIG_X86) += x86/ endif # !CONFIG_SPL_BUILD diff --git a/cmd/avb.c b/cmd/avb.c new file mode 100644 index 00000000000..f045a0c64c4 --- /dev/null +++ b/cmd/avb.c @@ -0,0 +1,372 @@ + +/* + * (C) Copyright 2018, Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <avb_verify.h> +#include <command.h> +#include <image.h> +#include <malloc.h> +#include <mmc.h> + +#define AVB_BOOTARGS "avb_bootargs" +static struct AvbOps *avb_ops; + +static const char * const requested_partitions[] = {"boot", + "system", + "vendor", + NULL}; + +int do_avb_init(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned long mmc_dev; + + if (argc != 2) + return CMD_RET_USAGE; + + mmc_dev = simple_strtoul(argv[1], NULL, 16); + + if (avb_ops) + avb_ops_free(avb_ops); + + avb_ops = avb_ops_alloc(mmc_dev); + if (avb_ops) + return CMD_RET_SUCCESS; + + return CMD_RET_FAILURE; +} + +int do_avb_read_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *part; + s64 offset; + size_t bytes, bytes_read = 0; + void *buffer; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, please run 'avb init'\n"); + return CMD_RET_USAGE; + } + + if (argc != 5) + return CMD_RET_USAGE; + + part = argv[1]; + offset = simple_strtoul(argv[2], NULL, 16); + bytes = simple_strtoul(argv[3], NULL, 16); + buffer = (void *)simple_strtoul(argv[4], NULL, 16); + + if (avb_ops->read_from_partition(avb_ops, part, offset, bytes, + buffer, &bytes_read) == + AVB_IO_RESULT_OK) { + printf("Read %zu bytes\n", bytes_read); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} + +int do_avb_read_part_hex(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + const char *part; + s64 offset; + size_t bytes, bytes_read = 0; + char *buffer; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, please run 'avb init'\n"); + return CMD_RET_USAGE; + } + + if (argc != 4) + return CMD_RET_USAGE; + + part = argv[1]; + offset = simple_strtoul(argv[2], NULL, 16); + bytes = simple_strtoul(argv[3], NULL, 16); + + buffer = malloc(bytes); + if (!buffer) { + printf("Failed to tlb_allocate buffer for data\n"); + return CMD_RET_FAILURE; + } + memset(buffer, 0, bytes); + + if (avb_ops->read_from_partition(avb_ops, part, offset, bytes, buffer, + &bytes_read) == AVB_IO_RESULT_OK) { + printf("Requested %zu, read %zu bytes\n", bytes, bytes_read); + printf("Data: "); + for (int i = 0; i < bytes_read; i++) + printf("%02X", buffer[i]); + + printf("\n"); + + free(buffer); + return CMD_RET_SUCCESS; + } + + free(buffer); + return CMD_RET_FAILURE; +} + +int do_avb_write_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *part; + s64 offset; + size_t bytes; + void *buffer; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 5) + return CMD_RET_USAGE; + + part = argv[1]; + offset = simple_strtoul(argv[2], NULL, 16); + bytes = simple_strtoul(argv[3], NULL, 16); + buffer = (void *)simple_strtoul(argv[4], NULL, 16); + + if (avb_ops->write_to_partition(avb_ops, part, offset, bytes, buffer) == + AVB_IO_RESULT_OK) { + printf("Wrote %zu bytes\n", bytes); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} + +int do_avb_read_rb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + size_t index; + u64 rb_idx; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 2) + return CMD_RET_USAGE; + + index = (size_t)simple_strtoul(argv[1], NULL, 16); + + if (avb_ops->read_rollback_index(avb_ops, index, &rb_idx) == + AVB_IO_RESULT_OK) { + printf("Rollback index: %llu\n", rb_idx); + return CMD_RET_SUCCESS; + } + return CMD_RET_FAILURE; +} + +int do_avb_write_rb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + size_t index; + u64 rb_idx; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 3) + return CMD_RET_USAGE; + + index = (size_t)simple_strtoul(argv[1], NULL, 16); + rb_idx = simple_strtoul(argv[2], NULL, 16); + + if (avb_ops->write_rollback_index(avb_ops, index, rb_idx) == + AVB_IO_RESULT_OK) + return CMD_RET_SUCCESS; + + return CMD_RET_FAILURE; +} + +int do_avb_get_uuid(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + const char *part; + char buffer[UUID_STR_LEN + 1]; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 2) + return CMD_RET_USAGE; + + part = argv[1]; + + if (avb_ops->get_unique_guid_for_partition(avb_ops, part, buffer, + UUID_STR_LEN + 1) == + AVB_IO_RESULT_OK) { + printf("'%s' UUID: %s\n", part, buffer); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} + +int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag, + int argc, char *const argv[]) +{ + AvbSlotVerifyResult slot_result; + AvbSlotVerifyData *out_data; + char *cmdline; + char *extra_args; + + bool unlocked = false; + int res = CMD_RET_FAILURE; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 1) + return CMD_RET_USAGE; + + printf("## Android Verified Boot 2.0 version %s\n", + avb_version_string()); + + if (avb_ops->read_is_device_unlocked(avb_ops, &unlocked) != + AVB_IO_RESULT_OK) { + printf("Can't determine device lock state.\n"); + return CMD_RET_FAILURE; + } + + slot_result = + avb_slot_verify(avb_ops, + requested_partitions, + "", + unlocked, + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, + &out_data); + + switch (slot_result) { + case AVB_SLOT_VERIFY_RESULT_OK: + /* Until we don't have support of changing unlock states, we + * assume that we are by default in locked state. + * So in this case we can boot only when verification is + * successful; we also supply in cmdline GREEN boot state + */ + printf("Verification passed successfully\n"); + + /* export additional bootargs to AVB_BOOTARGS env var */ + + extra_args = avb_set_state(avb_ops, AVB_GREEN); + if (extra_args) + cmdline = append_cmd_line(out_data->cmdline, + extra_args); + else + cmdline = out_data->cmdline; + + env_set(AVB_BOOTARGS, cmdline); + + res = CMD_RET_SUCCESS; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + printf("Verification failed\n"); + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + printf("I/O error occurred during verification\n"); + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + printf("OOM error occurred during verification\n"); + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + printf("Corrupted dm-verity metadata detected\n"); + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + printf("Unsupported version avbtool was used\n"); + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + printf("Checking rollback index failed\n"); + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + printf("Public key was rejected\n"); + break; + default: + printf("Unknown error occurred\n"); + } + + return res; +} + +int do_avb_is_unlocked(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + bool unlock; + + if (!avb_ops) { + printf("AVB not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 1) { + printf("--%s(-1)\n", __func__); + return CMD_RET_USAGE; + } + + if (avb_ops->read_is_device_unlocked(avb_ops, &unlock) == + AVB_IO_RESULT_OK) { + printf("Unlocked = %d\n", unlock); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} + +static cmd_tbl_t cmd_avb[] = { + U_BOOT_CMD_MKENT(init, 2, 0, do_avb_init, "", ""), + U_BOOT_CMD_MKENT(read_rb, 2, 0, do_avb_read_rb, "", ""), + U_BOOT_CMD_MKENT(write_rb, 3, 0, do_avb_write_rb, "", ""), + U_BOOT_CMD_MKENT(is_unlocked, 1, 0, do_avb_is_unlocked, "", ""), + U_BOOT_CMD_MKENT(get_uuid, 2, 0, do_avb_get_uuid, "", ""), + U_BOOT_CMD_MKENT(read_part, 5, 0, do_avb_read_part, "", ""), + U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""), + U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""), + U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""), +}; + +static int do_avb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + + cp = find_cmd_tbl(argv[1], cmd_avb, ARRAY_SIZE(cmd_avb)); + + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + + if (flag == CMD_FLAG_REPEAT) + return CMD_RET_FAILURE; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + avb, 29, 0, do_avb, + "Provides commands for testing Android Verified Boot 2.0 functionality", + "init <dev> - initialize avb2 for <dev>\n" + "avb read_rb <num> - read rollback index at location <num>\n" + "avb write_rb <num> <rb> - write rollback index <rb> to <num>\n" + "avb is_unlocked - returns unlock status of the device\n" + "avb get_uuid <partname> - read and print uuid of partition <part>\n" + "avb read_part <partname> <offset> <num> <addr> - read <num> bytes from\n" + " partition <partname> to buffer <addr>\n" + "avb read_part_hex <partname> <offset> <num> - read <num> bytes from\n" + " partition <partname> and print to stdout\n" + "avb write_part <partname> <offset> <num> <addr> - write <num> bytes to\n" + " <partname> by <offset> using data from <addr>\n" + "avb verify - run verification process using hash data\n" + " from vbmeta structure\n" + ); diff --git a/cmd/bootefi.c b/cmd/bootefi.c index f55a40dc84c..cd755b6bf44 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -61,6 +61,11 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; #endif +#ifdef CONFIG_GENERATE_ACPI_TABLE + ret = efi_acpi_register(); + if (ret != EFI_SUCCESS) + goto out; +#endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE ret = efi_smbios_register(); if (ret != EFI_SUCCESS) diff --git a/cmd/booti.c b/cmd/booti.c index 45fbb99b680..04353b68ecc 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -37,7 +37,7 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc, debug("* kernel: cmdline image address = 0x%08lx\n", ld); } - ret = booti_setup(ld, &relocated_addr, &image_size); + ret = booti_setup(ld, &relocated_addr, &image_size, false); if (ret != 0) return 1; diff --git a/cmd/efi.c b/cmd/efi.c index 2511c6cb78a..6c1eb88424b 100644 --- a/cmd/efi.c +++ b/cmd/efi.c @@ -83,7 +83,7 @@ void *efi_build_mem_table(struct efi_entry_memmap *map, int size, bool skip_bs) prev = NULL; addr = 0; dest = base; - end = base + count; + end = (struct efi_mem_desc *)((ulong)base + count * map->desc_size); for (desc = base; desc < end; desc = efi_get_next_mem_desc(map, desc)) { bool merge = true; int type = desc->type; diff --git a/cmd/iotrace.c b/cmd/iotrace.c index 601b8c8e32a..fa6c68b1982 100644 --- a/cmd/iotrace.c +++ b/cmd/iotrace.c @@ -9,12 +9,13 @@ static void do_print_stats(void) { - ulong start, size, offset, count; + ulong start, size, needed_size, offset, count; printf("iotrace is %sabled\n", iotrace_get_enabled() ? "en" : "dis"); - iotrace_get_buffer(&start, &size, &offset, &count); + iotrace_get_buffer(&start, &size, &needed_size, &offset, &count); printf("Start: %08lx\n", start); - printf("Size: %08lx\n", size); + printf("Actual Size: %08lx\n", size); + printf("Needed Size: %08lx\n", needed_size); iotrace_get_region(&start, &size); printf("Region: %08lx\n", start); printf("Size: %08lx\n", size); @@ -24,6 +25,36 @@ static void do_print_stats(void) printf("CRC32: %08lx\n", (ulong)iotrace_get_checksum()); } +static void do_print_trace(void) +{ + ulong start, size, needed_size, offset, count; + + struct iotrace_record *cur_record; + + iotrace_get_buffer(&start, &size, &needed_size, &offset, &count); + + if (!start || !size || !count) + return; + + printf("Timestamp Value Address\n"); + + cur_record = (struct iotrace_record *)start; + for (int i = 0; i < count; i++) { + if (cur_record->flags & IOT_WRITE) + printf("%08llu: 0x%08lx --> 0x%08llx\n", + cur_record->timestamp, + cur_record->value, + (unsigned long long)cur_record->addr); + else + printf("%08llu: 0x%08lx <-- 0x%08llx\n", + cur_record->timestamp, + cur_record->value, + (unsigned long long)cur_record->addr); + + cur_record++; + } +} + static int do_set_buffer(int argc, char * const argv[]) { ulong addr = 0, size = 0; @@ -76,6 +107,9 @@ int do_iotrace(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 's': do_print_stats(); break; + case 'd': + do_print_trace(); + break; default: return CMD_RET_USAGE; } @@ -90,5 +124,6 @@ U_BOOT_CMD( "iotrace buffer <address> <size> - set iotrace buffer\n" "iotrace limit <address> <size> - set iotrace region limit\n" "iotrace pause - pause tracing\n" - "iotrace resume - resume tracing" + "iotrace resume - resume tracing\n" + "iotrace dump - dump iotrace buffer" ); diff --git a/cmd/mmc.c b/cmd/mmc.c index c2ee2d9c0af..3920a1836a5 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -935,6 +935,7 @@ U_BOOT_CMD( "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" +#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) "mmc hwpartition [args...] - does hardware partitioning\n" " arguments (sizes in 512-byte blocks):\n" " [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes\n" @@ -942,6 +943,7 @@ U_BOOT_CMD( " [check|set|complete] - mode, complete set partitioning completed\n" " WARNING: Partitioning is a write-once setting once it is set to complete.\n" " Power cycling is required to initialize partitions after set to complete.\n" +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" " - Set the BOOT_BUS_WIDTH field of the specified device\n" diff --git a/cmd/net.c b/cmd/net.c index f83839c35ec..eca6dd8918e 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -183,6 +183,8 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, int size; ulong addr; + net_boot_file_name_explicit = false; + /* pre-set load_addr */ s = env_get("loadaddr"); if (s != NULL) @@ -199,15 +201,18 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, * mis-interpreted as a valid number. */ addr = simple_strtoul(argv[1], &end, 16); - if (end == (argv[1] + strlen(argv[1]))) + if (end == (argv[1] + strlen(argv[1]))) { load_addr = addr; - else + } else { + net_boot_file_name_explicit = true; copy_filename(net_boot_file_name, argv[1], sizeof(net_boot_file_name)); + } break; case 3: load_addr = simple_strtoul(argv[1], NULL, 16); + net_boot_file_name_explicit = true; copy_filename(net_boot_file_name, argv[2], sizeof(net_boot_file_name)); @@ -220,6 +225,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, printf("Invalid address/size\n"); return CMD_RET_USAGE; } + net_boot_file_name_explicit = true; copy_filename(net_boot_file_name, argv[3], sizeof(net_boot_file_name)); break; diff --git a/cmd/wol.c b/cmd/wol.c new file mode 100644 index 00000000000..8a756f373c8 --- /dev/null +++ b/cmd/wol.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Lothar Felte, lothar.felten@gmail.com + */ + +/* + * Wake-on-LAN support + */ +#include <common.h> +#include <command.h> +#include <net.h> + +#if defined(CONFIG_CMD_WOL) +void wol_set_timeout(ulong); + +int do_wol(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + /* Validate arguments */ + if (argc < 2) + return CMD_RET_USAGE; + wol_set_timeout(simple_strtol(argv[1], NULL, 10) * 1000); + if (net_loop(WOL) < 0) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + wol, 2, 1, do_wol, + "wait for an incoming wake-on-lan packet", + "Timeout" +); +#endif diff --git a/common/Makefile b/common/Makefile index b3da72ebb2c..66584f8f48b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -120,3 +120,5 @@ obj-$(CONFIG_$(SPL_)LOG) += log.o obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o obj-y += s_record.o obj-y += xyzModem.o + +obj-$(CONFIG_LIBAVB) += avb_verify.o diff --git a/common/avb_verify.c b/common/avb_verify.c new file mode 100644 index 00000000000..f9a00f8871c --- /dev/null +++ b/common/avb_verify.c @@ -0,0 +1,741 @@ +/* + * (C) Copyright 2018, Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <avb_verify.h> +#include <fastboot.h> +#include <image.h> +#include <malloc.h> +#include <part.h> + +const unsigned char avb_root_pub[1032] = { + 0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4, + 0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2, + 0x8c, 0xd3, 0x12, 0x55, 0xe9, 0x62, 0xc9, 0xf1, 0xf, 0x5e, + 0xcc, 0x16, 0x72, 0xab, 0x44, 0x7c, 0x2c, 0x65, 0x4a, 0x94, + 0xb5, 0x16, 0x2b, 0x0, 0xbb, 0x6, 0xef, 0x13, 0x7, 0x53, + 0x4c, 0xf9, 0x64, 0xb9, 0x28, 0x7a, 0x1b, 0x84, 0x98, 0x88, + 0xd8, 0x67, 0xa4, 0x23, 0xf9, 0xa7, 0x4b, 0xdc, 0x4a, 0xf, + 0xf7, 0x3a, 0x18, 0xae, 0x54, 0xa8, 0x15, 0xfe, 0xb0, 0xad, + 0xac, 0x35, 0xda, 0x3b, 0xad, 0x27, 0xbc, 0xaf, 0xe8, 0xd3, + 0x2f, 0x37, 0x34, 0xd6, 0x51, 0x2b, 0x6c, 0x5a, 0x27, 0xd7, + 0x96, 0x6, 0xaf, 0x6b, 0xb8, 0x80, 0xca, 0xfa, 0x30, 0xb4, + 0xb1, 0x85, 0xb3, 0x4d, 0xaa, 0xaa, 0xc3, 0x16, 0x34, 0x1a, + 0xb8, 0xe7, 0xc7, 0xfa, 0xf9, 0x9, 0x77, 0xab, 0x97, 0x93, + 0xeb, 0x44, 0xae, 0xcf, 0x20, 0xbc, 0xf0, 0x80, 0x11, 0xdb, + 0x23, 0xc, 0x47, 0x71, 0xb9, 0x6d, 0xd6, 0x7b, 0x60, 0x47, + 0x87, 0x16, 0x56, 0x93, 0xb7, 0xc2, 0x2a, 0x9a, 0xb0, 0x4c, + 0x1, 0xc, 0x30, 0xd8, 0x93, 0x87, 0xf0, 0xed, 0x6e, 0x8b, + 0xbe, 0x30, 0x5b, 0xf6, 0xa6, 0xaf, 0xdd, 0x80, 0x7c, 0x45, + 0x5e, 0x8f, 0x91, 0x93, 0x5e, 0x44, 0xfe, 0xb8, 0x82, 0x7, + 0xee, 0x79, 0xca, 0xbf, 0x31, 0x73, 0x62, 0x58, 0xe3, 0xcd, + 0xc4, 0xbc, 0xc2, 0x11, 0x1d, 0xa1, 0x4a, 0xbf, 0xfe, 0x27, + 0x7d, 0xa1, 0xf6, 0x35, 0xa3, 0x5e, 0xca, 0xdc, 0x57, 0x2f, + 0x3e, 0xf0, 0xc9, 0x5d, 0x86, 0x6a, 0xf8, 0xaf, 0x66, 0xa7, + 0xed, 0xcd, 0xb8, 0xed, 0xa1, 0x5f, 0xba, 0x9b, 0x85, 0x1a, + 0xd5, 0x9, 0xae, 0x94, 0x4e, 0x3b, 0xcf, 0xcb, 0x5c, 0xc9, + 0x79, 0x80, 0xf7, 0xcc, 0xa6, 0x4a, 0xa8, 0x6a, 0xd8, 0xd3, + 0x31, 0x11, 0xf9, 0xf6, 0x2, 0x63, 0x2a, 0x1a, 0x2d, 0xd1, + 0x1a, 0x66, 0x1b, 0x16, 0x41, 0xbd, 0xbd, 0xf7, 0x4d, 0xc0, + 0x4a, 0xe5, 0x27, 0x49, 0x5f, 0x7f, 0x58, 0xe3, 0x27, 0x2d, + 0xe5, 0xc9, 0x66, 0xe, 0x52, 0x38, 0x16, 0x38, 0xfb, 0x16, + 0xeb, 0x53, 0x3f, 0xe6, 0xfd, 0xe9, 0xa2, 0x5e, 0x25, 0x59, + 0xd8, 0x79, 0x45, 0xff, 0x3, 0x4c, 0x26, 0xa2, 0x0, 0x5a, + 0x8e, 0xc2, 0x51, 0xa1, 0x15, 0xf9, 0x7b, 0xf4, 0x5c, 0x81, + 0x9b, 0x18, 0x47, 0x35, 0xd8, 0x2d, 0x5, 0xe9, 0xad, 0xf, + 0x35, 0x74, 0x15, 0xa3, 0x8e, 0x8b, 0xcc, 0x27, 0xda, 0x7c, + 0x5d, 0xe4, 0xfa, 0x4, 0xd3, 0x5, 0xb, 0xba, 0x3a, 0xb2, + 0x49, 0x45, 0x2f, 0x47, 0xc7, 0xd, 0x41, 0x3f, 0x97, 0x80, + 0x4d, 0x3f, 0xc1, 0xb5, 0xbb, 0x70, 0x5f, 0xa7, 0x37, 0xaf, + 0x48, 0x22, 0x12, 0x45, 0x2e, 0xf5, 0xf, 0x87, 0x92, 0xe2, + 0x84, 0x1, 0xf9, 0x12, 0xf, 0x14, 0x15, 0x24, 0xce, 0x89, + 0x99, 0xee, 0xb9, 0xc4, 0x17, 0x70, 0x70, 0x15, 0xea, 0xbe, + 0xc6, 0x6c, 0x1f, 0x62, 0xb3, 0xf4, 0x2d, 0x16, 0x87, 0xfb, + 0x56, 0x1e, 0x45, 0xab, 0xae, 0x32, 0xe4, 0x5e, 0x91, 0xed, + 0x53, 0x66, 0x5e, 0xbd, 0xed, 0xad, 0xe6, 0x12, 0x39, 0xd, + 0x83, 0xc9, 0xe8, 0x6b, 0x6c, 0x2d, 0xa5, 0xee, 0xc4, 0x5a, + 0x66, 0xae, 0x8c, 0x97, 0xd7, 0xd, 0x6c, 0x49, 0xc7, 0xf5, + 0xc4, 0x92, 0x31, 0x8b, 0x9, 0xee, 0x33, 0xda, 0xa9, 0x37, + 0xb6, 0x49, 0x18, 0xf8, 0xe, 0x60, 0x45, 0xc8, 0x33, 0x91, + 0xef, 0x20, 0x57, 0x10, 0xbe, 0x78, 0x2d, 0x83, 0x26, 0xd6, + 0xca, 0x61, 0xf9, 0x2f, 0xe0, 0xbf, 0x5, 0x30, 0x52, 0x5a, + 0x12, 0x1c, 0x0, 0xa7, 0x5d, 0xcc, 0x7c, 0x2e, 0xc5, 0x95, + 0x8b, 0xa3, 0x3b, 0xf0, 0x43, 0x2e, 0x5e, 0xdd, 0x0, 0xdb, + 0xd, 0xb3, 0x37, 0x99, 0xa9, 0xcd, 0x9c, 0xb7, 0x43, 0xf7, + 0x35, 0x44, 0x21, 0xc2, 0x82, 0x71, 0xab, 0x8d, 0xaa, 0xb4, + 0x41, 0x11, 0xec, 0x1e, 0x8d, 0xfc, 0x14, 0x82, 0x92, 0x4e, + 0x83, 0x6a, 0xa, 0x6b, 0x35, 0x5e, 0x5d, 0xe9, 0x5c, 0xcc, + 0x8c, 0xde, 0x39, 0xd1, 0x4a, 0x5b, 0x5f, 0x63, 0xa9, 0x64, + 0xe0, 0xa, 0xcb, 0xb, 0xb8, 0x5a, 0x7c, 0xc3, 0xb, 0xe6, + 0xbe, 0xfe, 0x8b, 0xf, 0x7d, 0x34, 0x8e, 0x2, 0x66, 0x74, + 0x1, 0x6c, 0xca, 0x76, 0xac, 0x7c, 0x67, 0x8, 0x2f, 0x3f, + 0x1a, 0xa6, 0x2c, 0x60, 0xb3, 0xff, 0xda, 0x8d, 0xb8, 0x12, + 0xc, 0x0, 0x7f, 0xcc, 0x50, 0xa1, 0x5c, 0x64, 0xa1, 0xe2, + 0x5f, 0x32, 0x65, 0xc9, 0x9c, 0xbe, 0xd6, 0xa, 0x13, 0x87, + 0x3c, 0x2a, 0x45, 0x47, 0xc, 0xca, 0x42, 0x82, 0xfa, 0x89, + 0x65, 0xe7, 0x89, 0xb4, 0x8f, 0xf7, 0x1e, 0xe6, 0x23, 0xa5, + 0xd0, 0x59, 0x37, 0x79, 0x92, 0xd7, 0xce, 0x3d, 0xfd, 0xe3, + 0xa1, 0xb, 0xcf, 0x6c, 0x85, 0xa0, 0x65, 0xf3, 0x5c, 0xc6, + 0x4a, 0x63, 0x5f, 0x6e, 0x3a, 0x3a, 0x2a, 0x8b, 0x6a, 0xb6, + 0x2f, 0xbb, 0xf8, 0xb2, 0x4b, 0x62, 0xbc, 0x1a, 0x91, 0x25, + 0x66, 0xe3, 0x69, 0xca, 0x60, 0x49, 0xb, 0xf6, 0x8a, 0xbe, + 0x3e, 0x76, 0x53, 0xc2, 0x7a, 0xa8, 0x4, 0x17, 0x75, 0xf1, + 0xf3, 0x3, 0x62, 0x1b, 0x85, 0xb2, 0xb0, 0xef, 0x80, 0x15, + 0xb6, 0xd4, 0x4e, 0xdf, 0x71, 0xac, 0xdb, 0x2a, 0x4, 0xd4, + 0xb4, 0x21, 0xba, 0x65, 0x56, 0x57, 0xe8, 0xfa, 0x84, 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============================================================================ + */ +char *avb_set_state(AvbOps *ops, enum avb_boot_state boot_state) +{ + struct AvbOpsData *data; + char *cmdline = NULL; + + if (!ops) + return NULL; + + data = (struct AvbOpsData *)ops->user_data; + if (!data) + return NULL; + + data->boot_state = boot_state; + switch (boot_state) { + case AVB_GREEN: + cmdline = "androidboot.verifiedbootstate=green"; + break; + case AVB_YELLOW: + cmdline = "androidboot.verifiedbootstate=yellow"; + break; + case AVB_ORANGE: + cmdline = "androidboot.verifiedbootstate=orange"; + case AVB_RED: + break; + } + + return cmdline; +} + +char *append_cmd_line(char *cmdline_orig, char *cmdline_new) +{ + char *cmd_line; + + if (!cmdline_new) + return cmdline_orig; + + if (cmdline_orig) + cmd_line = cmdline_orig; + else + cmd_line = " "; + + cmd_line = avb_strdupv(cmd_line, " ", cmdline_new, NULL); + + return cmd_line; +} + +static int avb_find_dm_args(char **args, char *str) +{ + int i; + + if (!str) + return -1; + + for (i = 0; i < AVB_MAX_ARGS, args[i]; ++i) { + if (strstr(args[i], str)) + return i; + } + + return -1; +} + +static char *avb_set_enforce_option(const char *cmdline, const char *option) +{ + char *cmdarg[AVB_MAX_ARGS]; + char *newargs = NULL; + int i = 0; + int total_args; + + memset(cmdarg, 0, sizeof(cmdarg)); + cmdarg[i++] = strtok((char *)cmdline, " "); + + do { + cmdarg[i] = strtok(NULL, " "); + if (!cmdarg[i]) + break; + + if (++i >= AVB_MAX_ARGS) { + printf("%s: Can't handle more then %d args\n", + __func__, i); + return NULL; + } + } while (true); + + total_args = i; + i = avb_find_dm_args(&cmdarg[0], VERITY_TABLE_OPT_LOGGING); + if (i >= 0) { + cmdarg[i] = (char *)option; + } else { + i = avb_find_dm_args(&cmdarg[0], VERITY_TABLE_OPT_RESTART); + if (i < 0) { + printf("%s: No verity options found\n", __func__); + return NULL; + } + + cmdarg[i] = (char *)option; + } + + for (i = 0; i <= total_args; i++) + newargs = append_cmd_line(newargs, cmdarg[i]); + + return newargs; +} + +char *avb_set_ignore_corruption(const char *cmdline) +{ + char *newargs = NULL; + + newargs = avb_set_enforce_option(cmdline, VERITY_TABLE_OPT_LOGGING); + if (newargs) + newargs = append_cmd_line(newargs, + "androidboot.veritymode=eio"); + + return newargs; +} + +char *avb_set_enforce_verity(const char *cmdline) +{ + char *newargs; + + newargs = avb_set_enforce_option(cmdline, VERITY_TABLE_OPT_RESTART); + if (newargs) + newargs = append_cmd_line(newargs, + "androidboot.veritymode=enforcing"); + return newargs; +} + +/** + * ============================================================================ + * IO(mmc) auxiliary functions + * ============================================================================ + */ +static unsigned long mmc_read_and_flush(struct mmc_part *part, + lbaint_t start, + lbaint_t sectors, + void *buffer) +{ + unsigned long blks; + void *tmp_buf; + size_t buf_size; + bool unaligned = is_buf_unaligned(buffer); + + if (start < part->info.start) { + printf("%s: partition start out of bounds\n", __func__); + return 0; + } + if ((start + sectors) > (part->info.start + part->info.size)) { + sectors = part->info.start + part->info.size - start; + printf("%s: read sector aligned to partition bounds (%ld)\n", + __func__, sectors); + } + + /* + * Reading fails on unaligned buffers, so we have to + * use aligned temporary buffer and then copy to destination + */ + + if (unaligned) { + printf("Handling unaligned read buffer..\n"); + tmp_buf = get_sector_buf(); + buf_size = get_sector_buf_size(); + if (sectors > buf_size / part->info.blksz) + sectors = buf_size / part->info.blksz; + } else { + tmp_buf = buffer; + } + + blks = part->mmc->block_dev.block_read(part->mmc_blk, + start, sectors, tmp_buf); + /* flush cache after read */ + flush_cache((ulong)tmp_buf, sectors * part->info.blksz); + + if (unaligned) + memcpy(buffer, tmp_buf, sectors * part->info.blksz); + + return blks; +} + +static unsigned long mmc_write(struct mmc_part *part, lbaint_t start, + lbaint_t sectors, void *buffer) +{ + void *tmp_buf; + size_t buf_size; + bool unaligned = is_buf_unaligned(buffer); + + if (start < part->info.start) { + printf("%s: partition start out of bounds\n", __func__); + return 0; + } + if ((start + sectors) > (part->info.start + part->info.size)) { + sectors = part->info.start + part->info.size - start; + printf("%s: sector aligned to partition bounds (%ld)\n", + __func__, sectors); + } + if (unaligned) { + tmp_buf = get_sector_buf(); + buf_size = get_sector_buf_size(); + printf("Handling unaligned wrire buffer..\n"); + if (sectors > buf_size / part->info.blksz) + sectors = buf_size / part->info.blksz; + + memcpy(tmp_buf, buffer, sectors * part->info.blksz); + } else { + tmp_buf = buffer; + } + + return part->mmc->block_dev.block_write(part->mmc_blk, + start, sectors, tmp_buf); +} + +static struct mmc_part *get_partition(AvbOps *ops, const char *partition) +{ + int ret; + u8 dev_num; + int part_num = 0; + struct mmc_part *part; + struct blk_desc *mmc_blk; + + part = malloc(sizeof(struct mmc_part)); + if (!part) + return NULL; + + dev_num = get_boot_device(ops); + part->mmc = find_mmc_device(dev_num); + if (!part->mmc) { + printf("No MMC device at slot %x\n", dev_num); + return NULL; + } + + if (mmc_init(part->mmc)) { + printf("MMC initialization failed\n"); + return NULL; + } + + ret = mmc_switch_part(part->mmc, part_num); + if (ret) + return NULL; + + mmc_blk = mmc_get_blk_desc(part->mmc); + if (!mmc_blk) { + printf("Error - failed to obtain block descriptor\n"); + return NULL; + } + + ret = part_get_info_by_name(mmc_blk, partition, &part->info); + if (!ret) { + printf("Can't find partition '%s'\n", partition); + return NULL; + } + + part->dev_num = dev_num; + part->mmc_blk = mmc_blk; + + return part; +} + +static AvbIOResult mmc_byte_io(AvbOps *ops, + const char *partition, + s64 offset, + size_t num_bytes, + void *buffer, + size_t *out_num_read, + enum mmc_io_type io_type) +{ + ulong ret; + struct mmc_part *part; + u64 start_offset, start_sector, sectors, residue; + u8 *tmp_buf; + size_t io_cnt = 0; + + if (!partition || !buffer || io_type > IO_WRITE) + return AVB_IO_RESULT_ERROR_IO; + + part = get_partition(ops, partition); + if (!part) + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + + start_offset = calc_offset(part, offset); + while (num_bytes) { + start_sector = start_offset / part->info.blksz; + sectors = num_bytes / part->info.blksz; + /* handle non block-aligned reads */ + if (start_offset % part->info.blksz || + num_bytes < part->info.blksz) { + tmp_buf = get_sector_buf(); + if (start_offset % part->info.blksz) { + residue = part->info.blksz - + (start_offset % part->info.blksz); + if (residue > num_bytes) + residue = num_bytes; + } else { + residue = num_bytes; + } + + if (io_type == IO_READ) { + ret = mmc_read_and_flush(part, + part->info.start + + start_sector, + 1, tmp_buf); + + if (ret != 1) { + printf("%s: read error (%ld, %lld)\n", + __func__, ret, start_sector); + return AVB_IO_RESULT_ERROR_IO; + } + /* + * if this is not aligned at sector start, + * we have to adjust the tmp buffer + */ + tmp_buf += (start_offset % part->info.blksz); + memcpy(buffer, (void *)tmp_buf, residue); + } else { + ret = mmc_read_and_flush(part, + part->info.start + + start_sector, + 1, tmp_buf); + + if (ret != 1) { + printf("%s: read error (%ld, %lld)\n", + __func__, ret, start_sector); + return AVB_IO_RESULT_ERROR_IO; + } + memcpy((void *)tmp_buf + + start_offset % part->info.blksz, + buffer, residue); + + ret = mmc_write(part, part->info.start + + start_sector, 1, tmp_buf); + if (ret != 1) { + printf("%s: write error (%ld, %lld)\n", + __func__, ret, start_sector); + return AVB_IO_RESULT_ERROR_IO; + } + } + + io_cnt += residue; + buffer += residue; + start_offset += residue; + num_bytes -= residue; + continue; + } + + if (sectors) { + if (io_type == IO_READ) { + ret = mmc_read_and_flush(part, + part->info.start + + start_sector, + sectors, buffer); + } else { + ret = mmc_write(part, + part->info.start + + start_sector, + sectors, buffer); + } + + if (!ret) { + printf("%s: sector read error\n", __func__); + return AVB_IO_RESULT_ERROR_IO; + } + + io_cnt += ret * part->info.blksz; + buffer += ret * part->info.blksz; + start_offset += ret * part->info.blksz; + num_bytes -= ret * part->info.blksz; + } + } + + /* Set counter for read operation */ + if (io_type == IO_READ && out_num_read) + *out_num_read = io_cnt; + + return AVB_IO_RESULT_OK; +} + +/** + * ============================================================================ + * AVB 2.0 operations + * ============================================================================ + */ + +/** + * read_from_partition() - reads @num_bytes from @offset from partition + * identified by a string name + * + * @ops: contains AVB ops handlers + * @partition_name: partition name, NUL-terminated UTF-8 string + * @offset: offset from the beginning of partition + * @num_bytes: amount of bytes to read + * @buffer: destination buffer to store data + * @out_num_read: + * + * @return: + * AVB_IO_RESULT_OK, if partition was found and read operation succeed + * AVB_IO_RESULT_ERROR_IO, if i/o error occurred from the underlying i/o + * subsystem + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, if there is no partition with + * the given name + */ +static AvbIOResult read_from_partition(AvbOps *ops, + const char *partition_name, + s64 offset_from_partition, + size_t num_bytes, + void *buffer, + size_t *out_num_read) +{ + return mmc_byte_io(ops, partition_name, offset_from_partition, + num_bytes, buffer, out_num_read, IO_READ); +} + +/** + * write_to_partition() - writes N bytes to a partition identified by a string + * name + * + * @ops: AvbOps, contains AVB ops handlers + * @partition_name: partition name + * @offset_from_partition: offset from the beginning of partition + * @num_bytes: amount of bytes to write + * @buf: data to write + * @out_num_read: + * + * @return: + * AVB_IO_RESULT_OK, if partition was found and read operation succeed + * AVB_IO_RESULT_ERROR_IO, if input/output error occurred + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, if partition, specified in + * @partition_name was not found + */ +static AvbIOResult write_to_partition(AvbOps *ops, + const char *partition_name, + s64 offset_from_partition, + size_t num_bytes, + const void *buffer) +{ + return mmc_byte_io(ops, partition_name, offset_from_partition, + num_bytes, (void *)buffer, NULL, IO_WRITE); +} + +/** + * validate_vmbeta_public_key() - checks if the given public key used to sign + * the vbmeta partition is trusted + * + * @ops: AvbOps, contains AVB ops handlers + * @public_key_data: public key for verifying vbmeta partition signature + * @public_key_length: length of public key + * @public_key_metadata: + * @public_key_metadata_length: + * @out_key_is_trusted: + * + * @return: + * AVB_IO_RESULT_OK, if partition was found and read operation succeed + */ +static AvbIOResult validate_vbmeta_public_key(AvbOps *ops, + const u8 *public_key_data, + size_t public_key_length, + const u8 + *public_key_metadata, + size_t + public_key_metadata_length, + bool *out_key_is_trusted) +{ + if (!public_key_length || !public_key_data || !out_key_is_trusted) + return AVB_IO_RESULT_ERROR_IO; + + *out_key_is_trusted = false; + if (public_key_length != sizeof(avb_root_pub)) + return AVB_IO_RESULT_ERROR_IO; + + if (memcmp(avb_root_pub, public_key_data, public_key_length) == 0) + *out_key_is_trusted = true; + + return AVB_IO_RESULT_OK; +} + +/** + * read_rollback_index() - gets the rollback index corresponding to the + * location of given by @out_rollback_index. + * + * @ops: contains AvbOps handlers + * @rollback_index_slot: + * @out_rollback_index: used to write a retrieved rollback index. + * + * @return + * AVB_IO_RESULT_OK, if the roolback index was retrieved + */ +static AvbIOResult read_rollback_index(AvbOps *ops, + size_t rollback_index_slot, + u64 *out_rollback_index) +{ + /* For now we always return 0 as the stored rollback index. */ + printf("%s not supported yet\n", __func__); + + if (out_rollback_index) + *out_rollback_index = 0; + + return AVB_IO_RESULT_OK; +} + +/** + * write_rollback_index() - sets the rollback index corresponding to the + * location of given by @out_rollback_index. + * + * @ops: contains AvbOps handlers + * @rollback_index_slot: + * @rollback_index: rollback index to write. + * + * @return + * AVB_IO_RESULT_OK, if the roolback index was retrieved + */ +static AvbIOResult write_rollback_index(AvbOps *ops, + size_t rollback_index_slot, + u64 rollback_index) +{ + /* For now this is a no-op. */ + printf("%s not supported yet\n", __func__); + + return AVB_IO_RESULT_OK; +} + +/** + * read_is_device_unlocked() - gets whether the device is unlocked + * + * @ops: contains AVB ops handlers + * @out_is_unlocked: device unlock state is stored here, true if unlocked, + * false otherwise + * + * @return: + * AVB_IO_RESULT_OK: state is retrieved successfully + * AVB_IO_RESULT_ERROR_IO: an error occurred + */ +static AvbIOResult read_is_device_unlocked(AvbOps *ops, bool *out_is_unlocked) +{ + /* For now we always return that the device is unlocked. */ + + printf("%s not supported yet\n", __func__); + + *out_is_unlocked = true; + + return AVB_IO_RESULT_OK; +} + +/** + * get_unique_guid_for_partition() - gets the GUID for a partition identified + * by a string name + * + * @ops: contains AVB ops handlers + * @partition: partition name (NUL-terminated UTF-8 string) + * @guid_buf: buf, used to copy in GUID string. Example of value: + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * @guid_buf_size: @guid_buf buffer size + * + * @return: + * AVB_IO_RESULT_OK, on success (GUID found) + * AVB_IO_RESULT_ERROR_IO, if incorrect buffer size (@guid_buf_size) was + * provided + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, if partition was not found + */ +static AvbIOResult get_unique_guid_for_partition(AvbOps *ops, + const char *partition, + char *guid_buf, + size_t guid_buf_size) +{ + struct mmc_part *part; + size_t uuid_size; + + part = get_partition(ops, partition); + if (!part) + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + + uuid_size = sizeof(part->info.uuid); + if (uuid_size > guid_buf_size) + return AVB_IO_RESULT_ERROR_IO; + + memcpy(guid_buf, part->info.uuid, uuid_size); + guid_buf[uuid_size - 1] = 0; + + return AVB_IO_RESULT_OK; +} + +/** + * ============================================================================ + * AVB2.0 AvbOps alloc/initialisation/free + * ============================================================================ + */ +AvbOps *avb_ops_alloc(int boot_device) +{ + struct AvbOpsData *ops_data; + + ops_data = avb_calloc(sizeof(struct AvbOpsData)); + if (!ops_data) + return NULL; + + ops_data->ops.user_data = ops_data; + + ops_data->ops.read_from_partition = read_from_partition; + ops_data->ops.write_to_partition = write_to_partition; + ops_data->ops.validate_vbmeta_public_key = validate_vbmeta_public_key; + ops_data->ops.read_rollback_index = read_rollback_index; + ops_data->ops.write_rollback_index = write_rollback_index; + ops_data->ops.read_is_device_unlocked = read_is_device_unlocked; + ops_data->ops.get_unique_guid_for_partition = + get_unique_guid_for_partition; + + ops_data->mmc_dev = boot_device; + + return &ops_data->ops; +} + +void avb_ops_free(AvbOps *ops) +{ + struct AvbOpsData *ops_data; + + if (ops) + return; + + ops_data = ops->user_data; + + if (ops_data) + avb_free(ops_data); +} diff --git a/common/board_r.c b/common/board_r.c index 6b297068bd2..6949d4af0e3 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -596,7 +596,7 @@ static int initr_pcmcia(void) } #endif -#if defined(CONFIG_IDE) +#if defined(CONFIG_IDE) && !defined(CONFIG_BLK) static int initr_ide(void) { puts("IDE: "); @@ -826,7 +826,7 @@ static init_fnc_t init_sequence_r[] = { #if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE) initr_pcmcia, #endif -#if defined(CONFIG_IDE) +#if defined(CONFIG_IDE) && !defined(CONFIG_BLK) initr_ide, #endif #ifdef CONFIG_LAST_STAGE_INIT diff --git a/common/bootm.c b/common/bootm.c index e789f6818aa..e517d9f118a 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -202,8 +202,23 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, } if (images.os.type == IH_TYPE_KERNEL_NOLOAD) { - images.os.load = images.os.image_start; - images.ep += images.os.load; + if (CONFIG_IS_ENABLED(CMD_BOOTI) && + images.os.arch == IH_ARCH_ARM64) { + ulong image_addr; + ulong image_size; + + ret = booti_setup(images.os.image_start, &image_addr, + &image_size, true); + if (ret != 0) + return 1; + + images.os.type = IH_TYPE_KERNEL; + images.os.load = image_addr; + images.ep = image_addr; + } else { + images.os.load = images.os.image_start; + images.ep += images.os.image_start; + } } images.os.start = map_to_sysmem(os_hdr); diff --git a/common/console.c b/common/console.c index 2688af56e15..2ba33dc5740 100644 --- a/common/console.c +++ b/common/console.c @@ -502,8 +502,10 @@ void putc(const char c) return; } #endif + if (!gd) + return; #ifdef CONFIG_CONSOLE_RECORD - if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start) + if ((gd->flags & GD_FLG_RECORD) && gd->console_out.start) membuff_putbyte(&gd->console_out, c); #endif #ifdef CONFIG_SILENT_CONSOLE @@ -541,8 +543,10 @@ void puts(const char *s) return; } #endif + if (!gd) + return; #ifdef CONFIG_CONSOLE_RECORD - if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start) + if ((gd->flags & GD_FLG_RECORD) && gd->console_out.start) membuff_put(&gd->console_out, s, strlen(s)); #endif #ifdef CONFIG_SILENT_CONSOLE diff --git a/common/iotrace.c b/common/iotrace.c index 2f03a6082e8..49bee3c92a0 100644 --- a/common/iotrace.c +++ b/common/iotrace.c @@ -11,38 +11,12 @@ DECLARE_GLOBAL_DATA_PTR; -/* Support up to the machine word length for now */ -typedef ulong iovalue_t; - -enum iotrace_flags { - IOT_8 = 0, - IOT_16, - IOT_32, - - IOT_READ = 0 << 3, - IOT_WRITE = 1 << 3, -}; - -/** - * struct iotrace_record - Holds a single I/O trace record - * - * @flags: I/O access type - * @timestamp: Timestamp of access - * @addr: Address of access - * @value: Value written or read - */ -struct iotrace_record { - enum iotrace_flags flags; - u64 timestamp; - phys_addr_t addr; - iovalue_t value; -}; - /** * struct iotrace - current trace status and checksum * * @start: Start address of iotrace buffer - * @size: Size of iotrace buffer in bytes + * @size: Actual size of iotrace buffer in bytes + * @needed_size: Needed of iotrace buffer in bytes * @offset: Current write offset into iotrace buffer * @region_start: Address of IO region to trace * @region_size: Size of region to trace. if 0 will trace all address space @@ -52,6 +26,7 @@ struct iotrace_record { static struct iotrace { ulong start; ulong size; + ulong needed_size; ulong offset; ulong region_start; ulong region_size; @@ -82,7 +57,12 @@ static void add_record(int flags, const void *ptr, ulong value) rec = (struct iotrace_record *)map_sysmem( iotrace.start + iotrace.offset, sizeof(value)); + } else { + WARN_ONCE(1, "WARNING: iotrace buffer exhausted, please check needed length using \"iotrace stats\"\n"); + iotrace.needed_size += sizeof(struct iotrace_record); + return; } + rec->timestamp = timer_get_us(); rec->flags = flags; rec->addr = map_to_sysmem(ptr); @@ -92,6 +72,7 @@ static void add_record(int flags, const void *ptr, ulong value) iotrace.crc32 = crc32(iotrace.crc32, (unsigned char *)rec, sizeof(*rec)); + iotrace.needed_size += sizeof(struct iotrace_record); iotrace.offset += sizeof(struct iotrace_record); } @@ -189,10 +170,11 @@ void iotrace_set_buffer(ulong start, ulong size) iotrace.crc32 = 0; } -void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count) +void iotrace_get_buffer(ulong *start, ulong *size, ulong *needed_size, ulong *offset, ulong *count) { *start = iotrace.start; *size = iotrace.size; + *needed_size = iotrace.needed_size; *offset = iotrace.offset; *count = iotrace.offset / sizeof(struct iotrace_record); } diff --git a/common/log.c b/common/log.c index 3b5588ebe7a..59869cd29da 100644 --- a/common/log.c +++ b/common/log.c @@ -38,12 +38,16 @@ static const char *log_level_name[LOGL_COUNT] = { const char *log_get_cat_name(enum log_category_t cat) { - if (cat > LOGC_COUNT) - return "invalid"; + const char *name; + + if (cat < 0 || cat >= LOGC_COUNT) + return "<invalid>"; if (cat >= LOGC_NONE) return log_cat_name[cat - LOGC_NONE]; - return uclass_get_name((enum uclass_id)cat); + name = uclass_get_name((enum uclass_id)cat); + + return name ? name : "<missing>"; } enum log_category_t log_get_cat_by_name(const char *name) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 1f1479718e9..0bbf8d5b023 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -152,7 +152,8 @@ config SPL_DISPLAY_PRINT config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool "MMC raw mode: by sector" - default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_MX6 || \ + default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ + ARCH_MX6 || ARCH_MX7 || \ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP44XX || OMAP54XX || AM33XX || AM43XX @@ -165,7 +166,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR default 0x50 if ARCH_SUNXI default 0x75 if ARCH_DAVINCI - default 0x8a if ARCH_MX6 + default 0x8a if ARCH_MX6 || ARCH_MX7 default 0x100 if ARCH_UNIPHIER default 0x140 if ARCH_MVEBU default 0x200 if ARCH_SOCFPGA || ARCH_AT91 diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index fc04c874859..a328555af61 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -40,3 +40,4 @@ CONFIG_DM_SPI=y CONFIG_ATCSPI200_SPI=y CONFIG_TIMER=y CONFIG_ATCPIT100_TIMER=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 6d403eed7ad..38be7dbe7e5 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index bb1368b9adf..6a2b7ae670d 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -23,7 +23,6 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y # CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set # CONFIG_CMD_PART is not set # CONFIG_CMD_SETEXPR is not set @@ -37,6 +36,7 @@ CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 4db8a2bfb95..f51fbd4aa52 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -4,12 +4,14 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_DISPLAY5=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y @@ -32,6 +34,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y @@ -48,8 +51,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" -CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" -CONFIG_EFI_PARTITION=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),4m(swu-kernel),16m(swu-initramfs),1m(factory),-(reserved)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 10b025ce04e..14df849fb7d 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" @@ -53,7 +54,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" -CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),4m(swu-kernel),16m(swu-initramfs),1m(factory),-(reserved)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_app_defconfig index a2f072b2f2e..9c1d5e786ea 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_app_defconfig @@ -2,8 +2,8 @@ CONFIG_X86=y CONFIG_DEBUG_UART_BASE=0 CONFIG_DEBUG_UART_CLOCK=0 CONFIG_VENDOR_EFI=y -CONFIG_DEFAULT_DEVICE_TREE="efi" -CONFIG_TARGET_EFI=y +CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app" +CONFIG_TARGET_EFI_APP=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_USE_BOOTARGS=y diff --git a/configs/qemu-x86_efi_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 36705db89ad..5b6f125549b 100644 --- a/configs/qemu-x86_efi_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -1,31 +1,27 @@ CONFIG_X86=y -CONFIG_SYS_TEXT_BASE=0x1110000 -CONFIG_MAX_CPUS=2 -CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" -CONFIG_SMP=y +CONFIG_VENDOR_EFI=y +CONFIG_DEFAULT_DEVICE_TREE="efi-x86_payload" +CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y +CONFIG_FIT_SIGNATURE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_QFW=y -CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -36,12 +32,6 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_REGMAP=y CONFIG_SYSCON=y -CONFIG_CPU=y -CONFIG_SPI=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_112=y -CONFIG_CONSOLE_SCROLL_LINES=5 +# CONFIG_PCI_PNP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/qemu-x86_efi_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 5b0806bad9d..71fdb5c841f 100644 --- a/configs/qemu-x86_efi_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -1,31 +1,27 @@ CONFIG_X86=y -CONFIG_SYS_TEXT_BASE=0x1110000 -CONFIG_MAX_CPUS=2 -CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" -CONFIG_SMP=y +CONFIG_VENDOR_EFI=y +CONFIG_DEFAULT_DEVICE_TREE="efi-x86_payload" +CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y +CONFIG_FIT_SIGNATURE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_QFW=y -CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -36,13 +32,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_REGMAP=y CONFIG_SYSCON=y -CONFIG_CPU=y -CONFIG_SPI=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_112=y -CONFIG_CONSOLE_SCROLL_LINES=5 +# CONFIG_PCI_PNP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_STUB_64BIT=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 4ae09fff116..6cd1bfd15e9 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index e8f9cb44785..d3364a790ff 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -8,7 +8,7 @@ CONFIG_TARGET_MX6UL_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 49a653f0424..1eb13df4b48 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -16,10 +16,15 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_ADDR_ENABLE=y @@ -34,3 +39,12 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 451b48d3c40..d1b533141ab 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -6,10 +6,14 @@ CONFIG_TARGET_KP_IMX53=y CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" +CONFIG_SILENT_CONSOLE=y +# CONFIG_SILENT_CONSOLE_UPDATE_ON_SET is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="." CONFIG_CMD_BOOTZ=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -18,6 +22,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y @@ -26,6 +31,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 CONFIG_PHYLIB=y +CONFIG_PHY_ADDR=1 CONFIG_PHY_SMSC=y CONFIG_FEC_MXC=y CONFIG_PINCTRL=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 7ba2fa1fe2d..d4f2f58c8a7 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -13,13 +13,21 @@ CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_ADC=y +CONFIG_SARADC_MESON=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_ADDR_ENABLE=y @@ -34,3 +42,12 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig deleted file mode 100644 index e26d49aef61..00000000000 --- a/configs/m28evk_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_M28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(u-boot),512k(env1),512k(env2),14m(boot),238m(data),-@4096k(UBI)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_MMC_MXS=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_MXS_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig deleted file mode 100644 index 71f1d9fa6c9..00000000000 --- a/configs/m53evk_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX5=y -CONFIG_SYS_TEXT_BASE=0x71000000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_M53EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -# CONFIG_CMD_BMODE is not set -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttymxc1,115200" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SATA=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1024k(u-boot),512k(env1),512k(env2),14m(boot),240m(data),-@2048k(UBI)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_DWC_AHSATA=y -CONFIG_FSL_ESDHC=y -CONFIG_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_MCS7830=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig deleted file mode 100644 index 312191b6e3f..00000000000 --- a/configs/ma5d4evk_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x26f00000 -CONFIG_TARGET_MA5D4EVK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_ma5d4evk" -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS3,115200" -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_DFU_SF=y -CONFIG_SPI_FLASH=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="AriesEmbedded" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_FAT_WRITE=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index ecc8d03e318..9be69adcac9 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -18,11 +18,15 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_DM_ETH=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 344c04aa8d5..f9b282e2daa 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -16,10 +16,15 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_ADDR_ENABLE=y @@ -34,3 +39,12 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 0ee8e6e1b98..76b5715a990 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_WOL=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index d2eb53f091c..51227f11ed6 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -67,5 +67,6 @@ CONFIG_SPL_TIMER=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_112=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f489d52b6be..7144e9cfde1 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -47,5 +47,6 @@ CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_112=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index e656377e3d5..251415c03a6 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0x58280000 +CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_R8A77970=y @@ -24,6 +24,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -45,6 +46,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index d3cccec8fc0..f451950add9 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -46,6 +46,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_RENESAS_RPC_HF=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig deleted file mode 100644 index fcae88d09fe..00000000000 --- a/configs/socfpga_mcvevk_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 -CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" -CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y -CONFIG_DM_GPIO=y -CONFIG_DWAPB_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_DW=y -CONFIG_DM_MMC=y -CONFIG_MMC_DW=y -CONFIG_DM_ETH=y -CONFIG_PHY_GIGE=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_DM_RESET=y -CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="denx" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 785f1ab2a0a..89b7b4a0a21 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -42,10 +42,8 @@ CONFIG_NAND=y CONFIG_NAND_DENALI_DT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x0 -CONFIG_SMC911X_32_BIT=y +CONFIG_DM_ETH=y +CONFIG_SNI_AVE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index cb7680a0c62..93df2f6bbce 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -39,10 +39,8 @@ CONFIG_MMC_SDHCI_CADENCE=y CONFIG_NAND=y CONFIG_NAND_DENALI_DT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x0 -CONFIG_SMC911X_32_BIT=y +CONFIG_DM_ETH=y +CONFIG_SNI_AVE=y CONFIG_PINCONF=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/doc/README.avb2 b/doc/README.avb2 new file mode 100644 index 00000000000..67784b529e4 --- /dev/null +++ b/doc/README.avb2 @@ -0,0 +1,97 @@ +Android Verified Boot 2.0 + +This file contains information about the current support of Android Verified +Boot 2.0 in U-boot + +1. OVERVIEW +--------------------------------- +Verified Boot establishes a chain of trust from the bootloader to system images +* Provides integrity checking for: + - Android Boot image: Linux kernel + ramdisk. RAW hashing of the whole + partition is done and the hash is compared with the one stored in + the VBMeta image + - system/vendor partitions: verifying root hash of dm-verity hashtrees. +* Provides capabilities for rollback protection. + +Integrity of the bootloader (U-boot BLOB and environment) is out of scope. + +For additional details check: +https://android.googlesource.com/platform/external/avb/+/master/README.md + + +2. AVB 2.0 U-BOOT SHELL COMMANDS +----------------------------------- +Provides CLI interface to invoke AVB 2.0 verification + misc. commands for +different testing purposes: + +avb init <dev> - initialize avb 2.0 for <dev> +avb verify - run verification process using hash data from vbmeta structure +avb read_rb <num> - read rollback index at location <num> +avb write_rb <num> <rb> - write rollback index <rb> to <num> +avb is_unlocked - returns unlock status of the device +avb get_uuid <partname> - read and print uuid of partition <partname> +avb read_part <partname> <offset> <num> <addr> - read <num> bytes from +partition <partname> to buffer <addr> +avb write_part <partname> <offset> <num> <addr> - write <num> bytes to +<partname> by <offset> using data from <addr> + + +3. PARTITIONS TAMPERING (EXAMPLE) +----------------------------------- +Boot or system/vendor (dm-verity metadata section) is tampered: +=> avb init 1 +=> avb verify +avb_slot_verify.c:175: ERROR: boot: Hash of data does not match digest in +descriptor. +Slot verification result: ERROR_IO + +Vbmeta partition is tampered: +=> avb init 1 +=> avb verify +avb_vbmeta_image.c:206: ERROR: Hash does not match! +avb_slot_verify.c:388: ERROR: vbmeta: Error verifying vbmeta image: +HASH_MISMATCH +Slot verification result: ERROR_IO + + +4. ENABLE ON YOUR BOARD +----------------------------------- +The following options must be enabled: +CONFIG_LIBAVB=y +CONFIG_CMD_AVB=y + + +Then add `avb verify` invocation to your android boot sequence of commands, +e.g.: + +=> avb_verify=avb init $mmcdev; avb verify; +=> if run avb_verify; then \ + echo AVB verification OK. Continue boot; \ + set bootargs $bootargs $avb_bootargs; \ + else \ + echo AVB verification failed; \ + exit; \ + fi; \ + +=> emmc_android_boot= \ + echo Trying to boot Android from eMMC ...; \ + ... \ + run avb_verify; \ + mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; \ + mmc read ${loadaddr} ${boot_start} ${boot_size}; \ + bootm $loadaddr $loadaddr $fdtaddr; \ + + +To switch on automatic generation of vbmeta partition in AOSP build, add these +lines to device configuration mk file: + +BOARD_AVB_ENABLE := true +BOARD_AVB_ALGORITHM := SHA512_RSA4096 +BOARD_BOOTIMAGE_PARTITION_SIZE := <boot partition size> + +After flashing U-boot don't forget to update environment and write new +partition table: +=> env default -f -a +=> setenv partitions $partitions_android +=> env save +=> gpt write mmc 1 $partitions_android diff --git a/doc/README.u-boot_on_efi b/doc/README.u-boot_on_efi index d5903c7bd3b..e12dd4e3e65 100644 --- a/doc/README.u-boot_on_efi +++ b/doc/README.u-boot_on_efi @@ -65,18 +65,19 @@ for that board. It will be either 32-bit or 64-bit. Alternatively, you can opt for using QEMU [1] and the OVMF [2], as detailed below. To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI -and CONFIG_EFI_APP. The efi-x86 config (efi-x86_defconfig) is set up for this. -Just build U-Boot as normal, e.g. +and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app_defconfig) is set up +for this. Just build U-Boot as normal, e.g. - make efi-x86_defconfig + make efi-x86_app_defconfig make -To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), adjust an -existing config (like qemu-x86_defconfig) to enable CONFIG_EFI, CONFIG_EFI_STUB -and either CONFIG_EFI_STUB_32BIT or CONFIG_EFI_STUB_64BIT. All of these are -boolean Kconfig options. Then build U-Boot as normal, e.g. +To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), enable +CONFIG_EFI, CONFIG_EFI_STUB, and select either CONFIG_EFI_STUB_32BIT or +CONFIG_EFI_STUB_64BIT. The efi-x86_payload configs (efi-x86_payload32_defconfig +and efi-x86_payload32_defconfig) are set up for this. Then build U-Boot as +normal, e.g. - make qemu-x86_defconfig + make efi-x86_payload32_defconfig (or efi-x86_payload64_defconfig) make You will end up with one of these files depending on what you build for: @@ -211,11 +212,6 @@ Future work ----------- This work could be extended in a number of ways: -- Add a generic x86 EFI payload configuration. At present you need to modify -an existing one, but mostly the low-level x86 code is disabled when booting -on EFI anyway, so a generic 'EFI' board could be created with a suitable set -of drivers enabled. - - Add ARM support - Add 64-bit application support @@ -235,16 +231,15 @@ Where is the code? lib/efi payload stub, application, support code. Mostly arch-neutral -arch/x86/lib/efi - helper functions for the fake DRAM init, etc. These can be used by - any board that runs as a payload. - arch/x86/cpu/efi - x86 support code for running as an EFI application + x86 support code for running as an EFI application and payload -board/efi/efi-x86/efi.c +board/efi/efi-x86_app/efi.c x86 board code for running as an EFI application +board/efi/efi-x86_payload + generic x86 EFI payload board support code + common/cmd_efi.c the 'efi' command diff --git a/doc/README.vxworks b/doc/README.vxworks index 1aa8e44f420..3e087112076 100644 --- a/doc/README.vxworks +++ b/doc/README.vxworks @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2013, Miao Yan <miao.yan@windriver.com> -# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# Copyright (C) 2015-2018, Bin Meng <bmeng.cn@gmail.com> VxWorks Support =============== @@ -15,10 +15,13 @@ For booting old kernels (6.9.x) on PowerPC and ARM, and all kernel versions on other architectures, 'bootvx' shall be used. For booting VxWorks 7 kernels on PowerPC and ARM, 'bootm' shall be used. +With CONFIG_EFI_LOADER option, it's possible to chain load a VxWorks x86 kernel +via the UEFI boot loader application for VxWorks loaded by 'bootefi' command. + VxWorks 7 on PowerPC and ARM --------------------------- -From VxWorks 7, VxWorks starts adopting device tree as its hardware decription -mechansim (for PowerPC and ARM), thus requiring boot interface changes. +From VxWorks 7, VxWorks starts adopting device tree as its hardware description +mechanism (for PowerPC and ARM), thus requiring boot interface changes. This section will describe the new interface. For PowerPC, the calling convention of the new VxWorks entry point conforms to @@ -53,6 +56,9 @@ gatewayip, hostname, othbootargs. When using 'bootm', just define "bootargs" in the environment and U-Boot will handle bootline fix up for the kernel dtb automatically. +When using 'bootefi' to chain load an x86 kernel, the UEFI boot loader +application for VxWorks takes care of the kernel bootline preparation. + Serial console -------------- It's very common that VxWorks BSPs configure a different baud rate for the @@ -63,9 +69,9 @@ look like VxWorks hangs somewhere as nothing outputs on the serial console. x86-specific information ------------------------ -Before loading an x86 kernel, one additional environment variable need to be -provided. This is "vx_phys_mem_base", which represent the physical memory -base address of VxWorks. +Before direct loading an x86 kernel via 'bootvx', one additional environment +variable need to be provided. This is "vx_phys_mem_base", which represent the +physical memory base address of VxWorks. Check VxWorks kernel configuration to look for LOCAL_MEM_LOCAL_ADRS. For VxWorks 7, this is normally a virtual address and you need find out its diff --git a/doc/README.x86 b/doc/README.x86 index 78664c3d0a5..9162ea17d82 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -1134,18 +1134,43 @@ the "Power" submenu from the Windows start menu. EFI Support ----------- U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI. -This is enabled with CONFIG_EFI_STUB. U-Boot can also run as an EFI -application, with CONFIG_EFI_APP. The CONFIG_EFI_LOADER option, where U-Booot -provides an EFI environment to the kernel (i.e. replaces UEFI completely but -provides the same EFI run-time services) is not currently supported on x86. - -See README.efi for details of EFI support in U-Boot. +This is enabled with CONFIG_EFI_STUB to boot from both 32-bit and 64-bit +UEFI BIOS. U-Boot can also run as an EFI application, with CONFIG_EFI_APP. +The CONFIG_EFI_LOADER option, where U-Boot provides an EFI environment to +the kernel (i.e. replaces UEFI completely but provides the same EFI run-time +services) is supported too. For example, we can even use 'bootefi' command +to load a 'u-boot-payload.efi', see below test logs on QEMU. + + => load ide 0 3000000 u-boot-payload.efi + 489787 bytes read in 138 ms (3.4 MiB/s) + => bootefi 3000000 + Scanning disk ide.blk#0... + Found 2 disks + WARNING: booting without device tree + ## Starting EFI application at 03000000 ... + U-Boot EFI Payload + + + U-Boot 2018.07-rc2 (Jun 23 2018 - 17:12:58 +0800) + + CPU: x86_64, vendor AMD, device 663h + DRAM: 2 GiB + MMC: + Video: 1024x768x32 + Model: EFI x86 Payload + Net: e1000: 52:54:00:12:34:56 + + Warning: e1000#0 using MAC address from ROM + eth0: e1000#0 + No controllers found + Hit any key to stop autoboot: 0 + +See README.u-boot_on_efi and README.uefi for details of EFI support in U-Boot. 64-bit Support -------------- U-Boot supports booting a 64-bit kernel directly and is able to change to -64-bit mode to do so. It also supports (with CONFIG_EFI_STUB) booting from -both 32-bit and 64-bit UEFI. However, U-Boot itself is currently always built +64-bit mode to do so. However, U-Boot itself is currently always built in 32-bit mode. Some access to the full memory range is provided with arch_phys_memset(). diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index bcab76d0509..f7c919d3b0a 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c @@ -654,7 +654,7 @@ static int meson_saradc_probe(struct udevice *dev) struct meson_saradc_priv *priv = dev_get_priv(dev); int ret; - ret = regmap_init_mem(dev, &priv->regmap); + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); if (ret) return ret; diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 0792373cfc4..f9502b36bac 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -37,6 +37,13 @@ config BLOCK_CACHE it will prevent repeated reads from directory structures and other filesystem data structures. +config SPL_BLOCK_CACHE + bool "Use block device cache in SPL" + depends on SPL_BLK + default n + help + This option enables the disk-block cache in SPL + config IDE bool "Support IDE controllers" select HAVE_BLOCK_DEVICE diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 5fcafb193ee..0e80ce94058 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -11,4 +11,4 @@ endif obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_SANDBOX) += sandbox.o -obj-$(CONFIG_BLOCK_CACHE) += blkcache.o +obj-$(CONFIG_$(SPL_)BLOCK_CACHE) += blkcache.o diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 58139b13a89..426c67db9b4 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_ARCH_MESON) += clk_meson.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c new file mode 100644 index 00000000000..3850128e5c7 --- /dev/null +++ b/drivers/clk/clk_meson.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <dt-bindings/clock/gxbb-clkc.h> +#include "clk_meson.h" + +#define XTAL_RATE 24000000 + +struct meson_clk { + void __iomem *addr; +}; + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id); + +struct meson_gate gates[] = { + /* Everything Else (EE) domain gates */ + MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0), + MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1), + MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5), + MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6), + MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7), + MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8), + MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9), + MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10), + MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11), + MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12), + MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13), + MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14), + MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15), + MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16), + MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17), + MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18), + MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19), + MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23), + MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24), + MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25), + MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26), + MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30), + + MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2), + MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3), + MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4), + MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6), + MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7), + MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8), + MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9), + MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10), + MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11), + MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12), + MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13), + MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14), + MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15), + MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16), + MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20), + MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21), + MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22), + MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23), + MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24), + MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25), + MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26), + MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28), + MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29), + MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30), + MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31), + + MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1), + MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2), + MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3), + MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4), + MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8), + MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9), + MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11), + MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12), + MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15), + MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22), + MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25), + MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26), + MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29), + + MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1), + MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2), + MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3), + MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4), + MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8), + MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10), + MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14), + MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16), + MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20), + MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21), + MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22), + MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24), + MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25), + MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26), + MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31), + + /* Always On (AO) domain gates */ + MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0), + MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1), + MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2), + MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3), + MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4), + + /* PLL Gates */ + /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */ + MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28), + MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29), + MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30), + MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31), + MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14), + MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14), + MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14), + /* CLKID_CLK81 is critical for the system */ + + /* Peripheral Gates */ + MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8), + MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7), + MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23), + MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7), +}; + +static int meson_set_gate(struct clk *clk, bool on) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct meson_gate *gate; + + if (clk->id >= ARRAY_SIZE(gates)) + return -ENOENT; + + gate = &gates[clk->id]; + + if (gate->reg == 0) + return 0; + + clrsetbits_le32(priv->addr + gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); + return 0; +} + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate(clk, true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate(clk, false); +} + +static unsigned long meson_clk81_get_rate(struct clk *clk) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + unsigned long parent_rate; + u32 reg; + int parents[] = { + -1, + -1, + CLKID_FCLK_DIV7, + CLKID_MPLL1, + CLKID_MPLL2, + CLKID_FCLK_DIV4, + CLKID_FCLK_DIV3, + CLKID_FCLK_DIV5 + }; + + /* mux */ + reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); + reg = (reg >> 12) & 7; + + switch (reg) { + case 0: + parent_rate = XTAL_RATE; + break; + case 1: + return -ENOENT; + default: + parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]); + } + + /* divider */ + reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); + reg = reg & ((1 << 7) - 1); + + return parent_rate / reg; +} + +static long mpll_rate_from_params(unsigned long parent_rate, + unsigned long sdm, + unsigned long n2) +{ + unsigned long divisor = (SDM_DEN * n2) + sdm; + + if (n2 < N2_MIN) + return -EINVAL; + + return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); +} + +static struct parm meson_mpll0_parm[3] = { + {HHI_MPLL_CNTL7, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */ +}; + +static struct parm meson_mpll1_parm[3] = { + {HHI_MPLL_CNTL8, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */ +}; + +static struct parm meson_mpll2_parm[3] = { + {HHI_MPLL_CNTL9, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */ +}; + +/* + * MultiPhase Locked Loops are outputs from a PLL with additional frequency + * scaling capabilities. MPLL rates are calculated as: + * + * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) + */ +static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *psdm, *pn2; + unsigned long reg, sdm, n2; + unsigned long parent_rate; + + switch (id) { + case CLKID_MPLL0: + psdm = &meson_mpll0_parm[0]; + pn2 = &meson_mpll0_parm[1]; + break; + case CLKID_MPLL1: + psdm = &meson_mpll1_parm[0]; + pn2 = &meson_mpll1_parm[1]; + break; + case CLKID_MPLL2: + psdm = &meson_mpll2_parm[0]; + pn2 = &meson_mpll2_parm[1]; + break; + default: + return -ENOENT; + } + + parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL); + if (IS_ERR_VALUE(parent_rate)) + return parent_rate; + + reg = readl(priv->addr + psdm->reg_off); + sdm = PARM_GET(psdm->width, psdm->shift, reg); + + reg = readl(priv->addr + pn2->reg_off); + n2 = PARM_GET(pn2->width, pn2->shift, reg); + + return mpll_rate_from_params(parent_rate, sdm, n2); +} + +static struct parm meson_fixed_pll_parm[3] = { + {HHI_MPLL_CNTL, 0, 9}, /* pm */ + {HHI_MPLL_CNTL, 9, 5}, /* pn */ + {HHI_MPLL_CNTL, 16, 2}, /* pod */ +}; + +static struct parm meson_sys_pll_parm[3] = { + {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */ + {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */ + {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */ +}; + +static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *pm, *pn, *pod; + unsigned long parent_rate_mhz = XTAL_RATE / 1000000; + u16 n, m, od; + u32 reg; + + switch (id) { + case CLKID_FIXED_PLL: + pm = &meson_fixed_pll_parm[0]; + pn = &meson_fixed_pll_parm[1]; + pod = &meson_fixed_pll_parm[2]; + break; + case CLKID_SYS_PLL: + pm = &meson_sys_pll_parm[0]; + pn = &meson_sys_pll_parm[1]; + pod = &meson_sys_pll_parm[2]; + break; + default: + return -ENOENT; + } + + reg = readl(priv->addr + pn->reg_off); + n = PARM_GET(pn->width, pn->shift, reg); + + reg = readl(priv->addr + pm->reg_off); + m = PARM_GET(pm->width, pm->shift, reg); + + reg = readl(priv->addr + pod->reg_off); + od = PARM_GET(pod->width, pod->shift, reg); + + return ((parent_rate_mhz * m / n) >> od) * 1000000; +} + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) +{ + ulong rate; + + switch (id) { + case CLKID_FIXED_PLL: + case CLKID_SYS_PLL: + rate = meson_pll_get_rate(clk, id); + break; + case CLKID_FCLK_DIV2: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2; + break; + case CLKID_FCLK_DIV3: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3; + break; + case CLKID_FCLK_DIV4: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4; + break; + case CLKID_FCLK_DIV5: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5; + break; + case CLKID_FCLK_DIV7: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7; + break; + case CLKID_MPLL0: + case CLKID_MPLL1: + case CLKID_MPLL2: + rate = meson_mpll_get_rate(clk, id); + break; + case CLKID_CLK81: + rate = meson_clk81_get_rate(clk); + break; + default: + if (gates[id].reg != 0) { + /* a clock gate */ + rate = meson_clk81_get_rate(clk); + break; + } + return -ENOENT; + } + + printf("clock %lu has rate %lu\n", id, rate); + return rate; +} + +static ulong meson_clk_get_rate(struct clk *clk) +{ + return meson_clk_get_rate_by_id(clk, clk->id); +} + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + priv->addr = dev_read_addr_ptr(dev); + + debug("meson-clk: probed at addr %p\n", priv->addr); + + return 0; +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, +}; + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,gxbb-clkc" }, + { .compatible = "amlogic,gxl-clkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk) = { + .name = "meson_clk", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto_alloc_size = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; diff --git a/drivers/clk/clk_meson.h b/drivers/clk/clk_meson.h new file mode 100644 index 00000000000..7adc55a9803 --- /dev/null +++ b/drivers/clk/clk_meson.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef CLK_MESON_H +#define CLK_MESON_H + +/* Gate Structure */ + +struct meson_gate { + unsigned int reg; + unsigned int bit; +}; + +#define MESON_GATE(id, _reg, _bit) \ + [id] = { \ + .reg = (_reg), \ + .bit = (_bit), \ + } + +/* PLL Parameters */ + +struct parm { + u16 reg_off; + u8 shift; + u8 width; +}; + +#define PMASK(width) GENMASK(width - 1, 0) +#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) +#define CLRPMASK(width, shift) (~SETPMASK(width, shift)) + +#define PARM_GET(width, shift, reg) \ + (((reg) & SETPMASK(width, shift)) >> (shift)) +#define PARM_SET(width, shift, reg, val) \ + (((reg) & CLRPMASK(width, shift)) | ((val) << (shift))) + +/* MPLL Parameters */ + +#define SDM_DEN 16384 +#define N2_MIN 4 +#define N2_MAX 511 + +#endif diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index b3614a13555..1198ec5cbfc 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -43,6 +43,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, /* Module Clocks */ MOD_CLK_BASE @@ -70,6 +71,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), @@ -96,6 +98,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), + DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238), + DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), @@ -194,6 +198,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), + DEF_MOD("rpc", 917, R8A77990_CLK_RPC), DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 17592db3d34..e9c3aec9607 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -41,6 +41,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_SSPSRC, /* Module Clocks */ @@ -67,6 +68,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), /* Core Clock Outputs */ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), @@ -89,6 +91,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), + DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238), + DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), @@ -153,6 +157,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), + DEF_MOD("rpc", 917, R8A77995_CLK_RPC), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b7e4ffb09d6..29af22ecc70 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -109,7 +109,7 @@ config MSM_GPIO - MSM8916 config MXC_GPIO - bool "Freescale/NXP MXC UART driver" + bool "Freescale/NXP MXC GPIO driver" help Support GPIO controllers on various i.MX platforms diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index e410f5f9dfe..1a1d37ae2a4 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -7,11 +7,14 @@ */ #include <common.h> +#include <dm.h> +#include <fdtdec.h> #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/davinci_misc.h> +#ifndef CONFIG_DM_GPIO static struct gpio_registry { int is_registered; char name[GPIO_NAME_SIZE]; @@ -303,7 +306,7 @@ static const struct pinmux_config gpio_pinmux[] = { #define davinci_configure_pin_mux(a, b) #endif /* CONFIG_SOC_DA8XX */ -int gpio_request(unsigned gpio, const char *label) +int gpio_request(unsigned int gpio, const char *label) { if (gpio >= MAX_NUM_GPIOS) return -1; @@ -320,7 +323,7 @@ int gpio_request(unsigned gpio, const char *label) return 0; } -int gpio_free(unsigned gpio) +int gpio_free(unsigned int gpio) { if (gpio >= MAX_NUM_GPIOS) return -1; @@ -333,42 +336,30 @@ int gpio_free(unsigned gpio) /* Do not configure as input or change pin mux here */ return 0; } +#endif -int gpio_direction_input(unsigned gpio) +static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio, int value) { - struct davinci_gpio *bank; - - bank = GPIO_BANK(gpio); - setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); + clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); + gpio_set_value(gpio, value); return 0; } -int gpio_direction_output(unsigned gpio, int value) +static int _gpio_direction_input(struct davinci_gpio *bank, unsigned int gpio) { - struct davinci_gpio *bank; - - bank = GPIO_BANK(gpio); - clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); - gpio_set_value(gpio, value); + setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); return 0; } -int gpio_get_value(unsigned gpio) +static int _gpio_get_value(struct davinci_gpio *bank, unsigned int gpio) { - struct davinci_gpio *bank; unsigned int ip; - - bank = GPIO_BANK(gpio); ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio)); return ip ? 1 : 0; } -int gpio_set_value(unsigned gpio, int value) +static int _gpio_set_value(struct davinci_gpio *bank, unsigned int gpio, int value) { - struct davinci_gpio *bank; - - bank = GPIO_BANK(gpio); - if (value) bank->set_data = 1U << GPIO_BIT(gpio); else @@ -377,14 +368,21 @@ int gpio_set_value(unsigned gpio, int value) return 0; } +static int _gpio_get_dir(struct davinci_gpio *bank, unsigned int gpio) +{ + return in_le32(&bank->dir) & (1U << GPIO_BIT(gpio)); +} + +#ifndef CONFIG_DM_GPIO + void gpio_info(void) { - unsigned gpio, dir, val; + unsigned int gpio, dir, val; struct davinci_gpio *bank; for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) { bank = GPIO_BANK(gpio); - dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gpio)); + dir = _gpio_get_dir(bank, gpio); val = gpio_get_value(gpio); printf("% 4d: %s: %d [%c] %s\n", @@ -393,3 +391,150 @@ void gpio_info(void) gpio_registry[gpio].name); } } + +int gpio_direction_input(unsigned int gpio) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gpio); + return _gpio_direction_input(bank, gpio); +} + +int gpio_direction_output(unsigned int gpio, int value) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gpio); + return _gpio_direction_output(bank, gpio, value); +} + +int gpio_get_value(unsigned int gpio) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gpio); + return _gpio_get_value(bank, gpio); +} + +int gpio_set_value(unsigned int gpio, int value) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gpio); + return _gpio_set_value(bank, gpio, value); +} + +#else /* CONFIG_DM_GPIO */ + +static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset) +{ + struct davinci_gpio_bank *bank = dev_get_priv(dev); + + /* The device tree is not broken into banks but the infrastructure is + * expecting it this way, so we'll first include the 0x10 offset, then + * calculate the bank manually based on the offset. + */ + + return ((struct davinci_gpio *)bank->base) + 0x10 + (offset >> 5); +} + +static int davinci_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset); + + _gpio_direction_input(base, offset); + return 0; +} + +static int davinci_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset); + + _gpio_direction_output(base, offset, value); + return 0; +} + +static int davinci_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset); + + return _gpio_get_value(base, offset); +} + +static int davinci_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset); + + _gpio_set_value(base, offset, value); + + return 0; +} + +static int davinci_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + unsigned int dir; + struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset); + + dir = _gpio_get_dir(base, offset); + + if (dir) + return GPIOF_INPUT; + + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops gpio_davinci_ops = { + .direction_input = davinci_gpio_direction_input, + .direction_output = davinci_gpio_direction_output, + .get_value = davinci_gpio_get_value, + .set_value = davinci_gpio_set_value, + .get_function = davinci_gpio_get_function, +}; + +static int davinci_gpio_probe(struct udevice *dev) +{ + struct davinci_gpio_bank *bank = dev_get_priv(dev); + struct davinci_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + + uc_priv->bank_name = plat->port_name; + uc_priv->gpio_count = fdtdec_get_int(fdt, node, "ti,ngpio", -1); + bank->base = (struct davinci_gpio *)plat->base; + return 0; +} + +static const struct udevice_id davinci_gpio_ids[] = { + { .compatible = "ti,dm6441-gpio" }, + { } +}; + +static int davinci_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct davinci_gpio_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = addr; + return 0; +} + +U_BOOT_DRIVER(gpio_davinci) = { + .name = "gpio_davinci", + .id = UCLASS_GPIO, + .ops = &gpio_davinci_ops, + .ofdata_to_platdata = of_match_ptr(davinci_gpio_ofdata_to_platdata), + .of_match = davinci_gpio_ids, + .bind = dm_scan_fdt_dev, + .platdata_auto_alloc_size = sizeof(struct davinci_gpio_platdata), + .probe = davinci_gpio_probe, + .priv_auto_alloc_size = sizeof(struct davinci_gpio_bank), +}; + +#endif diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index d128f942a06..79a975ce71b 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -288,11 +288,17 @@ static int omap_gpio_probe(struct udevice *dev) struct gpio_bank *bank = dev_get_priv(dev); struct omap_gpio_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int banknum; + char name[18], *str; - uc_priv->bank_name = plat->port_name; + banknum = plat->bank_index; + sprintf(name, "GPIO%d_", banknum + 1); + str = strdup(name); + if (!str) + return -ENOMEM; + uc_priv->bank_name = str; uc_priv->gpio_count = GPIO_PER_BANK; bank->base = (void *)plat->base; - return 0; } diff --git a/drivers/i2c/meson_i2c.c b/drivers/i2c/meson_i2c.c index 8c9318d4f15..7d06d95cf38 100644 --- a/drivers/i2c/meson_i2c.c +++ b/drivers/i2c/meson_i2c.c @@ -3,8 +3,8 @@ * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com> */ #include <common.h> -#include <asm/arch/i2c.h> #include <asm/io.h> +#include <clk.h> #include <dm.h> #include <i2c.h> @@ -42,6 +42,7 @@ struct i2c_regs { }; struct meson_i2c { + struct clk clk; struct i2c_regs *regs; struct i2c_msg *msg; /* Current I2C message */ bool last; /* Whether the message is the last */ @@ -221,9 +222,13 @@ static int meson_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { struct meson_i2c *i2c = dev_get_priv(bus); - unsigned int clk_rate = MESON_I2C_CLK_RATE; + ulong clk_rate; unsigned int div; + clk_rate = clk_get_rate(&i2c->clk); + if (IS_ERR_VALUE(clk_rate)) + return -EINVAL; + div = DIV_ROUND_UP(clk_rate, speed * 4); /* clock divider has 12 bits */ @@ -238,7 +243,7 @@ static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIVEXT_MASK, (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT); - debug("meson i2c: set clk %u, src %u, div %u\n", speed, clk_rate, div); + debug("meson i2c: set clk %u, src %lu, div %u\n", speed, clk_rate, div); return 0; } @@ -246,6 +251,15 @@ static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) static int meson_i2c_probe(struct udevice *bus) { struct meson_i2c *i2c = dev_get_priv(bus); + int ret; + + ret = clk_get_by_index(bus, 0, &i2c->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&i2c->clk); + if (ret) + return ret; i2c->regs = dev_read_addr_ptr(bus); clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index 56cd0700fa4..b777404c097 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -21,7 +21,7 @@ */ struct swap_case_platdata { u16 command; - u32 bar[2]; + u32 bar[6]; }; #define offset_to_barnum(offset) \ diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 94fbf89e4b8..bdc272142e5 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -143,6 +143,7 @@ config NAND_MXC config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 + select SYS_NAND_SELF_INIT imply CMD_NAND select APBH_DMA select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 @@ -151,6 +152,21 @@ config NAND_MXS This enables NAND driver for the NAND flash controller on the MXS processors. +if NAND_MXS + +config NAND_MXS_DT + bool "Support MXS NAND controller as a DT device" + depends on OF_CONTROL && MTD + help + Enable the driver for MXS NAND flash on platforms using + device tree. + +config NAND_MXS_USE_MINIMUM_ECC + bool "Use minimum ECC strength supported by the controller" + default false + +endif + config NAND_ZYNQ bool "Support for Zynq Nand controller" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index e20ef077738..c61e3f38391 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o +obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o @@ -55,6 +56,7 @@ obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o +obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index b9ffa7cbae0..e3341812a20 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -13,8 +13,9 @@ */ #include <common.h> -#include <linux/mtd/mtd.h> +#include <dm.h> #include <linux/mtd/rawnand.h> +#include <linux/sizes.h> #include <linux/types.h> #include <malloc.h> #include <linux/errno.h> @@ -24,11 +25,10 @@ #include <asm/mach-imx/regs-bch.h> #include <asm/mach-imx/regs-gpmi.h> #include <asm/arch/sys_proto.h> -#include <asm/mach-imx/dma.h> +#include "mxs_nand.h" #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 -#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else @@ -45,35 +45,7 @@ #define MXS_NAND_BCH_TIMEOUT 10000 -struct mxs_nand_info { - int cur_chip; - - uint32_t cmd_queue_len; - uint32_t data_buf_size; - - uint8_t *cmd_buf; - uint8_t *data_buf; - uint8_t *oob_buf; - - uint8_t marking_block_bad; - uint8_t raw_oob_mode; - - /* Functions with altered behaviour */ - int (*hooked_read_oob)(struct mtd_info *mtd, - loff_t from, struct mtd_oob_ops *ops); - int (*hooked_write_oob)(struct mtd_info *mtd, - loff_t to, struct mtd_oob_ops *ops); - int (*hooked_block_markbad)(struct mtd_info *mtd, - loff_t ofs); - - /* DMA descriptors */ - struct mxs_dma_desc **desc; - uint32_t desc_index; -}; - struct nand_ecclayout fake_ecc_layout; -static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE; -static int galois_field = 13; /* * Cache management functions @@ -134,61 +106,21 @@ static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) info->desc_index = 0; } -static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size) -{ - return page_data_size / chunk_data_size; -} - -static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) -{ - return ecc_strength * galois_field; -} - static uint32_t mxs_nand_aux_status_offset(void) { return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; } -static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, - uint32_t page_oob_size) -{ - int ecc_strength; - int max_ecc_strength_supported; - - /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ - if (is_mx6sx() || is_mx7()) - max_ecc_strength_supported = 62; - else - max_ecc_strength_supported = 40; - - /* - * Determine the ECC layout with the formula: - * ECC bits per chunk = (total page spare data bits) / - * (bits per ECC level) / (chunks per page) - * where: - * total page spare data bits = - * (page oob size - meta data size) * (bits per byte) - */ - ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8) - / (galois_field * - mxs_nand_ecc_chunk_cnt(page_data_size)); - - return min(round_down(ecc_strength, 2), max_ecc_strength_supported); -} - -static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, - uint32_t ecc_strength) +static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo, + uint32_t page_data_size) { - uint32_t chunk_data_size_in_bits; - uint32_t chunk_ecc_size_in_bits; + uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8; + uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len; uint32_t chunk_total_size_in_bits; uint32_t block_mark_chunk_number; uint32_t block_mark_chunk_bit_offset; uint32_t block_mark_bit_offset; - chunk_data_size_in_bits = chunk_data_size * 8; - chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength); - chunk_total_size_in_bits = chunk_data_size_in_bits + chunk_ecc_size_in_bits; @@ -213,7 +145,7 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, (block_mark_chunk_number * chunk_total_size_in_bits); if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) - return 1; + return -EINVAL; /* * Now that we know the chunk number in which the block mark appears, @@ -222,36 +154,100 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, block_mark_bit_offset -= block_mark_chunk_number * chunk_ecc_size_in_bits; - return block_mark_bit_offset; + geo->block_mark_byte_offset = block_mark_bit_offset >> 3; + geo->block_mark_bit_offset = block_mark_bit_offset & 0x7; + + return 0; } -static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd) +static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo, + struct mtd_info *mtd, + unsigned int ecc_strength, + unsigned int ecc_step) { - uint32_t ecc_strength; - ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); - return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + + switch (ecc_step) { + case SZ_512: + geo->gf_len = 13; + break; + case SZ_1K: + geo->gf_len = 14; + break; + default: + return -EINVAL; + } + + geo->ecc_chunk_size = ecc_step; + geo->ecc_strength = round_up(ecc_strength, 2); + + /* Keep the C >= O */ + if (geo->ecc_chunk_size < mtd->oobsize) + return -EINVAL; + + if (geo->ecc_strength > nand_info->max_ecc_strength_supported) + return -EINVAL; + + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + + return 0; } -static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd) +static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, + struct mtd_info *mtd) { - uint32_t ecc_strength; - ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); - return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + + /* The default for the length of Galois Field. */ + geo->gf_len = 13; + + /* The default for chunk size. */ + geo->ecc_chunk_size = 512; + + if (geo->ecc_chunk_size < mtd->oobsize) { + geo->gf_len = 14; + geo->ecc_chunk_size *= 2; + } + + if (mtd->oobsize > geo->ecc_chunk_size) { + printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", + geo->ecc_chunk_size); + return -EINVAL; + } + + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + + /* + * Determine the ECC layout with the formula: + * ECC bits per chunk = (total page spare data bits) / + * (bits per ECC level) / (chunks per page) + * where: + * total page spare data bits = + * (page oob size - meta data size) * (bits per byte) + */ + geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8) + / (geo->gf_len * geo->ecc_chunk_count); + + geo->ecc_strength = min(round_down(geo->ecc_strength, 2), + nand_info->max_ecc_strength_supported); + + return 0; } /* * Wait for BCH complete IRQ and clear the IRQ */ -static int mxs_nand_wait_for_bch_complete(void) +static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info) { - struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; int timeout = MXS_NAND_BCH_TIMEOUT; int ret; - ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, + ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg, BCH_CTRL_COMPLETE_IRQ, timeout); - writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); + writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr); return ret; } @@ -349,11 +345,9 @@ static int mxs_nand_device_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(chip); - struct mxs_gpmi_regs *gpmi_regs = - (struct mxs_gpmi_regs *)MXS_GPMI_BASE; uint32_t tmp; - tmp = readl(&gpmi_regs->hw_gpmi_stat); + tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat); tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip); return tmp & 1; @@ -377,18 +371,15 @@ static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) * swapping the block mark, or swapping it *back* -- but it doesn't matter * because the the operation is the same. */ -static void mxs_nand_swap_block_mark(struct mtd_info *mtd, - uint8_t *data_buf, uint8_t *oob_buf) +static void mxs_nand_swap_block_mark(struct bch_geometry *geo, + uint8_t *data_buf, uint8_t *oob_buf) { - uint32_t bit_offset; - uint32_t buf_offset; + uint32_t bit_offset = geo->block_mark_bit_offset; + uint32_t buf_offset = geo->block_mark_byte_offset; uint32_t src; uint32_t dst; - bit_offset = mxs_nand_mark_bit_offset(mtd); - buf_offset = mxs_nand_mark_byte_offset(mtd); - /* * Get the byte from the data area that overlays the block mark. Since * the ECC engine applies its own view to the bits in the page, the @@ -564,6 +555,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, int page) { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; uint32_t corrected = 0, failed = 0; @@ -652,7 +644,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, goto rtn; } - ret = mxs_nand_wait_for_bch_complete(); + ret = mxs_nand_wait_for_bch_complete(nand_info); if (ret) { printf("MXS NAND: BCH read timeout\n"); goto rtn; @@ -662,11 +654,11 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, mxs_nand_inval_data_buf(nand_info); /* Read DMA completed, now do the mark swapping. */ - mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); + mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf); /* Loop over status bytes, accumulating ECC status. */ status = nand_info->oob_buf + mxs_nand_aux_status_offset(); - for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) { + for (i = 0; i < geo->ecc_chunk_count; i++) { if (status[i] == 0x00) continue; @@ -714,6 +706,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, int oob_required, int page) { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; int ret; @@ -722,7 +715,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize); /* Handle block mark swapping. */ - mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); + mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf); /* Compile the DMA descriptor - write data. */ d = mxs_nand_get_dma_desc(nand_info); @@ -759,7 +752,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, goto rtn; } - ret = mxs_nand_wait_for_bch_complete(); + ret = mxs_nand_wait_for_bch_complete(nand_info); if (ret) { printf("MXS NAND: BCH write timeout\n"); goto rtn; @@ -970,57 +963,69 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs) return 0; } +static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + + if (chip->ecc.strength > 0 && chip->ecc.size > 0) + return mxs_nand_calc_ecc_layout_by_info(geo, mtd, + chip->ecc.strength, chip->ecc.size); + + if (nand_info->use_minimum_ecc || + mxs_nand_calc_ecc_layout(geo, mtd)) { + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) + return -EINVAL; + + return mxs_nand_calc_ecc_layout_by_info(geo, mtd, + chip->ecc_strength_ds, chip->ecc_step_ds); + } + + return 0; +} + /* - * Nominally, the purpose of this function is to look for or create the bad - * block table. In fact, since the we call this function at the very end of - * the initialization process started by nand_scan(), and we doesn't have a - * more formal mechanism, we "hook" this function to continue init process. - * * At this point, the physical NAND Flash chips have been identified and * counted, so we know the physical geometry. This enables us to make some * important configuration decisions. * * The return value of this function propagates directly back to this driver's - * call to nand_scan(). Anything other than zero will cause this driver to + * board_nand_init(). Anything other than zero will cause this driver to * tear everything down and declare failure. */ -static int mxs_nand_scan_bbt(struct mtd_info *mtd) +int mxs_nand_setup_ecc(struct mtd_info *mtd) { struct nand_chip *nand = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(nand); - struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; + struct bch_geometry *geo = &nand_info->bch_geometry; + struct mxs_bch_regs *bch_regs = nand_info->bch_regs; uint32_t tmp; + int ret; - if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) { - galois_field = 14; - chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2; - } + ret = mxs_nand_set_geometry(mtd, geo); + if (ret) + return ret; - if (mtd->oobsize > chunk_data_size) { - printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size); - return -EINVAL; - } + mxs_nand_calc_mark_offset(geo, mtd->writesize); /* Configure BCH and set NFC geometry */ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); /* Configure layout 0 */ - tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) - << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; + tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; - tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) - << BCH_FLASHLAYOUT0_ECC0_OFFSET; - tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; - tmp |= (14 == galois_field ? 1 : 0) << + tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET; + tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + tmp |= (geo->gf_len == 14 ? 1 : 0) << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout0); tmp = (mtd->writesize + mtd->oobsize) << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; - tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) - << BCH_FLASHLAYOUT1_ECCN_OFFSET; - tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; - tmp |= (14 == galois_field ? 1 : 0) << + tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET; + tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + tmp |= (geo->gf_len == 14 ? 1 : 0) << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout1); @@ -1046,8 +1051,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd) mtd->_block_markbad = mxs_nand_hook_block_markbad; } - /* We use the reference implementation for bad block management. */ - return nand_default_bbt(mtd); + return 0; } /* @@ -1088,12 +1092,8 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) /* * Initializes the NFC hardware. */ -int mxs_nand_init(struct mxs_nand_info *info) +int mxs_nand_init_dma(struct mxs_nand_info *info) { - struct mxs_gpmi_regs *gpmi_regs = - (struct mxs_gpmi_regs *)MXS_GPMI_BASE; - struct mxs_bch_regs *bch_regs = - (struct mxs_bch_regs *)MXS_BCH_BASE; int i = 0, j, ret = 0; info->desc = malloc(sizeof(struct mxs_dma_desc *) * @@ -1122,14 +1122,14 @@ int mxs_nand_init(struct mxs_nand_info *info) } /* Reset the GPMI block. */ - mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); - mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); + mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg); + mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg); /* * Choose NAND mode, set IRQ polarity, disable write protection and * select BCH ECC. */ - clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, + clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1, GPMI_CTRL1_GPMI_MODE, GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | GPMI_CTRL1_BCH_MODE); @@ -1149,16 +1149,7 @@ err1: return ret; } -/*! - * This function is called during the driver binding process. - * - * @param pdev the device structure used to store device specific - * information that is used by the suspend, resume and - * remove functions - * - * @return The function always returns 0. - */ -int board_nand_init(struct nand_chip *nand) +int mxs_nand_init_spl(struct nand_chip *nand) { struct mxs_nand_info *nand_info; int err; @@ -1170,31 +1161,83 @@ int board_nand_init(struct nand_chip *nand) } memset(nand_info, 0, sizeof(struct mxs_nand_info)); + nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; + nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; err = mxs_nand_alloc_buffers(nand_info); if (err) - goto err1; + return err; + + err = mxs_nand_init_dma(nand_info); + if (err) + return err; + + nand_set_controller_data(nand, nand_info); + + nand->options |= NAND_NO_SUBPAGE_WRITE; + + nand->cmd_ctrl = mxs_nand_cmd_ctrl; + nand->dev_ready = mxs_nand_device_ready; + nand->select_chip = mxs_nand_select_chip; + + nand->read_byte = mxs_nand_read_byte; + nand->read_buf = mxs_nand_read_buf; + + nand->ecc.read_page = mxs_nand_ecc_read_page; + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.bytes = 9; + nand->ecc.size = 512; + nand->ecc.strength = 8; + + return 0; +} + +int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) +{ + struct mtd_info *mtd; + struct nand_chip *nand; + int err; + + nand = &nand_info->chip; + mtd = nand_to_mtd(nand); + err = mxs_nand_alloc_buffers(nand_info); + if (err) + return err; - err = mxs_nand_init(nand_info); + err = mxs_nand_init_dma(nand_info); if (err) - goto err2; + goto err_free_buffers; memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; +#endif + nand_set_controller_data(nand, nand_info); nand->options |= NAND_NO_SUBPAGE_WRITE; + if (nand_info->dev) + nand->flash_node = dev_of_offset(nand_info->dev); + nand->cmd_ctrl = mxs_nand_cmd_ctrl; nand->dev_ready = mxs_nand_device_ready; nand->select_chip = mxs_nand_select_chip; nand->block_bad = mxs_nand_block_bad; - nand->scan_bbt = mxs_nand_scan_bbt; nand->read_byte = mxs_nand_read_byte; nand->read_buf = mxs_nand_read_buf; nand->write_buf = mxs_nand_write_buf; + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) + goto err_free_buffers; + + if (mxs_nand_setup_ecc(mtd)) + goto err_free_buffers; + nand->ecc.read_page = mxs_nand_ecc_read_page; nand->ecc.write_page = mxs_nand_ecc_write_page; nand->ecc.read_oob = mxs_nand_ecc_read_oob; @@ -1202,16 +1245,58 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.layout = &fake_ecc_layout; nand->ecc.mode = NAND_ECC_HW; - nand->ecc.bytes = 9; - nand->ecc.size = 512; - nand->ecc.strength = 8; + nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size; + nand->ecc.strength = nand_info->bch_geometry.ecc_strength; + + /* second phase scan */ + err = nand_scan_tail(mtd); + if (err) + goto err_free_buffers; + + err = nand_register(0, mtd); + if (err) + goto err_free_buffers; return 0; -err2: +err_free_buffers: free(nand_info->data_buf); free(nand_info->cmd_buf); -err1: - free(nand_info); + return err; } + +#ifndef CONFIG_NAND_MXS_DT +void board_nand_init(void) +{ + struct mxs_nand_info *nand_info; + + nand_info = malloc(sizeof(struct mxs_nand_info)); + if (!nand_info) { + printf("MXS NAND: Failed to allocate private data\n"); + return; + } + memset(nand_info, 0, sizeof(struct mxs_nand_info)); + + nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; + nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; + + /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ + if (is_mx6sx() || is_mx7()) + nand_info->max_ecc_strength_supported = 62; + else + nand_info->max_ecc_strength_supported = 40; + +#ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC + nand_info->use_minimum_ecc = true; +#endif + + if (mxs_nand_init_ctrl(nand_info) < 0) + goto err; + + return; + +err: + free(nand_info); +} +#endif diff --git a/drivers/mtd/nand/mxs_nand.h b/drivers/mtd/nand/mxs_nand.h new file mode 100644 index 00000000000..4bd65cded94 --- /dev/null +++ b/drivers/mtd/nand/mxs_nand.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * NXP GPMI NAND flash driver + * + * Copyright (C) 2018 Toradex + * Authors: + * Stefan Agner <stefan.agner@toradex.com> + */ + +#include <linux/mtd/mtd.h> +#include <asm/cache.h> +#include <nand.h> +#include <asm/mach-imx/dma.h> + +/** + * @gf_len: The length of Galois Field. (e.g., 13 or 14) + * @ecc_strength: A number that describes the strength of the ECC + * algorithm. + * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note + * the first chunk in the page includes both data and + * metadata, so it's a bit larger than this value. + * @ecc_chunk_count: The number of ECC chunks in the page, + * @block_mark_byte_offset: The byte offset in the ECC-based page view at + * which the underlying physical block mark appears. + * @block_mark_bit_offset: The bit offset into the ECC-based page view at + * which the underlying physical block mark appears. + */ +struct bch_geometry { + unsigned int gf_len; + unsigned int ecc_strength; + unsigned int ecc_chunk_size; + unsigned int ecc_chunk_count; + unsigned int block_mark_byte_offset; + unsigned int block_mark_bit_offset; +}; + +struct mxs_nand_info { + struct nand_chip chip; + struct udevice *dev; + unsigned int max_ecc_strength_supported; + bool use_minimum_ecc; + int cur_chip; + + uint32_t cmd_queue_len; + uint32_t data_buf_size; + struct bch_geometry bch_geometry; + + uint8_t *cmd_buf; + uint8_t *data_buf; + uint8_t *oob_buf; + + uint8_t marking_block_bad; + uint8_t raw_oob_mode; + + struct mxs_gpmi_regs *gpmi_regs; + struct mxs_bch_regs *bch_regs; + + /* Functions with altered behaviour */ + int (*hooked_read_oob)(struct mtd_info *mtd, + loff_t from, struct mtd_oob_ops *ops); + int (*hooked_write_oob)(struct mtd_info *mtd, + loff_t to, struct mtd_oob_ops *ops); + int (*hooked_block_markbad)(struct mtd_info *mtd, + loff_t ofs); + + /* DMA descriptors */ + struct mxs_dma_desc **desc; + uint32_t desc_index; +}; + +int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info); +int mxs_nand_init_spl(struct nand_chip *nand); +int mxs_nand_setup_ecc(struct mtd_info *mtd); diff --git a/drivers/mtd/nand/mxs_nand_dt.c b/drivers/mtd/nand/mxs_nand_dt.c new file mode 100644 index 00000000000..f89eb091a99 --- /dev/null +++ b/drivers/mtd/nand/mxs_nand_dt.c @@ -0,0 +1,86 @@ +/* + * NXP GPMI NAND flash driver (DT initialization) + * + * Copyright (C) 2018 Toradex + * Authors: + * Stefan Agner <stefan.agner@toradex.com> + * + * Based on denali_dt.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/printk.h> + +#include "mxs_nand.h" + +struct mxs_nand_dt_data { + unsigned int max_ecc_strength_supported; +}; + +static const struct mxs_nand_dt_data mxs_nand_imx7d_data = { + .max_ecc_strength_supported = 62, +}; + +static const struct udevice_id mxs_nand_dt_ids[] = { + { + .compatible = "fsl,imx7d-gpmi-nand", + .data = (unsigned long)&mxs_nand_imx7d_data, + }, + { /* sentinel */ } +}; + +static int mxs_nand_dt_probe(struct udevice *dev) +{ + struct mxs_nand_info *info = dev_get_priv(dev); + const struct mxs_nand_dt_data *data; + struct resource res; + int ret; + + data = (void *)dev_get_driver_data(dev); + if (data) + info->max_ecc_strength_supported = data->max_ecc_strength_supported; + + info->dev = dev; + + ret = dev_read_resource_byname(dev, "gpmi-nand", &res); + if (ret) + return ret; + + info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res)); + + + ret = dev_read_resource_byname(dev, "bch", &res); + if (ret) + return ret; + + info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res)); + + info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); + + return mxs_nand_init_ctrl(info); +} + +U_BOOT_DRIVER(mxs_nand_dt) = { + .name = "mxs-nand-dt", + .id = UCLASS_MTD, + .of_match = mxs_nand_dt_ids, + .probe = mxs_nand_dt_probe, + .priv_auto_alloc_size = sizeof(struct mxs_nand_info), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(mxs_nand_dt), + &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize MXS NAND controller. (error %d)\n", + ret); +} diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c index 3e8b35f04ad..2d7bbe83cce 100644 --- a/drivers/mtd/nand/mxs_nand_spl.c +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -6,6 +6,7 @@ #include <common.h> #include <nand.h> #include <malloc.h> +#include "mxs_nand.h" static struct mtd_info *mtd; static struct nand_chip nand_chip; @@ -48,7 +49,29 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, } } -static int mxs_flash_ident(struct mtd_info *mtd) +#if defined (CONFIG_SPL_NAND_IDENT) + +/* Trying to detect the NAND flash using ONFi, JEDEC, and (extended) IDs */ +static int mxs_flash_full_ident(struct mtd_info *mtd) +{ + int nand_maf_id, nand_dev_id; + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_flash_dev *type; + + type = nand_get_flash_type(mtd, chip, &nand_maf_id, &nand_dev_id, NULL); + + if (IS_ERR(type)) { + chip->select_chip(mtd, -1); + return PTR_ERR(type); + } + + return 0; +} + +#else + +/* Trying to detect the NAND flash using ONFi only */ +static int mxs_flash_onfi_ident(struct mtd_info *mtd) { register struct nand_chip *chip = mtd_to_nand(mtd); int i; @@ -108,6 +131,19 @@ static int mxs_flash_ident(struct mtd_info *mtd) return 0; } +#endif /* CONFIG_SPL_NAND_IDENT */ + +static int mxs_flash_ident(struct mtd_info *mtd) +{ + int ret; +#if defined (CONFIG_SPL_NAND_IDENT) + ret = mxs_flash_full_ident(mtd); +#else + ret = mxs_flash_onfi_ident(mtd); +#endif + return ret; +} + static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) { register struct nand_chip *chip = mtd_to_nand(mtd); @@ -145,7 +181,7 @@ static int mxs_nand_init(void) return 0; /* init mxs nand driver */ - board_nand_init(&nand_chip); + mxs_nand_init_spl(&nand_chip); mtd = nand_to_mtd(&nand_chip); /* set mtd functions */ nand_chip.cmdfunc = mxs_nand_command; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index eb9f121f810..64e4621aaaf 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3755,7 +3755,7 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, /* * Get the flash and manufacturer id and lookup if the type is supported. */ -static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, +struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type) @@ -3927,6 +3927,7 @@ ident_done: mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); return type; } +EXPORT_SYMBOL(nand_get_flash_type); #if CONFIG_IS_ENABLED(OF_CONTROL) DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index 7893efee12a..f23c0e13e0c 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -567,16 +567,17 @@ int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs, strncpy(name, spec, sizeof(name) - 6); name[sizeof(name) - 6] = '\0'; strcat(name, "-emul"); - str = strdup(name); - if (!str) - return -ENOMEM; drv = lists_driver_lookup_name("sandbox_sf_emul"); if (!drv) { puts("Cannot find sandbox_sf_emul driver\n"); return -ENOENT; } + str = strdup(name); + if (!str) + return -ENOMEM; ret = device_bind(bus, drv, str, NULL, of_offset, &emul); if (ret) { + free(str); printf("Cannot create emul device for spec '%s' (err=%d)\n", spec, ret); return ret; diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index c45d2e80be0..9212373daec 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -110,7 +110,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, @@ -134,8 +134,8 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 45e5eda9552..ab697b9bc76 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -1702,11 +1702,13 @@ static int mvneta_probe(struct udevice *dev) /* Align buffer area for descs and rx_buffers to 1MiB */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE); mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc), ARCH_DMA_MINALIGN); + memset(buffer_loc.tx_descs, 0, size); buffer_loc.rx_descs = (struct mvneta_rx_desc *) ((phys_addr_t)bd_space + size); size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc), diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 999894f0f6d..749562db960 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -318,12 +318,13 @@ static int ravb_phy_config(struct udevice *dev) eth->phydev = phydev; - /* 10BASE is not supported for Ethernet AVB MAC */ - phydev->supported &= ~(SUPPORTED_10baseT_Full - | SUPPORTED_10baseT_Half); + phydev->supported &= SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | + SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + if (pdata->max_speed != 1000) { - phydev->supported &= ~(SUPPORTED_1000baseT_Half - | SUPPORTED_1000baseT_Full); + phydev->supported &= ~SUPPORTED_1000baseT_Full; reg = phy_read(phydev, -1, MII_CTRL1000); reg &= ~(BIT(9) | BIT(8)); phy_write(phydev, -1, MII_CTRL1000, reg); @@ -437,7 +438,7 @@ static int ravb_start(struct udevice *dev) ret = ravb_reset(dev); if (ret) - goto err; + return ret; ravb_base_desc_init(eth); ravb_tx_desc_init(eth); @@ -445,16 +446,12 @@ static int ravb_start(struct udevice *dev) ret = ravb_config(dev); if (ret) - goto err; + return ret; /* Setting the control will start the AVB-DMAC process. */ writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC); return 0; - -err: - clk_disable(ð->clk); - return ret; } static void ravb_stop(struct udevice *dev) @@ -469,6 +466,7 @@ static int ravb_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct ravb_priv *eth = dev_get_priv(dev); + struct ofnode_phandle_args phandle_args; struct mii_dev *mdiodev; void __iomem *iobase; int ret; @@ -480,8 +478,16 @@ static int ravb_probe(struct udevice *dev) if (ret < 0) goto err_mdio_alloc; - gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio, - GPIOD_IS_OUT); + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args); + if (!ret) { + gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0, + ð->reset_gpio, GPIOD_IS_OUT); + } + + if (!dm_gpio_is_valid(ð->reset_gpio)) { + gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio, + GPIOD_IS_OUT); + } mdiodev = mdio_alloc(); if (!mdiodev) { diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 645cde8e4ae..2e1123c488a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -810,6 +810,7 @@ static int sh_ether_probe(struct udevice *udev) struct eth_pdata *pdata = dev_get_platdata(udev); struct sh_ether_priv *priv = dev_get_priv(udev); struct sh_eth_dev *eth = &priv->shdev; + struct ofnode_phandle_args phandle_args; struct mii_dev *mdiodev; int ret; @@ -819,8 +820,16 @@ static int sh_ether_probe(struct udevice *udev) if (ret < 0) return ret; - gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio, - GPIOD_IS_OUT); + ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args); + if (!ret) { + gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + } + + if (!dm_gpio_is_valid(&priv->reset_gpio)) { + gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + } mdiodev = mdio_alloc(); if (!mdiodev) { diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a817f2e5d69..d1138fe0903 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -609,7 +609,7 @@ static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, { struct zynq_gem_priv *priv = bus->priv; int ret; - u16 val; + u16 val = 0; ret = phyread(priv, addr, reg, &val); debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 734df477d34..ad492b5366b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -1825,8 +1825,8 @@ static const unsigned int avb_mii_pins[] = { RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10), - RCAR_GP_PIN(3, 12), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12), }; static const unsigned int avb_mii_mux[] = { AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, @@ -1836,8 +1836,8 @@ static const unsigned int avb_mii_mux[] = { AVB_RXD3_MARK, AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, - AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK, - AVB_COL_MARK, + AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, + AVB_TX_CLK_MARK, AVB_COL_MARK, }; static const unsigned int avb_gmii_pins[] = { RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 43055896972..0b6a1b0c1dd 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -4146,6 +4146,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +/* - TPU -------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + RCAR_GP_PIN(6, 14), +}; +static const unsigned int tpu_to0_mux[] = { + TPU_TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + RCAR_GP_PIN(1, 17), +}; +static const unsigned int tpu_to1_mux[] = { + TPU_TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + RCAR_GP_PIN(1, 18), +}; +static const unsigned int tpu_to2_mux[] = { + TPU_TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + RCAR_GP_PIN(1, 24), +}; +static const unsigned int tpu_to3_mux[] = { + TPU_TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { RCAR_GP_PIN(7, 23), /* PWEN */ @@ -4432,7 +4458,7 @@ static const unsigned int vin2_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[342]; + struct sh_pfc_pin_group common[346]; struct sh_pfc_pin_group r8a779x[9]; } pinmux_groups = { .common = { @@ -4744,6 +4770,10 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), VIN_DATA_PIN_GROUP(vin0_data, 24), @@ -4827,6 +4857,10 @@ static const char * const can0_groups[] = { "can0_data_d", "can0_data_e", "can0_data_f", + /* + * Retained for backwards compatibility, use can_clk_groups in new + * designs. + */ "can_clk", "can_clk_b", "can_clk_c", @@ -4838,6 +4872,21 @@ static const char * const can1_groups[] = { "can1_data_b", "can1_data_c", "can1_data_d", + /* + * Retained for backwards compatibility, use can_clk_groups in new + * designs. + */ + "can_clk", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + +/* + * can_clk_groups allows for independent configuration, use can_clk function + * in new designs. + */ +static const char * const can_clk_groups[] = { "can_clk", "can_clk_b", "can_clk_c", @@ -5260,6 +5309,13 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -5309,7 +5365,7 @@ static const char * const vin2_groups[] = { }; static const struct { - struct sh_pfc_function common[56]; + struct sh_pfc_function common[58]; struct sh_pfc_function r8a779x[2]; } pinmux_functions = { .common = { @@ -5317,6 +5373,7 @@ static const struct { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), @@ -5364,6 +5421,7 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(vin0), @@ -6555,6 +6613,28 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { .pin_to_pocctrl = r8a7791_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7743 +const struct sh_pfc_soc_info r8a7743_pinmux_info = { + .name = "r8a77430_pfc", + .ops = &r8a7791_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index d06b8ddc336..7264c70e85f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -1608,6 +1608,116 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; + +/* - CAN -------------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), +}; + +static const unsigned int can0_data_mux[] = { + CAN0_TX_MARK, CAN0_RX_MARK, +}; + +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; + +static const unsigned int can0_data_c_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16), +}; + +static const unsigned int can0_data_c_mux[] = { + CAN0_TX_C_MARK, CAN0_RX_C_MARK, +}; + +static const unsigned int can0_data_d_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), +}; + +static const unsigned int can0_data_d_mux[] = { + CAN0_TX_D_MARK, CAN0_RX_D_MARK, +}; + +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24), +}; + +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +static const unsigned int can1_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), +}; + +static const unsigned int can1_data_b_mux[] = { + CAN1_TX_B_MARK, CAN1_RX_B_MARK, +}; + +static const unsigned int can1_data_c_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), +}; + +static const unsigned int can1_data_c_mux[] = { + CAN1_TX_C_MARK, CAN1_RX_C_MARK, +}; + +static const unsigned int can1_data_d_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30), +}; + +static const unsigned int can1_data_d_mux[] = { + CAN1_TX_D_MARK, CAN1_RX_D_MARK, +}; + +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(3, 31), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +static const unsigned int can_clk_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 23), +}; + +static const unsigned int can_clk_b_mux[] = { + CAN_CLK_B_MARK, +}; + +static const unsigned int can_clk_c_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int can_clk_c_mux[] = { + CAN_CLK_C_MARK, +}; + +static const unsigned int can_clk_d_pins[] = { + /* CLK */ + RCAR_GP_PIN(5, 0), +}; + +static const unsigned int can_clk_d_mux[] = { + CAN_CLK_D_MARK, +}; + /* - DU --------------------------------------------------------------------- */ static const unsigned int du0_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2118,6 +2228,35 @@ static const unsigned int i2c4_e_pins[] = { static const unsigned int i2c4_e_mux[] = { I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, }; +/* - I2C5 ------------------------------------------------------------------- */ +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int i2c5_mux[] = { + I2C5_SCL_MARK, I2C5_SDA_MARK, +}; +static const unsigned int i2c5_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int i2c5_b_mux[] = { + I2C5_SCL_B_MARK, I2C5_SDA_B_MARK, +}; +static const unsigned int i2c5_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int i2c5_c_mux[] = { + I2C5_SCL_C_MARK, I2C5_SDA_C_MARK, +}; +static const unsigned int i2c5_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int i2c5_d_mux[] = { + I2C5_SCL_D_MARK, I2C5_SDA_D_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ0 */ @@ -2436,6 +2575,109 @@ static const unsigned int msiof2_tx_b_pins[] = { static const unsigned int msiof2_tx_b_mux[] = { MSIOF2_TXD_B_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(1, 14), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(5, 3), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(4, 5), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + RCAR_GP_PIN(5, 10), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +static const unsigned int pwm1_c_pins[] = { + RCAR_GP_PIN(1, 18), +}; +static const unsigned int pwm1_c_mux[] = { + PWM1_C_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(4, 10), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + RCAR_GP_PIN(5, 17), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +static const unsigned int pwm2_c_pins[] = { + RCAR_GP_PIN(0, 13), +}; +static const unsigned int pwm2_c_mux[] = { + PWM2_C_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(4, 13), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm3_b_pins[] = { + RCAR_GP_PIN(0, 16), +}; +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(1, 3), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + RCAR_GP_PIN(0, 21), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(3, 30), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + RCAR_GP_PIN(4, 0), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +static const unsigned int pwm5_c_pins[] = { + RCAR_GP_PIN(0, 10), +}; +static const unsigned int pwm5_c_mux[] = { + PWM5_C_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(4, 8), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; +static const unsigned int pwm6_b_pins[] = { + RCAR_GP_PIN(0, 7), +}; +static const unsigned int pwm6_b_mux[] = { + PWM6_B_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3280,6 +3522,79 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +/* - TPU -------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + RCAR_GP_PIN(3, 31), +}; +static const unsigned int tpu_to0_mux[] = { + TPUTO0_MARK, +}; +static const unsigned int tpu_to0_b_pins[] = { + RCAR_GP_PIN(3, 30), +}; +static const unsigned int tpu_to0_b_mux[] = { + TPUTO0_B_MARK, +}; +static const unsigned int tpu_to0_c_pins[] = { + RCAR_GP_PIN(1, 18), +}; +static const unsigned int tpu_to0_c_mux[] = { + TPUTO0_C_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + RCAR_GP_PIN(4, 9), +}; +static const unsigned int tpu_to1_mux[] = { + TPUTO1_MARK, +}; +static const unsigned int tpu_to1_b_pins[] = { + RCAR_GP_PIN(4, 0), +}; +static const unsigned int tpu_to1_b_mux[] = { + TPUTO1_B_MARK, +}; +static const unsigned int tpu_to1_c_pins[] = { + RCAR_GP_PIN(4, 4), +}; +static const unsigned int tpu_to1_c_mux[] = { + TPUTO1_C_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + RCAR_GP_PIN(1, 3), +}; +static const unsigned int tpu_to2_mux[] = { + TPUTO2_MARK, +}; +static const unsigned int tpu_to2_b_pins[] = { + RCAR_GP_PIN(1, 0), +}; +static const unsigned int tpu_to2_b_mux[] = { + TPUTO2_B_MARK, +}; +static const unsigned int tpu_to2_c_pins[] = { + RCAR_GP_PIN(0, 22), +}; +static const unsigned int tpu_to2_c_mux[] = { + TPUTO2_C_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + RCAR_GP_PIN(1, 14), +}; +static const unsigned int tpu_to3_mux[] = { + TPUTO3_MARK, +}; +static const unsigned int tpu_to3_b_pins[] = { + RCAR_GP_PIN(1, 13), +}; +static const unsigned int tpu_to3_b_mux[] = { + TPUTO3_B_MARK, +}; +static const unsigned int tpu_to3_c_pins[] = { + RCAR_GP_PIN(0, 21), +}; +static const unsigned int tpu_to3_c_mux[] = { + TPUTO3_C_MARK, +}; /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { RCAR_GP_PIN(5, 24), /* PWEN */ @@ -3459,6 +3774,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can1_data_c), + SH_PFC_PIN_GROUP(can1_data_d), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), + SH_PFC_PIN_GROUP(can_clk_c), + SH_PFC_PIN_GROUP(can_clk_d), SH_PFC_PIN_GROUP(du0_rgb666), SH_PFC_PIN_GROUP(du0_rgb888), SH_PFC_PIN_GROUP(du0_clk0_out), @@ -3523,6 +3850,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4_c), SH_PFC_PIN_GROUP(i2c4_d), SH_PFC_PIN_GROUP(i2c4_e), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c5_b), + SH_PFC_PIN_GROUP(i2c5_c), + SH_PFC_PIN_GROUP(i2c5_d), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -3567,6 +3898,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_ss2_b), SH_PFC_PIN_GROUP(msiof2_rx_b), SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm1_c), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm2_c), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm5_c), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -3684,6 +4032,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to0_b), + SH_PFC_PIN_GROUP(tpu_to0_c), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to1_b), + SH_PFC_PIN_GROUP(tpu_to1_c), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to2_b), + SH_PFC_PIN_GROUP(tpu_to2_c), + SH_PFC_PIN_GROUP(tpu_to3), + SH_PFC_PIN_GROUP(tpu_to3_b), + SH_PFC_PIN_GROUP(tpu_to3_c), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), VIN_DATA_PIN_GROUP(vin0_data, 24), @@ -3731,6 +4091,47 @@ static const char * const avb_groups[] = { "avb_gmii", }; +static const char * const can0_groups[] = { + "can0_data", + "can0_data_b", + "can0_data_c", + "can0_data_d", + /* + * Retained for backwards compatibility, use can_clk_groups in new + * designs. + */ + "can_clk", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + +static const char * const can1_groups[] = { + "can1_data", + "can1_data_b", + "can1_data_c", + "can1_data_d", + /* + * Retained for backwards compatibility, use can_clk_groups in new + * designs. + */ + "can_clk", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + +/* + * can_clk_groups allows for independent configuration, use can_clk function + * in new designs. + */ +static const char * const can_clk_groups[] = { + "can_clk", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + static const char * const du0_groups[] = { "du0_rgb666", "du0_rgb888", @@ -3828,6 +4229,13 @@ static const char * const i2c4_groups[] = { "i2c4_e", }; +static const char * const i2c5_groups[] = { + "i2c5", + "i2c5_b", + "i2c5_c", + "i2c5_d", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -3887,6 +4295,44 @@ static const char * const msiof2_groups[] = { "msiof2_tx_b", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1", + "pwm1_b", + "pwm1_c", +}; + +static const char * const pwm2_groups[] = { + "pwm2", + "pwm2_b", + "pwm2_c", +}; + +static const char * const pwm3_groups[] = { + "pwm3", + "pwm3_b", +}; + +static const char * const pwm4_groups[] = { + "pwm4", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5", + "pwm5_b", + "pwm5_c", +}; + +static const char * const pwm6_groups[] = { + "pwm6", + "pwm6_b", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -4067,6 +4513,21 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to0_b", + "tpu_to0_c", + "tpu_to1", + "tpu_to1_b", + "tpu_to1_c", + "tpu_to2", + "tpu_to2_b", + "tpu_to2_c", + "tpu_to3", + "tpu_to3_b", + "tpu_to3_c", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4102,6 +4563,9 @@ static const char * const vin1_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(eth), @@ -4113,11 +4577,19 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -4139,6 +4611,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(vin0), diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 2e05e3492ca..a6ecc0cabe2 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -19,7 +19,7 @@ #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ @@ -54,6 +54,7 @@ #define GPSR0_0 F_(D0, IP5_15_12) /* GPSR1 */ +#define GPSR1_28 FM(CLKOUT) #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) #define GPSR1_26 F_(WE1_N, IP5_7_4) #define GPSR1_25 F_(WE0_N, IP5_3_0) @@ -156,11 +157,11 @@ #define GPSR5_11 F_(RX2_A, IP13_7_4) #define GPSR5_10 F_(TX2_A, IP13_3_0) #define GPSR5_9 F_(SCK2, IP12_31_28) -#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) +#define GPSR5_8 F_(RTS1_N, IP12_27_24) #define GPSR5_7 F_(CTS1_N, IP12_23_20) #define GPSR5_6 F_(TX1_A, IP12_19_16) #define GPSR5_5 F_(RX1_A, IP12_15_12) -#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) +#define GPSR5_4 F_(RTS0_N, IP12_11_8) #define GPSR5_3 F_(CTS0_N, IP12_7_4) #define GPSR5_2 F_(TX0, IP12_3_0) #define GPSR5_1 F_(RX0, IP11_31_28) @@ -213,16 +214,16 @@ #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -235,7 +236,7 @@ #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -251,7 +252,7 @@ #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -264,7 +265,7 @@ #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -311,11 +312,11 @@ #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -367,7 +368,7 @@ GPSR6_31 \ GPSR6_30 \ GPSR6_29 \ - GPSR6_28 \ + GPSR1_28 GPSR6_28 \ GPSR1_27 GPSR6_27 \ GPSR1_26 GPSR6_26 \ GPSR1_25 GPSR5_25 GPSR6_25 \ @@ -470,7 +471,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) +#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) @@ -547,7 +548,7 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ - FM(CLKOUT) FM(PRESETOUT) \ + FM(PRESETOUT) \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) @@ -586,6 +587,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS1), PINMUX_SINGLE(AVS2), + PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(HDMI0_CEC), PINMUX_SINGLE(HDMI1_CEC), PINMUX_SINGLE(I2C_SEL_0_1), @@ -621,7 +623,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -649,7 +651,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), - PINMUX_IPSR_GPSR(IP1_7_4, A25), PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), @@ -657,7 +658,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), - PINMUX_IPSR_GPSR(IP1_11_8, A24), PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), @@ -665,7 +665,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), - PINMUX_IPSR_GPSR(IP1_15_12, A23), PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), @@ -674,18 +673,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_19_16, PWM0), PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), - PINMUX_IPSR_GPSR(IP1_19_16, A22), PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_GPSR(IP1_23_20, A21), PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_GPSR(IP1_27_24, A20), PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), @@ -765,7 +761,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_7_4, A10), PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), PINMUX_IPSR_GPSR(IP3_11_8, A11), @@ -868,7 +864,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), - PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), @@ -949,7 +945,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), - PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), PINMUX_IPSR_GPSR(IP6_31_28, D12), @@ -1158,7 +1154,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), - PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), @@ -1187,7 +1183,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), - PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), @@ -1221,7 +1217,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), - PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), @@ -1229,14 +1225,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_15_12, HRX0), PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), PINMUX_IPSR_GPSR(IP13_19_16, HTX0), PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), @@ -1244,7 +1240,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), @@ -1253,7 +1249,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), @@ -1268,7 +1264,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), @@ -1277,7 +1273,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), - PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), @@ -1305,10 +1301,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), /* IPSR15 */ - PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), - PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), @@ -1397,11 +1393,11 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), - PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP16_31_28, SCK1), PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), @@ -1433,7 +1429,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), - PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), @@ -1443,7 +1439,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), @@ -1453,7 +1449,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), - PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), @@ -1465,7 +1461,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), - PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), @@ -1476,7 +1472,7 @@ static const u16 pinmux_data[] = { /* IPSR18 */ PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), - PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), @@ -1486,7 +1482,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), - PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), @@ -1507,12 +1503,13 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. + * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. * Physical layout rows: A - AW, cols: 1 - 39. */ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), @@ -1540,7 +1537,6 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), @@ -1571,6 +1567,127 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int audio_clk_a_a_mux[] = { + AUDIO_CLKA_A_MARK, +}; +static const unsigned int audio_clk_a_b_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int audio_clk_a_b_mux[] = { + AUDIO_CLKA_B_MARK, +}; +static const unsigned int audio_clk_a_c_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clk_a_c_mux[] = { + AUDIO_CLKA_C_MARK, +}; +static const unsigned int audio_clk_b_a_pins[] = { + /* CLK B */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int audio_clk_b_a_mux[] = { + AUDIO_CLKB_A_MARK, +}; +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; +static const unsigned int audio_clk_c_a_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clk_c_a_mux[] = { + AUDIO_CLKC_A_MARK, +}; +static const unsigned int audio_clk_c_b_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int audio_clk_c_b_mux[] = { + AUDIO_CLKC_B_MARK, +}; +static const unsigned int audio_clkout_a_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int audio_clkout_a_mux[] = { + AUDIO_CLKOUT_A_MARK, +}; +static const unsigned int audio_clkout_b_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; +static const unsigned int audio_clkout_c_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int audio_clkout_c_mux[] = { + AUDIO_CLKOUT_C_MARK, +}; +static const unsigned int audio_clkout_d_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clkout_d_mux[] = { + AUDIO_CLKOUT_D_MARK, +}; +static const unsigned int audio_clkout1_a_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int audio_clkout1_a_mux[] = { + AUDIO_CLKOUT1_A_MARK, +}; +static const unsigned int audio_clkout1_b_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int audio_clkout1_b_mux[] = { + AUDIO_CLKOUT1_B_MARK, +}; +static const unsigned int audio_clkout2_a_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int audio_clkout2_a_mux[] = { + AUDIO_CLKOUT2_A_MARK, +}; +static const unsigned int audio_clkout2_b_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int audio_clkout2_b_mux[] = { + AUDIO_CLKOUT2_B_MARK, +}; +static const unsigned int audio_clkout3_a_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clkout3_a_mux[] = { + AUDIO_CLKOUT3_A_MARK, +}; +static const unsigned int audio_clkout3_b_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int audio_clkout3_b_mux[] = { + AUDIO_CLKOUT3_B_MARK, +}; + /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { /* AVB_LINK */ @@ -1593,11 +1710,11 @@ static const unsigned int avb_phy_int_pins[] = { static const unsigned int avb_phy_int_mux[] = { AVB_PHY_INT_MARK, }; -static const unsigned int avb_mdc_pins[] = { +static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), }; -static const unsigned int avb_mdc_mux[] = { +static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, }; static const unsigned int avb_mii_pins[] = { @@ -1658,6 +1775,61 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int can0_data_a_mux[] = { + CAN0_TX_A_MARK, CAN0_RX_A_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD --------------------------------------------------------------- */ +static const unsigned int canfd0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int canfd0_data_a_mux[] = { + CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, +}; +static const unsigned int canfd0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int canfd0_data_b_mux[] = { + CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, +}; +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -1954,6 +2126,324 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi0_cec_pins[] = { + /* HDMI0_CEC */ + RCAR_GP_PIN(7, 2), +}; +static const unsigned int hdmi0_cec_mux[] = { + HDMI0_CEC_MARK, +}; +static const unsigned int hdmi1_cec_pins[] = { + /* HDMI1_CEC */ + RCAR_GP_PIN(7, 3), +}; +static const unsigned int hdmi1_cec_mux[] = { + HDMI1_CEC_MARK, +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; +static const unsigned int hscif1_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif1_ctrl_a_mux[] = { + HRTS1_N_A_MARK, HCTS1_N_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; +static const unsigned int hscif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif2_clk_b_mux[] = { + HSCK2_B_MARK, +}; +static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), +}; +static const unsigned int hscif2_ctrl_b_mux[] = { + HRTS2_N_B_MARK, HCTS2_N_B_MARK, +}; + +static const unsigned int hscif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), +}; +static const unsigned int hscif2_data_c_mux[] = { + HRX2_C_MARK, HTX2_C_MARK, +}; +static const unsigned int hscif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 24), +}; +static const unsigned int hscif2_clk_c_mux[] = { + HSCK2_C_MARK, +}; +static const unsigned int hscif2_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), +}; +static const unsigned int hscif2_ctrl_c_mux[] = { + HRTS2_N_C_MARK, HCTS2_N_C_MARK, +}; +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; +/* - HSCIF4 ----------------------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; +static const unsigned int hscif4_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_clk_mux[] = { + HSCK4_MARK, +}; +static const unsigned int hscif4_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int hscif4_ctrl_mux[] = { + HRTS4_N_MARK, HCTS4_N_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + +/* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c1_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int i2c1_a_mux[] = { + SDA1_A_MARK, SCL1_A_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), +}; +static const unsigned int i2c1_b_mux[] = { + SDA1_B_MARK, SCL1_B_MARK, +}; +static const unsigned int i2c2_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), +}; +static const unsigned int i2c2_a_mux[] = { + SDA2_A_MARK, SCL2_A_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c2_b_mux[] = { + SDA2_B_MARK, SCL2_B_MARK, +}; +static const unsigned int i2c6_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c6_a_mux[] = { + SDA6_A_MARK, SCL6_A_MARK, +}; +static const unsigned int i2c6_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int i2c6_b_mux[] = { + SDA6_B_MARK, SCL6_B_MARK, +}; +static const unsigned int i2c6_c_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), +}; +static const unsigned int i2c6_c_mux[] = { + SDA6_C_MARK, SCL6_C_MARK, +}; + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2751,6 +3241,22 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - SATA --------------------------------------------------------------------*/ +static const unsigned int sata0_devslp_a_pins[] = { + /* DEVSLP */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int sata0_devslp_a_mux[] = { + SATA_DEVSLP_A_MARK, +}; +static const unsigned int sata0_devslp_b_pins[] = { + /* DEVSLP */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int sata0_devslp_b_mux[] = { + SATA_DEVSLP_B_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -2771,7 +3277,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -2793,7 +3299,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { @@ -2845,7 +3351,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; static const unsigned int scif3_data_b_pins[] = { /* RX, TX */ @@ -2874,7 +3380,7 @@ static const unsigned int scif4_ctrl_a_pins[] = { RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), }; static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, + RTS4_N_A_MARK, CTS4_N_A_MARK, }; static const unsigned int scif4_data_b_pins[] = { /* RX, TX */ @@ -2895,7 +3401,7 @@ static const unsigned int scif4_ctrl_b_pins[] = { RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), }; static const unsigned int scif4_ctrl_b_mux[] = { - RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, + RTS4_N_B_MARK, CTS4_N_B_MARK, }; static const unsigned int scif4_data_c_pins[] = { /* RX, TX */ @@ -2916,7 +3422,7 @@ static const unsigned int scif4_ctrl_c_pins[] = { RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), }; static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, + RTS4_N_C_MARK, CTS4_N_C_MARK, }; /* - SCIF5 ------------------------------------------------------------------ */ static const unsigned int scif5_data_a_pins[] = { @@ -2948,6 +3454,22 @@ static const unsigned int scif5_clk_b_mux[] = { SCK5_B_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -3155,20 +3677,211 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; -/* - SCIF Clock ------------------------------------------------------------- */ -static const unsigned int scif_clk_a_pins[] = { - /* SCIF_CLK */ +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; +static const unsigned int ssi01239_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int ssi01239_ctrl_mux[] = { + SSI_SCK01239_MARK, SSI_WS01239_MARK, +}; +static const unsigned int ssi1_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 3), +}; +static const unsigned int ssi1_data_a_mux[] = { + SSI_SDATA1_A_MARK, +}; +static const unsigned int ssi1_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int ssi1_data_b_mux[] = { + SSI_SDATA1_B_MARK, +}; +static const unsigned int ssi1_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int ssi1_ctrl_a_mux[] = { + SSI_SCK1_A_MARK, SSI_WS1_A_MARK, +}; +static const unsigned int ssi1_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi1_ctrl_b_mux[] = { + SSI_SCK1_B_MARK, SSI_WS1_B_MARK, +}; +static const unsigned int ssi2_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 4), +}; +static const unsigned int ssi2_data_a_mux[] = { + SSI_SDATA2_A_MARK, +}; +static const unsigned int ssi2_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int ssi2_data_b_mux[] = { + SSI_SDATA2_B_MARK, +}; +static const unsigned int ssi2_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +}; +static const unsigned int ssi2_ctrl_a_mux[] = { + SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +}; +static const unsigned int ssi2_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int ssi2_ctrl_b_mux[] = { + SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +}; +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; +static const unsigned int ssi349_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +}; +static const unsigned int ssi349_ctrl_mux[] = { + SSI_SCK349_MARK, SSI_WS349_MARK, +}; +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 13), +}; +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; +static const unsigned int ssi9_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi9_data_a_mux[] = { + SSI_SDATA9_A_MARK, +}; +static const unsigned int ssi9_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int ssi9_data_b_mux[] = { + SSI_SDATA9_B_MARK, +}; +static const unsigned int ssi9_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int ssi9_ctrl_a_mux[] = { + SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +}; +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +}; +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + +/* - TMU -------------------------------------------------------------------- */ +static const unsigned int tmu_tclk1_a_pins[] = { + /* TCLK */ RCAR_GP_PIN(6, 23), }; -static const unsigned int scif_clk_a_mux[] = { - SCIF_CLK_A_MARK, +static const unsigned int tmu_tclk1_a_mux[] = { + TCLK1_A_MARK, }; -static const unsigned int scif_clk_b_pins[] = { - /* SCIF_CLK */ - RCAR_GP_PIN(5, 9), +static const unsigned int tmu_tclk1_b_pins[] = { + /* TCLK */ + RCAR_GP_PIN(5, 19), }; -static const unsigned int scif_clk_b_mux[] = { - SCIF_CLK_B_MARK, +static const unsigned int tmu_tclk1_b_mux[] = { + TCLK1_B_MARK, +}; +static const unsigned int tmu_tclk2_a_pins[] = { + /* TCLK */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int tmu_tclk2_a_mux[] = { + TCLK2_A_MARK, +}; +static const unsigned int tmu_tclk2_b_pins[] = { + /* TCLK */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tmu_tclk2_b_mux[] = { + TCLK2_B_MARK, }; /* - USB0 ------------------------------------------------------------------- */ @@ -3204,17 +3917,281 @@ static const unsigned int usb2_ch3_mux[] = { USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, }; +/* - USB30 ------------------------------------------------------------------ */ +static const unsigned int usb30_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int usb30_mux[] = { + USB30_PWEN_MARK, USB30_OVC_MARK, +}; + +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data18_a_pins[] = { + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data18_a_mux[] = { + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data18_b_pins[] = { + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data18_b_mux[] = { + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const union vin_data vin4_data_a_pins = { + .data24 = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + }, +}; +static const union vin_data vin4_data_a_mux = { + .data24 = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; +static const union vin_data vin4_data_b_pins = { + .data24 = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + }, +}; +static const union vin_data vin4_data_b_mux = { + .data24 = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; +static const unsigned int vin4_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), +}; +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; +static const unsigned int vin4_field_pins[] = { + /* FIELD */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; +static const unsigned int vin4_clkenb_pins[] = { + /* CLKENB */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; +static const unsigned int vin4_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + +/* - VIN5 ------------------------------------------------------------------- */ +static const unsigned int vin5_data8_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin5_data8_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, +}; +static const unsigned int vin5_data10_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +}; +static const unsigned int vin5_data10_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, +}; +static const unsigned int vin5_data12_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), +}; +static const unsigned int vin5_data12_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, +}; +static const unsigned int vin5_data16_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin5_data16_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, +}; +static const unsigned int vin5_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), +}; +static const unsigned int vin5_sync_mux[] = { + VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, +}; +static const unsigned int vin5_field_pins[] = { + RCAR_GP_PIN(1, 11), +}; +static const unsigned int vin5_field_mux[] = { + /* FIELD */ + VI5_FIELD_MARK, +}; +static const unsigned int vin5_clkenb_pins[] = { + RCAR_GP_PIN(1, 20), +}; +static const unsigned int vin5_clkenb_mux[] = { + /* CLKENB */ + VI5_CLKENB_MARK, +}; +static const unsigned int vin5_clk_pins[] = { + RCAR_GP_PIN(1, 21), +}; +static const unsigned int vin5_clk_mux[] = { + /* CLK */ + VI5_CLK_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdc), + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match_a), SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -3253,6 +4230,49 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hdmi0_cec), + SH_PFC_PIN_GROUP(hdmi1_cec), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -3365,6 +4385,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3420,17 +4442,94 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), + SH_PFC_PIN_GROUP(usb30), + VIN_DATA_PIN_GROUP(vin4_data_a, 8), + VIN_DATA_PIN_GROUP(vin4_data_a, 10), + VIN_DATA_PIN_GROUP(vin4_data_a, 12), + VIN_DATA_PIN_GROUP(vin4_data_a, 16), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data_a, 20), + VIN_DATA_PIN_GROUP(vin4_data_a, 24), + VIN_DATA_PIN_GROUP(vin4_data_b, 8), + VIN_DATA_PIN_GROUP(vin4_data_b, 10), + VIN_DATA_PIN_GROUP(vin4_data_b, 12), + VIN_DATA_PIN_GROUP(vin4_data_b, 16), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data_b, 20), + VIN_DATA_PIN_GROUP(vin4_data_b, 24), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + SH_PFC_PIN_GROUP(vin5_data8), + SH_PFC_PIN_GROUP(vin5_data10), + SH_PFC_PIN_GROUP(vin5_data12), + SH_PFC_PIN_GROUP(vin5_data16), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a_a", + "audio_clk_a_b", + "audio_clk_a_c", + "audio_clk_b_a", + "audio_clk_b_b", + "audio_clk_c_a", + "audio_clk_c_b", + "audio_clkout_a", + "audio_clkout_b", + "audio_clkout_c", + "audio_clkout_d", + "audio_clkout1_a", + "audio_clkout1_b", + "audio_clkout2_a", + "audio_clkout2_b", + "audio_clkout3_a", + "audio_clkout3_b", }; static const char * const avb_groups[] = { "avb_link", "avb_magic", "avb_phy_int", - "avb_mdc", + "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ + "avb_mdio", "avb_mii", "avb_avtp_pps", "avb_avtp_match_a", @@ -3439,6 +4538,28 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", +}; + +static const char * const can1_groups[] = { + "can1_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data_a", + "canfd0_data_b", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -3492,6 +4613,82 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const hdmi0_groups[] = { + "hdmi0_cec", +}; + +static const char * const hdmi1_groups[] = { + "hdmi1_cec", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_ctrl_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", + "hscif2_clk_b", + "hscif2_ctrl_b", + "hscif2_data_c", + "hscif2_clk_c", + "hscif2_ctrl_c", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_clk", + "hscif3_ctrl", + "hscif3_data_b", + "hscif3_data_c", + "hscif3_data_d", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk", + "hscif4_ctrl", + "hscif4_data_b", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", +}; + +static const char * const i2c6_groups[] = { + "i2c6_a", + "i2c6_b", + "i2c6_c", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3637,6 +4834,11 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const sata0_groups[] = { + "sata0_devslp_a", + "sata0_devslp_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -3725,6 +4927,41 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi01239_ctrl", + "ssi1_data_a", + "ssi1_data_b", + "ssi1_ctrl_a", + "ssi1_ctrl_b", + "ssi2_data_a", + "ssi2_data_b", + "ssi2_ctrl_a", + "ssi2_ctrl_b", + "ssi3_data", + "ssi349_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi78_ctrl", + "ssi8_data", + "ssi9_data_a", + "ssi9_data_b", + "ssi9_ctrl_a", + "ssi9_ctrl_b", +}; + +static const char * const tmu_groups[] = { + "tmu_tclk1_a", + "tmu_tclk1_b", + "tmu_tclk2_a", + "tmu_tclk2_b", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -3741,13 +4978,66 @@ static const char * const usb2_ch3_groups[] = { "usb2_ch3", }; +static const char * const usb30_groups[] = { + "usb30", +}; + +static const char * const vin4_groups[] = { + "vin4_data8_a", + "vin4_data10_a", + "vin4_data12_a", + "vin4_data16_a", + "vin4_data18_a", + "vin4_data20_a", + "vin4_data24_a", + "vin4_data8_b", + "vin4_data10_b", + "vin4_data12_b", + "vin4_data16_b", + "vin4_data18_b", + "vin4_data20_b", + "vin4_data24_b", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data8", + "vin5_data10", + "vin5_data12", + "vin5_data16", + "vin5_sync", + "vin5_field", + "vin5_clkenb", + "vin5_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hdmi0), + SH_PFC_FUNCTION(hdmi1), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -3759,6 +5049,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -3770,10 +5061,15 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), SH_PFC_FUNCTION(usb2_ch3), + SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -3817,7 +5113,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - 0, 0, + GP_1_28_FN, GPSR1_28, GP_1_27_FN, GPSR1_27, GP_1_26_FN, GPSR1_26, GP_1_25_FN, GPSR1_25, @@ -4419,7 +5715,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ } }, { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { - { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ + { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ @@ -4515,11 +5811,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ + { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ + { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ @@ -4586,11 +5882,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { }, }; +enum ioctrl_regs { + POCCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL] = { 0xe6060380, }, + { /* sentinel */ }, +}; + static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; - *pocctrl = 0xe6060380; + *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -4601,242 +5906,261 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return bit; } -#define PUEN 0xe6060400 -#define PUD 0xe6060440 - -#define PU0 0x00 -#define PU1 0x04 -#define PU2 0x08 -#define PU3 0x0c -#define PU4 0x10 -#define PU5 0x14 -#define PU6 0x18 - -static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ - { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ - { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ - { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ - { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ - { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ - { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ - { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ - { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ - { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ - { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ - { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ - { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ - { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ - { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ - { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ - { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ - { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ - - { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ - { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ - { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ - { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ - { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ - { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ - { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ - { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ - { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ - { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ - { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ - { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ - { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ - { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ - { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ - { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ - { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ - { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ - { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ - { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ - { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ - { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ - { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ - { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ - { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ - { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ - { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ - - { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ - { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ - { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ - { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ - { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ - { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ - { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ - { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ - { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ - { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ - { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ - { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ - { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ - { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ - { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ - { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ - { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ - { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ - { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ - { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ - { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ - { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ - { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ - { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ - { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ - { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ - { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ - { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ - { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ - { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ - - { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ - { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ - { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ - { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ - { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ - /* bit 8 n/a */ - { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ - { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ - { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ - { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ - { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ - { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ - - { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ - { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ - { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ - { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ - { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ - { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ - { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ - { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ - { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ - { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ - { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ - { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ - { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ - { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ - { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ - { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ - { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ - { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ - { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ - { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ - { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ - - { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ - { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ - { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ - { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ - { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ - { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ - { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ - { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ - { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ - { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ - { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */ - { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ + [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ + [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ + [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ + [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ + [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ + [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ + [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ + [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ + [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ + [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ + [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ + [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ + [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ + [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ + [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ + [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ + [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ + [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ + [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ + [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ + [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ + [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ + [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ + [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ + [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ + [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ + [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ + [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ + [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ + [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ + [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ + [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ + [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ + [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ + [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ + [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ + [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 8] = PIN_NONE, + [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { + [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { + [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ + [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ + [ 7] = PIN_NONE, + [ 8] = PIN_NONE, + [ 9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, }; static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - const struct sh_pfc_bias_info *info; - u32 reg; - u32 bit; + const struct pinmux_bias_reg *reg; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return PIN_CONFIG_BIAS_DISABLE; - reg = info->reg; - bit = BIT(info->bit); - - if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -4845,28 +6169,24 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; u32 enable, updown; - u32 reg; - u32 bit; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return; - reg = info->reg; - bit = BIT(info->bit); - - enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= bit; + enable |= BIT(bit); - updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= bit; + updown |= BIT(bit); - sh_pfc_write_reg(pfc, PUD + reg, 32, updown); - sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); } static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { @@ -4891,6 +6211,8 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = { .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 50b93317c47..f73f67dad68 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -163,11 +163,11 @@ #define GPSR5_11 F_(RX2_A, IP13_7_4) #define GPSR5_10 F_(TX2_A, IP13_3_0) #define GPSR5_9 F_(SCK2, IP12_31_28) -#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) +#define GPSR5_8 F_(RTS1_N, IP12_27_24) #define GPSR5_7 F_(CTS1_N, IP12_23_20) #define GPSR5_6 F_(TX1_A, IP12_19_16) #define GPSR5_5 F_(RX1_A, IP12_15_12) -#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) +#define GPSR5_4 F_(RTS0_N, IP12_11_8) #define GPSR5_3 F_(CTS0_N, IP12_7_4) #define GPSR5_2 F_(TX0, IP12_3_0) #define GPSR5_1 F_(RX0, IP11_31_28) @@ -220,16 +220,16 @@ #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -240,7 +240,7 @@ #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ @@ -258,7 +258,7 @@ #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -271,7 +271,7 @@ #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ @@ -318,11 +318,11 @@ #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -477,7 +477,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) +#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) @@ -495,14 +495,14 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) -/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) +#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) @@ -626,7 +626,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -654,7 +654,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), - PINMUX_IPSR_GPSR(IP1_7_4, A25), PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), @@ -662,7 +661,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), - PINMUX_IPSR_GPSR(IP1_11_8, A24), PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), @@ -670,7 +668,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), - PINMUX_IPSR_GPSR(IP1_15_12, A23), PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), @@ -678,18 +675,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1_19_16, PWM0), PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), - PINMUX_IPSR_GPSR(IP1_19_16, A22), PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_GPSR(IP1_23_20, A21), PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_GPSR(IP1_27_24, A20), PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), @@ -769,7 +763,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_7_4, A10), PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), PINMUX_IPSR_GPSR(IP3_11_8, A11), @@ -872,7 +866,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), - PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), @@ -953,7 +947,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), - PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), PINMUX_IPSR_GPSR(IP6_31_28, D12), @@ -1022,35 +1016,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1116,16 +1110,20 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), + PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), + PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), @@ -1161,7 +1159,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), - PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), @@ -1190,7 +1188,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), - PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), @@ -1224,7 +1222,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), - PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), @@ -1232,14 +1230,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_15_12, HRX0), PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), PINMUX_IPSR_GPSR(IP13_19_16, HTX0), PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), @@ -1247,7 +1245,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), @@ -1256,7 +1254,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), @@ -1269,9 +1267,9 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), @@ -1280,7 +1278,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), - PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), @@ -1308,10 +1306,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), /* IPSR15 */ - PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), - PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), @@ -1397,11 +1395,11 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), - PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP16_31_28, SCK1), PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), @@ -1433,7 +1431,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), - PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), @@ -1443,7 +1441,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), @@ -1453,7 +1451,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), - PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), @@ -1465,7 +1463,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), - PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), @@ -1476,7 +1474,7 @@ static const u16 pinmux_data[] = { /* IPSR18 */ PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), - PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), @@ -1486,7 +1484,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), - PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), @@ -1518,6 +1516,7 @@ static const u16 pinmux_data[] = { #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), @@ -1718,11 +1717,11 @@ static const unsigned int avb_phy_int_pins[] = { static const unsigned int avb_phy_int_mux[] = { AVB_PHY_INT_MARK, }; -static const unsigned int avb_mdc_pins[] = { +static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), }; -static const unsigned int avb_mdc_mux[] = { +static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, }; static const unsigned int avb_mii_pins[] = { @@ -2134,6 +2133,15 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi0_cec_pins[] = { + /* HDMI0_CEC */ + RCAR_GP_PIN(7, 2), +}; +static const unsigned int hdmi0_cec_mux[] = { + HDMI0_CEC_MARK, +}; + /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -2392,6 +2400,50 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3210,7 +3262,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -3232,7 +3284,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { @@ -3284,7 +3336,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; static const unsigned int scif3_data_b_pins[] = { /* RX, TX */ @@ -3313,7 +3365,7 @@ static const unsigned int scif4_ctrl_a_pins[] = { RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), }; static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, + RTS4_N_A_MARK, CTS4_N_A_MARK, }; static const unsigned int scif4_data_b_pins[] = { /* RX, TX */ @@ -3334,7 +3386,7 @@ static const unsigned int scif4_ctrl_b_pins[] = { RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), }; static const unsigned int scif4_ctrl_b_mux[] = { - RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, + RTS4_N_B_MARK, CTS4_N_B_MARK, }; static const unsigned int scif4_data_c_pins[] = { /* RX, TX */ @@ -3355,7 +3407,7 @@ static const unsigned int scif4_ctrl_c_pins[] = { RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), }; static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, + RTS4_N_C_MARK, CTS4_N_C_MARK, }; /* - SCIF5 ------------------------------------------------------------------ */ static const unsigned int scif5_data_a_pins[] = { @@ -3788,6 +3840,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +/* - TMU -------------------------------------------------------------------- */ +static const unsigned int tmu_tclk1_a_pins[] = { + /* TCLK */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int tmu_tclk1_a_mux[] = { + TCLK1_A_MARK, +}; +static const unsigned int tmu_tclk1_b_pins[] = { + /* TCLK */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int tmu_tclk1_b_mux[] = { + TCLK1_B_MARK, +}; +static const unsigned int tmu_tclk2_a_pins[] = { + /* TCLK */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int tmu_tclk2_a_mux[] = { + TCLK2_A_MARK, +}; +static const unsigned int tmu_tclk2_b_pins[] = { + /* TCLK */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tmu_tclk2_b_mux[] = { + TCLK2_B_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -3814,6 +3896,236 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data18_a_pins[] = { + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data18_a_mux[] = { + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data18_b_pins[] = { + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data18_b_mux[] = { + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const union vin_data vin4_data_a_pins = { + .data24 = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + }, +}; +static const union vin_data vin4_data_a_mux = { + .data24 = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; +static const union vin_data vin4_data_b_pins = { + .data24 = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + }, +}; +static const union vin_data vin4_data_b_mux = { + .data24 = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; +static const unsigned int vin4_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), +}; +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; +static const unsigned int vin4_field_pins[] = { + /* FIELD */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; +static const unsigned int vin4_clkenb_pins[] = { + /* CLKENB */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; +static const unsigned int vin4_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + +/* - VIN5 ------------------------------------------------------------------- */ +static const unsigned int vin5_data8_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin5_data8_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, +}; +static const unsigned int vin5_data10_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +}; +static const unsigned int vin5_data10_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, +}; +static const unsigned int vin5_data12_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), +}; +static const unsigned int vin5_data12_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, +}; +static const unsigned int vin5_data16_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin5_data16_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, +}; +static const unsigned int vin5_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), +}; +static const unsigned int vin5_sync_mux[] = { + VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, +}; +static const unsigned int vin5_field_pins[] = { + RCAR_GP_PIN(1, 11), +}; +static const unsigned int vin5_field_mux[] = { + /* FIELD */ + VI5_FIELD_MARK, +}; +static const unsigned int vin5_clkenb_pins[] = { + RCAR_GP_PIN(1, 20), +}; +static const unsigned int vin5_clkenb_mux[] = { + /* CLKENB */ + VI5_CLKENB_MARK, +}; +static const unsigned int vin5_clk_pins[] = { + RCAR_GP_PIN(1, 21), +}; +static const unsigned int vin5_clk_mux[] = { + /* CLK */ + VI5_CLK_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -3835,7 +4147,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdc), + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match_a), @@ -3887,6 +4200,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hdmi0_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -3922,6 +4236,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4114,9 +4434,39 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), + VIN_DATA_PIN_GROUP(vin4_data_a, 8), + VIN_DATA_PIN_GROUP(vin4_data_a, 10), + VIN_DATA_PIN_GROUP(vin4_data_a, 12), + VIN_DATA_PIN_GROUP(vin4_data_a, 16), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data_a, 20), + VIN_DATA_PIN_GROUP(vin4_data_a, 24), + VIN_DATA_PIN_GROUP(vin4_data_b, 8), + VIN_DATA_PIN_GROUP(vin4_data_b, 10), + VIN_DATA_PIN_GROUP(vin4_data_b, 12), + VIN_DATA_PIN_GROUP(vin4_data_b, 16), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data_b, 20), + VIN_DATA_PIN_GROUP(vin4_data_b, 24), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + SH_PFC_PIN_GROUP(vin5_data8), + SH_PFC_PIN_GROUP(vin5_data10), + SH_PFC_PIN_GROUP(vin5_data12), + SH_PFC_PIN_GROUP(vin5_data16), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), }; static const char * const audio_clk_groups[] = { @@ -4143,7 +4493,8 @@ static const char * const avb_groups[] = { "avb_link", "avb_magic", "avb_phy_int", - "avb_mdc", + "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ + "avb_mdio", "avb_mii", "avb_avtp_pps", "avb_avtp_match_a", @@ -4227,6 +4578,10 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const hdmi0_groups[] = { + "hdmi0_cec", +}; + static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -4286,6 +4641,15 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4547,6 +4911,13 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_b", }; +static const char * const tmu_groups[] = { + "tmu_tclk1_a", + "tmu_tclk1_b", + "tmu_tclk2_a", + "tmu_tclk2_b", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4559,6 +4930,38 @@ static const char * const usb30_groups[] = { "usb30", }; +static const char * const vin4_groups[] = { + "vin4_data8_a", + "vin4_data10_a", + "vin4_data12_a", + "vin4_data16_a", + "vin4_data18_a", + "vin4_data20_a", + "vin4_data24_a", + "vin4_data8_b", + "vin4_data10_b", + "vin4_data12_b", + "vin4_data16_b", + "vin4_data18_b", + "vin4_data20_b", + "vin4_data24_b", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data8", + "vin5_data10", + "vin5_data12", + "vin5_data16", + "vin5_sync", + "vin5_field", + "vin5_clkenb", + "vin5_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), @@ -4572,6 +4975,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hdmi0), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -4580,6 +4984,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -4603,9 +5008,12 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5345,11 +5753,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ + { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ + { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ @@ -5416,11 +5824,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { }, }; +enum ioctrl_regs { + POCCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL] = { 0xe6060380, }, + { /* sentinel */ }, +}; + static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; - *pocctrl = 0xe6060380; + *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -5431,242 +5848,261 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return bit; } -#define PUEN 0xe6060400 -#define PUD 0xe6060440 - -#define PU0 0x00 -#define PU1 0x04 -#define PU2 0x08 -#define PU3 0x0c -#define PU4 0x10 -#define PU5 0x14 -#define PU6 0x18 - -static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ - { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ - { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ - { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ - { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ - { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ - { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ - { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ - { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ - { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ - { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ - { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ - { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ - { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ - { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ - { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ - { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ - { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ - - { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ - { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ - { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ - { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ - { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ - { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ - { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ - { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ - { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ - { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ - { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ - { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ - { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ - { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ - { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ - { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ - { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ - { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ - { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ - { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ - { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ - { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ - { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ - { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ - { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ - { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ - { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ - - { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ - { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ - { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */ - { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ - { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ - { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ - { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ - { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ - { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ - { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ - { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ - { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ - { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ - { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ - { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ - { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ - { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ - { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ - { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ - { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ - { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ - { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ - { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ - { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ - { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ - { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ - { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ - { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ - { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ - { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ - - { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ - { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ - { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ - { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ - { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ - /* bit 8 n/a */ - { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ - { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ - { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ - { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ - { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ - { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */ - /* bit 1 n/a on M3*/ - { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */ - - { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ - { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ - { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ - { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ - { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ - { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ - { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ - { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ - { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ - { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ - { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ - { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ - { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ - { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ - { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ - { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ - { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ - { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ - { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ - { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ - { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ - - { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ - { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ - { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ - { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ - { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ - { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ - { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ - { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ - { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ - { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ - { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */ - { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ + [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ + [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ + [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ + [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ + [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ + [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ + [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ + [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ + [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ + [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ + [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ + [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ + [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ + [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ + [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ + [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ + [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ + [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ + [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ + [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ + [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ + [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ + [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ + [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ + [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ + [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ + [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ + [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ + [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ + [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */ + [ 1] = PIN_NONE, + [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ + [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ + [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ + [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ + [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ + [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 8] = PIN_NONE, + [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { + [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { + [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ + [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ + [ 7] = PIN_NONE, + [ 8] = PIN_NONE, + [ 9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, }; static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - const struct sh_pfc_bias_info *info; - u32 reg; - u32 bit; + const struct pinmux_bias_reg *reg; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return PIN_CONFIG_BIAS_DISABLE; - reg = info->reg; - bit = BIT(info->bit); - - if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -5675,28 +6111,24 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; u32 enable, updown; - u32 reg; - u32 bit; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return; - reg = info->reg; - bit = BIT(info->bit); - - enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= bit; + enable |= BIT(bit); - updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= bit; + updown |= BIT(bit); - sh_pfc_write_reg(pfc, PUD + reg, 32, updown); - sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); } static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { @@ -5721,6 +6153,8 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = { .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 22a8f06c292..c44e1bc961c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -23,8 +23,7 @@ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH) /* @@ -150,79 +149,79 @@ #define GPSR5_0 FM(QSPI0_SPCLK) -/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C */ /* D */ /* E */ /* F */ -#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N_A26) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ \ @@ -284,31 +283,7 @@ FM(IP8_23_20) IP8_23_20 \ FM(IP8_27_24) IP8_27_24 \ FM(IP8_31_28) IP8_31_28 -/* - Set Value = H'0 Set Value = H'1 -Register Function Pin Function Pin ------------------------------------------------------------- -sel_i2c3 SDA3_A VI0_DATA2 SDA3_B VI1_DATA10 - SCL3_A VI0_DATA3 SCL3_B VI1_DATA9 -sel_hscif0 HSCIF0_A SCIF_CLK HSCIF0_B SCIF_CLK -sel_scif1 SCIF1_A RX1 SCIF1_B TX1 - SCIF1_A TX1 SCIF1_B RX1 -sel_canfd0 CANFD0_A CANFD0_TX CANFD0_B CANFD0_TX - CANFD0_A CANFD0_RX CANFD0_B CANFD0_RX - CANFD0_A CANFD_CLK CANFD0_B CANFD_CLK -sel_pwm4 PWM4_A PWM4 PWM4_B PWM4 -sel_pwm3 PWM3_A PWM3 PWM3_B PWM3 -sel_pwm2 PWM2_A PWM2 PWM2_B PWM2 -sel_pwm1 PWM1_A PWM1 PWM1_B PWM1 -sel_pwm0 PWM0_A PWM0 PWM0_B PWM0 -sel_rfso RFSO_A FSO_CFE_0_N RFSO_B FSO_CFE_0_N - RFSO_A FSO_CFE_1_N RFSO_B FSO_CFE_1_N - RFSO_A FSO_TOE_N RFSO_B FSO_TOE_N -sel_rsp RSP_A SPEEDIN RSP_B SPEEDIN -sel_tmu TMU_A TCLK1 TMU_B TCLK1 - TMU_A TCLK2 TMU_B TCLK2 -*/ -/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +/* MOD_SEL0 */ /* 0 */ /* 1 */ #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1) #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) @@ -479,7 +454,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), PINMUX_IPSR_GPSR(IP2_7_4, A17), - PINMUX_IPSR_GPSR(IP2_7_4, STPWT_EXTFXR), PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0), @@ -492,11 +466,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), - PINMUX_IPSR_GPSR(IP2_19_16, A20), PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), - PINMUX_IPSR_GPSR(IP2_23_20, A21), PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT), @@ -531,15 +503,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), PINMUX_IPSR_GPSR(IP3_19_16, SCK1), - PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS), - PINMUX_IPSR_GPSR(IP3_23_20, SDA3_A), + PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0), PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), - PINMUX_IPSR_GPSR(IP3_27_24, SCL3_A), + PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0), PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), @@ -561,30 +533,26 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0), - PINMUX_IPSR_GPSR(IP4_15_12, A22), PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_GPSR(IP4_19_16, A23), PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_GPSR(IP4_23_20, A24), PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), PINMUX_IPSR_GPSR(IP4_27_24, HTX2), PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), - PINMUX_IPSR_GPSR(IP4_27_24, A25), PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1), PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), PINMUX_IPSR_GPSR(IP4_31_28, HRX2), PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), - PINMUX_IPSR_GPSR(IP4_31_28, CS1_N_A26), + PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A), /* IPSR5 */ @@ -653,12 +621,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS), PINMUX_IPSR_GPSR(IP6_23_20, D12), PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), - PINMUX_IPSR_GPSR(IP6_23_20, SCL3_B), + PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), PINMUX_IPSR_GPSR(IP6_27_24, D13), PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7), - PINMUX_IPSR_GPSR(IP6_27_24, SDA3_B), + PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1), PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), PINMUX_IPSR_GPSR(IP6_31_28, SCL4), @@ -720,31 +688,31 @@ static const u16 pinmux_data[] = { /* IPSR8 */ PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0), PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA), - PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1), + PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1), PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP), PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C), PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0), PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR), - PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1), + PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1), PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE), PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX), PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB), - PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1), + PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1), PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1), - PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1), PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX), PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR), - PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1), + PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1), PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1), - PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0), PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR), - PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1), - PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1), + PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1), PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1), PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN), @@ -758,129 +726,13 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; -/* - EtherAVB --------------------------------------------------------------- */ -static const unsigned int avb0_rx_ctrl_pins[] = { - /* AVB0_RX_CTL */ - RCAR_GP_PIN(1, 1), -}; -static const unsigned int avb0_rx_ctrl_mux[] = { - AVB0_RX_CTL_MARK, -}; -static const unsigned int avb0_rxc_pins[] = { - /* AVB0_RXC */ - RCAR_GP_PIN(1, 2), -}; -static const unsigned int avb0_rxc_mux[] = { - AVB0_RXC_MARK, -}; -static const unsigned int avb0_rd0_pins[] = { - /* AVB0_RD[0] */ - RCAR_GP_PIN(1, 3), -}; -static const unsigned int avb0_rd0_mux[] = { - AVB0_RD0_MARK, -}; -static const unsigned int avb0_rd1_pins[] = { - /* AVB0_RD[1] */ - RCAR_GP_PIN(1, 4), -}; -static const unsigned int avb0_rd1_mux[] = { - AVB0_RD1_MARK, -}; -static const unsigned int avb0_rd2_pins[] = { - /* AVB0_RD[2] */ - RCAR_GP_PIN(1, 5), -}; -static const unsigned int avb0_rd2_mux[] = { - AVB0_RD2_MARK, -}; -static const unsigned int avb0_rd3_pins[] = { - /* AVB0_RD[3] */ - RCAR_GP_PIN(1, 6), -}; -static const unsigned int avb0_rd3_mux[] = { - AVB0_RD3_MARK, -}; -static const unsigned int avb0_rd4_pins[] = { - /* AVB0_RD[3:0] */ - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int avb0_rd4_mux[] = { - AVB0_RD0_MARK, AVB0_RD1_MARK, - AVB0_RD2_MARK, AVB0_RD3_MARK, -}; -static const unsigned int avb0_tx_ctrl_pins[] = { - /* AVB0_TX_CTL */ - RCAR_GP_PIN(1, 7), -}; -static const unsigned int avb0_tx_ctrl_mux[] = { - AVB0_TX_CTL_MARK, -}; -static const unsigned int avb0_txc_pins[] = { - /* AVB0_TXC */ - RCAR_GP_PIN(1, 8), -}; -static const unsigned int avb0_txc_mux[] = { - AVB0_TXC_MARK, -}; -static const unsigned int avb0_td0_pins[] = { - /* AVB0_TD[0] */ - RCAR_GP_PIN(1, 9), -}; -static const unsigned int avb0_td0_mux[] = { - AVB0_TD0_MARK, -}; -static const unsigned int avb0_td1_pins[] = { - /* AVB0_TD[1] */ - RCAR_GP_PIN(1, 10), -}; -static const unsigned int avb0_td1_mux[] = { - AVB0_TD1_MARK, -}; -static const unsigned int avb0_td2_pins[] = { - /* AVB0_TD[2] */ - RCAR_GP_PIN(1, 11), -}; -static const unsigned int avb0_td2_mux[] = { - AVB0_TD2_MARK, -}; -static const unsigned int avb0_td3_pins[] = { - /* AVB0_TD[3] */ - RCAR_GP_PIN(1, 12), -}; -static const unsigned int avb0_td3_mux[] = { - AVB0_TD3_MARK, -}; -static const unsigned int avb0_td4_pins[] = { - /* AVB0_TD[3:0] */ - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), -}; -static const unsigned int avb0_td4_mux[] = { - AVB0_TD0_MARK, AVB0_TD1_MARK, - AVB0_TD2_MARK, AVB0_TD3_MARK, -}; -static const unsigned int avb0_txcrefclk_pins[] = { - /* AVB0_TXCREFCLK */ - RCAR_GP_PIN(1, 13), -}; -static const unsigned int avb0_txcrefclk_mux[] = { - AVB0_TXCREFCLK_MARK, -}; -static const unsigned int avb0_mdio_pins[] = { - /* AVB0_MDIO */ - RCAR_GP_PIN(1, 14), -}; -static const unsigned int avb0_mdio_mux[] = { - AVB0_MDIO_MARK, -}; -static const unsigned int avb0_mdc_pins[] = { - /* AVB0_MDC */ - RCAR_GP_PIN(1, 15), +/* - AVB0 ------------------------------------------------------------------- */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(1, 18), }; -static const unsigned int avb0_mdc_mux[] = { - AVB0_MDC_MARK, +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, }; static const unsigned int avb0_magic_pins[] = { /* AVB0_MAGIC */ @@ -896,19 +748,37 @@ static const unsigned int avb0_phy_int_pins[] = { static const unsigned int avb0_phy_int_mux[] = { AVB0_PHY_INT_MARK, }; -static const unsigned int avb0_link_pins[] = { - /* AVB0_LINK */ - RCAR_GP_PIN(1, 18), +static const unsigned int avb0_mdio_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), }; -static const unsigned int avb0_link_mux[] = { - AVB0_LINK_MARK, +static const unsigned int avb0_mdio_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_rgmii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3 + */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), }; -static const unsigned int avb0_avtp_match_pins[] = { - /* AVB0_AVTP_MATCH */ - RCAR_GP_PIN(1, 19), +static const unsigned int avb0_rgmii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, + AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, + AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, }; -static const unsigned int avb0_avtp_match_mux[] = { - AVB0_AVTP_MATCH_MARK, +static const unsigned int avb0_txcrefclk_pins[] = { + /* AVB0_TXCREFCLK */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int avb0_txcrefclk_mux[] = { + AVB0_TXCREFCLK_MARK, }; static const unsigned int avb0_avtp_pps_pins[] = { /* AVB0_AVTP_PPS */ @@ -924,6 +794,29 @@ static const unsigned int avb0_avtp_capture_pins[] = { static const unsigned int avb0_avtp_capture_mux[] = { AVB0_AVTP_CAPTURE_MARK, }; +static const unsigned int avb0_avtp_match_pins[] = { + /* AVB0_AVTP_MATCH */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int avb0_avtp_match_mux[] = { + AVB0_AVTP_MATCH_MARK, +}; + +/* - CANFD Clock ------------------------------------------------------------ */ +static const unsigned int canfd_clk_a_pins[] = { + /* CANFD_CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int canfd_clk_a_mux[] = { + CANFD_CLK_A_MARK, +}; +static const unsigned int canfd_clk_b_pins[] = { + /* CANFD_CLK */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int canfd_clk_b_mux[] = { + CANFD_CLK_B_MARK, +}; /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_a_pins[] = { @@ -933,13 +826,6 @@ static const unsigned int canfd0_data_a_pins[] = { static const unsigned int canfd0_data_a_mux[] = { CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, }; -static const unsigned int canfd_clk_a_pins[] = { - /* CLK */ - RCAR_GP_PIN(1, 25), -}; -static const unsigned int canfd_clk_a_mux[] = { - CANFD_CLK_A_MARK, -}; static const unsigned int canfd0_data_b_pins[] = { /* TX, RX */ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), @@ -947,13 +833,6 @@ static const unsigned int canfd0_data_b_pins[] = { static const unsigned int canfd0_data_b_mux[] = { CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, }; -static const unsigned int canfd_clk_b_pins[] = { - /* CLK */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int canfd_clk_b_mux[] = { - CANFD_CLK_B_MARK, -}; /* - CANFD1 ----------------------------------------------------------------- */ static const unsigned int canfd1_data_pins[] = { @@ -966,42 +845,27 @@ static const unsigned int canfd1_data_mux[] = { /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { - /* R[7:0] */ - RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), - RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), - RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), - /* G[7:0] */ - RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), - RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), - /* B[7:0] */ - RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), - RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), }; static const unsigned int du_rgb666_mux[] = { - DU_DR7_MARK, DU_DR6_MARK, - DU_DR5_MARK, DU_DR4_MARK, - DU_DR3_MARK, DU_DR2_MARK, - DU_DG7_MARK, DU_DG6_MARK, - DU_DG5_MARK, DU_DG4_MARK, - DU_DG3_MARK, DU_DG2_MARK, - DU_DB7_MARK, DU_DB6_MARK, - DU_DB5_MARK, DU_DB4_MARK, - DU_DB3_MARK, DU_DB2_MARK, -}; -static const unsigned int du_clk_out_0_pins[] = { - /* CLKOUT0 */ + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, + DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, + DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, + DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_clk_out_pins[] = { + /* DOTCLKOUT */ RCAR_GP_PIN(0, 18), }; -static const unsigned int du_clk_out_0_mux[] = { - DU_DOTCLKOUT_MARK, -}; -static const unsigned int du_clk_out_1_pins[] = { - /* CLKOUT1 */ - RCAR_GP_PIN(0, 18), /* @@ */ -}; -static const unsigned int du_clk_out_1_mux[] = { +static const unsigned int du_clk_out_mux[] = { DU_DOTCLKOUT_MARK, }; static const unsigned int du_sync_pins[] = { @@ -1009,10 +873,10 @@ static const unsigned int du_sync_pins[] = { RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), }; static const unsigned int du_sync_mux[] = { - DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK, + DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK }; static const unsigned int du_oddf_pins[] = { - /* EXDISP/EXODDF/EXCDE */ + /* EXODDF/ODDF/DISP/CDE */ RCAR_GP_PIN(0, 21), }; static const unsigned int du_oddf_mux[] = { @@ -1035,21 +899,21 @@ static const unsigned int du_disp_mux[] = { /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { - /* HRX0, HTX0 */ + /* HRX, HTX */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3), }; static const unsigned int hscif0_data_mux[] = { HRX0_MARK, HTX0_MARK, }; static const unsigned int hscif0_clk_pins[] = { - /* HSCK0 */ + /* HSCK */ RCAR_GP_PIN(0, 0), }; static const unsigned int hscif0_clk_mux[] = { HSCK0_MARK, }; static const unsigned int hscif0_ctrl_pins[] = { - /* HRTS0#, HCTS0# */ + /* HRTS#, HCTS# */ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), }; static const unsigned int hscif0_ctrl_mux[] = { @@ -1058,21 +922,21 @@ static const unsigned int hscif0_ctrl_mux[] = { /* - HSCIF1 ----------------------------------------------------------------- */ static const unsigned int hscif1_data_pins[] = { - /* HRX1, HTX1 */ + /* HRX, HTX */ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int hscif1_data_mux[] = { HRX1_MARK, HTX1_MARK, }; static const unsigned int hscif1_clk_pins[] = { - /* HSCK1 */ + /* HSCK */ RCAR_GP_PIN(2, 7), }; static const unsigned int hscif1_clk_mux[] = { HSCK1_MARK, }; static const unsigned int hscif1_ctrl_pins[] = { - /* HRTS1#, HCTS1# */ + /* HRTS#, HCTS# */ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), }; static const unsigned int hscif1_ctrl_mux[] = { @@ -1081,21 +945,21 @@ static const unsigned int hscif1_ctrl_mux[] = { /* - HSCIF2 ----------------------------------------------------------------- */ static const unsigned int hscif2_data_pins[] = { - /* HRX2, HTX2 */ + /* HRX, HTX */ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), }; static const unsigned int hscif2_data_mux[] = { HRX2_MARK, HTX2_MARK, }; static const unsigned int hscif2_clk_pins[] = { - /* HSCK2 */ + /* HSCK */ RCAR_GP_PIN(2, 12), }; static const unsigned int hscif2_clk_mux[] = { HSCK2_MARK, }; static const unsigned int hscif2_ctrl_pins[] = { - /* HRTS2#, HCTS2# */ + /* HRTS#, HCTS# */ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), }; static const unsigned int hscif2_ctrl_mux[] = { @@ -1104,74 +968,73 @@ static const unsigned int hscif2_ctrl_mux[] = { /* - HSCIF3 ----------------------------------------------------------------- */ static const unsigned int hscif3_data_pins[] = { - /* HRX3, HTX3 */ + /* HRX, HTX */ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int hscif3_data_mux[] = { HRX3_MARK, HTX3_MARK, }; static const unsigned int hscif3_clk_pins[] = { - /* HSCK3 */ + /* HSCK */ RCAR_GP_PIN(2, 0), }; static const unsigned int hscif3_clk_mux[] = { HSCK3_MARK, }; static const unsigned int hscif3_ctrl_pins[] = { - /* HRTS3#, HCTS3# */ + /* HRTS#, HCTS# */ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), }; static const unsigned int hscif3_ctrl_mux[] = { HRTS3_N_MARK, HCTS3_N_MARK, }; -/* - SCIF Clock ------------------------------------------------------------- */ -static const unsigned int scif_clk_a_pins[] = { - /* SCIF_CLK */ - RCAR_GP_PIN(0, 18), -}; -static const unsigned int scif_clk_a_mux[] = { - SCIF_CLK_A_MARK, -}; -static const unsigned int scif_clk_b_pins[] = { - /* SCIF_CLK */ - RCAR_GP_PIN(1, 25), -}; -static const unsigned int scif_clk_b_mux[] = { - SCIF_CLK_B_MARK, -}; - -/* - I2C -------------------------------------------------------------------- */ +/* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { - /* SDA0, SCL0 */ + /* SDA, SCL */ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), }; static const unsigned int i2c0_mux[] = { SDA0_MARK, SCL0_MARK, }; + +/* - I2C1 ------------------------------------------------------------------- */ static const unsigned int i2c1_pins[] = { - /* SDA1, SCL1 */ + /* SDA, SCL */ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int i2c1_mux[] = { SDA1_MARK, SCL1_MARK, }; + +/* - I2C2 ------------------------------------------------------------------- */ static const unsigned int i2c2_pins[] = { - /* SDA2, SCL2 */ + /* SDA, SCL */ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), }; static const unsigned int i2c2_mux[] = { SDA2_MARK, SCL2_MARK, }; -static const unsigned int i2c3_pins[] = { - /* SDA3_A, SCL3_A */ - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), }; -static const unsigned int i2c3_mux[] = { +static const unsigned int i2c3_a_mux[] = { SDA3_A_MARK, SCL3_A_MARK, }; +static const unsigned int i2c3_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), +}; +static const unsigned int i2c3_b_mux[] = { + SDA3_B_MARK, SCL3_B_MARK, +}; + +/* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_pins[] = { - /* SDA4, SCL4 */ + /* SDA, SCL */ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), }; static const unsigned int i2c4_mux[] = { @@ -1222,6 +1085,58 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, + MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, + MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int mmc_cd_mux[] = { + MMC_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int mmc_wp_mux[] = { + MMC_WP_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1400,14 +1315,12 @@ static const unsigned int msiof3_rxd_mux[] = { /* - PWM0 ------------------------------------------------------------------- */ static const unsigned int pwm0_a_pins[] = { - /* PWM0 */ RCAR_GP_PIN(2, 12), }; static const unsigned int pwm0_a_mux[] = { PWM0_A_MARK, }; static const unsigned int pwm0_b_pins[] = { - /* PWM0 */ RCAR_GP_PIN(1, 21), }; static const unsigned int pwm0_b_mux[] = { @@ -1416,14 +1329,12 @@ static const unsigned int pwm0_b_mux[] = { /* - PWM1 ------------------------------------------------------------------- */ static const unsigned int pwm1_a_pins[] = { - /* PWM1 */ RCAR_GP_PIN(2, 13), }; static const unsigned int pwm1_a_mux[] = { PWM1_A_MARK, }; static const unsigned int pwm1_b_pins[] = { - /* PWM1 */ RCAR_GP_PIN(1, 22), }; static const unsigned int pwm1_b_mux[] = { @@ -1432,14 +1343,12 @@ static const unsigned int pwm1_b_mux[] = { /* - PWM2 ------------------------------------------------------------------- */ static const unsigned int pwm2_a_pins[] = { - /* PWM2 */ RCAR_GP_PIN(2, 14), }; static const unsigned int pwm2_a_mux[] = { PWM2_A_MARK, }; static const unsigned int pwm2_b_pins[] = { - /* PWM2 */ RCAR_GP_PIN(1, 23), }; static const unsigned int pwm2_b_mux[] = { @@ -1448,14 +1357,12 @@ static const unsigned int pwm2_b_mux[] = { /* - PWM3 ------------------------------------------------------------------- */ static const unsigned int pwm3_a_pins[] = { - /* PWM3 */ RCAR_GP_PIN(2, 15), }; static const unsigned int pwm3_a_mux[] = { PWM3_A_MARK, }; static const unsigned int pwm3_b_pins[] = { - /* PWM3 */ RCAR_GP_PIN(1, 24), }; static const unsigned int pwm3_b_mux[] = { @@ -1464,20 +1371,34 @@ static const unsigned int pwm3_b_mux[] = { /* - PWM4 ------------------------------------------------------------------- */ static const unsigned int pwm4_a_pins[] = { - /* PWM4 */ RCAR_GP_PIN(2, 16), }; static const unsigned int pwm4_a_mux[] = { PWM4_A_MARK, }; static const unsigned int pwm4_b_pins[] = { - /* PWM4 */ RCAR_GP_PIN(1, 25), }; static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -1493,9 +1414,8 @@ static const unsigned int scif0_clk_pins[] = { static const unsigned int scif0_clk_mux[] = { SCK0_MARK, }; - static const unsigned int scif0_ctrl_pins[] = { - /* RTS, CTS */ + /* RTS#, CTS# */ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int scif0_ctrl_mux[] = { @@ -1518,7 +1438,7 @@ static const unsigned int scif1_clk_mux[] = { SCK1_MARK, }; static const unsigned int scif1_ctrl_pins[] = { - /* RTS, CTS */ + /* RTS#, CTS# */ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int scif1_ctrl_mux[] = { @@ -1548,7 +1468,7 @@ static const unsigned int scif3_clk_mux[] = { SCK3_MARK, }; static const unsigned int scif3_ctrl_pins[] = { - /* RTS, CTS */ + /* RTS#, CTS# */ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int scif3_ctrl_mux[] = { @@ -1571,65 +1491,13 @@ static const unsigned int scif4_clk_mux[] = { SCK4_MARK, }; static const unsigned int scif4_ctrl_pins[] = { - /* RTS, CTS */ + /* RTS#, CTS# */ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; static const unsigned int scif4_ctrl_mux[] = { RTS4_N_TANS_MARK, CTS4_N_MARK, }; -/* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 6), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { - /* D[0:7] */ - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), -}; -static const unsigned int mmc_data8_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, - MMC_D4_MARK, MMC_D5_MARK, - MMC_D6_MARK, MMC_D7_MARK, -}; -static const unsigned int mmc_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(3,10), RCAR_GP_PIN(3, 5), -}; -static const unsigned int mmc_ctrl_mux[] = { - MMC_CLK_MARK, MMC_CMD_MARK, -}; -static const unsigned int mmc_cd_pins[] = { - /* CD */ - RCAR_GP_PIN(3, 16), -}; -static const unsigned int mmc_cd_mux[] = { - MMC_CD_MARK, -}; -static const unsigned int mmc_wp_pins[] = { - /* WP */ - RCAR_GP_PIN(3, 15), -}; -static const unsigned int mmc_wp_mux[] = { - MMC_WP_MARK, -}; - /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { /* TCLK1 */ @@ -1704,8 +1572,8 @@ static const unsigned int vin0_data12_mux[] = { VI0_DATA10_MARK, VI0_DATA11_MARK, }; static const unsigned int vin0_sync_pins[] = { - /* VSYNC_N, HSYNC_N */ - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), }; static const unsigned int vin0_sync_mux[] = { VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK, @@ -1731,6 +1599,7 @@ static const unsigned int vin0_clk_pins[] = { static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; + /* - VIN1 ------------------------------------------------------------------- */ static const unsigned int vin1_data8_pins[] = { RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), @@ -1775,66 +1644,51 @@ static const unsigned int vin1_data12_mux[] = { VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { - /* VSYNC_N, HSYNC_N */ - RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), }; static const unsigned int vin1_sync_mux[] = { VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, }; static const unsigned int vin1_field_pins[] = { - /* FIELD */ RCAR_GP_PIN(3, 16), }; static const unsigned int vin1_field_mux[] = { + /* FIELD */ VI1_FIELD_MARK, }; static const unsigned int vin1_clkenb_pins[] = { - /* CLKENB */ RCAR_GP_PIN(3, 1), }; static const unsigned int vin1_clkenb_mux[] = { + /* CLKENB */ VI1_CLKENB_MARK, }; static const unsigned int vin1_clk_pins[] = { - /* CLK */ RCAR_GP_PIN(3, 0), }; static const unsigned int vin1_clk_mux[] = { + /* CLK */ VI1_CLK_MARK, }; static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(avb0_rx_ctrl), - SH_PFC_PIN_GROUP(avb0_rxc), - SH_PFC_PIN_GROUP(avb0_rd0), - SH_PFC_PIN_GROUP(avb0_rd1), - SH_PFC_PIN_GROUP(avb0_rd2), - SH_PFC_PIN_GROUP(avb0_rd3), - SH_PFC_PIN_GROUP(avb0_rd4), - SH_PFC_PIN_GROUP(avb0_tx_ctrl), - SH_PFC_PIN_GROUP(avb0_txc), - SH_PFC_PIN_GROUP(avb0_td0), - SH_PFC_PIN_GROUP(avb0_td1), - SH_PFC_PIN_GROUP(avb0_td2), - SH_PFC_PIN_GROUP(avb0_td3), - SH_PFC_PIN_GROUP(avb0_td4), - SH_PFC_PIN_GROUP(avb0_txcrefclk), - SH_PFC_PIN_GROUP(avb0_mdio), - SH_PFC_PIN_GROUP(avb0_mdc), + SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), - SH_PFC_PIN_GROUP(avb0_link), - SH_PFC_PIN_GROUP(avb0_avtp_match), + SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_rgmii), + SH_PFC_PIN_GROUP(avb0_txcrefclk), SH_PFC_PIN_GROUP(avb0_avtp_pps), SH_PFC_PIN_GROUP(avb0_avtp_capture), - SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(avb0_avtp_match), SH_PFC_PIN_GROUP(canfd_clk_a), - SH_PFC_PIN_GROUP(canfd0_data_b), SH_PFC_PIN_GROUP(canfd_clk_b), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_clk_out), SH_PFC_PIN_GROUP(du_sync), SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), @@ -1851,12 +1705,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif3_data), SH_PFC_PIN_GROUP(hscif3_clk), SH_PFC_PIN_GROUP(hscif3_ctrl), - SH_PFC_PIN_GROUP(scif_clk_a), - SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), @@ -1864,6 +1717,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1898,6 +1757,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1911,12 +1772,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif4_data), SH_PFC_PIN_GROUP(scif4_clk), SH_PFC_PIN_GROUP(scif4_ctrl), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), - SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(mmc_cd), - SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -1938,30 +1793,25 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { }; static const char * const avb0_groups[] = { - "avb0_rx_ctrl", - "avb0_rxc", - "avb0_rd1", - "avb0_rd4", - "avb0_tx_ctrl", - "avb0_txc", - "avb0_td1", - "avb0_td4", - "avb0_txcrefclk", - "avb0_mdio", - "avb0_mdc", + "avb0_link", "avb0_magic", "avb0_phy_int", - "avb0_link", - "avb0_avtp_match", + "avb0_mdio", + "avb0_rgmii", + "avb0_txcrefclk", "avb0_avtp_pps", "avb0_avtp_capture", + "avb0_avtp_match", +}; + +static const char * const canfd_clk_groups[] = { + "canfd_clk_a", + "canfd_clk_b", }; static const char * const canfd0_groups[] = { "canfd0_data_a", - "canfd_clk_a", "canfd0_data_b", - "canfd_clk_b", }; static const char * const canfd1_groups[] = { @@ -1970,8 +1820,7 @@ static const char * const canfd1_groups[] = { static const char * const du_groups[] = { "du_rgb666", - "du_clk_out_0", - "du_clk_out_1", + "du_clk_out", "du_sync", "du_oddf", "du_cde", @@ -2002,11 +1851,6 @@ static const char * const hscif3_groups[] = { "hscif3_ctrl", }; -static const char * const scif_clk_groups[] = { - "scif_clk_a", - "scif_clk_b", -}; - static const char * const i2c0_groups[] = { "i2c0", }; @@ -2020,7 +1864,8 @@ static const char * const i2c2_groups[] = { }; static const char * const i2c3_groups[] = { - "i2c3", + "i2c3_a", + "i2c3_b", }; static const char * const i2c4_groups[] = { @@ -2036,6 +1881,15 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2097,10 +1951,15 @@ static const char * const pwm4_groups[] = { "pwm4_b", }; +static const char * const scif_clk_groups[] = { + "scif_clk_a", + "scif_clk_b", +}; + static const char * const scif0_groups[] = { "scif0_data", -// "scif0_clk", -// "scif0_ctrl", + "scif0_clk", + "scif0_ctrl", }; static const char * const scif1_groups[] = { @@ -2122,15 +1981,6 @@ static const char * const scif4_groups[] = { "scif4_ctrl", }; -static const char * const mmc_groups[] = { - "mmc_data1", - "mmc_data4", - "mmc_data8", - "mmc_ctrl", - "mmc_cd", - "mmc_wp", -}; - static const char * const tmu_groups[] = { "tmu_tclk1_a", "tmu_tclk1_b", @@ -2158,17 +2008,9 @@ static const char * const vin1_groups[] = { "vin1_clk", }; -#define POCCTRL0 0x380 -#define POCCTRL1 0x384 -#define PIN2POCCTRL0_SHIFT(a) ({ \ - int _gp = (a) >> 5; \ - int _bit = (a) & 0x1f; \ - ((_gp == 3) && (_bit < 17)) ? _bit + 7 : -1; \ -}) - - static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb0), + SH_PFC_FUNCTION(canfd_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), @@ -2176,13 +2018,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), - SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2192,11 +2034,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), @@ -2509,28 +2351,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("MOD_SEL0", 0xe6060500, 32, 1) { - /* RESERVED 31..12 */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 4, 4, 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* RESERVED 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MOD_SEL0_11 MOD_SEL0_10 MOD_SEL0_9 @@ -2547,16 +2380,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) { - int bit = -EINVAL; + int bit = pin & 0x1f; - *pocctrl = 0xe6060384; + *pocctrl = 0xe6060380; + if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) + return bit; + if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) + return bit + 22; + *pocctrl += 4; + if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) + return bit - 10; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) - bit = (pin & 0x1f) + 7; + return bit + 7; - return bit; + return -EINVAL; } static const struct sh_pfc_soc_operations pinmux_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index f66b1597aa0..a99fd770f2f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -19,15 +19,21 @@ #include "sh_pfc.h" +#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_18(0, fn, sfx), \ PORT_GP_23(1, fn, sfx), \ PORT_GP_26(2, fn, sfx), \ - PORT_GP_16(3, fn, sfx), \ + PORT_GP_12(3, fn, sfx), \ + PORT_GP_1(3, 12, fn, sfx), \ + PORT_GP_1(3, 13, fn, sfx), \ + PORT_GP_1(3, 14, fn, sfx), \ + PORT_GP_1(3, 15, fn, sfx), \ PORT_GP_11(4, fn, sfx), \ PORT_GP_20(5, fn, sfx), \ PORT_GP_18(6, fn, sfx) - /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -464,6 +470,17 @@ MOD_SEL0_3 \ MOD_SEL0_2 \ MOD_SEL0_1_0 +/* + * These pins are not able to be muxed but have other properties + * that can be set, such as pull-up/pull-down enable. + */ +#define PINMUX_STATIC \ + FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \ + FM(AVB_TD3) \ + FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ + FM(ASEBRK) \ + FM(MLB_REF) + enum { PINMUX_RESERVED = 0, @@ -488,6 +505,7 @@ enum { PINMUX_GPSR PINMUX_IPSR PINMUX_MOD_SELS + PINMUX_STATIC PINMUX_MARK_END, #undef F_ #undef FM @@ -496,6 +514,13 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), + PINMUX_SINGLE(CLKOUT), + PINMUX_SINGLE(AVB_PHY_INT), + PINMUX_SINGLE(AVB_RD3), + PINMUX_SINGLE(AVB_RXC), + PINMUX_SINGLE(AVB_RX_CTL), + PINMUX_SINGLE(QSPI0_SSL), + /* IPSR0 */ PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), @@ -1230,16 +1255,3431 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), + +/* + * Static pins can not be muxed between different functions but + * still needs a mark entry in the pinmux list. Add each static + * pin to the list without an associated function. The sh-pfc + * core will do the right thing and skip trying to mux then pin + * while still applying configuration to it + */ +#define FM(x) PINMUX_DATA(x##_MARK, 0), + PINMUX_STATIC +#undef FM }; +/* + * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs. + * Physical layout rows: A - AE, cols: 1 - 25. + */ +#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) +#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300) +#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + + /* + * Pins not associated with a GPIO port. + * + * The pin positions are different between different R8A77990 + * packages, all that is needed for the pfc driver is a unique + * number for each pin. To this end use the pin layout from + * R8A77990 to calculate a unique number for each pin. + */ + SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS), +}; + +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(6, 8), +}; + +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; + +static const unsigned int audio_clk_b_a_pins[] = { + /* CLK B_A */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int audio_clk_b_a_mux[] = { + AUDIO_CLKB_A_MARK, +}; + +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK B_B */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; + +static const unsigned int audio_clk_b_c_pins[] = { + /* CLK B_C */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int audio_clk_b_c_mux[] = { + AUDIO_CLKB_C_MARK, +}; + +static const unsigned int audio_clk_c_a_pins[] = { + /* CLK C_A */ + RCAR_GP_PIN(5, 16), +}; + +static const unsigned int audio_clk_c_a_mux[] = { + AUDIO_CLKC_A_MARK, +}; + +static const unsigned int audio_clk_c_b_pins[] = { + /* CLK C_B */ + RCAR_GP_PIN(6, 3), +}; + +static const unsigned int audio_clk_c_b_mux[] = { + AUDIO_CLKC_B_MARK, +}; + +static const unsigned int audio_clk_c_c_pins[] = { + /* CLK C_C */ + RCAR_GP_PIN(6, 14), +}; + +static const unsigned int audio_clk_c_c_mux[] = { + AUDIO_CLKC_C_MARK, +}; + +static const unsigned int audio_clkout_a_pins[] = { + /* CLKOUT_A */ + RCAR_GP_PIN(5, 3), +}; + +static const unsigned int audio_clkout_a_mux[] = { + AUDIO_CLKOUT_A_MARK, +}; + +static const unsigned int audio_clkout_b_pins[] = { + /* CLKOUT_B */ + RCAR_GP_PIN(5, 13), +}; + +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; + +static const unsigned int audio_clkout1_a_pins[] = { + /* CLKOUT1_A */ + RCAR_GP_PIN(5, 4), +}; + +static const unsigned int audio_clkout1_a_mux[] = { + AUDIO_CLKOUT1_A_MARK, +}; + +static const unsigned int audio_clkout1_b_pins[] = { + /* CLKOUT1_B */ + RCAR_GP_PIN(5, 5), +}; + +static const unsigned int audio_clkout1_b_mux[] = { + AUDIO_CLKOUT1_B_MARK, +}; + +static const unsigned int audio_clkout1_c_pins[] = { + /* CLKOUT1_C */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int audio_clkout1_c_mux[] = { + AUDIO_CLKOUT1_C_MARK, +}; + +static const unsigned int audio_clkout2_a_pins[] = { + /* CLKOUT2_A */ + RCAR_GP_PIN(5, 8), +}; + +static const unsigned int audio_clkout2_a_mux[] = { + AUDIO_CLKOUT2_A_MARK, +}; + +static const unsigned int audio_clkout2_b_pins[] = { + /* CLKOUT2_B */ + RCAR_GP_PIN(6, 4), +}; + +static const unsigned int audio_clkout2_b_mux[] = { + AUDIO_CLKOUT2_B_MARK, +}; + +static const unsigned int audio_clkout2_c_pins[] = { + /* CLKOUT2_C */ + RCAR_GP_PIN(6, 15), +}; + +static const unsigned int audio_clkout2_c_mux[] = { + AUDIO_CLKOUT2_C_MARK, +}; + +static const unsigned int audio_clkout3_a_pins[] = { + /* CLKOUT3_A */ + RCAR_GP_PIN(5, 9), +}; + +static const unsigned int audio_clkout3_a_mux[] = { + AUDIO_CLKOUT3_A_MARK, +}; + +static const unsigned int audio_clkout3_b_pins[] = { + /* CLKOUT3_B */ + RCAR_GP_PIN(5, 6), +}; + +static const unsigned int audio_clkout3_b_mux[] = { + AUDIO_CLKOUT3_B_MARK, +}; + +static const unsigned int audio_clkout3_c_pins[] = { + /* CLKOUT3_C */ + RCAR_GP_PIN(6, 16), +}; + +static const unsigned int audio_clkout3_c_mux[] = { + AUDIO_CLKOUT3_C_MARK, +}; + +/* - EtherAVB --------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + /* AVB_LINK */ + RCAR_GP_PIN(2, 23), +}; + +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; + +static const unsigned int avb_magic_pins[] = { + /* AVB_MAGIC */ + RCAR_GP_PIN(2, 22), +}; + +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; + +static const unsigned int avb_phy_int_pins[] = { + /* AVB_PHY_INT */ + RCAR_GP_PIN(2, 21), +}; + +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; + +static const unsigned int avb_mii_pins[] = { + /* + * AVB_RX_CTL, AVB_RXC, AVB_RD0, + * AVB_RD1, AVB_RD2, AVB_RD3, + * AVB_TXCREFCLK + */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 20), +}; + +static const unsigned int avb_mii_mux[] = { + AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, + AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, + AVB_TXCREFCLK_MARK, +}; + +static const unsigned int avb_avtp_pps_pins[] = { + /* AVB_AVTP_PPS */ + RCAR_GP_PIN(1, 2), +}; + +static const unsigned int avb_avtp_pps_mux[] = { + AVB_AVTP_PPS_MARK, +}; + +static const unsigned int avb_avtp_match_a_pins[] = { + /* AVB_AVTP_MATCH_A */ + RCAR_GP_PIN(2, 24), +}; + +static const unsigned int avb_avtp_match_a_mux[] = { + AVB_AVTP_MATCH_A_MARK, +}; + +static const unsigned int avb_avtp_capture_a_pins[] = { + /* AVB_AVTP_CAPTURE_A */ + RCAR_GP_PIN(2, 25), +}; + +static const unsigned int avb_avtp_capture_a_mux[] = { + AVB_AVTP_CAPTURE_A_MARK, +}; + +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; + +static const unsigned int can0_data_mux[] = { + CAN0_TX_MARK, CAN0_RX_MARK, +}; + +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(0, 14), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD --------------------------------------------------------------- */ +static const unsigned int canfd0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; + +static const unsigned int canfd0_data_mux[] = { + CANFD0_TX_MARK, CANFD0_RX_MARK, +}; + +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + +/* - DRIF0 --------------------------------------------------------------- */ +static const unsigned int drif0_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19), +}; + +static const unsigned int drif0_ctrl_a_mux[] = { + RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, +}; + +static const unsigned int drif0_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(5, 17), +}; + +static const unsigned int drif0_data0_a_mux[] = { + RIF0_D0_A_MARK, +}; + +static const unsigned int drif0_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(5, 18), +}; + +static const unsigned int drif0_data1_a_mux[] = { + RIF0_D1_A_MARK, +}; + +static const unsigned int drif0_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int drif0_ctrl_b_mux[] = { + RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, +}; + +static const unsigned int drif0_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int drif0_data0_b_mux[] = { + RIF0_D0_B_MARK, +}; + +static const unsigned int drif0_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(3, 14), +}; + +static const unsigned int drif0_data1_b_mux[] = { + RIF0_D1_B_MARK, +}; + +/* - DRIF1 --------------------------------------------------------------- */ +static const unsigned int drif1_ctrl_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1), +}; + +static const unsigned int drif1_ctrl_mux[] = { + RIF1_CLK_MARK, RIF1_SYNC_MARK, +}; + +static const unsigned int drif1_data0_pins[] = { + /* D0 */ + RCAR_GP_PIN(5, 2), +}; + +static const unsigned int drif1_data0_mux[] = { + RIF1_D0_MARK, +}; + +static const unsigned int drif1_data1_pins[] = { + /* D1 */ + RCAR_GP_PIN(5, 3), +}; + +static const unsigned int drif1_data1_mux[] = { + RIF1_D1_MARK, +}; + +/* - DRIF2 --------------------------------------------------------------- */ +static const unsigned int drif2_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), +}; + +static const unsigned int drif2_ctrl_a_mux[] = { + RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, +}; + +static const unsigned int drif2_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(2, 8), +}; + +static const unsigned int drif2_data0_a_mux[] = { + RIF2_D0_A_MARK, +}; + +static const unsigned int drif2_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(2, 9), +}; + +static const unsigned int drif2_data1_a_mux[] = { + RIF2_D1_A_MARK, +}; + +static const unsigned int drif2_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), +}; + +static const unsigned int drif2_ctrl_b_mux[] = { + RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, +}; + +static const unsigned int drif2_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(1, 6), +}; + +static const unsigned int drif2_data0_b_mux[] = { + RIF2_D0_B_MARK, +}; + +static const unsigned int drif2_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(1, 7), +}; + +static const unsigned int drif2_data1_b_mux[] = { + RIF2_D1_B_MARK, +}; + +/* - DRIF3 --------------------------------------------------------------- */ +static const unsigned int drif3_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), +}; + +static const unsigned int drif3_ctrl_a_mux[] = { + RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, +}; + +static const unsigned int drif3_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(2, 12), +}; + +static const unsigned int drif3_data0_a_mux[] = { + RIF3_D0_A_MARK, +}; + +static const unsigned int drif3_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(2, 13), +}; + +static const unsigned int drif3_data1_a_mux[] = { + RIF3_D1_A_MARK, +}; + +static const unsigned int drif3_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), +}; + +static const unsigned int drif3_ctrl_b_mux[] = { + RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, +}; + +static const unsigned int drif3_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(0, 10), +}; + +static const unsigned int drif3_data0_b_mux[] = { + RIF3_D0_B_MARK, +}; + +static const unsigned int drif3_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(0, 11), +}; + +static const unsigned int drif3_data1_b_mux[] = { + RIF3_D1_B_MARK, +}; + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +}; + +static const unsigned int du_rgb666_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, +}; + +static const unsigned int du_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; + +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, +}; + +static const unsigned int du_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(1, 3), +}; + +static const unsigned int du_clk_out_0_mux[] = { + DU_DOTCLKOUT0_MARK +}; + +static const unsigned int du_sync_pins[] = { + /* VSYNC, HSYNC */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), +}; + +static const unsigned int du_sync_mux[] = { + DU_VSYNC_MARK, DU_HSYNC_MARK +}; + +static const unsigned int du_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int du_cde_mux[] = { + DU_CDE_MARK, +}; + +static const unsigned int du_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(1, 2), +}; + +static const unsigned int du_disp_mux[] = { + DU_DISP_MARK, +}; + +static const unsigned int du_disp_cde_pins[] = { + /* DISP/CDE */ + RCAR_GP_PIN(1, 1), +}; + +static const unsigned int du_disp_cde_mux[] = { + DU_DISP_CDE_MARK, +}; + +static const unsigned int du_clk_in_0_pins[] = { + /* DOTCLKIN0 */ + RCAR_GP_PIN(0, 16), +}; + +static const unsigned int du_clk_in_0_mux[] = { + DU_DOTCLKIN0_MARK, +}; + +static const unsigned int du_clk_in_1_pins[] = { + /* DOTCLKIN0 */ + RCAR_GP_PIN(1, 1), +}; + +static const unsigned int du_clk_in_1_mux[] = { + DU_DOTCLKIN1_MARK, +}; + +/* - HSCIF0 --------------------------------------------------*/ +static const unsigned int hscif0_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), +}; + +static const unsigned int hscif0_data_a_mux[] = { + HRX0_A_MARK, HTX0_A_MARK, +}; + +static const unsigned int hscif0_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int hscif0_clk_a_mux[] = { + HSCK0_A_MARK, +}; + +static const unsigned int hscif0_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), +}; + +static const unsigned int hscif0_ctrl_a_mux[] = { + HRTS0_N_A_MARK, HCTS0_N_A_MARK, +}; + +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; + +static const unsigned int hscif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int hscif0_clk_b_mux[] = { + HSCK0_B_MARK, +}; + +/* - HSCIF1 ------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; + +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; + +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; + +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), +}; + +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; + +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; + +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; + +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), +}; + +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; + +/* - HSCIF2 ------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), +}; + +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; + +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 14), +}; + +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; + +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), +}; + +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; + +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; + +/* - HSCIF3 ------------------------------------------------*/ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; + +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; + +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; + +static const unsigned int hscif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 4), +}; + +static const unsigned int hscif3_clk_b_mux[] = { + HSCK3_B_MARK, +}; + +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), +}; + +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; + +static const unsigned int hscif3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 11), +}; + +static const unsigned int hscif3_clk_c_mux[] = { + HSCK3_C_MARK, +}; + +static const unsigned int hscif3_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), +}; + +static const unsigned int hscif3_ctrl_c_mux[] = { + HRTS3_N_C_MARK, HCTS3_N_C_MARK, +}; + +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0), +}; + +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; + +static const unsigned int hscif3_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; + +static const unsigned int hscif3_data_e_mux[] = { + HRX3_E_MARK, HTX3_E_MARK, +}; + +static const unsigned int hscif3_ctrl_e_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), +}; + +static const unsigned int hscif3_ctrl_e_mux[] = { + HRTS3_N_E_MARK, HCTS3_N_E_MARK, +}; + +/* - HSCIF4 -------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), +}; + +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; + +static const unsigned int hscif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 0), +}; + +static const unsigned int hscif4_clk_a_mux[] = { + HSCK4_A_MARK, +}; + +static const unsigned int hscif4_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), +}; + +static const unsigned int hscif4_ctrl_a_mux[] = { + HRTS4_N_A_MARK, HCTS4_N_A_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), +}; + +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + +static const unsigned int hscif4_clk_b_pins[] = { +/* SCK */ + RCAR_GP_PIN(2, 6), +}; + +static const unsigned int hscif4_clk_b_mux[] = { + HSCK4_B_MARK, +}; + +static const unsigned int hscif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; + +static const unsigned int hscif4_data_c_mux[] = { + HRX4_C_MARK, HTX4_C_MARK, +}; + +static const unsigned int hscif4_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int hscif4_data_d_mux[] = { + HRX4_D_MARK, HTX4_D_MARK, +}; + +static const unsigned int hscif4_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; + +static const unsigned int hscif4_data_e_mux[] = { + HRX4_E_MARK, HTX4_E_MARK, +}; + +/* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c1_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), +}; + +static const unsigned int i2c1_a_mux[] = { + SCL1_A_MARK, SDA1_A_MARK, +}; + +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), +}; + +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; + +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5), +}; + +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; + +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), +}; + +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; + +static const unsigned int i2c2_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0), +}; + +static const unsigned int i2c2_a_mux[] = { + SCL2_A_MARK, SDA2_A_MARK, +}; + +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; + +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; + +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), +}; + +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; + +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; + +static const unsigned int i2c2_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), +}; + +static const unsigned int i2c2_e_mux[] = { + SCL2_E_MARK, SDA2_E_MARK, +}; + +static const unsigned int i2c4_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), +}; + +static const unsigned int i2c4_mux[] = { + SCL4_MARK, SDA4_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + +static const unsigned int i2c6_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), +}; + +static const unsigned int i2c6_a_mux[] = { + SCL6_A_MARK, SDA6_A_MARK, +}; + +static const unsigned int i2c6_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), +}; + +static const unsigned int i2c6_b_mux[] = { + SCL6_B_MARK, SDA6_B_MARK, +}; + +static const unsigned int i2c7_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25), +}; + +static const unsigned int i2c7_a_mux[] = { + SCL7_A_MARK, SDA7_A_MARK, +}; + +static const unsigned int i2c7_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), +}; + +static const unsigned int i2c7_b_mux[] = { + SCL7_B_MARK, SDA7_B_MARK, +}; + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 10), +}; + +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; + +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 13), +}; + +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; + +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 14), +}; + +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; + +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 15), +}; + +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; + +static const unsigned int msiof0_txd_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 12), +}; + +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; + +static const unsigned int msiof0_rxd_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 11), +}; + +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 19), +}; + +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; + +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 16), +}; + +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; + +static const unsigned int msiof1_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 14), +}; + +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; + +static const unsigned int msiof1_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 15), +}; + +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; + +static const unsigned int msiof1_txd_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 18), +}; + +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; + +static const unsigned int msiof1_rxd_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 17), +}; + +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; + +static const unsigned int msiof2_clk_a_mux[] = { + MSIOF2_SCK_A_MARK, +}; + +static const unsigned int msiof2_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 9), +}; + +static const unsigned int msiof2_sync_a_mux[] = { + MSIOF2_SYNC_A_MARK, +}; + +static const unsigned int msiof2_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 15), +}; + +static const unsigned int msiof2_ss1_a_mux[] = { + MSIOF2_SS1_A_MARK, +}; + +static const unsigned int msiof2_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 14), +}; + +static const unsigned int msiof2_ss2_a_mux[] = { + MSIOF2_SS2_A_MARK, +}; + +static const unsigned int msiof2_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 11), +}; + +static const unsigned int msiof2_txd_a_mux[] = { + MSIOF2_TXD_A_MARK, +}; + +static const unsigned int msiof2_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 10), +}; + +static const unsigned int msiof2_rxd_a_mux[] = { + MSIOF2_RXD_A_MARK, +}; + +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 13), +}; + +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; + +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 10), +}; + +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; + +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 16), +}; + +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; + +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 12), +}; + +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; + +static const unsigned int msiof2_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 15), +}; + +static const unsigned int msiof2_txd_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; + +static const unsigned int msiof2_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 14), +}; + +static const unsigned int msiof2_rxd_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; + +static const unsigned int msiof3_clk_a_mux[] = { + MSIOF3_SCK_A_MARK, +}; + +static const unsigned int msiof3_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 1), +}; + +static const unsigned int msiof3_sync_a_mux[] = { + MSIOF3_SYNC_A_MARK, +}; + +static const unsigned int msiof3_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 15), +}; + +static const unsigned int msiof3_ss1_a_mux[] = { + MSIOF3_SS1_A_MARK, +}; + +static const unsigned int msiof3_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 4), +}; + +static const unsigned int msiof3_ss2_a_mux[] = { + MSIOF3_SS2_A_MARK, +}; + +static const unsigned int msiof3_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 3), +}; + +static const unsigned int msiof3_txd_a_mux[] = { + MSIOF3_TXD_A_MARK, +}; + +static const unsigned int msiof3_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 2), +}; + +static const unsigned int msiof3_rxd_a_mux[] = { + MSIOF3_RXD_A_MARK, +}; + +static const unsigned int msiof3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 5), +}; + +static const unsigned int msiof3_clk_b_mux[] = { + MSIOF3_SCK_B_MARK, +}; + +static const unsigned int msiof3_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 4), +}; + +static const unsigned int msiof3_sync_b_mux[] = { + MSIOF3_SYNC_B_MARK, +}; + +static const unsigned int msiof3_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int msiof3_ss1_b_mux[] = { + MSIOF3_SS1_B_MARK, +}; + +static const unsigned int msiof3_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 7), +}; + +static const unsigned int msiof3_txd_b_mux[] = { + MSIOF3_TXD_B_MARK, +}; + +static const unsigned int msiof3_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 6), +}; + +static const unsigned int msiof3_rxd_b_mux[] = { + MSIOF3_RXD_B_MARK, +}; + +/* - PWM0 --------------------------------------------------------------------*/ +static const unsigned int pwm0_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 22), +}; + +static const unsigned int pwm0_a_mux[] = { + PWM0_A_MARK, +}; + +static const unsigned int pwm0_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 3), +}; + +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; + +/* - PWM1 --------------------------------------------------------------------*/ +static const unsigned int pwm1_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 23), +}; + +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; + +static const unsigned int pwm1_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 4), +}; + +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; + +/* - PWM2 --------------------------------------------------------------------*/ +static const unsigned int pwm2_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; + +static const unsigned int pwm2_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 4), +}; + +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; + +static const unsigned int pwm2_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 5), +}; + +static const unsigned int pwm2_c_mux[] = { + PWM2_C_MARK, +}; + +/* - PWM3 --------------------------------------------------------------------*/ +static const unsigned int pwm3_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 1), +}; + +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; + +static const unsigned int pwm3_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 5), +}; + +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; + +static const unsigned int pwm3_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 6), +}; + +static const unsigned int pwm3_c_mux[] = { + PWM3_C_MARK, +}; + +/* - PWM4 --------------------------------------------------------------------*/ +static const unsigned int pwm4_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 3), +}; + +static const unsigned int pwm4_a_mux[] = { + PWM4_A_MARK, +}; + +static const unsigned int pwm4_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; + +/* - PWM5 --------------------------------------------------------------------*/ +static const unsigned int pwm5_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 24), +}; + +static const unsigned int pwm5_a_mux[] = { + PWM5_A_MARK, +}; + +static const unsigned int pwm5_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 10), +}; + +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; + +/* - PWM6 --------------------------------------------------------------------*/ +static const unsigned int pwm6_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 25), +}; + +static const unsigned int pwm6_a_mux[] = { + PWM6_A_MARK, +}; + +static const unsigned int pwm6_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(6, 11), +}; + +static const unsigned int pwm6_b_mux[] = { + PWM6_B_MARK, +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; + +static const unsigned int scif0_data_a_mux[] = { + RX0_A_MARK, TX0_A_MARK, +}; + +static const unsigned int scif0_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; + +static const unsigned int scif0_clk_a_mux[] = { + SCK0_A_MARK, +}; + +static const unsigned int scif0_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; + +static const unsigned int scif0_ctrl_a_mux[] = { + RTS0_N_TANS_A_MARK, CTS0_N_A_MARK, +}; + +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), +}; + +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; + +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 18), +}; + +static const unsigned int scif0_clk_b_mux[] = { + SCK0_B_MARK, +}; + +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; + +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; + +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 16), +}; + +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; + +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7), +}; + +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; + +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), +}; + +static const unsigned int scif2_data_a_mux[] = { + RX2_A_MARK, TX2_A_MARK, +}; + +static const unsigned int scif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int scif2_clk_a_mux[] = { + SCK2_A_MARK, +}; + +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), +}; + +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; + +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; + +static const unsigned int scif3_data_a_mux[] = { + RX3_A_MARK, TX3_A_MARK, +}; + +static const unsigned int scif3_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 1), +}; + +static const unsigned int scif3_clk_a_mux[] = { + SCK3_A_MARK, +}; + +static const unsigned int scif3_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int scif3_ctrl_a_mux[] = { + RTS3_N_TANS_A_MARK, CTS3_N_A_MARK, +}; + +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; + +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; + +static const unsigned int scif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), +}; + +static const unsigned int scif3_data_c_mux[] = { + RX3_C_MARK, TX3_C_MARK, +}; + +static const unsigned int scif3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 24), +}; + +static const unsigned int scif3_clk_c_mux[] = { + SCK3_C_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; + +static const unsigned int scif4_data_a_mux[] = { + RX4_A_MARK, TX4_A_MARK, +}; + +static const unsigned int scif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 5), +}; + +static const unsigned int scif4_clk_a_mux[] = { + SCK4_A_MARK, +}; + +static const unsigned int scif4_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), +}; + +static const unsigned int scif4_ctrl_a_mux[] = { + RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, +}; + +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), +}; + +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; + +static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; + +static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, +}; + +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; + +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; + +static const unsigned int scif4_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), +}; + +static const unsigned int scif4_ctrl_c_mux[] = { + RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, +}; + +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9), +}; + +static const unsigned int scif5_data_a_mux[] = { + RX5_A_MARK, TX5_A_MARK, +}; + +static const unsigned int scif5_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 13), +}; + +static const unsigned int scif5_clk_a_mux[] = { + SCK5_A_MARK, +}; + +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), +}; + +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; + +static const unsigned int scif5_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; + +static const unsigned int scif5_data_c_mux[] = { + RX5_C_MARK, TX5_C_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(5, 3), +}; + +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; + +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; + +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; + +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; + +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; + +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; + +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; + +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; + +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; + +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; + +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; + +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; + +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; + +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; + +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; + +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; + +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; + +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; + +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; + +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; + +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; + +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; + +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; + +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; + +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; + +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; + +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; + +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; + +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; + +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 10), +}; + +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; + +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 2), +}; + +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; + +static const unsigned int ssi01239_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; + +static const unsigned int ssi01239_ctrl_mux[] = { + SSI_SCK01239_MARK, SSI_WS01239_MARK, +}; + +static const unsigned int ssi1_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 3), +}; + +static const unsigned int ssi1_data_mux[] = { + SSI_SDATA1_MARK, +}; + +static const unsigned int ssi1_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int ssi1_ctrl_mux[] = { + SSI_SCK1_MARK, SSI_WS1_MARK, +}; + +static const unsigned int ssi2_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 4), +}; + +static const unsigned int ssi2_data_mux[] = { + SSI_SDATA2_MARK, +}; + +static const unsigned int ssi2_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; + +static const unsigned int ssi2_ctrl_a_mux[] = { + SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +}; + +static const unsigned int ssi2_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; + +static const unsigned int ssi2_ctrl_b_mux[] = { + SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +}; + +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; + +static const unsigned int ssi349_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +}; + +static const unsigned int ssi349_ctrl_mux[] = { + SSI_SCK349_MARK, SSI_WS349_MARK, +}; + +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 10), +}; + +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; + +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), +}; + +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; + +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; + +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; + +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 16), +}; + +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; + +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; + +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; + +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 12), +}; + +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; + +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), +}; + +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; + +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 13), +}; + +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; + +static const unsigned int ssi9_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 16), +}; + +static const unsigned int ssi9_data_mux[] = { + SSI_SDATA9_MARK, +}; + +static const unsigned int ssi9_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10), +}; + +static const unsigned int ssi9_ctrl_a_mux[] = { + SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +}; + +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; + +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + +/* - TMU -------------------------------------------------------------------- */ +static const unsigned int tmu_tclk1_a_pins[] = { + /* TCLK */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int tmu_tclk1_a_mux[] = { + TCLK1_A_MARK, +}; + +static const unsigned int tmu_tclk1_b_pins[] = { + /* TCLK */ + RCAR_GP_PIN(5, 17), +}; + +static const unsigned int tmu_tclk1_b_mux[] = { + TCLK1_B_MARK, +}; + +static const unsigned int tmu_tclk2_a_pins[] = { + /* TCLK */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int tmu_tclk2_a_mux[] = { + TCLK2_A_MARK, +}; + +static const unsigned int tmu_tclk2_b_pins[] = { + /* TCLK */ + RCAR_GP_PIN(5, 18), +}; + +static const unsigned int tmu_tclk2_b_mux[] = { + TCLK2_B_MARK, +}; + +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_a_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), +}; + +static const unsigned int usb0_a_mux[] = { + USB0_PWEN_A_MARK, USB0_OVC_A_MARK, +}; + +static const unsigned int usb0_b_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int usb0_b_mux[] = { + USB0_PWEN_B_MARK, USB0_OVC_B_MARK, +}; + +static const unsigned int usb0_id_pins[] = { + /* ID */ + RCAR_GP_PIN(5, 0) +}; + +static const unsigned int usb0_id_mux[] = { + USB1_ID_MARK, +}; + +/* - USB30 ------------------------------------------------------------------ */ +static const unsigned int usb30_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), +}; + +static const unsigned int usb30_mux[] = { + USB30_PWEN_MARK, USB30_OVC_MARK, +}; + +static const unsigned int usb30_id_pins[] = { + /* ID */ + RCAR_GP_PIN(5, 0), +}; + +static const unsigned int usb30_id_mux[] = { + USB3HS0_ID_MARK, +}; + +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data8_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), +}; + +static const unsigned int vin4_data8_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, +}; + +static const unsigned int vin4_data10_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), +}; + +static const unsigned int vin4_data10_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, +}; + +static const unsigned int vin4_data12_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; + +static const unsigned int vin4_data12_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, +}; + +static const unsigned int vin4_data16_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int vin4_data16_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; + +static const unsigned int vin4_data20_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), +}; + +static const unsigned int vin4_data20_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, +}; + +static const unsigned int vin4_data24_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), +}; + +static const unsigned int vin4_data24_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const unsigned int vin4_data8_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), +}; + +static const unsigned int vin4_data8_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, +}; + +static const unsigned int vin4_data10_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), +}; + +static const unsigned int vin4_data10_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, +}; + +static const unsigned int vin4_data12_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; + +static const unsigned int vin4_data12_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, +}; + +static const unsigned int vin4_data16_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int vin4_data16_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; + +static const unsigned int vin4_data20_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), +}; + +static const unsigned int vin4_data20_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, +}; + +static const unsigned int vin4_data24_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), +}; + +static const unsigned int vin4_data24_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const unsigned int vin4_data8_sft8_pins[] = { + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int vin4_data8_sft8_mux[] = { + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; + +static const unsigned int vin4_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), +}; + +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; + +static const unsigned int vin4_field_pins[] = { + RCAR_GP_PIN(2, 23), +}; + +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; + +static const unsigned int vin4_clkenb_pins[] = { + RCAR_GP_PIN(1, 2), +}; + +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; + +static const unsigned int vin4_clk_pins[] = { + RCAR_GP_PIN(2, 22), +}; + +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + +/* - VIN5 ------------------------------------------------------------------- */ +static const unsigned int vin5_data8_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), +}; + +static const unsigned int vin5_data8_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, +}; + +static const unsigned int vin5_data8_sft8_a_pins[] = { + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; + +static const unsigned int vin5_data8_sft8_a_mux[] = { + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, +}; + +static const unsigned int vin5_data10_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; + +static const unsigned int vin5_data10_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, +}; + +static const unsigned int vin5_data12_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), +}; + +static const unsigned int vin5_data12_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, +}; + +static const unsigned int vin5_data16_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; + +static const unsigned int vin5_data16_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, +}; + +static const unsigned int vin5_data8_b_pins[] = { + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4), + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12), + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), +}; + +static const unsigned int vin5_data8_b_mux[] = { + VI5_DATA0_B_MARK, VI5_DATA1_B_MARK, + VI5_DATA2_B_MARK, VI5_DATA3_B_MARK, + VI5_DATA4_B_MARK, VI5_DATA5_B_MARK, + VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, +}; + +static const unsigned int vin5_sync_a_pins[] = { + /* HSYNC_N, VSYNC_N */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), +}; + +static const unsigned int vin5_sync_a_mux[] = { + VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK, +}; + +static const unsigned int vin5_field_a_pins[] = { + RCAR_GP_PIN(1, 10), +}; + +static const unsigned int vin5_field_a_mux[] = { + VI5_FIELD_A_MARK, +}; + +static const unsigned int vin5_clkenb_a_pins[] = { + RCAR_GP_PIN(0, 1), +}; + +static const unsigned int vin5_clkenb_a_mux[] = { + VI5_CLKENB_A_MARK, +}; + +static const unsigned int vin5_clk_a_pins[] = { + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int vin5_clk_a_mux[] = { + VI5_CLK_A_MARK, +}; + +static const unsigned int vin5_clk_b_pins[] = { + RCAR_GP_PIN(2, 22), +}; + +static const unsigned int vin5_clk_b_mux[] = { + VI5_CLK_B_MARK, }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_b_c), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clk_c_c), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout1_c), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout2_c), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), + SH_PFC_PIN_GROUP(audio_clkout3_c), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), + SH_PFC_PIN_GROUP(drif0_ctrl_b), + SH_PFC_PIN_GROUP(drif0_data0_b), + SH_PFC_PIN_GROUP(drif0_data1_b), + SH_PFC_PIN_GROUP(drif1_ctrl), + SH_PFC_PIN_GROUP(drif1_data0), + SH_PFC_PIN_GROUP(drif1_data1), + SH_PFC_PIN_GROUP(drif2_ctrl_a), + SH_PFC_PIN_GROUP(drif2_data0_a), + SH_PFC_PIN_GROUP(drif2_data1_a), + SH_PFC_PIN_GROUP(drif2_ctrl_b), + SH_PFC_PIN_GROUP(drif2_data0_b), + SH_PFC_PIN_GROUP(drif2_data1_b), + SH_PFC_PIN_GROUP(drif3_ctrl_a), + SH_PFC_PIN_GROUP(drif3_data0_a), + SH_PFC_PIN_GROUP(drif3_data1_a), + SH_PFC_PIN_GROUP(drif3_ctrl_b), + SH_PFC_PIN_GROUP(drif3_data0_b), + SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(du_disp_cde), + SH_PFC_PIN_GROUP(du_clk_in_0), + SH_PFC_PIN_GROUP(du_clk_in_1), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_clk_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_clk_b), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_clk_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_clk_c), + SH_PFC_PIN_GROUP(hscif3_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif3_data_e), + SH_PFC_PIN_GROUP(hscif3_ctrl_e), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk_a), + SH_PFC_PIN_GROUP(hscif4_ctrl_a), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(hscif4_clk_b), + SH_PFC_PIN_GROUP(hscif4_data_c), + SH_PFC_PIN_GROUP(hscif4_data_d), + SH_PFC_PIN_GROUP(hscif4_data_e), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c7_a), + SH_PFC_PIN_GROUP(i2c7_b), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(pwm0_a), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm2_c), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm3_c), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_clk_a), + SH_PFC_PIN_GROUP(scif0_ctrl_a), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_clk_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk_a), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk_a), + SH_PFC_PIN_GROUP(scif3_ctrl_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_clk_c), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_ctrl_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_ctrl_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_data_c), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(usb0_a), + SH_PFC_PIN_GROUP(usb0_b), + SH_PFC_PIN_GROUP(usb0_id), + SH_PFC_PIN_GROUP(usb30), + SH_PFC_PIN_GROUP(usb30_id), + SH_PFC_PIN_GROUP(vin4_data8_a), + SH_PFC_PIN_GROUP(vin4_data10_a), + SH_PFC_PIN_GROUP(vin4_data12_a), + SH_PFC_PIN_GROUP(vin4_data16_a), + SH_PFC_PIN_GROUP(vin4_data20_a), + SH_PFC_PIN_GROUP(vin4_data24_a), + SH_PFC_PIN_GROUP(vin4_data8_b), + SH_PFC_PIN_GROUP(vin4_data10_b), + SH_PFC_PIN_GROUP(vin4_data12_b), + SH_PFC_PIN_GROUP(vin4_data16_b), + SH_PFC_PIN_GROUP(vin4_data20_b), + SH_PFC_PIN_GROUP(vin4_data24_b), + SH_PFC_PIN_GROUP(vin4_data8_sft8), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + SH_PFC_PIN_GROUP(vin5_data8_a), + SH_PFC_PIN_GROUP(vin5_data8_sft8_a), + SH_PFC_PIN_GROUP(vin5_data10_a), + SH_PFC_PIN_GROUP(vin5_data12_a), + SH_PFC_PIN_GROUP(vin5_data16_a), + SH_PFC_PIN_GROUP(vin5_data8_b), + SH_PFC_PIN_GROUP(vin5_sync_a), + SH_PFC_PIN_GROUP(vin5_field_a), + SH_PFC_PIN_GROUP(vin5_clkenb_a), + SH_PFC_PIN_GROUP(vin5_clk_a), + SH_PFC_PIN_GROUP(vin5_clk_b), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b_a", + "audio_clk_b_b", + "audio_clk_b_c", + "audio_clk_c_a", + "audio_clk_c_b", + "audio_clk_c_c", + "audio_clkout_a", + "audio_clkout_b", + "audio_clkout1_a", + "audio_clkout1_b", + "audio_clkout1_c", + "audio_clkout2_a", + "audio_clkout2_b", + "audio_clkout2_c", + "audio_clkout3_a", + "audio_clkout3_b", + "audio_clkout3_c", +}; + +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mii", + "avb_avtp_pps", + "avb_avtp_match_a", + "avb_avtp_capture_a", +}; + +static const char * const can0_groups[] = { + "can0_data", +}; + +static const char * const can1_groups[] = { + "can1_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + +static const char * const drif0_groups[] = { + "drif0_ctrl_a", + "drif0_data0_a", + "drif0_data1_a", + "drif0_ctrl_b", + "drif0_data0_b", + "drif0_data1_b", +}; + +static const char * const drif1_groups[] = { + "drif1_ctrl", + "drif1_data0", + "drif1_data1", +}; + +static const char * const drif2_groups[] = { + "drif2_ctrl_a", + "drif2_data0_a", + "drif2_data1_a", + "drif2_ctrl_b", + "drif2_data0_b", + "drif2_data1_b", +}; + +static const char * const drif3_groups[] = { + "drif3_ctrl_a", + "drif3_data0_a", + "drif3_data1_a", + "drif3_ctrl_b", + "drif3_data0_b", + "drif3_data1_b", +}; + +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_out_0", + "du_sync", + "du_cde", + "du_disp", + "du_disp_cde", + "du_clk_in_0", + "du_clk_in_1", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_clk_a", + "hscif0_ctrl_a", + "hscif0_data_b", + "hscif0_clk_b", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_data_b", + "hscif3_clk_b", + "hscif3_data_c", + "hscif3_clk_c", + "hscif3_ctrl_c", + "hscif3_data_d", + "hscif3_data_e", + "hscif3_ctrl_e", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk_a", + "hscif4_ctrl_a", + "hscif4_data_b", + "hscif4_clk_b", + "hscif4_data_c", + "hscif4_data_d", + "hscif4_data_e", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", + "i2c1_c", + "i2c1_d", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", + "i2c2_c", + "i2c2_d", + "i2c2_e", +}; + +static const char * const i2c4_groups[] = { + "i2c4", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + +static const char * const i2c6_groups[] = { + "i2c6_a", + "i2c6_b", +}; + +static const char * const i2c7_groups[] = { + "i2c7_a", + "i2c7_b", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk_a", + "msiof2_sync_a", + "msiof2_ss1_a", + "msiof2_ss2_a", + "msiof2_txd_a", + "msiof2_rxd_a", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_txd_b", + "msiof2_rxd_b", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_txd_b", + "msiof3_rxd_b", +}; + +static const char * const pwm0_groups[] = { + "pwm0_a", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", + "pwm2_c", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", + "pwm3_c", +}; + +static const char * const pwm4_groups[] = { + "pwm4_a", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5_a", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6_a", + "pwm6_b", +}; + +static const char * const scif0_groups[] = { + "scif0_data_a", + "scif0_clk_a", + "scif0_ctrl_a", + "scif0_data_b", + "scif0_clk_b", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_clk_a", + "scif2_data_b", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_clk_a", + "scif3_ctrl_a", + "scif3_data_b", + "scif3_data_c", + "scif3_clk_c", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_clk_a", + "scif4_ctrl_a", + "scif4_data_b", + "scif4_clk_b", + "scif4_data_c", + "scif4_ctrl_c", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_clk_a", + "scif5_data_b", + "scif5_data_c", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk_a", + "scif_clk_b", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi01239_ctrl", + "ssi1_data", + "ssi1_ctrl", + "ssi2_data", + "ssi2_ctrl_a", + "ssi2_ctrl_b", + "ssi3_data", + "ssi349_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi78_ctrl", + "ssi8_data", + "ssi9_data", + "ssi9_ctrl_a", + "ssi9_ctrl_b", +}; + +static const char * const tmu_groups[] = { + "tmu_tclk1_a", + "tmu_tclk1_b", + "tmu_tclk2_a", + "tmu_tclk2_b", +}; + +static const char * const usb0_groups[] = { + "usb0_a", + "usb0_b", + "usb0_id", +}; + +static const char * const usb30_groups[] = { + "usb30", + "usb30_id", +}; + +static const char * const vin4_groups[] = { + "vin4_data8_a", + "vin4_data10_a", + "vin4_data12_a", + "vin4_data16_a", + "vin4_data20_a", + "vin4_data24_a", + "vin4_data8_b", + "vin4_data10_b", + "vin4_data12_b", + "vin4_data16_b", + "vin4_data20_b", + "vin4_data24_b", + "vin4_data8_sft8", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data8_a", + "vin5_data8_sft8_a", + "vin5_data10_a", + "vin5_data12_a", + "vin5_data16_a", + "vin5_data8_b", + "vin5_sync_a", + "vin5_field_a", + "vin5_clkenb_a", + "vin5_clk_a", + "vin5_clk_b", }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), + SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(i2c7), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 19009092bdb..97f75a184e4 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -198,8 +198,8 @@ #define GPSR6_0 FM(QSPI0_SPCLK) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ -#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -518,14 +518,14 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(QSPI0_MISO_IO1), PINMUX_SINGLE(QSPI0_MOSI_IO0), PINMUX_SINGLE(QSPI0_SPCLK), + PINMUX_SINGLE(SCL0), + PINMUX_SINGLE(SDA0), /* IPSR0 */ PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), - PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN), PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), - PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU), PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), @@ -936,6 +936,265 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - AUDIO CLOCK ------------------------------------------------------------- */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(4, 1), +}; +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; +static const unsigned int audio_clk_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int audio_clk_b_mux[] = { + AUDIO_CLKB_MARK, +}; +static const unsigned int audio_clkout_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, +}; +static const unsigned int audio_clkout1_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int audio_clkout1_mux[] = { + AUDIO_CLKOUT1_MARK, +}; + +/* - EtherAVB --------------------------------------------------------------- */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, +}; +static const unsigned int avb0_magic_pins[] = { + /* AVB0_MAGIC */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int avb0_magic_mux[] = { + AVB0_MAGIC_MARK, +}; +static const unsigned int avb0_phy_int_pins[] = { + /* AVB0_PHY_INT */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int avb0_phy_int_mux[] = { + AVB0_PHY_INT_MARK, +}; +static const unsigned int avb0_mdio_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16), +}; +static const unsigned int avb0_mdio_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_mii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, + * AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, + * AVB0_RD1, AVB0_RD2, AVB0_RD3, + * AVB0_TXCREFCLK + */ + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 15), +}; +static const unsigned int avb0_mii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK, + AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK, + AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, + AVB0_TXCREFCLK_MARK, +}; +static const unsigned int avb0_avtp_pps_a_pins[] = { + /* AVB0_AVTP_PPS_A */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int avb0_avtp_pps_a_mux[] = { + AVB0_AVTP_PPS_A_MARK, +}; +static const unsigned int avb0_avtp_match_a_pins[] = { + /* AVB0_AVTP_MATCH_A */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int avb0_avtp_match_a_mux[] = { + AVB0_AVTP_MATCH_A_MARK, +}; +static const unsigned int avb0_avtp_capture_a_pins[] = { + /* AVB0_AVTP_CAPTURE_A */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int avb0_avtp_capture_a_mux[] = { + AVB0_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int avb0_avtp_pps_b_pins[] = { + /* AVB0_AVTP_PPS_B */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int avb0_avtp_pps_b_mux[] = { + AVB0_AVTP_PPS_B_MARK, +}; +static const unsigned int avb0_avtp_match_b_pins[] = { + /* AVB0_AVTP_MATCH_B */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int avb0_avtp_match_b_mux[] = { + AVB0_AVTP_MATCH_B_MARK, +}; +static const unsigned int avb0_avtp_capture_b_pins[] = { + /* AVB0_AVTP_CAPTURE_B */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int avb0_avtp_capture_b_mux[] = { + AVB0_AVTP_CAPTURE_B_MARK, +}; + +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), +}; +static const unsigned int can0_data_a_mux[] = { + CAN0_TX_A_MARK, CAN0_RX_A_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; +static const unsigned int can1_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), +}; +static const unsigned int can1_data_a_mux[] = { + CAN1_TX_A_MARK, CAN1_RX_A_MARK, +}; +static const unsigned int can1_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), +}; +static const unsigned int can1_data_b_mux[] = { + CAN1_TX_B_MARK, CAN1_RX_B_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD ----------------------------------------------------------------- */ +static const unsigned int canfd0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), +}; +static const unsigned int canfd0_data_mux[] = { + CANFD0_TX_MARK, CANFD0_RX_MARK, +}; +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int du_rgb666_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, +}; +static const unsigned int du_clk_in_1_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int du_clk_in_1_mux[] = { + DU_DOTCLKIN1_MARK +}; +static const unsigned int du_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int du_clk_out_0_mux[] = { + DU_DOTCLKOUT0_MARK +}; +static const unsigned int du_sync_pins[] = { + /* VSYNC, HSYNC */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int du_sync_mux[] = { + DU_VSYNC_MARK, DU_HSYNC_MARK +}; +static const unsigned int du_disp_cde_pins[] = { + /* DISP_CDE */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int du_disp_cde_mux[] = { + DU_DISP_CDE_MARK, +}; +static const unsigned int du_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int du_cde_mux[] = { + DU_CDE_MARK, +}; +static const unsigned int du_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int du_disp_mux[] = { + DU_DISP_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SCL, SDA */ @@ -1018,6 +1277,118 @@ static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; +/* - PWM0 ------------------------------------------------------------------ */ +static const unsigned int pwm0_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 1), +}; + +static const unsigned int pwm0_a_mux[] = { + PWM0_A_MARK, +}; + +static const unsigned int pwm0_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 18), +}; + +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; + +static const unsigned int pwm0_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 29), +}; + +static const unsigned int pwm0_c_mux[] = { + PWM0_C_MARK, +}; + +/* - PWM1 ------------------------------------------------------------------ */ +static const unsigned int pwm1_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 2), +}; + +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; + +static const unsigned int pwm1_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 19), +}; + +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; + +static const unsigned int pwm1_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 30), +}; + +static const unsigned int pwm1_c_mux[] = { + PWM1_C_MARK, +}; + +/* - PWM2 ------------------------------------------------------------------ */ +static const unsigned int pwm2_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 3), +}; + +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; + +static const unsigned int pwm2_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 22), +}; + +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; + +static const unsigned int pwm2_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 31), +}; + +static const unsigned int pwm2_c_mux[] = { + PWM2_C_MARK, +}; + +/* - PWM3 ------------------------------------------------------------------ */ +static const unsigned int pwm3_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 4), +}; + +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; + +static const unsigned int pwm3_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 27), +}; + +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; + +static const unsigned int pwm3_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(4, 0), +}; + +static const unsigned int pwm3_c_mux[] = { + PWM3_C_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -1202,7 +1573,175 @@ static const unsigned int scif_clk_mux[] = { SCIF_CLK_MARK, }; +/* - SSI ---------------------------------------------------------------*/ +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(4, 3), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; +static const unsigned int ssi34_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4), +}; +static const unsigned int ssi34_ctrl_mux[] = { + SSI_SCK34_MARK, SSI_WS34_MARK, +}; +static const unsigned int ssi4_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), +}; +static const unsigned int ssi4_ctrl_a_mux[] = { + SSI_SCK4_A_MARK, SSI_WS4_A_MARK, +}; +static const unsigned int ssi4_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int ssi4_data_a_mux[] = { + SSI_SDATA4_A_MARK, +}; +static const unsigned int ssi4_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20), +}; +static const unsigned int ssi4_ctrl_b_mux[] = { + SSI_SCK4_B_MARK, SSI_WS4_B_MARK, +}; +static const unsigned int ssi4_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int ssi4_data_b_mux[] = { + SSI_SDATA4_B_MARK, +}; + +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, USB0_OVC_MARK, +}; + +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data18_pins[] = { + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), +}; +static const unsigned int vin4_data18_mux[] = { + VI4_DATA2_MARK, VI4_DATA3_MARK, + VI4_DATA4_MARK, VI4_DATA5_MARK, + VI4_DATA6_MARK, VI4_DATA7_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const union vin_data vin4_data_pins = { + .data24 = { + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), + }, +}; +static const union vin_data vin4_data_mux = { + .data24 = { + VI4_DATA0_MARK, VI4_DATA1_MARK, + VI4_DATA2_MARK, VI4_DATA3_MARK, + VI4_DATA4_MARK, VI4_DATA5_MARK, + VI4_DATA6_MARK, VI4_DATA7_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; +static const unsigned int vin4_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), +}; +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; +static const unsigned int vin4_field_pins[] = { + /* FIELD */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; +static const unsigned int vin4_clkenb_pins[] = { + /* CLKENB */ + RCAR_GP_PIN(2, 28), +}; +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; +static const unsigned int vin4_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout1), + SH_PFC_PIN_GROUP(avb0_link), + SH_PFC_PIN_GROUP(avb0_magic), + SH_PFC_PIN_GROUP(avb0_phy_int), + SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_mii), + SH_PFC_PIN_GROUP(avb0_avtp_pps_a), + SH_PFC_PIN_GROUP(avb0_avtp_match_a), + SH_PFC_PIN_GROUP(avb0_avtp_capture_a), + SH_PFC_PIN_GROUP(avb0_avtp_pps_b), + SH_PFC_PIN_GROUP(avb0_avtp_match_b), + SH_PFC_PIN_GROUP(avb0_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data_a), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_in_1), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_disp_cde), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), SH_PFC_PIN_GROUP(i2c2_a), @@ -1213,6 +1752,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(pwm0_a), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm0_c), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm1_c), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm2_c), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm3_c), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_data_b), @@ -1238,6 +1789,76 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_ctrl_a), + SH_PFC_PIN_GROUP(ssi4_data_a), + SH_PFC_PIN_GROUP(ssi4_ctrl_b), + SH_PFC_PIN_GROUP(ssi4_data_b), + SH_PFC_PIN_GROUP(usb0), + VIN_DATA_PIN_GROUP(vin4_data, 8), + VIN_DATA_PIN_GROUP(vin4_data, 10), + VIN_DATA_PIN_GROUP(vin4_data, 12), + VIN_DATA_PIN_GROUP(vin4_data, 16), + SH_PFC_PIN_GROUP(vin4_data18), + VIN_DATA_PIN_GROUP(vin4_data, 20), + VIN_DATA_PIN_GROUP(vin4_data, 24), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", + "audio_clkout", + "audio_clkout1", +}; + +static const char * const avb0_groups[] = { + "avb0_link", + "avb0_magic", + "avb0_phy_int", + "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */ + "avb0_mdio", + "avb0_mii", + "avb0_avtp_pps_a", + "avb0_avtp_match_a", + "avb0_avtp_capture_a", + "avb0_avtp_pps_b", + "avb0_avtp_match_b", + "avb0_avtp_capture_b", +}; + +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", +}; +static const char * const can1_groups[] = { + "can1_data_a", + "can1_data_b", +}; +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data", +}; +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_in_1", + "du_clk_out_0", + "du_sync", + "du_disp_cde", + "du_cde", + "du_disp", }; static const char * const i2c0_groups[] = { @@ -1264,6 +1885,30 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const pwm0_groups[] = { + "pwm0_a", + "pwm0_b", + "pwm0_c", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", + "pwm1_c", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", + "pwm2_c", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", + "pwm3_c", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -1310,12 +1955,51 @@ static const char * const scif_clk_groups[] = { "scif_clk", }; +static const char * const ssi_groups[] = { + "ssi3_data", + "ssi34_ctrl", + "ssi4_ctrl_a", + "ssi4_data_a", + "ssi4_ctrl_b", + "ssi4_data_b", +}; + +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const vin4_groups[] = { + "vin4_data8", + "vin4_data10", + "vin4_data12", + "vin4_data16", + "vin4_data18", + "vin4_data20", + "vin4_data24", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb0), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -1323,6 +2007,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(vin4), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 01a027f6636..90011537a85 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -119,12 +119,12 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, BUG(); } -u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width) +u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) { - return sh_pfc_read_raw_reg(pfc->regs + reg, width); + return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32); } -void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) +void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) { void __iomem *unlock_reg = (void __iomem *)(uintptr_t)pfc->info->unlock_reg; @@ -132,7 +132,7 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) if (pfc->info->unlock_reg) sh_pfc_write_raw_reg(unlock_reg, 32, ~data); - sh_pfc_write_raw_reg(pfc->regs + reg, width, data); + sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data); } static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, @@ -334,17 +334,22 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) return 0; } -const struct sh_pfc_bias_info * -sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, - unsigned int num, unsigned int pin) +const struct pinmux_bias_reg * +sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *bit) { - unsigned int i; + unsigned int i, j; - for (i = 0; i < num; i++) - if (info[i].pin == pin) - return &info[i]; + for (i = 0; pfc->info->bias_regs[i].puen; i++) { + for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { + if (pfc->info->bias_regs[i].pins[j] == pin) { + *bit = j; + return &pfc->info->bias_regs[i]; + } + } + } - printf("Pin %u is not in bias info list\n", pin); + WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); return NULL; } diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index f4060096e22..b98c2f185d2 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -36,13 +36,14 @@ struct sh_pfc_pin { unsigned int configs; }; -#define SH_PFC_PIN_GROUP(n) \ +#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ { \ - .name = #n, \ + .name = #alias, \ .pins = n##_pins, \ .mux = n##_mux, \ .nr_pins = ARRAY_SIZE(n##_pins), \ } +#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) struct sh_pfc_pin_group { const char *name; @@ -145,6 +146,21 @@ struct pinmux_drive_reg { .reg = r, \ .fields = +struct pinmux_bias_reg { + u32 puen; /* Pull-enable or pull-up control register */ + u32 pud; /* Pull-up/down control register (optional) */ + const u16 pins[32]; +}; + +#define PINMUX_BIAS_REG(name1, r1, name2, r2) \ + .puen = r1, \ + .pud = r2, \ + .pins = + +struct pinmux_ioctrl_reg { + u32 reg; +}; + struct pinmux_data_reg { u32 reg; u8 reg_width; @@ -180,10 +196,10 @@ struct pinmux_range { u16 force; }; -struct sh_pfc_bias_info { - u16 pin; - u16 reg : 11; - u16 bit : 5; +struct sh_pfc_window { + phys_addr_t phys; + void __iomem *virt; + unsigned long size; }; struct sh_pfc_pin_range; @@ -227,6 +243,8 @@ struct sh_pfc_soc_info { const struct pinmux_cfg_reg *cfg_regs; const struct pinmux_drive_reg *drive_regs; + const struct pinmux_bias_reg *bias_regs; + const struct pinmux_ioctrl_reg *ioctrl_regs; const struct pinmux_data_reg *data_regs; const u16 *pinmux_data; @@ -238,11 +256,11 @@ struct sh_pfc_soc_info { u32 unlock_reg; }; -u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width); -void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data); -const struct sh_pfc_bias_info * -sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, - unsigned int num, unsigned int pin); +u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); +void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); +const struct pinmux_bias_reg * +sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *bit); int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector); extern const struct sh_pfc_soc_info r8a7790_pinmux_info; @@ -348,13 +366,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ PORT_GP_CFG_4(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) + PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ - PORT_GP_CFG_4(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ + PORT_GP_CFG_6(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) @@ -375,7 +392,8 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ - PORT_GP_CFG_11(bank, fn, sfx, cfg), \ + PORT_GP_CFG_10(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) @@ -417,14 +435,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ - PORT_GP_CFG_18(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) + PORT_GP_CFG_21(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ - PORT_GP_CFG_21(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ + PORT_GP_CFG_22(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) @@ -433,9 +449,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) -#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ PORT_GP_CFG_24(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) +#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) + +#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ + PORT_GP_CFG_25(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) diff --git a/drivers/power/pmic/pfuze100.c b/drivers/power/pmic/pfuze100.c index 4670a84560e..8a5a8996b43 100644 --- a/drivers/power/pmic/pfuze100.c +++ b/drivers/power/pmic/pfuze100.c @@ -12,6 +12,7 @@ #include <power/pmic.h> #include <power/regulator.h> #include <power/pfuze100_pmic.h> +#include <power/pfuze3000_pmic.h> static const struct pmic_child_info pmic_children_info[] = { /* sw[x], swbst */ @@ -23,7 +24,7 @@ static const struct pmic_child_info pmic_children_info[] = { static int pfuze100_reg_count(struct udevice *dev) { - return PFUZE100_NUM_OF_REGS; + return dev->driver_data == PFUZE3000 ? PFUZE3000_NUM_OF_REGS : PFUZE100_NUM_OF_REGS; } static int pfuze100_write(struct udevice *dev, uint reg, const uint8_t *buff, diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c index f2a51fe4a49..1077fa5e9d9 100644 --- a/drivers/power/pmic/pmic_pfuze3000.c +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -22,7 +22,7 @@ int power_pfuze3000_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; + p->number_of_regs = PFUZE3000_NUM_OF_REGS; p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 657243ae620..39d684be4a1 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -71,7 +71,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */ UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */ - UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */ + UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ @@ -85,10 +85,13 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */ UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */ UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ - UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */ - UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */ - UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY */ - UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY */ + UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */ + UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */ + UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */ + UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */ + UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ + UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ + UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ UNIPHIER_RESET_END, }; diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 8878079666d..c7f46e55981 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <linux/bug.h> #include <linux/io.h> #include <linux/serial_reg.h> #include <linux/sizes.h> @@ -33,17 +34,17 @@ struct uniphier_serial { u32 dlr; /* Divisor Latch Register */ }; -struct uniphier_serial_private_data { +struct uniphier_serial_priv { struct uniphier_serial __iomem *membase; unsigned int uartclk; }; #define uniphier_serial_port(dev) \ - ((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase + ((struct uniphier_serial_priv *)dev_get_priv(dev))->membase static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) { - struct uniphier_serial_private_data *priv = dev_get_priv(dev); + struct uniphier_serial_priv *priv = dev_get_priv(dev); struct uniphier_serial __iomem *port = uniphier_serial_port(dev); const unsigned int mode_x_div = 16; unsigned int divisor; @@ -87,11 +88,34 @@ static int uniphier_serial_pending(struct udevice *dev, bool input) return !(readl(&port->lsr) & UART_LSR_THRE); } +/* + * SPL does not have enough memory footprint for the clock driver. + * Hardcode clock frequency for each SoC. + */ +struct uniphier_serial_clk_data { + const char *compatible; + unsigned int clk_rate; +}; + +static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = { + { .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 }, + { .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 }, + { .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 }, + { .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 }, + { .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 }, + { .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 }, + { .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 }, + { .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 }, + { .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 }, + { /* sentinel */ }, +}; + static int uniphier_serial_probe(struct udevice *dev) { - DECLARE_GLOBAL_DATA_PTR; - struct uniphier_serial_private_data *priv = dev_get_priv(dev); + struct uniphier_serial_priv *priv = dev_get_priv(dev); struct uniphier_serial __iomem *port; + const struct uniphier_serial_clk_data *clk_data; + ofnode root_node; fdt_addr_t base; u32 tmp; @@ -105,8 +129,19 @@ static int uniphier_serial_probe(struct udevice *dev) priv->membase = port; - priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + root_node = ofnode_path("/"); + clk_data = uniphier_serial_clk_data; + while (clk_data->compatible) { + if (ofnode_device_is_compatible(root_node, + clk_data->compatible)) + break; + clk_data++; + } + + if (WARN_ON(!clk_data->compatible)) + return -ENOTSUPP; + + priv->uartclk = clk_data->clk_rate; tmp = readl(&port->lcr_mcr); tmp &= ~LCR_MASK; @@ -133,6 +168,6 @@ U_BOOT_DRIVER(uniphier_serial) = { .id = UCLASS_SERIAL, .of_match = uniphier_uart_of_match, .probe = uniphier_serial_probe, - .priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data), + .priv_auto_alloc_size = sizeof(struct uniphier_serial_priv), .ops = &uniphier_serial_ops, }; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index b77129cc317..0dccc38b82d 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -60,7 +60,7 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) { if (CONFIG_IS_ENABLED(DM_SPI)) { - dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol); + dm_gpio_set_value(&mxcs->ss, 1); } else { if (mxcs->gpio > 0) gpio_set_value(mxcs->gpio, mxcs->ss_pol); @@ -70,7 +70,7 @@ static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs) { if (CONFIG_IS_ENABLED(DM_SPI)) { - dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol)); + dm_gpio_set_value(&mxcs->ss, 0); } else { if (mxcs->gpio > 0) gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); @@ -504,11 +504,11 @@ static int mxc_spi_probe(struct udevice *bus) return -EINVAL; } - plat->base = dev_get_addr(bus); + plat->base = devfdt_get_addr(bus); if (plat->base == FDT_ADDR_T_NONE) return -ENODEV; - ret = dm_gpio_set_value(&plat->ss, !(mxcs->ss_pol)); + ret = dm_gpio_set_value(&plat->ss, 0); if (ret) { dev_err(bus, "Setting cs error\n"); return ret; diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 4169abdef67..ecf54bb7148 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -443,9 +443,6 @@ static void spi_reset(struct mcspi *regs) static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) { unsigned int conf; - - spi_reset(priv->regs); - /* * setup when switching from (reset default) slave mode * to single-channel master mode @@ -480,6 +477,8 @@ int spi_claim_bus(struct spi_slave *slave) { struct omap3_spi_priv *priv = to_omap3_spi(slave); + spi_reset(priv->regs); + _omap3_spi_claim_bus(priv); _omap3_spi_set_wordlen(priv); _omap3_spi_set_mode(priv); @@ -492,8 +491,7 @@ void spi_release_bus(struct spi_slave *slave) { struct omap3_spi_priv *priv = to_omap3_spi(slave); - /* Reset the SPI hardware */ - spi_reset(priv->regs); + writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); } struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, @@ -590,6 +588,8 @@ static int omap3_spi_claim_bus(struct udevice *dev) struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); priv->cs = slave_plat->cs; + priv->freq = slave_plat->max_hz; + _omap3_spi_claim_bus(priv); return 0; @@ -600,8 +600,7 @@ static int omap3_spi_release_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct omap3_spi_priv *priv = dev_get_priv(bus); - /* Reset the SPI hardware */ - spi_reset(priv->regs); + writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); return 0; } @@ -634,6 +633,9 @@ static int omap3_spi_probe(struct udevice *dev) else priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; priv->wordlen = SPI_DEFAULT_WORDLEN; + + spi_reset(priv->regs); + return 0; } @@ -648,12 +650,10 @@ static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen, static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed) { - struct udevice *bus = dev->parent; - struct omap3_spi_priv *priv = dev_get_priv(bus); - struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); - priv->cs = slave_plat->cs; - priv->freq = slave_plat->max_hz; + struct omap3_spi_priv *priv = dev_get_priv(dev); + + priv->freq = speed; _omap3_spi_set_speed(priv); return 0; @@ -661,12 +661,10 @@ static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed) static int omap3_spi_set_mode(struct udevice *dev, uint mode) { - struct udevice *bus = dev->parent; - struct omap3_spi_priv *priv = dev_get_priv(bus); - struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct omap3_spi_priv *priv = dev_get_priv(dev); + + priv->mode = mode; - priv->cs = slave_plat->cs; - priv->mode = slave_plat->mode; _omap3_spi_set_mode(priv); return 0; diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index ee8796d470b..9ad1927a5d5 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -486,7 +486,7 @@ static int zynq_qspi_transfer(struct zynq_qspi_priv *priv) break; } - return 0; + return status; } static int zynq_qspi_claim_bus(struct udevice *dev) diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index cf869998bf9..747f190d384 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -377,14 +377,23 @@ static int tsc_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - tsc_timer_ensure_setup(); - uc_priv->clock_rate = gd->arch.clock_rate; + if (!uc_priv->clock_rate) { + tsc_timer_ensure_setup(); + uc_priv->clock_rate = gd->arch.clock_rate; + } else { + gd->arch.tsc_base = rdtsc(); + } return 0; } unsigned long notrace timer_early_get_rate(void) { + /* + * When TSC timer is used as the early timer, be warned that the timer + * clock rate can only be calibrated via some hardware ways. Specifying + * it in the device tree won't work for the early timer. + */ tsc_timer_ensure_setup(); return gd->arch.clock_rate; diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c index c5ff3797cfb..e8ee6650bc4 100644 --- a/drivers/usb/eth/lan78xx.c +++ b/drivers/usb/eth/lan78xx.c @@ -296,7 +296,7 @@ static int lan78xx_basic_reset(struct usb_device *udev, ret = lan7x_read_reg(udev, LAN78XX_USB_CFG0, &val); if (ret) return ret; - val |= LAN78XX_USB_CFG0_BIR; + val &= ~LAN78XX_USB_CFG0_BIR; return lan7x_write_reg(udev, LAN78XX_USB_CFG0, val); } diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 360efc91160..7a79931a979 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -17,16 +17,29 @@ #include <generic-phy.h> #ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 #define AHB_CLK_DIST 2 #else +#define BASE_DIST 0x1000 #define AHB_CLK_DIST 1 #endif +#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0 +#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0 + +struct ehci_sunxi_cfg { + bool has_reset; + u32 extra_ahb_gate_mask; + u32 reset0_cfg_offset; +}; + struct ehci_sunxi_priv { struct ehci_ctrl ehci; struct sunxi_ccm_reg *ccm; + u32 *reset0_cfg; int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ struct phy phy; + const struct ehci_sunxi_cfg *cfg; }; static int ehci_usb_probe(struct udevice *dev) @@ -36,12 +49,17 @@ static int ehci_usb_probe(struct udevice *dev) struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev); struct ehci_hcor *hcor; int extra_ahb_gate_mask = 0; + u8 reg_mask = 0; int phys, ret; + priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev); priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (IS_ERR(priv->ccm)) return PTR_ERR(priv->ccm); + priv->reset0_cfg = (void *)priv->ccm + + priv->cfg->reset0_cfg_offset; + phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); if (phys < 0) { phys = 0; @@ -71,19 +89,17 @@ no_phy: * This should go away once we've moved to the driver model for * clocks resp. phys. */ + reg_mask = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) - extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; -#endif - priv->ahb_gate_mask <<= phys * AHB_CLK_DIST; - extra_ahb_gate_mask <<= phys * AHB_CLK_DIST; + extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; + priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; + extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; setbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&priv->ccm->ahb_reset0_cfg, - priv->ahb_gate_mask | extra_ahb_gate_mask); -#endif + if (priv->cfg->has_reset) + setbits_le32(priv->reset0_cfg, + priv->ahb_gate_mask | extra_ahb_gate_mask); hcor = (struct ehci_hcor *)((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); @@ -108,25 +124,71 @@ static int ehci_usb_remove(struct udevice *dev) if (ret) return ret; -#ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask); -#endif + if (priv->cfg->has_reset) + clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask); clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); return 0; } +static const struct ehci_sunxi_cfg sun4i_a10_cfg = { + .has_reset = false, +}; + +static const struct ehci_sunxi_cfg sun6i_a31_cfg = { + .has_reset = true, + .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, +}; + +static const struct ehci_sunxi_cfg sun8i_h3_cfg = { + .has_reset = true, + .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0, + .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, +}; + +static const struct ehci_sunxi_cfg sun9i_a80_cfg = { + .has_reset = true, + .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET, +}; + static const struct udevice_id ehci_usb_ids[] = { - { .compatible = "allwinner,sun4i-a10-ehci", }, - { .compatible = "allwinner,sun5i-a13-ehci", }, - { .compatible = "allwinner,sun6i-a31-ehci", }, - { .compatible = "allwinner,sun7i-a20-ehci", }, - { .compatible = "allwinner,sun8i-a23-ehci", }, - { .compatible = "allwinner,sun8i-a83t-ehci", }, - { .compatible = "allwinner,sun8i-h3-ehci", }, - { .compatible = "allwinner,sun9i-a80-ehci", }, - { .compatible = "allwinner,sun50i-a64-ehci", }, - { } + { + .compatible = "allwinner,sun4i-a10-ehci", + .data = (ulong)&sun4i_a10_cfg, + }, + { + .compatible = "allwinner,sun5i-a13-ehci", + .data = (ulong)&sun4i_a10_cfg, + }, + { + .compatible = "allwinner,sun6i-a31-ehci", + .data = (ulong)&sun6i_a31_cfg, + }, + { + .compatible = "allwinner,sun7i-a20-ehci", + .data = (ulong)&sun4i_a10_cfg, + }, + { + .compatible = "allwinner,sun8i-a23-ehci", + .data = (ulong)&sun6i_a31_cfg, + }, + { + .compatible = "allwinner,sun8i-a83t-ehci", + .data = (ulong)&sun6i_a31_cfg, + }, + { + .compatible = "allwinner,sun8i-h3-ehci", + .data = (ulong)&sun8i_h3_cfg, + }, + { + .compatible = "allwinner,sun9i-a80-ehci", + .data = (ulong)&sun9i_a80_cfg, + }, + { + .compatible = "allwinner,sun50i-a64-ehci", + .data = (ulong)&sun8i_h3_cfg, + }, + { /* sentinel */ } }; U_BOOT_DRIVER(ehci_sunxi) = { diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index ce2b47a5c4b..0ddbdbe4609 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -17,17 +17,31 @@ #include <generic-phy.h> #ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 #define AHB_CLK_DIST 2 #else +#define BASE_DIST 0x1000 #define AHB_CLK_DIST 1 #endif +#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0 +#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0 + +struct ohci_sunxi_cfg { + bool has_reset; + u32 extra_ahb_gate_mask; + u32 extra_usb_gate_mask; + u32 reset0_cfg_offset; +}; + struct ohci_sunxi_priv { - struct sunxi_ccm_reg *ccm; ohci_t ohci; + struct sunxi_ccm_reg *ccm; + u32 *reset0_cfg; int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */ struct phy phy; + const struct ohci_sunxi_cfg *cfg; }; static int ohci_usb_probe(struct udevice *dev) @@ -36,12 +50,17 @@ static int ohci_usb_probe(struct udevice *dev) struct ohci_sunxi_priv *priv = dev_get_priv(dev); struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); int extra_ahb_gate_mask = 0; + u8 reg_mask = 0; int phys, ret; + priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev); priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (IS_ERR(priv->ccm)) return PTR_ERR(priv->ccm); + priv->reset0_cfg = (void *)priv->ccm + + priv->cfg->reset0_cfg_offset; + phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); if (phys < 0) { phys = 0; @@ -73,22 +92,21 @@ no_phy: * This should go away once we've moved to the driver model for * clocks resp. phys. */ + reg_mask = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; -#ifdef CONFIG_MACH_SUN8I_H3 - extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; -#endif + extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->ahb_gate_mask <<= phys * AHB_CLK_DIST; - extra_ahb_gate_mask <<= phys * AHB_CLK_DIST; - priv->usb_gate_mask <<= phys; + priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; + extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; + priv->usb_gate_mask <<= reg_mask; setbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); - setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask); -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&priv->ccm->ahb_reset0_cfg, - priv->ahb_gate_mask | extra_ahb_gate_mask); -#endif + setbits_le32(&priv->ccm->usb_clk_cfg, + priv->usb_gate_mask | priv->cfg->extra_usb_gate_mask); + if (priv->cfg->has_reset) + setbits_le32(priv->reset0_cfg, + priv->ahb_gate_mask | extra_ahb_gate_mask); return ohci_register(dev, regs); } @@ -110,26 +128,79 @@ static int ohci_usb_remove(struct udevice *dev) if (ret) return ret; -#ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask); -#endif + if (priv->cfg->has_reset) + clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask); clrbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask); clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); return 0; } +static const struct ohci_sunxi_cfg sun4i_a10_cfg = { + .has_reset = false, +}; + +static const struct ohci_sunxi_cfg sun6i_a31_cfg = { + .has_reset = true, + .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, +}; + +static const struct ohci_sunxi_cfg sun8i_h3_cfg = { + .has_reset = true, + .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, + .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, +}; + +static const struct ohci_sunxi_cfg sun9i_a80_cfg = { + .has_reset = true, + .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET, +}; + +static const struct ohci_sunxi_cfg sun50i_a64_cfg = { + .has_reset = true, + .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, + .extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK, + .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, +}; + static const struct udevice_id ohci_usb_ids[] = { - { .compatible = "allwinner,sun4i-a10-ohci", }, - { .compatible = "allwinner,sun5i-a13-ohci", }, - { .compatible = "allwinner,sun6i-a31-ohci", }, - { .compatible = "allwinner,sun7i-a20-ohci", }, - { .compatible = "allwinner,sun8i-a23-ohci", }, - { .compatible = "allwinner,sun8i-a83t-ohci", }, - { .compatible = "allwinner,sun8i-h3-ohci", }, - { .compatible = "allwinner,sun9i-a80-ohci", }, - { .compatible = "allwinner,sun50i-a64-ohci", }, - { } + { + .compatible = "allwinner,sun4i-a10-ohci", + .data = (ulong)&sun4i_a10_cfg, + }, + { + .compatible = "allwinner,sun5i-a13-ohci", + .data = (ulong)&sun4i_a10_cfg, + }, + { + .compatible = "allwinner,sun6i-a31-ohci", + .data = (ulong)&sun6i_a31_cfg, + }, + { + .compatible = "allwinner,sun7i-a20-ohci", + .data = (ulong)&sun4i_a10_cfg, + }, + { + .compatible = "allwinner,sun8i-a23-ohci", + .data = (ulong)&sun6i_a31_cfg, + }, + { + .compatible = "allwinner,sun8i-a83t-ohci", + .data = (ulong)&sun6i_a31_cfg, + }, + { + .compatible = "allwinner,sun8i-h3-ohci", + .data = (ulong)&sun8i_h3_cfg, + }, + { + .compatible = "allwinner,sun9i-a80-ohci", + .data = (ulong)&sun9i_a80_cfg, + }, + { + .compatible = "allwinner,sun50i-a64-ohci", + .data = (ulong)&sun50i_a64_cfg, + }, + { /* sentinel */ } }; U_BOOT_DRIVER(usb_ohci) = { diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index 23508319320..fba78dcf7a7 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -359,7 +359,7 @@ typedef struct } urb_priv_t; #define URB_DEL 1 -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ +#define NUM_EDS 32 /* num of preallocated endpoint descriptors */ #define NUM_TD 64 /* we need more TDs than EDs */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 4c4d2861fe7..5ee9032dc9b 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -156,6 +156,15 @@ config VIDEO_COREBOOT coreboot already. This can in principle be used with any platform that coreboot supports. +config VIDEO_EFI + bool "Enable EFI framebuffer driver support" + depends on EFI_STUB + help + Turn on this option to enable a framebuffeer driver when U-Boot is + loaded as a payload (see README.u-boot_on_efi) by an EFI BIOS where + the graphics device is configured by the EFI BIOS already. This can + in principle be used with any platform that has an EFI BIOS. + config VIDEO_VESA bool "Enable VESA video driver support" default n diff --git a/drivers/video/Makefile b/drivers/video/Makefile index cf7ad281c3b..7c89c67dcea 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o +obj-$(CONFIG_VIDEO_EFI) += efi.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o diff --git a/drivers/video/efi.c b/drivers/video/efi.c new file mode 100644 index 00000000000..653cb472652 --- /dev/null +++ b/drivers/video/efi.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * + * EFI framebuffer driver based on GOP + */ + +#include <common.h> +#include <dm.h> +#include <efi_api.h> +#include <vbe.h> +#include <video.h> + +struct pixel { + u8 pos; + u8 size; +}; + +static const struct efi_framebuffer { + struct pixel red; + struct pixel green; + struct pixel blue; + struct pixel rsvd; +} efi_framebuffer_format_map[] = { + [EFI_GOT_RGBA8] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, + [EFI_GOT_BGRA8] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, +}; + +static void efi_find_pixel_bits(u32 mask, u8 *pos, u8 *size) +{ + u8 first, len; + + first = 0; + len = 0; + + if (mask) { + while (!(mask & 0x1)) { + mask = mask >> 1; + first++; + } + + while (mask & 0x1) { + mask = mask >> 1; + len++; + } + } + + *pos = first; + *size = len; +} + +static int save_vesa_mode(struct vesa_mode_info *vesa) +{ + struct efi_entry_gopmode *mode; + const struct efi_framebuffer *fbinfo; + int size; + int ret; + + ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size); + if (ret == -ENOENT) { + debug("efi graphics output protocol mode not found\n"); + return -ENXIO; + } + + vesa->phys_base_ptr = mode->fb_base; + vesa->x_resolution = mode->info->width; + vesa->y_resolution = mode->info->height; + + if (mode->info->pixel_format < EFI_GOT_BITMASK) { + fbinfo = &efi_framebuffer_format_map[mode->info->pixel_format]; + vesa->red_mask_size = fbinfo->red.size; + vesa->red_mask_pos = fbinfo->red.pos; + vesa->green_mask_size = fbinfo->green.size; + vesa->green_mask_pos = fbinfo->green.pos; + vesa->blue_mask_size = fbinfo->blue.size; + vesa->blue_mask_pos = fbinfo->blue.pos; + vesa->reserved_mask_size = fbinfo->rsvd.size; + vesa->reserved_mask_pos = fbinfo->rsvd.pos; + + vesa->bits_per_pixel = 32; + vesa->bytes_per_scanline = mode->info->pixels_per_scanline * 4; + } else if (mode->info->pixel_format == EFI_GOT_BITMASK) { + efi_find_pixel_bits(mode->info->pixel_bitmask[0], + &vesa->red_mask_pos, + &vesa->red_mask_size); + efi_find_pixel_bits(mode->info->pixel_bitmask[1], + &vesa->green_mask_pos, + &vesa->green_mask_size); + efi_find_pixel_bits(mode->info->pixel_bitmask[2], + &vesa->blue_mask_pos, + &vesa->blue_mask_size); + efi_find_pixel_bits(mode->info->pixel_bitmask[3], + &vesa->reserved_mask_pos, + &vesa->reserved_mask_size); + vesa->bits_per_pixel = vesa->red_mask_size + + vesa->green_mask_size + + vesa->blue_mask_size + + vesa->reserved_mask_size; + vesa->bytes_per_scanline = (mode->info->pixels_per_scanline * + vesa->bits_per_pixel) / 8; + } else { + debug("efi set unknown framebuffer format: %d\n", + mode->info->pixel_format); + return -EINVAL; + } + + return 0; +} + +static int efi_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct vesa_mode_info *vesa = &mode_info.vesa; + int ret; + + /* Initialize vesa_mode_info structure */ + ret = save_vesa_mode(vesa); + if (ret) + goto err; + + ret = vbe_setup_video_priv(vesa, uc_priv, plat); + if (ret) + goto err; + + printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, + vesa->bits_per_pixel); + + return 0; + +err: + printf("No video mode configured in EFI!\n"); + return ret; +} + +static const struct udevice_id efi_video_ids[] = { + { .compatible = "efi-fb" }, + { } +}; + +U_BOOT_DRIVER(efi_video) = { + .name = "efi_video", + .id = UCLASS_VIDEO, + .of_match = efi_video_ids, + .probe = efi_video_probe, +}; diff --git a/dts/.gitignore b/dts/.gitignore deleted file mode 100644 index 1b3718065ca..00000000000 --- a/dts/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.dtb -*.dtb.S diff --git a/fs/btrfs/btrfs.h b/fs/btrfs/btrfs.h index 27d78837c54..986d0786797 100644 --- a/fs/btrfs/btrfs.h +++ b/fs/btrfs/btrfs.h @@ -13,7 +13,6 @@ struct btrfs_info { struct btrfs_super_block sb; - struct btrfs_root_backup *root_backup; struct btrfs_root tree_root; struct btrfs_root fs_root; diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index ad6641f3148..e680caa56a4 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -15,18 +15,34 @@ #define BTRFS_SUPER_INFO_SIZE 4096 -static int btrfs_newest_root_backup(struct btrfs_super_block *sb) +/* + * checks if a valid root backup is present. + * considers the case when all root backups empty valid. + * returns -1 in case of invalid root backup and 0 for valid. + */ +static int btrfs_check_super_roots(struct btrfs_super_block *sb) { struct btrfs_root_backup *root_backup; int i, newest = -1; + int num_empty = 0; for (i = 0; i < BTRFS_NUM_BACKUP_ROOTS; ++i) { root_backup = sb->super_roots + i; + + if (root_backup->tree_root == 0 && root_backup->tree_root_gen == 0) + num_empty++; + if (root_backup->tree_root_gen == sb->generation) newest = i; } - return newest; + if (num_empty == BTRFS_NUM_BACKUP_ROOTS) { + return 0; + } else if (newest >= 0) { + return 0; + } + + return -1; } static inline int is_power_of_2(u64 x) @@ -166,7 +182,7 @@ int btrfs_read_superblock(void) char raw_sb[BTRFS_SUPER_INFO_SIZE]; struct btrfs_super_block *sb = (struct btrfs_super_block *) raw_sb; u64 dev_total_bytes; - int i, root_backup_idx; + int i; dev_total_bytes = (u64) btrfs_part_info->size * btrfs_part_info->blksz; @@ -211,17 +227,15 @@ int btrfs_read_superblock(void) return -1; } - root_backup_idx = btrfs_newest_root_backup(&btrfs_info.sb); - if (root_backup_idx < 0) { + if (btrfs_check_super_roots(&btrfs_info.sb)) { printf("%s: No valid root_backup found!\n", __func__); return -1; } - btrfs_info.root_backup = btrfs_info.sb.super_roots + root_backup_idx; - if (btrfs_info.root_backup->num_devices != 1) { + if (btrfs_info.sb.num_devices != 1) { printf("%s: Unsupported number of devices (%lli). This driver " "only supports filesystem on one device.\n", __func__, - btrfs_info.root_backup->num_devices); + btrfs_info.sb.num_devices); return -1; } diff --git a/include/avb_verify.h b/include/avb_verify.h new file mode 100644 index 00000000000..eaa60f5393e --- /dev/null +++ b/include/avb_verify.h @@ -0,0 +1,96 @@ + +/* + * (C) Copyright 2018, Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _AVB_VERIFY_H +#define _AVB_VERIFY_H + +#include <../lib/libavb/libavb.h> +#include <mmc.h> + +#define AVB_MAX_ARGS 1024 +#define VERITY_TABLE_OPT_RESTART "restart_on_corruption" +#define VERITY_TABLE_OPT_LOGGING "ignore_corruption" +#define ALLOWED_BUF_ALIGN 8 + +enum avb_boot_state { + AVB_GREEN, + AVB_YELLOW, + AVB_ORANGE, + AVB_RED, +}; + +struct AvbOpsData { + struct AvbOps ops; + int mmc_dev; + enum avb_boot_state boot_state; +}; + +struct mmc_part { + int dev_num; + struct mmc *mmc; + struct blk_desc *mmc_blk; + disk_partition_t info; +}; + +enum mmc_io_type { + IO_READ, + IO_WRITE +}; + +AvbOps *avb_ops_alloc(int boot_device); +void avb_ops_free(AvbOps *ops); + +char *avb_set_state(AvbOps *ops, enum avb_boot_state boot_state); +char *avb_set_enforce_verity(const char *cmdline); +char *avb_set_ignore_corruption(const char *cmdline); + +char *append_cmd_line(char *cmdline_orig, char *cmdline_new); + +/** + * ============================================================================ + * I/O helper inline functions + * ============================================================================ + */ +static inline uint64_t calc_offset(struct mmc_part *part, int64_t offset) +{ + u64 part_size = part->info.size * part->info.blksz; + + if (offset < 0) + return part_size + offset; + + return offset; +} + +static inline size_t get_sector_buf_size(void) +{ + return (size_t)CONFIG_FASTBOOT_BUF_SIZE; +} + +static inline void *get_sector_buf(void) +{ + return (void *)CONFIG_FASTBOOT_BUF_ADDR; +} + +static inline bool is_buf_unaligned(void *buffer) +{ + return (bool)((uintptr_t)buffer % ALLOWED_BUF_ALIGN); +} + +static inline int get_boot_device(AvbOps *ops) +{ + struct AvbOpsData *data; + + if (ops) { + data = ops->user_data; + if (data) + return data->mmc_dev; + } + + return -1; +} + +#endif /* _AVB_VERIFY_H */ diff --git a/include/blk.h b/include/blk.h index fc0c239e468..86f6d5057f2 100644 --- a/include/blk.h +++ b/include/blk.h @@ -111,7 +111,7 @@ struct blk_desc { #define PAD_TO_BLOCKSIZE(size, blk_desc) \ (PAD_SIZE(size, blk_desc->blksz)) -#ifdef CONFIG_BLOCK_CACHE +#if CONFIG_IS_ENABLED(BLOCK_CACHE) /** * blkcache_read() - attempt to read a set of blocks from cache * diff --git a/include/common.h b/include/common.h index 60c79137e21..940161f1758 100644 --- a/include/common.h +++ b/include/common.h @@ -536,10 +536,10 @@ void show_activity(int arg); /* Multicore arch functions */ #ifdef CONFIG_MP -int cpu_status(int nr); -int cpu_reset(int nr); -int cpu_disable(int nr); -int cpu_release(int nr, int argc, char * const argv[]); +int cpu_status(u32 nr); +int cpu_reset(u32 nr); +int cpu_disable(u32 nr); +int cpu_release(u32 nr, int argc, char * const argv[]); #endif #else /* __ASSEMBLY__ */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 6231a1e4ae6..b5ff5d3fe18 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -70,8 +70,6 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ETHPRIME "eTSEC1" -#ifndef CONFIG_SPI_FLASH -#endif #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_L2_SIZE (256 << 10) diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index b1ca5ac11a9..b230896734e 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -11,7 +11,6 @@ * CPU and Board Configuration Options */ #define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SERVERIP /* * Miscellaneous configurable options diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index d2cd4403119..ebfdd1c7a37 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -40,7 +40,6 @@ #ifdef CONFIG_DIRECT_NOR_BOOT #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DA8XX_GPIO #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #endif @@ -227,6 +226,7 @@ #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ #endif +#define CONFIG_DA8XX_GPIO /* * U-Boot general configuration */ diff --git a/include/configs/display5.h b/include/configs/display5.h index cff689420e7..f3c87573856 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -30,9 +30,9 @@ * 0x020000 - 0x120000 : SPI.u-boot (1MiB) * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB) * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB) - * 0x140000 - 0x940000 : SPI.fitImage-recovery (8MiB) - * 0x940000 - 0xD40000 : SPI.swupdate-kernel-FIT (4MiB) - * 0xD40000 - 0x1540000 : SPI.swupdate-initramfs (8MiB) + * 0x140000 - 0x540000 : SPI.swupdate-kernel-FIT (4MiB) + * 0x540000 - 0x1540000 : SPI.swupdate-initramfs (16MiB) + * 0x1540000 - 0x1640000 : SPI.factory (1MiB) */ #ifndef CONFIG_SPL_BUILD @@ -100,7 +100,13 @@ #define CONFIG_BAUDRATE 115200 #ifndef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "run boot_mmc" +#define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \ + "run recovery;" \ + "else if test ${BOOT_FROM} = FACTORY; then " \ + "run factory_nfs;" \ + "else " \ + "run boot_mmc;" \ + "fi;fi" #endif #define PARTS_DEFAULT \ @@ -110,7 +116,7 @@ "name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \ "name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \ "name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \ - "name=rootfs2,size=1528M,uuid=${uuid_gpt_rootfs2};" \ + "name=rootfs2,size=512M,uuid=${uuid_gpt_rootfs2};" \ "name=data,size=-,uuid=${uuid_gpt_data}\0" #define FACTORY_PROCEDURE \ @@ -123,7 +129,6 @@ "run tftp_sf_SPL;" \ "run tftp_sf_uboot;" \ TFTP_UPDATE_KERNEL \ - "run tftp_sf_fitImg_recovery;" \ "run tftp_sf_fitImg_SWU;" \ "run tftp_sf_initramfs_SWU;" \ TFTP_UPDATE_ROOTFS \ @@ -139,6 +144,16 @@ "echo '#######################';" \ "echo '# RECOVERY SWUupdate #';" \ "echo '#######################';" \ + "echo '#######################';" \ + "echo '# GPT verify #';" \ + "if gpt verify mmc ${mmcdev} ${partitions}; then " \ + "echo '# OK ! #';" \ + "else " \ + "echo '# FAILED ! #';" \ + "echo '# GPT RESTORATION #';" \ + "gpt write mmc ${mmcdev} ${partitions};" \ + "fi;" \ + "echo '#######################';" \ "setenv loadaddr_swu_initramfs 0x14000000;" \ "setenv bootargs console=${console} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ @@ -146,15 +161,7 @@ "sf probe;" \ "sf read ${loadaddr} swu-kernel;" \ "sf read ${loadaddr_swu_initramfs} swu-initramfs;" \ - "bootm ${loadaddr} ${loadaddr_swu_initramfs};" - -#define KERNEL_RECOVERY_PROCEDURE \ - "echo '#######################';" \ - "echo '# RECOVERY KERNEL IMG #';" \ - "echo '#######################';" \ - "sf probe;" \ - "sf read ${loadaddr} lin-recovery;" \ - "bootm;" + "bootm ${loadaddr} ${loadaddr_swu_initramfs};reset;" #define SETUP_BOOTARGS \ "run set_rootfs_part;" \ @@ -197,13 +204,11 @@ "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ "; fi\0" \ -/* To save some considerable time, we only once download the rootfs image */ -/* and store it on 'active' and 'backup' rootfs partitions */ #define TFTP_UPDATE_ROOTFS \ "setenv rootfs_part ${rootfs_part_active};" \ "run tftp_mmc_rootfs;" \ - "part start mmc ${mmcdev} ${rootfs_part_backup} lba_start;" \ - "mmc write ${loadaddr} ${lba_start} ${fw_sz};" \ + "run tftp_mmc_rootfs_bkp;" \ + #define TFTP_UPDATE_RECOVERY_SWU_KERNEL \ "tftp_sf_fitImg_SWU=" \ @@ -214,7 +219,7 @@ "; fi\0" \ #define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ - "swu_initramfs_file=swupdate-image-display5.ext3.gz.u-boot\0" \ + "swu_initramfs_file=swupdate-image-display5.ext4.gz.u-boot\0" \ "tftp_sf_initramfs_SWU=" \ "if tftp ${loadaddr} ${swu_initramfs_file}; then " \ "sf probe;" \ @@ -222,15 +227,6 @@ "sf write ${loadaddr} swu-initramfs ${filesize};" \ "; fi\0" \ -#define TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ - "kernel_recovery_file=fitImage-initramfs\0" \ - "tftp_sf_fitImg_recovery=" \ - "if tftp ${loadaddr} ${kernel_recovery_file}; then " \ - "sf probe;" \ - "sf erase lin-recovery +${filesize};" \ - "sf write ${loadaddr} lin-recovery ${filesize};" \ - "; fi\0" \ - #define TFTP_UPDATE_BOOTLOADER \ "ubootfile=u-boot.img\0" \ "ubootfileSPL=SPL\0" \ @@ -248,8 +244,20 @@ "sf write ${loadaddr} 0x400 ${filesize};" \ "fi\0" \ +#define TFTP_UPDATE_SPINOR \ + "spinorfile=core-image-lwn-display5.spinor\0" \ + "spinorsize=0x2000000\0" \ + "tftp_sf_img=" \ + "if tftp ${loadaddr} ${spinorfile}; then " \ + "sf probe;" \ + "sf erase 0x0 ${spinorsize};" \ + "sf write ${loadaddr} 0x0 ${filesize};" \ + "fi\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ PARTS_DEFAULT \ + "gpio_recovery=93\0" \ + "check_em_pad=gpio input ${gpio_recovery};test $? -eq 0;\0" \ "display=tianma-tm070-800x480\0" \ "board=display5\0" \ "mmcdev=0\0" \ @@ -265,7 +273,7 @@ "hostname=display5\0" \ "loadaddr=0x12000000\0" \ "fdtaddr=0x12800000\0" \ - "console=ttymxc4,115200 quiet\0" \ + "console=ttymxc4,115200 quiet cma=256M\0" \ "fdtfile=imx6q-display5.dtb\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -273,21 +281,22 @@ "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ "download_kernel=" \ "tftpboot ${loadaddr} ${kernel_file};\0" \ - "boot_kernel_recovery=" KERNEL_RECOVERY_PROCEDURE "\0" \ + "factory_nfs=" \ + "setenv ipaddr 192.168.1.102;" \ + "setenv gatewayip 192.168.1.1;" \ + "setenv netmask 255.255.255.0;" \ + "setenv serverip 192.168.1.2;" \ + "echo BOOT: FACTORY (LEG);" \ + "run boot_nfs\0" \ "boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \ "recovery=" \ - "if test ${BOOT_FROM_RECOVERY} = SWU; then " \ "echo BOOT: RECOVERY: SWU;" \ - "run boot_swu_recovery;" \ - "else " \ - "echo BOOT: RECOVERY: Linux;" \ - "run boot_kernel_recovery;" \ - "fi\0" \ + "run boot_swu_recovery\0" \ "boot_tftp=" \ "if run download_kernel; then " \ "setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rootwait;" \ - "bootm ${loadaddr} - ${fdtaddr};" \ + "bootm ${loadaddr} - ${fdtaddr};reset;" \ "fi\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ @@ -304,7 +313,7 @@ "run addip;" \ "setenv bootargs ${bootargs} console=${console};" \ "setenv fdt_conf imx6q-${board}-${display}.dtb; " \ - "bootm ${loadaddr}#conf@${fdt_conf};" \ + "bootm ${loadaddr}#conf@${fdt_conf};reset;" \ "fi\0" \ "falcon_setup=" \ "if mmc dev ${mmcdev}; then " \ @@ -318,7 +327,7 @@ "boot_mmc=" \ "if mmc dev ${mmcdev}; then " \ SETUP_BOOTARGS \ - "bootm ${loadaddr}#conf@${fdt_conf};" \ + "bootm ${loadaddr}#conf@${fdt_conf};reset;" \ "fi\0" \ "set_kernel_part=" \ "if test ${BOOT_FROM} = ACTIVE; then " \ @@ -339,16 +348,20 @@ "run recovery;" \ "fi;fi\0" \ "BOOT_FROM=ACTIVE\0" \ - "BOOT_FROM_RECOVERY=Linux\0" \ TFTP_UPDATE_BOOTLOADER \ + TFTP_UPDATE_SPINOR \ "kernel_part_active=1\0" \ "kernel_part_backup=3\0" \ __TFTP_UPDATE_KERNEL \ "rootfs_part_active=2\0" \ "rootfs_part_backup=4\0" \ "rootfs_file=core-image-lwn-display5.ext4\0" \ + "rootfs_file_backup=core-image-lwn-backup-display5.ext4\0" \ __TFTP_UPDATE_ROOTFS \ - TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ + "tftp_mmc_rootfs_bkp=" \ + "setenv rootfs_part ${rootfs_part_backup};" \ + "setenv rootfs_file ${rootfs_file_backup};" \ + "run tftp_mmc_rootfs\0" \ TFTP_UPDATE_RECOVERY_SWU_KERNEL \ TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ "\0" \ @@ -383,6 +396,11 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE +/* Watchdog */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000 + /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE (SZ_64K) diff --git a/include/configs/draak.h b/include/configs/draak.h index e0a5344fbe7..e1b9bf18850 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -15,16 +15,12 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ -#define CONFIG_SYS_CLK_FREQ 33333333u - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 86fa735470c..46a7179f1be 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -94,6 +94,7 @@ REFLASH(dragonboard/u-boot.img, 8)\ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 /* mmc0 = emmc, mmc1 = sd */ +#define CONFIG_SYS_MMC_ENV_PART 2 /* Set env partition to BOOT2 partition */ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 560fe5c45e0..2e4974acb2f 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -18,10 +18,6 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ -#define CONFIG_SYS_CLK_FREQ 48000000u - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86_app.h index 33418cfbec4..33418cfbec4 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86_app.h diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h new file mode 100644 index 00000000000..1cf5c037e85 --- /dev/null +++ b/include/configs/efi-x86_payload.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* ATA/IDE support */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#endif /* __CONFIG_H */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 530c3557d03..0dc708e480a 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -46,6 +46,7 @@ "fdt_high=0xffffffff\0" \ "scriptaddr=0x74000000\0" \ "kernel_file=fitImage\0"\ + "silent=1\0"\ "rdinit=/sbin/init\0" \ "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ "upd_image=st.4k\0" \ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h deleted file mode 100644 index bb1d6b4f5d0..00000000000 --- a/include/configs/m28evk.h +++ /dev/null @@ -1,225 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_M28EVK_H__ -#define __CONFIGS_M28EVK_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* Memory configuration */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (24 * CONFIG_ENV_SECT_SIZE) /* 3 MiB */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#endif - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* RTC */ -#ifdef CONFIG_CMD_DATE -/* Use the internal RTC in the MXS chip */ -#define CONFIG_RTC_INTERNAL -#ifdef CONFIG_RTC_INTERNAL -#define CONFIG_RTC_MXS -#else -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* SPI */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_DEFAULT_SPI_BUS 2 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 - -/* SPI FLASH */ -#ifdef CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 40000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 - -#define CONFIG_ENV_SPI_BUS 2 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 40000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#endif - -#endif - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_HOSTNAME "m28evk" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyAMA0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p2\0" \ - "rootdev=/dev/mmcblk0p3\0" \ - "netdev=eth0\0" \ - "hostname=m28evk\0" \ - "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ - "kernel_addr_r=0x42000000\0" \ - "videomode=video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066," \ - "le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296," \ - "vmode:0\0" \ - "update_nand_full_filename=u-boot.nand\0" \ - "update_nand_firmware_filename=u-boot.sb\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_nand_firmware_maxsz=0x100000\0" \ - "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ - "nand device 0 ; " \ - "nand info ; " \ - "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ - "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_full=" /* Update FCB, DBBT and FW */ \ - "if tftp ${update_nand_full_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "nand scrub -y 0x0 ${filesize} ; " \ - "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ - "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ - "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ - "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ - "fi\0" \ - "update_nand_firmware=" /* Update only firmware */ \ - "if tftp ${update_nand_firmware_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ - "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ - "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ - "nand erase ${fcb_sz} ${fw_sz} ; " \ - "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ - "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ - "fi\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "adddfltmtd=" \ - "if test \"x${mtdparts}\" == \"x\" ; then " \ - "mtdparts default ; " \ - "fi\0" \ - "addmtd=" \ - "run adddfltmtd ; " \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addargs=run addcons addmtd addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ - "ubiload=" \ - "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "ubiargs=" \ - "setenv bootargs ubi.mtd=5 " \ - "root=ubi0:rootfs rootfstype=ubifs\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_ubi=" \ - "run mmcload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_mmc=" \ - "run ubiload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_ubi=" \ - "run ubiload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_nfs=" \ - "run ubiload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_ubi=" \ - "run netload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_M28EVK_H__ */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h deleted file mode 100644 index 9eaafc538cc..00000000000 --- a/include/configs/m53evk.h +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aries M53 configuration - * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - */ - -#ifndef __M53EVK_CONFIG_H__ -#define __M53EVK_CONFIG_H__ - -#include <asm/arch/imx-regs.h> - -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) -#define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x8ff00000 - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 -#endif - -/* - * NAND - */ -#define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_USE_FLASH_BBT - -/* Environment is in NAND */ -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#endif - -/* - * Ethernet on SOC (FEC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_MII -#define CONFIG_DISCOVER_PHY -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC0" -#endif - -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MX5 -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#endif - -/* - * SATA - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* - * LCD - */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASHIMAGE_GUARD -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_LOADADDR 0x70800000 -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * NAND SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" -#define CONFIG_SPL_TEXT_BASE 0x70008000 -#define CONFIG_SPL_PAD_TO 0x8000 -#define CONFIG_SPL_STACK 0x70004000 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 - -/* - * Extra Environments - */ -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_HOSTNAME "m53evk" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttymxc1\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p1\0" \ - "rootdev=/dev/mmcblk0p2\0" \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \ - "kernel_addr_r=0x72000000\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "adddfltmtd=" \ - "if test \"x${mtdparts}\" == \"x\" ; then " \ - "mtdparts default ; " \ - "fi\0" \ - "addmtd=" \ - "run adddfltmtd ; " \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addargs=run addcons addmtd addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ - "ubiload=" \ - "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "ubiargs=" \ - "setenv bootargs ubi.mtd=5 " \ - "root=ubi0:rootfs rootfstype=ubifs\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_ubi=" \ - "run mmcload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_mmc=" \ - "run ubiload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_ubi=" \ - "run ubiload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_nfs=" \ - "run ubiload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_ubi=" \ - "run netload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:1 ${bootscript} ; then " \ - "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -#endif /* __M53EVK_CONFIG_H__ */ diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h deleted file mode 100644 index 5e3d6e80a87..00000000000 --- a/include/configs/ma5d4evk.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aries MA5D4 configuration - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ - -#ifndef __MA5D4EVK_CONFIG_H__ -#define __MA5D4EVK_CONFIG_H__ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#include "at91-sama5_common.h" -#define CONFIG_SYS_USE_SERIALFLASH 1 -#define CONFIG_BOARD_LATE_INIT - -/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* - * Environment - */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* eMMC */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* - * U-Boot general configurations - */ - -/* - * Serial Driver - */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE 0xf802c000 -#define CONFIG_USART_ID 6 - -/* - * Ethernet - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_IP_DEFRAG -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP -#define LCD_BPP LCD_COLOR16 -#define LCD_OUTPUT_BPP 24 -#define CONFIG_ATMEL_HLCD -#endif - -/* - * SD/MMC - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* - * SPI NOR (boot memory) - */ -#ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB - -/* USB device */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024) -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#endif - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_LOADADDR 0x20800000 -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_HOSTNAME "ma5d4evk" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyS3\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p1\0" \ - "bootpart=0:1\0" \ - "rootdev=/dev/mmcblk0p2\0" \ - "netdev=eth0\0" \ - "dfu_alt_info=mmc raw 0 3867148288\0" \ - "kernel_addr_r=0x22000000\0" \ - "update_spi_firmware_spl_addr=0x21000000\0" \ - "update_spi_firmware_spl_filename=boot.bin\0" \ - "update_spi_firmware_addr=0x22000000\0" \ - "update_spi_firmware_filename=u-boot.img\0" \ - "update_spi_firmware=" /* Update the SPI flash firmware */ \ - "if sf probe ; then " \ - "if tftp ${update_spi_firmware_spl_addr} " \ - "${update_spi_firmware_spl_filename} ; then " \ - "setenv update_spi_firmware_spl_filesize ${filesize} ; "\ - "if tftp ${update_spi_firmware_addr} " \ - "${update_spi_firmware_filename} ; then " \ - "setenv update_spi_firmware_filesize ${filesize} ; " \ - "sf update ${update_spi_firmware_spl_addr} 0x0 " \ - "${update_spi_firmware_spl_filesize} ; " \ - "sf update ${update_spi_firmware_addr} 0x10000 " \ - "${update_spi_firmware_filesize} ; " \ - "fi ; " \ - "fi ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc ${bootpart} ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "fdtimg=if test ${bootmode} = \"sf\" ; then " \ - "setenv kernel_fdt 1 ; " \ - "else ; " \ - "setenv kernel_fdt 2 ; " \ - "fi\0" \ - "mmc_mmc=" \ - "run fdtimg mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "mmc_nfs=" \ - "run fdtimg mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "net_mmc=" \ - "run fdtimg netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "net_nfs=" \ - "run fdtimg netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 1:1 ${bootscript} ; then " \ - "if load mmc 1:1 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" -/* SPL */ -#define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - -#define CONFIG_SYS_USE_MMC -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT - -#endif /* __MA5D4EVK_CONFIG_H__ */ diff --git a/include/configs/meson-gx-common.h b/include/configs/meson-gx-common.h index 6e61b704a3c..7435f3475ea 100644 --- a/include/configs/meson-gx-common.h +++ b/include/configs/meson-gx-common.h @@ -23,10 +23,17 @@ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ + BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 6e213776982..803661cfa84 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -101,18 +101,18 @@ "fi; " \ "fi\0" \ "findfdt="\ - "if test $board_name = HUMMINGBOARD2 && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-hummingboard2.dtb; fi; " \ - "if test $board_name = HUMMINGBOARD2 && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-hummingboard2.dtb; fi; " \ - "if test $board_name = HUMMINGBOARD && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-hummingboard.dtb; fi; " \ - "if test $board_name = HUMMINGBOARD && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-hummingboard.dtb; fi; " \ - "if test $board_name = CUBOXI && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-cubox-i.dtb; fi; " \ - "if test $board_name = CUBOXI && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-cubox-i.dtb; fi; " \ + "if test $board_rev = MX6Q ; then " \ + "setenv fdtprefix imx6q; fi; " \ + "if test $board_rev = MX6DL ; then " \ + "setenv fdtprefix imx6dl; fi; " \ + "if test $som_rev = V15 ; then " \ + "setenv fdtsuffix -som-v15; fi; " \ + "if test $board_name = HUMMINGBOARD2 ; then " \ + "setenv fdtfile ${fdtprefix}-hummingboard2${fdtsuffix}.dtb; fi; " \ + "if test $board_name = HUMMINGBOARD ; then " \ + "setenv fdtfile ${fdtprefix}-hummingboard${fdtsuffix}.dtb; fi; " \ + "if test $board_name = CUBOXI ; then " \ + "setenv fdtfile ${fdtprefix}-cubox-i${fdtsuffix}.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ BOOTENV diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index b208d7f4d96..d2ffa70fc55 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -41,7 +41,7 @@ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-pico.dtb\0" \ + "fdt_file=imx7d-pico-pi.dtb\0" \ "fdt_addr=0x83000000\0" \ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 231c4ecea45..e1b2fa28e1e 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -33,7 +33,8 @@ #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) +#define CONFIG_SYS_LOAD_ADDR 0x50000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MONITOR_BASE 0x00000000 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index af7b196dc16..07f08db4fe7 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -42,7 +42,8 @@ #define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x48080000 +#define CONFIG_SYS_LOAD_ADDR 0x58000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index ecc6c5d80dc..1bf22349188 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -15,10 +15,6 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ -#define CONFIG_SYS_CLK_FREQ 33333333u - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h deleted file mode 100644 index 4d1c4f2c2bc..00000000000 --- a/include/configs/socfpga_mcvevk.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIG_ARIES_MCVEVK_H__ -#define __CONFIG_ARIES_MCVEVK_H__ - -#include <asm/arch/base_addr_ac5.h> - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Environment is in MMC */ -#define CONFIG_ENV_OVERWRITE - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyS0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p2\0" \ - "rootdev=/dev/mmcblk0p3\0" \ - "netdev=eth0\0" \ - "hostname=mcvevk\0" \ - "kernel_addr_r=0x10000000\0" \ - "dfu_alt_info=mmc raw 0 3867148288\0" \ - "update_filename=u-boot-with-spl.sfp\0" \ - "update_sd_offset=0x800\0" \ - "update_sd=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "update_qspi_offset=0x0\0" \ - "update_qspi=" /* Update the QSPI firmware */ \ - "if sf probe ; then " \ - "if tftp ${update_filename} ; then " \ - "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ - "fi ; " \ - "fi\0" \ - "fpga_filename=output_file.rbf\0" \ - "load_fpga=" /* Load FPGA bitstream */ \ - "if tftp ${fpga_filename} ; then " \ - "fpga load 0 $loadaddr $filesize ; " \ - "bridge enable ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/socfpga_common.h> - -#endif /* __CONFIG_ARIES_MCVEVK_H__ */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 86c6ed3a36a..6f2a0cc56dc 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -15,10 +15,6 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ -#define CONFIG_SYS_CLK_FREQ 33333333u - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 0d8ae0b099b..2456475f27c 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -257,9 +257,6 @@ #undef PCI_ONE_PCI1 #endif -#ifndef VME_CADDY2 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 1edd7a88270..cb32cd11f94 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -78,7 +78,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ + "console=ttymxc0\0" \ "splashpos=m,m\0" \ "fdtfile=undefined\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/div64.h b/include/div64.h index cecb2322bcb..76563ef9786 100644 --- a/include/div64.h +++ b/include/div64.h @@ -232,7 +232,7 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); #endif /* BITS_PER_LONG */ /* Wrapper for do_div(). Doesn't modify dividend and returns - * the result, not reminder. + * the result, not remainder. */ static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor) { diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index a7a1a50f33e..b2325d3e236 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -80,10 +80,10 @@ #define IMX7D_ARM_M4_ROOT_SRC 67 #define IMX7D_ARM_M4_ROOT_CG 68 #define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 -#define IMX7D_ARM_M0_ROOT_SRC 71 -#define IMX7D_ARM_M0_ROOT_CG 72 -#define IMX7D_ARM_M0_ROOT_DIV 73 +#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ +#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ +#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ +#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ #define IMX7D_MAIN_AXI_ROOT_CLK 74 #define IMX7D_MAIN_AXI_ROOT_SRC 75 #define IMX7D_MAIN_AXI_ROOT_CG 76 @@ -450,5 +450,10 @@ #define IMX7D_CLK_ARM 437 #define IMX7D_CKIL 438 #define IMX7D_OCOTP_CLK 439 -#define IMX7D_CLK_END 440 +#define IMX7D_NAND_RAWNAND_CLK 440 +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 +#define IMX7D_SNVS_CLK 442 +#define IMX7D_CAAM_CLK 443 +#define IMX7D_KPP_ROOT_CLK 444 +#define IMX7D_CLK_END 445 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h index e6b1e0a808a..2cc10ae4bbb 100644 --- a/include/dt-bindings/gpio/gpio.h +++ b/include/dt-bindings/gpio/gpio.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * @@ -9,7 +10,27 @@ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H +/* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +/* + * Open Drain/Collector is the combination of single-ended open drain interface. + * Open Source/Emitter is the combination of single-ended open source interface. + */ +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + #endif diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h new file mode 100644 index 00000000000..3a181e41051 --- /dev/null +++ b/include/dt-bindings/power/imx7-power.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2017 Impinj + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_IMX7_POWER_H__ +#define __DT_BINDINGS_IMX7_POWER_H__ + +#define IMX7_POWER_DOMAIN_MIPI_PHY 0 +#define IMX7_POWER_DOMAIN_PCIE_PHY 1 +#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2 + +#endif diff --git a/include/efi.h b/include/efi.h index e30a3c51c67..0fe15e65c06 100644 --- a/include/efi.h +++ b/include/efi.h @@ -19,12 +19,19 @@ #include <linux/string.h> #include <linux/types.h> -#if CONFIG_EFI_STUB_64BIT || (!defined(CONFIG_EFI_STUB) && defined(__x86_64__)) -/* EFI uses the Microsoft ABI which is not the default for GCC */ +/* + * EFI on x86_64 uses the Microsoft ABI which is not the default for GCC. + * + * There are two scenarios for EFI on x86_64: building a 64-bit EFI stub + * codes (CONFIG_EFI_STUB_64BIT) and building a 64-bit U-Boot (CONFIG_X86_64). + * Either needs to be properly built with the '-m64' compiler flag, and hence + * it is enough to only check the compiler provided define __x86_64__ here. + */ +#ifdef __x86_64__ #define EFIAPI __attribute__((ms_abi)) #else #define EFIAPI asmlinkage -#endif +#endif /* __x86_64__ */ struct efi_device_path; @@ -32,16 +39,7 @@ typedef struct { u8 b[16]; } efi_guid_t; -#define EFI_BITS_PER_LONG BITS_PER_LONG - -/* - * With 64-bit EFI stub, EFI_BITS_PER_LONG has to be 64. EFI_STUB is set - * in lib/efi/Makefile, when building the stub. - */ -#if defined(CONFIG_EFI_STUB_64BIT) && defined(EFI_STUB) -#undef EFI_BITS_PER_LONG -#define EFI_BITS_PER_LONG 64 -#endif +#define EFI_BITS_PER_LONG (sizeof(long) * 8) /* Bit mask for EFI status code with error */ #define EFI_ERROR_MASK (1UL << (EFI_BITS_PER_LONG - 1)) @@ -241,6 +239,7 @@ struct efi_open_protocol_info_entry { enum efi_entry_t { EFIET_END, /* Signals this is the last (empty) entry */ EFIET_MEMORY_MAP, + EFIET_GOP_MODE, /* Number of entries */ EFIET_MEMORY_COUNT, @@ -297,6 +296,40 @@ struct efi_entry_memmap { struct efi_mem_desc desc[]; }; +/** + * struct efi_entry_gopmode - a GOP mode table passed to U-Boot + * + * @fb_base: EFI's framebuffer base address + * @fb_size: EFI's framebuffer size + * @info_size: GOP mode info structure size + * @info: Start address of the GOP mode info structure + */ +struct efi_entry_gopmode { + efi_physical_addr_t fb_base; + /* + * Not like the ones in 'struct efi_gop_mode' which are 'unsigned + * long', @fb_size and @info_size have to be 'u64' here. As the EFI + * stub codes may have different bit size from the U-Boot payload, + * using 'long' will cause mismatch between the producer (stub) and + * the consumer (payload). + */ + u64 fb_size; + u64 info_size; + /* + * We cannot directly use 'struct efi_gop_mode_info info[]' here as + * it causes compiler to complain: array type has incomplete element + * type 'struct efi_gop_mode_info'. + */ + struct /* efi_gop_mode_info */ { + u32 version; + u32 width; + u32 height; + u32 pixel_format; + u32 pixel_bitmask[4]; + u32 pixels_per_scanline; + } info[]; +}; + static inline struct efi_mem_desc *efi_get_next_mem_desc( struct efi_entry_memmap *map, struct efi_mem_desc *desc) { diff --git a/include/efi_api.h b/include/efi_api.h index 094be6edf9b..0c3dd3cdd49 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -282,6 +282,10 @@ struct efi_runtime_services { EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \ 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0) +#define EFI_ACPI_TABLE_GUID \ + EFI_GUID(0x8868e871, 0xe4f1, 0x11d3, \ + 0xbc, 0x22, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81) + #define SMBIOS_TABLE_GUID \ EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \ 0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) diff --git a/include/efi_loader.h b/include/efi_loader.h index c66252a7dd2..d837e7b157f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -215,6 +215,14 @@ efi_status_t efi_net_register(void); efi_status_t efi_watchdog_register(void); /* Called by bootefi to make SMBIOS tables available */ /** + * efi_acpi_register() - write out ACPI tables + * + * Called by bootefi to make ACPI tables available + * + * @return 0 if OK, -ENOMEM if no memory is available for the tables + */ +efi_status_t efi_acpi_register(void); +/** * efi_smbios_register() - write out SMBIOS tables * * Called by bootefi to make SMBIOS tables available diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index a43b211df5e..2893cd4287a 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -13,6 +13,16 @@ #define CONSOLEDEV "ttyO2" #endif +#define VBMETA_PART_SIZE (64 * 1024) + +#if defined(CONFIG_LIBAVB) +#define VBMETA_PART \ + "name=vbmeta,size=" __stringify(VBMETA_PART_SIZE) \ + ",uuid=${uuid_gpt_vbmeta};" +#else +#define VBMETA_PART "" +#endif + #ifndef PARTS_DEFAULT /* Define the default GPT table for eMMC */ #define PARTS_DEFAULT \ @@ -37,9 +47,23 @@ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ + VBMETA_PART \ "name=userdata,size=-,uuid=${uuid_gpt_userdata}" #endif /* PARTS_DEFAULT */ +#if defined(CONFIG_CMD_AVB) +#define AVB_VERIFY_CHECK "if run avb_verify; then " \ + "echo AVB verification OK.;" \ + "set bootargs $bootargs $avb_bootargs;" \ + "else " \ + "echo AVB verification failed.;" \ + "exit; fi;" +#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify;\0" +#else +#define AVB_VERIFY_CHECK "" +#define AVB_VERIFY_CMD "" +#endif + #define DEFAULT_COMMON_BOOT_TI_ARGS \ "console=" CONSOLEDEV ",115200n8\0" \ "fdtfile=undefined\0" \ @@ -48,6 +72,7 @@ "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ + AVB_VERIFY_CMD \ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ "dofastboot=0\0" \ @@ -66,6 +91,7 @@ "setenv machid fe6; " \ "mmc dev $mmcdev; " \ "mmc rescan; " \ + AVB_VERIFY_CHECK \ "part start mmc ${mmcdev} environment fdt_start; " \ "part size mmc ${mmcdev} environment fdt_size; " \ "part start mmc ${mmcdev} boot boot_start; " \ diff --git a/include/image.h b/include/image.h index 95d5934344c..420b8ff5761 100644 --- a/include/image.h +++ b/include/image.h @@ -17,6 +17,7 @@ #include "compiler.h" #include <asm/byteorder.h> +#include <stdbool.h> /* Define this to avoid #ifdefs later on */ struct lmb; @@ -881,9 +882,11 @@ int bootz_setup(ulong image, ulong *start, ulong *end); * @image: Address of image * @start: Returns start address of image * @size : Returns size image + * @force_reloc: Ignore image->ep field, always place image to RAM start * @return 0 if OK, 1 if the image was not recognised */ -int booti_setup(ulong image, ulong *relocated_addr, ulong *size); +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc); /*******************************************************************/ /* New uImage format specific code (prefixed with fit_) */ diff --git a/include/iotrace.h b/include/iotrace.h index 1efb117343a..be1d2753e19 100644 --- a/include/iotrace.h +++ b/include/iotrace.h @@ -6,8 +6,36 @@ #ifndef __IOTRACE_H #define __IOTRACE_H +//#include <common.h> #include <linux/types.h> +/* Support up to the machine word length for now */ +typedef ulong iovalue_t; + +enum iotrace_flags { + IOT_8 = 0, + IOT_16, + IOT_32, + + IOT_READ = 0 << 3, + IOT_WRITE = 1 << 3, +}; + +/** + * struct iotrace_record - Holds a single I/O trace record + * + * @flags: I/O access type + * @timestamp: Timestamp of access + * @addr: Address of access + * @value: Value written or read + */ +struct iotrace_record { + enum iotrace_flags flags; + u64 timestamp; + phys_addr_t addr; + iovalue_t value; +}; + /* * This file is designed to be included in arch/<arch>/include/asm/io.h. * It redirects all IO access through a tracing/checksumming feature for @@ -118,11 +146,12 @@ void iotrace_set_buffer(ulong start, ulong size); * iotrace_get_buffer() - Get buffer information * * @start: Returns start address of buffer - * @size: Returns size of buffer in bytes + * @size: Returns actual size of buffer in bytes + * @needed_size: Returns needed size of buffer in bytes * @offset: Returns the byte offset where the next output trace record will * @count: Returns the number of trace records recorded * be written (or would be if the buffer was large enough) */ -void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count); +void iotrace_get_buffer(ulong *start, ulong *size, ulong *needed_size, ulong *offset, ulong *count); #endif /* __IOTRACE_H */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 7fe553fc51c..cdad7b85fa6 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -22,9 +22,16 @@ #include <asm/cache.h> struct mtd_info; +struct nand_chip; struct nand_flash_dev; struct device_node; +/* Get the flash and manufacturer id and lookup if the type is supported. */ +struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, + struct nand_chip *chip, + int *maf_id, int *dev_id, + struct nand_flash_dev *type); + /* Scan and identify a NAND device */ int nand_scan(struct mtd_info *mtd, int max_chips); /* @@ -247,9 +254,6 @@ typedef enum { #define NAND_CI_CELLTYPE_MSK 0x0C #define NAND_CI_CELLTYPE_SHIFT 2 -/* Keep gcc happy */ -struct nand_chip; - /* ONFI features */ #define ONFI_FEATURE_16_BIT_BUS (1 << 0) #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) diff --git a/include/log.h b/include/log.h index a3edd25546a..3e99d6e62b6 100644 --- a/include/log.h +++ b/include/log.h @@ -274,7 +274,8 @@ struct log_filter { * log_get_cat_name() - Get the name of a category * * @cat: Category to look up - * @return category name (which may be a uclass driver name) + * @return category name (which may be a uclass driver name) if found, or + * "<invalid>" if invalid, or "<missing>" if not found */ const char *log_get_cat_name(enum log_category_t cat); diff --git a/include/net.h b/include/net.h index 57606855564..f9984ae86ca 100644 --- a/include/net.h +++ b/include/net.h @@ -344,6 +344,7 @@ struct vlan_ethernet_hdr { #define PROT_IP 0x0800 /* IP protocol */ #define PROT_ARP 0x0806 /* IP ARP protocol */ +#define PROT_WOL 0x0842 /* ether-wake WoL protocol */ #define PROT_RARP 0x8035 /* IP ARP protocol */ #define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */ #define PROT_IPV6 0x86dd /* IPv6 over bluebook */ @@ -535,10 +536,12 @@ extern int net_restart_wrap; /* Tried all network devices */ enum proto_t { BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP, - TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT + TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL }; extern char net_boot_file_name[1024];/* Boot File name */ +/* Indicates whether the file name was specified on the command line */ +extern bool net_boot_file_name_explicit; /* The actual transferred size of the bootfile (in bytes) */ extern u32 net_boot_file_size; /* Boot file size in blocks as reported by the DHCP server */ diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h index 87ea7cad466..b836d67fb62 100644 --- a/include/power/pfuze3000_pmic.h +++ b/include/power/pfuze3000_pmic.h @@ -69,7 +69,7 @@ enum { PFUZE3000_VLDO3CTL = 0x70, PFUZE3000_VLD4CTL = 0x71, - PMIC_NUM_OF_REGS = 0x7F, + PFUZE3000_NUM_OF_REGS = 0x100, }; int power_pfuze3000_init(unsigned char bus); diff --git a/lib/Kconfig b/lib/Kconfig index dd54516f302..a77bf1c688a 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -187,6 +187,20 @@ config TPM endmenu +menu "Android Verified Boot" + +config LIBAVB + bool "Android Verified Boot 2.0 support" + depends on ANDROID_BOOT_IMAGE + default n + help + This enables support of Android Verified Boot 2.0 which can be used + to assure the end user of the integrity of the software running on a + device. Introduces such features as boot chain of trust, rollback + protection etc. + +endmenu + menu "Hashing Support" config SHA1 diff --git a/lib/Makefile b/lib/Makefile index 427d3591599..5f583aed37d 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o obj-$(CONFIG_$(SPL_)LZO) += lzo/ +obj-$(CONFIG_LIBAVB) += libavb/ obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ diff --git a/lib/efi/Makefile b/lib/efi/Makefile index f1a3929e32b..a790d2d554c 100644 --- a/lib/efi/Makefile +++ b/lib/efi/Makefile @@ -7,11 +7,11 @@ obj-$(CONFIG_EFI_STUB) += efi_info.o CFLAGS_REMOVE_efi_stub.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB \ +CFLAGS_efi_stub.o := -fpic -fshort-wchar \ $(if $(CONFIG_EFI_STUB_64BIT),-m64) CFLAGS_REMOVE_efi.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB \ +CFLAGS_efi.o := -fpic -fshort-wchar \ $(if $(CONFIG_EFI_STUB_64BIT),-m64) extra-$(CONFIG_EFI_STUB) += efi_stub.o efi.o diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c index c8280935c84..3eb8eeb677f 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi/efi_app.c @@ -96,7 +96,8 @@ static void free_memory(struct efi_priv *priv) * U-Boot. If it returns, EFI will continue. Another way to get back to EFI * is via reset_cpu(). */ -efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) +efi_status_t EFIAPI efi_main(efi_handle_t image, + struct efi_system_table *sys_table) { struct efi_priv local_priv, *priv = &local_priv; efi_status_t ret; diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c index 09023a2f67a..1b495ec81b2 100644 --- a/lib/efi/efi_stub.c +++ b/lib/efi/efi_stub.c @@ -268,12 +268,16 @@ static void add_entry_addr(struct efi_priv *priv, enum efi_entry_t type, * This function is called by our EFI start-up code. It handles running * U-Boot. If it returns, EFI will continue. */ -efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) +efi_status_t EFIAPI efi_main(efi_handle_t image, + struct efi_system_table *sys_table) { struct efi_priv local_priv, *priv = &local_priv; struct efi_boot_services *boot = sys_table->boottime; struct efi_mem_desc *desc; struct efi_entry_memmap map; + struct efi_gop *gop; + struct efi_entry_gopmode mode; + efi_guid_t efi_gop_guid = EFI_GOP_GUID; efi_uintn_t key, desc_size, size; efi_status_t ret; u32 version; @@ -312,6 +316,18 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) if (ret) return ret; + ret = boot->locate_protocol(&efi_gop_guid, NULL, (void **)&gop); + if (ret) { + puts(" GOP unavailable\n"); + } else { + mode.fb_base = gop->mode->fb_base; + mode.fb_size = gop->mode->fb_size; + mode.info_size = gop->mode->info_size; + add_entry_addr(priv, EFIET_GOP_MODE, &mode, sizeof(mode), + gop->mode->info, + sizeof(struct efi_gop_mode_info)); + } + ret = boot->get_memory_map(&size, desc, &key, &desc_size, &version); if (ret) { printhex2(ret); @@ -345,14 +361,14 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) } } + /* The EFI UART won't work now, switch to a debug one */ + use_uart = true; + map.version = version; map.desc_size = desc_size; add_entry_addr(priv, EFIET_MEMORY_MAP, &map, sizeof(map), desc, size); add_entry_addr(priv, EFIET_END, NULL, 0, 0, 0); - /* The EFI UART won't work now, switch to a debug one */ - use_uart = true; - memcpy((void *)CONFIG_SYS_TEXT_BASE, _binary_u_boot_bin_start, (ulong)_binary_u_boot_bin_end - (ulong)_binary_u_boot_bin_start); diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index c6046e36d26..d6402c4615f 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -22,4 +22,5 @@ obj-$(CONFIG_LCD) += efi_gop.o obj-$(CONFIG_DM_VIDEO) += efi_gop.o obj-$(CONFIG_PARTITIONS) += efi_disk.o obj-$(CONFIG_NET) += efi_net.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c new file mode 100644 index 00000000000..a4e5e53d15e --- /dev/null +++ b/lib/efi_loader/efi_acpi.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * EFI application ACPI tables support + * + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <efi_loader.h> +#include <asm/acpi_table.h> + +static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; + +/* + * Install the ACPI table as a configuration table. + * + * @return status code + */ +efi_status_t efi_acpi_register(void) +{ + /* Map within the low 32 bits, to allow for 32bit ACPI tables */ + u64 acpi = U32_MAX; + efi_status_t ret; + + /* Reserve 64kiB page for ACPI */ + ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, + EFI_RUNTIME_SERVICES_DATA, 16, &acpi); + if (ret != EFI_SUCCESS) + return ret; + + /* + * Generate ACPI tables - we know that efi_allocate_pages() returns + * a 4k-aligned address, so it is safe to assume that + * write_acpi_tables() will write the table at that address. + */ + assert(!(acpi & 0xf)); + write_acpi_tables(acpi); + + /* And expose them to our EFI payload */ + return efi_install_configuration_table(&acpi_guid, + (void *)(uintptr_t)acpi); +} diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 50d311548e2..261d66d97f7 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -43,7 +43,7 @@ static bool efi_is_direct_boot = true; * In most cases we want to pass an FDT to the payload, so reserve one slot of * config table space for it. The pointer gets populated by do_bootefi_exec(). */ -static struct efi_configuration_table __efi_runtime_data efi_conf_table[2]; +static struct efi_configuration_table __efi_runtime_data efi_conf_table[16]; #ifdef CONFIG_ARM /* diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 1afe8418e12..3a36bbcbfae 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -472,7 +472,7 @@ efi_status_t efi_gop_register(void) gopobj->info.version = 0; gopobj->info.width = col; gopobj->info.height = row; - gopobj->info.pixel_format = EFI_GOT_RGBA8; + gopobj->info.pixel_format = EFI_GOT_BGRA8; gopobj->info.pixels_per_scanline = col; gopobj->bpix = bpix; diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c index 046b46a2c1b..3b8de5b4ea7 100644 --- a/lib/efi_loader/helloworld.c +++ b/lib/efi_loader/helloworld.c @@ -14,6 +14,7 @@ static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID; static const efi_guid_t fdt_guid = EFI_FDT_GUID; +static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID; static int hw_memcmp(const void *buf1, const void *buf2, size_t length) @@ -79,6 +80,9 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, if (!hw_memcmp(&systable->tables[i].guid, &fdt_guid, sizeof(efi_guid_t))) con_out->output_string(con_out, L"Have device tree\n"); + if (!hw_memcmp(&systable->tables[i].guid, &acpi_guid, + sizeof(efi_guid_t))) + con_out->output_string(con_out, L"Have ACPI 2.0 table\n"); if (!hw_memcmp(&systable->tables[i].guid, &smbios_guid, sizeof(efi_guid_t))) con_out->output_string(con_out, L"Have SMBIOS table\n"); diff --git a/lib/libavb/Makefile b/lib/libavb/Makefile new file mode 100644 index 00000000000..b983fe768e5 --- /dev/null +++ b/lib/libavb/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2017 Linaro Limited + +obj-$(CONFIG_LIBAVB) += avb_chain_partition_descriptor.o avb_cmdline.o +obj-$(CONFIG_LIBAVB) += avb_crypto.o avb_footer.o avb_hashtree_descriptor.o +obj-$(CONFIG_LIBAVB) += avb_property_descriptor.o avb_sha256.o +obj-$(CONFIG_LIBAVB) += avb_slot_verify.o avb_util.o avb_version.o +obj-$(CONFIG_LIBAVB) += avb_descriptor.o avb_hash_descriptor.o +obj-$(CONFIG_LIBAVB) += avb_kernel_cmdline_descriptor.o avb_rsa.o avb_sha512.o +obj-$(CONFIG_LIBAVB) += avb_sysdeps_posix.o avb_vbmeta_image.o + +ccflags-y = -DAVB_COMPILATION diff --git a/lib/libavb/avb_chain_partition_descriptor.c b/lib/libavb/avb_chain_partition_descriptor.c new file mode 100644 index 00000000000..e2993063103 --- /dev/null +++ b/lib/libavb/avb_chain_partition_descriptor.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_chain_partition_descriptor.h" +#include "avb_util.h" + +bool avb_chain_partition_descriptor_validate_and_byteswap( + const AvbChainPartitionDescriptor* src, AvbChainPartitionDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbChainPartitionDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_CHAIN_PARTITION) { + avb_error("Invalid tag for chain partition descriptor.\n"); + return false; + } + + dest->rollback_index_location = avb_be32toh(dest->rollback_index_location); + dest->partition_name_len = avb_be32toh(dest->partition_name_len); + dest->public_key_len = avb_be32toh(dest->public_key_len); + + if (dest->rollback_index_location < 1) { + avb_error("Invalid rollback index location value.\n"); + return false; + } + + /* Check that partition_name and public_key are fully contained. */ + expected_size = sizeof(AvbChainPartitionDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->partition_name_len) || + !avb_safe_add_to(&expected_size, dest->public_key_len)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + return true; +} diff --git a/lib/libavb/avb_chain_partition_descriptor.h b/lib/libavb/avb_chain_partition_descriptor.h new file mode 100644 index 00000000000..80e2271782e --- /dev/null +++ b/lib/libavb/avb_chain_partition_descriptor.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_CHAIN_PARTITION_DESCRIPTOR_H_ +#define AVB_CHAIN_PARTITION_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* A descriptor containing a pointer to signed integrity data stored + * on another partition. The descriptor contains the partition name in + * question (without the A/B suffix), the public key used to sign the + * integrity data, and rollback index location to use for rollback + * protection. + * + * Following this struct are |partition_name_len| bytes of the + * partition name (UTF-8 encoded) and |public_key_len| bytes of the + * public key. + * + * The |reserved| field is for future expansion and must be set to NUL + * bytes. + */ +typedef struct AvbChainPartitionDescriptor { + AvbDescriptor parent_descriptor; + uint32_t rollback_index_location; + uint32_t partition_name_len; + uint32_t public_key_len; + uint8_t reserved[64]; +} AVB_ATTR_PACKED AvbChainPartitionDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_chain_partition_descriptor_validate_and_byteswap( + const AvbChainPartitionDescriptor* src, + AvbChainPartitionDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_CHAIN_PARTITION_DESCRIPTOR_H_ */ diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c new file mode 100644 index 00000000000..91a6615c740 --- /dev/null +++ b/lib/libavb/avb_cmdline.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_cmdline.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_version.h" + +#define NUM_GUIDS 3 + +/* Substitutes all variables (e.g. $(ANDROID_SYSTEM_PARTUUID)) with + * values. Returns NULL on OOM, otherwise the cmdline with values + * replaced. + */ +char* avb_sub_cmdline(AvbOps* ops, + const char* cmdline, + const char* ab_suffix, + bool using_boot_for_vbmeta, + const AvbCmdlineSubstList* additional_substitutions) { + const char* part_name_str[NUM_GUIDS] = {"system", "boot", "vbmeta"}; + const char* replace_str[NUM_GUIDS] = {"$(ANDROID_SYSTEM_PARTUUID)", + "$(ANDROID_BOOT_PARTUUID)", + "$(ANDROID_VBMETA_PARTUUID)"}; + char* ret = NULL; + AvbIOResult io_ret; + size_t n; + + /* Special-case for when the top-level vbmeta struct is in the boot + * partition. + */ + if (using_boot_for_vbmeta) { + part_name_str[2] = "boot"; + } + + /* Replace unique partition GUIDs */ + for (n = 0; n < NUM_GUIDS; n++) { + char part_name[AVB_PART_NAME_MAX_SIZE]; + char guid_buf[37]; + + if (!avb_str_concat(part_name, + sizeof part_name, + part_name_str[n], + avb_strlen(part_name_str[n]), + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + goto fail; + } + + io_ret = ops->get_unique_guid_for_partition( + ops, part_name, guid_buf, sizeof guid_buf); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + goto fail; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting unique GUID for partition.\n"); + goto fail; + } + + if (ret == NULL) { + ret = avb_replace(cmdline, replace_str[n], guid_buf); + } else { + char* new_ret = avb_replace(ret, replace_str[n], guid_buf); + avb_free(ret); + ret = new_ret; + } + if (ret == NULL) { + goto fail; + } + } + + avb_assert(ret != NULL); + + /* Replace any additional substitutions. */ + if (additional_substitutions != NULL) { + for (n = 0; n < additional_substitutions->size; ++n) { + char* new_ret = avb_replace(ret, + additional_substitutions->tokens[n], + additional_substitutions->values[n]); + avb_free(ret); + ret = new_ret; + if (ret == NULL) { + goto fail; + } + } + } + + return ret; + +fail: + if (ret != NULL) { + avb_free(ret); + } + return NULL; +} + +static int cmdline_append_option(AvbSlotVerifyData* slot_data, + const char* key, + const char* value) { + size_t offset, key_len, value_len; + char* new_cmdline; + + key_len = avb_strlen(key); + value_len = avb_strlen(value); + + offset = 0; + if (slot_data->cmdline != NULL) { + offset = avb_strlen(slot_data->cmdline); + if (offset > 0) { + offset += 1; + } + } + + new_cmdline = avb_calloc(offset + key_len + value_len + 2); + if (new_cmdline == NULL) { + return 0; + } + if (offset > 0) { + avb_memcpy(new_cmdline, slot_data->cmdline, offset - 1); + new_cmdline[offset - 1] = ' '; + } + avb_memcpy(new_cmdline + offset, key, key_len); + new_cmdline[offset + key_len] = '='; + avb_memcpy(new_cmdline + offset + key_len + 1, value, value_len); + if (slot_data->cmdline != NULL) { + avb_free(slot_data->cmdline); + } + slot_data->cmdline = new_cmdline; + + return 1; +} + +#define AVB_MAX_DIGITS_UINT64 32 + +/* Writes |value| to |digits| in base 10 followed by a NUL byte. + * Returns number of characters written excluding the NUL byte. + */ +static size_t uint64_to_base10(uint64_t value, + char digits[AVB_MAX_DIGITS_UINT64]) { + char rev_digits[AVB_MAX_DIGITS_UINT64]; + size_t n, num_digits; + + for (num_digits = 0; num_digits < AVB_MAX_DIGITS_UINT64 - 1;) { + rev_digits[num_digits++] = avb_div_by_10(&value) + '0'; + if (value == 0) { + break; + } + } + + for (n = 0; n < num_digits; n++) { + digits[n] = rev_digits[num_digits - 1 - n]; + } + digits[n] = '\0'; + return n; +} + +static int cmdline_append_version(AvbSlotVerifyData* slot_data, + const char* key, + uint64_t major_version, + uint64_t minor_version) { + char major_digits[AVB_MAX_DIGITS_UINT64]; + char minor_digits[AVB_MAX_DIGITS_UINT64]; + char combined[AVB_MAX_DIGITS_UINT64 * 2 + 1]; + size_t num_major_digits, num_minor_digits; + + num_major_digits = uint64_to_base10(major_version, major_digits); + num_minor_digits = uint64_to_base10(minor_version, minor_digits); + avb_memcpy(combined, major_digits, num_major_digits); + combined[num_major_digits] = '.'; + avb_memcpy(combined + num_major_digits + 1, minor_digits, num_minor_digits); + combined[num_major_digits + 1 + num_minor_digits] = '\0'; + + return cmdline_append_option(slot_data, key, combined); +} + +static int cmdline_append_uint64_base10(AvbSlotVerifyData* slot_data, + const char* key, + uint64_t value) { + char digits[AVB_MAX_DIGITS_UINT64]; + uint64_to_base10(value, digits); + return cmdline_append_option(slot_data, key, digits); +} + +static int cmdline_append_hex(AvbSlotVerifyData* slot_data, + const char* key, + const uint8_t* data, + size_t data_len) { + int ret; + char* hex_data = avb_bin2hex(data, data_len); + if (hex_data == NULL) { + return 0; + } + ret = cmdline_append_option(slot_data, key, hex_data); + avb_free(hex_data); + return ret; +} + +AvbSlotVerifyResult avb_append_options( + AvbOps* ops, + AvbSlotVerifyData* slot_data, + AvbVBMetaImageHeader* toplevel_vbmeta, + AvbAlgorithmType algorithm_type, + AvbHashtreeErrorMode hashtree_error_mode) { + AvbSlotVerifyResult ret; + const char* verity_mode; + bool is_device_unlocked; + AvbIOResult io_ret; + + /* Add androidboot.vbmeta.device option. */ + if (!cmdline_append_option(slot_data, + "androidboot.vbmeta.device", + "PARTUUID=$(ANDROID_VBMETA_PARTUUID)")) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + /* Add androidboot.vbmeta.avb_version option. */ + if (!cmdline_append_version(slot_data, + "androidboot.vbmeta.avb_version", + AVB_VERSION_MAJOR, + AVB_VERSION_MINOR)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + /* Set androidboot.avb.device_state to "locked" or "unlocked". */ + io_ret = ops->read_is_device_unlocked(ops, &is_device_unlocked); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting device state.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + if (!cmdline_append_option(slot_data, + "androidboot.vbmeta.device_state", + is_device_unlocked ? "unlocked" : "locked")) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + /* Set androidboot.vbmeta.{hash_alg, size, digest} - use same hash + * function as is used to sign vbmeta. + */ + switch (algorithm_type) { + /* Explicit fallthrough. */ + case AVB_ALGORITHM_TYPE_NONE: + case AVB_ALGORITHM_TYPE_SHA256_RSA2048: + case AVB_ALGORITHM_TYPE_SHA256_RSA4096: + case AVB_ALGORITHM_TYPE_SHA256_RSA8192: { + size_t n, total_size = 0; + uint8_t vbmeta_digest[AVB_SHA256_DIGEST_SIZE]; + avb_slot_verify_data_calculate_vbmeta_digest( + slot_data, AVB_DIGEST_TYPE_SHA256, vbmeta_digest); + for (n = 0; n < slot_data->num_vbmeta_images; n++) { + total_size += slot_data->vbmeta_images[n].vbmeta_size; + } + if (!cmdline_append_option( + slot_data, "androidboot.vbmeta.hash_alg", "sha256") || + !cmdline_append_uint64_base10( + slot_data, "androidboot.vbmeta.size", total_size) || + !cmdline_append_hex(slot_data, + "androidboot.vbmeta.digest", + vbmeta_digest, + AVB_SHA256_DIGEST_SIZE)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + } break; + /* Explicit fallthrough. */ + case AVB_ALGORITHM_TYPE_SHA512_RSA2048: + case AVB_ALGORITHM_TYPE_SHA512_RSA4096: + case AVB_ALGORITHM_TYPE_SHA512_RSA8192: { + size_t n, total_size = 0; + uint8_t vbmeta_digest[AVB_SHA512_DIGEST_SIZE]; + avb_slot_verify_data_calculate_vbmeta_digest( + slot_data, AVB_DIGEST_TYPE_SHA512, vbmeta_digest); + for (n = 0; n < slot_data->num_vbmeta_images; n++) { + total_size += slot_data->vbmeta_images[n].vbmeta_size; + } + if (!cmdline_append_option( + slot_data, "androidboot.vbmeta.hash_alg", "sha512") || + !cmdline_append_uint64_base10( + slot_data, "androidboot.vbmeta.size", total_size) || + !cmdline_append_hex(slot_data, + "androidboot.vbmeta.digest", + vbmeta_digest, + AVB_SHA512_DIGEST_SIZE)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + } break; + case _AVB_ALGORITHM_NUM_TYPES: + avb_assert_not_reached(); + break; + } + + /* Set androidboot.veritymode and androidboot.vbmeta.invalidate_on_error */ + if (toplevel_vbmeta->flags & AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED) { + verity_mode = "disabled"; + } else { + const char* dm_verity_mode; + char* new_ret; + + switch (hashtree_error_mode) { + case AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE: + if (!cmdline_append_option( + slot_data, "androidboot.vbmeta.invalidate_on_error", "yes")) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + verity_mode = "enforcing"; + dm_verity_mode = "restart_on_corruption"; + break; + case AVB_HASHTREE_ERROR_MODE_RESTART: + verity_mode = "enforcing"; + dm_verity_mode = "restart_on_corruption"; + break; + case AVB_HASHTREE_ERROR_MODE_EIO: + verity_mode = "eio"; + /* For now there's no option to specify the EIO mode. So + * just use 'ignore_zero_blocks' since that's already set + * and dm-verity-target.c supports specifying this multiple + * times. + */ + dm_verity_mode = "ignore_zero_blocks"; + break; + case AVB_HASHTREE_ERROR_MODE_LOGGING: + verity_mode = "logging"; + dm_verity_mode = "ignore_corruption"; + break; + } + new_ret = avb_replace( + slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode); + avb_free(slot_data->cmdline); + slot_data->cmdline = new_ret; + if (slot_data->cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + } + if (!cmdline_append_option( + slot_data, "androidboot.veritymode", verity_mode)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + ret = AVB_SLOT_VERIFY_RESULT_OK; + +out: + + return ret; +} + +AvbCmdlineSubstList* avb_new_cmdline_subst_list() { + return (AvbCmdlineSubstList*)avb_calloc(sizeof(AvbCmdlineSubstList)); +} + +void avb_free_cmdline_subst_list(AvbCmdlineSubstList* cmdline_subst) { + size_t i; + for (i = 0; i < cmdline_subst->size; ++i) { + avb_free(cmdline_subst->tokens[i]); + avb_free(cmdline_subst->values[i]); + } + cmdline_subst->size = 0; + avb_free(cmdline_subst); +} + +AvbSlotVerifyResult avb_add_root_digest_substitution( + const char* part_name, + const uint8_t* digest, + size_t digest_size, + AvbCmdlineSubstList* out_cmdline_subst) { + const char* kDigestSubPrefix = "$(AVB_"; + const char* kDigestSubSuffix = "_ROOT_DIGEST)"; + size_t part_name_len = avb_strlen(part_name); + size_t list_index = out_cmdline_subst->size; + + avb_assert(part_name_len < AVB_PART_NAME_MAX_SIZE); + avb_assert(digest_size <= AVB_SHA512_DIGEST_SIZE); + if (part_name_len >= AVB_PART_NAME_MAX_SIZE || + digest_size > AVB_SHA512_DIGEST_SIZE) { + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + + if (out_cmdline_subst->size >= AVB_MAX_NUM_CMDLINE_SUBST) { + /* The list is full. Currently dynamic growth of this list is not supported. + */ + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + + /* Construct the token to replace in the command line based on the partition + * name. For partition 'foo', this will be '$(AVB_FOO_ROOT_DIGEST)'. + */ + out_cmdline_subst->tokens[list_index] = + avb_strdupv(kDigestSubPrefix, part_name, kDigestSubSuffix, NULL); + if (out_cmdline_subst->tokens[list_index] == NULL) { + goto fail; + } + avb_uppercase(out_cmdline_subst->tokens[list_index]); + + /* The digest value is hex encoded when inserted in the command line. */ + out_cmdline_subst->values[list_index] = avb_bin2hex(digest, digest_size); + if (out_cmdline_subst->values[list_index] == NULL) { + goto fail; + } + + out_cmdline_subst->size++; + return AVB_SLOT_VERIFY_RESULT_OK; + +fail: + if (out_cmdline_subst->tokens[list_index]) { + avb_free(out_cmdline_subst->tokens[list_index]); + } + if (out_cmdline_subst->values[list_index]) { + avb_free(out_cmdline_subst->values[list_index]); + } + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; +} diff --git a/lib/libavb/avb_cmdline.h b/lib/libavb/avb_cmdline.h new file mode 100644 index 00000000000..9af3a999942 --- /dev/null +++ b/lib/libavb/avb_cmdline.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#ifdef AVB_INSIDE_LIBAVB_H +#error "You can't include avb_sha.h in the public header libavb.h." +#endif + +#ifndef AVB_COMPILATION +#error "Never include this file, it may only be used from internal avb code." +#endif + +#ifndef AVB_CMDLINE_H_ +#define AVB_CMDLINE_H_ + +#include "avb_ops.h" +#include "avb_slot_verify.h" + +/* Maximum allow length (in bytes) of a partition name, including + * ab_suffix. + */ +#define AVB_PART_NAME_MAX_SIZE 32 + +#define AVB_MAX_NUM_CMDLINE_SUBST 10 + +/* Holds information about command-line substitutions. */ +typedef struct AvbCmdlineSubstList { + size_t size; + char* tokens[AVB_MAX_NUM_CMDLINE_SUBST]; + char* values[AVB_MAX_NUM_CMDLINE_SUBST]; +} AvbCmdlineSubstList; + +/* Substitutes all variables (e.g. $(ANDROID_SYSTEM_PARTUUID)) with + * values. Returns NULL on OOM, otherwise the cmdline with values + * replaced. + */ +char* avb_sub_cmdline(AvbOps* ops, + const char* cmdline, + const char* ab_suffix, + bool using_boot_for_vbmeta, + const AvbCmdlineSubstList* additional_substitutions); + +AvbSlotVerifyResult avb_append_options( + AvbOps* ops, + AvbSlotVerifyData* slot_data, + AvbVBMetaImageHeader* toplevel_vbmeta, + AvbAlgorithmType algorithm_type, + AvbHashtreeErrorMode hashtree_error_mode); + +/* Allocates and initializes a new command line substitution list. Free with + * |avb_free_cmdline_subst_list|. + */ +AvbCmdlineSubstList* avb_new_cmdline_subst_list(void); + +/* Use this instead of |avb_free| to deallocate a AvbCmdlineSubstList. */ +void avb_free_cmdline_subst_list(AvbCmdlineSubstList* cmdline_subst); + +/* Adds a hashtree root digest to be substituted in $(AVB_*_ROOT_DIGEST) + * variables. The partition name differentiates the variable. For example, if + * |part_name| is "foo" then $(AVB_FOO_ROOT_DIGEST) will be substituted with the + * hex encoding of the digest. The substitution will be added to + * |out_cmdline_subst|. Returns AVB_SLOT_VERIFY_RESULT_OK on success. + */ +AvbSlotVerifyResult avb_add_root_digest_substitution( + const char* part_name, + const uint8_t* digest, + size_t digest_size, + AvbCmdlineSubstList* out_cmdline_subst); + +#endif diff --git a/lib/libavb/avb_crypto.c b/lib/libavb/avb_crypto.c new file mode 100644 index 00000000000..f1836d5fc31 --- /dev/null +++ b/lib/libavb/avb_crypto.c @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_crypto.h" +#include "avb_rsa.h" +#include "avb_sha.h" +#include "avb_util.h" + +/* NOTE: The PKC1-v1.5 padding is a blob of binary DER of ASN.1 and is + * obtained from section 5.2.2 of RFC 4880. + */ + +static const uint8_t + padding_RSA2048_SHA256[AVB_RSA2048_NUM_BYTES - AVB_SHA256_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; + +static const uint8_t + padding_RSA4096_SHA256[AVB_RSA4096_NUM_BYTES - AVB_SHA256_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; + +static const uint8_t + padding_RSA8192_SHA256[AVB_RSA8192_NUM_BYTES - AVB_SHA256_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; + +static const uint8_t + padding_RSA2048_SHA512[AVB_RSA2048_NUM_BYTES - AVB_SHA512_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, 0x00, 0x04, 0x40}; + +static const uint8_t + padding_RSA4096_SHA512[AVB_RSA4096_NUM_BYTES - AVB_SHA512_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x51, 0x30, + 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, + 0x05, 0x00, 0x04, 0x40}; + +static const uint8_t + padding_RSA8192_SHA512[AVB_RSA8192_NUM_BYTES - AVB_SHA512_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, 0x00, 0x04, 0x40}; + +static AvbAlgorithmData algorithm_data[_AVB_ALGORITHM_NUM_TYPES] = { + /* AVB_ALGORITHM_TYPE_NONE */ + {.padding = NULL, .padding_len = 0, .hash_len = 0}, + /* AVB_ALGORITHM_TYPE_SHA256_RSA2048 */ + {.padding = padding_RSA2048_SHA256, + .padding_len = sizeof(padding_RSA2048_SHA256), + .hash_len = AVB_SHA256_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA256_RSA4096 */ + {.padding = padding_RSA4096_SHA256, + .padding_len = sizeof(padding_RSA4096_SHA256), + .hash_len = AVB_SHA256_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA256_RSA8192 */ + {.padding = padding_RSA8192_SHA256, + .padding_len = sizeof(padding_RSA8192_SHA256), + .hash_len = AVB_SHA256_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA512_RSA2048 */ + {.padding = padding_RSA2048_SHA512, + .padding_len = sizeof(padding_RSA2048_SHA512), + .hash_len = AVB_SHA512_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA512_RSA4096 */ + {.padding = padding_RSA4096_SHA512, + .padding_len = sizeof(padding_RSA4096_SHA512), + .hash_len = AVB_SHA512_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA512_RSA8192 */ + {.padding = padding_RSA8192_SHA512, + .padding_len = sizeof(padding_RSA8192_SHA512), + .hash_len = AVB_SHA512_DIGEST_SIZE}, +}; + +const AvbAlgorithmData* avb_get_algorithm_data(AvbAlgorithmType algorithm) { + if ((size_t)algorithm < _AVB_ALGORITHM_NUM_TYPES) { + return &algorithm_data[algorithm]; + } + return NULL; +} + +bool avb_rsa_public_key_header_validate_and_byteswap( + const AvbRSAPublicKeyHeader* src, AvbRSAPublicKeyHeader* dest) { + avb_memcpy(dest, src, sizeof(AvbRSAPublicKeyHeader)); + + dest->key_num_bits = avb_be32toh(dest->key_num_bits); + dest->n0inv = avb_be32toh(dest->n0inv); + + return true; +} diff --git a/lib/libavb/avb_crypto.h b/lib/libavb/avb_crypto.h new file mode 100644 index 00000000000..d8f649b137c --- /dev/null +++ b/lib/libavb/avb_crypto.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_CRYPTO_H_ +#define AVB_CRYPTO_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Size of a RSA-2048 signature. */ +#define AVB_RSA2048_NUM_BYTES 256 + +/* Size of a RSA-4096 signature. */ +#define AVB_RSA4096_NUM_BYTES 512 + +/* Size of a RSA-8192 signature. */ +#define AVB_RSA8192_NUM_BYTES 1024 + +/* Size in bytes of a SHA-1 digest. */ +#define AVB_SHA1_DIGEST_SIZE 20 + +/* Size in bytes of a SHA-256 digest. */ +#define AVB_SHA256_DIGEST_SIZE 32 + +/* Size in bytes of a SHA-512 digest. */ +#define AVB_SHA512_DIGEST_SIZE 64 + +/* Possible digest types supported by libavb routines. */ +typedef enum { + AVB_DIGEST_TYPE_SHA256, + AVB_DIGEST_TYPE_SHA512, +} AvbDigestType; + +/* Algorithms that can be used in the vbmeta image for + * verification. An algorithm consists of a hash type and a signature + * type. + * + * The data used to calculate the hash is the three blocks mentioned + * in the documentation for |AvbVBMetaImageHeader| except for the data + * in the "Authentication data" block. + * + * For signatures with RSA keys, PKCS v1.5 padding is used. The public + * key data is stored in the auxiliary data block, see + * |AvbRSAPublicKeyHeader| for the serialization format. + * + * Each algorithm type is described below: + * + * AVB_ALGORITHM_TYPE_NONE: There is no hash, no signature of the + * data, and no public key. The data cannot be verified. The fields + * |hash_size|, |signature_size|, and |public_key_size| must be zero. + * + * AVB_ALGORITHM_TYPE_SHA256_RSA2048: The hash function used is + * SHA-256, resulting in 32 bytes of hash digest data. This hash is + * signed with a 2048-bit RSA key. The field |hash_size| must be 32, + * |signature_size| must be 256, and the public key data must have + * |key_num_bits| set to 2048. + * + * AVB_ALGORITHM_TYPE_SHA256_RSA4096: Like above, but only with + * a 4096-bit RSA key and |signature_size| set to 512. + * + * AVB_ALGORITHM_TYPE_SHA256_RSA8192: Like above, but only with + * a 8192-bit RSA key and |signature_size| set to 1024. + * + * AVB_ALGORITHM_TYPE_SHA512_RSA2048: The hash function used is + * SHA-512, resulting in 64 bytes of hash digest data. This hash is + * signed with a 2048-bit RSA key. The field |hash_size| must be 64, + * |signature_size| must be 256, and the public key data must have + * |key_num_bits| set to 2048. + * + * AVB_ALGORITHM_TYPE_SHA512_RSA4096: Like above, but only with + * a 4096-bit RSA key and |signature_size| set to 512. + * + * AVB_ALGORITHM_TYPE_SHA512_RSA8192: Like above, but only with + * a 8192-bit RSA key and |signature_size| set to 1024. + */ +typedef enum { + AVB_ALGORITHM_TYPE_NONE, + AVB_ALGORITHM_TYPE_SHA256_RSA2048, + AVB_ALGORITHM_TYPE_SHA256_RSA4096, + AVB_ALGORITHM_TYPE_SHA256_RSA8192, + AVB_ALGORITHM_TYPE_SHA512_RSA2048, + AVB_ALGORITHM_TYPE_SHA512_RSA4096, + AVB_ALGORITHM_TYPE_SHA512_RSA8192, + _AVB_ALGORITHM_NUM_TYPES +} AvbAlgorithmType; + +/* Holds algorithm-specific data. The |padding| is needed by avb_rsa_verify. */ +typedef struct { + const uint8_t* padding; + size_t padding_len; + size_t hash_len; +} AvbAlgorithmData; + +/* Provides algorithm-specific data for a given |algorithm|. Returns NULL if + * |algorithm| is invalid. + */ +const AvbAlgorithmData* avb_get_algorithm_data(AvbAlgorithmType algorithm) + AVB_ATTR_WARN_UNUSED_RESULT; + +/* The header for a serialized RSA public key. + * + * The size of the key is given by |key_num_bits|, for example 2048 + * for a RSA-2048 key. By definition, a RSA public key is the pair (n, + * e) where |n| is the modulus (which can be represented in + * |key_num_bits| bits) and |e| is the public exponent. The exponent + * is not stored since it's assumed to always be 65537. + * + * To optimize verification, the key block includes two precomputed + * values, |n0inv| (fits in 32 bits) and |rr| and can always be + * represented in |key_num_bits|. + + * The value |n0inv| is the value -1/n[0] (mod 2^32). The value |rr| + * is (2^key_num_bits)^2 (mod n). + * + * Following this header is |key_num_bits| bits of |n|, then + * |key_num_bits| bits of |rr|. Both values are stored with most + * significant bit first. Each serialized number takes up + * |key_num_bits|/8 bytes. + * + * All fields in this struct are stored in network byte order when + * serialized. To generate a copy with fields swapped to native byte + * order, use the function avb_rsa_public_key_header_validate_and_byteswap(). + * + * The avb_rsa_verify() function expects a key in this serialized + * format. + * + * The 'avbtool extract_public_key' command can be used to generate a + * serialized RSA public key. + */ +typedef struct AvbRSAPublicKeyHeader { + uint32_t key_num_bits; + uint32_t n0inv; +} AVB_ATTR_PACKED AvbRSAPublicKeyHeader; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + */ +bool avb_rsa_public_key_header_validate_and_byteswap( + const AvbRSAPublicKeyHeader* src, + AvbRSAPublicKeyHeader* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_CRYPTO_H_ */ diff --git a/lib/libavb/avb_descriptor.c b/lib/libavb/avb_descriptor.c new file mode 100644 index 00000000000..fb0b305f2cc --- /dev/null +++ b/lib/libavb/avb_descriptor.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_descriptor.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" + +bool avb_descriptor_validate_and_byteswap(const AvbDescriptor* src, + AvbDescriptor* dest) { + dest->tag = avb_be64toh(src->tag); + dest->num_bytes_following = avb_be64toh(src->num_bytes_following); + + if ((dest->num_bytes_following & 0x07) != 0) { + avb_error("Descriptor size is not divisible by 8.\n"); + return false; + } + return true; +} + +bool avb_descriptor_foreach(const uint8_t* image_data, + size_t image_size, + AvbDescriptorForeachFunc foreach_func, + void* user_data) { + const AvbVBMetaImageHeader* header = NULL; + bool ret = false; + const uint8_t* image_end; + const uint8_t* desc_start; + const uint8_t* desc_end; + const uint8_t* p; + + if (image_data == NULL) { + avb_error("image_data is NULL\n."); + goto out; + } + + if (foreach_func == NULL) { + avb_error("foreach_func is NULL\n."); + goto out; + } + + if (image_size < sizeof(AvbVBMetaImageHeader)) { + avb_error("Length is smaller than header.\n"); + goto out; + } + + /* Ensure magic is correct. */ + if (avb_memcmp(image_data, AVB_MAGIC, AVB_MAGIC_LEN) != 0) { + avb_error("Magic is incorrect.\n"); + goto out; + } + + /* Careful, not byteswapped - also ensure it's aligned properly. */ + avb_assert_aligned(image_data); + header = (const AvbVBMetaImageHeader*)image_data; + image_end = image_data + image_size; + + desc_start = image_data + sizeof(AvbVBMetaImageHeader) + + avb_be64toh(header->authentication_data_block_size) + + avb_be64toh(header->descriptors_offset); + + desc_end = desc_start + avb_be64toh(header->descriptors_size); + + if (desc_start < image_data || desc_start > image_end || + desc_end < image_data || desc_end > image_end || desc_end < desc_start) { + avb_error("Descriptors not inside passed-in data.\n"); + goto out; + } + + for (p = desc_start; p < desc_end;) { + const AvbDescriptor* dh = (const AvbDescriptor*)p; + avb_assert_aligned(dh); + uint64_t nb_following = avb_be64toh(dh->num_bytes_following); + uint64_t nb_total = sizeof(AvbDescriptor) + nb_following; + + if ((nb_total & 7) != 0) { + avb_error("Invalid descriptor length.\n"); + goto out; + } + + if (nb_total + p < desc_start || nb_total + p > desc_end) { + avb_error("Invalid data in descriptors array.\n"); + goto out; + } + + if (foreach_func(dh, user_data) == 0) { + goto out; + } + + p += nb_total; + } + + ret = true; + +out: + return ret; +} + +static bool count_descriptors(const AvbDescriptor* descriptor, + void* user_data) { + size_t* num_descriptors = user_data; + *num_descriptors += 1; + return true; +} + +typedef struct { + size_t descriptor_number; + const AvbDescriptor** descriptors; +} SetDescriptorData; + +static bool set_descriptors(const AvbDescriptor* descriptor, void* user_data) { + SetDescriptorData* data = user_data; + data->descriptors[data->descriptor_number++] = descriptor; + return true; +} + +const AvbDescriptor** avb_descriptor_get_all(const uint8_t* image_data, + size_t image_size, + size_t* out_num_descriptors) { + size_t num_descriptors = 0; + SetDescriptorData data; + + avb_descriptor_foreach( + image_data, image_size, count_descriptors, &num_descriptors); + + data.descriptor_number = 0; + data.descriptors = + avb_calloc(sizeof(const AvbDescriptor*) * (num_descriptors + 1)); + if (data.descriptors == NULL) { + return NULL; + } + avb_descriptor_foreach(image_data, image_size, set_descriptors, &data); + avb_assert(data.descriptor_number == num_descriptors); + + if (out_num_descriptors != NULL) { + *out_num_descriptors = num_descriptors; + } + + return data.descriptors; +} diff --git a/lib/libavb/avb_descriptor.h b/lib/libavb/avb_descriptor.h new file mode 100644 index 00000000000..d4f42ac964a --- /dev/null +++ b/lib/libavb/avb_descriptor.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_DESCRIPTOR_H_ +#define AVB_DESCRIPTOR_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Well-known descriptor tags. + * + * AVB_DESCRIPTOR_TAG_PROPERTY: see |AvbPropertyDescriptor| struct. + * AVB_DESCRIPTOR_TAG_HASHTREE: see |AvbHashtreeDescriptor| struct. + * AVB_DESCRIPTOR_TAG_HASH: see |AvbHashDescriptor| struct. + * AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE: see |AvbKernelCmdlineDescriptor| struct. + * AVB_DESCRIPTOR_TAG_CHAIN_PARTITION: see |AvbChainPartitionDescriptor| struct. + */ +typedef enum { + AVB_DESCRIPTOR_TAG_PROPERTY, + AVB_DESCRIPTOR_TAG_HASHTREE, + AVB_DESCRIPTOR_TAG_HASH, + AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE, + AVB_DESCRIPTOR_TAG_CHAIN_PARTITION, +} AvbDescriptorTag; + +/* The header for a serialized descriptor. + * + * A descriptor always have two fields, a |tag| (denoting its type, + * see the |AvbDescriptorTag| enumeration) and the size of the bytes + * following, |num_bytes_following|. + * + * For padding, |num_bytes_following| is always a multiple of 8. + */ +typedef struct AvbDescriptor { + uint64_t tag; + uint64_t num_bytes_following; +} AVB_ATTR_PACKED AvbDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_descriptor_validate_and_byteswap( + const AvbDescriptor* src, AvbDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Signature for callback function used in avb_descriptor_foreach(). + * The passed in descriptor is given by |descriptor| and the + * |user_data| passed to avb_descriptor_foreach() function is in + * |user_data|. Return true to continue iterating, false to stop + * iterating. + * + * Note that |descriptor| points into the image passed to + * avb_descriptor_foreach() - all fields need to be byteswapped! + */ +typedef bool AvbDescriptorForeachFunc(const AvbDescriptor* descriptor, + void* user_data); + +/* Convenience function to iterate over all descriptors in an vbmeta + * image. + * + * The function given by |foreach_func| will be called for each + * descriptor. The given function should return true to continue + * iterating, false to stop. + * + * The |user_data| parameter will be passed to |foreach_func|. + * + * Returns false if the iteration was short-circuited, that is if + * an invocation of |foreach_func| returned false. + * + * Before using this function, you MUST verify |image_data| with + * avb_vbmeta_image_verify() and reject it unless it's signed by a known + * good public key. Additionally, |image_data| must be word-aligned. + */ +bool avb_descriptor_foreach(const uint8_t* image_data, + size_t image_size, + AvbDescriptorForeachFunc foreach_func, + void* user_data); + +/* Gets all descriptors in a vbmeta image. + * + * The return value is a NULL-pointer terminated array of + * AvbDescriptor pointers. Free with avb_free() when you are done with + * it. If |out_num_descriptors| is non-NULL, the number of descriptors + * will be returned there. + * + * Note that each AvbDescriptor pointer in the array points into + * |image_data| - all fields need to be byteswapped! + * + * Before using this function, you MUST verify |image_data| with + * avb_vbmeta_image_verify() and reject it unless it's signed by a known + * good public key. Additionally, |image_data| must be word-aligned. + */ +const AvbDescriptor** avb_descriptor_get_all(const uint8_t* image_data, + size_t image_size, + size_t* out_num_descriptors) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_DESCRIPTOR_H_ */ diff --git a/lib/libavb/avb_footer.c b/lib/libavb/avb_footer.c new file mode 100644 index 00000000000..697a7152175 --- /dev/null +++ b/lib/libavb/avb_footer.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_footer.h" +#include "avb_util.h" + +bool avb_footer_validate_and_byteswap(const AvbFooter* src, AvbFooter* dest) { + avb_memcpy(dest, src, sizeof(AvbFooter)); + + dest->version_major = avb_be32toh(dest->version_major); + dest->version_minor = avb_be32toh(dest->version_minor); + + dest->original_image_size = avb_be64toh(dest->original_image_size); + dest->vbmeta_offset = avb_be64toh(dest->vbmeta_offset); + dest->vbmeta_size = avb_be64toh(dest->vbmeta_size); + + /* Check that magic is correct. */ + if (avb_safe_memcmp(dest->magic, AVB_FOOTER_MAGIC, AVB_FOOTER_MAGIC_LEN) != + 0) { + avb_error("Footer magic is incorrect.\n"); + return false; + } + + /* Ensure we don't attempt to access any fields if the footer major + * version is not supported. + */ + if (dest->version_major > AVB_FOOTER_VERSION_MAJOR) { + avb_error("No support for footer version.\n"); + return false; + } + + return true; +} diff --git a/lib/libavb/avb_footer.h b/lib/libavb/avb_footer.h new file mode 100644 index 00000000000..62a6e658d1b --- /dev/null +++ b/lib/libavb/avb_footer.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_FOOTER_H_ +#define AVB_FOOTER_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Magic for the footer. */ +#define AVB_FOOTER_MAGIC "AVBf" +#define AVB_FOOTER_MAGIC_LEN 4 + +/* Size of the footer. */ +#define AVB_FOOTER_SIZE 64 + +/* The current footer version used - keep in sync with avbtool. */ +#define AVB_FOOTER_VERSION_MAJOR 1 +#define AVB_FOOTER_VERSION_MINOR 0 + +/* The struct used as a footer used on partitions, used to find the + * AvbVBMetaImageHeader struct. This struct is always stored at the + * end of a partition. + */ +typedef struct AvbFooter { + /* 0: Four bytes equal to "AVBf" (AVB_FOOTER_MAGIC). */ + uint8_t magic[AVB_FOOTER_MAGIC_LEN]; + /* 4: The major version of the footer struct. */ + uint32_t version_major; + /* 8: The minor version of the footer struct. */ + uint32_t version_minor; + + /* 12: The original size of the image on the partition. */ + uint64_t original_image_size; + + /* 20: The offset of the |AvbVBMetaImageHeader| struct. */ + uint64_t vbmeta_offset; + + /* 28: The size of the vbmeta block (header + auth + aux blocks). */ + uint64_t vbmeta_size; + + /* 36: Padding to ensure struct is size AVB_FOOTER_SIZE bytes. This + * must be set to zeroes. + */ + uint8_t reserved[28]; +} AVB_ATTR_PACKED AvbFooter; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + */ +bool avb_footer_validate_and_byteswap(const AvbFooter* src, AvbFooter* dest) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_FOOTER_H_ */ diff --git a/lib/libavb/avb_hash_descriptor.c b/lib/libavb/avb_hash_descriptor.c new file mode 100644 index 00000000000..cd1438e0cd8 --- /dev/null +++ b/lib/libavb/avb_hash_descriptor.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_hash_descriptor.h" +#include "avb_util.h" + +bool avb_hash_descriptor_validate_and_byteswap(const AvbHashDescriptor* src, + AvbHashDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbHashDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_HASH) { + avb_error("Invalid tag for hash descriptor.\n"); + return false; + } + + dest->image_size = avb_be64toh(dest->image_size); + dest->partition_name_len = avb_be32toh(dest->partition_name_len); + dest->salt_len = avb_be32toh(dest->salt_len); + dest->digest_len = avb_be32toh(dest->digest_len); + dest->flags = avb_be32toh(dest->flags); + + /* Check that partition_name, salt, and digest are fully contained. */ + expected_size = sizeof(AvbHashDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->partition_name_len) || + !avb_safe_add_to(&expected_size, dest->salt_len) || + !avb_safe_add_to(&expected_size, dest->digest_len)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + return true; +} diff --git a/lib/libavb/avb_hash_descriptor.h b/lib/libavb/avb_hash_descriptor.h new file mode 100644 index 00000000000..bede97f818f --- /dev/null +++ b/lib/libavb/avb_hash_descriptor.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_HASH_DESCRIPTOR_H_ +#define AVB_HASH_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flags for hash descriptors. + * + * AVB_HASH_DESCRIPTOR_FLAGS_DO_NOT_USE_AB: Do not apply the default A/B + * partition logic to this partition. This is intentionally a negative boolean + * because A/B should be both the default and most used in practice. + */ +typedef enum { + AVB_HASH_DESCRIPTOR_FLAGS_DO_NOT_USE_AB = (1 << 0), +} AvbHashDescriptorFlags; + +/* A descriptor containing information about hash for an image. + * + * This descriptor is typically used for boot partitions to verify the + * entire kernel+initramfs image before executing it. + * + * Following this struct are |partition_name_len| bytes of the + * partition name (UTF-8 encoded), |salt_len| bytes of salt, and then + * |digest_len| bytes of the digest. + * + * The |reserved| field is for future expansion and must be set to NUL + * bytes. + * + * Changes in v1.1: + * - flags field is added which supports AVB_HASH_DESCRIPTOR_FLAGS_USE_AB + * - digest_len may be zero, which indicates the use of a persistent digest + */ +typedef struct AvbHashDescriptor { + AvbDescriptor parent_descriptor; + uint64_t image_size; + uint8_t hash_algorithm[32]; + uint32_t partition_name_len; + uint32_t salt_len; + uint32_t digest_len; + uint32_t flags; + uint8_t reserved[60]; +} AVB_ATTR_PACKED AvbHashDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_hash_descriptor_validate_and_byteswap(const AvbHashDescriptor* src, + AvbHashDescriptor* dest) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_HASH_DESCRIPTOR_H_ */ diff --git a/lib/libavb/avb_hashtree_descriptor.c b/lib/libavb/avb_hashtree_descriptor.c new file mode 100644 index 00000000000..2a61b35a8ff --- /dev/null +++ b/lib/libavb/avb_hashtree_descriptor.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_hashtree_descriptor.h" +#include "avb_util.h" + +bool avb_hashtree_descriptor_validate_and_byteswap( + const AvbHashtreeDescriptor* src, AvbHashtreeDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbHashtreeDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_HASHTREE) { + avb_error("Invalid tag for hashtree descriptor.\n"); + return false; + } + + dest->dm_verity_version = avb_be32toh(dest->dm_verity_version); + dest->image_size = avb_be64toh(dest->image_size); + dest->tree_offset = avb_be64toh(dest->tree_offset); + dest->tree_size = avb_be64toh(dest->tree_size); + dest->data_block_size = avb_be32toh(dest->data_block_size); + dest->hash_block_size = avb_be32toh(dest->hash_block_size); + dest->fec_num_roots = avb_be32toh(dest->fec_num_roots); + dest->fec_offset = avb_be64toh(dest->fec_offset); + dest->fec_size = avb_be64toh(dest->fec_size); + dest->partition_name_len = avb_be32toh(dest->partition_name_len); + dest->salt_len = avb_be32toh(dest->salt_len); + dest->root_digest_len = avb_be32toh(dest->root_digest_len); + dest->flags = avb_be32toh(dest->flags); + + /* Check that partition_name, salt, and root_digest are fully contained. */ + expected_size = sizeof(AvbHashtreeDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->partition_name_len) || + !avb_safe_add_to(&expected_size, dest->salt_len) || + !avb_safe_add_to(&expected_size, dest->root_digest_len)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + return true; +} diff --git a/lib/libavb/avb_hashtree_descriptor.h b/lib/libavb/avb_hashtree_descriptor.h new file mode 100644 index 00000000000..d7f3eb501a3 --- /dev/null +++ b/lib/libavb/avb_hashtree_descriptor.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_HASHTREE_DESCRIPTOR_H_ +#define AVB_HASHTREE_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flags for hashtree descriptors. + * + * AVB_HASHTREE_DESCRIPTOR_FLAGS_DO_NOT_USE_AB: Do not apply the default A/B + * partition logic to this partition. This is intentionally a negative boolean + * because A/B should be both the default and most used in practice. + */ +typedef enum { + AVB_HASHTREE_DESCRIPTOR_FLAGS_DO_NOT_USE_AB = (1 << 0), +} AvbHashtreeDescriptorFlags; + +/* A descriptor containing information about a dm-verity hashtree. + * + * Hash-trees are used to verify large partitions typically containing + * file systems. See + * https://gitlab.com/cryptsetup/cryptsetup/wikis/DMVerity for more + * information about dm-verity. + * + * Following this struct are |partition_name_len| bytes of the + * partition name (UTF-8 encoded), |salt_len| bytes of salt, and then + * |root_digest_len| bytes of the root digest. + * + * The |reserved| field is for future expansion and must be set to NUL + * bytes. + * + * Changes in v1.1: + * - flags field is added which supports AVB_HASHTREE_DESCRIPTOR_FLAGS_USE_AB + * - digest_len may be zero, which indicates the use of a persistent digest + */ +typedef struct AvbHashtreeDescriptor { + AvbDescriptor parent_descriptor; + uint32_t dm_verity_version; + uint64_t image_size; + uint64_t tree_offset; + uint64_t tree_size; + uint32_t data_block_size; + uint32_t hash_block_size; + uint32_t fec_num_roots; + uint64_t fec_offset; + uint64_t fec_size; + uint8_t hash_algorithm[32]; + uint32_t partition_name_len; + uint32_t salt_len; + uint32_t root_digest_len; + uint32_t flags; + uint8_t reserved[60]; +} AVB_ATTR_PACKED AvbHashtreeDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_hashtree_descriptor_validate_and_byteswap( + const AvbHashtreeDescriptor* src, + AvbHashtreeDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_HASHTREE_DESCRIPTOR_H_ */ diff --git a/lib/libavb/avb_kernel_cmdline_descriptor.c b/lib/libavb/avb_kernel_cmdline_descriptor.c new file mode 100644 index 00000000000..fa3fe4537b4 --- /dev/null +++ b/lib/libavb/avb_kernel_cmdline_descriptor.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_kernel_cmdline_descriptor.h" +#include "avb_util.h" + +bool avb_kernel_cmdline_descriptor_validate_and_byteswap( + const AvbKernelCmdlineDescriptor* src, AvbKernelCmdlineDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbKernelCmdlineDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE) { + avb_error("Invalid tag for kernel cmdline descriptor.\n"); + return false; + } + + dest->flags = avb_be32toh(dest->flags); + dest->kernel_cmdline_length = avb_be32toh(dest->kernel_cmdline_length); + + /* Check that kernel_cmdline is fully contained. */ + expected_size = sizeof(AvbKernelCmdlineDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->kernel_cmdline_length)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + + return true; +} diff --git a/lib/libavb/avb_kernel_cmdline_descriptor.h b/lib/libavb/avb_kernel_cmdline_descriptor.h new file mode 100644 index 00000000000..246fbdacf39 --- /dev/null +++ b/lib/libavb/avb_kernel_cmdline_descriptor.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_KERNEL_CMDLINE_DESCRIPTOR_H_ +#define AVB_KERNEL_CMDLINE_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flags for kernel command-line descriptors. + * + * AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_NOT_DISABLED: The + * cmdline will only be applied if hashtree verification is not + * disabled (cf. AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED). + * + * AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_DISABLED: The cmdline + * will only be applied if hashtree verification is disabled + * (cf. AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED). + */ +typedef enum { + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_NOT_DISABLED = (1 << 0), + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_DISABLED = (1 << 1) +} AvbKernelCmdlineFlags; + +/* A descriptor containing information to be appended to the kernel + * command-line. + * + * The |flags| field contains flags from the AvbKernelCmdlineFlags + * enumeration. + * + * Following this struct are |kernel_cmdline_len| bytes with the + * kernel command-line (UTF-8 encoded). + */ +typedef struct AvbKernelCmdlineDescriptor { + AvbDescriptor parent_descriptor; + uint32_t flags; + uint32_t kernel_cmdline_length; +} AVB_ATTR_PACKED AvbKernelCmdlineDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_kernel_cmdline_descriptor_validate_and_byteswap( + const AvbKernelCmdlineDescriptor* src, + AvbKernelCmdlineDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_KERNEL_CMDLINE_DESCRIPTOR_H_ */ diff --git a/lib/libavb/avb_ops.h b/lib/libavb/avb_ops.h new file mode 100644 index 00000000000..8bbdc7c31b9 --- /dev/null +++ b/lib/libavb/avb_ops.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_OPS_H_ +#define AVB_OPS_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Well-known names of named persistent values. */ +#define AVB_NPV_PERSISTENT_DIGEST_PREFIX "avb.persistent_digest." + +/* Return codes used for I/O operations. + * + * AVB_IO_RESULT_OK is returned if the requested operation was + * successful. + * + * AVB_IO_RESULT_ERROR_IO is returned if the underlying hardware (disk + * or other subsystem) encountered an I/O error. + * + * AVB_IO_RESULT_ERROR_OOM is returned if unable to allocate memory. + * + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION is returned if the requested + * partition does not exist. + * + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION is returned if the + * range of bytes requested to be read or written is outside the range + * of the partition. + * + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE is returned if a named persistent value + * does not exist. + * + * AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE is returned if a named persistent + * value size is not supported or does not match the expected size. + * + * AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE is returned if a buffer is too small + * for the requested operation. + */ +typedef enum { + AVB_IO_RESULT_OK, + AVB_IO_RESULT_ERROR_OOM, + AVB_IO_RESULT_ERROR_IO, + AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, + AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION, + AVB_IO_RESULT_ERROR_NO_SUCH_VALUE, + AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE, + AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE, +} AvbIOResult; + +struct AvbOps; +typedef struct AvbOps AvbOps; + +/* Forward-declaration of operations in libavb_ab. */ +struct AvbABOps; + +/* Forward-declaration of operations in libavb_atx. */ +struct AvbAtxOps; + +/* High-level operations/functions/methods that are platform + * dependent. + * + * Operations may be added in the future so when implementing it + * always make sure to zero out sizeof(AvbOps) bytes of the struct to + * ensure that unimplemented operations are set to NULL. + */ +struct AvbOps { + /* This pointer can be used by the application/bootloader using + * libavb and is typically used in each operation to get a pointer + * to platform-specific resources. It cannot be used by libraries. + */ + void* user_data; + + /* If libavb_ab is used, this should point to the + * AvbABOps. Otherwise it must be set to NULL. + */ + struct AvbABOps* ab_ops; + + /* If libavb_atx is used, this should point to the + * AvbAtxOps. Otherwise it must be set to NULL. + */ + struct AvbAtxOps* atx_ops; + + /* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if + * there was an I/O error from the underlying I/O subsystem. If the + * operation succeeds as requested AVB_IO_RESULT_OK is returned and + * the data is available in |buffer|. + * + * The only time partial I/O may occur is if reading beyond the end + * of the partition. In this case the value returned in + * |out_num_read| may be smaller than |num_bytes|. + */ + AvbIOResult (*read_from_partition)(AvbOps* ops, + const char* partition, + int64_t offset, + size_t num_bytes, + void* buffer, + size_t* out_num_read); + + /* Gets the starting pointer of a partition that is pre-loaded in memory, and + * save it to |out_pointer|. The preloaded partition is expected to be + * |num_bytes|, where the actual preloaded byte count is returned in + * |out_num_bytes_preloaded|. |out_num_bytes_preloaded| must be no larger than + * |num_bytes|. + * + * This provides an alternative way to access a partition that is preloaded + * into memory without a full memory copy. When this function pointer is not + * set (has value NULL), or when the |out_pointer| is set to NULL as a result, + * |read_from_partition| will be used as the fallback. This function is mainly + * used for accessing the entire partition content to calculate its hash. + * + * Preloaded partition data must outlive the lifespan of the + * |AvbSlotVerifyData| structure that |avb_slot_verify| outputs. + */ + AvbIOResult (*get_preloaded_partition)(AvbOps* ops, + const char* partition, + size_t num_bytes, + uint8_t** out_pointer, + size_t* out_num_bytes_preloaded); + + /* Writes |num_bytes| from |bffer| at offset |offset| to partition + * with name |partition| (NUL-terminated UTF-8 string). If |offset| + * is negative, its absolute value should be interpreted as the + * number of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO + * if there was an I/O error from the underlying I/O subsystem. If + * the operation succeeds as requested AVB_IO_RESULT_OK is + * returned. + * + * This function never does any partial I/O, it either transfers all + * of the requested bytes or returns an error. + */ + AvbIOResult (*write_to_partition)(AvbOps* ops, + const char* partition, + int64_t offset, + size_t num_bytes, + const void* buffer); + + /* Checks if the given public key used to sign the 'vbmeta' + * partition is trusted. Boot loaders typically compare this with + * embedded key material generated with 'avbtool + * extract_public_key'. + * + * The public key is in the array pointed to by |public_key_data| + * and is of |public_key_length| bytes. + * + * If there is no public key metadata (set with the avbtool option + * --public_key_metadata) then |public_key_metadata| will be set to + * NULL. Otherwise this field points to the data which is + * |public_key_metadata_length| bytes long. + * + * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set - + * true if trusted or false if untrusted. + */ + AvbIOResult (*validate_vbmeta_public_key)(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted); + + /* Gets the rollback index corresponding to the location given by + * |rollback_index_location|. The value is returned in + * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback + * index was retrieved, otherwise an error code. + * + * A device may have a limited amount of rollback index locations (say, + * one or four) so may error out if |rollback_index_location| exceeds + * this number. + */ + AvbIOResult (*read_rollback_index)(AvbOps* ops, + size_t rollback_index_location, + uint64_t* out_rollback_index); + + /* Sets the rollback index corresponding to the location given by + * |rollback_index_location| to |rollback_index|. Returns + * AVB_IO_RESULT_OK if the rollback index was set, otherwise an + * error code. + * + * A device may have a limited amount of rollback index locations (say, + * one or four) so may error out if |rollback_index_location| exceeds + * this number. + */ + AvbIOResult (*write_rollback_index)(AvbOps* ops, + size_t rollback_index_location, + uint64_t rollback_index); + + /* Gets whether the device is unlocked. The value is returned in + * |out_is_unlocked| (true if unlocked, false otherwise). Returns + * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error + * code. + */ + AvbIOResult (*read_is_device_unlocked)(AvbOps* ops, bool* out_is_unlocked); + + /* Gets the unique partition GUID for a partition with name in + * |partition| (NUL-terminated UTF-8 string). The GUID is copied as + * a string into |guid_buf| of size |guid_buf_size| and will be NUL + * terminated. The string must be lower-case and properly + * hyphenated. For example: + * + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ + AvbIOResult (*get_unique_guid_for_partition)(AvbOps* ops, + const char* partition, + char* guid_buf, + size_t guid_buf_size); + + /* Gets the size of a partition with the name in |partition| + * (NUL-terminated UTF-8 string). Returns the value in + * |out_size_num_bytes|. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ + AvbIOResult (*get_size_of_partition)(AvbOps* ops, + const char* partition, + uint64_t* out_size_num_bytes); + + /* Reads a persistent value corresponding to the given |name|. The value is + * returned in |out_buffer| which must point to |buffer_size| bytes. On + * success |out_num_bytes_read| contains the number of bytes read into + * |out_buffer|. If AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE is returned, + * |out_num_bytes_read| contains the number of bytes that would have been read + * which can be used to allocate a buffer. + * + * The |buffer_size| may be zero and the |out_buffer| may be NULL, but if + * |out_buffer| is NULL then |buffer_size| *must* be zero. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + * + * If the value does not exist, is not supported, or is not populated, returns + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If |buffer_size| is smaller than the + * size of the stored value, returns AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE. + * + * This operation is currently only used to support persistent digests. If a + * device does not use persistent digests this function pointer can be set to + * NULL. + */ + AvbIOResult (*read_persistent_value)(AvbOps* ops, + const char* name, + size_t buffer_size, + uint8_t* out_buffer, + size_t* out_num_bytes_read); + + /* Writes a persistent value corresponding to the given |name|. The value is + * supplied in |value| which must point to |value_size| bytes. Any existing + * value with the same name is overwritten. If |value_size| is zero, future + * calls to |read_persistent_value| will return + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + * + * If the value |name| is not supported, returns + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If the |value_size| is not supported, + * returns AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE. + * + * This operation is currently only used to support persistent digests. If a + * device does not use persistent digests this function pointer can be set to + * NULL. + */ + AvbIOResult (*write_persistent_value)(AvbOps* ops, + const char* name, + size_t value_size, + const uint8_t* value); +}; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_OPS_H_ */ diff --git a/lib/libavb/avb_property_descriptor.c b/lib/libavb/avb_property_descriptor.c new file mode 100644 index 00000000000..589c96310ab --- /dev/null +++ b/lib/libavb/avb_property_descriptor.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_property_descriptor.h" +#include "avb_util.h" + +bool avb_property_descriptor_validate_and_byteswap( + const AvbPropertyDescriptor* src, AvbPropertyDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbPropertyDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_PROPERTY) { + avb_error("Invalid tag for property descriptor.\n"); + return false; + } + + dest->key_num_bytes = avb_be64toh(dest->key_num_bytes); + dest->value_num_bytes = avb_be64toh(dest->value_num_bytes); + + /* Check that key and value are fully contained. */ + expected_size = sizeof(AvbPropertyDescriptor) - sizeof(AvbDescriptor) + 2; + if (!avb_safe_add_to(&expected_size, dest->key_num_bytes) || + !avb_safe_add_to(&expected_size, dest->value_num_bytes)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + + return true; +} + +typedef struct { + const char* key; + size_t key_size; + const char* ret_value; + size_t ret_value_size; +} PropertyIteratorData; + +static bool property_lookup_desc_foreach(const AvbDescriptor* header, + void* user_data) { + PropertyIteratorData* data = (PropertyIteratorData*)user_data; + AvbPropertyDescriptor prop_desc; + const uint8_t* p; + bool ret = true; + + if (header->tag != AVB_DESCRIPTOR_TAG_PROPERTY) { + goto out; + } + + if (!avb_property_descriptor_validate_and_byteswap( + (const AvbPropertyDescriptor*)header, &prop_desc)) { + goto out; + } + + p = (const uint8_t*)header; + if (p[sizeof(AvbPropertyDescriptor) + prop_desc.key_num_bytes] != 0) { + avb_error("No terminating NUL byte in key.\n"); + goto out; + } + + if (data->key_size == prop_desc.key_num_bytes) { + if (avb_memcmp(p + sizeof(AvbPropertyDescriptor), + data->key, + data->key_size) == 0) { + data->ret_value = (const char*)(p + sizeof(AvbPropertyDescriptor) + + prop_desc.key_num_bytes + 1); + data->ret_value_size = prop_desc.value_num_bytes; + /* Stop iterating. */ + ret = false; + goto out; + } + } + +out: + return ret; +} + +const char* avb_property_lookup(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + size_t* out_value_size) { + PropertyIteratorData data; + + if (key_size == 0) { + key_size = avb_strlen(key); + } + + data.key = key; + data.key_size = key_size; + + if (avb_descriptor_foreach( + image_data, image_size, property_lookup_desc_foreach, &data) == 0) { + if (out_value_size != NULL) { + *out_value_size = data.ret_value_size; + } + return data.ret_value; + } + + if (out_value_size != NULL) { + *out_value_size = 0; + } + return NULL; +} + +bool avb_property_lookup_uint64(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + uint64_t* out_value) { + const char* value; + bool ret = false; + uint64_t parsed_val; + int base; + int n; + + value = avb_property_lookup(image_data, image_size, key, key_size, NULL); + if (value == NULL) { + goto out; + } + + base = 10; + if (avb_memcmp(value, "0x", 2) == 0) { + base = 16; + value += 2; + } + + parsed_val = 0; + for (n = 0; value[n] != '\0'; n++) { + int c = value[n]; + int digit; + + parsed_val *= base; + + if (c >= '0' && c <= '9') { + digit = c - '0'; + } else if (base == 16 && c >= 'a' && c <= 'f') { + digit = c - 'a' + 10; + } else if (base == 16 && c >= 'A' && c <= 'F') { + digit = c - 'A' + 10; + } else { + avb_error("Invalid digit.\n"); + goto out; + } + + parsed_val += digit; + } + + ret = true; + if (out_value != NULL) { + *out_value = parsed_val; + } + +out: + return ret; +} diff --git a/lib/libavb/avb_property_descriptor.h b/lib/libavb/avb_property_descriptor.h new file mode 100644 index 00000000000..917c58f9fea --- /dev/null +++ b/lib/libavb/avb_property_descriptor.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_PROPERTY_DESCRIPTOR_H_ +#define AVB_PROPERTY_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* A descriptor for properties (free-form key/value pairs). + * + * Following this struct are |key_num_bytes| bytes of key data, + * followed by a NUL byte, then |value_num_bytes| bytes of value data, + * followed by a NUL byte and then enough padding to make the combined + * size a multiple of 8. + */ +typedef struct AvbPropertyDescriptor { + AvbDescriptor parent_descriptor; + uint64_t key_num_bytes; + uint64_t value_num_bytes; +} AVB_ATTR_PACKED AvbPropertyDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_property_descriptor_validate_and_byteswap( + const AvbPropertyDescriptor* src, + AvbPropertyDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Convenience function for looking up the value for a property with + * name |key| in a vbmeta image. If |key_size| is 0, |key| must be + * NUL-terminated. + * + * The |image_data| parameter must be a pointer to a vbmeta image of + * size |image_size|. + * + * This function returns a pointer to the value inside the passed-in + * image or NULL if not found. Note that the value is always + * guaranteed to be followed by a NUL byte. + * + * If the value was found and |out_value_size| is not NULL, the size + * of the value is returned there. + * + * This function is O(n) in number of descriptors so if you need to + * look up a lot of values, you may want to build a more efficient + * lookup-table by manually walking all descriptors using + * avb_descriptor_foreach(). + * + * Before using this function, you MUST verify |image_data| with + * avb_vbmeta_image_verify() and reject it unless it's signed by a + * known good public key. + */ +const char* avb_property_lookup(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + size_t* out_value_size) + AVB_ATTR_WARN_UNUSED_RESULT; + +/* Like avb_property_lookup() but parses the intial portions of the + * value as an unsigned 64-bit integer. Both decimal and hexadecimal + * representations (e.g. "0x2a") are supported. Returns false on + * failure and true on success. On success, the parsed value is + * returned in |out_value|. + */ +bool avb_property_lookup_uint64(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + uint64_t* out_value) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_PROPERTY_DESCRIPTOR_H_ */ diff --git a/lib/libavb/avb_rsa.c b/lib/libavb/avb_rsa.c new file mode 100644 index 00000000000..bbf15626b85 --- /dev/null +++ b/lib/libavb/avb_rsa.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: MIT OR BSD-3-Clause +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +/* Implementation of RSA signature verification which uses a pre-processed + * key for computation. The code extends libmincrypt RSA verification code to + * support multiple RSA key lengths and hash digest algorithms. + */ + +#include "avb_rsa.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" + +typedef struct IAvbKey { + unsigned int len; /* Length of n[] in number of uint32_t */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + uint32_t* n; /* modulus as array (host-byte order) */ + uint32_t* rr; /* R^2 as array (host-byte order) */ +} IAvbKey; + +static IAvbKey* iavb_parse_key_data(const uint8_t* data, size_t length) { + AvbRSAPublicKeyHeader h; + IAvbKey* key = NULL; + size_t expected_length; + unsigned int i; + const uint8_t* n; + const uint8_t* rr; + + if (!avb_rsa_public_key_header_validate_and_byteswap( + (const AvbRSAPublicKeyHeader*)data, &h)) { + avb_error("Invalid key.\n"); + goto fail; + } + + if (!(h.key_num_bits == 2048 || h.key_num_bits == 4096 || + h.key_num_bits == 8192)) { + avb_error("Unexpected key length.\n"); + goto fail; + } + + expected_length = sizeof(AvbRSAPublicKeyHeader) + 2 * h.key_num_bits / 8; + if (length != expected_length) { + avb_error("Key does not match expected length.\n"); + goto fail; + } + + n = data + sizeof(AvbRSAPublicKeyHeader); + rr = data + sizeof(AvbRSAPublicKeyHeader) + h.key_num_bits / 8; + + /* Store n and rr following the key header so we only have to do one + * allocation. + */ + key = (IAvbKey*)(avb_malloc(sizeof(IAvbKey) + 2 * h.key_num_bits / 8)); + if (key == NULL) { + goto fail; + } + + key->len = h.key_num_bits / 32; + key->n0inv = h.n0inv; + key->n = (uint32_t*)(key + 1); /* Skip ahead sizeof(IAvbKey) bytes. */ + key->rr = key->n + key->len; + + /* Crypto-code below (modpowF4() and friends) expects the key in + * little-endian format (rather than the format we're storing the + * key in), so convert it. + */ + for (i = 0; i < key->len; i++) { + key->n[i] = avb_be32toh(((uint32_t*)n)[key->len - i - 1]); + key->rr[i] = avb_be32toh(((uint32_t*)rr)[key->len - i - 1]); + } + return key; + +fail: + if (key != NULL) { + avb_free(key); + } + return NULL; +} + +static void iavb_free_parsed_key(IAvbKey* key) { + avb_free(key); +} + +/* a[] -= mod */ +static void subM(const IAvbKey* key, uint32_t* a) { + int64_t A = 0; + uint32_t i; + for (i = 0; i < key->len; ++i) { + A += (uint64_t)a[i] - key->n[i]; + a[i] = (uint32_t)A; + A >>= 32; + } +} + +/* return a[] >= mod */ +static int geM(const IAvbKey* key, uint32_t* a) { + uint32_t i; + for (i = key->len; i;) { + --i; + if (a[i] < key->n[i]) { + return 0; + } + if (a[i] > key->n[i]) { + return 1; + } + } + return 1; /* equal */ +} + +/* montgomery c[] += a * b[] / R % mod */ +static void montMulAdd(const IAvbKey* key, + uint32_t* c, + const uint32_t a, + const uint32_t* b) { + uint64_t A = (uint64_t)a * b[0] + c[0]; + uint32_t d0 = (uint32_t)A * key->n0inv; + uint64_t B = (uint64_t)d0 * key->n[0] + (uint32_t)A; + uint32_t i; + + for (i = 1; i < key->len; ++i) { + A = (A >> 32) + (uint64_t)a * b[i] + c[i]; + B = (B >> 32) + (uint64_t)d0 * key->n[i] + (uint32_t)A; + c[i - 1] = (uint32_t)B; + } + + A = (A >> 32) + (B >> 32); + + c[i - 1] = (uint32_t)A; + + if (A >> 32) { + subM(key, c); + } +} + +/* montgomery c[] = a[] * b[] / R % mod */ +static void montMul(const IAvbKey* key, uint32_t* c, uint32_t* a, uint32_t* b) { + uint32_t i; + for (i = 0; i < key->len; ++i) { + c[i] = 0; + } + for (i = 0; i < key->len; ++i) { + montMulAdd(key, c, a[i], b); + } +} + +/* In-place public exponentiation. (65537} + * Input and output big-endian byte array in inout. + */ +static void modpowF4(const IAvbKey* key, uint8_t* inout) { + uint32_t* a = (uint32_t*)avb_malloc(key->len * sizeof(uint32_t)); + uint32_t* aR = (uint32_t*)avb_malloc(key->len * sizeof(uint32_t)); + uint32_t* aaR = (uint32_t*)avb_malloc(key->len * sizeof(uint32_t)); + if (a == NULL || aR == NULL || aaR == NULL) { + goto out; + } + + uint32_t* aaa = aaR; /* Re-use location. */ + int i; + + /* Convert from big endian byte array to little endian word array. */ + for (i = 0; i < (int)key->len; ++i) { + uint32_t tmp = (inout[((key->len - 1 - i) * 4) + 0] << 24) | + (inout[((key->len - 1 - i) * 4) + 1] << 16) | + (inout[((key->len - 1 - i) * 4) + 2] << 8) | + (inout[((key->len - 1 - i) * 4) + 3] << 0); + a[i] = tmp; + } + + montMul(key, aR, a, key->rr); /* aR = a * RR / R mod M */ + for (i = 0; i < 16; i += 2) { + montMul(key, aaR, aR, aR); /* aaR = aR * aR / R mod M */ + montMul(key, aR, aaR, aaR); /* aR = aaR * aaR / R mod M */ + } + montMul(key, aaa, aR, a); /* aaa = aR * a / R mod M */ + + /* Make sure aaa < mod; aaa is at most 1x mod too large. */ + if (geM(key, aaa)) { + subM(key, aaa); + } + + /* Convert to bigendian byte array */ + for (i = (int)key->len - 1; i >= 0; --i) { + uint32_t tmp = aaa[i]; + *inout++ = (uint8_t)(tmp >> 24); + *inout++ = (uint8_t)(tmp >> 16); + *inout++ = (uint8_t)(tmp >> 8); + *inout++ = (uint8_t)(tmp >> 0); + } + +out: + if (a != NULL) { + avb_free(a); + } + if (aR != NULL) { + avb_free(aR); + } + if (aaR != NULL) { + avb_free(aaR); + } +} + +/* Verify a RSA PKCS1.5 signature against an expected hash. + * Returns false on failure, true on success. + */ +bool avb_rsa_verify(const uint8_t* key, + size_t key_num_bytes, + const uint8_t* sig, + size_t sig_num_bytes, + const uint8_t* hash, + size_t hash_num_bytes, + const uint8_t* padding, + size_t padding_num_bytes) { + uint8_t* buf = NULL; + IAvbKey* parsed_key = NULL; + bool success = false; + + if (key == NULL || sig == NULL || hash == NULL || padding == NULL) { + avb_error("Invalid input.\n"); + goto out; + } + + parsed_key = iavb_parse_key_data(key, key_num_bytes); + if (parsed_key == NULL) { + avb_error("Error parsing key.\n"); + goto out; + } + + if (sig_num_bytes != (parsed_key->len * sizeof(uint32_t))) { + avb_error("Signature length does not match key length.\n"); + goto out; + } + + if (padding_num_bytes != sig_num_bytes - hash_num_bytes) { + avb_error("Padding length does not match hash and signature lengths.\n"); + goto out; + } + + buf = (uint8_t*)avb_malloc(sig_num_bytes); + if (buf == NULL) { + avb_error("Error allocating memory.\n"); + goto out; + } + avb_memcpy(buf, sig, sig_num_bytes); + + modpowF4(parsed_key, buf); + + /* Check padding bytes. + * + * Even though there are probably no timing issues here, we use + * avb_safe_memcmp() just to be on the safe side. + */ + if (avb_safe_memcmp(buf, padding, padding_num_bytes)) { + avb_error("Padding check failed.\n"); + goto out; + } + + /* Check hash. */ + if (avb_safe_memcmp(buf + padding_num_bytes, hash, hash_num_bytes)) { + avb_error("Hash check failed.\n"); + goto out; + } + + success = true; + +out: + if (parsed_key != NULL) { + iavb_free_parsed_key(parsed_key); + } + if (buf != NULL) { + avb_free(buf); + } + return success; +} diff --git a/lib/libavb/avb_rsa.h b/lib/libavb/avb_rsa.h new file mode 100644 index 00000000000..8741790e094 --- /dev/null +++ b/lib/libavb/avb_rsa.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: MIT OR BSD-3-Clause */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifdef AVB_INSIDE_LIBAVB_H +#error "You can't include avb_rsa.h in the public header libavb.h." +#endif + +#ifndef AVB_COMPILATION +#error "Never include this file, it may only be used from internal avb code." +#endif + +#ifndef AVB_RSA_H_ +#define AVB_RSA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "avb_crypto.h" +#include "avb_sysdeps.h" + +/* Using the key given by |key|, verify a RSA signature |sig| of + * length |sig_num_bytes| against an expected |hash| of length + * |hash_num_bytes|. The padding to expect must be passed in using + * |padding| of length |padding_num_bytes|. + * + * The data in |key| must match the format defined in + * |AvbRSAPublicKeyHeader|, including the two large numbers + * following. The |key_num_bytes| must be the size of the entire + * serialized key. + * + * Returns false if verification fails, true otherwise. + */ +bool avb_rsa_verify(const uint8_t* key, + size_t key_num_bytes, + const uint8_t* sig, + size_t sig_num_bytes, + const uint8_t* hash, + size_t hash_num_bytes, + const uint8_t* padding, + size_t padding_num_bytes) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_RSA_H_ */ diff --git a/lib/libavb/avb_sha.h b/lib/libavb/avb_sha.h new file mode 100644 index 00000000000..365aaadc2f7 --- /dev/null +++ b/lib/libavb/avb_sha.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#ifdef AVB_INSIDE_LIBAVB_H +#error "You can't include avb_sha.h in the public header libavb.h." +#endif + +#ifndef AVB_COMPILATION +#error "Never include this file, it may only be used from internal avb code." +#endif + +#ifndef AVB_SHA_H_ +#define AVB_SHA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "avb_crypto.h" +#include "avb_sysdeps.h" + +/* Block size in bytes of a SHA-256 digest. */ +#define AVB_SHA256_BLOCK_SIZE 64 + + +/* Block size in bytes of a SHA-512 digest. */ +#define AVB_SHA512_BLOCK_SIZE 128 + +/* Data structure used for SHA-256. */ +typedef struct { + uint32_t h[8]; + uint32_t tot_len; + uint32_t len; + uint8_t block[2 * AVB_SHA256_BLOCK_SIZE]; + uint8_t buf[AVB_SHA256_DIGEST_SIZE]; /* Used for storing the final digest. */ +} AvbSHA256Ctx; + +/* Data structure used for SHA-512. */ +typedef struct { + uint64_t h[8]; + uint32_t tot_len; + uint32_t len; + uint8_t block[2 * AVB_SHA512_BLOCK_SIZE]; + uint8_t buf[AVB_SHA512_DIGEST_SIZE]; /* Used for storing the final digest. */ +} AvbSHA512Ctx; + +/* Initializes the SHA-256 context. */ +void avb_sha256_init(AvbSHA256Ctx* ctx); + +/* Updates the SHA-256 context with |len| bytes from |data|. */ +void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, uint32_t len); + +/* Returns the SHA-256 digest. */ +uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Initializes the SHA-512 context. */ +void avb_sha512_init(AvbSHA512Ctx* ctx); + +/* Updates the SHA-512 context with |len| bytes from |data|. */ +void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, uint32_t len); + +/* Returns the SHA-512 digest. */ +uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_SHA_H_ */ diff --git a/lib/libavb/avb_sha256.c b/lib/libavb/avb_sha256.c new file mode 100644 index 00000000000..d24c7015f67 --- /dev/null +++ b/lib/libavb/avb_sha256.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2005, 2007 Olivier Gay <olivier.gay@a3.epfl.ch> + * All rights reserved. + * + * FIPS 180-2 SHA-224/256/384/512 implementation + * Last update: 02/02/2007 + * Issue date: 04/30/2005 + */ + +#include "avb_sha.h" + +#define SHFR(x, n) (x >> n) +#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n))) +#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) +#define CH(x, y, z) ((x & y) ^ (~x & z)) +#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +#define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) +#define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) +#define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3)) +#define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10)) + +#define UNPACK32(x, str) \ + { \ + *((str) + 3) = (uint8_t)((x)); \ + *((str) + 2) = (uint8_t)((x) >> 8); \ + *((str) + 1) = (uint8_t)((x) >> 16); \ + *((str) + 0) = (uint8_t)((x) >> 24); \ + } + +#define PACK32(str, x) \ + { \ + *(x) = ((uint32_t) * ((str) + 3)) | ((uint32_t) * ((str) + 2) << 8) | \ + ((uint32_t) * ((str) + 1) << 16) | \ + ((uint32_t) * ((str) + 0) << 24); \ + } + +/* Macros used for loops unrolling */ + +#define SHA256_SCR(i) \ + { w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + w[i - 16]; } + +#define SHA256_EXP(a, b, c, d, e, f, g, h, j) \ + { \ + t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + sha256_k[j] + \ + w[j]; \ + t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \ + wv[d] += t1; \ + wv[h] = t1 + t2; \ + } + +static const uint32_t sha256_h0[8] = {0x6a09e667, + 0xbb67ae85, + 0x3c6ef372, + 0xa54ff53a, + 0x510e527f, + 0x9b05688c, + 0x1f83d9ab, + 0x5be0cd19}; + +static const uint32_t sha256_k[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, + 0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786, + 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, + 0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b, + 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, + 0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2}; + +/* SHA-256 implementation */ +void avb_sha256_init(AvbSHA256Ctx* ctx) { +#ifndef UNROLL_LOOPS + int i; + for (i = 0; i < 8; i++) { + ctx->h[i] = sha256_h0[i]; + } +#else + ctx->h[0] = sha256_h0[0]; + ctx->h[1] = sha256_h0[1]; + ctx->h[2] = sha256_h0[2]; + ctx->h[3] = sha256_h0[3]; + ctx->h[4] = sha256_h0[4]; + ctx->h[5] = sha256_h0[5]; + ctx->h[6] = sha256_h0[6]; + ctx->h[7] = sha256_h0[7]; +#endif /* !UNROLL_LOOPS */ + + ctx->len = 0; + ctx->tot_len = 0; +} + +static void SHA256_transform(AvbSHA256Ctx* ctx, + const uint8_t* message, + unsigned int block_nb) { + uint32_t w[64]; + uint32_t wv[8]; + uint32_t t1, t2; + const unsigned char* sub_block; + int i; + +#ifndef UNROLL_LOOPS + int j; +#endif + + for (i = 0; i < (int)block_nb; i++) { + sub_block = message + (i << 6); + +#ifndef UNROLL_LOOPS + for (j = 0; j < 16; j++) { + PACK32(&sub_block[j << 2], &w[j]); + } + + for (j = 16; j < 64; j++) { + SHA256_SCR(j); + } + + for (j = 0; j < 8; j++) { + wv[j] = ctx->h[j]; + } + + for (j = 0; j < 64; j++) { + t1 = wv[7] + SHA256_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha256_k[j] + + w[j]; + t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); + wv[7] = wv[6]; + wv[6] = wv[5]; + wv[5] = wv[4]; + wv[4] = wv[3] + t1; + wv[3] = wv[2]; + wv[2] = wv[1]; + wv[1] = wv[0]; + wv[0] = t1 + t2; + } + + for (j = 0; j < 8; j++) { + ctx->h[j] += wv[j]; + } +#else + PACK32(&sub_block[0], &w[0]); + PACK32(&sub_block[4], &w[1]); + PACK32(&sub_block[8], &w[2]); + PACK32(&sub_block[12], &w[3]); + PACK32(&sub_block[16], &w[4]); + PACK32(&sub_block[20], &w[5]); + PACK32(&sub_block[24], &w[6]); + PACK32(&sub_block[28], &w[7]); + PACK32(&sub_block[32], &w[8]); + PACK32(&sub_block[36], &w[9]); + PACK32(&sub_block[40], &w[10]); + PACK32(&sub_block[44], &w[11]); + PACK32(&sub_block[48], &w[12]); + PACK32(&sub_block[52], &w[13]); + PACK32(&sub_block[56], &w[14]); + PACK32(&sub_block[60], &w[15]); + + SHA256_SCR(16); + SHA256_SCR(17); + SHA256_SCR(18); + SHA256_SCR(19); + SHA256_SCR(20); + SHA256_SCR(21); + SHA256_SCR(22); + SHA256_SCR(23); + SHA256_SCR(24); + SHA256_SCR(25); + SHA256_SCR(26); + SHA256_SCR(27); + SHA256_SCR(28); + SHA256_SCR(29); + SHA256_SCR(30); + SHA256_SCR(31); + SHA256_SCR(32); + SHA256_SCR(33); + SHA256_SCR(34); + SHA256_SCR(35); + SHA256_SCR(36); + SHA256_SCR(37); + SHA256_SCR(38); + SHA256_SCR(39); + SHA256_SCR(40); + SHA256_SCR(41); + SHA256_SCR(42); + SHA256_SCR(43); + SHA256_SCR(44); + SHA256_SCR(45); + SHA256_SCR(46); + SHA256_SCR(47); + SHA256_SCR(48); + SHA256_SCR(49); + SHA256_SCR(50); + SHA256_SCR(51); + SHA256_SCR(52); + SHA256_SCR(53); + SHA256_SCR(54); + SHA256_SCR(55); + SHA256_SCR(56); + SHA256_SCR(57); + SHA256_SCR(58); + SHA256_SCR(59); + SHA256_SCR(60); + SHA256_SCR(61); + SHA256_SCR(62); + SHA256_SCR(63); + + wv[0] = ctx->h[0]; + wv[1] = ctx->h[1]; + wv[2] = ctx->h[2]; + wv[3] = ctx->h[3]; + wv[4] = ctx->h[4]; + wv[5] = ctx->h[5]; + wv[6] = ctx->h[6]; + wv[7] = ctx->h[7]; + + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 0); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 1); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 2); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 3); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 4); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 5); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 6); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 7); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 8); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 9); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 10); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 11); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 12); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 13); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 14); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 15); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 16); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 17); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 18); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 19); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 20); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 21); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 22); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 23); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 24); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 25); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 26); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 27); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 28); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 29); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 30); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 31); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 32); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 33); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 34); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 35); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 36); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 37); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 38); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 39); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 40); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 41); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 42); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 43); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 44); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 45); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 46); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 47); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 48); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 49); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 50); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 51); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 52); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 53); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 54); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 55); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 56); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 57); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 58); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 59); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 60); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 61); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 62); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 63); + + ctx->h[0] += wv[0]; + ctx->h[1] += wv[1]; + ctx->h[2] += wv[2]; + ctx->h[3] += wv[3]; + ctx->h[4] += wv[4]; + ctx->h[5] += wv[5]; + ctx->h[6] += wv[6]; + ctx->h[7] += wv[7]; +#endif /* !UNROLL_LOOPS */ + } +} + +void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, uint32_t len) { + unsigned int block_nb; + unsigned int new_len, rem_len, tmp_len; + const uint8_t* shifted_data; + + tmp_len = AVB_SHA256_BLOCK_SIZE - ctx->len; + rem_len = len < tmp_len ? len : tmp_len; + + avb_memcpy(&ctx->block[ctx->len], data, rem_len); + + if (ctx->len + len < AVB_SHA256_BLOCK_SIZE) { + ctx->len += len; + return; + } + + new_len = len - rem_len; + block_nb = new_len / AVB_SHA256_BLOCK_SIZE; + + shifted_data = data + rem_len; + + SHA256_transform(ctx, ctx->block, 1); + SHA256_transform(ctx, shifted_data, block_nb); + + rem_len = new_len % AVB_SHA256_BLOCK_SIZE; + + avb_memcpy(ctx->block, &shifted_data[block_nb << 6], rem_len); + + ctx->len = rem_len; + ctx->tot_len += (block_nb + 1) << 6; +} + +uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) { + unsigned int block_nb; + unsigned int pm_len; + unsigned int len_b; +#ifndef UNROLL_LOOPS + int i; +#endif + + block_nb = + (1 + ((AVB_SHA256_BLOCK_SIZE - 9) < (ctx->len % AVB_SHA256_BLOCK_SIZE))); + + len_b = (ctx->tot_len + ctx->len) << 3; + pm_len = block_nb << 6; + + avb_memset(ctx->block + ctx->len, 0, pm_len - ctx->len); + ctx->block[ctx->len] = 0x80; + UNPACK32(len_b, ctx->block + pm_len - 4); + + SHA256_transform(ctx, ctx->block, block_nb); + +#ifndef UNROLL_LOOPS + for (i = 0; i < 8; i++) { + UNPACK32(ctx->h[i], &ctx->buf[i << 2]); + } +#else + UNPACK32(ctx->h[0], &ctx->buf[0]); + UNPACK32(ctx->h[1], &ctx->buf[4]); + UNPACK32(ctx->h[2], &ctx->buf[8]); + UNPACK32(ctx->h[3], &ctx->buf[12]); + UNPACK32(ctx->h[4], &ctx->buf[16]); + UNPACK32(ctx->h[5], &ctx->buf[20]); + UNPACK32(ctx->h[6], &ctx->buf[24]); + UNPACK32(ctx->h[7], &ctx->buf[28]); +#endif /* !UNROLL_LOOPS */ + + return ctx->buf; +} diff --git a/lib/libavb/avb_sha512.c b/lib/libavb/avb_sha512.c new file mode 100644 index 00000000000..a5e7297aa70 --- /dev/null +++ b/lib/libavb/avb_sha512.c @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2005, 2007 Olivier Gay <olivier.gay@a3.epfl.ch> + * All rights reserved. + * + * FIPS 180-2 SHA-224/256/384/512 implementation + * Last update: 02/02/2007 + * Issue date: 04/30/2005 + */ + +#include "avb_sha.h" + +#define SHFR(x, n) (x >> n) +#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n))) +#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) +#define CH(x, y, z) ((x & y) ^ (~x & z)) +#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +#define SHA512_F1(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) +#define SHA512_F2(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41)) +#define SHA512_F3(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHFR(x, 7)) +#define SHA512_F4(x) (ROTR(x, 19) ^ ROTR(x, 61) ^ SHFR(x, 6)) + +#define UNPACK32(x, str) \ + { \ + *((str) + 3) = (uint8_t)((x)); \ + *((str) + 2) = (uint8_t)((x) >> 8); \ + *((str) + 1) = (uint8_t)((x) >> 16); \ + *((str) + 0) = (uint8_t)((x) >> 24); \ + } + +#define UNPACK64(x, str) \ + { \ + *((str) + 7) = (uint8_t)x; \ + *((str) + 6) = (uint8_t)((uint64_t)x >> 8); \ + *((str) + 5) = (uint8_t)((uint64_t)x >> 16); \ + *((str) + 4) = (uint8_t)((uint64_t)x >> 24); \ + *((str) + 3) = (uint8_t)((uint64_t)x >> 32); \ + *((str) + 2) = (uint8_t)((uint64_t)x >> 40); \ + *((str) + 1) = (uint8_t)((uint64_t)x >> 48); \ + *((str) + 0) = (uint8_t)((uint64_t)x >> 56); \ + } + +#define PACK64(str, x) \ + { \ + *(x) = \ + ((uint64_t) * ((str) + 7)) | ((uint64_t) * ((str) + 6) << 8) | \ + ((uint64_t) * ((str) + 5) << 16) | ((uint64_t) * ((str) + 4) << 24) | \ + ((uint64_t) * ((str) + 3) << 32) | ((uint64_t) * ((str) + 2) << 40) | \ + ((uint64_t) * ((str) + 1) << 48) | ((uint64_t) * ((str) + 0) << 56); \ + } + +/* Macros used for loops unrolling */ + +#define SHA512_SCR(i) \ + { w[i] = SHA512_F4(w[i - 2]) + w[i - 7] + SHA512_F3(w[i - 15]) + w[i - 16]; } + +#define SHA512_EXP(a, b, c, d, e, f, g, h, j) \ + { \ + t1 = wv[h] + SHA512_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + sha512_k[j] + \ + w[j]; \ + t2 = SHA512_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \ + wv[d] += t1; \ + wv[h] = t1 + t2; \ + } + +static const uint64_t sha512_h0[8] = {0x6a09e667f3bcc908ULL, + 0xbb67ae8584caa73bULL, + 0x3c6ef372fe94f82bULL, + 0xa54ff53a5f1d36f1ULL, + 0x510e527fade682d1ULL, + 0x9b05688c2b3e6c1fULL, + 0x1f83d9abfb41bd6bULL, + 0x5be0cd19137e2179ULL}; + +static const uint64_t sha512_k[80] = { + 0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, 0xb5c0fbcfec4d3b2fULL, + 0xe9b5dba58189dbbcULL, 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL, + 0x923f82a4af194f9bULL, 0xab1c5ed5da6d8118ULL, 0xd807aa98a3030242ULL, + 0x12835b0145706fbeULL, 0x243185be4ee4b28cULL, 0x550c7dc3d5ffb4e2ULL, + 0x72be5d74f27b896fULL, 0x80deb1fe3b1696b1ULL, 0x9bdc06a725c71235ULL, + 0xc19bf174cf692694ULL, 0xe49b69c19ef14ad2ULL, 0xefbe4786384f25e3ULL, + 0x0fc19dc68b8cd5b5ULL, 0x240ca1cc77ac9c65ULL, 0x2de92c6f592b0275ULL, + 0x4a7484aa6ea6e483ULL, 0x5cb0a9dcbd41fbd4ULL, 0x76f988da831153b5ULL, + 0x983e5152ee66dfabULL, 0xa831c66d2db43210ULL, 0xb00327c898fb213fULL, + 0xbf597fc7beef0ee4ULL, 0xc6e00bf33da88fc2ULL, 0xd5a79147930aa725ULL, + 0x06ca6351e003826fULL, 0x142929670a0e6e70ULL, 0x27b70a8546d22ffcULL, + 0x2e1b21385c26c926ULL, 0x4d2c6dfc5ac42aedULL, 0x53380d139d95b3dfULL, + 0x650a73548baf63deULL, 0x766a0abb3c77b2a8ULL, 0x81c2c92e47edaee6ULL, + 0x92722c851482353bULL, 0xa2bfe8a14cf10364ULL, 0xa81a664bbc423001ULL, + 0xc24b8b70d0f89791ULL, 0xc76c51a30654be30ULL, 0xd192e819d6ef5218ULL, + 0xd69906245565a910ULL, 0xf40e35855771202aULL, 0x106aa07032bbd1b8ULL, + 0x19a4c116b8d2d0c8ULL, 0x1e376c085141ab53ULL, 0x2748774cdf8eeb99ULL, + 0x34b0bcb5e19b48a8ULL, 0x391c0cb3c5c95a63ULL, 0x4ed8aa4ae3418acbULL, + 0x5b9cca4f7763e373ULL, 0x682e6ff3d6b2b8a3ULL, 0x748f82ee5defb2fcULL, + 0x78a5636f43172f60ULL, 0x84c87814a1f0ab72ULL, 0x8cc702081a6439ecULL, + 0x90befffa23631e28ULL, 0xa4506cebde82bde9ULL, 0xbef9a3f7b2c67915ULL, + 0xc67178f2e372532bULL, 0xca273eceea26619cULL, 0xd186b8c721c0c207ULL, + 0xeada7dd6cde0eb1eULL, 0xf57d4f7fee6ed178ULL, 0x06f067aa72176fbaULL, + 0x0a637dc5a2c898a6ULL, 0x113f9804bef90daeULL, 0x1b710b35131c471bULL, + 0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL, + 0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL, + 0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL}; + +/* SHA-512 implementation */ + +void avb_sha512_init(AvbSHA512Ctx* ctx) { +#ifdef UNROLL_LOOPS_SHA512 + ctx->h[0] = sha512_h0[0]; + ctx->h[1] = sha512_h0[1]; + ctx->h[2] = sha512_h0[2]; + ctx->h[3] = sha512_h0[3]; + ctx->h[4] = sha512_h0[4]; + ctx->h[5] = sha512_h0[5]; + ctx->h[6] = sha512_h0[6]; + ctx->h[7] = sha512_h0[7]; +#else + int i; + + for (i = 0; i < 8; i++) + ctx->h[i] = sha512_h0[i]; +#endif /* UNROLL_LOOPS_SHA512 */ + + ctx->len = 0; + ctx->tot_len = 0; +} + +static void SHA512_transform(AvbSHA512Ctx* ctx, + const uint8_t* message, + unsigned int block_nb) { + uint64_t w[80]; + uint64_t wv[8]; + uint64_t t1, t2; + const uint8_t* sub_block; + int i, j; + + for (i = 0; i < (int)block_nb; i++) { + sub_block = message + (i << 7); + +#ifdef UNROLL_LOOPS_SHA512 + PACK64(&sub_block[0], &w[0]); + PACK64(&sub_block[8], &w[1]); + PACK64(&sub_block[16], &w[2]); + PACK64(&sub_block[24], &w[3]); + PACK64(&sub_block[32], &w[4]); + PACK64(&sub_block[40], &w[5]); + PACK64(&sub_block[48], &w[6]); + PACK64(&sub_block[56], &w[7]); + PACK64(&sub_block[64], &w[8]); + PACK64(&sub_block[72], &w[9]); + PACK64(&sub_block[80], &w[10]); + PACK64(&sub_block[88], &w[11]); + PACK64(&sub_block[96], &w[12]); + PACK64(&sub_block[104], &w[13]); + PACK64(&sub_block[112], &w[14]); + PACK64(&sub_block[120], &w[15]); + + SHA512_SCR(16); + SHA512_SCR(17); + SHA512_SCR(18); + SHA512_SCR(19); + SHA512_SCR(20); + SHA512_SCR(21); + SHA512_SCR(22); + SHA512_SCR(23); + SHA512_SCR(24); + SHA512_SCR(25); + SHA512_SCR(26); + SHA512_SCR(27); + SHA512_SCR(28); + SHA512_SCR(29); + SHA512_SCR(30); + SHA512_SCR(31); + SHA512_SCR(32); + SHA512_SCR(33); + SHA512_SCR(34); + SHA512_SCR(35); + SHA512_SCR(36); + SHA512_SCR(37); + SHA512_SCR(38); + SHA512_SCR(39); + SHA512_SCR(40); + SHA512_SCR(41); + SHA512_SCR(42); + SHA512_SCR(43); + SHA512_SCR(44); + SHA512_SCR(45); + SHA512_SCR(46); + SHA512_SCR(47); + SHA512_SCR(48); + SHA512_SCR(49); + SHA512_SCR(50); + SHA512_SCR(51); + SHA512_SCR(52); + SHA512_SCR(53); + SHA512_SCR(54); + SHA512_SCR(55); + SHA512_SCR(56); + SHA512_SCR(57); + SHA512_SCR(58); + SHA512_SCR(59); + SHA512_SCR(60); + SHA512_SCR(61); + SHA512_SCR(62); + SHA512_SCR(63); + SHA512_SCR(64); + SHA512_SCR(65); + SHA512_SCR(66); + SHA512_SCR(67); + SHA512_SCR(68); + SHA512_SCR(69); + SHA512_SCR(70); + SHA512_SCR(71); + SHA512_SCR(72); + SHA512_SCR(73); + SHA512_SCR(74); + SHA512_SCR(75); + SHA512_SCR(76); + SHA512_SCR(77); + SHA512_SCR(78); + SHA512_SCR(79); + + wv[0] = ctx->h[0]; + wv[1] = ctx->h[1]; + wv[2] = ctx->h[2]; + wv[3] = ctx->h[3]; + wv[4] = ctx->h[4]; + wv[5] = ctx->h[5]; + wv[6] = ctx->h[6]; + wv[7] = ctx->h[7]; + + j = 0; + + do { + SHA512_EXP(0, 1, 2, 3, 4, 5, 6, 7, j); + j++; + SHA512_EXP(7, 0, 1, 2, 3, 4, 5, 6, j); + j++; + SHA512_EXP(6, 7, 0, 1, 2, 3, 4, 5, j); + j++; + SHA512_EXP(5, 6, 7, 0, 1, 2, 3, 4, j); + j++; + SHA512_EXP(4, 5, 6, 7, 0, 1, 2, 3, j); + j++; + SHA512_EXP(3, 4, 5, 6, 7, 0, 1, 2, j); + j++; + SHA512_EXP(2, 3, 4, 5, 6, 7, 0, 1, j); + j++; + SHA512_EXP(1, 2, 3, 4, 5, 6, 7, 0, j); + j++; + } while (j < 80); + + ctx->h[0] += wv[0]; + ctx->h[1] += wv[1]; + ctx->h[2] += wv[2]; + ctx->h[3] += wv[3]; + ctx->h[4] += wv[4]; + ctx->h[5] += wv[5]; + ctx->h[6] += wv[6]; + ctx->h[7] += wv[7]; +#else + for (j = 0; j < 16; j++) { + PACK64(&sub_block[j << 3], &w[j]); + } + + for (j = 16; j < 80; j++) { + SHA512_SCR(j); + } + + for (j = 0; j < 8; j++) { + wv[j] = ctx->h[j]; + } + + for (j = 0; j < 80; j++) { + t1 = wv[7] + SHA512_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha512_k[j] + + w[j]; + t2 = SHA512_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); + wv[7] = wv[6]; + wv[6] = wv[5]; + wv[5] = wv[4]; + wv[4] = wv[3] + t1; + wv[3] = wv[2]; + wv[2] = wv[1]; + wv[1] = wv[0]; + wv[0] = t1 + t2; + } + + for (j = 0; j < 8; j++) + ctx->h[j] += wv[j]; +#endif /* UNROLL_LOOPS_SHA512 */ + } +} + +void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, uint32_t len) { + unsigned int block_nb; + unsigned int new_len, rem_len, tmp_len; + const uint8_t* shifted_data; + + tmp_len = AVB_SHA512_BLOCK_SIZE - ctx->len; + rem_len = len < tmp_len ? len : tmp_len; + + avb_memcpy(&ctx->block[ctx->len], data, rem_len); + + if (ctx->len + len < AVB_SHA512_BLOCK_SIZE) { + ctx->len += len; + return; + } + + new_len = len - rem_len; + block_nb = new_len / AVB_SHA512_BLOCK_SIZE; + + shifted_data = data + rem_len; + + SHA512_transform(ctx, ctx->block, 1); + SHA512_transform(ctx, shifted_data, block_nb); + + rem_len = new_len % AVB_SHA512_BLOCK_SIZE; + + avb_memcpy(ctx->block, &shifted_data[block_nb << 7], rem_len); + + ctx->len = rem_len; + ctx->tot_len += (block_nb + 1) << 7; +} + +uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) { + unsigned int block_nb; + unsigned int pm_len; + unsigned int len_b; + +#ifndef UNROLL_LOOPS_SHA512 + int i; +#endif + + block_nb = + 1 + ((AVB_SHA512_BLOCK_SIZE - 17) < (ctx->len % AVB_SHA512_BLOCK_SIZE)); + + len_b = (ctx->tot_len + ctx->len) << 3; + pm_len = block_nb << 7; + + avb_memset(ctx->block + ctx->len, 0, pm_len - ctx->len); + ctx->block[ctx->len] = 0x80; + UNPACK32(len_b, ctx->block + pm_len - 4); + + SHA512_transform(ctx, ctx->block, block_nb); + +#ifdef UNROLL_LOOPS_SHA512 + UNPACK64(ctx->h[0], &ctx->buf[0]); + UNPACK64(ctx->h[1], &ctx->buf[8]); + UNPACK64(ctx->h[2], &ctx->buf[16]); + UNPACK64(ctx->h[3], &ctx->buf[24]); + UNPACK64(ctx->h[4], &ctx->buf[32]); + UNPACK64(ctx->h[5], &ctx->buf[40]); + UNPACK64(ctx->h[6], &ctx->buf[48]); + UNPACK64(ctx->h[7], &ctx->buf[56]); +#else + for (i = 0; i < 8; i++) + UNPACK64(ctx->h[i], &ctx->buf[i << 3]); +#endif /* UNROLL_LOOPS_SHA512 */ + + return ctx->buf; +} diff --git a/lib/libavb/avb_slot_verify.c b/lib/libavb/avb_slot_verify.c new file mode 100644 index 00000000000..a941850d934 --- /dev/null +++ b/lib/libavb/avb_slot_verify.c @@ -0,0 +1,1366 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_slot_verify.h" +#include "avb_chain_partition_descriptor.h" +#include "avb_cmdline.h" +#include "avb_footer.h" +#include "avb_hash_descriptor.h" +#include "avb_hashtree_descriptor.h" +#include "avb_kernel_cmdline_descriptor.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" +#include "avb_version.h" + +/* Maximum number of partitions that can be loaded with avb_slot_verify(). */ +#define MAX_NUMBER_OF_LOADED_PARTITIONS 32 + +/* Maximum number of vbmeta images that can be loaded with avb_slot_verify(). */ +#define MAX_NUMBER_OF_VBMETA_IMAGES 32 + +/* Maximum size of a vbmeta image - 64 KiB. */ +#define VBMETA_MAX_SIZE (64 * 1024) + +/* Helper function to see if we should continue with verification in + * allow_verification_error=true mode if something goes wrong. See the + * comments for the avb_slot_verify() function for more information. + */ +static inline bool result_should_continue(AvbSlotVerifyResult result) { + switch (result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + return false; + + case AVB_SLOT_VERIFY_RESULT_OK: + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + return true; + } + + return false; +} + +static AvbSlotVerifyResult load_full_partition(AvbOps* ops, + const char* part_name, + uint64_t image_size, + uint8_t** out_image_buf, + bool* out_image_preloaded) { + size_t part_num_read; + AvbIOResult io_ret; + + /* Make sure that we do not overwrite existing data. */ + avb_assert(*out_image_buf == NULL); + avb_assert(!*out_image_preloaded); + + /* We are going to implicitly cast image_size from uint64_t to size_t in the + * following code, so we need to make sure that the cast is safe. */ + if (image_size != (size_t)(image_size)) { + avb_errorv(part_name, ": Partition size too large to load.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + + /* Try use a preloaded one. */ + if (ops->get_preloaded_partition != NULL) { + io_ret = ops->get_preloaded_partition( + ops, part_name, image_size, out_image_buf, &part_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error loading data from partition.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + + if (*out_image_buf != NULL) { + if (part_num_read != image_size) { + avb_errorv(part_name, ": Read incorrect number of bytes.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + *out_image_preloaded = true; + } + } + + /* Allocate and copy the partition. */ + if (!*out_image_preloaded) { + *out_image_buf = avb_malloc(image_size); + if (*out_image_buf == NULL) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } + + io_ret = ops->read_from_partition(ops, + part_name, + 0 /* offset */, + image_size, + *out_image_buf, + &part_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error loading data from partition.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + if (part_num_read != image_size) { + avb_errorv(part_name, ": Read incorrect number of bytes.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + } + + return AVB_SLOT_VERIFY_RESULT_OK; +} + +static AvbSlotVerifyResult read_persistent_digest(AvbOps* ops, + const char* part_name, + size_t expected_digest_size, + uint8_t* out_digest) { + char* persistent_value_name = NULL; + AvbIOResult io_ret = AVB_IO_RESULT_OK; + size_t stored_digest_size = 0; + + if (ops->read_persistent_value == NULL) { + avb_errorv(part_name, ": Persistent values are not implemented.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + persistent_value_name = + avb_strdupv(AVB_NPV_PERSISTENT_DIGEST_PREFIX, part_name, NULL); + if (persistent_value_name == NULL) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } + io_ret = ops->read_persistent_value(ops, + persistent_value_name, + expected_digest_size, + out_digest, + &stored_digest_size); + avb_free(persistent_value_name); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } else if (io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_VALUE) { + avb_errorv(part_name, ": Persistent digest does not exist.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } else if (io_ret == AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE || + io_ret == AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE || + expected_digest_size != stored_digest_size) { + avb_errorv( + part_name, ": Persistent digest is not of expected size.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error reading persistent digest.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + return AVB_SLOT_VERIFY_RESULT_OK; +} + +static AvbSlotVerifyResult load_and_verify_hash_partition( + AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + bool allow_verification_error, + const AvbDescriptor* descriptor, + AvbSlotVerifyData* slot_data) { + AvbHashDescriptor hash_desc; + const uint8_t* desc_partition_name = NULL; + const uint8_t* desc_salt; + const uint8_t* desc_digest; + char part_name[AVB_PART_NAME_MAX_SIZE]; + AvbSlotVerifyResult ret; + AvbIOResult io_ret; + uint8_t* image_buf = NULL; + bool image_preloaded = false; + uint8_t* digest; + size_t digest_len; + const char* found; + uint64_t image_size; + size_t expected_digest_len = 0; + uint8_t expected_digest_buf[AVB_SHA512_DIGEST_SIZE]; + const uint8_t* expected_digest = NULL; + + if (!avb_hash_descriptor_validate_and_byteswap( + (const AvbHashDescriptor*)descriptor, &hash_desc)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + desc_partition_name = + ((const uint8_t*)descriptor) + sizeof(AvbHashDescriptor); + desc_salt = desc_partition_name + hash_desc.partition_name_len; + desc_digest = desc_salt + hash_desc.salt_len; + + if (!avb_validate_utf8(desc_partition_name, hash_desc.partition_name_len)) { + avb_error("Partition name is not valid UTF-8.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Don't bother loading or validating unless the partition was + * requested in the first place. + */ + found = avb_strv_find_str(requested_partitions, + (const char*)desc_partition_name, + hash_desc.partition_name_len); + if (found == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_OK; + goto out; + } + + if ((hash_desc.flags & AVB_HASH_DESCRIPTOR_FLAGS_DO_NOT_USE_AB) != 0) { + /* No ab_suffix, just copy the partition name as is. */ + if (hash_desc.partition_name_len >= AVB_PART_NAME_MAX_SIZE) { + avb_error("Partition name does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + avb_memcpy(part_name, desc_partition_name, hash_desc.partition_name_len); + part_name[hash_desc.partition_name_len] = '\0'; + } else if (hash_desc.digest_len == 0 && avb_strlen(ab_suffix) != 0) { + /* No ab_suffix allowed for partitions without a digest in the descriptor + * because these partitions hold data unique to this device and are not + * updated using an A/B scheme. + */ + avb_error("Cannot use A/B with a persistent digest.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } else { + /* Add ab_suffix to the partition name. */ + if (!avb_str_concat(part_name, + sizeof part_name, + (const char*)desc_partition_name, + hash_desc.partition_name_len, + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + } + + /* If we're allowing verification errors then hash_desc.image_size + * may no longer match what's in the partition... so in this case + * just load the entire partition. + * + * For example, this can happen if a developer does 'fastboot flash + * boot /path/to/new/and/bigger/boot.img'. We want this to work + * since it's such a common workflow. + */ + image_size = hash_desc.image_size; + if (allow_verification_error) { + if (ops->get_size_of_partition == NULL) { + avb_errorv(part_name, + ": The get_size_of_partition() operation is " + "not implemented so we may not load the entire partition. " + "Please implement.", + NULL); + } else { + io_ret = ops->get_size_of_partition(ops, part_name, &image_size); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error determining partition size.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + avb_debugv(part_name, ": Loading entire partition.\n", NULL); + } + } + + ret = load_full_partition( + ops, part_name, image_size, &image_buf, &image_preloaded); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + + if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha256") == 0) { + AvbSHA256Ctx sha256_ctx; + avb_sha256_init(&sha256_ctx); + avb_sha256_update(&sha256_ctx, desc_salt, hash_desc.salt_len); + avb_sha256_update(&sha256_ctx, image_buf, hash_desc.image_size); + digest = avb_sha256_final(&sha256_ctx); + digest_len = AVB_SHA256_DIGEST_SIZE; + } else if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha512") == 0) { + AvbSHA512Ctx sha512_ctx; + avb_sha512_init(&sha512_ctx); + avb_sha512_update(&sha512_ctx, desc_salt, hash_desc.salt_len); + avb_sha512_update(&sha512_ctx, image_buf, hash_desc.image_size); + digest = avb_sha512_final(&sha512_ctx); + digest_len = AVB_SHA512_DIGEST_SIZE; + } else { + avb_errorv(part_name, ": Unsupported hash algorithm.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (hash_desc.digest_len == 0) { + // Expect a match to a persistent digest. + avb_debugv(part_name, ": No digest, using persistent digest.\n", NULL); + expected_digest_len = digest_len; + expected_digest = expected_digest_buf; + avb_assert(expected_digest_len <= sizeof(expected_digest_buf)); + ret = + read_persistent_digest(ops, part_name, digest_len, expected_digest_buf); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + } else { + // Expect a match to the digest in the descriptor. + expected_digest_len = hash_desc.digest_len; + expected_digest = desc_digest; + } + + if (digest_len != expected_digest_len) { + avb_errorv( + part_name, ": Digest in descriptor not of expected size.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (avb_safe_memcmp(digest, expected_digest, digest_len) != 0) { + avb_errorv(part_name, + ": Hash of data does not match digest in descriptor.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION; + goto out; + } + + ret = AVB_SLOT_VERIFY_RESULT_OK; + +out: + + /* If it worked and something was loaded, copy to slot_data. */ + if ((ret == AVB_SLOT_VERIFY_RESULT_OK || result_should_continue(ret)) && + image_buf != NULL) { + AvbPartitionData* loaded_partition; + if (slot_data->num_loaded_partitions == MAX_NUMBER_OF_LOADED_PARTITIONS) { + avb_errorv(part_name, ": Too many loaded partitions.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + loaded_partition = + &slot_data->loaded_partitions[slot_data->num_loaded_partitions++]; + loaded_partition->partition_name = avb_strdup(found); + loaded_partition->data_size = image_size; + loaded_partition->data = image_buf; + loaded_partition->preloaded = image_preloaded; + image_buf = NULL; + } + +fail: + if (image_buf != NULL && !image_preloaded) { + avb_free(image_buf); + } + return ret; +} + +static AvbSlotVerifyResult load_requested_partitions( + AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + AvbSlotVerifyData* slot_data) { + AvbSlotVerifyResult ret; + uint8_t* image_buf = NULL; + bool image_preloaded = false; + size_t n; + + if (ops->get_size_of_partition == NULL) { + avb_error("get_size_of_partition() not implemented.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + } + + for (n = 0; requested_partitions[n] != NULL; n++) { + char part_name[AVB_PART_NAME_MAX_SIZE]; + AvbIOResult io_ret; + uint64_t image_size; + AvbPartitionData* loaded_partition; + + if (!avb_str_concat(part_name, + sizeof part_name, + requested_partitions[n], + avb_strlen(requested_partitions[n]), + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + io_ret = ops->get_size_of_partition(ops, part_name, &image_size); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error determining partition size.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + avb_debugv(part_name, ": Loading entire partition.\n", NULL); + + ret = load_full_partition( + ops, part_name, image_size, &image_buf, &image_preloaded); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + + /* Move to slot_data. */ + if (slot_data->num_loaded_partitions == MAX_NUMBER_OF_LOADED_PARTITIONS) { + avb_errorv(part_name, ": Too many loaded partitions.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + loaded_partition = + &slot_data->loaded_partitions[slot_data->num_loaded_partitions++]; + loaded_partition->partition_name = avb_strdup(requested_partitions[n]); + if (loaded_partition->partition_name == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + loaded_partition->data_size = image_size; + loaded_partition->data = image_buf; /* Transferring the owner. */ + loaded_partition->preloaded = image_preloaded; + image_buf = NULL; + image_preloaded = false; + } + + ret = AVB_SLOT_VERIFY_RESULT_OK; + +out: + /* Free the current buffer if any. */ + if (image_buf != NULL && !image_preloaded) { + avb_free(image_buf); + } + /* Buffers that are already saved in slot_data will be handled by the caller + * even on failure. */ + return ret; +} + +static AvbSlotVerifyResult load_and_verify_vbmeta( + AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + bool allow_verification_error, + AvbVBMetaImageFlags toplevel_vbmeta_flags, + int rollback_index_location, + const char* partition_name, + size_t partition_name_len, + const uint8_t* expected_public_key, + size_t expected_public_key_length, + AvbSlotVerifyData* slot_data, + AvbAlgorithmType* out_algorithm_type, + AvbCmdlineSubstList* out_additional_cmdline_subst) { + char full_partition_name[AVB_PART_NAME_MAX_SIZE]; + AvbSlotVerifyResult ret; + AvbIOResult io_ret; + size_t vbmeta_offset; + size_t vbmeta_size; + uint8_t* vbmeta_buf = NULL; + size_t vbmeta_num_read; + AvbVBMetaVerifyResult vbmeta_ret; + const uint8_t* pk_data; + size_t pk_len; + AvbVBMetaImageHeader vbmeta_header; + uint64_t stored_rollback_index; + const AvbDescriptor** descriptors = NULL; + size_t num_descriptors; + size_t n; + bool is_main_vbmeta; + bool is_vbmeta_partition; + AvbVBMetaData* vbmeta_image_data = NULL; + + ret = AVB_SLOT_VERIFY_RESULT_OK; + + avb_assert(slot_data != NULL); + + /* Since we allow top-level vbmeta in 'boot', use + * rollback_index_location to determine whether we're the main + * vbmeta struct. + */ + is_main_vbmeta = (rollback_index_location == 0); + is_vbmeta_partition = (avb_strcmp(partition_name, "vbmeta") == 0); + + if (!avb_validate_utf8((const uint8_t*)partition_name, partition_name_len)) { + avb_error("Partition name is not valid UTF-8.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Construct full partition name. */ + if (!avb_str_concat(full_partition_name, + sizeof full_partition_name, + partition_name, + partition_name_len, + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + avb_debugv("Loading vbmeta struct from partition '", + full_partition_name, + "'.\n", + NULL); + + /* If we're loading from the main vbmeta partition, the vbmeta + * struct is in the beginning. Otherwise we have to locate it via a + * footer. + */ + if (is_vbmeta_partition) { + vbmeta_offset = 0; + vbmeta_size = VBMETA_MAX_SIZE; + } else { + uint8_t footer_buf[AVB_FOOTER_SIZE]; + size_t footer_num_read; + AvbFooter footer; + + io_ret = ops->read_from_partition(ops, + full_partition_name, + -AVB_FOOTER_SIZE, + AVB_FOOTER_SIZE, + footer_buf, + &footer_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(full_partition_name, ": Error loading footer.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + avb_assert(footer_num_read == AVB_FOOTER_SIZE); + + if (!avb_footer_validate_and_byteswap((const AvbFooter*)footer_buf, + &footer)) { + avb_errorv(full_partition_name, ": Error validating footer.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Basic footer sanity check since the data is untrusted. */ + if (footer.vbmeta_size > VBMETA_MAX_SIZE) { + avb_errorv( + full_partition_name, ": Invalid vbmeta size in footer.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + vbmeta_offset = footer.vbmeta_offset; + vbmeta_size = footer.vbmeta_size; + } + + vbmeta_buf = avb_malloc(vbmeta_size); + if (vbmeta_buf == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + io_ret = ops->read_from_partition(ops, + full_partition_name, + vbmeta_offset, + vbmeta_size, + vbmeta_buf, + &vbmeta_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + /* If we're looking for 'vbmeta' but there is no such partition, + * go try to get it from the boot partition instead. + */ + if (is_main_vbmeta && io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION && + is_vbmeta_partition) { + avb_debugv(full_partition_name, + ": No such partition. Trying 'boot' instead.\n", + NULL); + ret = load_and_verify_vbmeta(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + 0 /* toplevel_vbmeta_flags */, + 0 /* rollback_index_location */, + "boot", + avb_strlen("boot"), + NULL /* expected_public_key */, + 0 /* expected_public_key_length */, + slot_data, + out_algorithm_type, + out_additional_cmdline_subst); + goto out; + } else { + avb_errorv(full_partition_name, ": Error loading vbmeta data.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + } + avb_assert(vbmeta_num_read <= vbmeta_size); + + /* Check if the image is properly signed and get the public key used + * to sign the image. + */ + vbmeta_ret = + avb_vbmeta_image_verify(vbmeta_buf, vbmeta_num_read, &pk_data, &pk_len); + switch (vbmeta_ret) { + case AVB_VBMETA_VERIFY_RESULT_OK: + avb_assert(pk_data != NULL && pk_len > 0); + break; + + case AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED: + case AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH: + case AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH: + ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION; + avb_errorv(full_partition_name, + ": Error verifying vbmeta image: ", + avb_vbmeta_verify_result_to_string(vbmeta_ret), + "\n", + NULL); + if (!allow_verification_error) { + goto out; + } + break; + + case AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER: + /* No way to continue this case. */ + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + avb_errorv(full_partition_name, + ": Error verifying vbmeta image: invalid vbmeta header\n", + NULL); + goto out; + + case AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION: + /* No way to continue this case. */ + ret = AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION; + avb_errorv(full_partition_name, + ": Error verifying vbmeta image: unsupported AVB version\n", + NULL); + goto out; + } + + /* Byteswap the header. */ + avb_vbmeta_image_header_to_host_byte_order((AvbVBMetaImageHeader*)vbmeta_buf, + &vbmeta_header); + + /* If we're the toplevel, assign flags so they'll be passed down. */ + if (is_main_vbmeta) { + toplevel_vbmeta_flags = (AvbVBMetaImageFlags)vbmeta_header.flags; + } else { + if (vbmeta_header.flags != 0) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + avb_errorv(full_partition_name, + ": chained vbmeta image has non-zero flags\n", + NULL); + goto out; + } + } + + /* Check if key used to make signature matches what is expected. */ + if (pk_data != NULL) { + if (expected_public_key != NULL) { + avb_assert(!is_main_vbmeta); + if (expected_public_key_length != pk_len || + avb_safe_memcmp(expected_public_key, pk_data, pk_len) != 0) { + avb_errorv(full_partition_name, + ": Public key used to sign data does not match key in chain " + "partition descriptor.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED; + if (!allow_verification_error) { + goto out; + } + } + } else { + bool key_is_trusted = false; + const uint8_t* pk_metadata = NULL; + size_t pk_metadata_len = 0; + + if (vbmeta_header.public_key_metadata_size > 0) { + pk_metadata = vbmeta_buf + sizeof(AvbVBMetaImageHeader) + + vbmeta_header.authentication_data_block_size + + vbmeta_header.public_key_metadata_offset; + pk_metadata_len = vbmeta_header.public_key_metadata_size; + } + + avb_assert(is_main_vbmeta); + io_ret = ops->validate_vbmeta_public_key( + ops, pk_data, pk_len, pk_metadata, pk_metadata_len, &key_is_trusted); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(full_partition_name, + ": Error while checking public key used to sign data.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + if (!key_is_trusted) { + avb_errorv(full_partition_name, + ": Public key used to sign data rejected.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED; + if (!allow_verification_error) { + goto out; + } + } + } + } + + /* Check rollback index. */ + io_ret = ops->read_rollback_index( + ops, rollback_index_location, &stored_rollback_index); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(full_partition_name, + ": Error getting rollback index for location.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + if (vbmeta_header.rollback_index < stored_rollback_index) { + avb_errorv( + full_partition_name, + ": Image rollback index is less than the stored rollback index.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX; + if (!allow_verification_error) { + goto out; + } + } + + /* Copy vbmeta to vbmeta_images before recursing. */ + if (is_main_vbmeta) { + avb_assert(slot_data->num_vbmeta_images == 0); + } else { + avb_assert(slot_data->num_vbmeta_images > 0); + } + if (slot_data->num_vbmeta_images == MAX_NUMBER_OF_VBMETA_IMAGES) { + avb_errorv(full_partition_name, ": Too many vbmeta images.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + vbmeta_image_data = &slot_data->vbmeta_images[slot_data->num_vbmeta_images++]; + vbmeta_image_data->partition_name = avb_strdup(partition_name); + vbmeta_image_data->vbmeta_data = vbmeta_buf; + /* Note that |vbmeta_buf| is actually |vbmeta_num_read| bytes long + * and this includes data past the end of the image. Pass the + * actual size of the vbmeta image. Also, no need to use + * avb_safe_add() since the header has already been verified. + */ + vbmeta_image_data->vbmeta_size = + sizeof(AvbVBMetaImageHeader) + + vbmeta_header.authentication_data_block_size + + vbmeta_header.auxiliary_data_block_size; + vbmeta_image_data->verify_result = vbmeta_ret; + + /* If verification has been disabled by setting a bit in the image, + * we're done... except that we need to load the entirety of the + * requested partitions. + */ + if (vbmeta_header.flags & AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED) { + AvbSlotVerifyResult sub_ret; + avb_debugv( + full_partition_name, ": VERIFICATION_DISABLED bit is set.\n", NULL); + /* If load_requested_partitions() fail it is always a fatal + * failure (e.g. ERROR_INVALID_ARGUMENT, ERROR_OOM, etc.) rather + * than recoverable (e.g. one where result_should_continue() + * returns true) and we want to convey that error. + */ + sub_ret = load_requested_partitions( + ops, requested_partitions, ab_suffix, slot_data); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + } + goto out; + } + + /* Now go through all descriptors and take the appropriate action: + * + * - hash descriptor: Load data from partition, calculate hash, and + * checks that it matches what's in the hash descriptor. + * + * - hashtree descriptor: Do nothing since verification happens + * on-the-fly from within the OS. (Unless the descriptor uses a + * persistent digest, in which case we need to find it). + * + * - chained partition descriptor: Load the footer, load the vbmeta + * image, verify vbmeta image (includes rollback checks, hash + * checks, bail on chained partitions). + */ + descriptors = + avb_descriptor_get_all(vbmeta_buf, vbmeta_num_read, &num_descriptors); + for (n = 0; n < num_descriptors; n++) { + AvbDescriptor desc; + + if (!avb_descriptor_validate_and_byteswap(descriptors[n], &desc)) { + avb_errorv(full_partition_name, ": Descriptor is invalid.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + switch (desc.tag) { + case AVB_DESCRIPTOR_TAG_HASH: { + AvbSlotVerifyResult sub_ret; + sub_ret = load_and_verify_hash_partition(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + descriptors[n], + slot_data); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + if (!allow_verification_error || !result_should_continue(ret)) { + goto out; + } + } + } break; + + case AVB_DESCRIPTOR_TAG_CHAIN_PARTITION: { + AvbSlotVerifyResult sub_ret; + AvbChainPartitionDescriptor chain_desc; + const uint8_t* chain_partition_name; + const uint8_t* chain_public_key; + + /* Only allow CHAIN_PARTITION descriptors in the main vbmeta image. */ + if (!is_main_vbmeta) { + avb_errorv(full_partition_name, + ": Encountered chain descriptor not in main image.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (!avb_chain_partition_descriptor_validate_and_byteswap( + (AvbChainPartitionDescriptor*)descriptors[n], &chain_desc)) { + avb_errorv(full_partition_name, + ": Chain partition descriptor is invalid.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (chain_desc.rollback_index_location == 0) { + avb_errorv(full_partition_name, + ": Chain partition has invalid " + "rollback_index_location field.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + chain_partition_name = ((const uint8_t*)descriptors[n]) + + sizeof(AvbChainPartitionDescriptor); + chain_public_key = chain_partition_name + chain_desc.partition_name_len; + + sub_ret = + load_and_verify_vbmeta(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + toplevel_vbmeta_flags, + chain_desc.rollback_index_location, + (const char*)chain_partition_name, + chain_desc.partition_name_len, + chain_public_key, + chain_desc.public_key_len, + slot_data, + NULL, /* out_algorithm_type */ + NULL /* out_additional_cmdline_subst */); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + if (!result_should_continue(ret)) { + goto out; + } + } + } break; + + case AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE: { + const uint8_t* kernel_cmdline; + AvbKernelCmdlineDescriptor kernel_cmdline_desc; + bool apply_cmdline; + + if (!avb_kernel_cmdline_descriptor_validate_and_byteswap( + (AvbKernelCmdlineDescriptor*)descriptors[n], + &kernel_cmdline_desc)) { + avb_errorv(full_partition_name, + ": Kernel cmdline descriptor is invalid.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + kernel_cmdline = ((const uint8_t*)descriptors[n]) + + sizeof(AvbKernelCmdlineDescriptor); + + if (!avb_validate_utf8(kernel_cmdline, + kernel_cmdline_desc.kernel_cmdline_length)) { + avb_errorv(full_partition_name, + ": Kernel cmdline is not valid UTF-8.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Compare the flags for top-level VBMeta struct with flags in + * the command-line descriptor so command-line snippets only + * intended for a certain mode (dm-verity enabled/disabled) + * are skipped if applicable. + */ + apply_cmdline = true; + if (toplevel_vbmeta_flags & AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED) { + if (kernel_cmdline_desc.flags & + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_NOT_DISABLED) { + apply_cmdline = false; + } + } else { + if (kernel_cmdline_desc.flags & + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_DISABLED) { + apply_cmdline = false; + } + } + + if (apply_cmdline) { + if (slot_data->cmdline == NULL) { + slot_data->cmdline = + avb_calloc(kernel_cmdline_desc.kernel_cmdline_length + 1); + if (slot_data->cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + avb_memcpy(slot_data->cmdline, + kernel_cmdline, + kernel_cmdline_desc.kernel_cmdline_length); + } else { + /* new cmdline is: <existing_cmdline> + ' ' + <newcmdline> + '\0' */ + size_t orig_size = avb_strlen(slot_data->cmdline); + size_t new_size = + orig_size + 1 + kernel_cmdline_desc.kernel_cmdline_length + 1; + char* new_cmdline = avb_calloc(new_size); + if (new_cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + avb_memcpy(new_cmdline, slot_data->cmdline, orig_size); + new_cmdline[orig_size] = ' '; + avb_memcpy(new_cmdline + orig_size + 1, + kernel_cmdline, + kernel_cmdline_desc.kernel_cmdline_length); + avb_free(slot_data->cmdline); + slot_data->cmdline = new_cmdline; + } + } + } break; + + case AVB_DESCRIPTOR_TAG_HASHTREE: { + AvbHashtreeDescriptor hashtree_desc; + + if (!avb_hashtree_descriptor_validate_and_byteswap( + (AvbHashtreeDescriptor*)descriptors[n], &hashtree_desc)) { + avb_errorv( + full_partition_name, ": Hashtree descriptor is invalid.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* We only need to continue when there is no digest in the descriptor. + * This is because the only processing here is to find the digest and + * make it available on the kernel command line. + */ + if (hashtree_desc.root_digest_len == 0) { + char part_name[AVB_PART_NAME_MAX_SIZE]; + size_t digest_len = 0; + uint8_t digest_buf[AVB_SHA512_DIGEST_SIZE]; + const uint8_t* desc_partition_name = + ((const uint8_t*)descriptors[n]) + sizeof(AvbHashtreeDescriptor); + + if (!avb_validate_utf8(desc_partition_name, + hashtree_desc.partition_name_len)) { + avb_error("Partition name is not valid UTF-8.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* No ab_suffix for partitions without a digest in the descriptor + * because these partitions hold data unique to this device and are + * not updated using an A/B scheme. + */ + if ((hashtree_desc.flags & + AVB_HASHTREE_DESCRIPTOR_FLAGS_DO_NOT_USE_AB) == 0 && + avb_strlen(ab_suffix) != 0) { + avb_error("Cannot use A/B with a persistent root digest.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + if (hashtree_desc.partition_name_len >= AVB_PART_NAME_MAX_SIZE) { + avb_error("Partition name does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + avb_memcpy( + part_name, desc_partition_name, hashtree_desc.partition_name_len); + part_name[hashtree_desc.partition_name_len] = '\0'; + + /* Determine the expected digest size from the hash algorithm. */ + if (avb_strcmp((const char*)hashtree_desc.hash_algorithm, "sha1") == + 0) { + digest_len = AVB_SHA1_DIGEST_SIZE; + } else if (avb_strcmp((const char*)hashtree_desc.hash_algorithm, + "sha256") == 0) { + digest_len = AVB_SHA256_DIGEST_SIZE; + } else if (avb_strcmp((const char*)hashtree_desc.hash_algorithm, + "sha512") == 0) { + digest_len = AVB_SHA512_DIGEST_SIZE; + } else { + avb_errorv(part_name, ": Unsupported hash algorithm.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + ret = read_persistent_digest(ops, part_name, digest_len, digest_buf); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + + if (out_additional_cmdline_subst) { + ret = + avb_add_root_digest_substitution(part_name, + digest_buf, + digest_len, + out_additional_cmdline_subst); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + } + } + } break; + + case AVB_DESCRIPTOR_TAG_PROPERTY: + /* Do nothing. */ + break; + } + } + + if (rollback_index_location >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) { + avb_errorv( + full_partition_name, ": Invalid rollback_index_location.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + slot_data->rollback_indexes[rollback_index_location] = + vbmeta_header.rollback_index; + + if (out_algorithm_type != NULL) { + *out_algorithm_type = (AvbAlgorithmType)vbmeta_header.algorithm_type; + } + +out: + /* If |vbmeta_image_data| isn't NULL it means that it adopted + * |vbmeta_buf| so in that case don't free it here. + */ + if (vbmeta_image_data == NULL) { + if (vbmeta_buf != NULL) { + avb_free(vbmeta_buf); + } + } + if (descriptors != NULL) { + avb_free(descriptors); + } + return ret; +} + +AvbSlotVerifyResult avb_slot_verify(AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbSlotVerifyResult ret; + AvbSlotVerifyData* slot_data = NULL; + AvbAlgorithmType algorithm_type = AVB_ALGORITHM_TYPE_NONE; + bool using_boot_for_vbmeta = false; + AvbVBMetaImageHeader toplevel_vbmeta; + bool allow_verification_error = + (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + AvbCmdlineSubstList* additional_cmdline_subst = NULL; + + /* Fail early if we're missing the AvbOps needed for slot verification. + * + * For now, handle get_size_of_partition() not being implemented. In + * a later release we may change that. + */ + avb_assert(ops->read_is_device_unlocked != NULL); + avb_assert(ops->read_from_partition != NULL); + avb_assert(ops->validate_vbmeta_public_key != NULL); + avb_assert(ops->read_rollback_index != NULL); + avb_assert(ops->get_unique_guid_for_partition != NULL); + + if (out_data != NULL) { + *out_data = NULL; + } + + /* Allowing dm-verity errors defeats the purpose of verified boot so + * only allow this if set up to allow verification errors + * (e.g. typically only UNLOCKED mode). + */ + if (hashtree_error_mode == AVB_HASHTREE_ERROR_MODE_LOGGING && + !allow_verification_error) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT; + goto fail; + } + + slot_data = avb_calloc(sizeof(AvbSlotVerifyData)); + if (slot_data == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + slot_data->vbmeta_images = + avb_calloc(sizeof(AvbVBMetaData) * MAX_NUMBER_OF_VBMETA_IMAGES); + if (slot_data->vbmeta_images == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + slot_data->loaded_partitions = + avb_calloc(sizeof(AvbPartitionData) * MAX_NUMBER_OF_LOADED_PARTITIONS); + if (slot_data->loaded_partitions == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + + additional_cmdline_subst = avb_new_cmdline_subst_list(); + if (additional_cmdline_subst == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + + ret = load_and_verify_vbmeta(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + 0 /* toplevel_vbmeta_flags */, + 0 /* rollback_index_location */, + "vbmeta", + avb_strlen("vbmeta"), + NULL /* expected_public_key */, + 0 /* expected_public_key_length */, + slot_data, + &algorithm_type, + additional_cmdline_subst); + if (!allow_verification_error && ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto fail; + } + + /* If things check out, mangle the kernel command-line as needed. */ + if (result_should_continue(ret)) { + if (avb_strcmp(slot_data->vbmeta_images[0].partition_name, "vbmeta") != 0) { + avb_assert( + avb_strcmp(slot_data->vbmeta_images[0].partition_name, "boot") == 0); + using_boot_for_vbmeta = true; + } + + /* Byteswap top-level vbmeta header since we'll need it below. */ + avb_vbmeta_image_header_to_host_byte_order( + (const AvbVBMetaImageHeader*)slot_data->vbmeta_images[0].vbmeta_data, + &toplevel_vbmeta); + + /* Fill in |ab_suffix| field. */ + slot_data->ab_suffix = avb_strdup(ab_suffix); + if (slot_data->ab_suffix == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + + /* If verification is disabled, we are done ... we specifically + * don't want to add any androidboot.* options since verification + * is disabled. + */ + if (toplevel_vbmeta.flags & AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED) { + /* Since verification is disabled we didn't process any + * descriptors and thus there's no cmdline... so set root= such + * that the system partition is mounted. + */ + avb_assert(slot_data->cmdline == NULL); + slot_data->cmdline = + avb_strdup("root=PARTUUID=$(ANDROID_SYSTEM_PARTUUID)"); + if (slot_data->cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + } else { + /* Add options - any failure in avb_append_options() is either an + * I/O or OOM error. + */ + AvbSlotVerifyResult sub_ret = avb_append_options(ops, + slot_data, + &toplevel_vbmeta, + algorithm_type, + hashtree_error_mode); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + goto fail; + } + } + + /* Substitute $(ANDROID_SYSTEM_PARTUUID) and friends. */ + if (slot_data->cmdline != NULL) { + char* new_cmdline; + new_cmdline = avb_sub_cmdline(ops, + slot_data->cmdline, + ab_suffix, + using_boot_for_vbmeta, + additional_cmdline_subst); + if (new_cmdline != slot_data->cmdline) { + if (new_cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + avb_free(slot_data->cmdline); + slot_data->cmdline = new_cmdline; + } + } + + if (out_data != NULL) { + *out_data = slot_data; + } else { + avb_slot_verify_data_free(slot_data); + } + } + + avb_free_cmdline_subst_list(additional_cmdline_subst); + additional_cmdline_subst = NULL; + + if (!allow_verification_error) { + avb_assert(ret == AVB_SLOT_VERIFY_RESULT_OK); + } + + return ret; + +fail: + if (slot_data != NULL) { + avb_slot_verify_data_free(slot_data); + } + if (additional_cmdline_subst != NULL) { + avb_free_cmdline_subst_list(additional_cmdline_subst); + } + return ret; +} + +void avb_slot_verify_data_free(AvbSlotVerifyData* data) { + if (data->ab_suffix != NULL) { + avb_free(data->ab_suffix); + } + if (data->cmdline != NULL) { + avb_free(data->cmdline); + } + if (data->vbmeta_images != NULL) { + size_t n; + for (n = 0; n < data->num_vbmeta_images; n++) { + AvbVBMetaData* vbmeta_image = &data->vbmeta_images[n]; + if (vbmeta_image->partition_name != NULL) { + avb_free(vbmeta_image->partition_name); + } + if (vbmeta_image->vbmeta_data != NULL) { + avb_free(vbmeta_image->vbmeta_data); + } + } + avb_free(data->vbmeta_images); + } + if (data->loaded_partitions != NULL) { + size_t n; + for (n = 0; n < data->num_loaded_partitions; n++) { + AvbPartitionData* loaded_partition = &data->loaded_partitions[n]; + if (loaded_partition->partition_name != NULL) { + avb_free(loaded_partition->partition_name); + } + if (loaded_partition->data != NULL && !loaded_partition->preloaded) { + avb_free(loaded_partition->data); + } + } + avb_free(data->loaded_partitions); + } + avb_free(data); +} + +const char* avb_slot_verify_result_to_string(AvbSlotVerifyResult result) { + const char* ret = NULL; + + switch (result) { + case AVB_SLOT_VERIFY_RESULT_OK: + ret = "OK"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = "ERROR_OOM"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = "ERROR_IO"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + ret = "ERROR_VERIFICATION"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + ret = "ERROR_ROLLBACK_INDEX"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + ret = "ERROR_PUBLIC_KEY_REJECTED"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + ret = "ERROR_INVALID_METADATA"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + ret = "ERROR_UNSUPPORTED_VERSION"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = "ERROR_INVALID_ARGUMENT"; + break; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (ret == NULL) { + avb_error("Unknown AvbSlotVerifyResult value.\n"); + ret = "(unknown)"; + } + + return ret; +} + +void avb_slot_verify_data_calculate_vbmeta_digest(AvbSlotVerifyData* data, + AvbDigestType digest_type, + uint8_t* out_digest) { + bool ret = false; + size_t n; + + switch (digest_type) { + case AVB_DIGEST_TYPE_SHA256: { + AvbSHA256Ctx ctx; + avb_sha256_init(&ctx); + for (n = 0; n < data->num_vbmeta_images; n++) { + avb_sha256_update(&ctx, + data->vbmeta_images[n].vbmeta_data, + data->vbmeta_images[n].vbmeta_size); + } + avb_memcpy(out_digest, avb_sha256_final(&ctx), AVB_SHA256_DIGEST_SIZE); + ret = true; + } break; + + case AVB_DIGEST_TYPE_SHA512: { + AvbSHA512Ctx ctx; + avb_sha512_init(&ctx); + for (n = 0; n < data->num_vbmeta_images; n++) { + avb_sha512_update(&ctx, + data->vbmeta_images[n].vbmeta_data, + data->vbmeta_images[n].vbmeta_size); + } + avb_memcpy(out_digest, avb_sha512_final(&ctx), AVB_SHA512_DIGEST_SIZE); + ret = true; + } break; + + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (!ret) { + avb_fatal("Unknown digest type"); + } +} diff --git a/lib/libavb/avb_slot_verify.h b/lib/libavb/avb_slot_verify.h new file mode 100644 index 00000000000..73fd70d4ce2 --- /dev/null +++ b/lib/libavb/avb_slot_verify.h @@ -0,0 +1,340 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_SLOT_VERIFY_H_ +#define AVB_SLOT_VERIFY_H_ + +#include "avb_ops.h" +#include "avb_vbmeta_image.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Return codes used in avb_slot_verify(), see that function for + * documentation for each field. + * + * Use avb_slot_verify_result_to_string() to get a textual + * representation usable for error/debug output. + */ +typedef enum { + AVB_SLOT_VERIFY_RESULT_OK, + AVB_SLOT_VERIFY_RESULT_ERROR_OOM, + AVB_SLOT_VERIFY_RESULT_ERROR_IO, + AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION, + AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX, + AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED, + AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA, + AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION, + AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT +} AvbSlotVerifyResult; + +/* Various error handling modes for when verification fails using a + * hashtree at runtime inside the HLOS. + * + * AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE means that the OS + * will invalidate the current slot and restart. + * + * AVB_HASHTREE_ERROR_MODE_RESTART means that the OS will restart. + * + * AVB_HASHTREE_ERROR_MODE_EIO means that an EIO error will be + * returned to applications. + * + * AVB_HASHTREE_ERROR_MODE_LOGGING means that errors will be logged + * and corrupt data may be returned to applications. This mode should + * be used ONLY for diagnostics and debugging. It cannot be used + * unless AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is also + * used. + */ +typedef enum { + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, + AVB_HASHTREE_ERROR_MODE_RESTART, + AVB_HASHTREE_ERROR_MODE_EIO, + AVB_HASHTREE_ERROR_MODE_LOGGING +} AvbHashtreeErrorMode; + +/* Flags that influence how avb_slot_verify() works. + * + * If AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is NOT set then + * avb_slot_verify() will bail out as soon as an error is encountered + * and |out_data| is set only if AVB_SLOT_VERIFY_RESULT_OK is + * returned. + * + * Otherwise if AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is set + * avb_slot_verify() will continue verification efforts and |out_data| + * is also set if AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED, + * AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION, or + * AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX is returned. It is + * undefined which error is returned if more than one distinct error + * is encountered. It is guaranteed that AVB_SLOT_VERIFY_RESULT_OK is + * returned if, and only if, there are no errors. This mode is needed + * to boot valid but unverified slots when the device is unlocked. + * + * Also, if AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is set the + * contents loaded from |requested_partition| will be the contents of + * the entire partition instead of just the size specified in the hash + * descriptor. + */ +typedef enum { + AVB_SLOT_VERIFY_FLAGS_NONE = 0, + AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR = (1 << 0) +} AvbSlotVerifyFlags; + +/* Get a textual representation of |result|. */ +const char* avb_slot_verify_result_to_string(AvbSlotVerifyResult result); + +/* Maximum number of rollback index locations supported. */ +#define AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS 32 + +/* AvbPartitionData contains data loaded from partitions when using + * avb_slot_verify(). The |partition_name| field contains the name of + * the partition (without A/B suffix), |data| points to the loaded + * data which is |data_size| bytes long. If |preloaded| is set to true, + * this structure dose not own |data|. The caller of |avb_slot_verify| + * needs to make sure that the preloaded data outlives this + * |AvbPartitionData| structure. + * + * Note that this is strictly less than the partition size - it's only + * the image stored there, not the entire partition nor any of the + * metadata. + */ +typedef struct { + char* partition_name; + uint8_t* data; + size_t data_size; + bool preloaded; +} AvbPartitionData; + +/* AvbVBMetaData contains a vbmeta struct loaded from a partition when + * using avb_slot_verify(). The |partition_name| field contains the + * name of the partition (without A/B suffix), |vbmeta_data| points to + * the loaded data which is |vbmeta_size| bytes long. + * + * The |verify_result| field contains the result of + * avb_vbmeta_image_verify() on the data. This is guaranteed to be + * AVB_VBMETA_VERIFY_RESULT_OK for all vbmeta images if + * avb_slot_verify() returns AVB_SLOT_VERIFY_RESULT_OK. + * + * You can use avb_descriptor_get_all(), avb_descriptor_foreach(), and + * avb_vbmeta_image_header_to_host_byte_order() with this data. + */ +typedef struct { + char* partition_name; + uint8_t* vbmeta_data; + size_t vbmeta_size; + AvbVBMetaVerifyResult verify_result; +} AvbVBMetaData; + +/* AvbSlotVerifyData contains data needed to boot a particular slot + * and is returned by avb_slot_verify() if partitions in a slot are + * successfully verified. + * + * All data pointed to by this struct - including data in each item in + * the |partitions| array - will be freed when the + * avb_slot_verify_data_free() function is called. + * + * The |ab_suffix| field is the copy of the of |ab_suffix| field + * passed to avb_slot_verify(). It is the A/B suffix of the slot. This + * value includes the leading underscore - typical values are "" (if + * no slots are in use), "_a" (for the first slot), and "_b" (for the + * second slot). + * + * The VBMeta images that were checked are available in the + * |vbmeta_images| field. The field |num_vbmeta_images| contains the + * number of elements in this array. The first element - + * vbmeta_images[0] - is guaranteed to be from the partition with the + * top-level vbmeta struct. This is usually the "vbmeta" partition in + * the requested slot but if there is no "vbmeta" partition it can + * also be the "boot" partition. + * + * The partitions loaded and verified from from the slot are + * accessible in the |loaded_partitions| array. The field + * |num_loaded_partitions| contains the number of elements in this + * array. The order of partitions in this array may not necessarily be + * the same order as in the passed-in |requested_partitions| array. + * + * Rollback indexes for the verified slot are stored in the + * |rollback_indexes| field. Note that avb_slot_verify() will NEVER + * modify stored_rollback_index[n] locations e.g. it will never use + * the write_rollback_index() AvbOps operation. Instead it is the job + * of the caller of avb_slot_verify() to do this based on e.g. A/B + * policy and other factors. See libavb_ab/avb_ab_flow.c for an + * example of how to do this. + * + * The |cmdline| field is a NUL-terminated string in UTF-8 resulting + * from concatenating all |AvbKernelCmdlineDescriptor| and then + * performing proper substitution of the variables + * $(ANDROID_SYSTEM_PARTUUID), $(ANDROID_BOOT_PARTUUID), and + * $(ANDROID_VBMETA_PARTUUID) using the + * get_unique_guid_for_partition() operation in |AvbOps|. Additionally + * $(ANDROID_VERITY_MODE) will be replaced with the proper dm-verity + * option depending on the value of |hashtree_error_mode|. + * + * Additionally, the |cmdline| field will have the following kernel + * command-line options set (unless verification is disabled, see + * below): + * + * androidboot.veritymode: This is set to 'disabled' if the + * AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED flag is set in top-level + * vbmeta struct. Otherwise it is set to 'enforcing' if the + * passed-in hashtree error mode is AVB_HASHTREE_ERROR_MODE_RESTART + * or AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, 'eio' if it's + * set to AVB_HASHTREE_ERROR_MODE_EIO, and 'logging' if it's set to + * AVB_HASHTREE_ERROR_MODE_LOGGING. + * + * androidboot.vbmeta.invalidate_on_error: This is set to 'yes' only + * if hashtree validation isn't disabled and the passed-in hashtree + * error mode is AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE. + * + * androidboot.vbmeta.device_state: set to "locked" or "unlocked" + * depending on the result of the result of AvbOps's + * read_is_unlocked() function. + * + * androidboot.vbmeta.{hash_alg, size, digest}: Will be set to + * the digest of all images in |vbmeta_images|. + * + * androidboot.vbmeta.device: This is set to the value + * PARTUUID=$(ANDROID_VBMETA_PARTUUID) before substitution so it + * will end up pointing to the vbmeta partition for the verified + * slot. If there is no vbmeta partition it will point to the boot + * partition of the verified slot. + * + * androidboot.vbmeta.avb_version: This is set to the decimal value + * of AVB_VERSION_MAJOR followed by a dot followed by the decimal + * value of AVB_VERSION_MINOR, for example "1.0" or "1.4". This + * version number represents the vbmeta file format version + * supported by libavb copy used in the boot loader. This is not + * necessarily the same version number of the on-disk metadata for + * the slot that was verified. + * + * Note that androidboot.slot_suffix is not set in the |cmdline| field + * in |AvbSlotVerifyData| - you will have to set this yourself. + * + * If the |AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED| flag is set + * in the top-level vbmeta struct then only the top-level vbmeta + * struct is verified and descriptors will not processed. The return + * value will be set accordingly (if this flag is set via 'avbctl + * disable-verification' then the return value will be + * |AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION|) and + * |AvbSlotVerifyData| is returned. Additionally all partitions in the + * |requested_partitions| are loaded and the |cmdline| field is set to + * "root=PARTUUID=$(ANDROID_SYSTEM_PARTUUID)" and the GUID for the + * appropriate system partition is substituted in. Note that none of + * the androidboot.* options mentioned above will be set. + * + * This struct may grow in the future without it being considered an + * ABI break. + */ +typedef struct { + char* ab_suffix; + AvbVBMetaData* vbmeta_images; + size_t num_vbmeta_images; + AvbPartitionData* loaded_partitions; + size_t num_loaded_partitions; + char* cmdline; + uint64_t rollback_indexes[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; +} AvbSlotVerifyData; + +/* Calculates a digest of all vbmeta images in |data| using + * the digest indicated by |digest_type|. Stores the result + * in |out_digest| which must be large enough to hold a digest + * of the requested type. + */ +void avb_slot_verify_data_calculate_vbmeta_digest(AvbSlotVerifyData* data, + AvbDigestType digest_type, + uint8_t* out_digest); + +/* Frees a |AvbSlotVerifyData| including all data it points to. */ +void avb_slot_verify_data_free(AvbSlotVerifyData* data); + +/* Performs a full verification of the slot identified by |ab_suffix| + * and load and verify the contents of the partitions whose name is in + * the NULL-terminated string array |requested_partitions| (each + * partition must use hash verification). If not using A/B, pass an + * empty string (e.g. "", not NULL) for |ab_suffix|. This parameter + * must include the leading underscore, for example "_a" should be + * used to refer to the first slot. + * + * Typically the |requested_partitions| array only contains a single + * item for the boot partition, 'boot'. + * + * Verification includes loading and verifying data from the 'vbmeta', + * the requested hash partitions, and possibly other partitions (with + * |ab_suffix| appended), inspecting rollback indexes, and checking if + * the public key used to sign the data is acceptable. The functions + * in |ops| will be used to do this. + * + * If |out_data| is not NULL, it will be set to a newly allocated + * |AvbSlotVerifyData| struct containing all the data needed to + * actually boot the slot. This data structure should be freed with + * avb_slot_verify_data_free() when you are done with it. See below + * for when this is returned. + * + * The |flags| parameter is used to influence the semantics of + * avb_slot_verify() - for example the + * AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR flag can be used to + * ignore verification errors which is something needed in the + * UNLOCKED state. See the AvbSlotVerifyFlags enumeration for details. + * + * The |hashtree_error_mode| parameter should be set to the desired + * error handling mode when hashtree validation fails inside the + * HLOS. This value isn't used by libavb per se - it is forwarded to + * the HLOS through the androidboot.veritymode and + * androidboot.vbmeta.invalidate_on_error cmdline parameters. See the + * AvbHashtreeErrorMode enumeration for details. + * + * Also note that |out_data| is never set if + * AVB_SLOT_VERIFY_RESULT_ERROR_OOM, AVB_SLOT_VERIFY_RESULT_ERROR_IO, + * or AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA is returned. + * + * AVB_SLOT_VERIFY_RESULT_OK is returned if everything is verified + * correctly and all public keys are accepted. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED is returned if + * everything is verified correctly out but one or more public keys + * are not accepted. This includes the case where integrity data is + * not signed. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_OOM is returned if unable to + * allocate memory. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_IO is returned if an I/O error + * occurred while trying to load data or get a rollback index. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION is returned if the data + * did not verify, e.g. the digest didn't match or signature checks + * failed. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX is returned if a + * rollback index was less than its stored value. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA is returned if some + * of the metadata is invalid or inconsistent. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION is returned if + * some of the metadata requires a newer version of libavb than what + * is in use. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT is returned if the + * caller passed invalid parameters, for example trying to use + * AVB_HASHTREE_ERROR_MODE_LOGGING without + * AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR. + */ +AvbSlotVerifyResult avb_slot_verify(AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_SLOT_VERIFY_H_ */ diff --git a/lib/libavb/avb_sysdeps.h b/lib/libavb/avb_sysdeps.h new file mode 100644 index 00000000000..f032de4a2e0 --- /dev/null +++ b/lib/libavb/avb_sysdeps.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_SYSDEPS_H_ +#define AVB_SYSDEPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Change these includes to match your platform to bring in the + * equivalent types available in a normal C runtime. At least things + * like uint8_t, uint64_t, and bool (with |false|, |true| keywords) + * must be present. + */ +#include <common.h> + +/* If you don't have gcc or clang, these attribute macros may need to + * be adjusted. + */ +#define AVB_ATTR_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) +#define AVB_ATTR_PACKED __attribute__((packed)) +#define AVB_ATTR_NO_RETURN __attribute__((noreturn)) +#define AVB_ATTR_SENTINEL __attribute__((__sentinel__)) + +/* Size in bytes used for alignment. */ +#ifdef __LP64__ +#define AVB_ALIGNMENT_SIZE 8 +#else +#define AVB_ALIGNMENT_SIZE 4 +#endif + +/* Compare |n| bytes in |src1| and |src2|. + * + * Returns an integer less than, equal to, or greater than zero if the + * first |n| bytes of |src1| is found, respectively, to be less than, + * to match, or be greater than the first |n| bytes of |src2|. */ +int avb_memcmp(const void* src1, + const void* src2, + size_t n) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Compare two strings. + * + * Return an integer less than, equal to, or greater than zero if |s1| + * is found, respectively, to be less than, to match, or be greater + * than |s2|. + */ +int avb_strcmp(const char* s1, const char* s2); + +/* Copy |n| bytes from |src| to |dest|. */ +void* avb_memcpy(void* dest, const void* src, size_t n); + +/* Set |n| bytes starting at |s| to |c|. Returns |dest|. */ +void* avb_memset(void* dest, const int c, size_t n); + +/* Prints out a message. The string passed must be a NUL-terminated + * UTF-8 string. + */ +void avb_print(const char* message); + +/* Prints out a vector of strings. Each argument must point to a + * NUL-terminated UTF-8 string and NULL should be the last argument. + */ +void avb_printv(const char* message, ...) AVB_ATTR_SENTINEL; + +/* Aborts the program or reboots the device. */ +void avb_abort(void) AVB_ATTR_NO_RETURN; + +/* Allocates |size| bytes. Returns NULL if no memory is available, + * otherwise a pointer to the allocated memory. + * + * The memory is not initialized. + * + * The pointer returned is guaranteed to be word-aligned. + * + * The memory should be freed with avb_free() when you are done with it. + */ +void* avb_malloc_(size_t size) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Frees memory previously allocated with avb_malloc(). */ +void avb_free(void* ptr); + +/* Returns the lenght of |str|, excluding the terminating NUL-byte. */ +size_t avb_strlen(const char* str) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Divide the |dividend| by 10 and saves back to the pointer. Return the + * remainder. */ +uint32_t avb_div_by_10(uint64_t* dividend); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_SYSDEPS_H_ */ diff --git a/lib/libavb/avb_sysdeps_posix.c b/lib/libavb/avb_sysdeps_posix.c new file mode 100644 index 00000000000..e9addc1c877 --- /dev/null +++ b/lib/libavb/avb_sysdeps_posix.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include <stdarg.h> +#include <stdlib.h> + +#include "avb_sysdeps.h" + +int avb_memcmp(const void* src1, const void* src2, size_t n) { + return memcmp(src1, src2, n); +} + +void* avb_memcpy(void* dest, const void* src, size_t n) { + return memcpy(dest, src, n); +} + +void* avb_memset(void* dest, const int c, size_t n) { + return memset(dest, c, n); +} + +int avb_strcmp(const char* s1, const char* s2) { + return strcmp(s1, s2); +} + +size_t avb_strlen(const char* str) { + return strlen(str); +} + +uint32_t avb_div_by_10(uint64_t* dividend) { + uint32_t rem = (uint32_t)(*dividend % 10); + *dividend /= 10; + return rem; +} + +void avb_abort(void) { + hang(); +} + +void avb_print(const char* message) { + printf("%s", message); +} + +void avb_printv(const char* message, ...) { + va_list ap; + const char* m; + + va_start(ap, message); + for (m = message; m != NULL; m = va_arg(ap, const char*)) { + printf("%s", m); + } + va_end(ap); +} + +void* avb_malloc_(size_t size) { + return malloc(size); +} + +void avb_free(void* ptr) { + free(ptr); +} diff --git a/lib/libavb/avb_util.c b/lib/libavb/avb_util.c new file mode 100644 index 00000000000..405d625351e --- /dev/null +++ b/lib/libavb/avb_util.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_util.h" + +#include <stdarg.h> + +uint32_t avb_be32toh(uint32_t in) { + uint8_t* d = (uint8_t*)∈ + uint32_t ret; + ret = ((uint32_t)d[0]) << 24; + ret |= ((uint32_t)d[1]) << 16; + ret |= ((uint32_t)d[2]) << 8; + ret |= ((uint32_t)d[3]); + return ret; +} + +uint64_t avb_be64toh(uint64_t in) { + uint8_t* d = (uint8_t*)∈ + uint64_t ret; + ret = ((uint64_t)d[0]) << 56; + ret |= ((uint64_t)d[1]) << 48; + ret |= ((uint64_t)d[2]) << 40; + ret |= ((uint64_t)d[3]) << 32; + ret |= ((uint64_t)d[4]) << 24; + ret |= ((uint64_t)d[5]) << 16; + ret |= ((uint64_t)d[6]) << 8; + ret |= ((uint64_t)d[7]); + return ret; +} + +/* Converts a 32-bit unsigned integer from host to big-endian byte order. */ +uint32_t avb_htobe32(uint32_t in) { + union { + uint32_t word; + uint8_t bytes[4]; + } ret; + ret.bytes[0] = (in >> 24) & 0xff; + ret.bytes[1] = (in >> 16) & 0xff; + ret.bytes[2] = (in >> 8) & 0xff; + ret.bytes[3] = in & 0xff; + return ret.word; +} + +/* Converts a 64-bit unsigned integer from host to big-endian byte order. */ +uint64_t avb_htobe64(uint64_t in) { + union { + uint64_t word; + uint8_t bytes[8]; + } ret; + ret.bytes[0] = (in >> 56) & 0xff; + ret.bytes[1] = (in >> 48) & 0xff; + ret.bytes[2] = (in >> 40) & 0xff; + ret.bytes[3] = (in >> 32) & 0xff; + ret.bytes[4] = (in >> 24) & 0xff; + ret.bytes[5] = (in >> 16) & 0xff; + ret.bytes[6] = (in >> 8) & 0xff; + ret.bytes[7] = in & 0xff; + return ret.word; +} + +int avb_safe_memcmp(const void* s1, const void* s2, size_t n) { + const unsigned char* us1 = s1; + const unsigned char* us2 = s2; + int result = 0; + + if (0 == n) { + return 0; + } + + /* + * Code snippet without data-dependent branch due to Nate Lawson + * (nate@root.org) of Root Labs. + */ + while (n--) { + result |= *us1++ ^ *us2++; + } + + return result != 0; +} + +bool avb_safe_add_to(uint64_t* value, uint64_t value_to_add) { + uint64_t original_value; + + avb_assert(value != NULL); + + original_value = *value; + + *value += value_to_add; + if (*value < original_value) { + avb_error("Overflow when adding values.\n"); + return false; + } + + return true; +} + +bool avb_safe_add(uint64_t* out_result, uint64_t a, uint64_t b) { + uint64_t dummy; + if (out_result == NULL) { + out_result = &dummy; + } + *out_result = a; + return avb_safe_add_to(out_result, b); +} + +bool avb_validate_utf8(const uint8_t* data, size_t num_bytes) { + size_t n; + unsigned int num_cc; + + for (n = 0, num_cc = 0; n < num_bytes; n++) { + uint8_t c = data[n]; + + if (num_cc > 0) { + if ((c & (0x80 | 0x40)) == 0x80) { + /* 10xx xxxx */ + } else { + goto fail; + } + num_cc--; + } else { + if (c < 0x80) { + num_cc = 0; + } else if ((c & (0x80 | 0x40 | 0x20)) == (0x80 | 0x40)) { + /* 110x xxxx */ + num_cc = 1; + } else if ((c & (0x80 | 0x40 | 0x20 | 0x10)) == (0x80 | 0x40 | 0x20)) { + /* 1110 xxxx */ + num_cc = 2; + } else if ((c & (0x80 | 0x40 | 0x20 | 0x10 | 0x08)) == + (0x80 | 0x40 | 0x20 | 0x10)) { + /* 1111 0xxx */ + num_cc = 3; + } else { + goto fail; + } + } + } + + if (num_cc != 0) { + goto fail; + } + + return true; + +fail: + return false; +} + +bool avb_str_concat(char* buf, + size_t buf_size, + const char* str1, + size_t str1_len, + const char* str2, + size_t str2_len) { + uint64_t combined_len; + + if (!avb_safe_add(&combined_len, str1_len, str2_len)) { + avb_error("Overflow when adding string sizes.\n"); + return false; + } + + if (combined_len > buf_size - 1) { + avb_error("Insufficient buffer space.\n"); + return false; + } + + avb_memcpy(buf, str1, str1_len); + avb_memcpy(buf + str1_len, str2, str2_len); + buf[combined_len] = '\0'; + + return true; +} + +void* avb_malloc(size_t size) { + void* ret = avb_malloc_(size); + if (ret == NULL) { + avb_error("Failed to allocate memory.\n"); + return NULL; + } + return ret; +} + +void* avb_calloc(size_t size) { + void* ret = avb_malloc(size); + if (ret == NULL) { + return NULL; + } + + avb_memset(ret, '\0', size); + return ret; +} + +char* avb_strdup(const char* str) { + size_t len = avb_strlen(str); + char* ret = avb_malloc(len + 1); + if (ret == NULL) { + return NULL; + } + + avb_memcpy(ret, str, len); + ret[len] = '\0'; + + return ret; +} + +const char* avb_strstr(const char* haystack, const char* needle) { + size_t n, m; + + /* Look through |haystack| and check if the first character of + * |needle| matches. If so, check the rest of |needle|. + */ + for (n = 0; haystack[n] != '\0'; n++) { + if (haystack[n] != needle[0]) { + continue; + } + + for (m = 1;; m++) { + if (needle[m] == '\0') { + return haystack + n; + } + + if (haystack[n + m] != needle[m]) { + break; + } + } + } + + return NULL; +} + +const char* avb_strv_find_str(const char* const* strings, + const char* str, + size_t str_size) { + size_t n; + for (n = 0; strings[n] != NULL; n++) { + if (avb_strlen(strings[n]) == str_size && + avb_memcmp(strings[n], str, str_size) == 0) { + return strings[n]; + } + } + return NULL; +} + +char* avb_replace(const char* str, const char* search, const char* replace) { + char* ret = NULL; + size_t ret_len = 0; + size_t search_len, replace_len; + const char* str_after_last_replace; + + search_len = avb_strlen(search); + replace_len = avb_strlen(replace); + + str_after_last_replace = str; + while (*str != '\0') { + const char* s; + size_t num_before; + size_t num_new; + + s = avb_strstr(str, search); + if (s == NULL) { + break; + } + + num_before = s - str; + + if (ret == NULL) { + num_new = num_before + replace_len + 1; + ret = avb_malloc(num_new); + if (ret == NULL) { + goto out; + } + avb_memcpy(ret, str, num_before); + avb_memcpy(ret + num_before, replace, replace_len); + ret[num_new - 1] = '\0'; + ret_len = num_new - 1; + } else { + char* new_str; + num_new = ret_len + num_before + replace_len + 1; + new_str = avb_malloc(num_new); + if (new_str == NULL) { + goto out; + } + avb_memcpy(new_str, ret, ret_len); + avb_memcpy(new_str + ret_len, str, num_before); + avb_memcpy(new_str + ret_len + num_before, replace, replace_len); + new_str[num_new - 1] = '\0'; + avb_free(ret); + ret = new_str; + ret_len = num_new - 1; + } + + str = s + search_len; + str_after_last_replace = str; + } + + if (ret == NULL) { + ret = avb_strdup(str_after_last_replace); + if (ret == NULL) { + goto out; + } + } else { + size_t num_remaining = avb_strlen(str_after_last_replace); + size_t num_new = ret_len + num_remaining + 1; + char* new_str = avb_malloc(num_new); + if (new_str == NULL) { + goto out; + } + avb_memcpy(new_str, ret, ret_len); + avb_memcpy(new_str + ret_len, str_after_last_replace, num_remaining); + new_str[num_new - 1] = '\0'; + avb_free(ret); + ret = new_str; + ret_len = num_new - 1; + } + +out: + return ret; +} + +/* We only support a limited amount of strings in avb_strdupv(). */ +#define AVB_STRDUPV_MAX_NUM_STRINGS 32 + +char* avb_strdupv(const char* str, ...) { + va_list ap; + const char* strings[AVB_STRDUPV_MAX_NUM_STRINGS]; + size_t lengths[AVB_STRDUPV_MAX_NUM_STRINGS]; + size_t num_strings, n; + uint64_t total_length; + char *ret = NULL, *dest; + + num_strings = 0; + total_length = 0; + va_start(ap, str); + do { + size_t str_len = avb_strlen(str); + strings[num_strings] = str; + lengths[num_strings] = str_len; + if (!avb_safe_add_to(&total_length, str_len)) { + avb_fatal("Overflow while determining total length.\n"); + break; + } + num_strings++; + if (num_strings == AVB_STRDUPV_MAX_NUM_STRINGS) { + avb_fatal("Too many strings passed.\n"); + break; + } + str = va_arg(ap, const char*); + } while (str != NULL); + va_end(ap); + + ret = avb_malloc(total_length + 1); + if (ret == NULL) { + goto out; + } + + dest = ret; + for (n = 0; n < num_strings; n++) { + avb_memcpy(dest, strings[n], lengths[n]); + dest += lengths[n]; + } + *dest = '\0'; + avb_assert(dest == ret + total_length); + +out: + return ret; +} + +const char* avb_basename(const char* str) { + int64_t n; + size_t len; + + len = avb_strlen(str); + if (len >= 2) { + for (n = len - 2; n >= 0; n--) { + if (str[n] == '/') { + return str + n + 1; + } + } + } + return str; +} + +void avb_uppercase(char* str) { + size_t i; + for (i = 0; str[i] != '\0'; ++i) { + if (str[i] <= 0x7A && str[i] >= 0x61) { + str[i] -= 0x20; + } + } +} + +char* avb_bin2hex(const uint8_t* data, size_t data_len) { + const char hex_digits[17] = "0123456789abcdef"; + char* hex_data; + size_t n; + + hex_data = avb_malloc(data_len * 2 + 1); + if (hex_data == NULL) { + return NULL; + } + + for (n = 0; n < data_len; n++) { + hex_data[n * 2] = hex_digits[data[n] >> 4]; + hex_data[n * 2 + 1] = hex_digits[data[n] & 0x0f]; + } + hex_data[n * 2] = '\0'; + return hex_data; +} diff --git a/lib/libavb/avb_util.h b/lib/libavb/avb_util.h new file mode 100644 index 00000000000..26dc6b045ac --- /dev/null +++ b/lib/libavb/avb_util.h @@ -0,0 +1,268 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_UTIL_H_ +#define AVB_UTIL_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AVB_STRINGIFY(x) #x +#define AVB_TO_STRING(x) AVB_STRINGIFY(x) + +#ifdef AVB_ENABLE_DEBUG +/* Aborts the program if |expr| is false. + * + * This has no effect unless AVB_ENABLE_DEBUG is defined. + */ +#define avb_assert(expr) \ + do { \ + if (!(expr)) { \ + avb_fatal("assert fail: " #expr "\n"); \ + } \ + } while (0) +#else +#define avb_assert(expr) +#endif + +/* Aborts the program if reached. + * + * This has no effect unless AVB_ENABLE_DEBUG is defined. + */ +#ifdef AVB_ENABLE_DEBUG +#define avb_assert_not_reached() \ + do { \ + avb_fatal("assert_not_reached()\n"); \ + } while (0) +#else +#define avb_assert_not_reached() +#endif + +/* Aborts the program if |addr| is not word-aligned. + * + * This has no effect unless AVB_ENABLE_DEBUG is defined. + */ +#define avb_assert_aligned(addr) \ + avb_assert((((uintptr_t)addr) & (AVB_ALIGNMENT_SIZE - 1)) == 0) + +#ifdef AVB_ENABLE_DEBUG +/* Print functions, used for diagnostics. + * + * These have no effect unless AVB_ENABLE_DEBUG is defined. + */ +#define avb_debug(message) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": DEBUG: ", \ + message, \ + NULL); \ + } while (0) +#define avb_debugv(message, ...) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": DEBUG: ", \ + message, \ + ##__VA_ARGS__); \ + } while (0) +#else +#define avb_debug(message) +#define avb_debugv(message, ...) +#endif + +/* Prints out a message. This is typically used if a runtime-error + * occurs. + */ +#define avb_error(message) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": ERROR: ", \ + message, \ + NULL); \ + } while (0) +#define avb_errorv(message, ...) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": ERROR: ", \ + message, \ + ##__VA_ARGS__); \ + } while (0) + +/* Prints out a message and calls avb_abort(). + */ +#define avb_fatal(message) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": FATAL: ", \ + message, \ + NULL); \ + avb_abort(); \ + } while (0) +#define avb_fatalv(message, ...) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": FATAL: ", \ + message, \ + ##__VA_ARGS__); \ + avb_abort(); \ + } while (0) + +/* Converts a 32-bit unsigned integer from big-endian to host byte order. */ +uint32_t avb_be32toh(uint32_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Converts a 64-bit unsigned integer from big-endian to host byte order. */ +uint64_t avb_be64toh(uint64_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Converts a 32-bit unsigned integer from host to big-endian byte order. */ +uint32_t avb_htobe32(uint32_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Converts a 64-bit unsigned integer from host to big-endian byte order. */ +uint64_t avb_htobe64(uint64_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Compare |n| bytes starting at |s1| with |s2| and return 0 if they + * match, 1 if they don't. Returns 0 if |n|==0, since no bytes + * mismatched. + * + * Time taken to perform the comparison is only dependent on |n| and + * not on the relationship of the match between |s1| and |s2|. + * + * Note that unlike avb_memcmp(), this only indicates inequality, not + * whether |s1| is less than or greater than |s2|. + */ +int avb_safe_memcmp(const void* s1, + const void* s2, + size_t n) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Adds |value_to_add| to |value| with overflow protection. + * + * Returns false if the addition overflows, true otherwise. In either + * case, |value| is always modified. + */ +bool avb_safe_add_to(uint64_t* value, + uint64_t value_to_add) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Adds |a| and |b| with overflow protection, returning the value in + * |out_result|. + * + * It's permissible to pass NULL for |out_result| if you just want to + * check that the addition would not overflow. + * + * Returns false if the addition overflows, true otherwise. + */ +bool avb_safe_add(uint64_t* out_result, + uint64_t a, + uint64_t b) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Checks if |num_bytes| data at |data| is a valid UTF-8 + * string. Returns true if valid UTF-8, false otherwise. + */ +bool avb_validate_utf8(const uint8_t* data, + size_t num_bytes) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Concatenates |str1| (of |str1_len| bytes) and |str2| (of |str2_len| + * bytes) and puts the result in |buf| which holds |buf_size| + * bytes. The result is also guaranteed to be NUL terminated. Fail if + * there is not enough room in |buf| for the resulting string plus + * terminating NUL byte. + * + * Returns true if the operation succeeds, false otherwise. + */ +bool avb_str_concat(char* buf, + size_t buf_size, + const char* str1, + size_t str1_len, + const char* str2, + size_t str2_len); + +/* Like avb_malloc_() but prints a error using avb_error() if memory + * allocation fails. + */ +void* avb_malloc(size_t size) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Like avb_malloc() but sets the memory with zeroes. */ +void* avb_calloc(size_t size) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Duplicates a NUL-terminated string. Returns NULL on OOM. */ +char* avb_strdup(const char* str) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Duplicates a NULL-terminated array of NUL-terminated strings by + * concatenating them. The returned string will be + * NUL-terminated. Returns NULL on OOM. + */ +char* avb_strdupv(const char* str, + ...) AVB_ATTR_WARN_UNUSED_RESULT AVB_ATTR_SENTINEL; + +/* Finds the first occurrence of |needle| in the string |haystack| + * where both strings are NUL-terminated strings. The terminating NUL + * bytes are not compared. + * + * Returns NULL if not found, otherwise points into |haystack| for the + * first occurrence of |needle|. + */ +const char* avb_strstr(const char* haystack, + const char* needle) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Finds the first occurrence of |str| in the NULL-terminated string + * array |strings|. Each element in |strings| must be + * NUL-terminated. The string given by |str| need not be + * NUL-terminated but its size must be given in |str_size|. + * + * Returns NULL if not found, otherwise points into |strings| for the + * first occurrence of |str|. + */ +const char* avb_strv_find_str(const char* const* strings, + const char* str, + size_t str_size); + +/* Replaces all occurrences of |search| with |replace| in |str|. + * + * Returns a newly allocated string or NULL if out of memory. + */ +char* avb_replace(const char* str, + const char* search, + const char* replace) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Calculates the CRC-32 for data in |buf| of size |buf_size|. */ +uint32_t avb_crc32(const uint8_t* buf, size_t buf_size); + +/* Returns the basename of |str|. This is defined as the last path + * component, assuming the normal POSIX separator '/'. If there are no + * separators, returns |str|. + */ +const char* avb_basename(const char* str); + +/* Converts any ascii lowercase characters in |str| to uppercase in-place. + * |str| must be NUL-terminated and valid UTF-8. + */ +void avb_uppercase(char* str); + +/* Converts |data_len| bytes of |data| to hex and returns the result. Returns + * NULL on OOM. Caller must free the returned string with avb_free. + */ +char* avb_bin2hex(const uint8_t* data, size_t data_len); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_UTIL_H_ */ diff --git a/lib/libavb/avb_vbmeta_image.c b/lib/libavb/avb_vbmeta_image.c new file mode 100644 index 00000000000..a7e2322b9e0 --- /dev/null +++ b/lib/libavb/avb_vbmeta_image.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#include "avb_vbmeta_image.h" +#include "avb_crypto.h" +#include "avb_rsa.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_version.h" + +AvbVBMetaVerifyResult avb_vbmeta_image_verify( + const uint8_t* data, + size_t length, + const uint8_t** out_public_key_data, + size_t* out_public_key_length) { + AvbVBMetaVerifyResult ret; + AvbVBMetaImageHeader h; + uint8_t* computed_hash; + const AvbAlgorithmData* algorithm; + AvbSHA256Ctx sha256_ctx; + AvbSHA512Ctx sha512_ctx; + const uint8_t* header_block; + const uint8_t* authentication_block; + const uint8_t* auxiliary_block; + int verification_result; + + ret = AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER; + + if (out_public_key_data != NULL) { + *out_public_key_data = NULL; + } + if (out_public_key_length != NULL) { + *out_public_key_length = 0; + } + + /* Ensure magic is correct. */ + if (avb_safe_memcmp(data, AVB_MAGIC, AVB_MAGIC_LEN) != 0) { + avb_error("Magic is incorrect.\n"); + goto out; + } + + /* Before we byteswap, ensure length is long enough. */ + if (length < sizeof(AvbVBMetaImageHeader)) { + avb_error("Length is smaller than header.\n"); + goto out; + } + avb_vbmeta_image_header_to_host_byte_order((const AvbVBMetaImageHeader*)data, + &h); + + /* Ensure we don't attempt to access any fields if we do not meet + * the specified minimum version of libavb. + */ + if ((h.required_libavb_version_major != AVB_VERSION_MAJOR) || + (h.required_libavb_version_minor > AVB_VERSION_MINOR)) { + avb_error("Mismatch between image version and libavb version.\n"); + ret = AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION; + goto out; + } + + /* Ensure |release_string| ends with a NUL byte. */ + if (h.release_string[AVB_RELEASE_STRING_SIZE - 1] != '\0') { + avb_error("Release string does not end with a NUL byte.\n"); + goto out; + } + + /* Ensure inner block sizes are multiple of 64. */ + if ((h.authentication_data_block_size & 0x3f) != 0 || + (h.auxiliary_data_block_size & 0x3f) != 0) { + avb_error("Block size is not a multiple of 64.\n"); + goto out; + } + + /* Ensure block sizes all add up to at most |length|. */ + uint64_t block_total = sizeof(AvbVBMetaImageHeader); + if (!avb_safe_add_to(&block_total, h.authentication_data_block_size) || + !avb_safe_add_to(&block_total, h.auxiliary_data_block_size)) { + avb_error("Overflow while computing size of boot image.\n"); + goto out; + } + if (block_total > length) { + avb_error("Block sizes add up to more than given length.\n"); + goto out; + } + + uintptr_t data_ptr = (uintptr_t)data; + /* Ensure passed in memory doesn't wrap. */ + if (!avb_safe_add(NULL, (uint64_t)data_ptr, length)) { + avb_error("Boot image location and length mismatch.\n"); + goto out; + } + + /* Ensure hash and signature are entirely in the Authentication data block. */ + uint64_t hash_end; + if (!avb_safe_add(&hash_end, h.hash_offset, h.hash_size) || + hash_end > h.authentication_data_block_size) { + avb_error("Hash is not entirely in its block.\n"); + goto out; + } + uint64_t signature_end; + if (!avb_safe_add(&signature_end, h.signature_offset, h.signature_size) || + signature_end > h.authentication_data_block_size) { + avb_error("Signature is not entirely in its block.\n"); + goto out; + } + + /* Ensure public key is entirely in the Auxiliary data block. */ + uint64_t pubkey_end; + if (!avb_safe_add(&pubkey_end, h.public_key_offset, h.public_key_size) || + pubkey_end > h.auxiliary_data_block_size) { + avb_error("Public key is not entirely in its block.\n"); + goto out; + } + + /* Ensure public key metadata (if set) is entirely in the Auxiliary + * data block. */ + if (h.public_key_metadata_size > 0) { + uint64_t pubkey_md_end; + if (!avb_safe_add(&pubkey_md_end, + h.public_key_metadata_offset, + h.public_key_metadata_size) || + pubkey_md_end > h.auxiliary_data_block_size) { + avb_error("Public key metadata is not entirely in its block.\n"); + goto out; + } + } + + /* Bail early if there's no hash or signature. */ + if (h.algorithm_type == AVB_ALGORITHM_TYPE_NONE) { + ret = AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED; + goto out; + } + + /* Ensure algorithm field is supported. */ + algorithm = avb_get_algorithm_data(h.algorithm_type); + if (!algorithm) { + avb_error("Invalid or unknown algorithm.\n"); + goto out; + } + + /* Bail if the embedded hash size doesn't match the chosen algorithm. */ + if (h.hash_size != algorithm->hash_len) { + avb_error("Embedded hash has wrong size.\n"); + goto out; + } + + /* No overflow checks needed from here-on after since all block + * sizes and offsets have been verified above. + */ + + header_block = data; + authentication_block = header_block + sizeof(AvbVBMetaImageHeader); + auxiliary_block = authentication_block + h.authentication_data_block_size; + + switch (h.algorithm_type) { + /* Explicit fall-through: */ + case AVB_ALGORITHM_TYPE_SHA256_RSA2048: + case AVB_ALGORITHM_TYPE_SHA256_RSA4096: + case AVB_ALGORITHM_TYPE_SHA256_RSA8192: + avb_sha256_init(&sha256_ctx); + avb_sha256_update( + &sha256_ctx, header_block, sizeof(AvbVBMetaImageHeader)); + avb_sha256_update( + &sha256_ctx, auxiliary_block, h.auxiliary_data_block_size); + computed_hash = avb_sha256_final(&sha256_ctx); + break; + /* Explicit fall-through: */ + case AVB_ALGORITHM_TYPE_SHA512_RSA2048: + case AVB_ALGORITHM_TYPE_SHA512_RSA4096: + case AVB_ALGORITHM_TYPE_SHA512_RSA8192: + avb_sha512_init(&sha512_ctx); + avb_sha512_update( + &sha512_ctx, header_block, sizeof(AvbVBMetaImageHeader)); + avb_sha512_update( + &sha512_ctx, auxiliary_block, h.auxiliary_data_block_size); + computed_hash = avb_sha512_final(&sha512_ctx); + break; + default: + avb_error("Unknown algorithm.\n"); + goto out; + } + + if (avb_safe_memcmp(authentication_block + h.hash_offset, + computed_hash, + h.hash_size) != 0) { + avb_error("Hash does not match!\n"); + ret = AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH; + goto out; + } + + verification_result = + avb_rsa_verify(auxiliary_block + h.public_key_offset, + h.public_key_size, + authentication_block + h.signature_offset, + h.signature_size, + authentication_block + h.hash_offset, + h.hash_size, + algorithm->padding, + algorithm->padding_len); + + if (verification_result == 0) { + ret = AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH; + goto out; + } + + if (h.public_key_size > 0) { + if (out_public_key_data != NULL) { + *out_public_key_data = auxiliary_block + h.public_key_offset; + } + if (out_public_key_length != NULL) { + *out_public_key_length = h.public_key_size; + } + } + + ret = AVB_VBMETA_VERIFY_RESULT_OK; + +out: + return ret; +} + +void avb_vbmeta_image_header_to_host_byte_order(const AvbVBMetaImageHeader* src, + AvbVBMetaImageHeader* dest) { + avb_memcpy(dest, src, sizeof(AvbVBMetaImageHeader)); + + dest->required_libavb_version_major = + avb_be32toh(dest->required_libavb_version_major); + dest->required_libavb_version_minor = + avb_be32toh(dest->required_libavb_version_minor); + + dest->authentication_data_block_size = + avb_be64toh(dest->authentication_data_block_size); + dest->auxiliary_data_block_size = + avb_be64toh(dest->auxiliary_data_block_size); + + dest->algorithm_type = avb_be32toh(dest->algorithm_type); + + dest->hash_offset = avb_be64toh(dest->hash_offset); + dest->hash_size = avb_be64toh(dest->hash_size); + + dest->signature_offset = avb_be64toh(dest->signature_offset); + dest->signature_size = avb_be64toh(dest->signature_size); + + dest->public_key_offset = avb_be64toh(dest->public_key_offset); + dest->public_key_size = avb_be64toh(dest->public_key_size); + + dest->public_key_metadata_offset = + avb_be64toh(dest->public_key_metadata_offset); + dest->public_key_metadata_size = avb_be64toh(dest->public_key_metadata_size); + + dest->descriptors_offset = avb_be64toh(dest->descriptors_offset); + dest->descriptors_size = avb_be64toh(dest->descriptors_size); + + dest->rollback_index = avb_be64toh(dest->rollback_index); + dest->flags = avb_be32toh(dest->flags); +} + +const char* avb_vbmeta_verify_result_to_string(AvbVBMetaVerifyResult result) { + const char* ret = NULL; + + switch (result) { + case AVB_VBMETA_VERIFY_RESULT_OK: + ret = "OK"; + break; + case AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED: + ret = "OK_NOT_SIGNED"; + break; + case AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER: + ret = "INVALID_VBMETA_HEADER"; + break; + case AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION: + ret = "UNSUPPORTED_VERSION"; + break; + case AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH: + ret = "HASH_MISMATCH"; + break; + case AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH: + ret = "SIGNATURE_MISMATCH"; + break; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (ret == NULL) { + avb_error("Unknown AvbVBMetaVerifyResult value.\n"); + ret = "(unknown)"; + } + + return ret; +} diff --git a/lib/libavb/avb_vbmeta_image.h b/lib/libavb/avb_vbmeta_image.h new file mode 100644 index 00000000000..24f8519ff60 --- /dev/null +++ b/lib/libavb/avb_vbmeta_image.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_VBMETA_IMAGE_H_ +#define AVB_VBMETA_IMAGE_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "avb_crypto.h" +#include "avb_descriptor.h" + +/* Size of the vbmeta image header. */ +#define AVB_VBMETA_IMAGE_HEADER_SIZE 256 + +/* Magic for the vbmeta image header. */ +#define AVB_MAGIC "AVB0" +#define AVB_MAGIC_LEN 4 + +/* Maximum size of the release string including the terminating NUL byte. */ +#define AVB_RELEASE_STRING_SIZE 48 + +/* Flags for the vbmeta image. + * + * AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED: If this flag is set, + * hashtree image verification will be disabled. + * + * AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED: If this flag is set, + * verification will be disabled and descriptors will not be parsed. + */ +typedef enum { + AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED = (1 << 0), + AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED = (1 << 1) +} AvbVBMetaImageFlags; + +/* Binary format for header of the vbmeta image. + * + * The vbmeta image consists of three blocks: + * + * +-----------------------------------------+ + * | Header data - fixed size | + * +-----------------------------------------+ + * | Authentication data - variable size | + * +-----------------------------------------+ + * | Auxiliary data - variable size | + * +-----------------------------------------+ + * + * The "Header data" block is described by this struct and is always + * |AVB_VBMETA_IMAGE_HEADER_SIZE| bytes long. + * + * The "Authentication data" block is |authentication_data_block_size| + * bytes long and contains the hash and signature used to authenticate + * the vbmeta image. The type of the hash and signature is defined by + * the |algorithm_type| field. + * + * The "Auxiliary data" is |auxiliary_data_block_size| bytes long and + * contains the auxiliary data including the public key used to make + * the signature and descriptors. + * + * The public key is at offset |public_key_offset| with size + * |public_key_size| in this block. The size of the public key data is + * defined by the |algorithm_type| field. The format of the public key + * data is described in the |AvbRSAPublicKeyHeader| struct. + * + * The descriptors starts at |descriptors_offset| from the beginning + * of the "Auxiliary Data" block and take up |descriptors_size| + * bytes. Each descriptor is stored as a |AvbDescriptor| with tag and + * number of bytes following. The number of descriptors can be + * determined by walking this data until |descriptors_size| is + * exhausted. + * + * The size of each of the "Authentication data" and "Auxiliary data" + * blocks must be divisible by 64. This is to ensure proper alignment. + * + * Descriptors are free-form blocks stored in a part of the vbmeta + * image subject to the same integrity checks as the rest of the + * image. See the documentation for |AvbDescriptor| for well-known + * descriptors. See avb_descriptor_foreach() for a convenience + * function to iterate over descriptors. + * + * This struct is versioned, see the |required_libavb_version_major| + * and |required_libavb_version_minor| fields. This represents the + * minimum version of libavb required to verify the header and depends + * on the features (e.g. algorithms, descriptors) used. Note that this + * may be 1.0 even if generated by an avbtool from 1.4 but where no + * features introduced after 1.0 has been used. See the "Versioning + * and compatibility" section in the README.md file for more details. + * + * All fields are stored in network byte order when serialized. To + * generate a copy with fields swapped to native byte order, use the + * function avb_vbmeta_image_header_to_host_byte_order(). + * + * Before reading and/or using any of this data, you MUST verify it + * using avb_vbmeta_image_verify() and reject it unless it's signed by + * a known good public key. + */ +typedef struct AvbVBMetaImageHeader { + /* 0: Four bytes equal to "AVB0" (AVB_MAGIC). */ + uint8_t magic[AVB_MAGIC_LEN]; + + /* 4: The major version of libavb required for this header. */ + uint32_t required_libavb_version_major; + /* 8: The minor version of libavb required for this header. */ + uint32_t required_libavb_version_minor; + + /* 12: The size of the signature block. */ + uint64_t authentication_data_block_size; + /* 20: The size of the auxiliary data block. */ + uint64_t auxiliary_data_block_size; + + /* 28: The verification algorithm used, see |AvbAlgorithmType| enum. */ + uint32_t algorithm_type; + + /* 32: Offset into the "Authentication data" block of hash data. */ + uint64_t hash_offset; + /* 40: Length of the hash data. */ + uint64_t hash_size; + + /* 48: Offset into the "Authentication data" block of signature data. */ + uint64_t signature_offset; + /* 56: Length of the signature data. */ + uint64_t signature_size; + + /* 64: Offset into the "Auxiliary data" block of public key data. */ + uint64_t public_key_offset; + /* 72: Length of the public key data. */ + uint64_t public_key_size; + + /* 80: Offset into the "Auxiliary data" block of public key metadata. */ + uint64_t public_key_metadata_offset; + /* 88: Length of the public key metadata. Must be set to zero if there + * is no public key metadata. + */ + uint64_t public_key_metadata_size; + + /* 96: Offset into the "Auxiliary data" block of descriptor data. */ + uint64_t descriptors_offset; + /* 104: Length of descriptor data. */ + uint64_t descriptors_size; + + /* 112: The rollback index which can be used to prevent rollback to + * older versions. + */ + uint64_t rollback_index; + + /* 120: Flags from the AvbVBMetaImageFlags enumeration. This must be + * set to zero if the vbmeta image is not a top-level image. + */ + uint32_t flags; + + /* 124: Reserved to ensure |release_string| start on a 16-byte + * boundary. Must be set to zeroes. + */ + uint8_t reserved0[4]; + + /* 128: The release string from avbtool, e.g. "avbtool 1.0.0" or + * "avbtool 1.0.0 xyz_board Git-234abde89". Is guaranteed to be NUL + * terminated. Applications must not make assumptions about how this + * string is formatted. + */ + uint8_t release_string[AVB_RELEASE_STRING_SIZE]; + + /* 176: Padding to ensure struct is size AVB_VBMETA_IMAGE_HEADER_SIZE + * bytes. This must be set to zeroes. + */ + uint8_t reserved[80]; +} AVB_ATTR_PACKED AvbVBMetaImageHeader; + +/* Copies |src| to |dest|, byte-swapping fields in the process. + * + * Make sure you've verified |src| using avb_vbmeta_image_verify() + * before accessing the data and/or using this function. + */ +void avb_vbmeta_image_header_to_host_byte_order(const AvbVBMetaImageHeader* src, + AvbVBMetaImageHeader* dest); + +/* Return codes used in avb_vbmeta_image_verify(). + * + * AVB_VBMETA_VERIFY_RESULT_OK is returned if the vbmeta image header + * is valid, the hash is correct and the signature is correct. Keep in + * mind that you still need to check that you know the public key used + * to sign the image, see avb_vbmeta_image_verify() for details. + * + * AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED is returned if the vbmeta + * image header is valid but there is no signature or hash. + * + * AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER is returned if the + * header of the vbmeta image is invalid, for example, invalid magic + * or inconsistent data. + * + * AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION is returned if a) the + * vbmeta image requires a minimum version of libavb which exceeds the + * version of libavb used; or b) the vbmeta image major version + * differs from the major version of libavb in use. + * + * AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH is returned if the hash + * stored in the "Authentication data" block does not match the + * calculated hash. + * + * AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH is returned if the + * signature stored in the "Authentication data" block is invalid or + * doesn't match the public key stored in the vbmeta image. + */ +typedef enum { + AVB_VBMETA_VERIFY_RESULT_OK, + AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED, + AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER, + AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION, + AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH, + AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH, +} AvbVBMetaVerifyResult; + +/* Get a textual representation of |result|. */ +const char* avb_vbmeta_verify_result_to_string(AvbVBMetaVerifyResult result); + +/* Checks that vbmeta image at |data| of size |length| is a valid + * vbmeta image. The complete contents of the vbmeta image must be + * passed in. It's fine if |length| is bigger than the actual image, + * typically callers of this function will load the entire contents of + * the 'vbmeta_a' or 'vbmeta_b' partition and pass in its length (for + * example, 1 MiB). + * + * See the |AvbVBMetaImageHeader| struct for information about the + * three blocks (header, authentication, auxiliary) that make up a + * vbmeta image. + * + * If the function returns |AVB_VBMETA_VERIFY_RESULT_OK| and + * |out_public_key_data| is non-NULL, it will be set to point inside + * |data| for where the serialized public key data is stored and + * |out_public_key_length|, if non-NULL, will be set to the length of + * the public key data. If there is no public key in the metadata then + * |out_public_key_data| is set to NULL. + * + * See the |AvbVBMetaVerifyResult| enum for possible return values. + * + * VERY IMPORTANT: + * + * 1. Even if |AVB_VBMETA_VERIFY_RESULT_OK| is returned, you still + * need to check that the public key embedded in the image + * matches a known key! You can use 'avbtool extract_public_key' + * to extract the key (at build time, then store it along your + * code) and compare it to what is returned in + * |out_public_key_data|. + * + * 2. You need to check the |rollback_index| field against a stored + * value in NVRAM and reject the vbmeta image if the value in + * NVRAM is bigger than |rollback_index|. You must also update + * the value stored in NVRAM to the smallest value of + * |rollback_index| field from boot images in all bootable and + * authentic slots marked as GOOD. + * + * This is a low-level function to only verify the vbmeta data - you + * are likely looking for avb_slot_verify() instead for verifying + * integrity data for a whole set of partitions. + */ +AvbVBMetaVerifyResult avb_vbmeta_image_verify( + const uint8_t* data, + size_t length, + const uint8_t** out_public_key_data, + size_t* out_public_key_length) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_VBMETA_IMAGE_H_ */ diff --git a/lib/libavb/avb_version.c b/lib/libavb/avb_version.c new file mode 100644 index 00000000000..1f20722e6ca --- /dev/null +++ b/lib/libavb/avb_version.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2017 The Android Open Source Project + */ + +#include "avb_version.h" + +#define AVB_QUOTE(str) #str +#define AVB_EXPAND_AND_QUOTE(str) AVB_QUOTE(str) + +/* Keep in sync with get_release_string() in avbtool. */ +const char* avb_version_string(void) { + return AVB_EXPAND_AND_QUOTE(AVB_VERSION_MAJOR) "." AVB_EXPAND_AND_QUOTE( + AVB_VERSION_MINOR) "." AVB_EXPAND_AND_QUOTE(AVB_VERSION_SUB); +} diff --git a/lib/libavb/avb_version.h b/lib/libavb/avb_version.h new file mode 100644 index 00000000000..57c6ece851c --- /dev/null +++ b/lib/libavb/avb_version.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2017 The Android Open Source Project + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_VERSION_H_ +#define AVB_VERSION_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* The version number of AVB - keep in sync with avbtool. */ +#define AVB_VERSION_MAJOR 1 +#define AVB_VERSION_MINOR 1 +#define AVB_VERSION_SUB 0 + +/* Returns a NUL-terminated string for the libavb version in use. The + * returned string usually looks like "%d.%d.%d". Applications must + * not make assumptions about the content of this string. + * + * Boot loaders should display this string in debug/diagnostics output + * to aid with debugging. + * + * This is similar to the string put in the |release_string| string + * field in the VBMeta struct by avbtool. + */ +const char* avb_version_string(void); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_VERSION_H_ */ diff --git a/lib/libavb/libavb.h b/lib/libavb/libavb.h new file mode 100644 index 00000000000..ac92a2bcb8a --- /dev/null +++ b/lib/libavb/libavb.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2016 The Android Open Source Project + */ + +#ifndef LIBAVB_H_ +#define LIBAVB_H_ + +/* The AVB_INSIDE_LIBAVB_H preprocessor symbol is used to enforce + * library users to include only this file. All public interfaces, and + * only public interfaces, must be included here. + */ + +#define AVB_INSIDE_LIBAVB_H +#include "avb_chain_partition_descriptor.h" +#include "avb_crypto.h" +#include "avb_descriptor.h" +#include "avb_footer.h" +#include "avb_hash_descriptor.h" +#include "avb_hashtree_descriptor.h" +#include "avb_kernel_cmdline_descriptor.h" +#include "avb_ops.h" +#include "avb_property_descriptor.h" +#include "avb_slot_verify.h" +#include "avb_sysdeps.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" +#include "avb_version.h" +#undef AVB_INSIDE_LIBAVB_H + +#endif /* LIBAVB_H_ */ diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index d2788bf79a4..cfe09cc94c2 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -635,6 +635,15 @@ static int fdt_add_bignum(void *blob, int noffset, const char *prop_name, big2 = BN_new(); big32 = BN_new(); big2_32 = BN_new(); + + /* + * Note: This code assumes that all of the above succeed, or all fail. + * In practice memory allocations generally do not fail (unless the + * process is killed), so it does not seem worth handling each of these + * as a separate case. Technicaly this could leak memory on failure, + * but a) it won't happen in practice, and b) it doesn't matter as we + * will immediately exit with a failure code. + */ if (!tmp || !big2 || !big32 || !big2_32) { fprintf(stderr, "Out of memory (bignum)\n"); return -ENOMEM; @@ -667,15 +676,13 @@ static int fdt_add_bignum(void *blob, int noffset, const char *prop_name, * might fail several times */ ret = fdt_setprop(blob, noffset, prop_name, buf, size); - if (ret) - return -FDT_ERR_NOSPACE; free(buf); BN_free(tmp); BN_free(big2); BN_free(big32); BN_free(big2_32); - return ret; + return ret ? -FDT_ERR_NOSPACE : 0; } int rsa_add_verify_data(struct image_sign_info *info, void *keydest) diff --git a/net/Makefile b/net/Makefile index 07466879f50..ce363621685 100644 --- a/net/Makefile +++ b/net/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CMD_RARP) += rarp.o obj-$(CONFIG_CMD_SNTP) += sntp.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot.o +obj-$(CONFIG_CMD_WOL) += wol.o # Disable this warning as it is triggered by: # sprintf(buf, index ? "foo%d" : "foo", index) diff --git a/net/bootp.c b/net/bootp.c index 9d7cb5d30c1..9a2b512e4a7 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -147,9 +147,14 @@ static void store_net_params(struct bootp_hdr *bp) { #if !defined(CONFIG_BOOTP_SERVERIP) struct in_addr tmp_ip; + bool overwrite_serverip = true; + +#if defined(CONFIG_BOOTP_PREFER_SERVERIP) + overwrite_serverip = false; +#endif net_copy_ip(&tmp_ip, &bp->bp_siaddr); - if (tmp_ip.s_addr != 0) + if (tmp_ip.s_addr != 0 && (overwrite_serverip || !net_server_ip.s_addr)) net_copy_ip(&net_server_ip, &bp->bp_siaddr); memcpy(net_server_ethaddr, ((struct ethernet_hdr *)net_rx_packet)->et_src, 6); @@ -157,7 +162,8 @@ static void store_net_params(struct bootp_hdr *bp) #if defined(CONFIG_CMD_DHCP) !(dhcp_option_overload & OVERLOAD_FILE) && #endif - (strlen(bp->bp_file) > 0)) { + (strlen(bp->bp_file) > 0) && + !net_boot_file_name_explicit) { copy_filename(net_boot_file_name, bp->bp_file, sizeof(net_boot_file_name)); } @@ -889,10 +895,13 @@ static void dhcp_process_options(uchar *popt, uchar *end) case 66: /* Ignore TFTP server name */ break; case 67: /* Bootfile option */ - size = truncate_sz("Bootfile", - sizeof(net_boot_file_name), oplen); - memcpy(&net_boot_file_name, popt + 2, size); - net_boot_file_name[size] = 0; + if (!net_boot_file_name_explicit) { + size = truncate_sz("Bootfile", + sizeof(net_boot_file_name), + oplen); + memcpy(&net_boot_file_name, popt + 2, size); + net_boot_file_name[size] = 0; + } break; default: #if defined(CONFIG_BOOTP_VENDOREX) diff --git a/net/fastboot.c b/net/fastboot.c index a9f7c0743da..8afc5529cd9 100644 --- a/net/fastboot.c +++ b/net/fastboot.c @@ -309,7 +309,9 @@ void fastboot_start_server(void) fastboot_our_port = WELL_KNOWN_PORT; +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) fastboot_set_progress_callback(fastboot_timed_send_info); +#endif net_set_udp_handler(fastboot_handler); /* zero out server ether in case the server ip has changed */ diff --git a/net/net.c b/net/net.c index b4563a4cab1..f35695b4fc9 100644 --- a/net/net.c +++ b/net/net.c @@ -78,6 +78,12 @@ * - own IP address * We want: - network time * Next step: none + * + * WOL: + * + * Prerequisites: - own ethernet address + * We want: - magic packet or timeout + * Next step: none */ @@ -108,6 +114,9 @@ #if defined(CONFIG_CMD_SNTP) #include "sntp.h" #endif +#if defined(CONFIG_CMD_WOL) +#include "wol.h" +#endif /** BOOTP EXTENTIONS **/ @@ -165,6 +174,8 @@ ushort net_native_vlan = 0xFFFF; /* Boot File name */ char net_boot_file_name[1024]; +/* Indicates whether the file name was specified on the command line */ +bool net_boot_file_name_explicit; /* The actual transferred size of the bootfile (in bytes) */ u32 net_boot_file_size; /* Boot file size in blocks as reported by the DHCP server */ @@ -515,6 +526,11 @@ restart: link_local_start(); break; #endif +#if defined(CONFIG_CMD_WOL) + case WOL: + wol_start(); + break; +#endif default: break; } @@ -1281,6 +1297,11 @@ void net_process_received_packet(uchar *in_packet, int len) ntohs(ip->udp_src), ntohs(ip->udp_len) - UDP_HDR_SIZE); break; +#ifdef CONFIG_CMD_WOL + case PROT_WOL: + wol_receive(ip, len); + break; +#endif } } diff --git a/net/wol.c b/net/wol.c new file mode 100644 index 00000000000..946bd91b473 --- /dev/null +++ b/net/wol.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Lothar Felten, lothar.felten@gmail.com + */ + +#include <common.h> +#include <command.h> +#include <net.h> +#include <environment.h> +#include "wol.h" + +static ulong wol_timeout = WOL_DEFAULT_TIMEOUT; + +/* + * Check incoming Wake-on-LAN packet for: + * - sync bytes + * - sixteen copies of the target MAC address + * + * @param wol Wake-on-LAN packet + * @param len Packet length + */ +static int wol_check_magic(struct wol_hdr *wol, unsigned int len) +{ + int i; + + if (len < sizeof(struct wol_hdr)) + return 0; + + for (i = 0; i < WOL_SYNC_COUNT; i++) + if (wol->wol_sync[i] != WOL_SYNC_BYTE) + return 0; + + for (i = 0; i < WOL_MAC_REPETITIONS; i++) + if (memcmp(&wol->wol_dest[i * ARP_HLEN], + net_ethaddr, ARP_HLEN) != 0) + return 0; + + return 1; +} + +void wol_receive(struct ip_udp_hdr *ip, unsigned int len) +{ + struct wol_hdr *wol; + + wol = (struct wol_hdr *)ip; + + if (!wol_check_magic(wol, len)) + return; + + /* save the optional password using the ether-wake formats */ + /* don't check for exact length, the packet might have padding */ + if (len >= (sizeof(struct wol_hdr) + WOL_PASSWORD_6B)) { + eth_env_set_enetaddr("wolpassword", wol->wol_passwd); + } else if (len >= (sizeof(struct wol_hdr) + WOL_PASSWORD_4B)) { + char buffer[16]; + struct in_addr *ip = (struct in_addr *)(wol->wol_passwd); + + ip_to_string(*ip, buffer); + env_set("wolpassword", buffer); + } + net_set_state(NETLOOP_SUCCESS); +} + +static void wol_udp_handler(uchar *pkt, unsigned int dest, struct in_addr sip, + unsigned int src, unsigned int len) +{ + struct wol_hdr *wol; + + wol = (struct wol_hdr *)pkt; + + /* UDP destination port must be 0, 7 or 9 */ + if (dest != 0 && dest != 7 && dest != 9) + return; + + if (!wol_check_magic(wol, len)) + return; + + net_set_state(NETLOOP_SUCCESS); +} + +void wol_set_timeout(ulong timeout) +{ + wol_timeout = timeout; +} + +static void wol_timeout_handler(void) +{ + eth_halt(); + net_set_state(NETLOOP_FAIL); +} + +void wol_start(void) +{ + net_set_timeout_handler(wol_timeout, wol_timeout_handler); + net_set_udp_handler(wol_udp_handler); +} diff --git a/net/wol.h b/net/wol.h new file mode 100644 index 00000000000..ebc81f24b6e --- /dev/null +++ b/net/wol.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * wol - Wake-on-LAN + * + * Supports both Wake-on-LAN packet types: + * - EtherType 0x0842 packets + * - UDP packets on ports 0, 7 and 9. + * + * Copyright 2018 Lothar Felten, lothar.felten@gmail.com + */ + +#if defined(CONFIG_CMD_WOL) + +#ifndef __WOL_H__ +#define __WOL_H__ + +#include <net.h> + +/**********************************************************************/ + +#define WOL_SYNC_BYTE 0xFF +#define WOL_SYNC_COUNT 6 +#define WOL_MAC_REPETITIONS 16 +#define WOL_DEFAULT_TIMEOUT 5000 +#define WOL_PASSWORD_4B 4 +#define WOL_PASSWORD_6B 6 + +/* + * Wake-on-LAN header + */ +struct wol_hdr { + u8 wol_sync[WOL_SYNC_COUNT]; /* sync bytes */ + u8 wol_dest[WOL_MAC_REPETITIONS * ARP_HLEN]; /* 16x MAC */ + u8 wol_passwd[0]; /* optional */ +}; + +/* + * Initialize wol (beginning of netloop) + */ +void wol_start(void); + +/* + * Check incoming Wake-on-LAN packet for: + * - sync bytes + * - sixteen copies of the target MAC address + * + * Optionally store the four or six byte password in the environment + * variable "wolpassword" + * + * @param ip IP header in the packet + * @param len Packet length + */ +void wol_receive(struct ip_udp_hdr *ip, unsigned int len); + +/* + * Set the timeout for the reception of a Wake-on-LAN packet + * + * @param timeout in milliseconds + */ +void wol_set_timeout(ulong timeout); + +/**********************************************************************/ + +#endif /* __WOL_H__ */ +#endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 1a543375940..1219dcc3bef 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1937,6 +1937,7 @@ CONFIG_SPL_NAND_BASE CONFIG_SPL_NAND_BOOT CONFIG_SPL_NAND_DRIVERS CONFIG_SPL_NAND_ECC +CONFIG_SPL_NAND_IDENT CONFIG_SPL_NAND_INIT CONFIG_SPL_NAND_LOAD CONFIG_SPL_NAND_MINIMAL diff --git a/test/py/tests/test_avb.py b/test/py/tests/test_avb.py new file mode 100644 index 00000000000..7996e4845db --- /dev/null +++ b/test/py/tests/test_avb.py @@ -0,0 +1,116 @@ +# Copyright (c) 2018, Linaro Limited +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Android Verified Boot 2.0 Test + +""" +This tests Android Verified Boot 2.0 support in U-boot: + +For additional details about how to build proper vbmeta partition +check doc/README.avb2 + +For configuration verification: +- Corrupt boot partition and check for failure +- Corrupt vbmeta partition and check for failure +""" + +import pytest +import u_boot_utils as util + +# defauld mmc id +mmc_dev = 1 +temp_addr = 0x90000000 +temp_addr2 = 0x90002000 + +@pytest.mark.buildconfigspec('cmd_avb') +def test_avb_verify(u_boot_console): + """Run AVB 2.0 boot verification chain with avb subset of commands + """ + + success_str = "Verification passed successfully" + + response = u_boot_console.run_command('avb init %s' %str(mmc_dev)) + assert response == '' + response = u_boot_console.run_command('avb verify') + assert response.find(success_str) + + +@pytest.mark.buildconfigspec('cmd_avb') +def test_avb_mmc_uuid(u_boot_console): + """Check if 'avb get_uuid' works, compare results with + 'part list mmc 1' output + """ + + response = u_boot_console.run_command('avb init %s' % str(mmc_dev)) + assert response == '' + + response = u_boot_console.run_command('mmc rescan; mmc dev %s' % + str(mmc_dev)) + assert response.find('is current device') + + part_lines = u_boot_console.run_command('mmc part').splitlines() + part_list = {} + cur_partname = "" + + for line in part_lines: + if "\"" in line: + start_pt = line.find("\"") + end_pt = line.find("\"", start_pt + 1) + cur_partname = line[start_pt + 1: end_pt] + + if "guid:" in line: + guid_to_check = line.split("guid:\t") + part_list[cur_partname] = guid_to_check[1] + + # lets check all guids with avb get_guid + for part, guid in part_list.iteritems(): + avb_guid_resp = u_boot_console.run_command('avb get_uuid %s' % part) + assert guid == avb_guid_resp.split("UUID: ")[1] + + +@pytest.mark.buildconfigspec('cmd_avb') +def test_avb_read_rb(u_boot_console): + """Test reading rollback indexes + """ + + response = u_boot_console.run_command('avb init %s' % str(mmc_dev)) + assert response == '' + + response = u_boot_console.run_command('avb read_rb 1') + + +@pytest.mark.buildconfigspec('cmd_avb') +def test_avb_is_unlocked(u_boot_console): + """Test if device is in the unlocked state + """ + + response = u_boot_console.run_command('avb init %s' % str(mmc_dev)) + assert response == '' + + response = u_boot_console.run_command('avb is_unlocked') + + +@pytest.mark.buildconfigspec('cmd_avb') +def test_avb_mmc_read(u_boot_console): + """Test mmc read operation + """ + + response = u_boot_console.run_command('mmc rescan; mmc dev %s 0' % + str(mmc_dev)) + assert response.find('is current device') + + response = u_boot_console.run_command('mmc read 0x%x 0x100 0x1' % temp_addr) + assert response.find('read: OK') + + response = u_boot_console.run_command('avb init %s' % str(mmc_dev)) + assert response == '' + + response = u_boot_console.run_command('avb read_part xloader 0 100 0x%x' % + temp_addr2) + assert response.find('Read 512 bytes') + + # Now lets compare two buffers + response = u_boot_console.run_command('cmp 0x%x 0x%x 40' % + (temp_addr, temp_addr2)) + assert response.find('64 word') diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index f2b8b71ed74..8f44f599c1c 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -133,11 +133,11 @@ static int value_add(struct display_info *disp, struct value_node **headp, } str = strdup(str); + if (!str) + goto err_mem; node = malloc(sizeof(*node)); - if (!str || !node) { - fprintf(stderr, "Out of memory\n"); - return -1; - } + if (!node) + goto err_mem; node->next = *headp; node->type = type; node->include = include; @@ -145,6 +145,9 @@ static int value_add(struct display_info *disp, struct value_node **headp, *headp = node; return 0; +err_mem: + fprintf(stderr, "Out of memory\n"); + return -1; } static bool util_is_printable_string(const void *data, int len) @@ -773,7 +776,7 @@ char *utilfdt_read(const char *filename) */ static int do_fdtgrep(struct display_info *disp, const char *filename) { - struct fdt_region *region; + struct fdt_region *region = NULL; int max_regions; int count = 100; char path[1024]; @@ -801,7 +804,7 @@ static int do_fdtgrep(struct display_info *disp, const char *filename) * The first pass will count the regions, but if it is too many, * we do another pass to actually record them. */ - for (i = 0; i < 3; i++) { + for (i = 0; i < 2; i++) { region = malloc(count * sizeof(struct fdt_region)); if (!region) { fprintf(stderr, "Out of memory for %d regions\n", @@ -815,11 +818,14 @@ static int do_fdtgrep(struct display_info *disp, const char *filename) disp->flags); if (count < 0) { report_error("fdt_find_regions", count); + free(region); return -1; } if (count <= max_regions) break; free(region); + fprintf(stderr, "Internal error with fdtgrep_find_region)(\n"); + return -1; } /* Optionally print a list of regions */ diff --git a/tools/patman/README b/tools/patman/README index 606780e2ed9..7917fc8bdc3 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -107,6 +107,7 @@ patman.py. For reference, the useful ones (at the moment) shown below ignore_errors: True process_tags: False verbose: True +smtp_server: /path/to/sendmail <<< diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index 85372f3c0ad..3f7e0321447 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -149,7 +149,8 @@ class TestFunctional(unittest.TestCase): patchstream.InsertCoverLetter(cover_fname, series, count) series.DoChecks() cc_file = series.MakeCcFile(process_tags, cover_fname, - not ignore_bad_tags, add_maintainers) + not ignore_bad_tags, add_maintainers, + None) cmd = gitutil.EmailPatches(series, cover_fname, args, dry_run, not ignore_bad_tags, cc_file, in_reply_to=in_reply_to, thread=None) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 64ac0c8d3d6..9905bb0bbd8 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -332,7 +332,8 @@ def BuildEmailList(in_list, tag=None, alias=None, raise_on_error=True): return result def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, - self_only=False, alias=None, in_reply_to=None, thread=False): + self_only=False, alias=None, in_reply_to=None, thread=False, + smtp_server=None): """Email a patch series. Args: @@ -348,6 +349,7 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, Should be a message ID that this is in reply to. thread: True to add --thread to git send-email (make all patches reply to cover-letter or first patch in series) + smtp_server: SMTP server to use to send patches Returns: Git command that was/would be run @@ -405,6 +407,8 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, to = BuildEmailList([os.getenv('USER')], '--to', alias, raise_on_error) cc = [] cmd = ['git', 'send-email', '--annotate'] + if smtp_server: + cmd.append('--smtp-server=%s' % smtp_server) if in_reply_to: if type(in_reply_to) != str: in_reply_to = in_reply_to.encode('utf-8') diff --git a/tools/patman/patman.py b/tools/patman/patman.py index 8d2c78235a7..27a2febf704 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -38,6 +38,8 @@ parser.add_option('-i', '--ignore-errors', action='store_true', parser.add_option('-m', '--no-maintainers', action='store_false', dest='add_maintainers', default=True, help="Don't cc the file maintainers automatically") +parser.add_option('-l', '--limit-cc', dest='limit', type='int', + default=None, help='Limit the cc list to LIMIT entries [default: %default]') parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', default=False, help="Do a dry run (create but don't email patches)") parser.add_option('-p', '--project', default=project.DetectProject(), @@ -60,6 +62,8 @@ parser.add_option('--no-check', action='store_false', dest='check_patch', help="Don't check for patch compliance") parser.add_option('--no-tags', action='store_false', dest='process_tags', default=True, help="Don't process subject tags as aliaes") +parser.add_option('--smtp-server', type='str', + help="Specify the SMTP server to 'git send-email'") parser.add_option('-T', '--thread', action='store_true', dest='thread', default=False, help='Create patches as a single thread') @@ -157,7 +161,7 @@ else: cc_file = series.MakeCcFile(options.process_tags, cover_fname, not options.ignore_bad_tags, - options.add_maintainers) + options.add_maintainers, options.limit) # Email the patches out (giving the user time to check / cancel) cmd = '' @@ -165,7 +169,8 @@ else: if its_a_go: cmd = gitutil.EmailPatches(series, cover_fname, args, options.dry_run, not options.ignore_bad_tags, cc_file, - in_reply_to=options.in_reply_to, thread=options.thread) + in_reply_to=options.in_reply_to, thread=options.thread, + smtp_server=options.smtp_server) else: print(col.Color(col.RED, "Not sending emails due to errors/warnings")) diff --git a/tools/patman/series.py b/tools/patman/series.py index d526d4ee91d..2735afaf88f 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -202,7 +202,7 @@ class Series(dict): print(col.Color(col.RED, str)) def MakeCcFile(self, process_tags, cover_fname, raise_on_error, - add_maintainers): + add_maintainers, limit): """Make a cc file for us to use for per-commit Cc automation Also stores in self._generated_cc to make ShowActions() faster. @@ -215,6 +215,7 @@ class Series(dict): add_maintainers: Either: True/False to call the get_maintainers to CC maintainers List of maintainers to include (for testing) + limit: Limit the length of the Cc list Return: Filename of temp file created """ @@ -238,6 +239,8 @@ class Series(dict): print(col.Color(col.YELLOW, 'Skipping "%s"' % x)) cc = set(cc) - set(settings.bounces) cc = [m.encode('utf-8') if type(m) != str else m for m in cc] + if limit is not None: + cc = cc[:limit] all_ccs += cc print(commit.patch, ', '.join(set(cc)), file=fd) self._generated_cc[commit.patch] = cc diff --git a/tools/patman/test.py b/tools/patman/test.py index c7ba4e6bb47..e1b94bd1a7d 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -148,7 +148,7 @@ index 0000000..2234c87 --- /dev/null +++ b/common/bootstage.c @@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0+ ++%s +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * @@ -189,19 +189,22 @@ index 0000000..2234c87 1.7.3.1 ''' signoff = 'Signed-off-by: Simon Glass <sjg@chromium.org>\n' + license = '// SPDX-License-Identifier: GPL-2.0+' tab = ' ' indent = ' ' if data_type == 'good': pass elif data_type == 'no-signoff': signoff = '' + elif data_type == 'no-license': + license = '' elif data_type == 'spaces': tab = ' ' elif data_type == 'indent': indent = tab else: print('not implemented') - return data % (signoff, tab, indent, tab) + return data % (signoff, license, tab, indent, tab) def SetupData(self, data_type): inhandle, inname = tempfile.mkstemp() @@ -234,6 +237,17 @@ index 0000000..2234c87 self.assertEqual(result.lines, 62) os.remove(inf) + def testNoLicense(self): + inf = self.SetupData('no-license') + result = checkpatch.CheckPatch(inf) + self.assertEqual(result.ok, False) + self.assertEqual(len(result.problems), 1) + self.assertEqual(result.errors, 0) + self.assertEqual(result.warnings, 1) + self.assertEqual(result.checks, 0) + self.assertEqual(result.lines, 62) + os.remove(inf) + def testSpaces(self): inf = self.SetupData('spaces') result = checkpatch.CheckPatch(inf) |