diff options
67 files changed, 573 insertions, 516 deletions
diff --git a/.gitignore b/.gitignore index 272257a77bb..bb03833b5f2 100644 --- a/.gitignore +++ b/.gitignore @@ -75,6 +75,7 @@ fit-dtb.blob* /keep-syms-lto.* /*imx8mimage* /*imx8mcst* +/*rcar4-sa0* /drivers/video/u_boot_logo.S /test/overlay/test-fdt-overlay.dtbo.S /test/overlay/test-fdt-overlay-stacked.dtbo.S @@ -2529,7 +2529,7 @@ distclean: mrproper -o -name '.*.rej' -o -name '*%' -o -name 'core' \ -o -name '*.pyc' \) \ -type f -print | xargs rm -f - @rm -f boards.cfg CHANGELOG + @rm -f boards.cfg CHANGELOG .binman_stamp # See doc/develop/python_cq.rst PHONY += pylint pylint_err @@ -379,15 +379,6 @@ The following options need to be configured: CONFIG_SH_ETHER Support for Renesas on-chip Ethernet controller - CFG_SH_ETHER_USE_PORT - Define the number of ports to be used - - CFG_SH_ETHER_PHY_ADDR - Define the ETH PHY's address - - CFG_SH_ETHER_CACHE_WRITEBACK - If this option is set, the driver enables cache flush. - - TPM Support: CONFIG_TPM Support TPM devices. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 10404ce076e..17795f8f746 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -924,6 +924,7 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RZA1) += \ + r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r7s72100-genmai-u-boot.dtsi b/arch/arm/dts/r7s72100-genmai-u-boot.dtsi new file mode 100644 index 00000000000..782ebfea2fb --- /dev/null +++ b/arch/arm/dts/r7s72100-genmai-u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Genmai board + * Based on GR Peach, Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + */ + +/ { + soc { + bootph-all; + }; +}; + +&bsc { + bootph-all; +}; + +&ostm0 { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&scif2 { + bootph-all; + clock = <66666666>; /* ToDo: Replace by DM clock driver */ +}; + +&scif2_pins { + bootph-all; +}; diff --git a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index 744f4aaaad9..d88e839a890 100644 --- a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index 305c4861520..8269d967af9 100644 --- a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 84a28bf885c..0a1602cdd23 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index 6372f953956..d2a0406be17 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index d9a28fe9bab..518466aca35 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index aa5de3d0465..3905bf4e4f7 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dtsi b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index 34a735ae5b2..382bfe8cacd 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -14,7 +14,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c0/eeprom@50}>; bootph-all; }; }; @@ -22,10 +22,7 @@ &i2c0 { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; }; }; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index b6b7b8f3609..a52c5de4ddf 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -10,23 +10,16 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; &i2c_dvfs { - compatible = "renesas,iic-r8a77990", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dtsi b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 1922c40a438..19d19542efd 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c0/eeprom@50}>; bootph-all; }; }; @@ -18,10 +18,7 @@ &i2c0 { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; }; }; diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index 5aa61314834..bd6a3d0713f 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -7,73 +7,25 @@ / { binman: binman { - multiple-images; - section { filename = "flash.bin"; pad-byte = <0xff>; - /* Offset 0x0000 set to 0x0000_0000 */ - fill@0 { - offset = <0x0>; - size = <0x4>; - fill-byte = [00]; - }; - - /* Offset 0x300c set to 0x0000_0000 */ - fill@300c { - offset = <0x300c>; - size = <0x4>; - fill-byte = [00]; - }; - - /* Offset 0x3154 set to 0xeb21_0000 */ - fill@3154 { - offset = <0x3154>; - size = <0x2>; - fill-byte = [00]; - }; - - fill@3156 { - offset = <0x3156>; - size = <0x1>; - fill-byte = [21]; - }; - - fill@3157 { - offset = <0x3157>; - size = <0x1>; - fill-byte = [eb]; - }; - - /* Offset 0x3264 set to 0x0003_b000 */ - fill@3264 { - offset = <0x3264>; - size = <0x1>; - fill-byte = [00]; - }; - - fill@3265 { - offset = <0x3265>; - size = <0x1>; - fill-byte = [b0]; - }; - - fill@3266 { - offset = <0x3266>; - size = <0x1>; - fill-byte = [03]; - }; - - fill@3267 { - offset = <0x3267>; - size = <0x1>; - fill-byte = [00]; - }; - - u-boot-spl { - offset = <0x40000>; - align-end = <4>; + renesas-rcar4-sa0 { + filename = "sa0.bin"; + pad-byte = <0xff>; + renesas,loader-address = <CONFIG_SPL_TEXT_BASE>; + + /* + * This section starts after 0x40000 Bytes long + * header added by the renesas-rcar4-sa0 binman + * etype. That means u-boot-spl {} below starts + * at offset 0x40000 in flash.bin . + */ + u-boot-spl { + offset = <0x40000>; + align-end = <4>; + }; }; u-boot { diff --git a/arch/arm/mach-renesas/Kconfig.rza1 b/arch/arm/mach-renesas/Kconfig.rza1 index e88f9a2eedb..c9e2b835204 100644 --- a/arch/arm/mach-renesas/Kconfig.rza1 +++ b/arch/arm/mach-renesas/Kconfig.rza1 @@ -14,12 +14,16 @@ choice prompt "Renesas RZ/A1 board select" # Renesas Supported Boards +config TARGET_GENMAI + bool "GENMAI board" + config TARGET_GRPEACH bool "GR-PEACH board" endchoice # Renesas Supported Boards +source "board/renesas/genmai/Kconfig" source "board/renesas/grpeach/Kconfig" endif diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 317fce02d2b..9165ceab4a3 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -19,12 +19,12 @@ ifneq ($(CONFIG_RCAR_64),) obj-$(CONFIG_ARMV8_PSCI) += psci-rcar64.o endif -OBJCOPYFLAGS_u-boot-spl.srec := -O srec +OBJCOPYFLAGS_u-boot-spl.srec := -I binary -O srec --change-addresses=$(CONFIG_SPL_TEXT_BASE) quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ $(OBJCOPYFLAGS_$(@F)) $< $@ -spl/u-boot-spl.srec: spl/u-boot-spl FORCE +spl/u-boot-spl.srec: spl/u-boot-spl.bin FORCE $(call if_changed,objcopy) srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"} @@ -34,6 +34,15 @@ else srec_cat_le_cmd := "-l-e-constant" endif +ifneq ($(CONFIG_RCAR_GEN4),) +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ + -Output_Block_Size 16 \ + -generate 0xeb203000 0xeb203154 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xeb203154 0xeb203158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xeb203158 0xeb203264 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xeb203264 0xeb203268 $(srec_cat_le_cmd) $$(( ( $2 + 4 ) / 4 )) 4 +else ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),) # # The first 6 generate statements generate the R-Car Gen3 SCIF loader header. @@ -90,6 +99,7 @@ quiet_cmd_srec_cat = SRECCAT $@ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif +endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}')) diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index f656f361cd5..6e3f9547fee 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -74,7 +74,14 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) +#define out_64(a,v) writeq(v,a) +#define out_32(a,v) writel(v,a) +#define out_16(a,v) writew(v,a) #define out_8(a,v) writeb(v,a) + +#define in_64(a) readq(a) +#define in_32(a) readl(a) +#define in_16(a) readw(a) #define in_8(a) readb(a) #define clrbits(type, addr, clear) \ @@ -106,6 +113,18 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define clrbits_16(addr, clear) clrbits(16, addr, clear) +#define setbits_16(addr, set) setbits(16, addr, set) +#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set) + +#define clrbits_32(addr, clear) clrbits(32, addr, clear) +#define setbits_32(addr, set) setbits(32, addr, set) +#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set) + +#define clrbits_64(addr, clear) clrbits(64, addr, clear) +#define setbits_64(addr, set) setbits(64, addr, set) +#define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set) + /* I/O access functions */ int _inl(unsigned int addr); int _inw(unsigned int addr); diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 5e51b691178..1849c995aee 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -5,6 +5,7 @@ # # R-Car SoCs +ifndef CONFIG_RZA1 ifndef CONFIG_RZG2L # 32 bit SoCs @@ -45,3 +46,10 @@ endif endif endif +endif + +# RZ/A1 SoCs +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif diff --git a/board/renesas/common/rza1-common.c b/board/renesas/common/rza1-common.c new file mode 100644 index 00000000000..5027319a58a --- /dev/null +++ b/board/renesas/common/rza1-common.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <init.h> +#include <asm/io.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/common/rza1-lowlevel_init.S index b83c4e86867..b83c4e86867 100644 --- a/board/renesas/grpeach/lowlevel_init.S +++ b/board/renesas/common/rza1-lowlevel_init.S diff --git a/board/renesas/genmai/Kconfig b/board/renesas/genmai/Kconfig new file mode 100644 index 00000000000..4e67a9b325a --- /dev/null +++ b/board/renesas/genmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENMAI + +config SYS_BOARD + default "genmai" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "genmai" + +endif diff --git a/board/renesas/genmai/MAINTAINERS b/board/renesas/genmai/MAINTAINERS new file mode 100644 index 00000000000..1f1c2944632 --- /dev/null +++ b/board/renesas/genmai/MAINTAINERS @@ -0,0 +1,5 @@ +GENMAI BOARD +M: Magnus Damm <damm@opensource.se> +S: Maintained +F: arch/arm/dts/r7s72100* +N: genmai diff --git a/board/renesas/genmai/Makefile b/board/renesas/genmai/Makefile new file mode 100644 index 00000000000..73f5e45affd --- /dev/null +++ b/board/renesas/genmai/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Magnus Damm <damm@opensource.se> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := genmai.o diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c new file mode 100644 index 00000000000..8153aed15e3 --- /dev/null +++ b/board/renesas/genmai/genmai.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Magnus Damm <damm@opensource.se> + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> + +#define RZA1_BCR_BASE 0x3FFFC000 +#define CS0BCR (RZA1_BCR_BASE + 0x04) +#define CS0WCR (RZA1_BCR_BASE + 0x28) +#define CS1BCR (RZA1_BCR_BASE + 0x08) +#define CS1WCR (RZA1_BCR_BASE + 0x2c) + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* setup NOR Flash on CS0 and CS1 */ + writel(0x00000b40, CS0WCR); + writel(0x10000c00, CS0BCR); + writel(0x00000b40, CS1WCR); + writel(0x10000c00, CS1BCR); + return 0; +} + +/* + * The Genmai DT will most likely contain memory nodes describing the external + * SDRAM memory connected to CS2 and CS3, however we do not yet have any code + * in U-Boot to setup the memory controller. For now ignore DT and make use of + * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE. + */ + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + gd->ram_size = 10 << 20; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile index 48e185ce3e8..89f8e0e8544 100644 --- a/board/renesas/grpeach/Makefile +++ b/board/renesas/grpeach/Makefile @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a0..3a6393fdce1 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include <cpu_func.h> #include <errno.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ int dram_init_banksize(void) return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} diff --git a/cmd/Kconfig b/cmd/Kconfig index a8a52357fbd..b3b5be1ea79 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -414,7 +414,7 @@ config BOOTM_RTEMS config CMD_SEAMA bool "Support read SEAMA NAND images" - depends on MTD_RAW_NAND + depends on (TARGET_BCMNS || TARGET_BCMNS3) && MTD_RAW_NAND help Support reading NAND Seattle Image (SEAMA) images. diff --git a/common/log_syslog.c b/common/log_syslog.c index 0dcb5f7cdea..73bd3aca07e 100644 --- a/common/log_syslog.c +++ b/common/log_syslog.c @@ -5,6 +5,7 @@ * Copyright (c) 2020, Heinrich Schuchardt <xypron.glpk@gmx.de> */ +#include <env.h> #include <log.h> #include <net.h> #include <asm/global_data.h> diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 9a17ccb2d3d..4e26b3940d8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1598,7 +1598,7 @@ config SPL_OPENSBI_SCRATCH_OPTIONS config SPL_TARGET string "Addtional build targets for 'make'" default "spl/u-boot-spl.srec" if RCAR_GEN2 - default "spl/u-boot-spl.scif" if RCAR_GEN3 + default "spl/u-boot-spl.scif" if RCAR_64 default "" help On some platforms we need to have 'make' run additional build target diff --git a/configs/genmai_defconfig b/configs/genmai_defconfig new file mode 100644 index 00000000000..d3407f671e2 --- /dev/null +++ b/configs/genmai_defconfig @@ -0,0 +1,17 @@ +#include <configs/renesas_rza1.config> + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-genmai" +CONFIG_TARGET_GENMAI=y + +CONFIG_ENV_IS_IN_MTD=y +CONFIG_ENV_MTD_DEV="nor0" +CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_MTD=y +CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 0f141b6f0a2..110af10860b 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -1,69 +1,18 @@ +#include <configs/renesas_rza1.config> + CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x18000000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-gr-peach" -CONFIG_RZA1=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_MONITOR_LEN=524288 -CONFIG_SYS_LOAD_ADDR=0x20400000 -CONFIG_SYS_CLK_FREQ=66666666 -# CONFIG_EFI_LOADER is not set -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="ignore_loglevel" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_BOARD_EARLY_INIT_F is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_ELF is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_USB=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MAC_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y +CONFIG_TARGET_GRPEACH=y + +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_MAX_HZ=50000000 +CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_RZA1_GPIO=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -# CONFIG_MMC is not set +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_BITBANGMII=y -CONFIG_PHY_SMSC=y -CONFIG_DM_ETH_PHY=y -CONFIG_SH_ETHER=y -CONFIG_PINCTRL=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SCIF_CONSOLE=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_RENESAS_RPC_SPI=y -CONFIG_TIMER=y -CONFIG_RENESAS_OSTM_TIMER=y -CONFIG_USB=y -CONFIG_USB_R8A66597_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/renesas_rza1.config b/configs/renesas_rza1.config new file mode 100644 index 00000000000..10d817f03a7 --- /dev/null +++ b/configs/renesas_rza1.config @@ -0,0 +1,55 @@ +CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x400 +# CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_CMD_ELF is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_MMC is not set +CONFIG_BITBANGMII=y +CONFIG_BOOTARGS="ignore_loglevel" +CONFIG_BOOTDELAY=3 +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_USB=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 +CONFIG_DM_ETH_PHY=y +CONFIG_DM_GPIO=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SPI=y +CONFIG_ENV_OVERWRITE=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MAC_PARTITION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PHY_SMSC=y +CONFIG_PINCTRL=y +CONFIG_RENESAS_OSTM_TIMER=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_RZA1=y +CONFIG_RZA1_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SH_ETHER=y +CONFIG_SPI=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_CLK_FREQ=66666666 +CONFIG_SYS_LOAD_ADDR=0x20400000 +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SYS_PBSIZE=256 +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_USB_R8A66597_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USE_BOOTARGS=y diff --git a/disk/part_dos.c b/disk/part_dos.c index 5c77225cef9..18dd35c9b98 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -421,7 +421,7 @@ int write_mbr_partitions(struct blk_desc *dev, /* write EBR */ if (blk_dwrite(dev, ext_part_sect, 1, buffer) != 1) { - printf("%s: failed writing 'EBR' (1 blks at 0x%lx)\n", + printf("%s: failed writing 'EBR' (1 blks at 0x" LBAF ")\n", __func__, ext_part_sect); return -1; } diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 37235f557a3..2b45f9e5eba 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -18,7 +18,7 @@ config SPL_ADC config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" - depends on ADC + depends on ADC && ARCH_EXYNOS5 help This enables basic driver for Exynos ADC compatible with Exynos54xx. It provides: @@ -49,7 +49,7 @@ config SARADC_MESON config SARADC_ROCKCHIP bool "Enable Rockchip SARADC driver" - depends on ADC + depends on ADC && ARCH_ROCKCHIP help This enables driver for Rockchip SARADC. It provides: diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 29ceab849c0..da9c72a99d0 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -131,6 +131,7 @@ config FSL_SATA_V2 config SATA_MV bool "Enable Marvell SATA controller driver support" + depends on ARCH_KIRKWOOD || ARCH_MVEBU select AHCI select LIBATA help @@ -148,7 +149,7 @@ config SATA_SIL config SYS_SATA_MAX_DEVICE int "Maximum number of SATA devices" - depends on !AHCI || FSL_SATA || SATA_MV + depends on !AHCI || FSL_SATA || SATA_MV || API help Sets the maximum number of SATA devices which can be supported by U-Boot. diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 6efcd7da738..401225b8528 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -1,3 +1,5 @@ +if ARCH_ASPEED + config ASPEED_HACE bool "ASPEED Hash and Crypto Engine" depends on DM_HASH @@ -38,3 +40,5 @@ config ASPEED_CPTRA_ECDSA Enabling this allows the use of ECDSA384 signature verification in hardware. Note that only ECDSA384 is supported by Caliptra. + +endif diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 9ed56632fcd..fe694f6022c 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -1,3 +1,5 @@ +if ARM || PPC + config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL @@ -95,3 +97,5 @@ config FSL_DCP_RNG module of the DCP. It uses the True Random Number Generator (TRNG) and a Pseudo-Random Number Generator (PRNG) to achieve a true randomness and cryptographic strength. + +endif diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig index aa355c44be8..72b955ac791 100644 --- a/drivers/crypto/hash/Kconfig +++ b/drivers/crypto/hash/Kconfig @@ -18,7 +18,7 @@ config HASH_SOFTWARE config HASH_ASPEED bool "Enable Hash with ASPEED hash accelerator" - depends on DM_HASH + depends on DM_HASH && ARCH_ASPEED select ASPEED_HACE help Enable this to support HW-assisted hashing operations using ASPEED Hash diff --git a/drivers/crypto/nuvoton/Kconfig b/drivers/crypto/nuvoton/Kconfig index 034fcadfcc8..0eb4396816e 100644 --- a/drivers/crypto/nuvoton/Kconfig +++ b/drivers/crypto/nuvoton/Kconfig @@ -1,5 +1,6 @@ config NPCM_AES bool "Support the NPCM AES algorithm" + depends on (ARM && ARCH_NPCM) select NPCM_OTP help This provides a means to encrypt and decrypt data using the NPCM diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e8ef90e2bd6..1fccbc96f07 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -37,6 +37,7 @@ config BCM6348_IUDMA config TI_EDMA3 bool "TI EDMA3 driver" + depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE select DMA_LEGACY help Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5dee00f832e..fd227d46f5a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -115,7 +115,7 @@ config ALTERA_PIO config BCM2835_GPIO bool "BCM2835 GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_BCM283X config BCM6345_GPIO bool "BCM6345 GPIO driver" @@ -140,6 +140,7 @@ config DWAPB_GPIO config AT91_GPIO bool "AT91 PIO GPIO driver" + depends on ARCH_AT91 help Say yes here to select AT91 PIO GPIO driver. AT91 PIO controller manages up to 32 fully programmable input/output @@ -151,7 +152,7 @@ config AT91_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_AT91 help Say yes here to support the Atmel PIO4 driver. The PIO4 is new version of Atmel PIO controller, which manages @@ -194,11 +195,11 @@ config FXL6408_GPIO config HIKEY_GPIO bool "HI6220 GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && TARGET_HIKEY config INTEL_BROADWELL_GPIO bool "Intel Broadwell GPIO driver" - depends on DM + depends on DM_GPIO && X86 help This driver supports Broadwell U devices which have an expanded GPIO feature set. The difference is large enough to merit a separate @@ -207,7 +208,7 @@ config INTEL_BROADWELL_GPIO config INTEL_GPIO bool "Intel generic GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && X86 help Say yes here to select Intel generic GPIO driver. This controller supports recent chips (e.g. Apollo Lake). It permits basic GPIO @@ -216,13 +217,13 @@ config INTEL_GPIO config INTEL_ICH6_GPIO bool "Intel ICH6 compatible legacy GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && X86 help Say yes here to select Intel ICH6 compatible legacy GPIO driver. config IMX_RGPIO2P bool "i.MX7ULP RGPIO2P driver" - depends on DM + depends on DM && (ARCH_MX7ULP || ARCH_IMX8ULP || ARCH_IMX9) help This driver supports i.MX7ULP Rapid GPIO2P controller. @@ -244,12 +245,13 @@ config HSDK_CREG_GPIO config KIRKWOOD_GPIO bool "Kirkwood GPIO driver" + depends on ARCH_KIRKWOOD help This drdiver supports GPIOs on Kirkwood platforms config LPC32XX_GPIO bool "LPC32XX GPIO driver" - depends on DM + depends on DM && ARCH_LPC32XX help Support for the LPC32XX GPIO driver. @@ -296,7 +298,7 @@ config MSCC_SGPIO config MSM_GPIO bool "Qualcomm GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_SNAPDRAGON help Support GPIO controllers on Qualcomm Snapdragon family of SoCs. This controller have single bank (default name "soc"), every @@ -309,24 +311,26 @@ config MSM_GPIO config MXC_GPIO bool "Freescale/NXP MXC GPIO driver" + depends on MACH_IMX help Support GPIO controllers on various i.MX platforms config MXS_GPIO bool "Freescale/NXP MXS GPIO driver" + depends on ARCH_MX23 || ARCH_MX28 help Support GPIO controllers on i.MX23 and i.MX28 platforms config NPCM_GPIO bool "Nuvoton NPCM GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_NPCM help Support GPIO controllers on Nuvovon NPCM SoCs. NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins. config NPCM_SGPIO bool "Nuvoton NPCM SGPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_NPCM help Support Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver support. Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595) @@ -380,7 +384,7 @@ config RZA1_GPIO config ROCKCHIP_GPIO bool "Rockchip GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_ROCKCHIP help Support GPIO access on Rockchip SoCs. The GPIOs are arranged into a number of banks (different for each SoC type) each with 32 GPIOs. @@ -430,7 +434,7 @@ config XILINX_GPIO config TEGRA_GPIO bool "Tegra20..210 GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && ARCH_TEGRA help Support for the GPIO controller contained in NVIDIA Tegra20 through Tegra210. @@ -451,7 +455,7 @@ config GPIO_UNIPHIER config VYBRID_GPIO bool "Vybrid GPIO driver" - depends on DM + depends on DM && MACH_IMX help Say yes here to support Vybrid vf610 GPIOs. @@ -490,7 +494,7 @@ config STM32_GPIO config SIFIVE_GPIO bool "SiFive GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && RISCV help Device model driver for GPIO controller present in SiFive FU540 SoC. This driver enables GPIO interface on HiFive Unleashed A00 board. @@ -577,7 +581,7 @@ config PCA953X config MPC8XXX_GPIO bool "Freescale MPC8XXX GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) help This driver supports the built-in GPIO controller of MPC8XXX CPUs. Each GPIO bank is identified by its own entry in the device tree, @@ -618,7 +622,7 @@ config QE_GPIO config MPC8XX_GPIO bool "Freescale MPC8XX GPIO driver" - depends on DM_GPIO + depends on DM_GPIO && PPC help This driver supports parallel IO ports from MPC8XX CPUs. Each GPIO bank is identified by its own entry in the device tree. @@ -685,7 +689,7 @@ config SL28CPLD_GPIO config SLG7XL45106_I2C_GPO bool "slg7xl45106 i2c gpo expander" - depends on DM_GPIO + depends on DM_GPIO && ARCH_ZYNQMP help Support for slg7xl45106 i2c gpo expander. It is an i2c based 8-bit gpo expander, all gpo lines are controlled by writing diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index ee8eae1efd9..a02dbe900b8 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -7,6 +7,7 @@ * (C) 2012 NetModule AG, David Andrey, added KSZ9031 * (C) Copyright 2017 Adaptrum, Inc. * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc. + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include <dm.h> #include <env.h> @@ -110,6 +111,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, { struct udevice *dev = phydev->dev; struct phy_driver *drv = phydev->drv; + struct ofnode_phandle_args phandle; int val[4]; int i, changed = 0, offset, max; u16 regval = 0; @@ -126,8 +128,14 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, } if (!ofnode_valid(node)) { - /* No node found, look in the Ethernet node */ - node = dev_ofnode(dev); + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle)) { + /* No phy-handle found, look in the Ethernet node */ + node = dev_ofnode(dev); + } else { + /* phy-handle found */ + node = phandle.node; + } } for (i = 0; i < ofcfg->grpsz; i++) { diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index f695a3a41d2..1160c1d6cfa 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -29,45 +29,30 @@ #include "sh_eth.h" -#ifndef CFG_SH_ETHER_USE_PORT -# error "Please define CFG_SH_ETHER_USE_PORT" -#endif -#ifndef CFG_SH_ETHER_PHY_ADDR -# error "Please define CFG_SH_ETHER_PHY_ADDR" -#endif +static void flush_cache_wback(void *addr, unsigned long len) +{ + flush_dcache_range((unsigned long)addr, + (unsigned long)(addr + ALIGN(len, SH_ETHER_ALIGN_SIZE))); +} -#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ - !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#define flush_cache_wback(addr, len) \ - flush_dcache_range((unsigned long)addr, \ - (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE))) -#else -#define flush_cache_wback(...) -#endif +static void invalidate_cache(void *addr, unsigned long len) +{ + unsigned long line_size = SH_ETHER_ALIGN_SIZE; + unsigned long start, end; -#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) -#define invalidate_cache(addr, len) \ - { \ - unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ - unsigned long start, end; \ - \ - start = (unsigned long)addr; \ - end = start + len; \ - start &= ~(line_size - 1); \ - end = ((end + line_size - 1) & ~(line_size - 1)); \ - \ - invalidate_dcache_range(start, end); \ - } -#else -#define invalidate_cache(...) -#endif + start = (unsigned long)addr; + end = start + len; + start &= ~(line_size - 1); + end = (end + line_size - 1) & ~(line_size - 1); + + invalidate_dcache_range(start, end); +} #define TIMEOUT_CNT 1000 -static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) +static int sh_eth_send_common(struct sh_eth_info *port_info, void *packet, int len) { int ret = 0, timeout; - struct sh_eth_info *port_info = ð->port_info[eth->port]; if (!packet || len > 0xffff) { printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); @@ -121,10 +106,8 @@ err: return ret; } -static int sh_eth_recv_start(struct sh_eth_dev *eth) +static int sh_eth_recv_start(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - /* Check if the rx descriptor is ready */ invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (port_info->rx_desc_cur->rd0 & RD_RACT) @@ -137,11 +120,9 @@ static int sh_eth_recv_start(struct sh_eth_dev *eth) return port_info->rx_desc_cur->rd1 & 0xffff; } -static void sh_eth_recv_finish(struct sh_eth_dev *eth) +static void sh_eth_recv_finish(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); + invalidate_cache((void *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); /* Make current descriptor available again */ if (port_info->rx_desc_cur->rd0 & RD_RDLE) @@ -159,9 +140,8 @@ static void sh_eth_recv_finish(struct sh_eth_dev *eth) port_info->rx_desc_cur = port_info->rx_desc_base; } -static int sh_eth_reset(struct sh_eth_dev *eth) +static int sh_eth_reset(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; @@ -192,12 +172,11 @@ static int sh_eth_reset(struct sh_eth_dev *eth) #endif } -static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) +static int sh_eth_tx_desc_init(struct sh_eth_info *port_info) { - int i, ret = 0; u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct tx_desc_s *cur_tx_desc; + int i, ret = 0; /* * Allocate rx descriptors. They must be aligned to size of struct @@ -244,11 +223,10 @@ err: return ret; } -static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) +static int sh_eth_rx_desc_init(struct sh_eth_info *port_info) { int i, ret = 0; u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct rx_desc_s *cur_rx_desc; u8 *rx_buf; @@ -318,20 +296,16 @@ err: return ret; } -static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) +static void sh_eth_tx_desc_free(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - if (port_info->tx_desc_alloc) { free(port_info->tx_desc_alloc); port_info->tx_desc_alloc = NULL; } } -static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) +static void sh_eth_rx_desc_free(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - if (port_info->rx_desc_alloc) { free(port_info->rx_desc_alloc); port_info->rx_desc_alloc = NULL; @@ -343,21 +317,21 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) } } -static int sh_eth_desc_init(struct sh_eth_dev *eth) +static int sh_eth_desc_init(struct sh_eth_info *port_info) { int ret = 0; - ret = sh_eth_tx_desc_init(eth); + ret = sh_eth_tx_desc_init(port_info); if (ret) goto err_tx_init; - ret = sh_eth_rx_desc_init(eth); + ret = sh_eth_rx_desc_init(port_info); if (ret) goto err_rx_init; return ret; err_rx_init: - sh_eth_tx_desc_free(eth); + sh_eth_tx_desc_free(port_info); err_tx_init: return ret; @@ -375,9 +349,8 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, sh_eth_write(port_info, val, MALR); } -static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) +static void sh_eth_mac_regs_config(struct sh_eth_info *port_info, unsigned char *mac) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; unsigned long edmr; /* Configure e-dmac registers */ @@ -422,9 +395,8 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) #endif } -static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) +static int sh_eth_phy_regs_config(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct phy_device *phy = port_info->phydev; int ret = 0; u32 val = 0; @@ -470,10 +442,8 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) return ret; } -static void sh_eth_start(struct sh_eth_dev *eth) +static void sh_eth_start(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - /* * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit @@ -481,33 +451,30 @@ static void sh_eth_start(struct sh_eth_dev *eth) sh_eth_write(port_info, EDRRR_R, EDRRR); } -static void sh_eth_stop(struct sh_eth_dev *eth) +static void sh_eth_stop(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - sh_eth_write(port_info, ~EDRRR_R, EDRRR); } -static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac) +static int sh_eth_init_common(struct sh_eth_info *port_info, unsigned char *mac) { int ret = 0; - ret = sh_eth_reset(eth); + ret = sh_eth_reset(port_info); if (ret) return ret; - ret = sh_eth_desc_init(eth); + ret = sh_eth_desc_init(port_info); if (ret) return ret; - sh_eth_mac_regs_config(eth, mac); + sh_eth_mac_regs_config(port_info, mac); return 0; } -static int sh_eth_start_common(struct sh_eth_dev *eth) +static int sh_eth_start_common(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; int ret; ret = phy_startup(port_info->phydev); @@ -516,17 +483,17 @@ static int sh_eth_start_common(struct sh_eth_dev *eth) return ret; } - ret = sh_eth_phy_regs_config(eth); + ret = sh_eth_phy_regs_config(port_info); if (ret) return ret; - sh_eth_start(eth); + sh_eth_start(port_info); return 0; } struct sh_ether_priv { - struct sh_eth_dev shdev; + struct sh_eth_info port_info; struct mii_dev *bus; phys_addr_t iobase; @@ -536,20 +503,19 @@ struct sh_ether_priv { static int sh_ether_send(struct udevice *dev, void *packet, int len) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; - return sh_eth_send_common(eth, packet, len); + return sh_eth_send_common(port_info, packet, len); } static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2); int len; - len = sh_eth_recv_start(eth); + len = sh_eth_recv_start(port_info); if (len > 0) { invalidate_cache(packet, len); *packetp = packet; @@ -567,10 +533,9 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; - sh_eth_recv_finish(eth); + sh_eth_recv_finish(port_info); /* Restart the receiver if disabled */ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) @@ -582,8 +547,7 @@ static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) static int sh_ether_write_hwaddr(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; struct eth_pdata *pdata = dev_get_plat(dev); sh_eth_write_hwaddr(port_info, pdata->enetaddr); @@ -595,10 +559,9 @@ static int sh_eth_phy_config(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct sh_eth_dev *eth = &priv->shdev; - int ret = 0; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; struct phy_device *phydev; + int ret = 0; phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface); if (!phydev) @@ -614,40 +577,38 @@ static int sh_ether_start(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; int ret; - ret = sh_eth_init_common(eth, pdata->enetaddr); + ret = sh_eth_init_common(port_info, pdata->enetaddr); if (ret) return ret; - ret = sh_eth_start_common(eth); + ret = sh_eth_start_common(port_info); if (ret) goto err_start; return 0; err_start: - sh_eth_tx_desc_free(eth); - sh_eth_rx_desc_free(eth); + sh_eth_tx_desc_free(port_info); + sh_eth_rx_desc_free(port_info); return ret; } static void sh_ether_stop(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; phy_shutdown(port_info->phydev); - sh_eth_stop(&priv->shdev); + sh_eth_stop(port_info); } /******* for bb_miiphy *******/ static int sh_eth_bb_mdio_active(struct mii_dev *miidev) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); @@ -656,8 +617,7 @@ static int sh_eth_bb_mdio_active(struct mii_dev *miidev) static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); @@ -666,8 +626,7 @@ static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev) static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; if (v) sh_eth_write(port_info, @@ -681,8 +640,7 @@ static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v) static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; @@ -691,8 +649,7 @@ static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v) static int sh_eth_bb_set_mdc(struct mii_dev *miidev, int v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; if (v) sh_eth_write(port_info, @@ -738,7 +695,7 @@ static int sh_ether_probe(struct udevice *udev) { struct eth_pdata *pdata = dev_get_plat(udev); struct sh_ether_priv *priv = dev_get_priv(udev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; struct mii_dev *mdiodev; int ret; @@ -757,7 +714,7 @@ static int sh_ether_probe(struct udevice *udev) mdiodev->read = sh_eth_bb_miiphy_read; mdiodev->write = sh_eth_bb_miiphy_write; - mdiodev->priv = eth; + mdiodev->priv = port_info; snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name); ret = mdio_register(mdiodev); @@ -766,10 +723,7 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = mdiodev; - eth->port = CFG_SH_ETHER_USE_PORT; - eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; - eth->port_info[eth->port].iobase = - (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); + port_info->iobase = (void __iomem *)(uintptr_t)BASE_IO_ADDR; #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&priv->clk); @@ -777,7 +731,7 @@ static int sh_ether_probe(struct udevice *udev) goto err_mdio_register; #endif - ret = sh_eth_init_common(eth, pdata->enetaddr); + ret = sh_eth_init_common(port_info, pdata->enetaddr); if (ret) goto err_phy_config; @@ -801,8 +755,7 @@ err_mdio_register: static int sh_ether_remove(struct udevice *udev) { struct sh_ether_priv *priv = dev_get_priv(udev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; #if CONFIG_IS_ENABLED(CLK) clk_disable(&priv->clk); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index ecf4a697e27..c395e6e8fc7 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -19,23 +19,17 @@ /* The ethernet controller needs to use physical addresses */ #define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000) +#define SH_ETHER_ALIGN_SIZE 16 #elif defined(CONFIG_ARM) #ifndef inl #define inl readl #define outl writel +#define SH_ETHER_ALIGN_SIZE 64 #endif #define ADDR_TO_PHY(addr) ((uintptr_t)(addr)) #define ADDR_TO_P2(addr) (addr) #endif /* defined(CONFIG_SH) */ -/* base padding size is 16 */ -#ifndef CFG_SH_ETHER_ALIGNE_SIZE -#define CFG_SH_ETHER_ALIGNE_SIZE 16 -#endif - -/* Number of supported ports */ -#define MAX_PORT_NUM 2 - /* Buffers must be big enough to hold the largest ethernet frame. Also, rx buffers must be a multiple of 32 bytes */ #define MAX_BUF_SIZE (48 * 32) @@ -47,7 +41,7 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) +#define TX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { @@ -62,9 +56,9 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) +#define RX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12) /* aligned cache line size */ -#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) +#define RX_BUF_ALIGNE_SIZE (SH_ETHER_ALIGN_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { @@ -84,17 +78,11 @@ struct sh_eth_info { u8 *rx_buf_alloc; u8 *rx_buf_base; u8 mac_addr[6]; - u8 phy_addr; struct eth_device *dev; struct phy_device *phydev; void __iomem *iobase; }; -struct sh_eth_dev { - int port; - struct sh_eth_info port_info[MAX_PORT_NUM]; -}; - /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ enum { /* E-DMAC registers */ @@ -388,11 +376,11 @@ enum DMAC_M_BIT { #endif }; -#if CFG_SH_ETHER_ALIGNE_SIZE == 64 +#if SH_ETHER_ALIGN_SIZE == 64 # define EMDR_DESC EDMR_DL1 -#elif CFG_SH_ETHER_ALIGNE_SIZE == 32 +#elif SH_ETHER_ALIGN_SIZE == 32 # define EMDR_DESC EDMR_DL0 -#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +#elif SH_ETHER_ALIGN_SIZE == 16 /* Default */ # define EMDR_DESC 0 #endif diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c index 2639f960631..d8df3c9afb0 100644 --- a/drivers/net/ti/icssg_prueth.c +++ b/drivers/net/ti/icssg_prueth.c @@ -63,6 +63,7 @@ /* Number of PRU Cores per Slice */ #define ICSSG_NUM_PRU_CORES 3 +#define ICSSG_NUM_FIRMWARES 6 static int icssg_gmii_select(struct prueth_priv *priv) { @@ -192,25 +193,6 @@ static int icssg_update_link(struct prueth_priv *priv) return phy->link; } -struct icssg_firmwares { - char *pru; - char *rtu; - char *txpru; -}; - -static struct icssg_firmwares icssg_emac_firmwares[] = { - { - .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru0-prueth-fw.elf", - .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", - .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", - }, - { - .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru1-prueth-fw.elf", - .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", - .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", - } -}; - static int icssg_start_pru_cores(struct udevice *dev) { struct prueth_priv *priv = dev_get_priv(dev); @@ -223,7 +205,7 @@ static int icssg_start_pru_cores(struct udevice *dev) slice = priv->port_id; index = slice * ICSSG_NUM_PRU_CORES; - firmwares = icssg_emac_firmwares; + firmwares = prueth->firmwares; ofnode_read_u32_index(dev_ofnode(prueth->dev), "ti,prus", index, &phandle); ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); @@ -476,6 +458,24 @@ static const struct eth_ops prueth_ops = { .stop = prueth_stop, }; +static char *prepend_fw_path(const char *fw_name) +{ + static const char fw_dir[] = "/lib/firmware/"; + char *result; + int len; + + if (!fw_name) + return NULL; + + len = strlen(fw_dir) + strlen(fw_name) + 1; + result = malloc(len); + if (!result) + return NULL; + + sprintf(result, "%s%s", fw_dir, fw_name); + return result; +} + static int icssg_ofdata_parse_phy(struct udevice *dev) { struct prueth_priv *priv = dev_get_priv(dev); @@ -534,6 +534,8 @@ static int prueth_probe(struct udevice *dev) struct udevice **prussdev = NULL; ofnode eth_ports_node, eth_node; struct udevice *port_dev; + const char **fw_names; + int fw_count, i; int ret = 0; prueth->dev = dev; @@ -659,6 +661,18 @@ static int prueth_probe(struct udevice *dev) } } + /* Parse firmware-name property from DT */ + fw_count = dev_read_string_list(dev, "firmware-name", &fw_names); + if (fw_count != ICSSG_NUM_FIRMWARES) { + dev_err(dev, "Expected %d firmware names, got %d\n", ICSSG_NUM_FIRMWARES, fw_count); + return -EINVAL; + } + for (i = 0; i < 2; i++) { + prueth->firmwares[i].pru = prepend_fw_path(fw_names[i * 3 + 0]); + prueth->firmwares[i].rtu = prepend_fw_path(fw_names[i * 3 + 1]); + prueth->firmwares[i].txpru = prepend_fw_path(fw_names[i * 3 + 2]); + } + return 0; out: clk_disable(&prueth->mdiofck); diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h index c69cfd4f162..d88b6fa88e7 100644 --- a/drivers/net/ti/icssg_prueth.h +++ b/drivers/net/ti/icssg_prueth.h @@ -38,6 +38,12 @@ enum prueth_port { PRUETH_PORT_MII1, /* physical port MII 1 */ }; +struct icssg_firmwares { + char *pru; + char *rtu; + char *txpru; +}; + struct prueth { struct udevice *dev; struct udevice *pruss; @@ -66,6 +72,7 @@ struct prueth { u8 rtu_core_id; u8 txpru_core_id; u8 icssg_hwcmdseq; + struct icssg_firmwares firmwares[PRUETH_NUM_MACS]; }; struct prueth_priv { diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 7c58ceb78f5..2b14437f69c 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -912,8 +912,10 @@ int nvme_init(struct udevice *udev) goto free_id; ret = bootdev_setup_for_sibling_blk(ns_udev, "nvme_bootdev"); - if (ret) - return log_msg_ret("bootdev", ret); + if (ret) { + log_err("bootdev: returning err=%d\n", ret); + goto free_id; + } ret = blk_probe_or_unbind(ns_udev); if (ret) diff --git a/include/configs/alt.h b/include/configs/alt.h index 8f03762583e..4c5d2de2bdf 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -20,16 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" diff --git a/include/configs/blanche.h b/include/configs/blanche.h index d4e0f677e67..46521aa16bf 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -29,8 +29,4 @@ #define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif -/* Board Clock */ - -/* ENV setting */ - #endif /* __BLANCHE_H */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 50c8d173383..b340800cc11 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -11,17 +11,4 @@ #include "rcar-gen3-common.h" -/* Environment compatibility */ - -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - #endif /* __CONDOR_H */ diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index ad5944230a6..707e7c28d55 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -9,8 +9,6 @@ #ifndef __EBISU_H #define __EBISU_H -#undef DEBUG - #include "rcar-gen3-common.h" /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 0b62ff9fbe1..e1cace73550 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,7 +11,4 @@ #include "rcar-gen4-common.h" -/* Board Clock */ -/* XTAL_CLK : 16.66MHz */ - #endif /* __FALCON_H */ diff --git a/include/configs/genmai.h b/include/configs/genmai.h new file mode 100644 index 00000000000..1d43f8e06af --- /dev/null +++ b/include/configs/genmai.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Renesas GENMAI board + * + * Copyright (C) 2017-2019 Renesas Electronics + */ + +#ifndef __GENMAI_H +#define __GENMAI_H + +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) + +#endif /* __GENAMI_H */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 7ae0726518d..4a5954af76f 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -19,16 +19,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 8de4a36e931..e4564b67a79 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -8,20 +8,8 @@ #ifndef __GRPEACH_H #define __GRPEACH_H -/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ - -/* Miscellaneous */ - /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) -/* Network interface */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index d47d70178cc..c2713b77e0a 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -19,19 +19,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __KOELSCH_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 2577c7a7da6..13f327fabf2 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -20,19 +20,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __LAGER_H */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 2cb430be8b0..4612845db19 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -21,19 +21,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __PORTER_H */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 7bed32d8553..09ef2a848bd 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -21,19 +21,7 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __SILK_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h index 1278ba63f4f..f98ebb324f3 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -25,19 +25,7 @@ /* SCIF */ #define CFG_SCIF_A -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __STOUT_H */ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index 58c2e88c0b7..3298e627e53 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -12,17 +12,4 @@ #include "rcar-gen3-common.h" -/* Environment compatibility */ - -/* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 -#define CFG_SH_ETHER_PHY_ADDR 0x0 -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - #endif /* __V3HSK_H */ diff --git a/test/Kconfig b/test/Kconfig index 31016eedbf8..77e7cad3984 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -122,6 +122,7 @@ endif # UNIT_TEST config POST bool "Power On Self Test support" + depends on ARM || PPC help See doc/README.POST for more details diff --git a/tools/binman/etype/renesas_rcar4_sa0.py b/tools/binman/etype/renesas_rcar4_sa0.py new file mode 100644 index 00000000000..3a7c0988fdc --- /dev/null +++ b/tools/binman/etype/renesas_rcar4_sa0.py @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> +# +# Entry-type module for generating the Renesas R-Car Gen4 SA0 header. +# + +import os +import struct + +from binman.etype.section import Entry_section +from dtoc import fdt_util +from u_boot_pylib import tools + +RCAR_GEN4_SF_HEADER_SIZE = 0x40000 +RCAR_GEN4_SF_MAX_LOAD_SIZE = 0xec000 + +class Entry_renesas_rcar4_sa0(Entry_section): + """Renesas R-Car Gen4 SA0 generator""" + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.required_props = ['renesas,loader-address'] + + def ReadNode(self): + self.loader_address = fdt_util.GetInt(self._node, 'renesas,loader-address') + super().ReadNode() + + def BuildSectionData(self, required): + data = super().BuildSectionData(required)[RCAR_GEN4_SF_HEADER_SIZE:] + + # Offset 0x0000 / Value 0x00000000 + header = struct.pack('<I', 0) + header += tools.get_bytes(0xff, 0x3008) + # Offset 0x300c / Value 0x00000000 + header += struct.pack('<I', 0) + header += tools.get_bytes(0xff, 0x144) + # Offset 0x3154 / Value (payload load address) + header += struct.pack('<I', self.loader_address) + header += tools.get_bytes(0xff, 0x10c) + # Offset 0x3264 / Value (payload size in 4-byte words, aligned to 4k) + header += struct.pack('<I', int(tools.align(len(data), 0x1000) / 4)) + header += tools.get_bytes(0xff, 0x3cd98) + if len(data) > RCAR_GEN4_SF_MAX_LOAD_SIZE: + self.Raise(f'SRAM data longer than {RCAR_GEN4_SF_MAX_LOAD_SIZE} Bytes') + + return header + data diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 8225216fbec..a90db3c9351 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -5586,6 +5586,17 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFile('347_bl1.dts') self.assertEqual(ATF_BL1_DATA, data[:len(ATF_BL1_DATA)]) + def testRenesasRCarGen4SA0Image(self): + """Test that binman can produce an Renesas R-Car Gen4 SA0 image""" + self._DoTestFile('348_renesas_rcar4_sa0.dts') + + def testRenesasRCarGen4SA0ImageSize(self): + """Test that binman can not produce large Renesas R-Car Gen4 SA0 image""" + with self.assertRaises(ValueError) as exc: + self._DoTestFile('349_renesas_rcar4_sa0_size.dts') + self.assertIn("Node '/binman/renesas-rcar4-sa0': SRAM data longer than 966656 Bytes", + str(exc.exception)) + def testFitFdtOper(self): """Check handling of a specified FIT operation""" entry_args = { diff --git a/tools/binman/test/348_renesas_rcar4_sa0.dts b/tools/binman/test/348_renesas_rcar4_sa0.dts new file mode 100644 index 00000000000..4a8717520f2 --- /dev/null +++ b/tools/binman/test/348_renesas_rcar4_sa0.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + renesas-rcar4-sa0 { + filename = "sa0.bin"; + renesas,loader-address = <0x10>; + }; + }; +}; diff --git a/tools/binman/test/349_renesas_rcar4_sa0_size.dts b/tools/binman/test/349_renesas_rcar4_sa0_size.dts new file mode 100644 index 00000000000..eaf4507260b --- /dev/null +++ b/tools/binman/test/349_renesas_rcar4_sa0_size.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + renesas-rcar4-sa0 { + filename = "sa0.bin"; + renesas,loader-address = <0x10>; + + fill { /* Oversize fill to cover size check */ + size = <0x140000>; + fill-byte = [ff]; + }; + }; + }; +}; |