diff options
736 files changed, 13476 insertions, 5801 deletions
@@ -31,6 +31,8 @@ Jagan Teki <jagannadh.teki@gmail.com> Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> Markus Klotzbuecher <mk@denx.de> +Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> +Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> Prabhakar Kushwaha <prabhakar@freescale.com> Rajeshwari Shinde <rajeshwari.s@samsung.com> diff --git a/MAINTAINERS b/MAINTAINERS index 874cf2c0e57..127e30c0a5e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -385,7 +385,7 @@ F: drivers/smem/msm_smem.c F: drivers/usb/host/ehci-msm.c ARM STI -M: Patrice Chotard <patrice.chotard@st.com> +M: Patrice Chotard <patrice.chotard@foss.st.com> S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git F: arch/arm/mach-sti/ @@ -411,8 +411,8 @@ F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ ARM STM STM32MP -M: Patrick Delaunay <patrick.delaunay@st.com> -M: Patrice Chotard <patrice.chotard@st.com> +M: Patrick Delaunay <patrick.delaunay@foss.st.com> +M: Patrice Chotard <patrice.chotard@foss.st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained @@ -758,6 +758,7 @@ T: git https://gitlab.denx.de/u-boot/u-boot.git F: common/log* F: cmd/log.c F: doc/develop/logging.rst +F: include/log.h F: lib/getopt.c F: test/log/ F: test/py/tests/test_log.py @@ -3,7 +3,7 @@ VERSION = 2021 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -3832,16 +3832,8 @@ when your kernel is intended to use an initial ramdisk: Load Address: 0x00000000 Entry Point: 0x00000000 -The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i" -option performs the converse operation of the mkimage's second form (the "-d" -option). Given an image built by mkimage, the dumpimage extracts a "data file" -from the image: - - tools/dumpimage -i image -T type -p position data_file - -i ==> extract from the 'image' a specific 'data_file' - -T ==> set image type to 'type' - -p ==> 'position' (starting at 0) of the 'data_file' inside the 'image' - +The "dumpimage" tool can be used to disassemble or list the contents of images +built by mkimage. See dumpimage's help output (-h) for details. Installing a Linux Image: ------------------------- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b2f7fcbd6ec..fbe90875ae4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS is a high-performance development platform that supports the QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. +config TARGET_LX2162AQDS + bool "Support lx2162aqds" + select ARCH_LX2162A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT + help + Support for NXP LX2162AQDS platform. + The lx2162aqds support is based on LX2160A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 @@ -1721,7 +1733,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK - select BINMAN if !ARM64 + select BINMAN if SPL_OPTEE select DM select DM_GPIO select DM_I2C diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 937989b2786..747059b56a5 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,11 +5,11 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 - select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 - select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A008997 if USB + select SYS_FSL_ERRATUM_A009007 if USB + select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009663 - select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A009798 if USB select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3655990772c..f2474413cca 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -115,7 +115,7 @@ config PSCI_RESET !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ - !TARGET_LX2160AQDS && \ + !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index be51b7d8566..4d465872140 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -208,6 +208,35 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config ARCH_LX2160A bool select ARMV8_SET_SMPEN @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar - to erratum A-009007, but this one is for LX2160A, + to erratum A-009007, but this one is for LX2160A and LX2162A, and the register value is different. config SYS_FSL_ERRATUM_A010315 @@ -362,6 +391,7 @@ config MAX_CPUS default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A default 16 if ARCH_LX2160A + default 16 if ARCH_LX2162A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A default 4 if ARCH_LX2160A + default 4 if ARCH_LX2162A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -560,14 +593,14 @@ config SYS_FSL_EC1 bool help Ethernet controller 1, this is connected to - MAC17 for LX2160A or to MAC3 for other SoCs + MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help Ethernet controller 2, this is connected to - MAC18 for LX2160A or to MAC4 for other SoCs + MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 9ecb372b4e6..598c36ee660 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o obj-y += icid.o lx2160_ids.o endif +ifneq ($(CONFIG_ARCH_LX2162A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o obj-y += icid.o ls2088_ids.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 596b88d3e29..1a5d26b5372 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), + CPU_TYPE_ENTRY(LX2162A, LX2162A, 16), + CPU_TYPE_ENTRY(LX2122A, LX2122A, 12), + CPU_TYPE_ENTRY(LX2082A, LX2082A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -403,7 +406,7 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (IS_C_PROCESSOR(svr)) strcat(name, "C"); #endif @@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; void __efi_runtime reset_cpu(ulong addr) { -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* clear the RST_REQ_MSK and SW_RST_REQ */ out_le32(rstcr, 0x0); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index ad55573c85e..f33d05d0539 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -9,6 +9,7 @@ SoC overview 7. LS2081A 8. LX2160A 9. LS1028A + 10. LX2162A LS1043A --------- @@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features: - Layerscape Trust Architecture - Service Processor (SP) provides pre-boot initialization and secure-boot capabilities + +LX2162A +-------- +The QorIQ LX2162A processor is built on the Layerscape architecture +combining sixteen ARM A72 processor cores with advanced, high-performance +datapath acceleration and network, peripheral interfaces required for +networking, wireless infrastructure, storage, and general-purpose embedded +applications. + +LX2162A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2162A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508) + One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 12 Serdes lanes at up to 25 GHz + Ethernet interfaces + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + One PCIe Gen 3.0 8-lane controllers supporting SR-IOV, + Two PCIe Gen 3.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + One USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2162A SoC has 2 more similar SoC personalities +1)LX2122A, few difference w.r.t. LX2162A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2082A, few difference w.r.t. LX2162A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 6d3391db3b3..3a04dce56fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -400,10 +400,12 @@ void fdt_fixup_remove_jr(void *blob) while (jr_node != -FDT_ERR_NOTFOUND) { reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len); - jr_offset = fdt_read_number(reg, addr_cells); - if (jr_offset == used_jr) { - fdt_del_node(blob, jr_node); - break; + if (reg) { + jr_offset = fdt_read_number(reg, addr_cells); + if (jr_offset == used_jr) { + fdt_del_node(blob, jr_node); + break; + } } jr_node = fdt_node_offset_by_compatible(blob, jr_node, "fsl,sec-v4.0-job-ring"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index aa6fd6b28ce..fad7a935662 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2016-2018 NXP + * Copyright 2016-2018, 2020 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) int xfi_dpmac[XFI14 + 1]; int sgmii_dpmac[SGMII18 + 1]; int a25gaui_dpmac[_25GE10 + 1]; @@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], (int)lane_prtcl); @@ -552,7 +552,7 @@ void fsl_serdes_init(void) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int i , j; -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) for (i = XFI1, j = 1; i <= XFI14; i++, j++) xfi_dpmac[i] = j; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 7f8178f72eb..bf153c720e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015, Freescale Semiconductor, Inc. - * Copyright 2019 NXP Semiconductors + * Copyright 2019-2020 NXP * * Derived from arch/power/cpu/mpc85xx/speed.c */ @@ -180,7 +180,7 @@ int get_clocks(void) #ifdef CONFIG_FSL_ESDHC #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) clock = sys_info.freq_cga_m2; -#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A) clock = sys_info.freq_systembus; #endif gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c index a04a370268b..5941d90e036 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP */ #include <common.h> @@ -11,6 +11,22 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; +#if defined(CONFIG_ARCH_LX2162A) +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } }, + {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {_25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } }, + {} +}; +#else static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, @@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, {} }; +#endif static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 96b2775f3f9..7553b5bce2e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #include <common.h> @@ -33,13 +33,10 @@ #include <fsl_validate.h> #endif #include <fsl_immap.h> -#ifdef CONFIG_TFABOOT -#include <env_internal.h> -#endif #include <dm.h> #include <dm/device_compat.h> #include <linux/err.h> -#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS) +#ifdef CONFIG_GIC_V3_ITS DECLARE_GLOBAL_DATA_PTR; #endif @@ -186,7 +183,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ - defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) + defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -222,7 +220,7 @@ static void erratum_a009007(void) #if defined(CONFIG_FSL_LSCH3) static void erratum_a050106(void) { -#if defined(CONFIG_ARCH_LX2160A) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); @@ -392,7 +390,8 @@ void fsl_lsch3_early_init_f(void) #endif #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ - defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) set_icids(); #endif } @@ -954,28 +953,12 @@ int board_late_init(void) #endif #ifdef CONFIG_TFABOOT /* - * check if gd->env_addr is default_environment; then setenv bootcmd - * and mcinitcmd. - */ -#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR - if (gd->env_addr == (ulong)&default_environment[0]) { -#else - if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { -#endif - fsl_setenv_bootcmd(); - fsl_setenv_mcinitcmd(); - } - - /* - * If the boot mode is secure, default environment is not present then - * setenv command needs to be run by default + * Set bootcmd and mcinitcmd if they don't exist in the environment. */ -#ifdef CONFIG_CHAIN_OF_TRUST - if ((fsl_check_boot_mode_secure() == 1)) { + if (!env_get("bootcmd")) fsl_setenv_bootcmd(); + if (!env_get("mcinitcmd")) fsl_setenv_mcinitcmd(); - } -#endif #endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5308713df7d..fd47e408f82 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -204,7 +204,6 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ armada-3720-espressobin.dtb \ - armada-3720-espressobin-emmc.dtb \ armada-3720-turris-mox.dtb \ armada-3720-uDPU.dtb \ armada-375-db.dtb \ @@ -350,7 +349,8 @@ dtb-$(CONFIG_AM33XX) += \ am335x-sl50.dtb \ am335x-base0033.dtb \ am335x-guardian.dtb \ - am335x-wega-rdk.dtb + am335x-wega-rdk.dtb \ + am335x-regor-rdk.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ @@ -414,7 +414,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-lx2160a-qds-19-x-x.dtb \ fsl-lx2160a-qds-19-11-x.dtb \ fsl-lx2160a-qds-20-x-x.dtb \ - fsl-lx2160a-qds-20-11-x.dtb + fsl-lx2160a-qds-20-11-x.dtb \ + fsl-lx2162a-qds.dtb\ + fsl-lx2162a-qds-17-x.dtb\ + fsl-lx2162a-qds-18-x.dtb\ + fsl-lx2162a-qds-20-x.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ @@ -616,6 +620,10 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb \ sun50i-a64-pinebook.dtb \ + sun50i-a64-pinephone-1.0.dtb \ + sun50i-a64-pinephone-1.1.dtb \ + sun50i-a64-pinephone-1.2.dtb \ + sun50i-a64-pinetab.dtb \ sun50i-a64-sopine-baseboard.dtb \ sun50i-a64-teres-i.dtb dtb-$(CONFIG_MACH_SUN9I) += \ @@ -638,14 +646,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ - imx6dl-aristainetos2_4.dtb \ - imx6dl-aristainetos2_7.dtb \ - imx6dl-aristainetos2b_4.dtb \ - imx6dl-aristainetos2b_7.dtb \ - imx6dl-aristainetos2b_csl_4.dtb \ - imx6dl-aristainetos2b_csl_7.dtb \ - imx6dl-aristainetos2c_4.dtb \ imx6dl-aristainetos2c_7.dtb \ + imx6dl-aristainetos2c_cslb_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ @@ -763,6 +765,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ + fsl-imx8qxp-apalis.dtb \ fsl-imx8qxp-mek.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb @@ -960,6 +963,7 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-odyssey.dtb \ stm32mp15xx-dhcom-drc02.dtb \ stm32mp15xx-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-picoitx.dtb \ stm32mp15xx-dhcor-avenger96.dtb dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi new file mode 100644 index 00000000000..1ddd7158750 --- /dev/null +++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + */ + +/ { + chosen { + #address-cells = <1>; + #size-cells = <1>; + + bootargs = "console=ttyO0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + ocp { + u-boot,dm-pre-reloc; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&mmc1 { + u-boot,dm-pre-reloc; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/am335x-regor-rdk.dts b/arch/arm/dts/am335x-regor-rdk.dts new file mode 100644 index 00000000000..66a1360b83d --- /dev/null +++ b/arch/arm/dts/am335x-regor-rdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-regor.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&serial_flash { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi new file mode 100644 index 00000000000..86b3f074297 --- /dev/null +++ b/arch/arm/dts/am335x-regor.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + */ + +/ { + model = "Phytec AM335x phyBOARD-REGOR"; + compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; + + vcc3v3: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* User IO */ + user_leds: user_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + run_stop-led { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + error-led { + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + }; +}; + +/* User Leds */ +&am33xx_pinmux { + user_leds_pins: pinmux_user_leds { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2_22 */ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ + >; + }; +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux_ethernet1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_emac1 { + phy-handle = <&phy1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac { + slaves = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; + dual_emac = <1>; +}; + +/* GPIOs */ +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&user_gpios_pins>; + + user_gpios_pins: pinmux_user_gpios { + pinctrl-single,pins = < + /* DIGIN 1-4 */ + AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7) /* gpmc_ad11.gpio0_27 */ + AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7) /* gpmc_ad8.gpio0_22 */ + /* DIGOUT 1-4 */ + AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad15.gpio1_15 */ + AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad14.gpio1_14 */ + AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad13.gpio1_13 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + >; + }; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* RTC */ +&i2c_rtc { + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + uart2_pins: pinmux_uart2 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +/* RS485 - UART1 */ +&am33xx_pinmux { + uart1_rs485_pins: pinmux_uart1_rs485_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rs485_pins>; + status = "okay"; + linux,rs485-enabled-at-boot-time; +}; diff --git a/arch/arm/dts/armada-3720-espressobin-emmc.dts b/arch/arm/dts/armada-3720-espressobin-emmc.dts deleted file mode 100644 index 29ccb6a573e..00000000000 --- a/arch/arm/dts/armada-3720-espressobin-emmc.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier <romain.perier@free-electrons.com> - * Konstantin Porotchkin <kostap@marvell.com> - * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; - compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -/* U11 */ -&sdhci1 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 1542d836c09..96a4b3d95b8 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -1,20 +1,192 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board + * Device Tree file for Marvell Armada 3720 community board + * (ESPRESSOBin) * Copyright (C) 2016 Marvell * - * Romain Perier <romain.perier@free-electrons.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Konstantin Porotchkin <kostap@marvell.com> * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -#include "armada-3720-espressobin.dtsi" +#include "armada-372x.dtsi" / { model = "Globalscale Marvell ESPRESSOBin Board"; compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð0; + i2c0 = &i2c0; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + vcc_sd_reg0: regulator@0 { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-type = "voltage"; + states = <1800000 0x1 + 3300000 0x0>; + gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&comphy { + max-lanes = <3>; + phy0 { + phy-type = <PHY_TYPE_USB3_HOST0>; + phy-speed = <PHY_SPEED_5G>; + }; + + phy1 { + phy-type = <PHY_TYPE_PEX0>; + phy-speed = <PHY_SPEED_2_5G>; + }; + + phy2 { + phy-type = <PHY_TYPE_SATA0>; + phy-speed = <PHY_SPEED_5G>; + }; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&smi_pins>; + phy-mode = "rgmii"; + phy_addr = <0x1>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +/* CON3 */ +&sata { + status = "okay"; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vcc_sd_reg0>; + status = "okay"; +}; + +/* U11 */ +&sdhci1 { + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +/* Exported on the micro USB connector CON32 through an FTDI */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +/* CON29 */ +&usb2 { + status = "okay"; +}; + +/* CON31 */ +&usb3 { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + status = "okay"; }; diff --git a/arch/arm/dts/armada-3720-espressobin.dtsi b/arch/arm/dts/armada-3720-espressobin.dtsi deleted file mode 100644 index 05dec89834c..00000000000 --- a/arch/arm/dts/armada-3720-espressobin.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Device Tree file for Marvell Armada 3720 community board - * (ESPRESSOBin) - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * Konstantin Porotchkin <kostap@marvell.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "armada-372x.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = ð0; - i2c0 = &i2c0; - spi0 = &spi0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - vcc_sd_reg0: regulator@0 { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-type = "voltage"; - states = <1800000 0x1 - 3300000 0x0>; - gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; - }; -}; - -&comphy { - max-lanes = <3>; - phy0 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; - }; - - phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; - }; - - phy2 { - phy-type = <PHY_TYPE_SATA0>; - phy-speed = <PHY_SPEED_5G>; - }; -}; - -ð0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&smi_pins>; - phy-mode = "rgmii"; - phy_addr = <0x1>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -/* CON3 */ -&sata { - status = "okay"; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - bus-width = <4>; - cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vcc_sd_reg0>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; -}; - -/* Exported on the micro USB connector CON32 through an FTDI */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* CON29 */ -&usb2 { - status = "okay"; -}; - -/* CON31 */ -&usb3 { - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/dts/armv7-m.dtsi b/arch/arm/dts/armv7-m.dtsi index 31349da75aa..26f5443d85e 100644 --- a/arch/arm/dts/armv7-m.dtsi +++ b/arch/arm/dts/armv7-m.dtsi @@ -1,5 +1,4 @@ -#include "skeleton.dtsi" - +// SPDX-License-Identifier: GPL-2.0 / { nvic: interrupt-controller@e000e100 { compatible = "arm,armv7m-nvic"; @@ -22,4 +21,3 @@ ranges; }; }; - diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi index e5eae8bafc4..10e9186a76b 100644 --- a/arch/arm/dts/axp803.dtsi +++ b/arch/arm/dts/axp803.dtsi @@ -1,44 +1,5 @@ -/* - * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz> /* * AXP803 Integrated Power Management Chip @@ -49,6 +10,39 @@ interrupt-controller; #interrupt-cells = <1>; + ac_power_supply: ac-power-supply { + compatible = "x-powers,axp803-ac-power-supply", + "x-powers,axp813-ac-power-supply"; + status = "disabled"; + }; + + axp_adc: adc { + compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0_ldo: gpio0-ldo { + pins = "GPIO0"; + function = "ldo"; + }; + + gpio1_ldo: gpio1-ldo { + pins = "GPIO1"; + function = "ldo"; + }; + }; + + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp803-battery-power-supply", + "x-powers,axp813-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; @@ -152,4 +146,10 @@ status = "disabled"; }; }; + + usb_power_supply: usb-power-supply { + compatible = "x-powers,axp803-usb-power-supply", + "x-powers,axp813-usb-power-supply"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi new file mode 100644 index 00000000000..e41911a04aa --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&{/imx8qx-pm} { + + u-boot,dm-pre-proper; +}; + +&mu { + u-boot,dm-pre-proper; +}; + +&clk { + u-boot,dm-pre-proper; +}; + +&iomuxc { + u-boot,dm-pre-proper; +}; + +&pd_lsio { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio0 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio1 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio2 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio3 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio4 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio5 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio6 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio7 { + u-boot,dm-pre-proper; +}; + +&pd_dma { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart0 { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart3 { + u-boot,dm-pre-proper; +}; + +&pd_conn { + u-boot,dm-pre-proper; +}; + +&pd_conn_sdch0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_sdch1 { + u-boot,dm-pre-proper; +}; + +&pd_conn_sdch2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_enet0 { + u-boot,dm-pre-proper; +}; + +&gpio0 { + u-boot,dm-pre-proper; +}; + +&gpio1 { + u-boot,dm-pre-proper; +}; + +&gpio2 { + u-boot,dm-pre-proper; +}; + +&gpio3 { + u-boot,dm-pre-proper; +}; + +&gpio4 { + u-boot,dm-pre-proper; +}; + +&gpio5 { + u-boot,dm-pre-proper; +}; + +&gpio6 { + u-boot,dm-pre-proper; +}; + +&gpio7 { + u-boot,dm-pre-proper; +}; + +&lpuart3 { + u-boot,dm-pre-proper; +}; + +&lpuart0 { + u-boot,dm-pre-proper; +}; + +&usdhc1 { + u-boot,dm-pre-proper; + /delete-property/ assigned-clock-parents; +}; + +&usdhc2 { + u-boot,dm-pre-proper; + /delete-property/ assigned-clock-parents; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts new file mode 100644 index 00000000000..6bd231b2834 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" +#include "fsl-imx8qxp-apalis-u-boot.dtsi" + +/ { + model = "Toradex Apalis iMX8X"; + compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP1,115200"; + stdout-path = &lpuart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>; + + apalis-imx8x { + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */ + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */ + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 + /* On-module ETH_RESET# */ + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020 + /* On-module ETH_INT# */ + SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 + >; + }; + + /* Apalis BKL_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + /* Apalis USBO1_EN */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */ + >; + }; + + /* Apalis RESET_MOCI# */ + pinctrl_reset_moci: gpioresetmocigrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_usdhc2_gpio: mmc1gpiogrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */ + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */ + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */ + SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + }; +}; + +/* Apalis Gigabit LAN */ +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + disable-wp; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 2d70c82a728..c401ba33ac5 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* + * Copyright 2020 NXP * Copyright 2016 Freescale Semiconductor */ @@ -116,7 +117,7 @@ status = "disabled"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x40000 /* lut registers */ diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index bf6373d5ec5..d0850237c79 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls1028a SOC common device tree source * - * Copyright 2019 NXP + * Copyright 2019-2020 NXP * */ @@ -91,7 +91,7 @@ status = "disabled"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 0x00 0x03480000 0x0 0x40000 /* lut registers */ @@ -107,7 +107,7 @@ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 0x00 0x03580000 0x0 0x40000 /* lut registers */ diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index f7db44c0fa5..8ca57ea7b96 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * Device Tree Include file for NXP Layerscape-1043A family SoC. * + * Copyright 2020 NXP * Copyright (C) 2014-2015, Freescale Semiconductor * * Mingkai Hu <Mingkai.hu@freescale.com> @@ -240,7 +241,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */ 0x00 0x03410000 0x0 0x10000 /* lut registers */ @@ -255,7 +256,7 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */ 0x00 0x03510000 0x0 0x10000 /* lut registers */ @@ -271,7 +272,7 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */ 0x00 0x03610000 0x0 0x10000 /* lut registers */ diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 3f11d6cd18d..155455d591e 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -241,7 +241,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x40000 /* lut registers */ @@ -257,7 +257,7 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie_ep@3400000 { + pcie_ep1: pcie_ep@3400000 { compatible = "fsl,ls-pcie-ep"; reg = <0x00 0x03400000 0x0 0x80000 0x00 0x034c0000 0x0 0x40000 @@ -268,7 +268,7 @@ big-endian; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x40000 /* lut registers */ @@ -285,7 +285,7 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie_ep@3500000 { + pcie_ep2: pcie_ep@3500000 { compatible = "fsl,ls-pcie-ep"; reg = <0x00 0x03500000 0x0 0x80000 0x00 0x035c0000 0x0 0x40000 @@ -296,7 +296,7 @@ big-endian; }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x40000 /* lut registers */ @@ -312,7 +312,7 @@ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie_ep@3600000 { + pcie_ep3: pcie_ep@3600000 { compatible = "fsl,ls-pcie-ep"; reg = <0x00 0x03600000 0x0 0x80000 0x00 0x036c0000 0x0 0x40000 diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 6653794d1c3..7b4ac6d3ded 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls1088a SOC common device tree source * - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ / { @@ -135,7 +135,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */ @@ -151,7 +151,7 @@ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */ @@ -167,7 +167,7 @@ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */ diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 6b7bf8eb169..f0f4a82c146 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a SOC common device tree source + * NXP ls2080a SOC common device tree source * + * Copyright 2020 NXP * Copyright 2013-2015 Freescale Semiconductor, Inc. */ @@ -133,7 +134,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */ @@ -148,7 +149,7 @@ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */ @@ -163,7 +164,7 @@ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */ @@ -178,7 +179,7 @@ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3700000 { + pcie4: pcie@3700000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ 0x00 0x03780000 0x0 0x80000 /* lut registers */ diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index e0f5d5e2d38..332c778d3a6 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -13,7 +13,4 @@ / { model = "NXP Layerscape LX2160AQDS Board"; compatible = "fsl,lx2160aqds", "fsl,lx2160a"; - aliases { - spi0 = &fspi; - }; }; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 96c980004bf..288607c0347 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -2,12 +2,18 @@ /* * NXP LX2160AQDS common device tree source * - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ #include "fsl-lx2160a.dtsi" +/ { + aliases { + spi0 = &fspi; + }; +}; + &dpmac17 { status = "okay"; phy-handle = <&rgmii_phy1>; @@ -251,6 +257,20 @@ }; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index bfdf1787387..a6f0e9bc56b 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -325,7 +325,7 @@ }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */ 0x00 0x03480000 0x0 0x40000 /* LUT registers */ @@ -340,7 +340,7 @@ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */ 0x00 0x03580000 0x0 0x40000 /* LUT registers */ @@ -356,7 +356,7 @@ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */ 0x00 0x03680000 0x0 0x40000 /* LUT registers */ @@ -371,7 +371,7 @@ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3700000 { + pcie4: pcie@3700000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */ 0x00 0x03780000 0x0 0x40000 /* LUT registers */ @@ -386,7 +386,7 @@ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3800000 { + pcie5: pcie@3800000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */ 0x00 0x03880000 0x0 0x40000 /* LUT registers */ @@ -401,7 +401,7 @@ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3900000 { + pcie6: pcie@3900000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */ 0x00 0x03980000 0x0 0x40000 /* LUT registers */ diff --git a/arch/arm/dts/fsl-lx2162a-qds-17-x.dts b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts new file mode 100644 index 00000000000..8a8895f0238 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 17.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-17.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 17.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-18-x.dts b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts new file mode 100644 index 00000000000..c28e5e24972 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 18.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-18.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 18.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-20-x.dts b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts new file mode 100644 index 00000000000..7882c767e29 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 20.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-20.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi new file mode 100644 index 00000000000..60f5a4ee435 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17 + * + * Some assumptions are made: + * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy2>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy3>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; + + inphi_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x2>; + }; + + inphi_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi new file mode 100644 index 00000000000..8e11b0680a9 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi new file mode 100644 index 00000000000..faf4285eaba --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20 + * + * Some assumptions are made: + * * Mezzanine card M8 is connected to IO SLOT1 + * (xlaui4 for DPMAC 1) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&cortina_phy1_0>; + phy-connection-type = "xlaui4"; +}; + +&emdio1_slot1 { + cortina_phy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts new file mode 100644 index 00000000000..b16526503d9 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds.dtsi" + +/ { + model = "NXP Layerscape LX2162AQDS Board"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + + aliases { + pcie@3500000 { + status = "disabled"; + }; + + pcie@3800000 { + status = "disabled"; + }; + + pcie@3900000 { + status = "disabled"; + }; + }; +}; + +&usb1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx53-ppd-uboot.dtsi b/arch/arm/dts/imx53-ppd-uboot.dtsi index d61b7cb8764..b293e27a03c 100644 --- a/arch/arm/dts/imx53-ppd-uboot.dtsi +++ b/arch/arm/dts/imx53-ppd-uboot.dtsi @@ -28,7 +28,7 @@ #size-cells = <1>; vpd@0 { - reg = <0 1022>; + reg = <0 800>; }; bootcount: bootcount@1022 { diff --git a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi deleted file mode 100644 index ac7052c7b76..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -#include <imx6qdl-aristainetos2-u-boot.dtsi> - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts deleted file mode 100644 index 0157e244ae4..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * parts for 4.3 inch LG display on spi1 port0 - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi deleted file mode 100644 index be4601b4b2b..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * parts for 4.3 inch LG display on the parallel port and atmel maxtouch - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; -#include "imx6dl.dtsi" - -/ { - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi deleted file mode 100644 index 25bc562064b..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -#include <imx6qdl-aristainetos2-u-boot.dtsi> -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts deleted file mode 100644 index 0d1e83cb686..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi index 52d6a517a7f..ec633b8ed1c 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0) /* * support for the imx6 based aristainetos2 board - * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch + * parts for 7 inch LG display connected to the LVDS port * * Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2015 Heiko Schocher <hs@denx.de> @@ -26,15 +26,6 @@ }; }; -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - &ldb { status = "okay"; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi deleted file mode 100644 index ee02df39c15..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -#include <imx6qdl-aristainetos2b-u-boot.dtsi> - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_4.dts deleted file mode 100644 index a48a25c1195..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2b.dtsi" - -/ { - model = "aristainetos2b i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi deleted file mode 100644 index 0cb4f1974b9..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -#include <imx6qdl-aristainetos2b-u-boot.dtsi> -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_7.dts deleted file mode 100644 index f1496cbfdd9..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2b.dtsi" - -/ { - model = "aristainetos2b i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi deleted file mode 100644 index 654ac122a16..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts deleted file mode 100644 index bfbb799f20c..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b csl board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2b_csl.dtsi" - -/ { - model = "aristainetos2b csl i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts deleted file mode 100644 index ecf767da6ce..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2b_csl.dtsi" - -/ { - model = "aristainetos2b csl i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi deleted file mode 100644 index 052d51852b9..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -#include <imx6qdl-aristainetos2c-u-boot.dtsi> - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts deleted file mode 100644 index 142b108acec..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2c_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2c board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2c.dtsi" - -/ { - model = "aristainetos2c i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts index 35435e1c104..e1f9e882915 100644 --- a/arch/arm/dts/imx6dl-aristainetos2c_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts @@ -11,6 +11,6 @@ #include "imx6qdl-aristainetos2c.dtsi" / { - model = "aristainetos2c i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; }; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi index 70d195ecbfe..b069debc1e3 100644 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2019 Heiko Schocher <hs@denx.de> */ -#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> +#include <imx6qdl-aristainetos2c_cslb-u-boot.dtsi> / { vdd_panel_reg: regulator-panel { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts new file mode 100644 index 00000000000..7f839ca5e20 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c cslb board + * + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> + * Copyright (C) 2015 Heiko Schocher <hs@denx.de> + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2c_cslb.dtsi" + +/ { + model = "aristainetos2c cslb i.MX6 Dual Lite Board 7"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi index 01321cab781..2de3b850ec8 100644 --- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi +++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi @@ -27,7 +27,7 @@ #size-cells = <1>; vpd@0 { - reg = <0 1022>; + reg = <0 800>; }; bootcount: bootcount { diff --git a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi index 2aa531b1ab7..570143694e8 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2 board + * support for the imx6 based aristainetos2 boards * parts common to all versions * * Copyright (C) 2019 Heiko Schocher <hs@denx.de> @@ -13,6 +13,8 @@ / { aliases { eeprom0 = &i2c_eeprom0; + eeprom1 = &i2c_eeprom1; + eeprom2 = &i2c_eeprom2; pmic0 = &i2c_pmic0; }; @@ -250,6 +252,12 @@ }; }; + i2c_eeprom2: eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + rtc@68 { compatible = "st,m41t11"; reg = <0x68>; @@ -274,6 +282,19 @@ }; }; +&gpio2 { + tpm_pp { + gpio-hog; + output-low; + gpios = <17 GPIO_ACTIVE_HIGH>; + }; + tpm_reset { + gpio-hog; + output-high; + gpios = <18 GPIO_ACTIVE_HIGH>; + }; +}; + &gpio6 { spi_bus_ena { gpio-hog; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi index c713efd84c7..3063f01d700 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -50,28 +50,6 @@ }; }; -&iomuxc { - pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>; - u-boot,dm-pre-reloc; - - pinctrl_gpio_fix: gpiofixgrp { - /* - * usdhc2 has a levelshifter on the carrier board Rev. DV1, - * that will automatically detect the driving direction. - * During initialisation this isn't working correctly, - * which causes DAT3 to be driven low towards the SD-card. - * This causes a SD-card enetring the SPI-Mode - * and therefore getting inaccessible until next power cycle. - * As workaround we drive the DAT3 line as GPIO and set it high. - * This makes usdhc2 unusable in u-boot, but works for the - * initialisation in Linux - */ - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000 - >; - }; -}; - &gpio1 { usdhc_fix { gpio-hog; diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 788e13edad0..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/imx6qdl-clock.h> - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 level shifter output enable */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi deleted file mode 100644 index 88826a2634c..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - */ - -/ { - chosen { - u-boot,dm-pre-reloc; - stdout-path = &uart2; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - }; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_gpio { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&iomuxc { - u-boot,dm-pre-reloc; -}; - -&aips2 { - u-boot,dm-pre-reloc; -}; - -&backlight { - pwms = <&pwm1 0 300000>; - default-brightness-level = <2>; -}; - -/* - * allow switching write protect / reset pin by gpio, - * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot - */ -&gpio2 { - u-boot,dm-pre-reloc; - - wp_spi_nor { - gpio-hog; - output-high; - gpios = <15 GPIO_ACTIVE_HIGH>; - }; - - reset_spi_nor { - gpio-hog; - output-high; - gpios = <28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio4 { - u-boot,dm-pre-reloc; -}; - -&ecspi1 { - u-boot,dm-pre-reloc; -}; - -&flash { - u-boot,dm-pre-reloc; -}; - -&pinctrl_ecspi1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi deleted file mode 100644 index 7d92ea2af7e..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b board - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/imx6qdl-clock.h> - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; -}; - -&i2c1 { - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - /* - * comment out this line to make the WiFi Eval-Module work in - * SD-Slot2, and add line: - * broken-cd; - * causes 6% CPU load if no WiFi module installed (polling) - */ - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SS0# */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - /* SS1# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 - /* SS2# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 - /* WP pin NOR Flash */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 - /* Flash nReset */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - /* make sure pin is GPIO and not ENET_REF_CLK */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 - /* SD2 level shifter output enable / SD2 Reset# */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi index ba13d55f419..70c0177d295 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2c board + * support for the imx6 based aristainetos2c+2d boards * * Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2015 Heiko Schocher <hs@denx.de> @@ -79,6 +79,14 @@ }; }; +&gpio7 { + eMMC_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; @@ -172,6 +180,8 @@ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 /* TPM Reset */ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + /* eMMC Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi index 8c2ed700751..8c2ed700751 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi index fa4dadefb65..c3724ec86fc 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2b-csl board + * support for the imx6 based aristainetos2c-cslb board * * Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2015 Heiko Schocher <hs@denx.de> @@ -104,19 +104,13 @@ }; &gpio7 { - wlan_reset { + eMMC_reset { gpio-hog; output-high; gpios = <8 GPIO_ACTIVE_HIGH>; }; }; -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -127,7 +121,9 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; no-1-8-v; + non-removable; status = "okay"; }; @@ -190,31 +186,15 @@ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 /* make sure pin is GPIO and not ENET_REF_CLK */ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 - /* WLAN Module Reset# */ + /* TPM PP */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 + /* TPM Reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + /* eMMC Reset# */ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 >; }; - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 @@ -237,12 +217,16 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 >; }; }; diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index fe6bb9bf03c..249b0f8f667 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -2,7 +2,6 @@ /* * Copyright 2020 Toradex */ - / { wdt-reboot { compatible = "wdt-reboot"; @@ -90,11 +89,11 @@ u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { +&{/soc@0/bus@30800000/i2c@30a20000/pmic} { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { +&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index 1c67c08c880..fb0756d6e19 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -203,115 +203,123 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71840", "rohm,bd71837"; - bd71837,pmic-buck2-uses-i2c-dvs; - bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ - gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; - /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + /* Assembled on V1.1 HW and later */ + pmic { + reg = <0x25>; + u-boot,dm-spl; + compatible = "nxp,pca9450a"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - reg = <0x4b>; - - gpo { - rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ - }; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-always-on; - regulator-boot-on; + u-boot,dm-spl; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; regulator-compatible = "buck1"; - regulator-max-microvolt = <1300000>; - regulator-min-microvolt = <700000>; - regulator-ramp-delay = <1250>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-always-on; - regulator-boot-on; + buck2_reg: regulator@1 { + reg = <1>; regulator-compatible = "buck2"; - regulator-max-microvolt = <1300000>; - regulator-min-microvolt = <700000>; - regulator-ramp-delay = <1250>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; }; - buck5_reg: BUCK5 { - regulator-always-on; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; - regulator-compatible = "buck5"; - regulator-max-microvolt = <1350000>; - regulator-min-microvolt = <700000>; + regulator-always-on; }; - buck6_reg: BUCK6 { - regulator-always-on; + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; - regulator-compatible = "buck6"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3000000>; + regulator-always-on; }; - buck7_reg: BUCK7 { - regulator-always-on; + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; - regulator-compatible = "buck7"; - regulator-max-microvolt = <1995000>; - regulator-min-microvolt = <1605000>; + regulator-always-on; }; - buck8_reg: BUCK8 { - regulator-always-on; + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; - regulator-compatible = "buck8"; - regulator-max-microvolt = <1400000>; - regulator-min-microvolt = <800000>; + regulator-always-on; }; - ldo1_reg: LDO1 { - regulator-always-on; - regulator-boot-on; + ldo1_reg: regulator@6 { + reg = <6>; regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-always-on; - regulator-boot-on; + ldo2_reg: regulator@7 { + reg = <7>; regulator-compatible = "ldo2"; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-always-on; - regulator-boot-on; + ldo3_reg: regulator@8 { + reg = <8>; regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-always-on; - regulator-boot-on; + ldo4_reg: regulator@9 { + reg = <9>; regulator-compatible = "ldo4"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; - ldo5_reg: LDO5 { + ldo5_reg: regulator@10 { + reg = <10>; regulator-compatible = "ldo5"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; }; - ldo6_reg: LDO6 { - regulator-always-on; - regulator-boot-on; - regulator-compatible = "ldo6"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <900000>; - }; }; }; @@ -321,12 +329,6 @@ reg = <0x32>; }; - adc@34 { - compatible = "maxim,max11607"; - reg = <0x34>; - vcc-supply = <&ldo5_reg>; - }; - eeprom_module: eeprom@50 { compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; diff --git a/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi index f66eca14b12..489efa150a6 100644 --- a/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi +++ b/arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi @@ -4,4 +4,5 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ +#include "meson-g12-common-u-boot.dtsi" #include "meson-khadas-vim3-u-boot.dtsi" diff --git a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi index b5da4fdfc3e..81fd5be3783 100644 --- a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi +++ b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi @@ -4,8 +4,6 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ -#include "meson-g12-common-u-boot.dtsi" - / { aliases { spi0 = &spifc; diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi b/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi index f66eca14b12..a591c0c9f23 100644 --- a/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi @@ -4,4 +4,5 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ +#include "meson-sm1-u-boot.dtsi" #include "meson-khadas-vim3-u-boot.dtsi" diff --git a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi index 2a8f0545b1a..c4319880759 100644 --- a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi @@ -4,7 +4,7 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ -#include "meson-g12-common-u-boot.dtsi" +#include "meson-sm1-u-boot.dtsi" ðmac { snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; diff --git a/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi b/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi index 236f2468dc2..8ebc1caa4a7 100644 --- a/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-sei610-u-boot.dtsi @@ -4,4 +4,4 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ -#include "meson-g12-common-u-boot.dtsi" +#include "meson-sm1-u-boot.dtsi" diff --git a/arch/arm/dts/meson-sm1-u-boot.dtsi b/arch/arm/dts/meson-sm1-u-boot.dtsi new file mode 100644 index 00000000000..e05d4c369ad --- /dev/null +++ b/arch/arm/dts/meson-sm1-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_a { + compatible = "amlogic,meson-sm1-mmc"; +}; + +&sd_emmc_b { + compatible = "amlogic,meson-sm1-mmc"; +}; + +&sd_emmc_c { + compatible = "amlogic,meson-sm1-mmc"; +}; + diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index cb8991aa253..6317b47e41a 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" / { - aliases { - spi0 = &spi1; - }; - chosen { u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; }; diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi index fe437bbfe2f..e75cf99f8fa 100644 --- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -136,7 +136,7 @@ }; &pinctrl { - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; @@ -217,3 +217,7 @@ }; }; }; + +&timer5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts index c5afa0c1620..592b182c1aa 100644 --- a/arch/arm/dts/stm32429i-eval.dts +++ b/arch/arm/dts/stm32429i-eval.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@00000000 { device_type = "memory"; reg = <0x00000000 0x2000000>; }; @@ -54,19 +54,26 @@ regulator-max-microvolt = <3300000>; }; + vdd_panel: vdd-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpiog 6 1>; linux,default-trigger = "heartbeat"; }; - orange { + led-orange { gpios = <&gpiog 7 1>; }; - red { + led-red { gpios = <&gpiog 10 1>; }; - blue { + led-blue { gpios = <&gpiog 12 1>; }; }; @@ -97,6 +104,7 @@ panel_rgb: panel-rgb { compatible = "ampire,am-480272h3tmqw-t01h"; + power-supply = <&vdd_panel>; status = "okay"; port { panel_in_rgb: endpoint { @@ -191,9 +199,8 @@ <dc { status = "okay"; - pinctrl-0 = <<dc_pins>; + pinctrl-0 = <<dc_pins_a>; pinctrl-names = "default"; - dma-ranges; port { ltdc_out_rgb: endpoint { diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi index d5fb92795d6..f2195a6c517 100644 --- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -165,7 +165,7 @@ }; }; - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; @@ -178,7 +178,7 @@ &qspi { reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>; - qflash0: n25q512a { + qflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index d77eb53c6aa..9940cf18730 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x2000000>; }; @@ -30,17 +30,17 @@ leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpiof 10 1>; linux,default-trigger = "heartbeat"; }; - orange { + led-orange { gpios = <&stmfx_pinctrl 17 1>; }; - red { + led-red { gpios = <&gpiob 7 1>; }; - blue { + led-blue { gpios = <&stmfx_pinctrl 19 1>; }; }; @@ -59,7 +59,6 @@ joystick { compatible = "gpio-keys"; - #size-cells = <0>; pinctrl-0 = <&joystick_pins>; pinctrl-names = "default"; button-0 { @@ -130,7 +129,7 @@ interrupts = <8 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gpioi>; - stmfx_pinctrl: stmfx-pin-controller { + stmfx_pinctrl: pinctrl { compatible = "st,stmfx-0300-pinctrl"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi index 7ed68286ba5..adf502694b5 100644 --- a/arch/arm/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/dts/stm32f4-pinctrl.dtsi @@ -127,7 +127,7 @@ st,bank-name = "GPIOK"; }; - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; @@ -140,7 +140,7 @@ }; }; - usart3_pins_a: usart3@0 { + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ bias-disable; @@ -153,7 +153,7 @@ }; }; - usbotg_fs_pins_a: usbotg_fs@0 { + usbotg_fs_pins_a: usbotg-fs-0 { pins { pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ @@ -164,7 +164,7 @@ }; }; - usbotg_fs_pins_b: usbotg_fs@1 { + usbotg_fs_pins_b: usbotg-fs-1 { pins { pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */ <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */ @@ -175,7 +175,7 @@ }; }; - usbotg_hs_pins_a: usbotg_hs@0 { + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/ <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ @@ -195,7 +195,7 @@ }; }; - ethernet_mii: mii@0 { + ethernet_mii: mii-0 { pins { pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */ <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */ @@ -215,13 +215,13 @@ }; }; - adc3_in8_pin: adc@200 { + adc3_in8_pin: adc-200 { pins { pinmux = <STM32_PINMUX('F', 10, ANALOG)>; }; }; - pwm1_pins: pwm@1 { + pwm1_pins: pwm1-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ @@ -229,14 +229,14 @@ }; }; - pwm3_pins: pwm@3 { + pwm3_pins: pwm3-0 { pins { pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ }; }; - i2c1_pins: i2c1@0 { + i2c1_pins: i2c1-0 { pins { pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */ <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */ @@ -246,7 +246,7 @@ }; }; - ltdc_pins: ltdc@0 { + ltdc_pins_a: ltdc-0 { pins { pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ @@ -280,7 +280,86 @@ }; }; - dcmi_pins: dcmi@0 { + ltdc_pins_b: ltdc-1 { + pins { + pinmux = <STM32_PINMUX('C', 6, AF14)>, + /* LCD_HSYNC */ + <STM32_PINMUX('A', 4, AF14)>, + /* LCD_VSYNC */ + <STM32_PINMUX('G', 7, AF14)>, + /* LCD_CLK */ + <STM32_PINMUX('C', 10, AF14)>, + /* LCD_R2 */ + <STM32_PINMUX('B', 0, AF9)>, + /* LCD_R3 */ + <STM32_PINMUX('A', 11, AF14)>, + /* LCD_R4 */ + <STM32_PINMUX('A', 12, AF14)>, + /* LCD_R5 */ + <STM32_PINMUX('B', 1, AF9)>, + /* LCD_R6*/ + <STM32_PINMUX('G', 6, AF14)>, + /* LCD_R7 */ + <STM32_PINMUX('A', 6, AF14)>, + /* LCD_G2 */ + <STM32_PINMUX('G', 10, AF9)>, + /* LCD_G3 */ + <STM32_PINMUX('B', 10, AF14)>, + /* LCD_G4 */ + <STM32_PINMUX('D', 6, AF14)>, + /* LCD_B2 */ + <STM32_PINMUX('G', 11, AF14)>, + /* LCD_B3*/ + <STM32_PINMUX('B', 11, AF14)>, + /* LCD_G5 */ + <STM32_PINMUX('C', 7, AF14)>, + /* LCD_G6 */ + <STM32_PINMUX('D', 3, AF14)>, + /* LCD_G7 */ + <STM32_PINMUX('G', 12, AF9)>, + /* LCD_B4 */ + <STM32_PINMUX('A', 3, AF14)>, + /* LCD_B5 */ + <STM32_PINMUX('B', 8, AF14)>, + /* LCD_B6 */ + <STM32_PINMUX('B', 9, AF14)>, + /* LCD_B7 */ + <STM32_PINMUX('F', 10, AF14)>; + /* LCD_DE */ + slew-rate = <2>; + }; + }; + + spi5_pins: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF5)>, + /* SPI5_CLK */ + <STM32_PINMUX('F', 9, AF5)>; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 8, AF5)>; + /* SPI5_MISO */ + bias-disable; + }; + }; + + i2c3_pins: i2c3-0 { + pins { + pinmux = <STM32_PINMUX('C', 9, AF4)>, + /* I2C3_SDA */ + <STM32_PINMUX('A', 8, AF4)>; + /* I2C3_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; + + dcmi_pins: dcmi-0 { pins { pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */ @@ -303,7 +382,7 @@ }; }; - sdio_pins: sdio_pins@0 { + sdio_pins: sdio-pins-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ @@ -316,7 +395,7 @@ }; }; - sdio_pins_od: sdio_pins_od@0 { + sdio_pins_od: sdio-pins-od-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index 52f80320bc8..df99e01393a 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -123,7 +123,7 @@ }; &pinctrl { - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; @@ -192,3 +192,7 @@ &rcc { u-boot,dm-pre-reloc; }; + +&timer5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts index 3a83ef5f604..42477c8d3ff 100644 --- a/arch/arm/dts/stm32f429-disco.dts +++ b/arch/arm/dts/stm32f429-disco.dts @@ -7,6 +7,8 @@ #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -17,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@90000000 { device_type = "memory"; reg = <0x90000000 0x800000>; }; @@ -28,10 +30,10 @@ leds { compatible = "gpio-leds"; - red { + led-red { gpios = <&gpiog 14 0>; }; - green { + led-green { gpios = <&gpiog 13 0>; linux,default-trigger = "heartbeat"; }; @@ -66,12 +68,103 @@ status = "okay"; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; + + stmpe811@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioa>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + }; +}; + +<dc { + status = "okay"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-names = "default"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + &rtc { assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSI>; status = "okay"; }; +&spi5 { + status = "okay"; + pinctrl-0 = <&spi5_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>; + + l3gd20: l3gd20@0 { + compatible = "st,l3gd20-gyro"; + spi-max-frequency = <10000000>; + st,drdy-int-pin = <2>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>, + <2 IRQ_TYPE_EDGE_RISING>; + reg = <0>; + status = "okay"; + }; + + display: display@1{ + /* Connect panel-ilitek-9341 to ltdc */ + compatible = "st,sf-tc240t-9370-t"; + reg = <1>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi index db0b82e89ea..a81e916064c 100644 --- a/arch/arm/dts/stm32f429.dtsi +++ b/arch/arm/dts/stm32f429.dtsi @@ -39,7 +39,7 @@ }; soc { - romem: nvmem@1fff7800 { + romem: efuse@1fff7800 { compatible = "st,stm32f4-otp"; reg = <0x1fff7800 0x400>; #address-cells = <1>; @@ -277,12 +277,10 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; clocks = <&rcc 1 CLK_RTC>; - clock-names = "ck_rtc"; assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; - interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -362,6 +360,18 @@ status = "disabled"; }; + i2c3: i2c@40005c00 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005c00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32F4_APB1_RESET(I2C3)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; @@ -374,14 +384,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; @@ -546,8 +556,8 @@ status = "disabled"; }; - syscfg: system-config@40013800 { - compatible = "syscon"; + syscfg: syscon@40013800 { + compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; }; @@ -620,6 +630,9 @@ reg = <0x40015000 0x400>; interrupts = <85>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + dmas = <&dma2 3 2 0x400 0x0>, + <&dma2 4 2 0x400 0x0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -634,7 +647,7 @@ }; pwrcfg: power-config@40007000 { - compatible = "syscon"; + compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; }; @@ -748,7 +761,6 @@ rng: rng@50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; - interrupts = <80>; clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; }; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 5a89f130548..7223ba4a60d 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -66,7 +66,7 @@ }; }; - qspi: quadspi@A0001000 { + qspi: spi@A0001000 { compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; @@ -220,7 +220,7 @@ }; }; - usart3_pins_a: usart3@0 { + usart3_pins_a: usart3-0 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; @@ -235,17 +235,9 @@ u-boot,dm-pre-reloc; }; -&rcc { - u-boot,dm-pre-reloc; -}; - -&syscfg { - u-boot,dm-pre-reloc; -}; - &qspi { reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; - flash0: n25q128a { + flash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -255,3 +247,15 @@ reg = <0>; }; }; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; +}; + +&timer5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index d50c38dc788..23d87ee27a1 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@00000000 { device_type = "memory"; reg = <0x00000000 0x1000000>; }; @@ -35,23 +35,30 @@ regulator-max-microvolt = <3300000>; }; + vdd_dsi: vdd-dsi { + compatible = "regulator-fixed"; + regulator-name = "vdd_dsi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; - orange { + led-orange { gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; }; - red { + led-red { gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; }; - blue { + led-blue { gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; }; }; @@ -114,6 +121,7 @@ compatible = "orisetech,otm8009a"; reg = <0>; /* dsi virtual channel (0..3) */ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; + power-supply = <&vdd_dsi>; status = "okay"; port { @@ -125,7 +133,6 @@ }; <dc { - dma-ranges; status = "okay"; port { diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi index 69c862d973b..5f6a7976bb3 100644 --- a/arch/arm/dts/stm32f469.dtsi +++ b/arch/arm/dts/stm32f469.dtsi @@ -8,7 +8,6 @@ dsi: dsi@40016c00 { compatible = "st,stm32-dsi"; reg = <0x40016c00 0x800>; - interrupts = <92>; resets = <&rcc STM32F4_APB2_RESET(DSI)>; reset-names = "apb"; clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi index 9314128df18..fe4cfda72a4 100644 --- a/arch/arm/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/dts/stm32f7-pinctrl.dtsi @@ -127,7 +127,7 @@ st,bank-name = "GPIOK"; }; - cec_pins_a: cec@0 { + cec_pins_a: cec-0 { pins { pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */ slew-rate = <0>; @@ -136,7 +136,7 @@ }; }; - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; @@ -149,7 +149,7 @@ }; }; - usart1_pins_b: usart1@1 { + usart1_pins_b: usart1-1 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; @@ -162,7 +162,7 @@ }; }; - i2c1_pins_b: i2c1@0 { + i2c1_pins_b: i2c1-0 { pins { pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */ <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */ @@ -172,7 +172,7 @@ }; }; - usbotg_hs_pins_a: usbotg-hs@0 { + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ @@ -192,7 +192,7 @@ }; }; - usbotg_hs_pins_b: usbotg-hs@1 { + usbotg_hs_pins_b: usbotg-hs-1 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */ @@ -212,7 +212,7 @@ }; }; - usbotg_fs_pins_a: usbotg-fs@0 { + usbotg_fs_pins_a: usbotg-fs-0 { pins { pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ @@ -223,7 +223,7 @@ }; }; - sdio_pins_a: sdio_pins_a@0 { + sdio_pins_a: sdio-pins-a-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */ @@ -236,7 +236,7 @@ }; }; - sdio_pins_od_a: sdio_pins_od_a@0 { + sdio_pins_od_a: sdio-pins-od-a-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */ @@ -254,7 +254,7 @@ }; }; - sdio_pins_b: sdio_pins_b@0 { + sdio_pins_b: sdio-pins-b-0 { pins { pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */ @@ -267,7 +267,7 @@ }; }; - sdio_pins_od_b: sdio_pins_od_b@0 { + sdio_pins_od_b: sdio-pins-od-b-0 { pins1 { pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */ diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 32613c97694..46bd1102df5 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -26,7 +26,6 @@ interrupt-names = "macirq", "eth_wake_irq"; snps,pbl = <8>; snps,mixed-burst; - dma-ranges; pinctrl-0 = <ðernet_mii>; phy-mode = "rmii"; phy-handle = <&phy0>; @@ -43,7 +42,7 @@ }; }; - qspi: quadspi@A0001000 { + qspi: spi@A0001000 { compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index d8f9d8dc5f2..4f34fc9a8cb 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -212,7 +212,7 @@ }; }; - usart1_pins_b: usart1@1 { + usart1_pins_b: usart1-1 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; @@ -229,7 +229,7 @@ &qspi { reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; - qflash0: n25q128a { + qflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -239,7 +239,3 @@ reg = <0>; }; }; - -&timer5 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 4fef0164cf5..9430dc08ec5 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x800000>; }; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 3f312ab3a77..ba9b3cd03ce 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -264,12 +264,10 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; clocks = <&rcc 1 CLK_RTC>; - clock-names = "ck_rtc"; assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; - interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -461,8 +459,8 @@ status = "disabled"; }; - syscfg: system-config@40013800 { - compatible = "syscon"; + syscfg: syscon@40013800 { + compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; }; @@ -529,7 +527,7 @@ }; pwrcfg: power-config@40007000 { - compatible = "syscon"; + compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; }; @@ -551,7 +549,7 @@ assigned-clock-rates = <1000000>; }; - dma1: dma@40026000 { + dma1: dma-controller@40026000 { compatible = "st,stm32-dma"; reg = <0x40026000 0x400>; interrupts = <11>, @@ -567,7 +565,7 @@ status = "disabled"; }; - dma2: dma@40026400 { + dma2: dma-controller@40026400 { compatible = "st,stm32-dma"; reg = <0x40026400 0x400>; interrupts = <56>, diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index c1d7d6b8f52..7dfe430a402 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -215,7 +215,7 @@ }; }; - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; @@ -228,7 +228,7 @@ &qspi { reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>; - flash0: mx66l51235l { + flash0: mx66l51235l@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 8d51e5b0fb8..03cfbd7cc2f 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x1000000>; }; @@ -30,11 +30,11 @@ leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - red { + led-red { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index 361c8e5d80f..54dd406b6ba 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -39,7 +39,7 @@ /* * Memory configuration from sdram datasheet IS42S32800G-6BLI - * firsct bank is bank@0 + * first bank is bank@0 * second bank is bank@1 */ bank1: bank@1 { @@ -218,3 +218,7 @@ &sdmmc1 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; }; + +&timer5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index e3a5c537f3c..141083f8d12 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -163,7 +163,7 @@ #interrupt-cells = <2>; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */ <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */ @@ -173,7 +173,7 @@ }; }; - ethernet_rmii: rmii@0 { + ethernet_rmii: rmii-0 { pins { pinmux = <STM32_PINMUX('G', 11, AF11)>, <STM32_PINMUX('G', 13, AF11)>, @@ -256,7 +256,7 @@ }; }; - usart1_pins: usart1@0 { + usart1_pins: usart1-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ bias-disable; @@ -269,7 +269,7 @@ }; }; - usart2_pins: usart2@0 { + usart2_pins: usart2-0 { pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ bias-disable; @@ -282,7 +282,7 @@ }; }; - usbotg_hs_pins_a: usbotg-hs@0 { + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */ <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */ diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 4b4e7a99f74..e4e472336b1 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -74,6 +74,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40003800 0x400>; interrupts = <36>; + resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; clocks = <&rcc SPI2_CK>; status = "disabled"; @@ -85,12 +86,13 @@ compatible = "st,stm32h7-spi"; reg = <0x40003c00 0x400>; interrupts = <51>; + resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; clocks = <&rcc SPI3_CK>; status = "disabled"; }; usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; @@ -144,21 +146,21 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; }; usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; @@ -171,6 +173,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013000 0x400>; interrupts = <35>; + resets = <&rcc STM32H7_APB2_RESET(SPI1)>; clocks = <&rcc SPI1_CK>; status = "disabled"; }; @@ -181,6 +184,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013400 0x400>; interrupts = <84>; + resets = <&rcc STM32H7_APB2_RESET(SPI4)>; clocks = <&rcc SPI4_CK>; status = "disabled"; }; @@ -191,11 +195,12 @@ compatible = "st,stm32h7-spi"; reg = <0x40015000 0x400>; interrupts = <85>; + resets = <&rcc STM32H7_APB2_RESET(SPI5)>; clocks = <&rcc SPI5_CK>; status = "disabled"; }; - dma1: dma@40020000 { + dma1: dma-controller@40020000 { compatible = "st,stm32-dma"; reg = <0x40020000 0x400>; interrupts = <11>, @@ -213,7 +218,7 @@ status = "disabled"; }; - dma2: dma@40020400 { + dma2: dma-controller@40020400 { compatible = "st,stm32-dma"; reg = <0x40020400 0x400>; interrupts = <56>, @@ -293,7 +298,17 @@ status = "disabled"; }; - mdma1: dma@52000000 { + ltdc: display-controller@50001000 { + compatible = "st,stm32-ltdc"; + reg = <0x50001000 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32H7_APB3_RESET(LTDC)>; + clocks = <&rcc LTDC_CK>; + clock-names = "lcd"; + status = "disabled"; + }; + + mdma1: dma-controller@52000000 { compatible = "st,stm32h7-mdma"; reg = <0x52000000 0x1000>; interrupts = <122>; @@ -325,8 +340,8 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; }; - syscfg: system-config@58000400 { - compatible = "syscon"; + syscfg: syscon@58000400 { + compatible = "st,stm32-syscfg", "syscon"; reg = <0x58000400 0x400>; }; @@ -336,6 +351,7 @@ compatible = "st,stm32h7-spi"; reg = <0x58001400 0x400>; interrupts = <86>; + resets = <&rcc STM32H7_APB4_RESET(SPI6)>; clocks = <&rcc SPI6_CK>; status = "disabled"; }; @@ -451,7 +467,6 @@ assigned-clock-parents = <&rcc LSE_CK>; interrupt-parent = <&exti>; interrupts = <17 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -466,7 +481,7 @@ }; pwrcfg: power-config@58024800 { - compatible = "syscon"; + compatible = "st,stm32-power-config", "syscon"; reg = <0x58024800 0x400>; }; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 43c30bfcbe5..81007161e74 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@d0000000 { device_type = "memory"; reg = <0xd0000000 0x2000000>; }; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index e4d3c58f3d9..8f398178f5e 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -53,7 +53,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@d0000000 { device_type = "memory"; reg = <0xd0000000 0x2000000>; }; diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 7ec90fe4a3f..d0aa5eabe5e 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -159,6 +159,13 @@ u-boot,dm-pre-proper; }; +/* temp = waiting kernel update */ +&m4_rproc { + resets = <&rcc MCU_R>, + <&rcc MCU_HOLD_BOOT_R>; + reset-names = "mcu_rst", "hold_boot"; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index 5a237a3b7bf..e8508aa4d5a 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -105,9 +105,18 @@ * On DRC02, the SoM does not have SDIO WiFi. The pins * are used for on-board microSD slot instead. */ - /delete-property/broken-cd; - cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; }; &spi1 { diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi new file mode 100644 index 00000000000..3cac663d987 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15xx-dhcom-u-boot.dtsi" + +/ { + aliases { + /delete-property/ ethernet1; + }; +}; + +/delete-node/ &ksz8851; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts new file mode 100644 index 00000000000..7f5cff49b70 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15xx-dhcom.dtsi" + +/ { + model = "DH Electronics STM32MP15xx DHCOM PicoITX"; + compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx"; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpioa { + /* + * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable + * port power. This signal should be handled by USB power sequencing + * in order to turn on port power when USB bus is powered up, but so + * far there is no such functionality. + */ + usb-port-power { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-low; + line-name = "usb-port-power"; + }; +}; + +&i2c2 { /* On board-to-board connector (optional) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* On board-to-board connector */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index 643aec94ce7..dafcce43239 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -299,8 +299,8 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; @@ -314,15 +314,6 @@ #address-cells = <1>; #size-cells = <1>; }; - - flash1: mx66l51235l@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; }; &rng1 { @@ -338,16 +329,29 @@ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,sig-dir; st,neg-edge; - st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; status = "okay"; }; +&sdmmc1_b4_pins_a { + /* + * SD bus pull-up resistors: + * - optional on SoMs with SD voltage translator + * - mandatory on SoMs without SD voltage translator + */ + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + &sdmmc2 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index 88f25d89b22..9b5dda318ec 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -192,7 +192,8 @@ }; &usbotg_hs { - dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; diff --git a/arch/arm/dts/sun50i-a64-amarula-relic.dts b/arch/arm/dts/sun50i-a64-amarula-relic.dts index 6cb2b7f0c81..c7bd73f35ed 100644 --- a/arch/arm/dts/sun50i-a64-amarula-relic.dts +++ b/arch/arm/dts/sun50i-a64-amarula-relic.dts @@ -1,12 +1,11 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Amarula Solutions B.V. - * Author: Jagan Teki <jagan@amarulasolutions.com> - */ +// Copyright (C) 2018 Amarula Solutions B.V. +// Author: Jagan Teki <jagan@amarulasolutions.com> /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -22,6 +21,41 @@ stdout-path = "serial0:115200n8"; }; + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_mclk_pin>; + clocks = <&ccu CLK_CSI_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_aldo1>; + DOVDD-supply = <®_dldo3>; + DVDD-supply = <®_eldo3>; + reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* CSI-RST-R: PE14 */ + powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* CSI-STBY-R: PE15 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc 1>; @@ -30,10 +64,70 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&csi { + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + &ehci0 { status = "okay"; }; +&i2c0 { + status = "okay"; + + sensor@48 { + compatible = "st,stlm75"; + reg = <0x48>; + }; +}; + +&i2c0_pins { + bias-pull-up; +}; + +&i2c1 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt5663"; + reg = <0x5d>; + AVDD28-supply = <®_ldo_io0>; /* VCC-CTP: GPIO0-LDO */ + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ + reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8 */ + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; @@ -197,6 +291,13 @@ regulator-name = "vdd-cpus"; }; +®_ldo_io0 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index ef1c90401bb..883f217efb8 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -1,48 +1,10 @@ -/* - * Copyright (c) 2016 ARM Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2016 ARM Ltd. /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -94,9 +56,40 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -130,8 +123,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -207,6 +198,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { /* * This regulator also drives the PE pingroup GPIOs, @@ -326,6 +325,22 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + status = "okay"; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Headphone Jack", "HP", + "MIC2", "Microphone Jack", + "Onboard Microphone", "MBIAS", + "MIC1", "Onboard Microphone"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; @@ -335,7 +350,19 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo4>; + device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; }; &usb_otg { @@ -343,8 +370,13 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi new file mode 100644 index 00000000000..578c37490d9 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Vasily khoruzhick <anarsoul@gmail.com> + */ + +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1120000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1160000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1240000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1260000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts index 31884dbc883..e58db8a6cab 100644 --- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts +++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts @@ -1,48 +1,10 @@ -/* - * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2017 Jagan Teki <jteki@openedev.com> /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -87,6 +49,22 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; @@ -120,12 +98,6 @@ }; /* i2c1 connected with gpio headers like pine64, bananapi */ -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; -}; - &i2c1_pins { bias-pull-up; }; @@ -186,6 +158,10 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/dts/sun50i-a64-oceanic-5205-5inmfd.dts b/arch/arm/dts/sun50i-a64-oceanic-5205-5inmfd.dts index 6a2154525d1..577f9e1d08a 100644 --- a/arch/arm/dts/sun50i-a64-oceanic-5205-5inmfd.dts +++ b/arch/arm/dts/sun50i-a64-oceanic-5205-5inmfd.dts @@ -1,9 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Oceanic Systems (UK) Ltd. - * Copyright (C) 2019 Amarula Solutions B.V. - * Author: Jagan Teki <jagan@amarulasolutions.com> - */ +// Copyright (C) 2019 Oceanic Systems (UK) Ltd. +// Copyright (C) 2019 Amarula Solutions B.V. +// Author: Jagan Teki <jagan@amarulasolutions.com> /dts-v1/; @@ -37,6 +35,22 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + AVDD28-supply = <®_ldo_io0>; /* VDD_CTP: GPIO0-LDO */ + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ + reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH11 */ + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -52,6 +66,13 @@ regulator-name = "vcc-phy"; }; +®_ldo_io0 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vdd-ctp"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts index 96ab0227e82..efb20846de4 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts @@ -1,8 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Martin Ayotte <martinayotte@gmail.com> - * Copyright (C) 2019 Sunil Mohan Adapa <sunil@medhas.org> - */ +// Copyright (C) 2018 Martin Ayotte <martinayotte@gmail.com> +// Copyright (C) 2019 Sunil Mohan Adapa <sunil@medhas.org> #include "sun50i-a64-olinuxino.dts" @@ -15,9 +13,13 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; status = "okay"; }; + +&pio { + vcc-pc-supply = <®_eldo1>; +}; diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index f7a4bccaa5d..f3f8e177ab6 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -1,48 +1,10 @@ -/* - * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2017 Jagan Teki <jteki@openedev.com> /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -70,6 +32,15 @@ }; }; + leds { + compatible = "gpio-leds"; + + led-0 { + label = "a64-olinuxino:red:user"; + gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + }; + }; + reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; regulator-name = "usb1-vbus"; @@ -87,6 +58,22 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; @@ -140,7 +127,7 @@ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_aldo2>; + vmmc-supply = <®_dcdc1>; vqmmc-supply = <®_dldo4>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -163,6 +150,34 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_aldo1>; + vcc-pg-supply = <®_dldo4>; +}; + +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo2>; + */ +}; + +&pio { + vcc-pa-supply = <®_dcdc1>; + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo4>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_rsb { status = "okay"; @@ -175,8 +190,22 @@ }; }; +/* VCC-PL is powered by aldo2 but we cannot add it as the RSB */ +/* interface used to talk to the PMIC in on the PL pins */ +/* &r_pio { */ +/* vcc-pl-supply = <®_aldo2>; */ +/* }; */ + #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <2800000>; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts index b0c64f75792..fde9c7a99b1 100644 --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -1,49 +1,11 @@ -/* - * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> - * Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2017 Jagan Teki <jteki@openedev.com> +// Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org> /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -109,9 +71,40 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -170,6 +163,14 @@ bus-width = <4>; non-removable; status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupt-names = "host-wake"; + }; }; &ohci0 { @@ -180,6 +181,10 @@ status = "okay"; }; +&r_ir { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -188,11 +193,20 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ }; }; #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -310,6 +324,22 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + status = "okay"; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Headphone Jack", "HP", + "MIC2", "Microphone Jack", + "Onboard Microphone", "MBIAS", + "MIC1", "Onboard Microphone"; +}; + &spi0 { status = "okay"; @@ -333,7 +363,20 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <1500000>; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo4>; + device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; }; /* On Pi-2 connector, RTS/CTS optional */ diff --git a/arch/arm/dts/sun50i-a64-pine64-lts.dts b/arch/arm/dts/sun50i-a64-pine64-lts.dts index 72d6961dc31..302e24be0a3 100644 --- a/arch/arm/dts/sun50i-a64-pine64-lts.dts +++ b/arch/arm/dts/sun50i-a64-pine64-lts.dts @@ -1,8 +1,5 @@ -/* - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2018 ARM Ltd. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 ARM Ltd. #include "sun50i-a64-sopine-baseboard.dts" diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts index 24f1aac366d..b26181cf909 100644 --- a/arch/arm/dts/sun50i-a64-pine64-plus.dts +++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts @@ -1,44 +1,5 @@ -/* - * Copyright (c) 2016 ARM Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2016 ARM Ltd. #include "sun50i-a64-pine64.dts" @@ -63,3 +24,12 @@ reg = <1>; }; }; + +®_dc1sw { + /* + * Ethernet PHY needs 30ms to properly power up and some more + * to initialize. 100ms should be plenty of time to finish + * whole process. + */ + regulator-enable-ramp-delay = <100000>; +}; diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts index c077b6c1f45..2165f238af1 100644 --- a/arch/arm/dts/sun50i-a64-pine64.dts +++ b/arch/arm/dts/sun50i-a64-pine64.dts @@ -1,48 +1,10 @@ -/* - * Copyright (c) 2016 ARM Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2016 ARM Ltd. /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -75,6 +37,35 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -109,8 +100,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -156,6 +145,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; @@ -259,6 +256,20 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "MIC2", "Microphone Jack"; + status = "okay"; +}; + /* On Euler connector */ &spdif { status = "disabled"; diff --git a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi deleted file mode 100644 index 650ab97ec99..00000000000 --- a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com> - * - */ - -#include "sunxi-u-boot.dtsi" - -/* The ANX6345 eDP-bridge is on r_i2c */ -&r_i2c { - anx6345: edp-bridge@38 { - compatible = "analogix,anx6345"; - reg = <0x38>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - status = "okay"; - }; -}; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts index ec537c52972..64b1c54f87c 100644 --- a/arch/arm/dts/sun50i-a64-pinebook.dts +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -1,15 +1,14 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz> - * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com> - * - */ +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz> +// Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com> /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pwm/pwm.h> @@ -22,32 +21,17 @@ ethernet0 = &rtl8723cs; }; - vdd_bl: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "bl-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - enable-active-high; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 50000 0>; brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; default-brightness-level = <2>; enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - power-supply = <&vdd_bl>; + power-supply = <®_vbklt>; }; chosen { stdout-path = "serial0:115200n8"; - - framebuffer-lcd { - panel-supply = <®_dc1sw>; - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_fldo1>; - }; }; gpio_keys { @@ -60,20 +44,85 @@ linux,code = <SW_LID>; linux,can-disable; wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + panel_edp: panel-edp { + compatible = "neweast,wjfh116008a"; + backlight = <&backlight>; + power-supply = <®_dc1sw>; + + port { + panel_edp_in: endpoint { + remote-endpoint = <&anx6345_out_edp>; + }; }; }; - reg_vcc3v3: vcc3v3 { + reg_vbklt: vbklt { compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "vbklt"; + regulator-min-microvolt = <18000000>; + regulator-max-microvolt = <18000000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; + enable-active-high; }; wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + VCC-supply = <®_vcc5v0>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + sound-name-prefix = "Speaker Amp"; + }; + +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; }; &ehci0 { @@ -86,11 +135,15 @@ status = "okay"; }; +&mixer0 { + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ disable-wp; bus-width = <4>; status = "okay"; @@ -133,10 +186,61 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_eldo1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_aldo1>; + vcc-pg-supply = <®_eldo1>; +}; + &pwm { status = "okay"; }; +&r_i2c { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pl89_pins>; + status = "okay"; + + anx6345: anx6345@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + anx6345_in: port@0 { + reg = <0>; + anx6345_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_anx6345>; + }; + }; + + anx6345_out: port@1 { + reg = <1>; + anx6345_out_edp: endpoint { + remote-endpoint = <&panel_edp_in>; + }; + }; + }; + }; +}; + +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo2>; + */ +}; + &r_rsb { status = "okay"; @@ -148,20 +252,18 @@ }; }; -/* The ANX6345 eDP-bridge is on r_i2c */ -&r_i2c { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pl89_pins>; +#include "axp803.dtsi" + +&ac_power_supply { status = "okay"; }; -#include "axp803.dtsi" +&battery_power_supply { + status = "okay"; +}; ®_aldo1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-csi"; + regulator-name = "vcc-pe"; }; ®_aldo2 { @@ -224,12 +326,6 @@ regulator-name = "vcc-edp"; }; -®_dldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avdd-csi"; -}; - ®_dldo4 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -243,12 +339,6 @@ regulator-name = "cpvdd"; }; -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-1v8-csi"; -}; - ®_fldo1 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -262,21 +352,56 @@ regulator-name = "vdd-cpus"; }; -®_ldo_io0 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb"; - status = "okay"; -}; - ®_rtc_ldo { regulator-name = "vcc-rtc"; }; +&simplefb_lcd { + panel-supply = <®_dc1sw>; + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; +}; + &simplefb_hdmi { vcc-hdmi-supply = <®_dldo1>; }; +&sound { + status = "okay"; + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Microphone", "Internal Microphone Left", + "Microphone", "Internal Microphone Right", + "Headphone", "Headphone Jack", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Internal Microphone Left", "MBIAS", + "MIC1", "Internal Microphone Left", + "Internal Microphone Right", "HBIAS", + "MIC2", "Internal Microphone Right"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + + status = "okay"; +}; + +&tcon0_out { + tcon0_out_anx6345: endpoint { + remote-endpoint = <&anx6345_in_tcon0>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; @@ -288,7 +413,7 @@ }; &usbphy { - usb0_vbus-supply = <®_ldo_io0>; - usb1_vbus-supply = <®_ldo_io0>; + usb0_vbus-supply = <®_vcc5v0>; + usb1_vbus-supply = <®_vcc5v0>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts new file mode 100644 index 00000000000..0c42272106a --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> + +/dts-v1/; + +#include "sun50i-a64-pinephone.dtsi" + +/ { + model = "Pine64 PinePhone Developer Batch (1.0)"; + compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; +}; diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts new file mode 100644 index 00000000000..3e99a87e9ce --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> + +/dts-v1/; + +#include "sun50i-a64-pinephone.dtsi" + +/ { + model = "Pine64 PinePhone Braveheart (1.1)"; + compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64"; +}; + +&backlight { + power-supply = <®_ldo_io0>; + /* + * PWM backlight circuit on this PinePhone revision was changed since + * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight + * being off is around 20%. Duty cycle for the lowest brightness level + * also varries quite a bit between individual boards, so the lowest + * value here was chosen as a safe default. + */ + brightness-levels = < + 774 793 814 842 + 882 935 1003 1088 + 1192 1316 1462 1633 + 1830 2054 2309 2596 + 2916 3271 3664 4096>; + num-interpolated-steps = <50>; + default-brightness-level = <400>; +}; diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.2.dts b/arch/arm/dts/sun50i-a64-pinephone-1.2.dts new file mode 100644 index 00000000000..a9f5b670c9b --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinephone-1.2.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> + +/dts-v1/; + +#include "sun50i-a64-pinephone.dtsi" + +/ { + model = "Pine64 PinePhone (1.2)"; + compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64"; +}; + +&backlight { + power-supply = <®_ldo_io0>; + /* + * PWM backlight circuit on this PinePhone revision was changed since 1.0, + * and the lowest PWM duty cycle that doesn't lead to backlight being off + * is around 10%. Duty cycle for the lowest brightness level also varries + * quite a bit between individual boards, so the lowest value here was + * chosen as a safe default. + */ + brightness-levels = < + 5000 5248 5506 5858 6345 + 6987 7805 8823 10062 11543 + 13287 15317 17654 20319 23336 + 26724 30505 34702 39335 44427 + 50000 + >; + num-interpolated-steps = <50>; + default-brightness-level = <500>; +}; + +&lis3mdl { + /* + * Board revision 1.2 fixed routing of the interrupt to DRDY pin, + * enable interrupts. + */ + interrupt-parent = <&pio>; + interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ +}; diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi new file mode 100644 index 00000000000..25150aba749 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz> +// Copyright (C) 2020 Martijn Braam <martijn@brixit.nl> +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> + +#include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; + enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + /* Backlight configuration differs per PinePhone revision. */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + blue { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + }; + + green { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ + }; + + red { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + }; + }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ + sound-name-prefix = "Speaker Amp"; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ + vcc-supply = <®_dcdc1>; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dldo1>; + status = "okay"; + + panel@0 { + compatible = "xingbangda,xbd599"; + reg = <0>; + reset-gpios = <&pio 3 23 GPIO_ACTIVE_LOW>; /* PD23 */ + iovcc-supply = <®_dldo2>; + vcc-supply = <®_ldo_io0>; + backlight = <&backlight>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt917s"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + AVDD28-supply = <®_ldo_io0>; + VDDIO-supply = <®_ldo_io0>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + }; +}; + +&i2c1 { + status = "okay"; + + /* Magnetometer */ + lis3mdl: lis3mdl@1e { + compatible = "st,lis3mdl-magn"; + reg = <0x1e>; + vdd-supply = <®_dldo1>; + vddio-supply = <®_dldo1>; + }; + + /* Accelerometer/gyroscope */ + mpu6050@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&pio>; + interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ + vdd-supply = <®_dldo1>; + vddio-supply = <®_dldo1>; + }; +}; + +/* Connected to pogo pins (external spring based pinheader for user addons) */ +&i2c2 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo4>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo2>; + */ +}; + +&r_pwm { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dovdd-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-dsi-sensor"; +}; + +®_dldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-mipi-io"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-wifi-io"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-lpddr"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-lcd-ctp-stk"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8-typec"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Microphone", "Headset Microphone", + "Microphone", "Internal Microphone", + "Headphone", "Headphone Jack", + "Speaker", "Internal Earpiece", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Headphone Jack", "HP", + "Internal Earpiece", "EARPIECE", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Internal Microphone", "MBIAS", + "MIC1", "Internal Microphone", + "Headset Microphone", "HBIAS", + "MIC2", "Headset Microphone"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* Connected to the modem (hardware flow control can't be used) */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts new file mode 100644 index 00000000000..dc4ab6b434f --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinetab.dts @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz> + * + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "PineTab"; + compatible = "pine64,pinetab", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + ethernet0 = &rtl8723cs; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; + default-brightness-level = <15>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + power-supply = <&vdd_bl>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2c-csi { + compatible = "i2c-gpio"; + sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ + scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + /* Rear camera */ + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_mclk_pin>; + clocks = <&ccu CLK_CSI_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_dldo3>; + DOVDD-supply = <®_aldo1>; + DVDD-supply = <®_eldo3>; + reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ + powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; + }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + sound-name-prefix = "Speaker Amp"; + }; + + vdd_bl: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "bl-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + post-power-on-delay-ms = <200>; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&csi { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dldo1>; + status = "okay"; + + panel@0 { + compatible = "feixin,k101-im2ba02"; + reg = <0>; + avdd-supply = <®_dc1sw>; + dvdd-supply = <®_dc1sw>; + cvdd-supply = <®_ldo_io1>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + backlight = <&backlight>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + AVDD28-supply = <®_ldo_io1>; + }; +}; + +&i2c0_pins { + bias-pull-up; +}; + +&i2c1 { + status = "okay"; + + /* TODO: add Bochs BMA223 accelerometer here */ +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mixer1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723cs: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "dovdd-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi-dsi-sensor"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca-1v8"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <3500000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Microphone", "Internal Microphone Left", + "Microphone", "Internal Microphone Right", + "Headphone", "Headphone Jack", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Internal Microphone Left", "MBIAS", + "MIC1", "Internal Microphone Left", + "Internal Microphone Right", "HBIAS", + "MIC2", "Internal Microphone Right"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_ldo_io0>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts index 53fcc9098df..2f6ea9f3f6a 100644 --- a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts @@ -1,47 +1,7 @@ -/* - * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> - * - * Based on sun50i-a64-pine64.dts, which is: - * Copyright (c) 2016 ARM Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> +// Based on sun50i-a64-pine64.dts, which is: +// Copyright (c) 2016 ARM Ltd. /dts-v1/; @@ -55,6 +15,10 @@ aliases { ethernet0 = &emac; serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; }; chosen { @@ -80,6 +44,26 @@ }; }; +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -139,6 +123,12 @@ }; ®_dc1sw { + /* + * Ethernet PHY needs 30ms to properly power up and some more + * to initialize. 100ms should be plenty of time to finish + * whole process. + */ + regulator-enable-ramp-delay = <100000>; regulator-name = "vcc-phy"; }; @@ -164,12 +154,47 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "MIC2", "Microphone Jack"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; +/* On Pi-2 connector */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +/* On Euler connector */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +/* On Euler connector, RTS/CTS optional */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "disabled"; +}; + &usb_otg { dr_mode = "host"; status = "okay"; diff --git a/arch/arm/dts/sun50i-a64-sopine.dtsi b/arch/arm/dts/sun50i-a64-sopine.dtsi index 6723b8695e0..c48692b06e1 100644 --- a/arch/arm/dts/sun50i-a64-sopine.dtsi +++ b/arch/arm/dts/sun50i-a64-sopine.dtsi @@ -1,52 +1,33 @@ -/* - * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> - * - * Based on sun50i-a64-pine64.dts, which is: - * Copyright (c) 2016 ARM Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> +// Based on sun50i-a64-pine64.dts, which is: +// Copyright (c) 2016 ARM Ltd. #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> +&codec_analog { + cpvdd-supply = <®_eldo1>; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi deleted file mode 100644 index 1a64b7d09c2..00000000000 --- a/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Vasily Khoruzhick <anarsoul@gmail.com> - * - */ - -#include "sunxi-u-boot.dtsi" - -/ { - vdd_bl: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "bl-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 0>; - brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; - default-brightness-level = <2>; - enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - power-supply = <&vdd_bl>; - }; -}; - -/* The ANX6345 eDP-bridge is on i2c */ -&i2c0 { - anx6345: edp-bridge@38 { - compatible = "analogix,anx6345"; - reg = <0x38>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - status = "okay"; - }; -}; - -&pwm { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts index c455b24dd07..f5df5f705b7 100644 --- a/arch/arm/dts/sun50i-a64-teres-i.dts +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -1,13 +1,11 @@ -/* - * Copyright (C) Harald Geyer <harald@ccbib.org> - * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com> - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) Harald Geyer <harald@ccbib.org> +// based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com> /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -21,6 +19,15 @@ serial0 = &uart0; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 0>; + power-supply = <®_dcdc1>; + brightness-levels = <0 5 7 10 14 20 28 40 56 80 112>; + default-brightness-level = <5>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + }; + chosen { stdout-path = "serial0:115200n8"; @@ -70,6 +77,45 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ + sound-name-prefix = "Speaker Amp"; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; }; &ehci1 { @@ -77,14 +123,31 @@ }; -/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline) - * driver for this chip at the moment, the bootloader initializes it. - * However it can be accessed with the i2c-dev driver from user space. - */ &i2c0 { clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + anx6345: anx6345@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_dldo3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + anx6345_in: endpoint { + remote-endpoint = <&tcon0_out_anx6345>; + }; + }; + }; + }; +}; + +&mixer0 { status = "okay"; }; @@ -131,6 +194,10 @@ status = "okay"; }; +&pwm { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -145,6 +212,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <2800000>; @@ -239,7 +314,7 @@ }; /* - * The A64 chip cannot work without this regulator off, although + * The A64 chip cannot work with this regulator off, although * it seems to be only driving the AR100 core. * Maybe we don't still know well about CPUs domain. */ @@ -258,6 +333,43 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Microphone", "Headset Microphone", + "Microphone", "Internal Microphone", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Headphone Jack", "HP", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Internal Microphone", "MBIAS", + "MIC1", "Internal Microphone", + "Headset Microphone", "HBIAS", + "MIC2", "Headset Microphone"; + status = "okay"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + + status = "okay"; +}; + +&tcon0_out { + tcon0_out_anx6345: endpoint@0 { + reg = <0>; + remote-endpoint = <&anx6345_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index ff41abc96a9..8dfbcd14407 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -1,46 +1,7 @@ -/* - * Copyright (C) 2016 ARM Ltd. - * based on the Allwinner H3 dtsi: - * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2016 ARM Ltd. +// based on the Allwinner H3 dtsi: +// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> #include <dt-bindings/clock/sun50i-a64-ccu.h> #include <dt-bindings/clock/sun8i-de2.h> @@ -49,6 +10,7 @@ #include <dt-bindings/reset/sun50i-a64-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-r-ccu.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -84,35 +46,47 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; next-level-cache = <&L2>; + clocks = <&ccu 21>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; next-level-cache = <&L2>; + clocks = <&ccu 21>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; next-level-cache = <&L2>; + clocks = <&ccu 21>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; next-level-cache = <&L2>; + clocks = <&ccu 21>; + clock-names = "cpu"; + #cooling-cells = <2>; }; L2: l2-cache { @@ -139,15 +113,16 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-output-names = "ext-osc32k"; }; - iosc: internal-osc-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-accuracy = <300000000>; - clock-output-names = "iosc"; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { @@ -155,26 +130,33 @@ method = "smc"; }; - sound_spdif { + sound: sound { compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; + simple-audio-card,name = "sun50i-a64-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC"; + status = "disabled"; - simple-audio-card,cpu { - sound-dai = <&spdif>; + cpudai: simple-audio-card,cpu { + sound-dai = <&dai>; }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; + link_codec: simple-audio-card,codec { + sound-dai = <&codec>; }; }; - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - timer { compatible = "arm,armv8-timer"; + allwinner,erratum-unknown1; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 @@ -185,13 +167,76 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu0_thermal: gpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + + gpu1_thermal: gpu1-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - de2@1000000 { + bus@1000000 { compatible = "allwinner,sun50i-a64-de2"; reg = <0x1000000 0x400000>; allwinner,sram = <&de2_sram 1>; @@ -201,16 +246,28 @@ display_clocks: clock@0 { compatible = "allwinner,sun50i-a64-de2-clk"; - reg = <0x0 0x100000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; + reg = <0x0 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; resets = <&ccu RST_BUS_DE>; #clock-cells = <1>; #reset-cells = <1>; }; + rotate: rotate@20000 { + compatible = "allwinner,sun50i-a64-de2-rotate", + "allwinner,sun8i-a83t-de2-rotate"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&display_clocks CLK_BUS_ROT>, + <&display_clocks CLK_ROT>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_ROT>; + }; + mixer0: mixer@100000 { compatible = "allwinner,sun50i-a64-de2-mixer-0"; reg = <0x100000 0x100000>; @@ -225,11 +282,19 @@ #size-cells = <0>; mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - mixer0_out_tcon0: endpoint { + mixer0_out_tcon0: endpoint@0 { + reg = <0>; remote-endpoint = <&tcon0_in_mixer0>; }; + + mixer0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer0>; + }; }; }; }; @@ -248,9 +313,17 @@ #size-cells = <0>; mixer1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - mixer1_out_tcon1: endpoint { + mixer1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer1>; + }; + + mixer1_out_tcon1: endpoint@1 { + reg = <1>; remote-endpoint = <&tcon1_in_mixer1>; }; }; @@ -259,8 +332,7 @@ }; syscon: syscon@1c00000 { - compatible = "allwinner,sun50i-a64-system-control", - "syscon"; + compatible = "allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -278,6 +350,20 @@ reg = <0x0000 0x28000>; }; }; + + sram_c1: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x40000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x40000>; + }; + }; }; dma: dma-controller@1c02000 { @@ -299,6 +385,7 @@ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; @@ -315,12 +402,23 @@ reg = <0>; remote-endpoint = <&mixer0_out_tcon0>; }; + + tcon0_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon0>; + }; }; tcon0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; }; }; }; @@ -340,9 +438,17 @@ #size-cells = <0>; tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - tcon1_in_mixer1: endpoint { + tcon1_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon1>; + }; + + tcon1_in_mixer1: endpoint@1 { + reg = <1>; remote-endpoint = <&mixer1_out_tcon1>; }; }; @@ -360,6 +466,17 @@ }; }; + video-codec@1c0e000 { + compatible = "allwinner,sun50i-a64-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; @@ -405,6 +522,31 @@ sid: eeprom@1c14000 { compatible = "allwinner,sun50i-a64-sid"; reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 0x8>; + }; + }; + + crypto: crypto@1c15000 { + compatible = "allwinner,sun50i-a64-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun50i-a64-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; }; usb_otg: usb@1c19000 { @@ -417,6 +559,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; + dr_mode = "otg"; status = "disabled"; }; @@ -491,7 +634,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -503,22 +646,50 @@ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu 58>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; - i2c0_pins: i2c0_pins { + csi_pins: csi-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", + "PE7", "PE8", "PE9", "PE10", "PE11"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi_mclk_pin: csi-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + + i2c0_pins: i2c0-pins { pins = "PH0", "PH1"; function = "i2c0"; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pins = "PH2", "PH3"; function = "i2c1"; }; + i2c2_pins: i2c2-pins { + pins = "PE14", "PE15"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD6", "PD7", "PD8", "PD9", + "PD10", "PD11", "PD12", "PD13", + "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function = "lcd0"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -551,19 +722,19 @@ bias-pull-up; }; - pwm_pin: pwm_pin { + pwm_pin: pwm-pin { pins = "PD22"; function = "pwm"; }; - rmii_pins: rmii_pins { + rmii_pins: rmii-pins { pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; function = "emac"; drive-strength = <40>; }; - rgmii_pins: rgmii_pins { + rgmii_pins: rgmii-pins { pins = "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23"; @@ -571,17 +742,17 @@ drive-strength = <40>; }; - spdif_tx_pin: spdif { + spdif_tx_pin: spdif-tx-pin { pins = "PH8"; function = "spdif"; }; - spi0_pins: spi0 { + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; }; - spi1_pins: spi1 { + spi1_pins: spi1-pins { pins = "PD0", "PD1", "PD2", "PD3"; function = "spi1"; }; @@ -591,12 +762,12 @@ function = "uart0"; }; - uart1_pins: uart1_pins { + uart1_pins: uart1-pins { pins = "PG6", "PG7"; function = "uart1"; }; - uart1_rts_cts_pins: uart1_rts_cts_pins { + uart1_rts_cts_pins: uart1-rts-cts-pins { pins = "PG8", "PG9"; function = "uart1"; }; @@ -638,6 +809,14 @@ status = "disabled"; }; + lradc: lradc@1c21800 { + compatible = "allwinner,sun50i-a64-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c21800 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2s0: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-i2s", @@ -666,6 +845,41 @@ status = "disabled"; }; + dai: dai@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-codec-i2s"; + reg = <0x01c22c00 0x200>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec: codec@1c22e00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a33-codec"; + reg = <0x01c22e00 0x600>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "bus", "mod"; + status = "disabled"; + }; + + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun50i-a64-ths"; + reg = <0x01c25000 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -727,6 +941,8 @@ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -738,6 +954,8 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -749,12 +967,13 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; @@ -808,6 +1027,28 @@ }; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, @@ -830,6 +1071,75 @@ status = "disabled"; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 112>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + + dsi: dsi@1ca0000 { + compatible = "allwinner,sun50i-a64-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MIPI_DSI>; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun50i-a64-mipi-dphy", + "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + + deinterlace: deinterlace@1e00000 { + compatible = "allwinner,sun50i-a64-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01e00000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + <&ccu CLK_DRAM_DEINTERLACE>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; @@ -842,7 +1152,7 @@ resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; + phy-names = "phy"; status = "disabled"; ports { @@ -867,7 +1177,7 @@ compatible = "allwinner,sun50i-a64-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu 7>; + <&ccu CLK_PLL_VIDEO0>; clock-names = "bus", "mod", "pll-0"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; @@ -875,11 +1185,12 @@ }; rtc: rtc@1f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; + compatible = "allwinner,sun50i-a64-rtc", + "allwinner,sun8i-h3-rtc"; + reg = <0x01f00000 0x400>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; + clock-output-names = "osc32k", "osc32k-out", "iosc"; clocks = <&osc32k>; #clock-cells = <1>; }; @@ -896,13 +1207,19 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, - <&ccu 11>; + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; #reset-cells = <1>; }; + codec_analog: codec-analog@1f015c0 { + compatible = "allwinner,sun50i-a64-codec-analog"; + reg = <0x01f015c0 0x4>; + status = "disabled"; + }; + r_i2c: i2c@1f02400 { compatible = "allwinner,sun50i-a64-i2c", "allwinner,sun6i-a31-i2c"; @@ -915,6 +1232,19 @@ #size-cells = <0>; }; + r_ir: ir@1f02000 { + compatible = "allwinner,sun50i-a64-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01f02000 0x400>; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "disabled"; + }; + r_pwm: pwm@1f03800 { compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"; @@ -942,12 +1272,17 @@ function = "s_i2c"; }; - r_pwm_pin: pwm { + r_ir_rx_pin: r-ir-rx-pin { + pins = "PL11"; + function = "s_cir_rx"; + }; + + r_pwm_pin: r-pwm-pin { pins = "PL10"; function = "s_pwm"; }; - r_rsb_pins: rsb { + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; }; @@ -972,6 +1307,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; }; }; }; diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts new file mode 100644 index 00000000000..d18192d51d1 --- /dev/null +++ b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Sipeed Lichee Zero Plus"; + compatible = "sipeed,lichee-zero-plus", "sochip,s3", + "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts new file mode 100644 index 00000000000..9bab6b7f401 --- /dev/null +++ b/arch/arm/dts/sun8i-s3-pinecube.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "PineCube IP Camera"; + compatible = "pine64,pinecube", "allwinner,sun8i-s3"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "pine64:ir:led1"; + gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; + + led2 { + label = "pine64:ir:led2"; + gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_wifi: vcc-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ + vin-supply = <®_dcdc3>; + startup-delay-us = <200000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ + post-power-on-delay-ms = <200>; + }; +}; + +&csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_8bit_pins>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp203", + "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pe_pins>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi1_mclk_pin>; + clocks = <&ccu CLK_CSI1_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_ldo3>; + DOVDD-supply = <®_ldo3>; + DVDD-supply = <®_ldo4>; + reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ + powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Setup"; + linux,code = <KEY_SETUP>; + channel = <0>; + voltage = <190000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc_wifi>; + vqmmc-supply = <®_dcdc3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_dcdc3>; + vcc-pe-supply = <®_ldo3>; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-sys-cpu-ephy"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-dovdd-2v8-csi"; + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +®_ldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi new file mode 100644 index 00000000000..ca4672ed2e0 --- /dev/null +++ b/arch/arm/dts/sun8i-v3.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include "sun8i-v3s.dtsi" + +&ccu { + compatible = "allwinner,sun8i-v3-ccu"; +}; + +&emac { + /delete-property/ phy-handle; + /delete-property/ phy-mode; +}; + +&mdio_mux { + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&pio { + compatible = "allwinner,sun8i-v3-pinctrl"; +}; diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts new file mode 100644 index 00000000000..db5cd0b8574 --- /dev/null +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-v3s-licheepi-zero.dts" + +#include <dt-bindings/input/input.h> + +/ { + model = "Lichee Pi Zero with Dock"; + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", + "allwinner,sun8i-v3s"; + + leds { + /* The LEDs use PG0~2 pins, which conflict with MMC1 */ + status = "disabled"; + }; +}; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; + + button-600 { + label = "Select"; + linux,code = <KEY_SELECT>; + channel = <0>; + voltage = <600000>; + }; + + button-800 { + label = "Start"; + linux,code = <KEY_OK>; + channel = <0>; + voltage = <800000>; + }; +}; diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts index 3d9168cbaec..2e4587d26ce 100644 --- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts @@ -55,11 +55,29 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + blue_led { + label = "licheepi:blue:usr"; + gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + }; + + green_led { + label = "licheepi:green:usr"; + gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + default-state = "on"; + }; + + red_led { + label = "licheepi:red:usr"; + gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ + }; + }; }; &mmc0 { - pinctrl-0 = <&mmc0_pins_a>; - pinctrl-names = "default"; broken-cd; bus-width = <4>; vmmc-supply = <®_vcc3v3>; @@ -67,7 +85,7 @@ }; &uart0 { - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; pinctrl-names = "default"; status = "okay"; }; @@ -78,6 +96,6 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index ebefc0fefef..0c734167692 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -40,16 +40,31 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/clock/sun8i-de2.h> / { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -62,6 +77,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -79,6 +100,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -86,7 +108,8 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-accuracy = <50000>; + clock-output-names = "ext-osc32k"; }; }; @@ -96,7 +119,86 @@ #size-cells = <1>; ranges; - mmc0: mmc@01c0f000 { + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-v3s-de2-clk"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks 0>, + <&display_clocks 6>; + clock-names = "bus", + "mod"; + resets = <&display_clocks 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-v3s-system-control", + "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, @@ -110,12 +212,14 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, @@ -129,12 +233,14 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, @@ -153,7 +259,18 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + crypto@1c15000 { + compatible = "allwinner,sun8i-v3s-crypto", + "allwinner,sun8i-a33-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_CE>; + reset-names = "ahb"; + }; + + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -166,7 +283,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-v3s-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>; @@ -180,64 +297,118 @@ #phy-cells = <1>; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; - rtc: rtc@01c20400 { - compatible = "allwinner,sun6i-a31-rtc"; + rtc: rtc@1c20400 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-v3-rtc"; reg = <0x01c20400 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc32k>; + clock-output-names = "osc32k", "osc32k-out"; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-v3s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; - uart0_pins_a: uart0@0 { + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + + i2c0_pins: i2c0-pins { + pins = "PB6", "PB7"; + function = "i2c0"; + }; + + /omit-if-no-ref/ + i2c1_pe_pins: i2c1-pe-pins { + pins = "PE21", "PE22"; + function = "i2c1"; + }; + + uart0_pb_pins: uart0-pb-pins { pins = "PB8", "PB9"; function = "uart0"; - bias-pull-up; }; - mmc0_pins_a: mmc0@0 { + uart2_pins: uart2-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; drive-strength = <30>; bias-pull-up; }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + spi0_pins: spi0-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; }; - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; + timer@1c20c00 { + compatible = "allwinner,sun8i-v3s-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc24M>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -248,7 +419,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -259,7 +430,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -267,11 +438,106 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-v3s-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio_mux: mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + }; + + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csi1: camera@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x3000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; status = "disabled"; }; - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x1000>, <0x01c84000 0x2000>, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index e13f4d83e69..a9bd8b24fdc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2016-2018 NXP + * Copyright 2016-2018, 2020 NXP * Copyright 2015, Freescale Semiconductor */ @@ -179,8 +179,8 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ -/* LX2160A Soc Support */ -#elif defined(CONFIG_ARCH_LX2160A) +/* LX2160A/LX2162A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define TZPC_BASE 0x02200000 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) #if !defined(CONFIG_DM_I2C) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 7759acdb8f6..4335aa0ec28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2020 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -53,7 +53,7 @@ #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 -#ifndef CONFIG_ARCH_LX2160A +#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162) #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #else #define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 24a64b75752..b61666ed4b7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -15,7 +15,7 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) #else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) @@ -198,12 +198,12 @@ #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) #endif -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL @@ -267,7 +267,7 @@ defined(CONFIG_ARCH_LS1028A) #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 -#elif defined(CONFIG_ARCH_LX2160A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define USB_PHY_RX_EQ_VAL_3 0x0080 #define USB_PHY_RX_EQ_VAL_4 0x0880 #endif @@ -391,7 +391,7 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 -#elif defined(CONFIG_ARCH_LX2160A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define FSL_CHASSIS3_EC1_REGSR 27 #define FSL_CHASSIS3_EC2_REGSR 27 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 020548ac6ce..b24f38cac90 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * Copyright 2015 Freescale Semiconductor */ @@ -106,13 +106,16 @@ enum boot_src get_boot_src(void); #define SVR_LX2160A 0x873600 #define SVR_LX2120A 0x873620 #define SVR_LX2080A 0x873602 +#define SVR_LX2162A 0x873608 +#define SVR_LX2122A 0x873628 +#define SVR_LX2082A 0x87360A #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) #endif #ifdef CONFIG_ARCH_LS1028A diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 4c54e3d3d5e..36f36699a7c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2019 NXP + * Copyright 2015-2020 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -74,11 +74,13 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) #define FSL_DMA_STREAM_ID 5 @@ -91,7 +93,7 @@ #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_PEX_STREAM_ID_END 18 -#elif defined(CONFIG_ARCH_LX2160A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define FSL_PEX_STREAM_ID_END (0x100) #endif diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index 105a335daba..94e5bb674f2 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 872a158b714..52446e97c69 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h index d5557b89fcb..1735c0e3918 100644 --- a/arch/arm/include/asm/arch-stih410/sdhci.h +++ b/arch/arm/include/asm/arch-stih410/sdhci.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __STI_SDHCI_H__ diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h index f9e8d3704a8..30e7f398ebe 100644 --- a/arch/arm/include/asm/arch-stih410/sys_proto.h +++ b/arch/arm/include/asm/arch-stih410/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef _ASM_ARCH_SYS_PROTO_H diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h index bd3f4fd30ae..a1ce81ecadd 100644 --- a/arch/arm/include/asm/arch-stm32/stm32f.h +++ b/arch/arm/include/asm/arch-stm32/stm32f.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef _ASM_ARCH_STM32F_H diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h index 8af6de220d8..fe6ca03d2df 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h index 02faaeb663c..5cd6553d04d 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h index 2dad52a4002..4f57f175ff6 100644 --- a/arch/arm/include/asm/arch-stm32h7/gpio.h +++ b/arch/arm/include/asm/arch-stm32h7/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef _STM32_GPIO_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h index 458baca458b..2b0a6700080 100644 --- a/arch/arm/include/asm/arch-stm32h7/stm32.h +++ b/arch/arm/include/asm/arch-stm32h7/stm32.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index a646ea6a3ce..f817d328f43 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -158,6 +158,7 @@ enum sunxi_gpio_number { #define SUN5I_GPB_TWI1 2 #define SUN4I_GPB_TWI2 2 #define SUN5I_GPB_TWI2 2 +#define SUN8I_V3S_GPB_TWI0 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 5f0c1ae2182..43eae6d796d 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -183,6 +183,11 @@ void init_src(void); void init_snvs(void); void imx_wdog_disable_powerdown(void); +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size); + int arch_auxiliary_core_check_up(u32 core_id); int board_mmc_get_env_dev(int devno); diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9d1f73dfc70..04b9729109e 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -65,6 +65,11 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP +config TARGET_APALIS_IMX8X + bool "Support Apalis iMX8X module" + select BOARD_LATE_INIT + select IMX8QXP + config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT @@ -98,6 +103,7 @@ source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" +source "board/toradex/apalis-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" config IMX_SNVS_SEC_SC diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 5dbe1d56e02..4bb7c469215 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/image.h> #include <console.h> +#include <cpu_func.h> DECLARE_GLOBAL_DATA_PTR; @@ -92,7 +93,7 @@ int authenticate_os_container(ulong addr) sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); - debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", + debug("img %d, dst 0x%x, src 0x%lux, size 0x%x\n", i, (uint32_t) img->dst, img->offset + addr, img->size); memcpy((void *)img->dst, (const void *)(img->offset + addr), @@ -106,7 +107,7 @@ int authenticate_os_container(ulong addr) /* Find the memreg and set permission for seco pt */ err = sc_rm_find_memreg(-1, &mr, s, e); if (err) { - printf("Error: can't find memreg for image load address 0x%x, error %d\n", img->dst, err); + printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err); ret = -ENOMEM; goto exit; } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 38b2c0926f5..911d6a51d1e 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -260,14 +260,30 @@ static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, return -EINVAL; } +__weak void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + phys_size_t get_effective_memsize(void) { sc_rm_mr_t mr; sc_faddr_t start, end, end1, start_aligned; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -277,29 +293,35 @@ phys_size_t get_effective_memsize(void) continue; /* Find the memory region runs the U-Boot */ - if (start >= PHYS_SDRAM_1 && start <= end1 && + if (start >= phys_sdram_1_start && start <= end1 && (start <= CONFIG_SYS_TEXT_BASE && end >= CONFIG_SYS_TEXT_BASE)) { - if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + - PHYS_SDRAM_1_SIZE)) - return (end - PHYS_SDRAM_1 + 1); + if ((end + 1) <= + ((sc_faddr_t)phys_sdram_1_start + + phys_sdram_1_size)) + return (end - phys_sdram_1_start + 1); else - return PHYS_SDRAM_1_SIZE; + return phys_sdram_1_size; } } } - return PHYS_SDRAM_1_SIZE; + return phys_sdram_1_size; } int dram_init(void) { sc_rm_mr_t mr; sc_faddr_t start, end, end1, end2; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; - end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -308,12 +330,13 @@ int dram_init(void) if (start > end) continue; - if (start >= PHYS_SDRAM_1 && start <= end1) { + if (start >= phys_sdram_1_start && start <= end1) { if ((end + 1) <= end1) gd->ram_size += end - start + 1; else gd->ram_size += end1 - start; - } else if (start >= PHYS_SDRAM_2 && start <= end2) { + } else if (start >= phys_sdram_2_start && + start <= end2) { if ((end + 1) <= end2) gd->ram_size += end - start + 1; else @@ -324,8 +347,8 @@ int dram_init(void) /* If error, set to the default value */ if (!gd->ram_size) { - gd->ram_size = PHYS_SDRAM_1_SIZE; - gd->ram_size += PHYS_SDRAM_2_SIZE; + gd->ram_size = phys_sdram_1_size; + gd->ram_size += phys_sdram_2_size; } return 0; } @@ -358,11 +381,15 @@ int dram_init_banksize(void) sc_rm_mr_t mr; sc_faddr_t start, end, end1, end2; int i = 0; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; - end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -370,7 +397,7 @@ int dram_init_banksize(void) if (start > end) /* Small memory region, no use it */ continue; - if (start >= PHYS_SDRAM_1 && start <= end1) { + if (start >= phys_sdram_1_start && start <= end1) { gd->bd->bi_dram[i].start = start; if ((end + 1) <= end1) @@ -381,7 +408,7 @@ int dram_init_banksize(void) dram_bank_sort(i); i++; - } else if (start >= PHYS_SDRAM_2 && start <= end2) { + } else if (start >= phys_sdram_2_start && start <= end2) { gd->bd->bi_dram[i].start = start; if ((end + 1) <= end2) @@ -398,10 +425,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[0].start = phys_sdram_1_start; + gd->bd->bi_dram[0].size = phys_sdram_1_size; + gd->bd->bi_dram[1].start = phys_sdram_2_start; + gd->bd->bi_dram[1].size = phys_sdram_2_size; } return 0; @@ -411,11 +438,16 @@ static u64 get_block_attrs(sc_faddr_t addr_start) { u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; + + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); - if ((addr_start >= PHYS_SDRAM_1 && - addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) || - (addr_start >= PHYS_SDRAM_2 && - addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) + if ((addr_start >= phys_sdram_1_start && + addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) || + (addr_start >= phys_sdram_2_start && + addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size))) return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); return attr; @@ -424,14 +456,20 @@ static u64 get_block_attrs(sc_faddr_t addr_start) static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) { sc_faddr_t end1, end2; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; + + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; - end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; - if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) { + if (addr_start >= phys_sdram_1_start && addr_start <= end1) { if ((addr_end + 1) > end1) return end1 - addr_start; - } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) { + } else if (addr_start >= phys_sdram_2_start && addr_start <= end2) { if ((addr_end + 1) > end2) return end2 - addr_start; } diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 9bca5bf9727..5df8e175101 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -210,6 +210,9 @@ int dram_init(void) else gd->ram_size = sdram_size; + /* also update the SDRAM size in the mem_map used externally */ + imx8m_mem_map[5].size = sdram_size; + #ifdef PHYS_SDRAM_2_SIZE gd->ram_size += PHYS_SDRAM_2_SIZE; #endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 0646b7369c2..513d007ce75 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -128,30 +128,8 @@ config TARGET_APALIS_IMX6 imply CMD_DM imply CMD_SATA -config TARGET_ARISTAINETOS2 - bool "aristainetos2" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - -config TARGET_ARISTAINETOS2B - bool "Support aristainetos2-revB" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - -config TARGET_ARISTAINETOS2BCSL - bool "Support aristainetos2-revB CSL" +config TARGET_ARISTAINETOS2C + bool "Support aristainetos2-revC" depends on MX6DL select BOARD_LATE_INIT select SYS_I2C_MXC @@ -161,8 +139,8 @@ config TARGET_ARISTAINETOS2BCSL imply CMD_SATA imply CMD_DM -config TARGET_ARISTAINETOS2C - bool "Support aristainetos2-revC" +config TARGET_ARISTAINETOS2CCSLB + bool "Support aristainetos2-revC CSL" depends on MX6DL select BOARD_LATE_INIT select SYS_I2C_MXC diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index 3abb27e03b4..e61d1adb10f 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -38,6 +38,7 @@ static const struct meson_gx_soc_id { { "G12A", 0x28 }, { "G12B", 0x29 }, { "SM1", 0x2b }, + { "A1", 0x2c }, }; static const struct meson_gx_package_id { @@ -65,7 +66,11 @@ static const struct meson_gx_package_id { { "S905X2", 0x28, 0x40, 0xf0 }, { "A311D", 0x29, 0x10, 0xf0 }, { "S922X", 0x29, 0x40, 0xf0 }, - { "S905X3", 0x2b, 0x5, 0xf }, + { "S905D3", 0x2b, 0x4, 0xf5 }, + { "S905X3", 0x2b, 0x5, 0xf5 }, + { "S905X3", 0x2b, 0x10, 0x3f }, + { "S905D3", 0x2b, 0x30, 0x3f }, + { "A113L", 0x2c, 0x0, 0xf8 }, }; DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0d8e0922a2a..72aee8b3e58 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -30,6 +30,12 @@ config ARMADA_38X select ARMADA_32BIT select HAVE_MVEBU_EFUSE +config ARMADA_38X_HS_IMPEDANCE_THRESH + hex "Armada 38x USB 2.0 High-Speed Impedance Threshold (0x0 - 0x7)" + depends on ARMADA_38X + default 0x6 + range 0x0 0x7 + config ARMADA_XP bool select ARMADA_32BIT diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 2454730e6d8..ae2a3611049 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -677,9 +677,9 @@ struct op_params usb2_power_up_params[] = { {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, /* Change the High speed impedance threshold */ - {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, - {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, - {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc0008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, + {0xc2008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, + {0xc4008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index be3ea3c1a9c..0ef6cf619b4 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -8,6 +8,7 @@ config R8A774A1 config R8A774B1 bool "Renesas SoC R8A774B1" imply CLK_R8A774B1 + imply PINCTRL_PFC_R8A774B1 config R8A774C0 bool "Renesas SoC R8A774C0" @@ -16,6 +17,7 @@ config R8A774C0 config R8A774E1 bool "Renesas SoC R8A774E1" imply CLK_R8A774E1 + imply PINCTRL_PFC_R8A774E1 config R8A7795 bool "Renesas SoC R8A7795" diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 1f12da401c1..0bd8d7b22c4 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 6785ab6b582..1520c6eaed6 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -226,8 +226,8 @@ static void early_enable_caches(void) if (IS_ENABLED(CONFIG_SPL_BUILD)) mmu_set_region_dcache_behaviour( - ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), - round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), + ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), + ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), DCACHE_DEFAULT_OPTION); else mmu_set_region_dcache_behaviour(STM32_DDR_BASE, diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index b679b0a6454..66a634654ee 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -55,6 +55,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION int spl_mmc_boot_partition(const u32 boot_device) { switch (boot_device) { @@ -66,6 +67,7 @@ int spl_mmc_boot_partition(const u32 boot_device) return -EINVAL; } } +#endif #ifdef CONFIG_SPL_DISPLAY_PRINT void spl_display_print(void) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index be0822bfb7d..49ef217f08c 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -253,7 +253,7 @@ config MACH_SUN8I_R40 select PHY_SUN4I_USB config MACH_SUN8I_V3S - bool "sun8i (Allwinner V3s)" + bool "sun8i (Allwinner V3/V3s/S3/S3L)" select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT @@ -363,7 +363,6 @@ choice config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 - depends on !MACH_SUN8I_V3S ---help--- This option is the original only supported memory type, which suits many H3/H5/A64 boards available now. @@ -1010,4 +1009,11 @@ config PINE64_DT_SELECTION option, the device tree selection code specific to Pine64 which utilizes the DRAM size will be enabled. +config PINEPHONE_DT_SELECTION + bool "Enable PinePhone device tree selection code" + depends on MACH_SUN50I + help + Enable this option to automatically select the device tree for the + correct PinePhone hardware revision during boot. + endif diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 6fa31ea0a16..fb016aa46c9 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -19,6 +19,7 @@ config TARGET_JETSON_TK1 config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" + select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT select CPU_V7_HAS_NONSEC if !SPL_BUILD select CPU_V7_HAS_VIRT if !SPL_BUILD diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index c5ba42124b0..b328837c694 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -134,7 +134,8 @@ struct apu_regs { struct csu_regs { u32 reserved0[4]; u32 multi_boot; - u32 reserved1[12]; + u32 reserved1[11]; + u32 idcode; u32 version; }; @@ -149,7 +150,4 @@ struct pmu_regs { #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) -#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 -#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 - #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 96c39b1278b..de5b97e719c 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -9,6 +9,9 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ +PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections + +LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 92826433498..5dc09dbad2d 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -14,7 +14,7 @@ SECTIONS { __text_start = .; arch/microblaze/cpu/start.o (.text) - *(.text) + *(.text*) __text_end = .; } @@ -28,7 +28,7 @@ SECTIONS .data ALIGN(0x4): { __data_start = .; - *(.data) + *(.data*) __data_end = .; } @@ -51,7 +51,7 @@ SECTIONS __bss_start = .; *(.sbss) *(.scommon) - *(.bss) + *(.bss*) *(COMMON) . = ALIGN(4); __bss_end = .; diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index d0c412236dd..335aafa6a8d 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -74,9 +74,14 @@ .endm ENTRY(_start) - /* U-Boot entry point */ + /* + * U-Boot entry point. + * Do not add instructions to the branch delay slot! Some SoC's + * like Octeon might patch the final U-Boot binary at this location + * with additional boot headers. + */ b reset - mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing + nop #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* @@ -123,6 +128,7 @@ ENTRY(_start) #endif reset: + mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing #if __mips_isa_rev >= 6 mfc0 t0, CP0_CONFIG, 5 and t0, t0, MIPS_CONF5_VP diff --git a/arch/mips/mach-octeon/bootoctlinux.c b/arch/mips/mach-octeon/bootoctlinux.c index 75d7e83bd71..26136902f34 100644 --- a/arch/mips/mach-octeon/bootoctlinux.c +++ b/arch/mips/mach-octeon/bootoctlinux.c @@ -9,7 +9,6 @@ #include <dm.h> #include <elf.h> #include <env.h> -#include <ram.h> #include <asm/io.h> #include <linux/compat.h> @@ -370,8 +369,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, struct cvmx_coremask avail_coremask; int first_core; int core; - struct ram_info ram; - struct udevice *dev; const u64 *nmi_code; int num_dwords; u8 node_mask = 0x01; @@ -470,19 +467,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, */ cvmx_coremask_or(&coremask_to_run, &coremask_to_run, &core_mask); - /* Get RAM size */ - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - /* * Load kernel ELF image, or try binary if ELF is not detected. * This way the much smaller vmlinux.bin can also be started but @@ -498,7 +482,7 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, /* Init bootmem list for Linux kernel booting */ if (!cvmx_bootmem_phy_mem_list_init( - ram.size, OCTEON_RESERVED_LOW_MEM_SIZE, + gd->ram_size, OCTEON_RESERVED_LOW_MEM_SIZE, (void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE))) { printf("FATAL: Error initializing free memory list\n"); return 0; @@ -517,7 +501,8 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, if (core == first_core) cvmx_bootinfo_array[core].flags |= BOOT_FLAG_INIT_CORE; - cvmx_bootinfo_array[core].dram_size = ram.size / (1024 * 1024); + cvmx_bootinfo_array[core].dram_size = gd->ram_size / + (1024 * 1024); cvmx_bootinfo_array[core].dclock_hz = gd->mem_clk * 1000000; cvmx_bootinfo_array[core].eclock_hz = gd->cpu_clk; diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 6dc08e19da4..4679260f17a 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -33,7 +33,7 @@ int dram_init(void) return ret; } - gd->ram_size = min_t(size_t, ram.size, UBOOT_RAM_SIZE_MAX); + gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", (unsigned long)ram.base, (unsigned long)ram.size); } else { @@ -72,6 +72,11 @@ void board_add_ram_info(int use_default) } } +phys_size_t get_effective_memsize(void) +{ + return UBOOT_RAM_SIZE_MAX; +} + ulong board_get_usable_ram_top(ulong total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h index 337987178f4..97438ff787a 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h @@ -125,226 +125,4 @@ struct cvmx_bootinfo { #endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ -/* Type defines for board and chip types */ -enum cvmx_board_types_enum { - CVMX_BOARD_TYPE_NULL = 0, - CVMX_BOARD_TYPE_SIM = 1, - CVMX_BOARD_TYPE_EBT3000 = 2, - CVMX_BOARD_TYPE_KODAMA = 3, - CVMX_BOARD_TYPE_NIAGARA = 4, - CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */ - CVMX_BOARD_TYPE_THUNDER = 6, - CVMX_BOARD_TYPE_TRANTOR = 7, - CVMX_BOARD_TYPE_EBH3000 = 8, - CVMX_BOARD_TYPE_EBH3100 = 9, - CVMX_BOARD_TYPE_HIKARI = 10, - CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11, - CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12, - CVMX_BOARD_TYPE_KBP = 13, - /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */ - CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14, - CVMX_BOARD_TYPE_EBT5800 = 15, - CVMX_BOARD_TYPE_NICPRO2 = 16, - CVMX_BOARD_TYPE_EBH5600 = 17, - CVMX_BOARD_TYPE_EBH5601 = 18, - CVMX_BOARD_TYPE_EBH5200 = 19, - CVMX_BOARD_TYPE_BBGW_REF = 20, - CVMX_BOARD_TYPE_NIC_XLE_4G = 21, - CVMX_BOARD_TYPE_EBT5600 = 22, - CVMX_BOARD_TYPE_EBH5201 = 23, - CVMX_BOARD_TYPE_EBT5200 = 24, - CVMX_BOARD_TYPE_CB5600 = 25, - CVMX_BOARD_TYPE_CB5601 = 26, - CVMX_BOARD_TYPE_CB5200 = 27, - /* Special 'generic' board type, supports many boards */ - CVMX_BOARD_TYPE_GENERIC = 28, - CVMX_BOARD_TYPE_EBH5610 = 29, - CVMX_BOARD_TYPE_LANAI2_A = 30, - CVMX_BOARD_TYPE_LANAI2_U = 31, - CVMX_BOARD_TYPE_EBB5600 = 32, - CVMX_BOARD_TYPE_EBB6300 = 33, - CVMX_BOARD_TYPE_NIC_XLE_10G = 34, - CVMX_BOARD_TYPE_LANAI2_G = 35, - CVMX_BOARD_TYPE_EBT5810 = 36, - CVMX_BOARD_TYPE_NIC10E = 37, - CVMX_BOARD_TYPE_EP6300C = 38, - CVMX_BOARD_TYPE_EBB6800 = 39, - CVMX_BOARD_TYPE_NIC4E = 40, - CVMX_BOARD_TYPE_NIC2E = 41, - CVMX_BOARD_TYPE_EBB6600 = 42, - CVMX_BOARD_TYPE_REDWING = 43, - CVMX_BOARD_TYPE_NIC68_4 = 44, - CVMX_BOARD_TYPE_NIC10E_66 = 45, - CVMX_BOARD_TYPE_MAX, - - /* - * The range from CVMX_BOARD_TYPE_MAX to - * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future - * SDK use. - */ - - /* - * Set aside a range for customer boards. These numbers are managed - * by Cavium. - */ - CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, - CVMX_BOARD_TYPE_CUST_WSX16 = 10001, - CVMX_BOARD_TYPE_CUST_NS0216 = 10002, - CVMX_BOARD_TYPE_CUST_NB5 = 10003, - CVMX_BOARD_TYPE_CUST_WMR500 = 10004, - CVMX_BOARD_TYPE_CUST_ITB101 = 10005, - CVMX_BOARD_TYPE_CUST_NTE102 = 10006, - CVMX_BOARD_TYPE_CUST_AGS103 = 10007, - CVMX_BOARD_TYPE_CUST_GST104 = 10008, - CVMX_BOARD_TYPE_CUST_GCT105 = 10009, - CVMX_BOARD_TYPE_CUST_AGS106 = 10010, - CVMX_BOARD_TYPE_CUST_SGM107 = 10011, - CVMX_BOARD_TYPE_CUST_GCT108 = 10012, - CVMX_BOARD_TYPE_CUST_AGS109 = 10013, - CVMX_BOARD_TYPE_CUST_GCT110 = 10014, - CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015, - CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016, - CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017, - CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018, - CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019, - CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020, - CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021, - CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, - - /* - * Set aside a range for customer private use. The SDK won't - * use any numbers in this range. - */ - CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, - CVMX_BOARD_TYPE_UBNT_E100 = 20002, - CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, - CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, - CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, - - /* The remaining range is reserved for future use. */ -}; - -enum cvmx_chip_types_enum { - CVMX_CHIP_TYPE_NULL = 0, - CVMX_CHIP_SIM_TYPE_DEPRECATED = 1, - CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2, - CVMX_CHIP_TYPE_MAX, -}; - -/* - * Compatibility alias for NAC38 name change, planned to be removed - * from SDK 1.7 - */ -#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 - -/* Functions to return string based on type */ -#define ENUM_BRD_TYPE_CASE(x) \ - case x: \ - return(#x + 16) /* Skip CVMX_BOARD_TYPE_ */ - -static inline const char *cvmx_board_type_to_string(enum - cvmx_board_types_enum type) -{ - switch (type) { - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX); - - /* Customer boards listed here */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX); - - /* Customer private range */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX); - } - - return NULL; -} - -#define ENUM_CHIP_TYPE_CASE(x) \ - case x: \ - return(#x + 15) /* Skip CVMX_CHIP_TYPE */ - -static inline const char *cvmx_chip_type_to_string(enum - cvmx_chip_types_enum type) -{ - switch (type) { - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL); - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED); - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE); - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX); - } - - return "Unsupported Chip"; -} - #endif /* __CVMX_BOOTINFO_H__ */ diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootloader.h b/arch/mips/mach-octeon/include/mach/cvmx-bootloader.h new file mode 100644 index 00000000000..9abe0214523 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-bootloader.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +/* + * Bootloader definitions that are shared with other programs + */ + +#ifndef __CVMX_BOOTLOADER__ +#define __CVMX_BOOTLOADER__ + +/* + * The bootloader_header_t structure defines the header that is present + * at the start of binary u-boot images. This header is used to locate + * the bootloader image in NAND, and also to allow verification of images + * for normal NOR booting. This structure is placed at the beginning of a + * bootloader binary image, and remains in the executable code. + */ +#define BOOTLOADER_HEADER_MAGIC 0x424f4f54 /* "BOOT" in ASCII */ + +#define BOOTLOADER_HEADER_COMMENT_LEN 64 +#define BOOTLOADER_HEADER_VERSION_LEN 64 +/* limited by the space to the next exception handler */ +#define BOOTLOADER_HEADER_MAX_SIZE 0x200 + +#define BOOTLOADER_HEADER_CURRENT_MAJOR_REV 1 +#define BOOTLOADER_HEADER_CURRENT_MINOR_REV 2 +/* + * Revision history + * 1.1 Initial released revision. (SDK 1.9) + * 1.2 TLB based relocatable image (SDK 2.0) + */ + +#ifndef __ASSEMBLY__ +struct bootloader_header { + uint32_t jump_instr; /* + * Jump to executable code following the + * header. This allows this header to be + * (and remain) part of the executable image) + */ + uint32_t nop_instr; /* Must be 0x0 */ + uint32_t magic; /* Magic number to identify header */ + uint32_t hcrc; /* CRC of all of header excluding this field */ + + uint16_t hlen; /* Length of header in bytes */ + uint16_t maj_rev; /* Major revision */ + uint16_t min_rev; /* Minor revision */ + uint16_t board_type; /* Board type that the image is for */ + + uint32_t dlen; /* Length of data (following header) in bytes */ + uint32_t dcrc; /* CRC of data */ + uint64_t address; /* Mips virtual address */ + uint32_t flags; + uint16_t image_type; /* Defined in bootloader_image_t enum */ + uint16_t resv0; /* pad */ + + uint32_t reserved1; + uint32_t reserved2; + uint32_t reserved3; + uint32_t reserved4; + + /* Optional, for descriptive purposes */ + char comment_string[BOOTLOADER_HEADER_COMMENT_LEN]; + /* Optional, for descriptive purposes */ + char version_string[BOOTLOADER_HEADER_VERSION_LEN]; +} __packed; + +/* Defines for flag field */ +#define BL_HEADER_FLAG_FAILSAFE 1 + +enum bootloader_image { + BL_HEADER_IMAGE_UNKNOWN = 0x0, + BL_HEADER_IMAGE_STAGE2, /* Binary bootloader stage2 image */ + BL_HEADER_IMAGE_STAGE3, /* Binary bootloader stage3 image */ + BL_HEADER_IMAGE_NOR, /* Binary bootloader for NOR boot */ + BL_HEADER_IMAGE_PCIBOOT, /* Binary bootloader for PCI boot */ + BL_HEADER_IMAGE_UBOOT_ENV, /* Environment for u-boot */ + /* Bootloader before U-Boot (stage 1/1.5) */ + BL_HEADER_IMAGE_PRE_UBOOT, + BL_HEADER_IMAGE_STAGE1, /* NOR stage 1 bootloader */ + BL_HEADER_IMAGE_MAX, + /* Range for customer private use. Will not be used by Cavium Inc. */ + BL_HEADER_IMAGE_CUST_RESERVED_MIN = 0x1000, + BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Maximum address searched for NAND boot images and environments. + * This is used by stage1 and stage2. + */ +#define MAX_NAND_SEARCH_ADDR 0x800000 + +/* Maximum address to look for start of normal bootloader */ +#define MAX_NOR_SEARCH_ADDR 0x400000 + +/* + * Defines for RAM based environment set by the host or the previous + * bootloader in a chain boot configuration. + */ + +#define U_BOOT_RAM_ENV_ADDR 0x1000 +#define U_BOOT_RAM_ENV_SIZE 0x1000 +#define U_BOOT_RAM_ENV_CRC_SIZE 0x4 +#define U_BOOT_RAM_ENV_ADDR_2 (U_BOOT_RAM_ENV_ADDR + U_BOOT_RAM_ENV_SIZE) +/* Address of environment in L2 cache if booted from cache */ +#define U_BOOT_CACHE_ENV_ADDR 0x000ff000 +/* Size of environment in L2 cache */ +#define U_BOOT_CACHE_ENV_SIZE 0x1000 + +/* Board numbers and names */ + +/* Type defines for board and chip types */ +enum cvmx_board_types_enum { + CVMX_BOARD_TYPE_NULL = 0, + CVMX_BOARD_TYPE_SIM = 1, + /* Special 'generic' board type, supports many boards */ + CVMX_BOARD_TYPE_GENERIC = 28, + CVMX_BOARD_TYPE_EBB7304 = 76, + CVMX_BOARD_TYPE_MAX, + /* NOTE: 256-257 are being used by a customer. */ + + /* + * The range from CVMX_BOARD_TYPE_MAX to + * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved + * for future SDK use. + */ + + /* + * Set aside a range for customer boards. These numbers are managed + * by Cavium. + */ + CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, + CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, + + /* + * Set aside a range for customer private use. The SDK won't + * use any numbers in this range. + */ + CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, +}; + +/* Functions to return string based on type */ +/* Skip CVMX_BOARD_TYPE_ */ +#define ENUM_BRD_TYPE_CASE(x) case x: return(#x + 16) + +static inline const char +*cvmx_board_type_to_string(enum cvmx_board_types_enum type) +{ + switch (type) { + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB7304); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX); + + /* Customer boards listed here */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX); + + /* Customer private range */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX); + } + + return "Unsupported Board"; +} + +#endif /* __CVMX_BOOTLOADER__ */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4ca1e2b325f..f25ba1af092 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -116,7 +116,9 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index ac3f183342f..61bd5c426ed 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -35,6 +35,8 @@ config SIFIVE_FU540 imply SIFIVE_OTP imply DM_PWM imply PWM_SIFIVE + imply DM_I2C + imply SYS_I2C_OCORES if ENV_IS_IN_SPI_FLASH diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 5180eb06fcd..6f095c53a57 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -158,7 +158,7 @@ int mtrr_commit(bool do_caches) /* Clear the ones that are unused */ debug("clear\n"); - for (; i < MTRR_MAX_COUNT; i++) + for (; i < mtrr_get_var_count(); i++) wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); debug("close\n"); mtrr_close(&state, do_caches); diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 43f4b33da1b..d66e128ae62 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -55,12 +55,27 @@ write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; smbios { - manufacturer = "Google"; - product = "Coral"; - version = "rev2"; - serial = "123456789"; - sku = "sku3"; - family = "Google_Coral"; + /* Type 1 table */ + system { + manufacturer = "Google"; + product = "Coral"; + version = "rev2"; + serial = "123456789"; + sku = "sku3"; + family = "Google_Coral"; + }; + + /* Type 2 table */ + baseboard { + manufacturer = "Google"; + product = "Coral"; + asset-tag = "ABC123"; + }; + + /* Type 3 table */ + chassis { + manufacturer = "Google"; + }; }; }; diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 73d69e03880..f67b04b78cc 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -8,6 +8,7 @@ #include <env.h> #include <i2c.h> #include <init.h> +#include <mmc.h> #include <phy.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -83,6 +84,7 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { + struct mmc *mmc_dev; bool ddr4, emmc; if (env_get("fdtfile")) @@ -95,7 +97,9 @@ int board_late_init(void) ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS) & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4; - emmc = of_machine_is_compatible("globalscale,espressobin-emmc"); + /* eMMC is mmc dev num 1 */ + mmc_dev = find_mmc_device(1); + emmc = (mmc_dev && mmc_init(mmc_dev) == 0); if (ddr4 && emmc) env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb"); diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS index 15660cd17d4..55e485faa96 100644 --- a/board/Marvell/mvebu_armada-8k/MAINTAINERS +++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS @@ -13,6 +13,7 @@ F: configs/mvebu_mcbin-88f8040_defconfig Puzzle-M801 BOARD M: Luka Kovacic <luka.kovacic@sartura.hr> +M: Luka Perkov <luka.perkov@sartura.hr> S: Maintained F: configs/mvebu_puzzle-m801-88f8040_defconfig F: arch/arm/dts/armada-8040-puzzle-m801.dts diff --git a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS index b142ee02e62..58a4d253c3e 100644 --- a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS +++ b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS @@ -2,5 +2,6 @@ i.MX8QM ROM 7720 a1 BOARD M: Oliver Graute <oliver.graute@kococonnector.com> S: Maintained F: board/advantech/imx8qm_rom7720_a1/ +F: arch/arm/dts/imx8qm-rom7720-a1.dts F: include/configs/imx8qm_rom7720.h F: configs/imx8qm_rom7720_a1_4G_defconfig diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README deleted file mode 100644 index 585fde440d4..00000000000 --- a/board/advantech/imx8qm_rom7720_a1/README +++ /dev/null @@ -1,61 +0,0 @@ -U-Boot for the NXP i.MX8QM ROM 7720a1 board - -Quick Start -=========== - -- Build the ARM Trusted firmware binary -- Get scfw_tcm.bin and ahab-container.img -- Get imx-mkimage -- Build U-Boot -- Build imx-mkimage -- Flash the binary into the SD card -- Boot - -Get and Build the ARM Trusted firmware -====================================== - -$ git clone https://source.codeaurora.org/external/imx/imx-atf -$ cd imx-atf/ -$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga -$ make PLAT=imx8qm bl31 - -Get scfw_tcm.bin and ahab-container.img -============================== - -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin -$ chmod +x imx-sc-firmware-1.1.bin -$ ./imx-sc-firmware-1.1.bin -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin -$ chmod +x firmware-imx-8.0.bin -$ ./firmware-imx-8.0.bin - -Or use this to avoid running random scripts from the internet, -but note that you must agree to the license the script displays: - -$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 -$ tar -xf imx-sc-firmware-1.1.tar.bz2 -$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) - -$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 -$ tar -xf firmware-imx-8.0.tar.bz2 -$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) - -Build U-Boot -============ - -$ export ATF_LOAD_ADDR=0x80000000 -$ export BL33_LOAD_ADDR=0x80020000 -$ make imx8qm_rom7720_a1_4G_defconfig -$ make u-boot.bin -$ make flash.bin - -Flash the binary into the SD card -================================= - -Burn the flash.bin binary to SD card offset 32KB: - -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync - -Boot -==== -Set Boot switch SW2: 1100. diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2ad3dbd56cb..cc603c1bc2d 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,28 +1,4 @@ -if TARGET_ARISTAINETOS2 - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 2 - -endif - -if TARGET_ARISTAINETOS2B - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 3 - -endif - -if TARGET_ARISTAINETOS2BCSL +if TARGET_ARISTAINETOS2C source "board/aristainetos/common/Kconfig" @@ -30,11 +6,11 @@ config SYS_BOARD default "aristainetos" config SYS_BOARD_VERSION - default 4 + default 5 endif -if TARGET_ARISTAINETOS2C +if TARGET_ARISTAINETOS2CCSLB source "board/aristainetos/common/Kconfig" @@ -42,6 +18,6 @@ config SYS_BOARD default "aristainetos" config SYS_BOARD_VERSION - default 5 + default 6 endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index b4ca7abb9c6..c81bef9cb7c 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -3,34 +3,16 @@ M: Heiko Schocher <hs@denx.de> S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h -F: configs/aristainetos2_defconfig -F: configs/aristainetos2b_defconfig -F: configs/aristainetos2bcsl_defconfig F: configs/aristainetos2c_defconfig -F: arch/arm/dts/imx6qdl-aristainetos2.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_7.dts -F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_4.dts -F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_4.dts -F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_7.dts -F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts -F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts -F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2c_4.dts -F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi +F: configs/aristainetos2ccslb_defconfig F: arch/arm/dts/imx6dl-aristainetos2c_7.dts F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts +F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 14931120f6f..07d2e3ec7bb 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -27,6 +27,7 @@ #include <bmp_logo.h> #include <dm/root.h> #include <env.h> +#include <env_internal.h> #include <i2c_eeprom.h> #include <i2c.h> #include <micrel.h> @@ -194,87 +195,6 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[3]); } -static void enable_spi_display(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - -#if defined(CONFIG_VIDEO_BMP_LOGO) - rotate_logo(3); /* portrait display in landscape mode */ -#endif - - reg = readl(&ccm->cs2cdr); - - /* select pll 5 clock */ - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - writel(reg, &ccm->cs2cdr); - - /* set PLL5 to 197994996Hz */ - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), - &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), - &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &ccm->cs2cdr); - - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} - static void setup_display(void) { enable_ipu_clock(); @@ -331,25 +251,36 @@ static void setup_board_gpio(void) setup_one_led("led_blue", LEDST_OFF); } -#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \ - " rescueReason=%d " - static void aristainetos_run_rescue_command(int reason) { - char rescue_reason_command[80]; + char rescue_reason_command[20]; - sprintf(rescue_reason_command, ARI_RESC_FMT, reason); + sprintf(rescue_reason_command, "setenv rreason %d", reason); run_command(rescue_reason_command, 0); } -static int aristainetos_eeprom(void) +static int aristainetos_bootmode_settings(void) { + struct gpio_desc *desc; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int sbmr1 = readl(&psrc->sbmr1); + char *my_bootdelay; + char bootmode = 0; + int ret; struct udevice *dev; int off; - int ret; u8 data[0x10]; u8 rescue_reason; + /* jumper controlled reset of the environment */ + ret = gpio_hog_lookup_name("env_reset", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + printf("\nReset u-boot environment (jumper)\n"); + run_command("run default_env; saveenv; saveenv", 0); + } + } + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); if (off < 0) { printf("%s: No eeprom0 path offset\n", __func__); @@ -366,37 +297,26 @@ static int aristainetos_eeprom(void) if (ret) return ret; - ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6); + ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data)); if (ret) { printf("%s: Could not read EEPROM\n", __func__); return ret; } - if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { - rescue_reason = *(uint8_t *)&data[9]; - memset(&data[3], 0xff, 7); - i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); - printf("\nBooting into Rescue System (EEPROM)\n"); - aristainetos_run_rescue_command(rescue_reason); - run_command("run rescue_load_fit rescueboot", 0); - } else if (strncmp((char *)data, "DeF", 3) == 0) { + /* software controlled reset of the environment (EEPROM magic) */ + if (strncmp((char *)data, "DeF", 3) == 0) { memset(data, 0xff, 3); i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3); - printf("\nClear u-boot environment (set back to defaults)\n"); + printf("\nReset u-boot environment (EEPROM)\n"); run_command("run default_env; saveenv; saveenv", 0); } - return 0; -}; - -static void aristainetos_bootmode_settings(void) -{ - struct gpio_desc *desc; - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned int sbmr1 = readl(&psrc->sbmr1); - char *my_bootdelay; - char bootmode = 0; - int ret; + if (sbmr1 & 0x40) { + env_set("bootmode", "1"); + printf("SD bootmode jumper set!\n"); + } else { + env_set("bootmode", "0"); + } /* * Check the boot-source. If booting from NOR Flash, @@ -420,28 +340,27 @@ static void aristainetos_bootmode_settings(void) env_set("bootdelay", "-2"); } - if (sbmr1 & 0x40) { - env_set("bootmode", "1"); - printf("SD bootmode jumper set!\n"); - } else { - env_set("bootmode", "0"); - } - - /* read out some jumper values*/ - ret = gpio_hog_lookup_name("env_reset", &desc); - if (!ret) { - if (dm_gpio_get_value(desc)) { - printf("\nClear env (set back to defaults)\n"); - run_command("run default_env; saveenv; saveenv", 0); - } - } + /* jumper controlled boot of the rescue system */ ret = gpio_hog_lookup_name("boot_rescue", &desc); if (!ret) { if (dm_gpio_get_value(desc)) { + printf("\nBooting into Rescue System (jumper)\n"); aristainetos_run_rescue_command(16); run_command("run rescue_xload_boot", 0); } } + + /* software controlled boot of the rescue system (EEPROM magic) */ + if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { + rescue_reason = *(uint8_t *)&data[9]; + memset(&data[3], 0xff, 7); + i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); + printf("\nBooting into Rescue System (EEPROM)\n"); + aristainetos_run_rescue_command(rescue_reason); + run_command("run rescue_xload_boot", 0); + } + + return 0; } #if defined(CONFIG_DM_PMIC_DA9063) @@ -497,15 +416,15 @@ static int setup_pmic_voltages(void) int board_late_init(void) { int x, y; + int ret; led_default_state(); splash_get_pos(&x, &y); bmp_display((ulong)&bmp_logo_bitmap[0], x, y); - aristainetos_bootmode_settings(); - - /* eeprom work */ - aristainetos_eeprom(); + ret = aristainetos_bootmode_settings(); + if (ret) + return ret; /* set board_type */ if (gd->board_type == BOARD_TYPE_4) @@ -549,97 +468,9 @@ struct display_info_t const displays[] = { .vmode = FB_VMODE_NONINTERLACED } } -#if ((CONFIG_SYS_BOARD_VERSION == 2) || \ - (CONFIG_SYS_BOARD_VERSION == 3) || \ - (CONFIG_SYS_BOARD_VERSION == 4) || \ - (CONFIG_SYS_BOARD_VERSION == 5)) - , { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = NULL, - .enable = enable_spi_display, - .mode = { - .name = "lg4573", - .refresh = 57, - .xres = 480, - .yres = 800, - .pixclock = 37037, - .left_margin = 59, - .right_margin = 10, - .upper_margin = 15, - .lower_margin = 15, - .hsync_len = 10, - .vsync_len = 15, - .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED - } - } -#endif }; size_t display_count = ARRAY_SIZE(displays); -#if defined(CONFIG_MTD_RAW_NAND) -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, - ARRAY_SIZE(nfc_pads)); - - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#else -static void setup_gpmi_nand(void) -{ -} -#endif - int board_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -648,7 +479,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; setup_board_gpio(); - setup_gpmi_nand(); setup_display(); /* GPIO_1 for USB_OTG_ID */ @@ -698,3 +528,22 @@ int embedded_dtb_select(void) return 0; } #endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_SPI_FLASH; + + switch (prio) { + case 0: + return ENVL_NOWHERE; + + case 1: + return ENVL_SPI_FLASH; + + default: + return ENVL_UNKNOWN; + } + + return ENVL_UNKNOWN; +} diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index e26de5144d6..328243c2f9a 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -2,10 +2,8 @@ config SYS_BOARD_VERSION int "select version of aristainetos board" help version of aristainetos board version - 2 version 2 - 3 version 2b - 4 version 2bcsl - 5 version 2c + 5 version 2c and 2d + 6 version 2c-cslb config SYS_I2C_MXC_I2C1 default y diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 70f6cd80d5a..8fea8ff3529 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -55,7 +55,6 @@ int board_init(void) { gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; - gd->flags = 0; icache_enable(); flash__init(); diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its index 905be57dffd..ba48786e08d 100644 --- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its +++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its @@ -31,6 +31,14 @@ arch = "arm"; compression = "none"; }; + + fdt-3 { + description = ".dtb"; + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + }; }; configurations { @@ -64,6 +72,20 @@ fdt = "fdt-2"; }; + config-5 { + /* DT+SoM+board model */ + description = "dh,stm32mp15xx-dhcom-picoitx_somrev0_boardrev0"; + loadables = "uboot"; + fdt = "fdt-3"; + }; + + config-6 { + /* DT+SoM+board model */ + description = "dh,stm32mp15xx-dhcom-picoitx_somrev1_boardrev0"; + loadables = "uboot"; + fdt = "fdt-3"; + }; + /* Add 587-100..587-400 with fdt-2..fdt-4 here */ }; }; diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 617c4aa33ff..0818048ba64 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -29,33 +29,40 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV select SUPPORT_SPL - imply SYS_NS16550 - imply VIRTIO_MMIO - imply VIRTIO_NET - imply VIRTIO_BLK - imply VIRTIO_PCI + imply AHCI + imply SMP + imply BOARD_LATE_INIT + imply PCI_INIT_R + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE + imply CMD_PCI + imply CMD_POWEROFF + imply CMD_SCSI imply CMD_PING - imply CMD_FS_GENERIC - imply DOS_PARTITION - imply EFI_PARTITION - imply ISO_PARTITION imply CMD_EXT2 imply CMD_EXT4 imply CMD_FAT - imply BOARD_LATE_INIT - imply SIFIVE_SERIAL - imply SMP + imply CMD_FS_GENERIC + imply DOS_PARTITION + imply ISO_PARTITION + imply EFI_PARTITION + imply SCSI_AHCI + imply AHCI_PCI + imply E1000 + imply NVME imply PCI imply DM_PCI imply PCIE_ECAM_GENERIC - imply CMD_PCI - imply E1000 - imply NVME - imply SPL_RAM_SUPPORT - imply SPL_RAM_DEVICE + imply SCSI + imply DM_SCSI + imply SYS_NS16550 + imply SIFIVE_SERIAL imply SYSRESET - imply SYSRESET_SYSCON - imply CMD_POWEROFF imply SYSRESET_CMD_POWEROFF + imply SYSRESET_SYSCON + imply VIRTIO_MMIO + imply VIRTIO_PCI + imply VIRTIO_NET + imply VIRTIO_BLK endif diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 93638d24524..0860bd23126 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -141,4 +141,29 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_EVDD_BY_SDHC_VS 0x0c +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC +#define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 +#define NON_EXTENDED_DUTCFG +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 +#endif + #endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 728245d81cd..33ae4c15ba7 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -175,9 +175,11 @@ static int read_eeprom(void) struct udevice *dev; #ifdef CONFIG_SYS_EEPROM_BUS_NUM ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); #else - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); #endif if (!ret) ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 9c51f502608..2617f61520b 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include <common.h> @@ -484,10 +485,10 @@ int adjust_vdd(ulong vdd_override) u8 vid; #endif int vdd_target, vdd_current, vdd_last; - int ret, i2caddress; + int ret, i2caddress = 0; unsigned long vdd_string_override; char *vdd_string; -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) static const u16 vdd[32] = { 8250, 7875, diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 65b348ee42f..5bbaecace4e 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __VID_H_ @@ -37,6 +38,35 @@ */ #define EN_WRITE_ALL_CMD (0) +#ifdef CONFIG_TARGET_LX2160ARDB +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 925 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +/* PM Bus commands code for LTC3882*/ +#define PWM_CHANNEL0 0x0 +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_MUX_CH_VOL_MONITOR 0xA +#endif + int adjust_vdd(ulong vdd_override); #endif /* __VID_H_ */ diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 8112c12568d..6500c2fcf67 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: @@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 650013bb6fc..df5a69bcba3 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, @@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index 35daa1e80f3..de7b692f3fe 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the @@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index 55b414e1689..4ac69d71174 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -16,6 +16,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40400000 @@ -65,6 +69,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40020000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40060000 @@ -77,6 +85,9 @@ config SYS_LS_PFE_ESBC_ADDR hex "PFE Firmware HDR Addr" default 0x401f8000 +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index 8844557aae4..59b1a876655 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -20,6 +20,14 @@ if CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR hex "PPA Firmware HDR Addr" default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if FSL_PFE @@ -39,9 +47,9 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40700000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 5a2fa91f6be..c4acea3ae2d 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -20,6 +20,14 @@ if CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR hex "PPA Firmware HDR Addr" default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40640000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if FSL_PFE @@ -33,9 +41,9 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40640000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" @@ -89,6 +97,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 95412df1d7b..c3efe8a0be6 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -479,6 +479,8 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 8f5f95e3968..33db552adb8 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -409,6 +409,8 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig index 122a385100a..7556f7dd215 100644 --- a/board/freescale/lx2160a/Kconfig +++ b/board/freescale/lx2160a/Kconfig @@ -32,3 +32,19 @@ config SYS_CONFIG_NAME source "board/freescale/common/Kconfig" endif +if TARGET_LX2162AQDS + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2162aqds" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index 9fe79c0ef7a..c627417cf72 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -1,4 +1,5 @@ LX2160ARDB BOARD +M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> M: Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/lx2160a/ @@ -14,6 +15,7 @@ S: Maintained F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig LX2160AQDS BOARD +M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> M: Pankaj Bansal <pankaj.bansal@nxp.com> S: Maintained F: board/freescale/lx2160a/eth_lx2160aqds.h @@ -25,3 +27,27 @@ LX2160AQDS_SECURE_BOOT BOARD M: Udit Agarwal <udit.agarwal@nxp.com> S: Maintained F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS BOARD +M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> +S: Maintained +F: board/freescale/lx2160a/eth_lx2162aqds.h +F: include/configs/lx2162aqds.h +F: configs/lx2162aqds_tfa_defconfig +F: arch/arm/dts/fsl-lx2162a-qds.dts +F: arch/arm/dts/fsl-lx2162a-qds-17-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-18-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-20-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi + +LX2162AQDS_SECURE_BOOT BOARD +M: Manish Tomar <Manish.Tomar@nxp.com> +S: Maintained +F: configs/lx2162aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS_VERIFIED_BOOT BOARD +M: Manish Tomar <Manish.Tomar@nxp.com> +S: Maintained +F: configs/lx2162aqds_tfa_verified_boot_defconfig diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile index d1a621b6821..c9561bfadea 100644 --- a/board/freescale/lx2160a/Makefile +++ b/board/freescale/lx2160a/Makefile @@ -8,3 +8,4 @@ obj-y += lx2160a.o obj-y += ddr.o obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o +obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README index 62fb9eab151..7bca98dd3d7 100644 --- a/board/freescale/lx2160a/README +++ b/board/freescale/lx2160a/README @@ -195,3 +195,135 @@ SERDES3 |CARDS |Connect I/O cable to IO_SLOT6(J125) ------------------------------------------------------------------------- +LX2162A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2162AQDS board Overview +---------------------- +DDR Memory + One ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 2.9 GT/s. + +SERDES ports + Two serdes controllers (12 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector, + four SATA 3.0 connectors + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + One high speed USB 3.0 ports. First USB 3.0 port configured as Host + with Type-A connector, second USB 3.0 port configured as OTG with + micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot +c) eMMC boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd/eMMC card +---------------------------- +Image SD/eMMC card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 + +Various Mezzanine cards and their connection for different SERDES protocols is +as below: + +SERDES1 |CARDS +----------------------------------------------------------------------- +1 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +3 |Mezzanine:X-M11-USXGMII (29828) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +15 |Mezzanine:X-M8-50G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +17 |Mezzanine:X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) +------------------------------------------------------------------------ +20 |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J108) +------------------------------------------------------------------------ + + +SERDES2 |CARDS +----------------------------------------------------------------------- +2 |Mezzanine:X-M6-PCIE-X8 (29737) * + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT3(J116) +------------------------------------------------------------------------ +3 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +5 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M5-SATA (29687) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +11 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT7(J127) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT8(J131) +------------------------------------------------------------------------ diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index b448883ee14..b3125b7748d 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -19,6 +19,7 @@ #include <asm/arch/fsl_serdes.h> #include <fsl-mc/fsl_mc.h> #include <fsl-mc/ldpaa_wriop.h> +#include "lx2160a.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c new file mode 100644 index 00000000000..4683f674f0e --- /dev/null +++ b/board/freescale/lx2160a/eth_lx2162aqds.c @@ -0,0 +1,974 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include <common.h> +#include <env.h> +#include <fdt_support.h> +#include <hwconfig.h> +#include <command.h> +#include <log.h> +#include <net.h> +#include <netdev.h> +#include <malloc.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <exports.h> +#include <asm/arch/fsl_serdes.h> +#include <fsl-mc/fsl_mc.h> +#include <fsl-mc/ldpaa_wriop.h> +#include <linux/libfdt.h> + +#include "../common/qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_ETH +#define EMI_NONE 0 +#define EMI1 1 /* Mdio Bus 1 */ +#define EMI2 2 /* Mdio Bus 2 */ + +#if defined(CONFIG_FSL_MC_ENET) +enum io_slot { + IO_SLOT_NONE = 0, + IO_SLOT_1, + IO_SLOT_2, + IO_SLOT_3, + IO_SLOT_4, + IO_SLOT_5, + IO_SLOT_6, + IO_SLOT_7, + IO_SLOT_8, + EMI1_RGMII1, + EMI1_RGMII2, + IO_SLOT_MAX +}; + +struct lx2162a_qds_mdio { + enum io_slot ioslot : 4; + u8 realbusnum : 4; + struct mii_dev *realbus; +}; + +/* structure explaining the phy configuration on 8 lanes of a serdes*/ +struct serdes_phy_config { + u8 serdes; /* serdes protocol */ + struct phy_config { + u8 dpmacid; + /* -1 terminated array */ + int phy_address[WRIOP_MAX_PHY_NUM + 1]; + u8 mdio_bus; + enum io_slot ioslot; + } phy_config[SRDS_MAX_LANES]; +}; + +/* Table defining the phy configuration on 8 lanes of a serdes. + * Various assumptions have been made while defining this table. + * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII + * card is being used for dpmac 3-4. (X-M12-XFI could also have been used) + * And also that this card is connected to IO Slot 1 (could have been connected + * to any of the 8 IO slots (IO slot 1 - IO slot 8)). + * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card + * used in serdes1 protocol 19 (could have selected MDIO 2) + * To override these settings "dpmac" environment variable can be used after + * defining "dpmac_override" in hwconfig environment variable. + * This table has limited serdes protocol entries. It can be expanded as per + * requirement. + */ +/***************************************************************** + *| SERDES_1 PROTOCOL | IO_SLOT | CARD | + ****************************************************************** + *| 2 | IO_SLOT_1 | M4-PCIE-SGMII | + *| 3 | IO_SLOT_1 | M11-USXGMII | + *| 15 | IO_SLOT_1 | M13-25G | + *| 17 | IO_SLOT_1 | M13-25G | + *| 18 | IO_SLOT_1 | M11-USXGMII | + *| | IO_SLOT_6 | M13-25G | + *| 20 | IO_SLOT_1 | M7-40G | + ***************************************************************** + */ +static const struct serdes_phy_config serdes1_phy_config[] = { + {1, {} }, + {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_1} } }, + {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1}, + EMI1, IO_SLOT_1} } }, + {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1} } }, + {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1} } }, + {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_6}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_6} } }, + {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1} } } +}; + +/***************************************************************** + *| SERDES_2 PROTOCOL | IO_SLOT | CARD | + ****************************************************************** + *| 2 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 3 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 5 | IO_SLOT_7 | M4-PCIE-SGMII | + *| 10 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 11 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 12 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + ****************************************************************** + */ +static const struct serdes_phy_config serdes2_phy_config[] = { + {2, {} }, + {3, {} }, + {5, {} }, + {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } }, + {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_8}, + {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_8}, + {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_8} } }, + {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } } +}; + +static inline +const struct phy_config *get_phy_config(u8 serdes, + const struct serdes_phy_config *table, + u8 table_size) +{ + int i; + + for (i = 0; i < table_size; i++) { + if (table[i].serdes == serdes) + return table[i].phy_config; + } + + return NULL; +} + +/* BRDCFG4 controls EMI routing for the board. + * Bits Function + * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V): + * EMI1 00= On-board PHY #1 + * 01= On-board PHY #2 + * 10= (reserved) + * 11= Slots 1..8 multiplexer and translator. + * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V): + * EMI1X 000= Slot #1 + * 001= Slot #2 + * 010= Slot #3 + * 011= Slot #4 + * 100= Slot #5 + * 101= Slot #6 + * 110= Slot #7 + * 111= Slot #8 + * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2): + * EMI2 000= Slot #1 (secondary EMI) + * 001= Slot #2 (secondary EMI) + * 010= Slot #3 (secondary EMI) + * 011= Slot #4 (secondary EMI) + * 100= Slot #5 (secondary EMI) + * 101= Slot #6 (secondary EMI) + * 110= Slot #7 (secondary EMI) + * 111= Slot #8 (secondary EMI) + */ +static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot) +{ + switch (realbusnum) { + case EMI1: + switch (ioslot) { + case EMI1_RGMII1: + return 0; + case EMI1_RGMII2: + return 0x40; + default: + return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0); + } + break; + case EMI2: + return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT); + default: + return -1; + } +} + +static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv) +{ + u8 brdcfg4, mux_val, reg; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + reg = brdcfg4; + mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + + switch (priv->realbusnum) { + case EMI1: + brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK; + brdcfg4 |= mux_val; + break; + case EMI2: + brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK; + brdcfg4 |= mux_val; + break; + } + + if (brdcfg4 ^ reg) + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr, + int devad, int regnum) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + lx2162a_qds_mux_mdio(priv); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + lx2162a_qds_mux_mdio(priv); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int lx2162a_qds_mdio_reset(struct mii_dev *bus) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot) +{ + struct lx2162a_qds_mdio *pmdio; + struct mii_dev *bus; + /*should be within MDIO_NAME_LEN*/ + char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1"; + + if (realbusnum == EMI2) { + if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) { + printf("invalid ioslot %d\n", ioslot); + return NULL; + } + } else if (realbusnum == EMI1) { + if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) { + printf("invalid ioslot %d\n", ioslot); + return NULL; + } + } else { + printf("not supported real mdio bus %d\n", realbusnum); + return NULL; + } + + if (ioslot == EMI1_RGMII1) + strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1"); + else if (ioslot == EMI1_RGMII2) + strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2"); + else + sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d", + realbusnum, ioslot); + bus = miiphy_get_dev_by_name(dummy_mdio_name); + + if (bus) + return bus; + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate %s bus\n", dummy_mdio_name); + return NULL; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate %s private data\n", dummy_mdio_name); + free(bus); + return NULL; + } + + switch (realbusnum) { + case EMI1: + pmdio->realbus = + miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + break; + case EMI2: + pmdio->realbus = + miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + break; + } + + if (!pmdio->realbus) { + printf("No real mdio bus num %d found\n", realbusnum); + free(bus); + free(pmdio); + return NULL; + } + + pmdio->realbusnum = realbusnum; + pmdio->ioslot = ioslot; + bus->read = lx2162a_qds_mdio_read; + bus->write = lx2162a_qds_mdio_write; + bus->reset = lx2162a_qds_mdio_reset; + strcpy(bus->name, dummy_mdio_name); + bus->priv = pmdio; + + if (!mdio_register(bus)) + return bus; + + printf("No bus with name %s\n", dummy_mdio_name); + free(bus); + free(pmdio); + return NULL; +} + +static inline void do_phy_config(const struct phy_config *phy_config) +{ + struct mii_dev *bus; + int i, phy_num, phy_address; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (!phy_config[i].dpmacid) + continue; + + for (phy_num = 0; + phy_num < ARRAY_SIZE(phy_config[i].phy_address); + phy_num++) { + phy_address = phy_config[i].phy_address[phy_num]; + if (phy_address == -1) + break; + wriop_set_phy_address(phy_config[i].dpmacid, + phy_num, phy_address); + } + /*Register the muxing front-ends to the MDIO buses*/ + bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus, + phy_config[i].ioslot); + if (!bus) + printf("could not get bus for mdio %d ioslot %d\n", + phy_config[i].mdio_bus, + phy_config[i].ioslot); + else + wriop_set_mdio(phy_config[i].dpmacid, bus); + } +} + +static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, + char *env_dpmac) +{ + const char *ret; + size_t len; + u8 realbusnum, ioslot; + struct mii_dev *bus; + int phy_num; + char *phystr = "phy00"; + + /*search phy in dpmac arg*/ + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { + sprintf(phystr, "phy%d", phy_num + 1); + ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac); + if (!ret) { + /*look for phy instead of phy1*/ + if (!phy_num) + ret = hwconfig_subarg_f(arg_dpmacid, "phy", + &len, env_dpmac); + if (!ret) + continue; + } + + if (len != 4 || strncmp(ret, "0x", 2)) + printf("invalid phy format in %s variable.\n" + "specify phy%d for %s in hex format e.g. 0x12\n", + env_dpmac, phy_num + 1, arg_dpmacid); + else + wriop_set_phy_address(dpmac, phy_num, + simple_strtoul(ret, NULL, 16)); + } + + /*search mdio in dpmac arg*/ + ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac); + if (ret) + realbusnum = *ret - '0'; + else + realbusnum = EMI_NONE; + + if (realbusnum) { + /*search io in dpmac arg*/ + ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac); + if (ret) + ioslot = *ret - '0'; + else + ioslot = IO_SLOT_NONE; + /*Register the muxing front-ends to the MDIO buses*/ + bus = lx2162a_qds_mdio_init(realbusnum, ioslot); + if (!bus) + printf("could not get bus for mdio %d ioslot %d\n", + realbusnum, ioslot); + else + wriop_set_mdio(dpmac, bus); + } +} + +#endif +#endif /* !CONFIG_DM_ETH */ + +int board_eth_init(struct bd_info *bis) +{ +#ifndef CONFIG_DM_ETH +#if defined(CONFIG_FSL_MC_ENET) + struct memac_mdio_info mdio_info; + struct memac_mdio_controller *regs; + int i; + const char *ret; + char *env_dpmac; + char dpmacid[] = "dpmac00", srds[] = "00_00_00"; + size_t len; + struct mii_dev *bus; + const struct phy_config *phy_config; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1, srds_s2; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + sprintf(srds, "%d_%d", srds_s1, srds_s2); + + regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = regs; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /*Register the EMI 1*/ + fm_memac_mdio_init(bis, &mdio_info); + + regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = regs; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /*Register the EMI 2*/ + fm_memac_mdio_init(bis, &mdio_info); + + /* "dpmac" environment variable can be used after + * defining "dpmac_override" in hwconfig environment variable. + */ + if (hwconfig("dpmac_override")) { + env_dpmac = env_get("dpmac"); + if (env_dpmac) { + ret = hwconfig_arg_f("srds", &len, env_dpmac); + if (ret) { + if (strncmp(ret, srds, strlen(srds))) { + printf("SERDES configuration changed.\n" + "previous: %.*s, current: %s.\n" + "update dpmac variable.\n", + (int)len, ret, srds); + } + } else { + printf("SERDES configuration not found.\n" + "Please add srds:%s in dpmac variable\n", + srds); + } + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + /* Look for dpmac1 to dpmac24(current max) arg + * in dpmac environment variable + */ + sprintf(dpmacid, "dpmac%d", i); + ret = hwconfig_arg_f(dpmacid, &len, env_dpmac); + if (ret) + do_dpmac_config(i, dpmacid, env_dpmac); + } + } else { + printf("Warning: environment dpmac not found.\n" + "DPAA network interfaces may not work\n"); + } + } else { + /*Look for phy config for serdes1 in phy config table*/ + phy_config = get_phy_config(srds_s1, serdes1_phy_config, + ARRAY_SIZE(serdes1_phy_config)); + if (!phy_config) { + printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n", + __func__, srds_s1); + } else { + do_phy_config(phy_config); + } + phy_config = get_phy_config(srds_s2, serdes2_phy_config, + ARRAY_SIZE(serdes2_phy_config)); + if (!phy_config) { + printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n", + __func__, srds_s2); + } else { + do_phy_config(phy_config); + } + } + + if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) { + wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1); + bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1); + if (!bus) + printf("could not get bus for RGMII1\n"); + else + wriop_set_mdio(WRIOP1_DPMAC17, bus); + } + + if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) { + wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2); + bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2); + if (!bus) + printf("could not get bus for RGMII2\n"); + else + wriop_set_mdio(WRIOP1_DPMAC18, bus); + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + +#ifdef CONFIG_DM_ETH + return 0; +#else + return pci_eth_init(bis); +#endif +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +#ifndef CONFIG_DM_ETH +#if defined(CONFIG_FSL_MC_ENET) +int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) +{ + int offset; + int ret; + char dpmac_str[] = "dpmacs@00"; + const char *phy_string; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (offset < 0) { + printf("dpmacs node not found in device tree\n"); + return offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + debug("dpmac_str = %s\n", dpmac_str); + + offset = fdt_subnode_offset(fdt, offset, dpmac_str); + if (offset < 0) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL); + if (is_backplane_mode(phy_string)) { + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", dpmac_id); + return 0; + } + + ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle); + if (ret) + printf("%d@%s %d\n", __LINE__, __func__, ret); + + phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id)); + ret = fdt_setprop_string(fdt, offset, "phy-connection-type", + phy_string); + if (ret) + printf("%d@%s %d\n", __LINE__, __func__, ret); + + return ret; +} + +int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) +{ + char mdio_ioslot_str[] = "mdio@00"; + struct lx2162a_qds_mdio *priv; + u64 reg; + u32 phandle; + int offset, mux_val; + + /*Test if the MDIO bus is real mdio bus or muxing front end ?*/ + if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO", + strlen("LX2162A_QDS_MDIO"))) + return -1; + + /*Get the real MDIO bus num and ioslot info from bus's priv data*/ + priv = mii_dev->priv; + + debug("real_bus_num = %d, ioslot = %d\n", + priv->realbusnum, priv->ioslot); + + if (priv->realbusnum == EMI1) + reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + else + reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + + offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); + if (offset < 0) { + printf("mdio@%llx node not found in device tree\n", reg); + return offset; + } + + phandle = fdt_get_phandle(fdt, offset); + phandle = cpu_to_fdt32(phandle); + offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus", + &phandle, 4); + if (offset < 0) { + printf("mdio-mux-%d node not found in device tree\n", + priv->realbusnum == EMI1 ? 1 : 2); + return offset; + } + + mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + if (priv->realbusnum == EMI1) + mux_val >>= BRDCFG4_EMI1SEL_SHIFT; + else + mux_val >>= BRDCFG4_EMI2SEL_SHIFT; + sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val); + + offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str); + if (offset < 0) { + printf("%s node not found in device tree\n", mdio_ioslot_str); + return offset; + } + + return offset; +} + +int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset, + struct phy_device *phy_dev, int phandle) +{ + char phy_node_name[] = "ethernet-phy@00"; + char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,"; + int ret; + + sprintf(phy_node_name, "ethernet-phy@%x", phyaddr); + debug("phy_node_name = %s\n", phy_node_name); + + *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name); + if (*subnodeoffset <= 0) { + printf("Could not add subnode %s inside node %s err = %s\n", + phy_node_name, fdt_get_name(fdt, offset, NULL), + fdt_strerror(*subnodeoffset)); + return *subnodeoffset; + } + + sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,", + phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF); + debug("phy_id_compatible_str %s\n", phy_id_compatible_str); + + ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible", + phy_id_compatible_str); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + + if (phy_dev->is_c45) { + ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", + "ethernet-phy-ieee802.3-c45"); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + } else { + ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", + "ethernet-phy-ieee802.3-c22"); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + } + + ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + + ret = fdt_set_phandle(fdt, *subnodeoffset, phandle); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + +out: + if (ret) + fdt_del_node(fdt, *subnodeoffset); + + return ret; +} + +#define is_rgmii(dpmac_id) \ + wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID + +int fdt_fixup_board_phy(void *fdt) +{ + int fpga_offset, offset, subnodeoffset; + struct mii_dev *mii_dev; + struct list_head *mii_devs, *entry; + int ret, dpmac_id, phandle, i; + struct phy_device *phy_dev; + char ethname[ETH_NAME_LEN]; + phy_interface_t phy_iface; + + ret = 0; + /* we know FPGA is connected to i2c0, therefore search path directly, + * instead of compatible property, as it saves time + */ + fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga"); + + if (fpga_offset < 0) + fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga"); + + if (fpga_offset < 0) { + printf("i2c@2000000/fpga node not found in device tree\n"); + return fpga_offset; + } + + phandle = fdt_alloc_phandle(fdt); + mii_devs = mdio_get_list_head(); + + list_for_each(entry, mii_devs) { + mii_dev = list_entry(entry, struct mii_dev, link); + debug("mii_dev name : %s\n", mii_dev->name); + offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset); + if (offset < 0) + continue; + + // Look for phy devices attached to MDIO bus muxing front end + // and create their entries with compatible being the device id + for (i = 0; i < PHY_MAX_ADDR; i++) { + phy_dev = mii_dev->phymap[i]; + if (!phy_dev) + continue; + + // TODO: use sscanf instead of loop + dpmac_id = WRIOP1_DPMAC1; + while (dpmac_id < NUM_WRIOP_PORTS) { + phy_iface = wriop_get_enet_if(dpmac_id); + snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", + dpmac_id, + phy_string_for_interface(phy_iface)); + if (strcmp(ethname, phy_dev->dev->name) == 0) + break; + dpmac_id++; + } + if (dpmac_id == NUM_WRIOP_PORTS) + continue; + + if ((dpmac_id == 17 || dpmac_id == 18) && + is_rgmii(dpmac_id)) + continue; + + ret = fdt_create_phy_node(fdt, offset, i, + &subnodeoffset, + phy_dev, phandle); + if (ret) + break; + + ret = fdt_fixup_dpmac_phy_handle(fdt, + dpmac_id, phandle); + if (ret) { + fdt_del_node(fdt, subnodeoffset); + break; + } + /* calculate offset again as new node addition may have + * changed offset; + */ + offset = fdt_get_ioslot_offset(fdt, mii_dev, + fpga_offset); + phandle++; + } + + if (ret) + break; + } + + return ret; +} +#endif // CONFIG_FSL_MC_ENET +#endif + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 2, true}, + {1, 3, true}, + {1, 15, true}, + {1, 17, true}, + {1, 18, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 10, false}, + {2, 11, true}, + {2, 12, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 0ff987eeb4e..222906fdff9 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -32,12 +32,13 @@ #include "../common/vid.h" #include <fsl_immap.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> +#include "lx2160a.h" #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" #endif -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) @@ -47,7 +48,7 @@ #define SDHC1_BASE_PMUX_DSPI 2 #define SDHC2_BASE_PMUX_DSPI 2 #define IIC5_PMUX_SPI3 3 -#endif /* CONFIG_TARGET_LX2160AQDS */ +#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ DECLARE_GLOBAL_DATA_PTR; @@ -191,7 +192,7 @@ int board_fix_fdt(void *fdt) } #endif -#if defined(CONFIG_TARGET_LX2160AQDS) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; @@ -259,7 +260,7 @@ void esdhc_dspi_status_fixup(void *blob) int esdhc_status_fixup(void *blob, const char *compat) { -#if defined(CONFIG_TARGET_LX2160AQDS) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) /* Enable esdhc and dspi DT nodes based on RCW fields */ esdhc_dspi_status_fixup(blob); #else @@ -297,7 +298,7 @@ int checkboard(void) enum boot_src src = get_boot_src(); char buf[64]; u8 sw; -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; static const char *const freq[] = {"100", "125", "156.25", "161.13", "322.26", "", "", "", @@ -306,7 +307,7 @@ int checkboard(void) #endif cpu_name(buf); -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else printf("Board: %s-RDB, ", buf); @@ -339,7 +340,13 @@ int checkboard(void) break; } } -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160ARDB) + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#else printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); @@ -350,31 +357,27 @@ int checkboard(void) sw = QIXIS_READ(brdcfg[2]); clock = sw >> 4; printf("Clock1 = %sMHz ", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) clock = sw & 0x0f; printf("Clock2 = %sMHz", freq[clock]); - +#endif sw = QIXIS_READ(brdcfg[3]); puts("\nSERDES2 Reference : "); clock = sw >> 4; printf("Clock1 = %sMHz ", freq[clock]); clock = sw & 0x0f; - printf("Clock2 = %sMHz", freq[clock]); - + printf("Clock2 = %sMHz\n", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) sw = QIXIS_READ(brdcfg[12]); - puts("\nSERDES3 Reference : "); + puts("SERDES3 Reference : "); clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); -#else - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - - puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); - puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); - puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#endif #endif return 0; } -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) /* * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. */ @@ -562,7 +565,7 @@ int config_board_mux(void) unsigned long get_board_sys_clk(void) { -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x03) { @@ -581,7 +584,7 @@ unsigned long get_board_sys_clk(void) unsigned long get_board_ddr_clk(void) { -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); switch ((ddrclk_conf & 0x30) >> 4) { diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h new file mode 100644 index 00000000000..52b020765dc --- /dev/null +++ b/board/freescale/lx2160a/lx2160a.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2160_H +#define __LX2160_H + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* SYSCLK */ +#define QIXIS_SYSCLK_100 0x0 +#define QIXIS_SYSCLK_125 0x1 +#define QIXIS_SYSCLK_133 0x2 + +/* DDRCLK */ +#define QIXIS_DDRCLK_100 0x0 +#define QIXIS_DDRCLK_125 0x1 +#define QIXIS_DDRCLK_133 0x2 + +#define BRDCFG4_EMI1SEL_MASK 0xF8 +#define BRDCFG4_EMI1SEL_SHIFT 3 +#define BRDCFG4_EMI2SEL_MASK 0x07 +#define BRDCFG4_EMI2SEL_SHIFT 0 +#endif + +#define QIXIS_XMAP_SHIFT 5 + +/* RTC */ +#define I2C_MUX_CH_RTC 0xB + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define AQ_PHY_ADDR1 0x00 +#define AQ_PHY_ADDR2 0x01 +#define AQ_PHY_ADDR3 0x02 +#define AQ_PHY_ADDR4 0x03 +#endif + +#ifdef CONFIG_TARGET_LX2160ARDB +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 +#define AQR107_IRQ_MASK 0x0C +#endif + +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define INPHI_PHY_ADDR2 0x1 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif +#endif + +#endif /* __LX2160_H */ diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 396981605d2..23fd619ceed 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { phy_interface_t intf = fm_info_get_enet_if(port); char phy[16]; + int lane; + u8 slot; + switch (intf) { /* The RGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_RGMII) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); - } - + break; /* The SGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_SGMII) { - int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - u8 slot; + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); if (lane < 0) return; slot = lane_to_slot[lane]; @@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } - } - - if (intf == PHY_INTERFACE_MODE_XGMII) { + break; + case PHY_INTERFACE_MODE_XGMII: /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); + lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { /* The XAUI PHY is identified by the slot */ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); fdt_set_phy_handle(fdt, compat, addr, phy); } + break; + default: + break; } } #endif /* #ifdef CONFIG_FMAN_ENET */ @@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(i, riser_phy_addr[i]); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index b64590f9d79..56e6109288f 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -89,6 +89,9 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 8e2f0358740..b034f11d68a 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -77,6 +77,9 @@ int board_eth_init(struct bd_info *bis) break; #endif case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 5044b5695b6..aaa3490aaa2 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -765,6 +765,9 @@ int board_eth_init(struct bd_info *bis) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4 || FM1_DTSEC10) diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index c16538850cd..e77f3f7146f 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -76,6 +76,9 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 8a38ac5d4e4..4754647fb4a 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -43,28 +43,17 @@ DECLARE_GLOBAL_DATA_PTR; -static int confidx; /* Default to generic. */ +#define VPD_PRODUCT_B850 1 +#define VPD_PRODUCT_B650 2 +#define VPD_PRODUCT_B450 3 + +static int productid; /* Default to generic. */ static struct vpd_cache vpd; #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -127,7 +116,7 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int is_b850v3(void) { - return confidx == 3; + return productid == VPD_PRODUCT_B850; } static int detect_lcd(struct display_info_t const *dev) @@ -314,9 +303,6 @@ int overwrite_console(void) #define VPD_TYPE_INVALID 0x00 #define VPD_BLOCK_NETWORK 0x20 #define VPD_BLOCK_HWID 0x44 -#define VPD_PRODUCT_B850 1 -#define VPD_PRODUCT_B650 2 -#define VPD_PRODUCT_B450 3 #define VPD_HAS_MAC1 0x1 #define VPD_HAS_MAC2 0x2 #define VPD_MAC_ADDRESS_LENGTH 6 @@ -398,6 +384,7 @@ static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL), }; #define SUS_S3_OUT IMX_GPIO_NR(4, 11) +#define PWGIN_IN IMX_GPIO_NR(4, 14) #define WIFI_EN IMX_GPIO_NR(6, 14) int board_early_init_f(void) @@ -412,28 +399,13 @@ int board_early_init_f(void) return 0; } -static void set_confidx(const struct vpd_cache* vpd) -{ - switch (vpd->product_id) { - case VPD_PRODUCT_B450: - confidx = 1; - break; - case VPD_PRODUCT_B650: - confidx = 2; - break; - case VPD_PRODUCT_B850: - confidx = 3; - break; - } -} - int board_init(void) { if (!read_i2c_vpd(&vpd, vpd_callback)) { int ret, rescan; vpd.is_read = true; - set_confidx(&vpd); + productid = vpd.product_id; ret = fdtdec_resetup(&rescan); if (!ret && rescan) { @@ -445,6 +417,9 @@ int board_init(void) gpio_request(SUS_S3_OUT, "sus_s3_out"); gpio_direction_output(SUS_S3_OUT, 1); + gpio_request(PWGIN_IN, "pwgin_in"); + gpio_direction_input(PWGIN_IN); + gpio_request(WIFI_EN, "wifi_en"); gpio_direction_output(WIFI_EN, 1); @@ -494,6 +469,17 @@ void pmic_init(void) } } +static void detect_boot_cause(void) +{ + const char *cause = "POR"; + + if (is_b850v3()) + if (!gpio_get_value(PWGIN_IN)) + cause = "PM_WDOG"; + + env_set("bootcause", cause); +} + int board_late_init(void) { process_vpd(&vpd); @@ -507,6 +493,8 @@ int board_late_init(void) else env_set("videoargs", "video=LVDS-1:1024x768@65"); + detect_boot_cause(); + /* board specific pmic init */ pmic_init(); diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c index 421fee59229..c28d2c03cfe 100644 --- a/board/ge/common/vpd_reader.c +++ b/board/ge/common/vpd_reader.c @@ -209,7 +209,7 @@ int read_i2c_vpd(struct vpd_cache *cache, u8 *data; int size; - ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev); + ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev); if (ret) return ret; diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat Binary files differindex e69de29bb2d..b0b5b9ba648 100644 --- a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat +++ b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index 7dfbc3ac867..441a1a376a9 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <dm.h> #include <init.h> #ifdef CONFIG_SPL_BUILD @@ -31,3 +32,25 @@ int board_early_init_f(void) return 0; } #endif + +#ifndef CONFIG_SPL_BUILD +int board_early_init_r(void) +{ + struct udevice *clk; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(clk_rk3399), &clk); + if (ret) { + debug("%s: CLK init failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} +#endif diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index bbafabdcb2c..8247ae39d32 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -15,6 +15,12 @@ config KM_ENABLE_FULL_DM_DTS_SUPPORT select PHYLIB endmenu +config SYS_MEMTEST_START + default 0x00100000 + +config SYS_MEMTEST_END + default 0x00f00000 + if TARGET_KMETER1 config SYS_BOARD diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 9eb000cca4d..a984165e241 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -236,12 +236,8 @@ void post_word_store(ulong value) int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - /* - * These match CONFIG_SYS_MEMTEST_START and - * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) - */ - *vstart = 0x00100000; - *size = 0xe00000; + *vstart = CONFIG_SYS_MEMTEST_START; + *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); return 0; diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt index d3c974f1f91..4c12d3e1c49 100644 --- a/board/keymile/scripts/develop-arm.txt +++ b/board/keymile/scripts/develop-arm.txt @@ -1 +1 @@ -setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure +setup_debug_env=tftpboot ${load_addr_r} scripts/develop-common.txt && env import -t ${load_addr_r} ${filesize} && run configure diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index f77a26abe8d..4384c0da301 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -9,4 +9,4 @@ toolchain=/opt/eldk rootfssize=0 set_uimage=printenv uimage || setenv uimage uImage set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi -try_import_nfs_path=if tftpboot 0x200000 ${tftppath}/nfs-path.txt; then env import -t 0x200000 ${filesize}; else echo no auto nfs path imported; echo you can set nfsargs in /tftpboot/${tftppath}/nfs-path.txt and rerun develop; fi +try_import_nfs_path=if tftpboot ${load_addr_r} ${tftppath}/nfs-path.txt; then env import -t ${load_addr_r} ${filesize}; else echo no auto nfs path imported; echo you can set nfsargs in /tftpboot/${tftppath}/nfs-path.txt and rerun develop; fi diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt index d3c974f1f91..4c12d3e1c49 100644 --- a/board/keymile/scripts/develop-ppc_82xx.txt +++ b/board/keymile/scripts/develop-ppc_82xx.txt @@ -1 +1 @@ -setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure +setup_debug_env=tftpboot ${load_addr_r} scripts/develop-common.txt && env import -t ${load_addr_r} ${filesize} && run configure diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt index d3c974f1f91..4c12d3e1c49 100644 --- a/board/keymile/scripts/develop-ppc_8xx.txt +++ b/board/keymile/scripts/develop-ppc_8xx.txt @@ -1 +1 @@ -setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure +setup_debug_env=tftpboot ${load_addr_r} scripts/develop-common.txt && env import -t ${load_addr_r} ${filesize} && run configure diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt index 87e984e179b..93f87fabab2 100644 --- a/board/keymile/scripts/ramfs-arm.txt +++ b/board/keymile/scripts/ramfs-arm.txt @@ -1 +1 @@ -setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure +setup_debug_env=tftpboot ${load_addr_r} scripts/ramfs-common.txt && env import -t ${load_addr_r} ${filesize} && run configure diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index 290c602aabc..e590a2bee6a 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -12,4 +12,4 @@ tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage} tftpramfs=tftpboot ${rootfsaddr} ${tftppath}/rootfsImage set_uimage=printenv uimage || setenv uimage uImage set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi -try_import_rootfssize=if tftpboot 0x200000 ${tftppath}/rootfssize.txt; then env import -t 0x200000 ${filesize}; else echo no auto rootfs size; echo you can set rootfssize in /tftpboot/${tftppath}/rootfssize.txt and rerun ramfs; fi +try_import_rootfssize=if tftpboot ${load_addr_r} ${tftppath}/rootfssize.txt; then env import -t ${load_addr_r} ${filesize}; else echo no auto rootfs size; echo you can set rootfssize in /tftpboot/${tftppath}/rootfssize.txt and rerun ramfs; fi diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt index 87e984e179b..93f87fabab2 100644 --- a/board/keymile/scripts/ramfs-ppc_82xx.txt +++ b/board/keymile/scripts/ramfs-ppc_82xx.txt @@ -1 +1 @@ -setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure +setup_debug_env=tftpboot ${load_addr_r} scripts/ramfs-common.txt && env import -t ${load_addr_r} ${filesize} && run configure diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt index 87e984e179b..93f87fabab2 100644 --- a/board/keymile/scripts/ramfs-ppc_8xx.txt +++ b/board/keymile/scripts/ramfs-ppc_8xx.txt @@ -1 +1 @@ -setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure +setup_debug_env=tftpboot ${load_addr_r} scripts/ramfs-common.txt && env import -t ${load_addr_r} ${filesize} && run configure diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index f624dbfbebc..3d62b5d9ad6 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <dm.h> #include <env.h> #include <init.h> #include <watchdog.h> @@ -33,6 +34,7 @@ #include <asm/setup.h> #include <asm/bitops.h> #include <asm/mach-types.h> +#include <asm/omap_i2c.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> @@ -198,8 +200,25 @@ static void reuse_atags(void) */ int board_init(void) { +#if defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs_onenandrx51[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1_RX51, + ONENAND_GPMC_CONFIG2_RX51, + ONENAND_GPMC_CONFIG3_RX51, + ONENAND_GPMC_CONFIG4_RX51, + ONENAND_GPMC_CONFIG5_RX51, + ONENAND_GPMC_CONFIG6_RX51, + 0 + }; +#endif /* in SRAM or SDRAM, finish GPMC */ gpmc_init(); +#if defined(CONFIG_CMD_ONENAND) + enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0], + CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M); +#endif + /* Enable the clks & power */ + per_clocks_enable(); /* boot param addr */ gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100; return 0; @@ -386,14 +405,13 @@ static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) */ int misc_init_r(void) { + struct udevice *dev; char buf[12]; u8 state; - /* reset lp5523 led */ - i2c_set_bus_num(1); - state = 0xff; - i2c_write(0x32, 0x3d, 1, &state, 1); - i2c_set_bus_num(0); + /* disable lp5523 led */ + if (i2c_get_chip_for_busnum(1, 0x32, 1, &dev) == 0) + dm_i2c_reg_write(dev, 0x00, 0x00); /* initialize twl4030 power managment */ twl4030_power_init(); @@ -626,8 +644,8 @@ int rx51_kp_tstc(struct stdio_dev *sdev) continue; /* read the key state */ - i2c_read(TWL4030_CHIP_KEYPAD, - TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8); + twl4030_i2c_read(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_FULL_CODE_7_0, keys, 8); /* cut out modifier keys from the keystate */ mods = keys[4] >> 4; @@ -684,3 +702,15 @@ void board_mmc_power_init(void) twl4030_power_mmc_init(0); twl4030_power_mmc_init(1); } + +static const struct omap_i2c_platdata rx51_i2c[] = { + { I2C_BASE1, 2200000, OMAP_I2C_REV_V1 }, + { I2C_BASE2, 100000, OMAP_I2C_REV_V1 }, + { I2C_BASE3, 400000, OMAP_I2C_REV_V1 }, +}; + +U_BOOT_DEVICES(rx51_i2c) = { + { "i2c_omap", &rx51_i2c[0] }, + { "i2c_omap", &rx51_i2c[1] }, + { "i2c_omap", &rx51_i2c[2] }, +}; diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h index fa1b42bf21e..4eff823a1b3 100644 --- a/board/nokia/rx51/rx51.h +++ b/board/nokia/rx51/rx51.h @@ -367,4 +367,11 @@ struct emu_hal_params_rx51 { MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ +#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202 +#define ONENAND_GPMC_CONFIG2_RX51 0x00111100 +#define ONENAND_GPMC_CONFIG3_RX51 0x00020200 +#define ONENAND_GPMC_CONFIG4_RX51 0x11001102 +#define ONENAND_GPMC_CONFIG5_RX51 0x03101616 +#define ONENAND_GPMC_CONFIG6_RX51 0x90060000 + #endif diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS index e56f30fdc09..8d02b0e1980 100644 --- a/board/phytec/phycore_am335x_r2/MAINTAINERS +++ b/board/phytec/phycore_am335x_r2/MAINTAINERS @@ -1,7 +1,11 @@ phyCORE AM335x R2 WEGA BOARD M: Niel Fourie <lusus@denx.de> -M: Parthiban Nallathambi <pn@denx.de> +M: Parthiban Nallathambi <parthiban@linumiz.com> S: Maintained +F: arch/arm/dts/am335x-regor.dtsi +F: arch/arm/dts/am335x-regor-rdk.dts +F: arch/arm/dts/am335x-regor-rdk-u-boot.dtsi F: board/phytec/phycore_am335x_r2 F: include/configs/phycore_am335x_r2.h +F: configs/phycore-am335x-r2-regor_defconfig F: configs/phycore-am335x-r2-wega_defconfig diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index e70d1e53f9c..64fdbd44b4a 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SPI_FLASH_ISSI imply SYSRESET imply SYSRESET_GPIO + imply CMD_I2C endif diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index b1147f2e1a7..e06f05bfa48 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 92e3d40a1b6..22a193d8fc3 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 85988acb241..4ad4ee69c7c 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 0484c3c2504..0b5afa05ac7 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 0484c3c2504..0b5afa05ac7 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/board/st/stm32mp1/fit_copro_kernel_dtb.its b/board/st/stm32mp1/fit_copro_kernel_dtb.its index 3e08fd943ed..dc43639af4b 100644 --- a/board/st/stm32mp1/fit_copro_kernel_dtb.its +++ b/board/st/stm32mp1/fit_copro_kernel_dtb.its @@ -1,6 +1,20 @@ /* * Compilation: * mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb + * + * M4 firmware to load with remoteproc: rproc-m4-fw.elf + * + * Files in linux build dir: + * - arch/arm/boot/zImage + * - arch/arm/boot/dts/stm32mp157c-dk2.dtb + * - arch/arm/boot/dts/stm32mp157c-ev1.dtb + * + * load mmc 0:4 $kernel_addr_r fit_copro_kernel_dtb.itb + * bootm $kernel_addr_r + * bootm $kernel_addr_r#dk2 + * bootm $kernel_addr_r#ev1 + * bootm $kernel_addr_r#dk2-m4 + * bootm $kernel_addr_r#ev1-m4 */ /dts-v1/; @@ -29,8 +43,8 @@ arch = "arm"; os = "linux"; compression = "none"; - load = <0xC0008000>; - entry = <0xC0008000>; + load = <0xC4000000>; + entry = <0xC4000000>; hash-1 { algo = "sha1"; }; diff --git a/board/st/stm32mp1/fit_kernel_dtb.its b/board/st/stm32mp1/fit_kernel_dtb.its index 18d03ebf3c0..8456a3c460f 100644 --- a/board/st/stm32mp1/fit_kernel_dtb.its +++ b/board/st/stm32mp1/fit_kernel_dtb.its @@ -3,7 +3,7 @@ * mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb * * Files in linux build dir: - * - arch/arm/boot/zImage + * - arch/arm/boot/Image (gzipped in Image.gz) * - arch/arm/boot/dts/stm32mp157c-dk2.dtb * - arch/arm/boot/dts/stm32mp157c-ev1.dtb * @@ -23,11 +23,11 @@ images { kernel { description = "Linux kernel"; - data = /incbin/("zImage"); + data = /incbin/("Image.gz"); type = "kernel"; arch = "arm"; os = "linux"; - compression = "none"; + compression = "gzip"; load = <0xC0008000>; entry = <0xC0008000>; hash-1 { diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 03a19af9302..d3cffdd770a 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -827,11 +827,22 @@ const char *env_ext4_get_intf(void) const char *env_ext4_get_dev_part(void) { + static char *const env_dev_part = +#ifdef CONFIG_ENV_EXT4_DEVICE_AND_PART + CONFIG_ENV_EXT4_DEVICE_AND_PART; +#else + ""; +#endif static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"}; + + if (strlen(env_dev_part) > 0) + return env_dev_part; + u32 bootmode = get_bootmode(); return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1]; } + int mmc_get_env_dev(void) { u32 bootmode = get_bootmode(); @@ -848,9 +859,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, }; - - if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + char *boot_device; + + /* Check the boot-source and don't update MTD for serial or usb boot */ + boot_device = env_get("boot_device"); + if (!boot_device || + (strcmp(boot_device, "serial") && strcmp(boot_device, "usb"))) + if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); return 0; } diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1180b86db3b..d3755ae41a9 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -451,6 +451,11 @@ M: Icenowy Zheng <icenowy@aosc.io> S: Maintained F: configs/pine_h64_defconfig +PINEPHONE BOARD +M: Samuel Holland <samuel@sholland.org> +S: Maintained +F: configs/pinephone_defconfig + R16 EVB PARROT BOARD M: Quentin Schulz <quentin.schulz@free-electrons.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index a5cf0b65c7b..708a27ed78e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -27,6 +27,7 @@ #include <asm/arch/dram.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/prcm.h> #include <asm/arch/spl.h> #include <linux/delay.h> #include <u-boot/crc.h> @@ -101,6 +102,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I_V3S) + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); + clock_twi_onoff(0, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); @@ -319,6 +324,17 @@ static struct boot_file_head * get_spl_header(uint8_t req_version) return spl; } +static const char *get_spl_dt_name(void) +{ + struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION); + + /* Check if there is a DT name stored in the SPL header. */ + if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) + return (char *)spl + spl->dt_name_offset; + + return NULL; +} + int dram_init(void) { struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION); @@ -843,6 +859,7 @@ static void setup_environment(const void *fdt) int misc_init_r(void) { + const char *spl_dt_name; uint boot; env_set("fel_booted", NULL); @@ -861,6 +878,16 @@ int misc_init_r(void) env_set("mmc_bootdev", "1"); } + /* Set fdtfile to match the FIT configuration chosen in SPL. */ + spl_dt_name = get_spl_dt_name(); + if (spl_dt_name) { + char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : ""; + char str[64]; + + snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name); + env_set("fdtfile", str); + } + setup_environment(gd->fdt_blob); #ifdef CONFIG_USB_ETHER @@ -889,33 +916,72 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #ifdef CONFIG_SPL_LOAD_FIT + +static void set_spl_dt_name(const char *name) +{ + struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION); + + if (spl == INVALID_SPL_HEADER) + return; + + /* Promote the header version for U-Boot proper, if needed. */ + if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION) + spl->spl_signature[3] = SPL_DT_HEADER_VERSION; + + strcpy((char *)&spl->string_pool, name); + spl->dt_name_offset = offsetof(struct boot_file_head, string_pool); +} + int board_fit_config_name_match(const char *name) { - struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION); - const char *cmp_str = (const char *)spl; + const char *best_dt_name = get_spl_dt_name(); + int ret; - /* Check if there is a DT name stored in the SPL header and use that. */ - if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) { - cmp_str += spl->dt_name_offset; - } else { #ifdef CONFIG_DEFAULT_DEVICE_TREE - cmp_str = CONFIG_DEFAULT_DEVICE_TREE; -#else - return 0; + if (best_dt_name == NULL) + best_dt_name = CONFIG_DEFAULT_DEVICE_TREE; #endif - }; + if (best_dt_name == NULL) { + /* No DT name was provided, so accept the first config. */ + return 0; + } #ifdef CONFIG_PINE64_DT_SELECTION -/* Differentiate the two Pine64 board DTs by their DRAM size. */ - if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) { - if ((gd->ram_size > 512 * 1024 * 1024)) - return !strstr(name, "plus"); + if (strstr(best_dt_name, "-pine64-plus")) { + /* Differentiate the Pine A64 boards by their DRAM size. */ + if ((gd->ram_size == 512 * 1024 * 1024)) + best_dt_name = "sun50i-a64-pine64"; + } +#endif +#ifdef CONFIG_PINEPHONE_DT_SELECTION + if (strstr(best_dt_name, "-pinephone")) { + /* Differentiate the PinePhone revisions by GPIO inputs. */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO); + sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT); + udelay(100); + + /* PL6 is pulled low by the modem on v1.2. */ + if (gpio_get_value(SUNXI_GPL(6)) == 0) + best_dt_name = "sun50i-a64-pinephone-1.2"; else - return !!strstr(name, "plus"); - } else { - return strcmp(name, cmp_str); + best_dt_name = "sun50i-a64-pinephone-1.1"; + + sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE); + sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE); + prcm_apb0_disable(PRCM_APB0_GATE_PIO); } #endif - return strcmp(name, cmp_str); + + ret = strcmp(name, best_dt_name); + + /* + * If one of the FIT configurations matches the most accurate DT name, + * update the SPL header to provide that DT name to U-Boot proper. + */ + if (ret == 0) + set_spl_dt_name(best_dt_name); + + return ret; } #endif diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 9263b0f51fa..2ed66261d28 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -37,6 +37,29 @@ static void setup_iomux_uart(void) imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + u32 is_quadplus = 0, val = 0; + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + + if (scierr == SC_ERR_NONE) { + /* QP has one A72 core disabled */ + is_quadplus = ((val >> 4) & 0x3) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + if (is_quadplus) + /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + *phys_sdram_2_size = 0x0UL; + else + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + int board_early_init_f(void) { sc_pm_clock_rate_t rate = SC_80MHZ; diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig new file mode 100644 index 00000000000..ee61e09736f --- /dev/null +++ b/board/toradex/apalis-imx8x/Kconfig @@ -0,0 +1,30 @@ +if TARGET_APALIS_IMX8X + +config SYS_BOARD + default "apalis-imx8x" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis-imx8x" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS new file mode 100644 index 00000000000..fbf93799315 --- /dev/null +++ b/board/toradex/apalis-imx8x/MAINTAINERS @@ -0,0 +1,10 @@ +Apalis iMX8X +M: Igor Opaniuk <igor.opaniuk@toradex.com> +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8x-apalis.dts +F: arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi +F: board/toradex/apalis-imx8x/ +F: configs/apalis-imx8x_defconfig +F: doc/board/toradex/apalis-imx8x.rst +F: include/configs/apalis-imx8x.h diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile new file mode 100644 index 00000000000..9d6e85b7429 --- /dev/null +++ b/board/toradex/apalis-imx8x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Toradex +# + +obj-y += apalis-imx8x.o diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg new file mode 100644 index 00000000000..58c62d0a659 --- /dev/null +++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND mx8qx-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-apalis-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c new file mode 100644 index 00000000000..739d2e51554 --- /dev/null +++ b/board/toradex/apalis-imx8x/apalis-imx8x.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Toradex + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> + +#include <asm/arch/clock.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <env.h> +#include <errno.h> +#include <linux/libfdt.h> + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart1_pads[] = { + SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + u32 is_dualx = 0, val = 0; + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + + if (scierr == SC_ERR_NONE) { + /* DX has two A35 cores disabled */ + is_dualx = (val & 0xf) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + if (is_dualx) + /* Our DX based SKUs only have 1 GB RAM */ + *phys_sdram_1_size = SZ_1G; + else + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate; + sc_err_t err = 0; + + /* + * This works around that having only UART3 up the baudrate is 1.2M + * instead of 115.2k. Set UART0 clock root to 80 MHz + */ + rate = 80000000; + err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + return 0; + + /* Set UART3 clock root to 80 MHz and enable it */ + rate = SC_80MHZ; + err = sc_pm_setup_uart(SC_R_UART_1, rate); + if (err != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Model: Toradex Apalis iMX8X\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */ + env_set("board_name", "Apalis iMX8X"); +#endif + + return 0; +} diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index 49c2df7ab25..3a2cf4606e3 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -11,7 +11,9 @@ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ +/* TRISTATE here means output driver is tri-stated */ \ .tristate = PMUX_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_DEFAULT, \ .od = PMUX_PIN_OD_DEFAULT, \ @@ -118,7 +120,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + /* UARTD RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), @@ -187,12 +190,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + /* UARTB RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + /* UARTC RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index f981c11a37c..da081e30bec 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -39,6 +39,29 @@ static void setup_iomux_uart(void) imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); } +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + u32 is_dualx = 0, val = 0; + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + + if (scierr == SC_ERR_NONE) { + /* DX has two A35 cores disabled */ + is_dualx = (val & 0xf) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + if (is_dualx) + /* Our DX based SKUs only have 1 GB RAM */ + *phys_sdram_1_size = SZ_1G; + else + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + int board_early_init_f(void) { sc_pm_clock_rate_t rate; diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index c5562f6d578..20cbb75a365 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -58,6 +58,17 @@ void pinmux_init(void) } /* + * Disable RS232 serial transceiver ForceOFF# pins on Iris + */ +void gpio_early_init_uart(void) +{ + gpio_request(TEGRA_GPIO(X, 6), "Force OFF# X13"); + gpio_direction_output(TEGRA_GPIO(X, 6), 1); + gpio_request(TEGRA_GPIO(X, 7), "Force OFF# X14"); + gpio_direction_output(TEGRA_GPIO(X, 7), 1); +} + +/* * Enable AX88772B USB to LAN controller */ void pin_mux_usb(void) diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index bdbbf5e49a1..5ac1a6da978 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -11,7 +11,9 @@ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ +/* TRISTATE here means output driver is tri-stated */ \ .tristate = PMUX_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_DEFAULT, \ .od = PMUX_PIN_OD_DEFAULT, \ @@ -178,14 +180,16 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + /* UARTC RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), @@ -204,11 +208,11 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + /* UARTB RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, UP, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT), - /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT), DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), @@ -268,10 +272,10 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT), /* LAN_RESET */ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT), diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index bf27b2fa66a..adab0a08020 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -16,7 +16,8 @@ defined(CONFIG_TARGET_COLIBRI_IMX6) || \ defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MN) + defined(CONFIG_TARGET_VERDIN_IMX8MN) || \ + defined(CONFIG_TARGET_VERDIN_IMX8MP) #include <asm/arch/sys_proto.h> #else #define is_cpu_type(cpu) (0) @@ -137,8 +138,12 @@ const char * const toradex_modules[] = { [53] = "Apalis iMX8 QuadXPlus 2GB ECC IT", [54] = "Apalis iMX8 DualXPlus 1GB", [55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT", - [56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */ + [56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */ [57] = "Verdin iMX8M Mini DualLite 1GB", + [58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT", + [59] = "Verdin iMX8M Mini Quad 2GB IT", + [60] = "Verdin iMX8M Mini DualLite 1GB WB IT", + [61] = "Verdin iMX8M Plus Quad 2GB", }; const char * const toradex_carrier_boards[] = { @@ -361,21 +366,15 @@ static int get_cfgblock_interactive(void) if (cpu_is_pxa27x()) sprintf(message, "Is the module the 312 MHz version? [y/N] "); -#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) || !defined(CONFIG_TARGET_VERDIN_IMX8MN) - else - sprintf(message, "Is the module an IT version? [y/N] "); - - len = cli_readline(message); - it = console_buffer[0]; -#else else it = 'y'; -#endif #if defined(CONFIG_TARGET_APALIS_IMX8) || \ defined(CONFIG_TARGET_APALIS_IMX8X) || \ defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \ - defined(CONFIG_TARGET_COLIBRI_IMX8X) + defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ + defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ + defined(CONFIG_TARGET_VERDIN_IMX8MP) sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] "); len = cli_readline(message); wb = console_buffer[0]; @@ -424,12 +423,6 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX7D; else if (!strcmp("imx7s", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7S; - else if (is_cpu_type(MXC_CPU_IMX8MM)) - tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; - else if (is_cpu_type(MXC_CPU_IMX8MMDL)) - tdx_hw_tag.prodid = VERDIN_IMX8MMDL; - else if (is_cpu_type(MXC_CPU_IMX8MN)) - tdx_hw_tag.prodid = VERDIN_IMX8MNSL; else if (is_cpu_type(MXC_CPU_IMX8QM)) { if (it == 'y' || it == 'Y') { if (wb == 'y' || wb == 'Y') @@ -465,6 +458,23 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX8DX; } #endif + } else if (is_cpu_type(MXC_CPU_IMX8MMDL)) { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MMDL; + } else if (is_cpu_type(MXC_CPU_IMX8MM)) { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT; + } else if (is_cpu_type(MXC_CPU_IMX8MN)) { + tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT; + } else if (is_cpu_type(MXC_CPU_IMX8MP)) { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MPQ; } else if (!strcmp("tegra20", soc)) { if (it == 'y' || it == 'Y') if (gd->ram_size == 0x10000000) diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 8f91d9aec65..9debd5f0462 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -75,9 +75,13 @@ enum { COLIBRI_IMX8DX, APALIS_IMX8QXP, APALIS_IMX8DXP, - VERDIN_IMX8MMQ_WIFI_BT_IT, - VERDIN_IMX8MNSL, + VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */ + VERDIN_IMX8MNQ_WIFI_BT, VERDIN_IMX8MMDL, + VERDIN_IMX8MPQ_WIFI_BT_IT, + VERDIN_IMX8MMQ_IT, + VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */ + VERDIN_IMX8MPQ, }; enum { diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index cc78c5666bb..72e2e09e256 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -21,12 +21,16 @@ #include <dm/uclass.h> #include <dm/uclass-internal.h> #include <hang.h> +#include <i2c.h> #include <power/bd71837.h> +#include <power/pca9450.h> #include <power/pmic.h> #include <spl.h> DECLARE_GLOBAL_DATA_PTR; +#define I2C_PMIC_BUS_ID 1 + int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -101,33 +105,29 @@ int power_init_board(void) struct udevice *dev; int ret; - ret = pmic_get("pmic@4b", &dev); - if (ret == -ENODEV) { - puts("No pmic\n"); - return 0; - } - if (ret != 0) - return ret; + if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) { + ret = pmic_get("pmic", &dev); + if (ret == -ENODEV) { + puts("No pmic found\n"); + return ret; + } - /* decrease RESET key long push time from the default 10s to 10ms */ - pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + if (ret != 0) + return ret; - /* unlock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - /* increase VDD_SOC to typical value 0.85v before first DRAM access */ - pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c); - /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ - pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); -#ifndef CONFIG_IMX8M_LPDDR4 - /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ - pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); -#endif + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); - /* lock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + return 0; + } return 0; } diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 66950ed218b..7cfae8767ce 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -8,12 +8,22 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <i2c.h> #include <miiphy.h> #include <netdev.h> #include <micrel.h> +#include "../common/tdx-cfg-block.h" + DECLARE_GLOBAL_DATA_PTR; +#define I2C_PMIC 0 + +enum pcb_rev_t { + PCB_VERSION_1_0, + PCB_VERSION_1_1 +}; + #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { @@ -104,8 +114,79 @@ int board_mmc_get_env_dev(int devno) return devno; } +static enum pcb_rev_t get_pcb_revision(void) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + u8 is_bd71837 = 0; + + ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, &bus); + if (!ret) + ret = dm_i2c_probe(bus, 0x4b, 0, &i2c_dev); + if (!ret) + ret = dm_i2c_read(i2c_dev, 0x0, &is_bd71837, 1); + + /* BD71837_REV, High Nibble is major version, fix 1010 */ + is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0); + return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1; +} + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a + * module with Wi-Fi/Bluetooth make sure we use the -wifi + * device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT); + } + + switch (get_pcb_revision()) { + case PCB_VERSION_1_0: + printf("Detected a V1.0 module\n"); + if (is_wifi) + strncpy(&variant[0], "wifi", sizeof(variant)); + else + strncpy(&variant[0], "nonwifi", sizeof(variant)); + break; + default: + if (is_wifi) + strncpy(&variant[0], "wifi-v1.1", sizeof(variant)); + else + strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant)); + break; + } + + if (strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + env_save(); + } +} + int board_late_init(void) { + select_dt_from_module_version(); + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + return 0; } diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h index a3e65202571..e7284709dde 100644 --- a/board/xilinx/common/fru.h +++ b/board/xilinx/common/fru.h @@ -50,12 +50,16 @@ struct fru_board_data { /* Xilinx custom fields */ u8 rev_type_len; u8 rev[FRU_BOARD_MAX_LEN]; + u8 pcie_type_len; + u8 pcie[FRU_BOARD_MAX_LEN]; + u8 uuid_type_len; + u8 uuid[FRU_BOARD_MAX_LEN]; }; struct fru_table { - bool captured; struct fru_common_hdr hdr; struct fru_board_data brd; + bool captured; }; #define FRU_TYPELEN_CODE_MASK 0xC0 diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index fc3add7d93d..b4cd3d49988 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -163,12 +163,15 @@ static int fru_parse_board(unsigned long addr) { u8 i, type; int len; - u8 *data, *term; + u8 *data, *term, *limit; memcpy(&fru_data.brd.ver, (void *)addr, 6); addr += 6; data = (u8 *)&fru_data.brd.manufacturer_type_len; + /* Record max structure limit not to write data over allocated space */ + limit = data + sizeof(struct fru_board_data); + for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) { len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code, &type); @@ -178,6 +181,9 @@ static int fru_parse_board(unsigned long addr) if (len == -EINVAL) break; + /* Stop when amount of chars is more then fields to record */ + if (data + len > limit) + break; /* This record type/len field */ *data++ = *(u8 *)addr; @@ -217,7 +223,7 @@ int fru_capture(unsigned long addr) hdr = (struct fru_common_hdr *)addr; - memcpy((void *)&fru_data.hdr, (void *)hdr, + memcpy((void *)&fru_data, (void *)hdr, sizeof(struct fru_common_hdr)); fru_data.captured = true; diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h deleted file mode 100644 index 5e0911faf63..00000000000 --- a/board/xilinx/microblaze-generic/xparameters.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK <monstr@monstr.eu> - * - * CAUTION: This file is a faked configuration !!! - * There is no real target for the microblaze-generic - * configuration. You have to replace this file with - * the generated file from your Xilinx design flow. - */ - -/* Microblaze is microblaze_0 */ -#define XILINX_FSL_NUMBER 3 - -/* Flash Memory is FLASH_2Mx32 */ -#define XILINX_FLASH_START 0x2c000000 -#define XILINX_FLASH_SIZE 0x00800000 diff --git a/common/common_fit.c b/common/common_fit.c index a9933081007..219674d4673 100644 --- a/common/common_fit.c +++ b/common/common_fit.c @@ -67,7 +67,7 @@ int fit_find_config_node(const void *fdt) if (board_fit_config_name_match(name)) continue; - debug("Selecting config '%s'", name); + debug("Selecting config '%s'\n", name); return node; } diff --git a/common/update.c b/common/update.c index 808be0880df..a5879cb52c4 100644 --- a/common/update.c +++ b/common/update.c @@ -29,7 +29,7 @@ #include <errno.h> #include <mtd/cfi_flash.h> -#ifdef CONFIG_DFU_TFTP +#if defined(CONFIG_DFU_TFTP) || defined(CONFIG_UPDATE_TFTP) /* env variable holding the location of the update file */ #define UPDATE_FILE_ENV "updatefile" @@ -99,7 +99,6 @@ static int update_load(char *filename, ulong msec_max, int cnt_max, ulong addr) return rv; } -#endif /* CONFIG_DFU_TFTP */ #ifdef CONFIG_MTD_NOR_FLASH static int update_flash_protect(int prot, ulong addr_first, ulong addr_last) @@ -216,6 +215,7 @@ static int update_flash(ulong addr_source, ulong addr_first, ulong size) #endif return 0; } +#endif /* CONFIG_DFU_TFTP || CONFIG_UPDATE_TFTP */ static int update_fit_getparams(const void *fit, int noffset, ulong *addr, ulong *fladdr, ulong *size) @@ -233,7 +233,7 @@ static int update_fit_getparams(const void *fit, int noffset, ulong *addr, return 0; } -#ifdef CONFIG_DFU_TFTP +#if defined(CONFIG_DFU_TFTP) || defined(CONFIG_UPDATE_TFTP) int update_tftp(ulong addr, char *interface, char *devstring) { char *filename, *env_addr, *fit_image_name; @@ -340,7 +340,7 @@ next_node: return ret; } -#endif /* CONFIG_DFU_UPDATE */ +#endif /* CONFIG_DFU_UPDATE || CONFIG_UPDATE_TFTP */ #ifdef CONFIG_UPDATE_FIT /** diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 769709e9d21..0dc1d29c8de 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 CONFIG_SPL_TEXT_BASE=0xFFFD8000 @@ -31,8 +33,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index 516692e1a44..6cf2d6ce409 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_TEXT_BASE=0xFFFD8000 @@ -29,8 +31,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index f63d739e34d..8fe44cbcec4 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y @@ -17,8 +19,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 0b16784b616..d9b0cf0535e 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -31,8 +33,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index f5cf6ef710f..5756db7c4ba 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y @@ -16,8 +18,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 9cda891a898..f9776ffe555 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_TEXT_BASE=0xFFFD8000 @@ -35,8 +37,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index a7d9ebf27e8..529522a5299 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_TEXT_BASE=0xFFFD8000 @@ -33,8 +35,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index ff2aaaef619..f33c0022f91 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" @@ -20,8 +22,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index a7191944733..fe01675ed04 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -35,8 +37,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index cc31e5a6100..4b95136694a 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" @@ -20,8 +22,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 656caa6b5bc..d7ccee25592 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00201000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_TEXT_BASE=0xFFFD8000 @@ -31,8 +33,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 63356202ed5..99ea925df8f 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00201000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_TEXT_BASE=0xFFFD8000 @@ -29,8 +31,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 605b9107daa..b82a4cca955 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y @@ -15,8 +17,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index b57dadf39a6..c820c2bf5ae 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -2,6 +2,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00201000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -31,8 +33,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 039eefa3343..54579fa8aae 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y @@ -13,8 +15,6 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 50c24f5aeb1..d20de349de7 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" @@ -16,8 +18,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00200000 -CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 8a94ad15305..941073ce7f1 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 2c7217afb64..7d467c167e9 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index a2c03a01f48..a10bff8ae63 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9F000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -25,8 +27,6 @@ CONFIG_SYS_PROMPT="ap121 # " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80100000 -CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index bf3db115826..e685a96a17c 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9F000000 CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -26,8 +28,6 @@ CONFIG_SYS_PROMPT="ap143 # " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80100000 -CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig index d776675286d..7eb7de68793 100644 --- a/configs/ap152_defconfig +++ b/configs/ap152_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9F000000 CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -26,8 +28,6 @@ CONFIG_SYS_PROMPT="ap152 # " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80100000 -CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 1402fe66f4f..2450797030c 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y @@ -19,8 +21,6 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig new file mode 100644 index 00000000000..e6aa5753805 --- /dev/null +++ b/configs/apalis-imx8x_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_TARGET_APALIS_IMX8X=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Apalis iMX8X # " +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index bc0327b7dae..1c791ab7484 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6Q=y @@ -38,8 +40,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig deleted file mode 100644 index d47a074645b..00000000000 --- a/configs/aristainetos2b_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2B=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig deleted file mode 100644 index 30139621d83..00000000000 --- a/configs/aristainetos2bcsl_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2BCSL=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 50cadb749af..df0b26d6a0a 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_SYS_MALLOC_F_LEN=0x13000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xD0000 CONFIG_MX6DL=y @@ -10,11 +10,11 @@ CONFIG_DM_GPIO=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 +CONFIG_BOOTDELAY=-2 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" @@ -30,6 +30,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -51,14 +53,17 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_APBH_DMA=y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2ccslb_defconfig index 35e4b09715f..0156493934c 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -1,21 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_SYS_MALLOC_F_LEN=0x13000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xD0000 CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2=y +CONFIG_TARGET_ARISTAINETOS2CCSLB=y CONFIG_DM_GPIO=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set -# CONFIG_CMD_NANDBCB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_cslb_7" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 +CONFIG_BOOTDELAY=-2 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" @@ -31,11 +30,12 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y # CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y @@ -53,16 +53,22 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y +CONFIG_APBH_DMA=y +CONFIG_APBH_DMA_BURST=y +CONFIG_APBH_DMA_BURST8=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_PCA953X=y @@ -74,11 +80,7 @@ CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y @@ -94,7 +96,10 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_DA9063=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_DA9063=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y CONFIG_PWM_IMX=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 2426179d442..6c0d22c2ab7 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_DM_GPIO=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 @@ -22,8 +24,6 @@ CONFIG_BOOTDELAY=0 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_OS_BOOT=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_MMC=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index acf7f81f6f6..85e206105c1 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -4,6 +4,8 @@ CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y @@ -24,8 +26,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80010000 -CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index b6dde0e191d..f11581427bf 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -16,8 +18,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 7b345ed5180..a1d523b6f44 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -17,8 +19,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index f668fca8943..e8cedccad8f 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -17,8 +19,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index 7fe4f739142..948d527fc79 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -18,8 +20,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 4baf7ba6408..0eb8efd499c 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -17,8 +19,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index d63efee3735..500284b5d3b 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -18,8 +20,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index 08dd017cc79..3e06176dca0 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -17,8 +19,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 74a43d524f9..a3aeb944878 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -1,5 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_TARGET_BOSTON=y @@ -18,8 +20,6 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index a1b494ec0f1..987e3ac8e95 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_ARMV7_PSCI_0_1=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index c3f608264d3..26f74662f80 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -71,6 +71,7 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 4608892fb56..73635f0d13f 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,6 +19,11 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_BLOBLIST_ADDR=0x100000 +CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 2c33e0eedac..5e18f66d71b 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x380000 CONFIG_MX6ULL=y @@ -28,8 +30,6 @@ CONFIG_SYS_PROMPT="Colibri iMX6ULL # " CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -84,6 +84,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 022caea9fc2..dab8a92d656 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y @@ -18,8 +20,6 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index e2cb9eb7414..9e03ac09db6 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6DL=y @@ -37,8 +39,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index a6a00536815..71e331ef71e 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x380000 CONFIG_DM_GPIO=y @@ -29,8 +31,6 @@ CONFIG_SYS_PROMPT="Colibri iMX7 # " # CONFIG_CMD_XIMG is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -82,6 +82,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 2b21f3442f3..c5a6c4433d5 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y @@ -32,8 +34,6 @@ CONFIG_SYS_PROMPT="Colibri iMX7 # " CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -79,6 +79,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 15077887bab..abac672cf2e 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -4,6 +4,8 @@ CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x180000 CONFIG_DM_GPIO=y @@ -29,8 +31,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80010000 -CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_DFU=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 9d99aff1c8e..10a4bda12ee 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_TARGET_DB_XC3_24G4XG=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 @@ -16,8 +18,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00800000 -CONFIG_SYS_MEMTEST_END=0x00ffffff # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SPI=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 7af060096bf..0d1f0cfeac1 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -35,8 +37,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_CMD_UNZIP=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 5765ef456be..899e61ad3ce 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -1,6 +1,8 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07e00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y @@ -128,8 +130,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_BINOP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07e00000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index fd47aad6482..41e190bf1e8 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -81,6 +81,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 2a87353ca98..66b04419782 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -85,6 +85,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index d2fa6d70227..9022f350d13 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -85,6 +85,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 3749ae1e6ed..06005c4288e 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6QDL=y @@ -25,8 +27,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 664e3d3df06..fa2adaf47d7 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y @@ -17,8 +19,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 751eee8c0eb..f38b06dab98 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6QDL=y @@ -26,8 +28,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 38801bc789f..36dc24d0807 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x100000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6Q=y @@ -39,8 +41,6 @@ CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x1500000 CONFIG_CMD_SPL_WRITE_SIZE=0x00100000 CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 68aea247d28..f1b53894701 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y @@ -34,8 +36,6 @@ CONFIG_SYS_PROMPT="icorem6qdl-mipi> " CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 3e3d0a9f91b..a32ae6a75dc 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y @@ -37,8 +39,6 @@ CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 751eee8c0eb..f38b06dab98 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6QDL=y @@ -26,8 +28,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index f63479aa083..34e3250f955 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y @@ -31,8 +33,6 @@ CONFIG_SYS_PROMPT="icorem6qdl-rqs> " CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 84bcd97e75f..4b47e196f31 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 2679847f10c..9870612edfb 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 95b75edc5cc..2e33db21d82 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index e8b1b755fd6..9c4f742135a 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 7c900b1d2e3..1d2526b5f1b 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6de8666956c..982e3df2f22 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index acbc04359c6..28bf56e7e10 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 1b59da2d954..b258880b947 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6UL=y @@ -24,8 +26,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -56,6 +56,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index bd2d7d56925..6ddc9737ae8 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012A2G5RDB=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -25,8 +27,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 0620b8fd005..66aec34ad0e 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012A2G5RDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -25,8 +27,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index f24f5f35c57..27a73931b55 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRDM=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -24,8 +26,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 7b94958e7c4..d17f1e28edf 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012AFRDM=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -24,8 +26,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index f08d962c95f..a0217fdd852 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -23,8 +25,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index ff041bf70a6..6b8212c76d1 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x1D0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -24,8 +26,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 60486183f53..b85513115f1 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012AFRWY=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -23,8 +25,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index c8b02da638e..b773738a6b1 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012AFRWY=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x1D0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -24,8 +26,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index c56d04ed177..1771f1a8a6c 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -28,8 +30,6 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 914400371cb..8f6ca820a24 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -26,8 +28,6 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index a6a44fea8e5..fcd53196c0b 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -28,8 +30,6 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 3c3376b3b6b..be59d29dc2c 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -25,8 +27,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 6675cef0a2d..e6742ecb219 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -25,8 +27,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 5edbdc8379e..fdf4703d207 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -25,8 +27,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index b56f8139667..42bfa9b1884 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1012ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -25,8 +27,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index ee2213d19d5..a581f9bdc05 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 49783e3e78a..1bba6f52500 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index f76ce195612..c32f5e19482 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 CONFIG_DM_GPIO=y @@ -37,8 +39,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index bb226bb3d50..ea490708ccc 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index ebcd77cebf1..7ba5d2d07c7 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index ddd75233df5..13ce8588d31 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index f44783c3515..dcf0dbb4a60 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -23,8 +25,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index ea3844d092c..5e6f531ee8a 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -35,8 +37,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 8a6cb2a3020..5477d702b25 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -34,8 +36,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 73d007411f8..f13428d4f02 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -23,8 +25,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 11a981a022c..a17b66ea4c4 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 0946f8f9c5a..10ce0454459 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -24,8 +26,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index a764714ba8f..bd9dc934a05 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -25,8 +27,6 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 3d3e093f3cd..41b16758f5b 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -38,8 +40,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index f96514a9f73..5a40bb213a6 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -37,8 +39,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 3b9cef04829..957790288d5 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -36,8 +38,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 4d255acc064..14c49cd0d6f 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 55dd9313ef5..09a69237087 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -23,8 +25,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 01d51ac1bf6..a3749b56273 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -23,8 +25,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 166d0f29f70..b034580aeff 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 85b1e0ea6f9..4bed352420a 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -22,8 +24,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 77993f8ad89..b24a316e49e 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 8b486efab57..805e69d8b26 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 060dd19c13a..6b8c77b6144 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -37,8 +39,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index a6d3d136691..5c07c912cda 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index aa4b14c62d8..6188ac5e431 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -23,8 +25,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index eb1929b1d5c..a6e77fc4f6c 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -37,8 +39,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 6bde77cec72..b426569aab4 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -36,8 +38,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 59e468f0ec6..1e3ac53070c 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1043AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -23,8 +25,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 5f8611abc14..43ac60e18b0 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1043AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 @@ -24,8 +26,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 2141e661c0c..ff0f1ccfc42 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 5b7e02857be..10a23af7b67 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 7d07efe41a6..6b07708caed 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 1bf24607abd..03be431622a 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -30,8 +32,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 3183523d653..deb6ac19a7f 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -22,8 +24,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 705986f7bbb..4ea81422658 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -38,8 +40,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 47c61760704..b031fce4e10 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y @@ -37,8 +39,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 7b8b540aab9..49f9cb4b10b 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1046AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -23,8 +25,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 08d6869111f..547848ffeba 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_LS1046AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -24,8 +26,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 90c59a5d05c..e95e8714452 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -3,6 +3,8 @@ CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_FSL_LS_PPA=y @@ -21,8 +23,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 5cbe40658f3..a053ea86a7a 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y @@ -23,8 +25,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 97b60c0aaca..2b0d21d208a 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -3,6 +3,8 @@ CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -24,8 +26,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 240bcb2a052..725f6bb0bb6 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_SPL_TEXT_BASE=0x1800a000 @@ -32,8 +34,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 051bc3b12f4..e775e490b18 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_SPL_TEXT_BASE=0x1800a000 @@ -34,8 +36,6 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 99fb3c0a02e..019d8995edb 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -5,6 +5,8 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -27,8 +29,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index c45442cea9d..b4fdc00aa50 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -3,6 +3,8 @@ CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y @@ -24,8 +26,6 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 84aa85f1c9c..40fe7c4520e 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -3,6 +3,8 @@ CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -25,8 +27,6 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index d55a5c53c4d..9c7a85fe62b 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_SPL_TEXT_BASE=0x1800a000 @@ -36,8 +38,6 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 6caf595edf0..d409ef3f945 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_SPL_TEXT_BASE=0x1800a000 @@ -35,8 +37,6 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index f7a40b2227a..6a075770154 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -5,6 +5,8 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y @@ -27,8 +29,6 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index efbe1772c0c..d9b11eba717 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -5,6 +5,8 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -28,8 +30,6 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index a6a3feba931..cf4bf8a19a6 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y @@ -69,6 +70,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index d96c3b129d7..f0e8dca8f92 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y @@ -76,6 +77,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index b2912e418b3..0551ef07930 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -52,6 +52,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y @@ -61,6 +62,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 5a9e2e776ee..52ac1264aee 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -61,6 +61,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y @@ -70,6 +71,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 2d7b4af4b29..d9c16740266 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -61,6 +61,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y @@ -70,6 +71,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 00000000000..610e09d7266 --- /dev/null +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_TFABOOT=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_NXP_ESBC=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MPC8XXX_GPIO=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig new file mode 100644 index 00000000000..af7a63f6af6 --- /dev/null +++ b/configs/lx2162aqds_tfa_defconfig @@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_OPTEE_TA_AVB=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_CMD_OPTEE_RPMB=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig new file mode 100644 index 00000000000..32c583cf82e --- /dev/null +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_RSA=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_OPTEE_TA_AVB=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MPC8XXX_GPIO=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 22578714b5c..d2bd9c46d25 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -38,6 +38,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/meerkat96_defconfig b/configs/meerkat96_defconfig index 7bc658aba02..08a9d4bf1a2 100644 --- a/configs/meerkat96_defconfig +++ b/configs/meerkat96_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_DM_GPIO=y @@ -18,8 +20,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 08c88856dcd..761cc65cbfa 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -48,8 +48,10 @@ CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 563bd299208..2540272e405 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -32,8 +34,6 @@ CONFIG_SYS_PROMPT="jr2 # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fc00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 667821f1020..d2ce2798f57 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -34,8 +36,6 @@ CONFIG_SYS_PROMPT="luton # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x87c00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index e453e1b4a56..6e163502fad 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -31,8 +33,6 @@ CONFIG_SYS_PROMPT="ocelot # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fc00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index f6dbe786ab7..f1e0ec0ccf2 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -29,8 +31,6 @@ CONFIG_SYS_PROMPT="serval # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x87c00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index bb876d5e1cd..6c22824aacf 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -28,8 +30,6 @@ CONFIG_SYS_PROMPT="servalt # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fc00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 4cabe9076a3..a373d52c93d 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 9aa602f902a..41ff942cf1c 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_MX6QDL=y CONFIG_MX6_DDRCAL=y @@ -31,8 +33,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x20000000 # CONFIG_CMD_FUSE is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 47ff35f56ce..c1f808562c0 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6Q=y @@ -21,8 +23,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 3241ef8e065..4faf49ef059 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -89,6 +89,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index baa304f7449..0016fbac20d 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -100,6 +100,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 171941a8f71..5fd78c3629a 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 925886cb403..9777166727e 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index b430955cb37..4e44bc2c79a 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 247f04b39b0..1e446a3e439 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6SLL=y @@ -15,8 +17,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -48,6 +48,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 37ad688a748..3e0e1006b96 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6SLL=y @@ -16,8 +18,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index f645f751e26..0d8c07b57d8 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -61,6 +61,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 0e672efb7b2..af5acc178f2 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -66,6 +66,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 1fb5c004c12..878df78ccec 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y @@ -30,8 +32,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -80,6 +80,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 3d4f0e0c3ff..9587ff808f1 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -75,6 +75,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 6b864110b9c..fdd44838178 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y @@ -14,8 +16,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -58,3 +58,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index da752219317..a6c30b3fb68 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y @@ -15,8 +17,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -57,3 +57,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 77807a3d1ca..71801208adb 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y @@ -14,8 +16,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -49,3 +49,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 29f3afdc739..3687a65283f 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -70,6 +70,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index bf0e2cee604..c216b8c5be6 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -77,6 +77,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index bc0fa9bf1f4..e918634a014 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -13,8 +15,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x60000000 -CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index cc91d9a4134..8a80f898c7a 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -11,8 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x60000000 -CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index db79c63e8cf..e929216c832 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x4000 CONFIG_MX6ULL=y CONFIG_TARGET_MYS_6ULX=y @@ -24,8 +26,6 @@ CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -66,6 +66,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 5e76c96ad50..8817023d75d 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 @@ -23,8 +25,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index d7efcfd091d..bb07eceed21 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 @@ -23,8 +25,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 3042b0f1a91..0308db162c3 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 @@ -23,8 +25,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 5369535275f..2dfdb9ef722 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 @@ -23,8 +25,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index ffd91167a83..f30fbc5b397 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 @@ -23,8 +25,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 18ddb7c5fad..3d855667d1e 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 @@ -23,8 +25,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 1d353520a9f..d0c89295251 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -43,6 +43,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(bootloader)ro,384k(config),256k(l CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set +CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_TWL4030_LED=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MMC_OMAP_HS=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 591caa7a0d4..3f80bf43519 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -4,6 +4,8 @@ CONFIG_ARCH_OCTEONTX2=y CONFIG_SYS_TEXT_BASE=0x04000000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x04000000 +CONFIG_SYS_MEMTEST_END=0x040f0000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -27,8 +29,6 @@ CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x04000000 -CONFIG_SYS_MEMTEST_END=0x040f0000 CONFIG_CMD_SHA1SUM=y CONFIG_SHA1SUM_VERIFY=y CONFIG_CMD_DM=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index c006a14bdcb..f0585a74884 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -4,6 +4,8 @@ CONFIG_ARCH_OCTEONTX=y CONFIG_SYS_TEXT_BASE=0x2800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x2800000 +CONFIG_SYS_MEMTEST_END=0x28f0000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -28,8 +30,6 @@ CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x2800000 -CONFIG_SYS_MEMTEST_END=0x28f0000 CONFIG_CMD_SHA1SUM=y CONFIG_SHA1SUM_VERIFY=y CONFIG_CMD_DM=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index a4fb70b5bfd..4f8a524c1dc 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -53,6 +53,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 81feb2ff2f4..ec3bf903069 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -64,6 +64,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 23683255ce4..196bfc5b31c 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -3,6 +3,8 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xA0000 CONFIG_DM_GPIO=y @@ -15,8 +17,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80010000 -CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index dc7151b6107..fa8ed31e5be 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -71,4 +71,5 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig new file mode 100644 index 00000000000..6d404975373 --- /dev/null +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_OFFSET=0xA0000 +CONFIG_AM33XX=y +CONFIG_SYS_MPUCLK=1000 +CONFIG_TARGET_PHYCORE_AM335X_R2=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk" +# CONFIG_FIT is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_DRIVERS=y +CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SPL=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_DNS2=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),1m(NAND.u-boot),-(NAND.UBI)" +CONFIG_CMD_UBI=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_TI=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETHER=y +CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index a5b5dfacacf..65239a049d5 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x4000 CONFIG_MX6UL=y CONFIG_TARGET_PCL063=y @@ -20,8 +22,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -59,6 +59,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 9cc0892daba..c57ca29f3bc 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 6ff1ee3489d..cb363a7cb1e 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9D004000 CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x88080000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_MACH_PIC32=y @@ -14,8 +16,6 @@ CONFIG_SYS_PROMPT="dask # " CONFIG_LOOPW=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x88080000 CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index f14b80f8cbd..de098475509 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y @@ -26,8 +28,6 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 085913ef82d..dbfa2e0a8cf 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 42c419d3e8f..e452f9c600f 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 6b3b100d20e..f33a72571c0 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 6017b257c93..9cc50141ed8 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y @@ -29,8 +31,6 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index be9661fc3ce..947dfcbf9eb 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_MX7=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -26,8 +28,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -62,6 +62,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_CONS_INDEX=4 CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index e2e3a56437f..cc49e6f80ab 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 085913ef82d..dbfa2e0a8cf 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 2572f31504a..d93f342361f 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y @@ -27,8 +29,6 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 4005f8d1afb..ab630cace7c 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 1ed54ad0eda..8fbd7280ace 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -55,6 +55,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y @@ -76,8 +78,9 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig new file mode 100644 index 00000000000..64ecef59c90 --- /dev/null +++ b/configs/pinephone_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_PINEPHONE_DT_SELECTION=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1c632770b3b..b652057d743 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -39,6 +39,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index 42d737771c4..95549ff5b7f 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -49,6 +49,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index bfba8704072..575b7a20d50 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_DM_KEYBOARD=y @@ -41,6 +42,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig index 6d791e6bd70..656f63f76ab 100644 --- a/configs/s32v234evb_defconfig +++ b/configs/s32v234evb_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_S32V234EVB=y CONFIG_SYS_TEXT_BASE=0x3E800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc7c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DISTRO_DEFAULTS=y @@ -11,8 +13,6 @@ CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0xc0000000 -CONFIG_SYS_MEMTEST_END=0xc7c00000 CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index 075210942f1..c5537bac345 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -3,6 +3,8 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_NEXELL=y CONFIG_SYS_TEXT_BASE=0x74C00000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x71000000 +CONFIG_SYS_MEMTEST_END=0xb0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x2E0200 CONFIG_DM_GPIO=y @@ -22,8 +24,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x71000000 -CONFIG_SYS_MEMTEST_END=0xb0000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index dc993cd13aa..5fbbfd7236c 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -1,5 +1,7 @@ CONFIG_SYS_TEXT_BASE=0 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -39,8 +41,6 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00100000 -CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index f2a767a4cde..f1ec701a9fb 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -1,5 +1,7 @@ CONFIG_SYS_TEXT_BASE=0 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 CONFIG_PRE_CON_BUF_ADDR=0xf0000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -45,8 +47,6 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00100000 -CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_BIND=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 1f593eba8fd..edca7f1808f 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -1,5 +1,7 @@ CONFIG_SYS_TEXT_BASE=0 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_DEFAULT_DEVICE_TREE="sandbox" @@ -33,8 +35,6 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00100000 -CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 1ac843e1bcd..479f0226e37 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -2,6 +2,8 @@ CONFIG_SYS_TEXT_BASE=0 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -46,8 +48,6 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00100000 -CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index b0b8926c279..69fc1b8b859 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x40400000 CONFIG_ENV_SIZE=0x4000 CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_SANSA_FUZE_PLUS=y @@ -20,8 +22,6 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x40000000 -CONFIG_SYS_MEMTEST_END=0x40400000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig index 927f46f5db4..9b3706124ff 100644 --- a/configs/sksimx6_defconfig +++ b/configs/sksimx6_defconfig @@ -49,4 +49,5 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 95e5fb744df..230d3c2ce5c 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 @@ -21,8 +23,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index a7fe25cd529..bf864d089fe 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x40000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -25,8 +27,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x40000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index e4633001e38..3df44bb88d5 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 @@ -22,8 +24,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x3fe00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 0cd1d9df6ac..52e34e3b3f7 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y @@ -14,8 +16,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index d1dbe1a92d1..1843bbcc783 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 @@ -33,8 +35,6 @@ CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0xc0000000 -CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index d7b4cd76c86..ed285e91617 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_SIZE=0x4000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_DM_SPI=y @@ -33,8 +35,6 @@ CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0xc0000000 -CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -57,7 +57,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y # CONFIG_SPL_DOS_PARTITION is not set -CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02" +CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx" CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 9ff2ee70f01..964f4c28850 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_TARGET_ST_STM32MP15x=y @@ -17,8 +19,6 @@ CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0xc0000000 -CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index c458a1c2183..0ec9e278102 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IDENT_STRING=" strider con 0.01" @@ -109,8 +111,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index f337bfc0a7b..304f9caca7a 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IDENT_STRING=" strider con dp 0.01" @@ -109,8 +111,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 50b346a57de..d1c388cfb85 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IDENT_STRING=" strider cpu 0.01" @@ -109,8 +111,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index f4c66721228..61c6240e94d 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IDENT_STRING=" strider cpu dp 0.01" @@ -109,8 +111,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 838df289c77..7fe5f99f4d4 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_STV0991=y CONFIG_SYS_TEXT_BASE=0x00010000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00100000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x30000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -19,8 +21,6 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="STV0991> " CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00100000 CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index f846533f3ba..239e9ed04ec 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x2f400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6Q=y @@ -29,8 +31,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_FDT is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x2f400000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -84,6 +84,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 9aa8b4819b1..ec66bb09584 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_DM_GPIO=y @@ -24,8 +26,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 7b338f47083..e4145948859 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_DM_GPIO=y @@ -24,8 +26,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index a89156d95ba..0041ee15366 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_DM_GPIO=y @@ -24,8 +26,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index 6348b315c8f..418f94b4bce 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_TOTAL_COMPUTE=y CONFIG_SYS_TEXT_BASE=0xe0000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_ENV_SIZE=0x2a00000 CONFIG_DEFAULT_DEVICE_TREE="total_compute" CONFIG_DISTRO_DEFAULTS=y @@ -24,8 +26,6 @@ CONFIG_SYS_PROMPT="TOTAL_COMPUTE# " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_CMD_ARMFLASH=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 29219d07c25..19769577793 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -1,6 +1,8 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xA1000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ARCH_ATH79=y CONFIG_BOARD_TPLINK_WDR4300=y @@ -14,8 +16,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80100000 -CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 0940b3e4fa2..4b8843d7be6 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -8,6 +8,8 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_TARGET_TURRIS_OMNIA=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xF0000 @@ -34,8 +36,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00800000 -CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_CMD_SHA1SUM=y CONFIG_CMD_LZMADEC=y CONFIG_CMD_GPIO=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 89e9363dc56..ba1e6d31f8d 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -38,4 +38,5 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 722211c2e5b..e1128e5d6ad 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX5=y CONFIG_SYS_TEXT_BASE=0x77800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x70000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_TARGET_USBARMORY=y @@ -9,8 +11,6 @@ CONFIG_TARGET_USBARMORY=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x70000000 -CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_FUSE=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 37d9687c065..5f94cea5ddc 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 531d566fec6..ea0b5978f1f 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_SYS_I2C_MXC_I2C1=y @@ -43,8 +45,6 @@ CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x40000000 -CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y @@ -90,7 +90,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y -CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 005d3d17899..7ca95142149 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_VEXPRESS64_JUNO=y CONFIG_SYS_TEXT_BASE=0xe0000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IDENT_STRING=" vexpress_aemv8a" @@ -18,8 +20,6 @@ CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index ee41ec37df3..a26137ef5dc 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_VEXPRESS64_BASE_FVP=y CONFIG_SYS_TEXT_BASE=0x88000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_IDENT_STRING=" vexpress_aemv8a" @@ -20,8 +22,6 @@ CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set # CONFIG_CMD_ITEST is not set diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 7c3408369fe..24a7bdedf0a 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -3,6 +3,8 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -16,8 +18,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80010000 -CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 7c8ac626901..7cf8ae66042 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -3,6 +3,8 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x180000 CONFIG_DM_GPIO=y @@ -16,8 +18,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80010000 -CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index b0a9c652a98..31e6cfb4252 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -78,6 +78,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 7c0fec918db..4b45fcd50ab 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_DM_GPIO=y @@ -14,8 +16,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -52,6 +52,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OPTEE=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index b4cf58652a5..3d11196080f 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y @@ -20,8 +22,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -58,6 +58,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OPTEE=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig index 6a3851c1d1e..ca47edf3211 100644 --- a/configs/wb45n_defconfig +++ b/configs/wb45n_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x20000000 +CONFIG_SYS_MEMTEST_END=0x23e00000 CONFIG_ENV_OFFSET=0xA0000 CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL_SUPPORT=y @@ -24,8 +26,6 @@ CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x20000000 -CONFIG_SYS_MEMTEST_END=0x23e00000 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig index a75ac41be09..0ffc5b4d73a 100644 --- a/configs/wb50n_defconfig +++ b/configs/wb50n_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x21000000 +CONFIG_SYS_MEMTEST_END=0x22000000 CONFIG_ENV_OFFSET=0xA0000 CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL_SUPPORT=y @@ -24,8 +26,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x21000000 -CONFIG_SYS_MEMTEST_END=0x22000000 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 427268bd588..85d783c07cb 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_ENV_SIZE=0x80 CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MEM_RSVD_FOR_MMU=y @@ -39,8 +41,6 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_ECHO is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 7291c51c2dc..69adb0b69db 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -3,6 +3,8 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_DM_GPIO=y CONFIG_CMD_FRU=y CONFIG_DEFINE_TCM_OCM_MMAP=y @@ -18,8 +20,6 @@ CONFIG_SYS_PROMPT="Versal> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index da84c01b0a1..552f1b4dfb9 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_DM_GPIO=y CONFIG_SPL_STACK_R_ADDR=0x200000 @@ -30,8 +32,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 9e63533bb97..64989db2917 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -3,6 +3,8 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi" CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_ENV_SIZE=0x80 CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_PSU_INIT_ENABLED=y @@ -35,8 +37,6 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_CMD_DM is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 0c816de707a..e400cd4702e 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -3,6 +3,8 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_DM_GPIO=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -33,8 +35,6 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -57,6 +57,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y +CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y @@ -137,6 +138,7 @@ CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y @@ -156,5 +158,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_WDT=y CONFIG_WDT_CDNS=y CONFIG_PANIC_HANG=y +CONFIG_TPM=y CONFIG_SPL_GZIP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index bbdd1f80b7c..b77bf9a4709 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6UL=y @@ -14,8 +16,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -40,6 +40,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index 6b9fff74fd4..aee059dea0c 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6UL=y @@ -25,8 +27,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -51,6 +51,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index 94acdbed859..321a9351d28 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10800000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 @@ -28,8 +30,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -58,4 +58,5 @@ CONFIG_PCI=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index 76ec3d2fd69..ed6978e32cd 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10800000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 @@ -28,8 +30,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -56,4 +56,5 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/doc/README.marvell b/doc/README.marvell index 6f05ad4cb16..6fc5ac8a409 100644 --- a/doc/README.marvell +++ b/doc/README.marvell @@ -43,11 +43,8 @@ Build Procedure In order to prevent this, the required device-tree MUST be set during compilation. All device-tree files are located in ./arch/arm/dts/ folder. - For the EspressoBin board with populated eMMC device use - # make DEVICE_TREE=armada-3720-espressobin-emmc - - For other DB boards (MacchiatoBin, EspressoBin without soldered eMMC and 3700 DB board) - compile u-boot with just default device-tree from defconfig using: + For other DB boards (MacchiatoBin, EspressoBin and 3700 DB board) compile u-boot with + just default device-tree from defconfig using: # make diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst new file mode 100644 index 00000000000..bd4be1dbeb4 --- /dev/null +++ b/doc/board/advantech/imx8qm-rom7720-a1.rst @@ -0,0 +1,75 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the NXP i.MX8QM ROM 7720a1 board +=========================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Build imx-mkimage +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ cd imx-atf/ + $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga + $ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin + $ chmod +x imx-sc-firmware-1.1.bin + $ ./imx-sc-firmware-1.1.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin + $ chmod +x firmware-imx-8.0.bin + $ ./firmware-imx-8.0.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 + $ tar -xf imx-sc-firmware-1.1.tar.bz2 + $ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + + $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 + $ tar -xf firmware-imx-8.0.tar.bz2 + $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make imx8qm_rom7720_a1_4G_defconfig + $ make u-boot.bin + $ make flash.bin + +Flash the binary into the SD card +--------------------------------- + +Burn the flash.bin binary to SD card offset 32KB: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set Boot switch SW2: 1100. diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst new file mode 100644 index 00000000000..e9b198c5c3e --- /dev/null +++ b/doc/board/advantech/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Advantech +========= + +.. toctree:: + :maxdepth: 2 + + imx8qm-rom7720-a1.rst diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index b68db95a45f..3acd40630ea 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -105,3 +105,11 @@ configurations are: qemu-system-riscv64 -nographic -machine virt -bios spl/u-boot-spl \ -device loader,file=u-boot.itb,addr=0x80200000 + +An attached disk can be emulated by adding:: + + -device ich9-ahci,id=ahci \ + -drive if=none,file=riscv64.img,format=raw,id=mydisk \ + -device ide-hd,drive=mydisk,bus=ahci.0 + +You will have to run 'scsi scan' to use it. diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/freescale/imx8mp_evk.rst index b34742e33e7..96df6d470f4 100644 --- a/doc/board/freescale/imx8mp_evk.rst +++ b/doc/board/freescale/imx8mp_evk.rst @@ -23,7 +23,7 @@ branch: imx_5.4.3_2.0.0 .. code-block:: bash $ make PLAT=imx8mp bl31 - $ sudo cp build/imx8mp/release/bl31.bin $(srctree) + $ cp build/imx8mp/release/bl31.bin $(srctree) Get the ddr firmware -------------------- @@ -32,11 +32,11 @@ Get the ddr firmware $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin $ chmod +x firmware-imx-8.7.bin - $ ./firmware-imx-8.7 - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin + $ ./firmware-imx-8.7.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin Build U-Boot ------------ diff --git a/doc/board/index.rst b/doc/board/index.rst index 4b6a996eb1d..915f1be8a56 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -7,6 +7,7 @@ Board-specific doc :maxdepth: 2 actions/index + advantech/index AndesTech/index amlogic/index atmel/index diff --git a/doc/board/toradex/apalix-imx8x.rst b/doc/board/toradex/apalix-imx8x.rst new file mode 100644 index 00000000000..ce7dde8d006 --- /dev/null +++ b/doc/board/toradex/apalix-imx8x.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Apalis iMX8X V1.1A Module +========================== + +Quick Start +----------- + +- Build the ARM trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Load U-Boot binary using uuu +- Flash U-Boot binary into the eMMC +- Boot + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone -b toradex_imx_5.4.24_2.1.0 http://git.toradex.com/cgit/imx-atf.git + $ cd imx-atf/ + $ make PLAT=imx8qx bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/blob/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin + $ chmod +x imx-seco-3.6.3.bin + $ ./imx-seco-3.6.3.bin + +Copy the following binaries to the U-Boot folder: + +.. code-block:: bash + + $ cp imx-atf/build/imx8qx/release/bl31.bin . + $ cp imx-seco-3.6.3/firmware/seco/mx8qxb0-ahab-container.img mx8qx-ahab-container.imx8_defconfig + +Build U-Boot +------------ +.. code-block:: bash + + $ make apalis-imx8x_defconfig + $ make u-boot-dtb.imx + +Load the U-Boot Binary Using UUU +-------------------------------- + +Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``: + +https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases + +Put the module into USB recovery aka serial downloader mode, connect USB device +to your host and execute uuu: + +.. code-block:: bash + + sudo ./uuu u-boot/u-boot-dtb.imx + +Flash the U-Boot Binary into the eMMC +------------------------------------- + +Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area +partition and boot: + +.. code-block:: bash + + load mmc 1:1 $loadaddr u-boot-dtb.imx + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + mmc dev 0 1 + mmc write ${loadaddr} 0x0 ${blkcnt} diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 16b5a0770d1..abba648f868 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -7,6 +7,7 @@ Toradex :maxdepth: 2 apalix-imx8 + apalix-imx8x colibri_imx7 colibri-imx8x verdin-imx8mm diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt index da98407403d..edfe4b426c4 100644 --- a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt +++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt @@ -45,6 +45,8 @@ Required properties: - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY port#1 and must be <1> for PHY port#2, to select USB controller +Optional properties: +- vbus-supply: phandle to the regulator providing 5V vbus to the USB connector Example: usbphyc: usb-phy@5a006000 { diff --git a/doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt b/doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt index 06a9cc060f3..73871f59305 100644 --- a/doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt +++ b/doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt @@ -18,7 +18,7 @@ Pin configuration nodes are documented in pinctrl-bindings.txt Required properties for pin-configuration nodes or sub-nodes are: - groups: list of power groups to which the configuration applies. Valid groups are: - A0, A1, A2, B0, B1, B2, C0, C1 + A0, A1, A2, B3, B4, B5, C6, C7 (either this or "pinmux" must be specified) - pinmux: integer array representing pin multiplexing configuration. In addition to the 256 standard functions, each pin can also output the direction diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 5e6abca56fa..edf90ee00f3 100644 --- a/drivers/clk/clk_stm32h7.c +++ b/drivers/clk/clk_stm32h7.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 54fb09fda40..7e466d630a0 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -53,19 +53,27 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU; break; + case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: + case IMX8QM_I2C0_DIV: resource = SC_R_I2C_0; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C1_IPG_CLK: case IMX8QM_I2C1_CLK: + case IMX8QM_I2C1_DIV: resource = SC_R_I2C_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C2_IPG_CLK: case IMX8QM_I2C2_CLK: + case IMX8QM_I2C2_DIV: resource = SC_R_I2C_2; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C3_IPG_CLK: case IMX8QM_I2C3_CLK: + case IMX8QM_I2C3_DIV: resource = SC_R_I2C_3; pm_clk = SC_PM_CLK_PER; break; @@ -148,19 +156,27 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); switch (clk->id) { + case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: + case IMX8QM_I2C0_DIV: resource = SC_R_I2C_0; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C1_IPG_CLK: case IMX8QM_I2C1_CLK: + case IMX8QM_I2C1_DIV: resource = SC_R_I2C_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C2_IPG_CLK: case IMX8QM_I2C2_CLK: + case IMX8QM_I2C2_DIV: resource = SC_R_I2C_2; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C3_IPG_CLK: case IMX8QM_I2C3_CLK: + case IMX8QM_I2C3_DIV: resource = SC_R_I2C_3; pm_clk = SC_PM_CLK_PER; break; @@ -242,19 +258,27 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id); switch (clk->id) { + case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: + case IMX8QM_I2C0_DIV: resource = SC_R_I2C_0; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C1_IPG_CLK: case IMX8QM_I2C1_CLK: + case IMX8QM_I2C1_DIV: resource = SC_R_I2C_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C2_IPG_CLK: case IMX8QM_I2C2_CLK: + case IMX8QM_I2C2_DIV: resource = SC_R_I2C_2; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C3_IPG_CLK: case IMX8QM_I2C3_CLK: + case IMX8QM_I2C3_DIV: resource = SC_R_I2C_3; pm_clk = SC_PM_CLK_PER; break; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 478d76d428c..3fd863e7bd0 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -23,6 +23,8 @@ #include <linux/bitops.h> #include <linux/delay.h> +DECLARE_GLOBAL_DATA_PTR; + #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_plat { struct dtd_rockchip_rk3399_cru dtd; @@ -50,10 +52,9 @@ struct pll_div { .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; -#if defined(CONFIG_SPL_BUILD) static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); -#else +#if !defined(CONFIG_SPL_BUILD) static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); #endif @@ -1293,7 +1294,6 @@ static struct clk_ops rk3399_clk_ops = { .disable = rk3399_clk_disable, }; -#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rockchip_cru *cru) { u32 aclk_div; @@ -1371,20 +1371,30 @@ static void rkclk_init(struct rockchip_cru *cru) hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); } -#endif static int rk3399_clk_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD struct rk3399_clk_priv *priv = dev_get_priv(dev); + bool init_clocks = false; #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_plat *plat = dev_get_platdata(dev); priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif - rkclk_init(priv->cru); + +#if defined(CONFIG_SPL_BUILD) + init_clocks = true; +#elif CONFIG_IS_ENABLED(HANDOFF) + if (!(gd->flags & GD_FLG_RELOC)) { + if (!(gd->spl_handoff)) + init_clocks = true; + } #endif + + if (init_clocks) + rkclk_init(priv->cru); + return 0; } diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index b79446cc4fd..f3fc06ab31e 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -56,6 +56,8 @@ static int v3s_clk_bind(struct udevice *dev) static const struct udevice_id v3s_clk_ids[] = { { .compatible = "allwinner,sun8i-v3s-ccu", .data = (ulong)&v3s_ccu_desc }, + { .compatible = "allwinner,sun8i-v3-ccu", + .data = (ulong)&v3s_ccu_desc }, { } }; diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index efdb0f29058..0924a575f53 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -152,7 +152,7 @@ void device_free(struct udevice *dev) static bool flags_remove(uint flags, uint drv_flags) { if ((flags & DM_REMOVE_NORMAL) || - (flags & (drv_flags & (DM_FLAG_ACTIVE_DMA | DM_FLAG_OS_PREPARE)))) + (flags && (drv_flags & (DM_FLAG_ACTIVE_DMA | DM_FLAG_OS_PREPARE)))) return true; return false; diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index f75d97b15c4..5f62489a90f 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -47,6 +47,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P5020 || \ ARCH_P5040 || \ ARCH_LX2160A || \ + ARCH_LX2162A || \ ARCH_T4160 default 1 diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index b7427fc4f0d..121dc54f546 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -20,9 +20,8 @@ config DFU_WRITE_ALT config DFU_TFTP bool "DFU via TFTP" - select DFU_WRITE_ALT - select DFU_OVER_TFTP select UPDATE_COMMON + select DFU_OVER_TFTP help This option allows performing update of DFU-managed medium with data sent via TFTP boot. diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index b885cfb57e5..51e1efd7014 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -212,11 +212,11 @@ static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, } else if (flags & GPIOD_IS_IN) { stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN); - if (flags & GPIOD_PULL_UP) - stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP); - else if (flags & GPIOD_PULL_DOWN) - stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN); } + if (flags & GPIOD_PULL_UP) + stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP); + else if (flags & GPIOD_PULL_DOWN) + stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN); return 0; } @@ -243,16 +243,16 @@ static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset, break; case STM32_GPIO_MODE_IN: dir_flags |= GPIOD_IS_IN; - switch (stm32_gpio_get_pupd(regs, idx)) { - case STM32_GPIO_PUPD_UP: - dir_flags |= GPIOD_PULL_UP; - break; - case STM32_GPIO_PUPD_DOWN: - dir_flags |= GPIOD_PULL_DOWN; - break; - default: - break; - } + break; + default: + break; + } + switch (stm32_gpio_get_pupd(regs, idx)) { + case STM32_GPIO_PUPD_UP: + dir_flags |= GPIOD_PULL_UP; + break; + case STM32_GPIO_PUPD_DOWN: + dir_flags |= GPIOD_PULL_DOWN; break; default: break; diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 3efccf496fc..02c3471b568 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -351,6 +351,7 @@ static const struct udevice_id sunxi_gpio_ids[] = { ID("allwinner,sun8i-a83t-pinctrl", a_all), ID("allwinner,sun8i-h3-pinctrl", a_all), ID("allwinner,sun8i-r40-pinctrl", a_all), + ID("allwinner,sun8i-v3-pinctrl", a_all), ID("allwinner,sun8i-v3s-pinctrl", a_all), ID("allwinner,sun9i-a80-pinctrl", a_all), ID("allwinner,sun50i-a64-pinctrl", a_all), diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 8ae54e1e93b..37958083af9 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -342,6 +342,13 @@ config SYS_I2C_NEXELL have several I2C ports and all are provided, controlled by the device tree. +config SYS_I2C_OCORES + bool "ocores I2C driver" + depends on DM_I2C + help + Add support for ocores I2C controller. For details see + https://opencores.org/projects/i2c + config SYS_I2C_OMAP24XX bool "TI OMAP2+ I2C driver" depends on ARCH_OMAP2PLUS || ARCH_K3 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index b37198036c0..1aac5c481e2 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o +obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 791f32e971c..c54989504ea 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -774,10 +774,12 @@ int designware_i2c_ofdata_to_platdata(struct udevice *bus) dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns); ret = reset_get_bulk(bus, &priv->resets); - if (ret) - dev_warn(bus, "Can't get reset: %d\n", ret); - else + if (ret) { + if (ret != -ENOTSUPP) + dev_warn(bus, "Can't get reset: %d\n", ret); + } else { reset_deassert_bulk(&priv->resets); + } #if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(bus, 0, &priv->clk); diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index fdb8fd42e5c..14c594d648b 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -823,7 +823,8 @@ static int mvtwsi_i2c_bind(struct udevice *bus) struct mvtwsi_registers *twsi = dev_read_addr_ptr(bus); /* Disable the hidden slave in i2c0 of these platforms */ - if ((IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARCH_KIRKWOOD)) + if ((IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARCH_KIRKWOOD) + || IS_ENABLED(CONFIG_ARMADA_8K)) && bus->req_seq == 0) twsi_disable_i2c_slave(twsi); diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c new file mode 100644 index 00000000000..c4f2cc43f9e --- /dev/null +++ b/drivers/i2c/ocores_i2c.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ocores-i2c.c: I2C bus driver for OpenCores I2C controller + * (https://opencores.org/projects/i2c) + * + * (C) Copyright Peter Korsgaard <peter@korsgaard.com> + * + * Copyright (C) 2020 SiFive, Inc. + * Pragnesh Patel <pragnesh.patel@sifive.com> + * + * Support for the GRLIB port of the controller by + * Andreas Larsson <andreas@gaisler.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <i2c.h> +#include <linux/io.h> +#include <linux/compat.h> +#include <linux/log2.h> +#include <linux/delay.h> + +/* registers */ +#define OCI2C_PRELOW 0 +#define OCI2C_PREHIGH 1 +#define OCI2C_CONTROL 2 +#define OCI2C_DATA 3 +#define OCI2C_CMD 4 /* write only */ +#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ + +#define OCI2C_CTRL_IEN 0x40 +#define OCI2C_CTRL_EN 0x80 + +#define OCI2C_CMD_START 0x91 +#define OCI2C_CMD_STOP 0x41 +#define OCI2C_CMD_READ 0x21 +#define OCI2C_CMD_WRITE 0x11 +#define OCI2C_CMD_READ_ACK 0x21 +#define OCI2C_CMD_READ_NACK 0x29 +#define OCI2C_CMD_IACK 0x01 + +#define OCI2C_STAT_IF 0x01 +#define OCI2C_STAT_TIP 0x02 +#define OCI2C_STAT_ARBLOST 0x20 +#define OCI2C_STAT_BUSY 0x40 +#define OCI2C_STAT_NACK 0x80 + +#define STATE_DONE 0 +#define STATE_START 1 +#define STATE_WRITE 2 +#define STATE_READ 3 +#define STATE_ERROR 4 + +#define TYPE_OCORES 0 +#define TYPE_GRLIB 1 + +#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ + +struct ocores_i2c_bus { + void __iomem *base; + u32 reg_shift; + u32 reg_io_width; + unsigned long flags; + struct i2c_msg *msg; + int pos; + int nmsgs; + int state; /* see STATE_ */ + struct clk clk; + int ip_clk_khz; + int bus_clk_khz; + void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value); + u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg); +}; + +DECLARE_GLOBAL_DATA_PTR; + +/* Boolean attribute values */ +enum { + FALSE = 0, + TRUE, +}; + +static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + writeb(value, i2c->base + (reg << i2c->reg_shift)); +} + +static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + writew(value, i2c->base + (reg << i2c->reg_shift)); +} + +static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + writel(value, i2c->base + (reg << i2c->reg_shift)); +} + +static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + out_be16(i2c->base + (reg << i2c->reg_shift), value); +} + +static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + out_be32(i2c->base + (reg << i2c->reg_shift), value); +} + +static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg) +{ + return readb(i2c->base + (reg << i2c->reg_shift)); +} + +static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg) +{ + return readw(i2c->base + (reg << i2c->reg_shift)); +} + +static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg) +{ + return readl(i2c->base + (reg << i2c->reg_shift)); +} + +static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg) +{ + return in_be16(i2c->base + (reg << i2c->reg_shift)); +} + +static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg) +{ + return in_be32(i2c->base + (reg << i2c->reg_shift)); +} + +static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + i2c->setreg(i2c, reg, value); +} + +static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg) +{ + return i2c->getreg(i2c, reg); +} + +static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg) +{ + return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0); +} + +static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat) +{ + struct i2c_msg *msg = i2c->msg; + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { + /* stop has been sent */ + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); + return; + } + + /* error? */ + if (stat & OCI2C_STAT_ARBLOST) { + i2c->state = STATE_ERROR; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + return; + } + + if (i2c->state == STATE_START || i2c->state == STATE_WRITE) { + i2c->state = + (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; + + if (stat & OCI2C_STAT_NACK) { + i2c->state = STATE_ERROR; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + return; + } + } else { + msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); + } + + /* end of msg? */ + if (i2c->pos == msg->len) { + i2c->nmsgs--; + i2c->msg++; + i2c->pos = 0; + msg = i2c->msg; + + if (i2c->nmsgs) { /* end? */ + /* send start? */ + if (!(msg->flags & I2C_M_NOSTART)) { + u8 addr = i2c_8bit_addr_from_msg(msg); + + i2c->state = STATE_START; + + oc_setreg(i2c, OCI2C_DATA, addr); + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); + return; + } + i2c->state = (msg->flags & I2C_M_RD) + ? STATE_READ : STATE_WRITE; + } else { + i2c->state = STATE_DONE; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + return; + } + } + + if (i2c->state == STATE_READ) { + oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ? + OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); + } else { + oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); + } +} + +static irqreturn_t ocores_isr(int irq, void *dev_id) +{ + struct ocores_i2c_bus *i2c = dev_id; + u8 stat = oc_getreg(i2c, OCI2C_STATUS); + + if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) { + if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY)) + return IRQ_NONE; + } else if (!(stat & OCI2C_STAT_IF)) { + return IRQ_NONE; + } + ocores_process(i2c, stat); + + return IRQ_HANDLED; +} + +/** + * Wait until something change in a given register + * @i2c: ocores I2C device instance + * @reg: register to query + * @mask: bitmask to apply on register value + * @val: expected result + * @msec: timeout in msec + * + * Timeout is necessary to avoid to stay here forever when the chip + * does not answer correctly. + * + * Return: 0 on success, -ETIMEDOUT on timeout + */ +static int ocores_wait(struct ocores_i2c_bus *i2c, + int reg, u8 mask, u8 val, + const unsigned long msec) +{ + u32 count = 0; + + while (1) { + u8 status = oc_getreg(i2c, reg); + + if ((status & mask) == val) + break; + + udelay(1); + count += 1; + + if (count == (1000 * msec)) + return -ETIMEDOUT; + } + return 0; +} + +/** + * Wait until is possible to process some data + * @i2c: ocores I2C device instance + * + * Used when the device is in polling mode (interrupts disabled). + * + * Return: 0 on success, -ETIMEDOUT on timeout + */ +static int ocores_poll_wait(struct ocores_i2c_bus *i2c) +{ + u8 mask; + int err; + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { + /* transfer is over */ + mask = OCI2C_STAT_BUSY; + } else { + /* on going transfer */ + mask = OCI2C_STAT_TIP; + /* + * We wait for the data to be transferred (8bit), + * then we start polling on the ACK/NACK bit + */ + udelay((8 * 1000) / i2c->bus_clk_khz); + } + + /* + * once we are here we expect to get the expected result immediately + * so if after 1ms we timeout then something is broken. + */ + err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1); + if (err) + debug("%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", + __func__, mask); + return err; +} + +/** + * It handles an IRQ-less transfer + * @i2c: ocores I2C device instance + * + * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same + * (only that IRQ are not produced). This means that we can re-use entirely + * ocores_isr(), we just add our polling code around it. + * + * It can run in atomic context + */ +static void ocores_process_polling(struct ocores_i2c_bus *i2c) +{ + while (1) { + irqreturn_t ret; + int err; + + err = ocores_poll_wait(i2c); + if (err) { + i2c->state = STATE_ERROR; + break; /* timeout */ + } + + ret = ocores_isr(-1, i2c); + if (ret == IRQ_NONE) { + break; /* all messages have been transferred */ + } else { + if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) + if (i2c->state == STATE_DONE) + break; + } + } +} + +static int ocores_xfer_core(struct ocores_i2c_bus *i2c, + struct i2c_msg *msgs, int num, bool polling) +{ + u8 ctrl; + + ctrl = oc_getreg(i2c, OCI2C_CONTROL); + + if (polling) + oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); + + i2c->msg = msgs; + i2c->pos = 0; + i2c->nmsgs = num; + i2c->state = STATE_START; + + oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); + + if (polling) + ocores_process_polling(i2c); + + return (i2c->state == STATE_DONE) ? num : -EIO; +} + +static int ocores_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + struct ocores_i2c_bus *bus = dev_get_priv(dev); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + + ret = ocores_xfer_core(bus, msg, nmsgs, 1); + + if (ret != nmsgs) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + + return 0; +} + +static int ocores_i2c_enable_clk(struct udevice *dev) +{ + struct ocores_i2c_bus *bus = dev_get_priv(dev); + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &bus->clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&bus->clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&bus->clk); + if (!clk_rate) + return -EINVAL; + + bus->ip_clk_khz = clk_rate / 1000; + + clk_free(&bus->clk); + + return 0; +} + +static int ocores_init(struct udevice *dev, struct ocores_i2c_bus *bus) +{ + int prescale; + int diff; + u8 ctrl = oc_getreg(bus, OCI2C_CONTROL); + + /* make sure the device is disabled */ + ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); + oc_setreg(bus, OCI2C_CONTROL, ctrl); + + prescale = (bus->ip_clk_khz / (5 * bus->bus_clk_khz)) - 1; + prescale = clamp(prescale, 0, 0xffff); + + diff = bus->ip_clk_khz / (5 * (prescale + 1)) - bus->bus_clk_khz; + if (abs(diff) > bus->bus_clk_khz / 10) { + debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n", + bus->ip_clk_khz, bus->bus_clk_khz); + return -EINVAL; + } + + oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff); + oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8); + + /* Init the device */ + oc_setreg(bus, OCI2C_CMD, OCI2C_CMD_IACK); + oc_setreg(bus, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); + + return 0; +} + +/* + * Read and write functions for the GRLIB port of the controller. Registers are + * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one + * register. The subsequent registers have their offsets decreased accordingly. + */ +static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg) +{ + u32 rd; + int rreg = reg; + + if (reg != OCI2C_PRELOW) + rreg--; + rd = in_be32(i2c->base + (rreg << i2c->reg_shift)); + if (reg == OCI2C_PREHIGH) + return (u8)(rd >> 8); + else + return (u8)rd; +} + +static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value) +{ + u32 curr, wr; + int rreg = reg; + + if (reg != OCI2C_PRELOW) + rreg--; + if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { + curr = in_be32(i2c->base + (rreg << i2c->reg_shift)); + if (reg == OCI2C_PRELOW) + wr = (curr & 0xff00) | value; + else + wr = (((u32)value) << 8) | (curr & 0xff); + } else { + wr = value; + } + out_be32(i2c->base + (rreg << i2c->reg_shift), wr); +} + +static int ocores_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + int prescale; + int diff; + struct ocores_i2c_bus *bus = dev_get_priv(dev); + + /* speed in Khz */ + speed = speed / 1000; + + prescale = (bus->ip_clk_khz / (5 * speed)) - 1; + prescale = clamp(prescale, 0, 0xffff); + + diff = bus->ip_clk_khz / (5 * (prescale + 1)) - speed; + if (abs(diff) > speed / 10) { + debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n", + bus->ip_clk_khz, speed); + return -EINVAL; + } + + oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff); + oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8); + + bus->bus_clk_khz = speed; + return 0; +} + +int ocores_i2c_get_bus_speed(struct udevice *dev) +{ + struct ocores_i2c_bus *bus = dev_get_priv(dev); + + return (bus->bus_clk_khz * 1000); +} + +static const struct dm_i2c_ops ocores_i2c_ops = { + .xfer = ocores_i2c_xfer, + .set_bus_speed = ocores_i2c_set_bus_speed, + .get_bus_speed = ocores_i2c_get_bus_speed, +}; + +static int ocores_i2c_probe(struct udevice *dev) +{ + struct ocores_i2c_bus *bus = dev_get_priv(dev); + bool clock_frequency_present; + u32 val; + u32 clock_frequency_khz; + int ret; + + bus->base = (void __iomem *)devfdt_get_addr(dev); + + if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) { + /* no 'reg-shift', check for deprecated 'regstep' */ + ret = dev_read_u32(dev, "regstep", &val); + if (ret) { + dev_err(dev, + "missing both reg-shift and regstep property: %d\n", ret); + return -EINVAL; + } else { + bus->reg_shift = ilog2(val); + dev_warn(dev, + "regstep property deprecated, use reg-shift\n"); + } + } + + if (dev_read_u32(dev, "clock-frequency", &val)) { + bus->bus_clk_khz = 100; + clock_frequency_present = FALSE; + } else { + bus->bus_clk_khz = val / 1000; + clock_frequency_khz = val / 1000; + clock_frequency_present = TRUE; + } + + ret = ocores_i2c_enable_clk(dev); + if (ret) + return ret; + + if (bus->ip_clk_khz == 0) { + if (dev_read_u32(dev, "opencores,ip-clock-frequency", &val)) { + if (!clock_frequency_present) { + dev_err(dev, + "Missing required parameter 'opencores,ip-clock-frequency'\n"); + clk_disable(&bus->clk); + return -ENODEV; + } + + bus->ip_clk_khz = clock_frequency_khz; + dev_warn(dev, + "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); + } else { + bus->ip_clk_khz = val / 1000; + if (clock_frequency_present) + bus->bus_clk_khz = clock_frequency_khz; + } + } + + bus->reg_io_width = dev_read_u32_default(dev, "reg-io-width", 1); + + if (dev_get_driver_data(dev) == TYPE_GRLIB) { + debug("GRLIB variant of i2c-ocores\n"); + bus->setreg = oc_setreg_grlib; + bus->getreg = oc_getreg_grlib; + } + + if (!bus->setreg || !bus->getreg) { + bool be = (cpu_to_be32(0x12345678) == 0x12345678); + + switch (bus->reg_io_width) { + case 1: + bus->setreg = oc_setreg_8; + bus->getreg = oc_getreg_8; + break; + + case 2: + bus->setreg = be ? oc_setreg_16be : oc_setreg_16; + bus->getreg = be ? oc_getreg_16be : oc_getreg_16; + break; + + case 4: + bus->setreg = be ? oc_setreg_32be : oc_setreg_32; + bus->getreg = be ? oc_getreg_32be : oc_getreg_32; + break; + + default: + debug("Unsupported I/O width (%d)\n", + bus->reg_io_width); + ret = -EINVAL; + goto err_clk; + } + } + + /* + * Set OCORES_FLAG_BROKEN_IRQ to enable workaround for + * FU540-C000 SoC in polling mode. + * Since the SoC does have an interrupt, its DT has an interrupt + * property - But this should be bypassed as the IRQ logic in this + * SoC is broken. + */ + + if (device_is_compatible(dev, "sifive,fu540-c000-i2c")) + bus->flags |= OCORES_FLAG_BROKEN_IRQ; + + ret = ocores_init(dev, bus); + if (ret) + goto err_clk; + + return 0; + +err_clk: + clk_disable(&bus->clk); + return ret; +} + +static const struct udevice_id ocores_i2c_ids[] = { +{ .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES }, +{ .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB }, +{ .compatible = "sifive,fu540-c000-i2c" }, +{ .compatible = "sifive,i2c0" }, +}; + +U_BOOT_DRIVER(i2c_ocores) = { + .name = "i2c_ocores", + .id = UCLASS_I2C, + .of_match = ocores_i2c_ids, + .probe = ocores_i2c_probe, + .priv_auto_alloc_size = sizeof(struct ocores_i2c_bus), + .ops = &ocores_i2c_ops, +}; diff --git a/drivers/led/led_bcm6858.c b/drivers/led/led_bcm6858.c index b415d8b2b40..511185ffad7 100644 --- a/drivers/led/led_bcm6858.c +++ b/drivers/led/led_bcm6858.c @@ -40,8 +40,8 @@ #define LED_FLASH_RATE_CONTROL_REG0 0x10 /* Soft LED input register */ #define LED_SW_LED_IP_REG 0xb8 -/* Soft LED input polarity register */ -#define LED_SW_LED_IP_PPOL_REG 0xbc +/* Parallel LED Output Polarity Register */ +#define LED_PLED_OP_PPOL_REG 0xc0 struct bcm6858_led_priv { void __iomem *regs; @@ -198,9 +198,9 @@ static int bcm6858_led_probe(struct udevice *dev) /* configure the polarity */ if (dev_read_bool(dev, "active-low")) - clrbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin); + clrbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin); else - setbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin); + setbits_32(regs + LED_PLED_OP_PPOL_REG, 1 << pin); } return 0; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index c3674908ee8..1b22f1883ee 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -495,18 +495,18 @@ int cros_ec_read_current_image(struct udevice *dev, } static int cros_ec_wait_on_hash_done(struct udevice *dev, + struct ec_params_vboot_hash *p, struct ec_response_vboot_hash *hash) { - struct ec_params_vboot_hash p; ulong start; start = get_timer(0); while (hash->status == EC_VBOOT_HASH_STATUS_BUSY) { mdelay(50); /* Insert some reasonable delay */ - p.cmd = EC_VBOOT_HASH_GET; - if (ec_command(dev, EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), - hash, sizeof(*hash)) < 0) + p->cmd = EC_VBOOT_HASH_GET; + if (ec_command(dev, EC_CMD_VBOOT_HASH, 0, p, sizeof(*p), hash, + sizeof(*hash)) < 0) return -1; if (get_timer(start) > CROS_EC_CMD_HASH_TIMEOUT_MS) { @@ -530,7 +530,7 @@ int cros_ec_read_hash(struct udevice *dev, uint hash_offset, return -1; /* If the EC is busy calculating the hash, fidget until it's done. */ - rv = cros_ec_wait_on_hash_done(dev, hash); + rv = cros_ec_wait_on_hash_done(dev, &p, hash); if (rv) return rv; @@ -553,9 +553,13 @@ int cros_ec_read_hash(struct udevice *dev, uint hash_offset, hash, sizeof(*hash)) < 0) return -1; - rv = cros_ec_wait_on_hash_done(dev, hash); + rv = cros_ec_wait_on_hash_done(dev, &p, hash); if (rv) return rv; + if (hash->status != EC_VBOOT_HASH_STATUS_DONE) { + log_err("Hash did not complete, status=%d\n", hash->status); + return -EIO; + } debug("%s: hash done\n", __func__); diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index 63702f90fbc..e0002b9753f 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -25,13 +25,16 @@ #define debug_trace(fmt, b...) #endif +/* Timeout waiting for a flash erase command to complete */ +static const int CROS_EC_CMD_TIMEOUT_MS = 5000; + static int wait_for_sync(struct cros_ec_dev *dev) { unsigned long start; start = get_timer(0); while (inb(EC_LPC_ADDR_HOST_CMD) & EC_LPC_STATUS_BUSY_MASK) { - if (get_timer(start) > 1000) { + if (get_timer(start) > CROS_EC_CMD_TIMEOUT_MS) { debug("%s: Timeout waiting for CROS_EC sync\n", __func__); return -1; diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index a191f061b89..d72db3eace9 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -460,6 +460,14 @@ static int process_cmd(struct ec_state *ec, case EC_CMD_ENTERING_MODE: len = 0; break; + case EC_CMD_GET_NEXT_EVENT: { + struct ec_response_get_next_event *resp = resp_data; + + resp->event_type = EC_MKBP_EVENT_KEY_MATRIX; + cros_ec_keyscan(ec, resp->data.key_matrix); + len = sizeof(*resp); + break; + } default: printf(" ** Unknown EC command %#02x\n", req_hdr->command); return -1; diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index b82fe54c600..86275454be0 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 642784e1f35..a18316eda71 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -70,7 +70,9 @@ struct fsl_esdhc { uint sdtimingctl; /* SD timing control register */ char reserved8[20]; /* reserved */ uint dllcfg0; /* DLL config 0 register */ - char reserved9[680]; /* reserved */ + char reserved9[12]; /* reserved */ + uint dllstat0; /* DLL status 0 register */ + char reserved10[664];/* reserved */ uint esdhcctl; /* eSDHC control register */ }; @@ -617,9 +619,11 @@ static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv) esdhc_tuning_block_enable(priv, false); } -static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) +static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) { struct fsl_esdhc *regs = priv->esdhc_regs; + ulong start; + u32 val; /* Exit HS400 mode before setting any other mode */ if (esdhc_read32(®s->tbctl) & HS400_MODE && @@ -640,17 +644,33 @@ static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL); esdhc_setbits32(®s->dllcfg0, DLL_ENABLE); + + esdhc_setbits32(®s->dllcfg0, DLL_RESET); + udelay(1); + esdhc_clrbits32(®s->dllcfg0, DLL_RESET); + + start = get_timer(0); + val = DLL_STS_SLV_LOCK; + while (!(esdhc_read32(®s->dllstat0) & val)) { + if (get_timer(start) > 1000) { + printf("fsl_esdhc: delay chain lock timeout\n"); + return -ETIMEDOUT; + } + } + esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST); esdhc_clock_control(priv, false); esdhc_flush_async_fifo(priv); } esdhc_clock_control(priv, true); + return 0; } static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) { struct fsl_esdhc *regs = priv->esdhc_regs; + int ret; if (priv->is_sdhc_per_clk) { /* Select to use peripheral clock */ @@ -667,7 +687,9 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) set_sysctl(priv, mmc, mmc->clock); /* Set timing */ - esdhc_set_timing(priv, mmc->selected_mode); + ret = esdhc_set_timing(priv, mmc->selected_mode); + if (ret) + return ret; /* Set the bus width */ esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); @@ -715,7 +737,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ - mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); + set_sysctl(priv, mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 22040c67a84..e5409ade1bc 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -760,7 +760,6 @@ static int esdhc_set_timing(struct mmc *mmc) case MMC_HS_400_ES: mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; esdhc_write32(®s->mixctrl, mixctrl); - esdhc_set_strobe_dll(mmc); break; case MMC_HS: case MMC_HS_52: @@ -933,6 +932,23 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) int ret __maybe_unused; u32 clock; +#ifdef MMC_SUPPORTS_TUNING + /* + * call esdhc_set_timing() before update the clock rate, + * This is because current we support DDR and SDR mode, + * Once the DDR_EN bit is set, the card clock will be + * divide by 2 automatically. So need to do this before + * setting clock rate. + */ + if (priv->mode != mmc->selected_mode) { + ret = esdhc_set_timing(mmc); + if (ret) { + printf("esdhc_set_timing error %d\n", ret); + return ret; + } + } +#endif + /* Set the clock speed */ clock = mmc->clock; if (clock < mmc->cfg->f_min) @@ -957,13 +973,13 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #endif } - if (priv->mode != mmc->selected_mode) { - ret = esdhc_set_timing(mmc); - if (ret) { - printf("esdhc_set_timing error %d\n", ret); - return ret; - } - } + /* + * For HS400/HS400ES mode, make sure set the strobe dll in the + * target clock rate. So call esdhc_set_strobe_dll() after the + * clock updated. + */ + if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) + esdhc_set_strobe_dll(mmc); if (priv->signal_voltage != mmc->signal_voltage) { ret = esdhc_set_voltage(mmc); @@ -1646,6 +1662,20 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev) } #endif +static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, + int timeout_us) +{ + int ret; + u32 tmp; + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + struct fsl_esdhc *regs = priv->esdhc_regs; + + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, + !!(tmp & PRSSTAT_DAT0) == !!state, + timeout_us); + return ret; +} + static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, @@ -1656,6 +1686,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe, #endif + .wait_dat0 = fsl_esdhc_wait_dat0, }; #endif diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 719dd1e5e57..a5e9ac5637b 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -13,9 +13,17 @@ #include <mmc.h> #include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/sd_emmc.h> #include <linux/delay.h> #include <linux/log2.h> +#include "meson_gx_mmc.h" + +bool meson_gx_mmc_is_compatible(struct udevice *dev, + enum meson_gx_mmc_compatible family) +{ + enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); + + return compat == family; +} static inline void *get_regbase(const struct mmc *mmc) { @@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc) if (!mmc->clock) return; + /* TOFIX This should use the proper clock taken from DT */ + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ if (mmc->clock > 16000000) { clk = SD_EMMC_CLKSRC_DIV2; @@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock); - /* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; + /* + * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180 + * If CLK_CO_PHASE_270 is used, it's more stable than other. + * Other SoCs use CLK_CO_PHASE_180 by default. + * It needs to find what is a proper value about each SoCs. + */ + if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) + meson_mmc_clk |= CLK_CO_PHASE_270; + else + meson_mmc_clk |= CLK_CO_PHASE_180; /* 180 phase tx clock */ meson_mmc_clk |= CLK_TX_PHASE_000; @@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev) } static const struct udevice_id meson_mmc_match[] = { - { .compatible = "amlogic,meson-gx-mmc" }, - { .compatible = "amlogic,meson-axg-mmc" }, + { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, + { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, + { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, { /* sentinel */ } }; diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/drivers/mmc/meson_gx_mmc.h index 1e9f8cf498b..92aec5329f6 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/drivers/mmc/meson_gx_mmc.h @@ -3,14 +3,16 @@ * (C) Copyright 2016 Carlo Caione <carlo@caione.org> */ -#ifndef __SD_EMMC_H__ -#define __SD_EMMC_H__ +#ifndef __MESON_GX_MMC_H__ +#define __MESON_GX_MMC_H__ #include <mmc.h> -#ifndef __ASSEMBLY__ #include <linux/bitops.h> -#endif +enum meson_gx_mmc_compatible { + MMC_COMPATIBLE_GX, + MMC_COMPATIBLE_SM1, +}; #define SDIO_PORT_A 0 #define SDIO_PORT_B 1 diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a47700e313c..a6394bcf308 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -207,26 +207,65 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) } #endif +/** + * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error + * + * @dev: device to receive the command + * @cmd: command to send + * @data: additional data to send/receive + * @retries: how many times to retry; mmc_send_cmd is always called at least + * once + * @return 0 if ok, -ve on error + */ +static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data, uint retries) +{ + int ret; + + do { + ret = mmc_send_cmd(mmc, cmd, data); + } while (ret && retries--); + + return ret; +} + +/** + * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a + * specific quirk is enabled + * + * @dev: device to receive the command + * @cmd: command to send + * @data: additional data to send/receive + * @quirk: retry only if this quirk is enabled + * @retries: how many times to retry; mmc_send_cmd is always called at least + * once + * @return 0 if ok, -ve on error + */ +static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data, u32 quirk, uint retries) +{ + if (CONFIG_IS_ENABLED(MMC_QUIRKS) && mmc->quirks & quirk) + return mmc_send_cmd_retry(mmc, cmd, data, retries); + else + return mmc_send_cmd(mmc, cmd, data); +} + int mmc_send_status(struct mmc *mmc, unsigned int *status) { struct mmc_cmd cmd; - int err, retries = 5; + int ret; cmd.cmdidx = MMC_CMD_SEND_STATUS; cmd.resp_type = MMC_RSP_R1; if (!mmc_host_is_spi(mmc)) cmd.cmdarg = mmc->rca << 16; - while (retries--) { - err = mmc_send_cmd(mmc, &cmd, NULL); - if (!err) { - mmc_trace_state(mmc, &cmd); - *status = cmd.response[0]; - return 0; - } - } + ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4); mmc_trace_state(mmc, &cmd); - return -ECOMM; + if (!ret) + *status = cmd.response[0]; + + return ret; } int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) @@ -274,7 +313,6 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd; - int err; if (mmc->ddr_mode) return 0; @@ -283,24 +321,8 @@ int mmc_set_blocklen(struct mmc *mmc, int len) cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = len; - err = mmc_send_cmd(mmc, &cmd, NULL); - -#ifdef CONFIG_MMC_QUIRKS - if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) { - int retries = 4; - /* - * It has been seen that SET_BLOCKLEN may fail on the first - * attempt, let's try a few more time - */ - do { - err = mmc_send_cmd(mmc, &cmd, NULL); - if (!err) - break; - } while (retries--); - } -#endif - - return err; + return mmc_send_cmd_quirks(mmc, &cmd, NULL, + MMC_QUIRK_RETRY_SET_BLOCKLEN, 4); } #ifdef MMC_SUPPORTS_TUNING @@ -771,7 +793,6 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS; bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) && (index == EXT_CSD_PART_CONF); - int retries = 3; int ret; if (mmc->gen_cmd6_time) @@ -786,10 +807,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, (index << 16) | (value << 8); - do { - ret = mmc_send_cmd(mmc, &cmd, NULL); - } while (ret && retries-- > 0); - + ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3); if (ret) return ret; @@ -1287,22 +1305,15 @@ static int sd_get_capabilities(struct mmc *mmc) cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = 0; - timeout = 3; - -retry_scr: data.dest = (char *)scr; data.blocksize = 8; data.blocks = 1; data.flags = MMC_DATA_READ; - err = mmc_send_cmd(mmc, &cmd, &data); - - if (err) { - if (timeout--) - goto retry_scr; + err = mmc_send_cmd_retry(mmc, &cmd, &data, 3); + if (err) return err; - } mmc->scr[0] = __be32_to_cpu(scr[0]); mmc->scr[1] = __be32_to_cpu(scr[1]); @@ -1463,28 +1474,13 @@ static int sd_read_ssr(struct mmc *mmc) struct mmc_cmd cmd; ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); struct mmc_data data; - int timeout = 3; unsigned int au, eo, et, es; cmd.cmdidx = MMC_CMD_APP_CMD; cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = mmc->rca << 16; - err = mmc_send_cmd(mmc, &cmd, NULL); -#ifdef CONFIG_MMC_QUIRKS - if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) { - int retries = 4; - /* - * It has been seen that APP_CMD may fail on the first - * attempt, let's try a few more times - */ - do { - err = mmc_send_cmd(mmc, &cmd, NULL); - if (!err) - break; - } while (retries--); - } -#endif + err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4); if (err) return err; @@ -1492,19 +1488,14 @@ static int sd_read_ssr(struct mmc *mmc) cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = 0; -retry_ssr: data.dest = (char *)ssr; data.blocksize = 64; data.blocks = 1; data.flags = MMC_DATA_READ; - err = mmc_send_cmd(mmc, &cmd, &data); - if (err) { - if (timeout--) - goto retry_ssr; - + err = mmc_send_cmd_retry(mmc, &cmd, &data, 3); + if (err) return err; - } for (i = 0; i < 16; i++) ssr[i] = be32_to_cpu(ssr[i]); @@ -2179,7 +2170,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) err = mmc_execute_tuning(mmc, mwt->tuning); if (err) { - pr_debug("tuning failed\n"); + pr_debug("tuning failed : %d\n", err); goto error; } } @@ -2200,7 +2191,7 @@ error: } } - pr_err("unable to select a mode\n"); + pr_err("unable to select a mode : %d\n", err); return -ENOTSUPP; } @@ -2441,23 +2432,7 @@ static int mmc_startup(struct mmc *mmc) cmd.resp_type = MMC_RSP_R2; cmd.cmdarg = 0; - err = mmc_send_cmd(mmc, &cmd, NULL); - -#ifdef CONFIG_MMC_QUIRKS - if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) { - int retries = 4; - /* - * It has been seen that SEND_CID may fail on the first - * attempt, let's try a few more time - */ - do { - err = mmc_send_cmd(mmc, &cmd, NULL); - if (!err) - break; - } while (retries--); - } -#endif - + err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4); if (err) return err; @@ -2745,8 +2720,8 @@ static int mmc_power_on(struct mmc *mmc) if (mmc->vmmc_supply) { int ret = regulator_set_enable(mmc->vmmc_supply, true); - if (ret) { - puts("Error enabling VMMC supply\n"); + if (ret && ret != -EACCES) { + printf("Error enabling VMMC supply : %d\n", ret); return ret; } } @@ -2761,8 +2736,8 @@ static int mmc_power_off(struct mmc *mmc) if (mmc->vmmc_supply) { int ret = regulator_set_enable(mmc->vmmc_supply, false); - if (ret) { - pr_debug("Error disabling VMMC supply\n"); + if (ret && ret != -EACCES) { + pr_debug("Error disabling VMMC supply : %d\n", ret); return ret; } } @@ -2866,7 +2841,7 @@ retry: if (err) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("Card did not respond to voltage select!\n"); + pr_err("Card did not respond to voltage select! : %d\n", err); #endif return -EOPNOTSUPP; } diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 5578feebef7..c3a1b344427 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 77871d5afc9..1f1b6cf4fb5 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 36daef01aec..09daa0dd36e 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -2657,6 +2657,7 @@ int onenand_probe(struct mtd_info *mtd) else mtd->size = this->chipsize; + mtd->type = ONENAND_IS_MLC(this) ? MTD_MLCNANDFLASH : MTD_NANDFLASH; mtd->flags = MTD_CAP_NANDFLASH; mtd->_erase = onenand_erase; mtd->_read_oob = onenand_read_oob; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index bc9d4f7e9f8..09e81960488 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -278,6 +278,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig index 2cf651d3b3e..ae4c35799bf 100644 --- a/drivers/net/fsl-mc/Kconfig +++ b/drivers/net/fsl-mc/Kconfig @@ -4,7 +4,7 @@ menuconfig FSL_MC_ENET bool "NXP Management Complex" - depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A default y select RESV_RAM help @@ -17,7 +17,7 @@ if FSL_MC_ENET config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 1d85b2cfa8a..52ab828f0b8 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -7,3 +7,4 @@ obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o +obj-$(CONFIG_ARCH_LX2162A) += lx2160a.o diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index d414c750d42..41999e176d4 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -10,6 +10,8 @@ * files. */ +#include <dm.h> +#include <dm/device-internal.h> #include <image.h> #include <log.h> #include <malloc.h> @@ -24,6 +26,9 @@ #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" static const void *pfe_fit_addr; +#ifdef CONFIG_CHAIN_OF_TRUST +static const void *pfe_esbc_hdr_addr; +#endif /* * PFE elf firmware loader. @@ -169,7 +174,7 @@ int pfe_spi_flash_init(void) struct spi_flash *pfe_flash; struct udevice *new; int ret = 0; - void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH); if (!addr) return -ENOMEM; @@ -179,21 +184,56 @@ int pfe_spi_flash_init(void) CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE, &new); + if (ret) { + printf("SF: failed to probe spi\n"); + free(addr); + device_remove(new, DM_REMOVE_NORMAL); + return ret; + } + pfe_flash = dev_get_uclass_priv(new); if (!pfe_flash) { printf("SF: probe for pfe failed\n"); free(addr); + device_remove(new, DM_REMOVE_NORMAL); return -ENODEV; } ret = spi_flash_read(pfe_flash, CONFIG_SYS_LS_PFE_FW_ADDR, - CONFIG_SYS_QE_FMAN_FW_LENGTH, + CONFIG_SYS_LS_PFE_FW_LENGTH, addr); - if (ret) + if (ret) { printf("SF: read for pfe failed\n"); + free(addr); + spi_flash_free(pfe_flash); + return ret; + } +#ifdef CONFIG_CHAIN_OF_TRUST + void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH); + + if (!hdr_addr) { + free(addr); + spi_flash_free(pfe_flash); + return -ENOMEM; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_ESBC_ADDR, + CONFIG_SYS_LS_PFE_ESBC_LENGTH, + hdr_addr); + if (ret) { + printf("SF: failed to read pfe esbc header\n"); + free(addr); + free(hdr_addr); + spi_flash_free(pfe_flash); + return ret; + } + + pfe_esbc_hdr_addr = hdr_addr; +#endif pfe_fit_addr = addr; spi_flash_free(pfe_flash); @@ -233,7 +273,7 @@ int pfe_firmware_init(void) goto err; #ifdef CONFIG_CHAIN_OF_TRUST - pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR; + pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr; pfe_img_addr = (uintptr_t)pfe_fit_addr; if (fsl_check_boot_mode_secure() != 0) { /* diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4e1a93be221..51733dd1237 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -100,6 +100,15 @@ config PHY_BROADCOM config PHY_CORTINA bool "Cortina Ethernet PHYs support" +config SYS_CORTINA_NO_FW_UPLOAD + bool "Cortina firmware loading support" + default n + depends on PHY_CORTINA + help + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. + choice prompt "Location of the Cortina firmware" default SYS_CORTINA_FW_IN_NOR diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index dbc20b14051..b381a431fd9 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -3,7 +3,7 @@ * Cortina CS4315/CS4340 10G PHY drivers * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -29,7 +29,7 @@ #error The Cortina PHY needs 10G support #endif -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, @@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) int cs4340_phy_init(struct phy_device *phydev) { -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD int timeout = 100; /* 100ms */ #endif int reg_value; @@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev) * Boards designed with EEPROM attached to Cortina * does not require FW upload. */ -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index af927849508..65498bce1d9 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +228,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index eba230e3a5f..d7d4a44b228 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <asm/arch/fsl_serdes.h> #include <dm.h> #include <dm/devres.h> #include <errno.h> @@ -272,7 +273,9 @@ static int ls_pcie_ep_probe(struct udevice *dev) svr = SVR_SOC_VER(get_svr()); - if (svr == SVR_LX2160A) + if (svr == SVR_LX2160A || svr == SVR_LX2162A || + svr == SVR_LX2120A || svr == SVR_LX2080A || + svr == SVR_LX2122A || svr == SVR_LX2082A) pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET; else pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET; @@ -294,7 +297,8 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "num-ob-windows", 8); - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Endpoint"); ls_pcie_setup_ep(pcie_ep); if (!ls_pcie_link_up(pcie)) { diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index 0a42997696b..40f0ef10ac4 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -99,6 +99,8 @@ int lx2_board_fix_fdt(void *fdt) if (!prop) { printf("%s: Failed to fixup PCIe EP node @0x%x\n", __func__, off); + off = fdt_node_offset_by_compatible(fdt, off, + "fsl,lx2160a-pcie-ep"); continue; } @@ -121,13 +123,16 @@ int pcie_board_fix_fdt(void *fdt) svr = SVR_SOC_VER(get_svr()); - if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0)) + if ((svr == SVR_LX2160A || svr == SVR_LX2162A || + svr == SVR_LX2120A || svr == SVR_LX2080A || + svr == SVR_LX2122A || svr == SVR_LX2082A) && + IS_SVR_REV(get_svr(), 2, 0)) return lx2_board_fix_fdt(fdt); return 0; } -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* returns the next available streamid for pcie, -errno if failed */ int pcie_next_streamid(int currentid, int idx) { diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 428bfcab09f..6e71173621f 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * * PCIe Gen4 driver for NXP Layerscape SoCs * Author: Hou Zhiqiang <Minder.Hou@gmail.com> @@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev) u32 link_ctrl_sta; u32 val; int ret; + fdt_size_t cfg_size; pcie->bus = dev; @@ -472,7 +473,8 @@ static int ls_pcie_g4_probe(struct udevice *dev) pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); if (!pcie->enabled) { - printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx), + dev->name); return 0; } @@ -487,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie->cfg_res); + if (cfg_size < SZ_4K) { + printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n", + PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K); + return 0; + } + pcie->cfg = map_physmem(pcie->cfg_res.start, fdt_resource_size(&pcie->cfg_res), MAP_NOCACHE); @@ -522,10 +531,12 @@ static int ls_pcie_g4_probe(struct udevice *dev) pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f; if (pcie->mode == PCI_HEADER_TYPE_NORMAL) { - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Endpoint"); ls_pcie_g4_setup_ep(pcie); } else { - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Root Complex"); ls_pcie_g4_setup_ctrl(pcie); } diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 25c6ddebce0..cdfcad6b0be 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev) pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); if (!pcie_rc->enabled) { - printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx), + dev->name); return 0; } @@ -313,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie_rc->cfg_res); + if (cfg_size < SZ_8K) { + printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n", + PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K); + return 0; + } + /* * Fix the pcie memory map address and PF control registers address * for LS2088A series SoCs @@ -322,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev) if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || svr == SVR_LS2081A || svr == SVR_LS2041A) { - cfg_size = fdt_resource_size(&pcie_rc->cfg_res); pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size; @@ -342,7 +349,8 @@ static int ls_pcie_probe(struct udevice *dev) (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0, pcie->big_endian); - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Root Complex"); ls_pcie_setup_ctrl(pcie_rc); if (!ls_pcie_link_up(pcie)) { diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index a1e62197586..447ce7283db 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -66,10 +66,10 @@ struct phy_meson_g12a_usb2_priv { static int phy_meson_g12a_usb2_power_on(struct phy *phy) { +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *dev = phy->dev; struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev); -#if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->phy_supply) { int ret = regulator_set_enable(priv->phy_supply, true); if (ret) @@ -82,10 +82,10 @@ static int phy_meson_g12a_usb2_power_on(struct phy *phy) static int phy_meson_g12a_usb2_power_off(struct phy *phy) { +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *dev = phy->dev; struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev); -#if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->phy_supply) { int ret = regulator_set_enable(priv->phy_supply, false); if (ret) { diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 9d4296d6491..ab4a913c934 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -59,6 +59,7 @@ struct stm32_usbphyc { struct udevice *vdda1v8; struct stm32_usbphyc_phy { struct udevice *vdd; + struct udevice *vbus; bool init; bool powered; } phys[MAX_PHYS]; @@ -244,6 +245,11 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy) if (ret) return ret; } + if (usbphyc_phy->vbus) { + ret = regulator_set_enable(usbphyc_phy->vbus, true); + if (ret) + return ret; + } usbphyc_phy->powered = true; @@ -262,6 +268,11 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) if (stm32_usbphyc_is_powered(usbphyc)) return 0; + if (usbphyc_phy->vbus) { + ret = regulator_set_enable(usbphyc_phy->vbus, false); + if (ret) + return ret; + } if (usbphyc_phy->vdd) { ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false); if (ret) @@ -271,7 +282,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) return 0; } -static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, +static int stm32_usbphyc_get_regulator(ofnode node, char *supply_name, struct udevice **regulator) { @@ -281,19 +292,14 @@ static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, ret = ofnode_parse_phandle_with_args(node, supply_name, NULL, 0, 0, ®ulator_phandle); - if (ret) { - dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret); + if (ret) return ret; - } ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR, regulator_phandle.node, regulator); - - if (ret) { - dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret); + if (ret) return ret; - } return 0; } @@ -380,10 +386,17 @@ static int stm32_usbphyc_probe(struct udevice *dev) usbphyc_phy->init = false; usbphyc_phy->powered = false; - ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply", + ret = stm32_usbphyc_get_regulator(node, "phy-supply", &usbphyc_phy->vdd); - if (ret) + if (ret) { + dev_err(dev, "Can't get phy-supply regulator\n"); return ret; + } + + ret = stm32_usbphyc_get_regulator(node, "vbus-supply", + &usbphyc_phy->vbus); + if (ret) + usbphyc_phy->vbus = NULL; node = dev_read_next_subnode(node); } diff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c index 2a20f7601c0..51468b45732 100644 --- a/drivers/phy/sti_usb_phy.c +++ b/drivers/phy/sti_usb_phy.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/pinctrl/pinctrl-kendryte.c b/drivers/pinctrl/pinctrl-kendryte.c index 5ad049d9555..04162016ccd 100644 --- a/drivers/pinctrl/pinctrl-kendryte.c +++ b/drivers/pinctrl/pinctrl-kendryte.c @@ -55,8 +55,9 @@ #define K210_PC_MODE_IN (K210_PC_IE | K210_PC_ST) #define K210_PC_MODE_OUT (K210_PC_DRIVE_7 | K210_PC_OE) -#define K210_PC_MODE_I2C (K210_PC_MODE_IN | K210_PC_IE_INV | K210_PC_SL | \ - K210_PC_OE | K210_PC_OE_INV | K210_PC_PU) +#define K210_PC_MODE_I2C (K210_PC_MODE_IN | K210_PC_SL | K210_PC_OE | \ + K210_PC_PU) +#define K210_PC_MODE_SCCB (K210_PC_MODE_I2C | K210_PC_OE_INV | K210_PC_IE_INV) #define K210_PC_MODE_SPI (K210_PC_MODE_IN | K210_PC_IE_INV | \ K210_PC_MODE_OUT | K210_PC_OE_INV) #define K210_PC_MODE_GPIO (K210_PC_MODE_IN | K210_PC_MODE_OUT) @@ -152,11 +153,11 @@ static const char k210_pc_group_names[][3] = { [0] = "A0", [1] = "A1", [2] = "A2", - [3] = "B0", - [4] = "B1", - [5] = "B2", - [6] = "C0", - [7] = "C1", + [3] = "B3", + [4] = "B4", + [5] = "B5", + [6] = "C6", + [7] = "C7", }; static int k210_pc_get_groups_count(struct udevice *dev) @@ -176,6 +177,7 @@ enum k210_pc_mode_id { K210_PC_DEFAULT_IN_TIE, K210_PC_DEFAULT_OUT, K210_PC_DEFAULT_I2C, + K210_PC_DEFAULT_SCCB, K210_PC_DEFAULT_SPI, K210_PC_DEFAULT_GPIO, K210_PC_DEFAULT_INT13, @@ -189,6 +191,7 @@ static const u32 k210_pc_mode_id_to_mode[] = { [K210_PC_DEFAULT_IN_TIE] = K210_PC_MODE_IN, DEFAULT(OUT), DEFAULT(I2C), + DEFAULT(SCCB), DEFAULT(SPI), DEFAULT(GPIO), [K210_PC_DEFAULT_INT13] = K210_PC_MODE_IN | K210_PC_PU, @@ -362,8 +365,8 @@ static const struct k210_pcf_info k210_pcf_infos[] = { FUNC(DVP_D5, IN), FUNC(DVP_D6, IN), FUNC(DVP_D7, IN), - FUNC(SCCB_SCLK, I2C), - FUNC(SCCB_SDA, I2C), + FUNC(SCCB_SCLK, SCCB), + FUNC(SCCB_SDA, SCCB), FUNC(UART1_CTS, IN), FUNC(UART1_DSR, IN), FUNC(UART1_DCD, IN), diff --git a/drivers/pinctrl/pinctrl-sti.c b/drivers/pinctrl/pinctrl-sti.c index 8e942a82802..2f3ee004532 100644 --- a/drivers/pinctrl/pinctrl-sti.c +++ b/drivers/pinctrl/pinctrl-sti.c @@ -3,7 +3,7 @@ * Pinctrl driver for STMicroelectronics STi SoCs * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index c2ea82770e6..a62be44d2d8 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -343,8 +343,8 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev) } /* - * STMFX pins[15:0] are called "gpio[15:0]" - * and STMFX pins[23:16] are called "agpio[7:0]" + * STMFX pins[15:0] are called "stmfx_gpio[15:0]" + * and STMFX pins[23:16] are called "stmfx_agpio[7:0]" */ #define MAX_PIN_NAME_LEN 7 static char pin_name[MAX_PIN_NAME_LEN]; @@ -352,9 +352,9 @@ static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector) { if (selector < STMFX_MAX_GPIO) - snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector); else - snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16); + snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector - 16); return pin_name; } @@ -408,8 +408,11 @@ static int stmfx_pinctrl_bind(struct udevice *dev) { struct stmfx_pinctrl *plat = dev_get_platdata(dev); + /* subnode name is not explicit: use father name */ + device_set_name(dev, dev->parent->name); + return device_bind_driver_to_node(dev->parent, - "stmfx-gpio", "stmfx-gpio", + "stmfx-gpio", dev->parent->name, dev_ofnode(dev), &plat->gpio); }; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index dbea99532cb..262b2c3d7e5 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -48,15 +48,15 @@ static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { "alt function", }; -static const char * const pinmux_output[] = { - [STM32_GPIO_PUPD_NO] = "bias-disable", - [STM32_GPIO_PUPD_UP] = "bias-pull-up", - [STM32_GPIO_PUPD_DOWN] = "bias-pull-down", +static const char * const pinmux_bias[] = { + [STM32_GPIO_PUPD_NO] = "", + [STM32_GPIO_PUPD_UP] = "pull-up", + [STM32_GPIO_PUPD_DOWN] = "pull-down", }; static const char * const pinmux_input[] = { - [STM32_GPIO_OTYPE_PP] = "drive-push-pull", - [STM32_GPIO_OTYPE_OD] = "drive-open-drain", + [STM32_GPIO_OTYPE_PP] = "push-pull", + [STM32_GPIO_OTYPE_OD] = "open-drain", }; static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) @@ -213,6 +213,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", selector, gpio_idx, mode); priv = dev_get_priv(gpio_dev); + pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK; switch (mode) { @@ -224,20 +225,19 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, break; case GPIOF_FUNC: af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); - snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num); + snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num, + pinmux_bias[pupd]); break; case GPIOF_OUTPUT: - pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & - PUPD_MASK; snprintf(buf, size, "%s %s %s", - pinmux_mode[mode], pinmux_output[pupd], + pinmux_mode[mode], pinmux_bias[pupd], label ? label : ""); break; case GPIOF_INPUT: otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; - snprintf(buf, size, "%s %s %s", + snprintf(buf, size, "%s %s %s %s", pinmux_mode[mode], pinmux_input[otype], - label ? label : ""); + pinmux_bias[pupd], label ? label : ""); break; } diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index e14294b6e7e..d2be4c84ba1 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -67,6 +67,26 @@ config PINCTRL_PFC_R8A774A1 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_PFC_R8A774B1 + bool "Renesas RZ/G2 R8A774B1 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + +config PINCTRL_PFC_R8A774E1 + bool "Renesas RZ/G2 R8A774E1 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_PFC_R8A7795 bool "Renesas RCar Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index a4eb912d548..1d007520512 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -1,5 +1,7 @@ obj-$(CONFIG_PINCTRL_PFC) += pfc.o obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o +obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o +obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index ba17a557752..898f837950d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -683,7 +683,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), @@ -1836,6 +1836,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2050,6 +2051,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -3902,6 +3904,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4136,353 +4168,368 @@ static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a_a), - SH_PFC_PIN_GROUP(audio_clk_a_b), - SH_PFC_PIN_GROUP(audio_clk_a_c), - SH_PFC_PIN_GROUP(audio_clk_b_a), - SH_PFC_PIN_GROUP(audio_clk_b_b), - SH_PFC_PIN_GROUP(audio_clk_c_a), - SH_PFC_PIN_GROUP(audio_clk_c_b), - SH_PFC_PIN_GROUP(audio_clkout_a), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(audio_clkout1_a), - SH_PFC_PIN_GROUP(audio_clkout1_b), - SH_PFC_PIN_GROUP(audio_clkout2_a), - SH_PFC_PIN_GROUP(audio_clkout2_b), - SH_PFC_PIN_GROUP(audio_clkout3_a), - SH_PFC_PIN_GROUP(audio_clkout3_b), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_avtp_pps), - SH_PFC_PIN_GROUP(avb_avtp_match_a), - SH_PFC_PIN_GROUP(avb_avtp_capture_a), - SH_PFC_PIN_GROUP(avb_avtp_match_b), - SH_PFC_PIN_GROUP(avb_avtp_capture_b), - SH_PFC_PIN_GROUP(can0_data_a), - SH_PFC_PIN_GROUP(can0_data_b), - SH_PFC_PIN_GROUP(can1_data), - SH_PFC_PIN_GROUP(can_clk), - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), - SH_PFC_PIN_GROUP(drif0_ctrl_a), - SH_PFC_PIN_GROUP(drif0_data0_a), - SH_PFC_PIN_GROUP(drif0_data1_a), - SH_PFC_PIN_GROUP(drif0_ctrl_b), - SH_PFC_PIN_GROUP(drif0_data0_b), - SH_PFC_PIN_GROUP(drif0_data1_b), - SH_PFC_PIN_GROUP(drif0_ctrl_c), - SH_PFC_PIN_GROUP(drif0_data0_c), - SH_PFC_PIN_GROUP(drif0_data1_c), - SH_PFC_PIN_GROUP(drif1_ctrl_a), - SH_PFC_PIN_GROUP(drif1_data0_a), - SH_PFC_PIN_GROUP(drif1_data1_a), - SH_PFC_PIN_GROUP(drif1_ctrl_b), - SH_PFC_PIN_GROUP(drif1_data0_b), - SH_PFC_PIN_GROUP(drif1_data1_b), - SH_PFC_PIN_GROUP(drif1_ctrl_c), - SH_PFC_PIN_GROUP(drif1_data0_c), - SH_PFC_PIN_GROUP(drif1_data1_c), - SH_PFC_PIN_GROUP(drif2_ctrl_a), - SH_PFC_PIN_GROUP(drif2_data0_a), - SH_PFC_PIN_GROUP(drif2_data1_a), - SH_PFC_PIN_GROUP(drif2_ctrl_b), - SH_PFC_PIN_GROUP(drif2_data0_b), - SH_PFC_PIN_GROUP(drif2_data1_b), - SH_PFC_PIN_GROUP(drif3_ctrl_a), - SH_PFC_PIN_GROUP(drif3_data0_a), - SH_PFC_PIN_GROUP(drif3_data1_a), - SH_PFC_PIN_GROUP(drif3_ctrl_b), - SH_PFC_PIN_GROUP(drif3_data0_b), - SH_PFC_PIN_GROUP(drif3_data1_b), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync), - SH_PFC_PIN_GROUP(du_oddf), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_a), - SH_PFC_PIN_GROUP(hscif1_clk_a), - SH_PFC_PIN_GROUP(hscif1_ctrl_a), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_a), - SH_PFC_PIN_GROUP(hscif2_clk_a), - SH_PFC_PIN_GROUP(hscif2_ctrl_a), - SH_PFC_PIN_GROUP(hscif2_data_b), - SH_PFC_PIN_GROUP(hscif2_clk_b), - SH_PFC_PIN_GROUP(hscif2_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_c), - SH_PFC_PIN_GROUP(hscif2_clk_c), - SH_PFC_PIN_GROUP(hscif2_ctrl_c), - SH_PFC_PIN_GROUP(hscif3_data_a), - SH_PFC_PIN_GROUP(hscif3_clk), - SH_PFC_PIN_GROUP(hscif3_ctrl), - SH_PFC_PIN_GROUP(hscif3_data_b), - SH_PFC_PIN_GROUP(hscif3_data_c), - SH_PFC_PIN_GROUP(hscif3_data_d), - SH_PFC_PIN_GROUP(hscif4_data_a), - SH_PFC_PIN_GROUP(hscif4_clk), - SH_PFC_PIN_GROUP(hscif4_ctrl), - SH_PFC_PIN_GROUP(hscif4_data_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1_a), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c2_a), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(i2c5), - SH_PFC_PIN_GROUP(i2c6_a), - SH_PFC_PIN_GROUP(i2c6_b), - SH_PFC_PIN_GROUP(i2c6_c), - SH_PFC_PIN_GROUP(intc_ex_irq0), - SH_PFC_PIN_GROUP(intc_ex_irq1), - SH_PFC_PIN_GROUP(intc_ex_irq2), - SH_PFC_PIN_GROUP(intc_ex_irq3), - SH_PFC_PIN_GROUP(intc_ex_irq4), - SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_txd), - SH_PFC_PIN_GROUP(msiof0_rxd), - SH_PFC_PIN_GROUP(msiof1_clk_a), - SH_PFC_PIN_GROUP(msiof1_sync_a), - SH_PFC_PIN_GROUP(msiof1_ss1_a), - SH_PFC_PIN_GROUP(msiof1_ss2_a), - SH_PFC_PIN_GROUP(msiof1_txd_a), - SH_PFC_PIN_GROUP(msiof1_rxd_a), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_sync_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_txd_b), - SH_PFC_PIN_GROUP(msiof1_rxd_b), - SH_PFC_PIN_GROUP(msiof1_clk_c), - SH_PFC_PIN_GROUP(msiof1_sync_c), - SH_PFC_PIN_GROUP(msiof1_ss1_c), - SH_PFC_PIN_GROUP(msiof1_ss2_c), - SH_PFC_PIN_GROUP(msiof1_txd_c), - SH_PFC_PIN_GROUP(msiof1_rxd_c), - SH_PFC_PIN_GROUP(msiof1_clk_d), - SH_PFC_PIN_GROUP(msiof1_sync_d), - SH_PFC_PIN_GROUP(msiof1_ss1_d), - SH_PFC_PIN_GROUP(msiof1_ss2_d), - SH_PFC_PIN_GROUP(msiof1_txd_d), - SH_PFC_PIN_GROUP(msiof1_rxd_d), - SH_PFC_PIN_GROUP(msiof1_clk_e), - SH_PFC_PIN_GROUP(msiof1_sync_e), - SH_PFC_PIN_GROUP(msiof1_ss1_e), - SH_PFC_PIN_GROUP(msiof1_ss2_e), - SH_PFC_PIN_GROUP(msiof1_txd_e), - SH_PFC_PIN_GROUP(msiof1_rxd_e), - SH_PFC_PIN_GROUP(msiof1_clk_f), - SH_PFC_PIN_GROUP(msiof1_sync_f), - SH_PFC_PIN_GROUP(msiof1_ss1_f), - SH_PFC_PIN_GROUP(msiof1_ss2_f), - SH_PFC_PIN_GROUP(msiof1_txd_f), - SH_PFC_PIN_GROUP(msiof1_rxd_f), - SH_PFC_PIN_GROUP(msiof1_clk_g), - SH_PFC_PIN_GROUP(msiof1_sync_g), - SH_PFC_PIN_GROUP(msiof1_ss1_g), - SH_PFC_PIN_GROUP(msiof1_ss2_g), - SH_PFC_PIN_GROUP(msiof1_txd_g), - SH_PFC_PIN_GROUP(msiof1_rxd_g), - SH_PFC_PIN_GROUP(msiof2_clk_a), - SH_PFC_PIN_GROUP(msiof2_sync_a), - SH_PFC_PIN_GROUP(msiof2_ss1_a), - SH_PFC_PIN_GROUP(msiof2_ss2_a), - SH_PFC_PIN_GROUP(msiof2_txd_a), - SH_PFC_PIN_GROUP(msiof2_rxd_a), - SH_PFC_PIN_GROUP(msiof2_clk_b), - SH_PFC_PIN_GROUP(msiof2_sync_b), - SH_PFC_PIN_GROUP(msiof2_ss1_b), - SH_PFC_PIN_GROUP(msiof2_ss2_b), - SH_PFC_PIN_GROUP(msiof2_txd_b), - SH_PFC_PIN_GROUP(msiof2_rxd_b), - SH_PFC_PIN_GROUP(msiof2_clk_c), - SH_PFC_PIN_GROUP(msiof2_sync_c), - SH_PFC_PIN_GROUP(msiof2_ss1_c), - SH_PFC_PIN_GROUP(msiof2_ss2_c), - SH_PFC_PIN_GROUP(msiof2_txd_c), - SH_PFC_PIN_GROUP(msiof2_rxd_c), - SH_PFC_PIN_GROUP(msiof2_clk_d), - SH_PFC_PIN_GROUP(msiof2_sync_d), - SH_PFC_PIN_GROUP(msiof2_ss1_d), - SH_PFC_PIN_GROUP(msiof2_ss2_d), - SH_PFC_PIN_GROUP(msiof2_txd_d), - SH_PFC_PIN_GROUP(msiof2_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_a), - SH_PFC_PIN_GROUP(msiof3_sync_a), - SH_PFC_PIN_GROUP(msiof3_ss1_a), - SH_PFC_PIN_GROUP(msiof3_ss2_a), - SH_PFC_PIN_GROUP(msiof3_txd_a), - SH_PFC_PIN_GROUP(msiof3_rxd_a), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_ss1_b), - SH_PFC_PIN_GROUP(msiof3_ss2_b), - SH_PFC_PIN_GROUP(msiof3_txd_b), - SH_PFC_PIN_GROUP(msiof3_rxd_b), - SH_PFC_PIN_GROUP(msiof3_clk_c), - SH_PFC_PIN_GROUP(msiof3_sync_c), - SH_PFC_PIN_GROUP(msiof3_txd_c), - SH_PFC_PIN_GROUP(msiof3_rxd_c), - SH_PFC_PIN_GROUP(msiof3_clk_d), - SH_PFC_PIN_GROUP(msiof3_sync_d), - SH_PFC_PIN_GROUP(msiof3_ss1_d), - SH_PFC_PIN_GROUP(msiof3_txd_d), - SH_PFC_PIN_GROUP(msiof3_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_e), - SH_PFC_PIN_GROUP(msiof3_sync_e), - SH_PFC_PIN_GROUP(msiof3_ss1_e), - SH_PFC_PIN_GROUP(msiof3_ss2_e), - SH_PFC_PIN_GROUP(msiof3_txd_e), - SH_PFC_PIN_GROUP(msiof3_rxd_e), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm1_a), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2_a), - SH_PFC_PIN_GROUP(pwm2_b), - SH_PFC_PIN_GROUP(pwm3_a), - SH_PFC_PIN_GROUP(pwm3_b), - SH_PFC_PIN_GROUP(pwm4_a), - SH_PFC_PIN_GROUP(pwm4_b), - SH_PFC_PIN_GROUP(pwm5_a), - SH_PFC_PIN_GROUP(pwm5_b), - SH_PFC_PIN_GROUP(pwm6_a), - SH_PFC_PIN_GROUP(pwm6_b), - SH_PFC_PIN_GROUP(sata0_devslp_a), - SH_PFC_PIN_GROUP(sata0_devslp_b), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif1_data_a), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif2_data_a), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif3_data_a), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_ctrl), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif4_data_a), - SH_PFC_PIN_GROUP(scif4_clk_a), - SH_PFC_PIN_GROUP(scif4_ctrl_a), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_clk_b), - SH_PFC_PIN_GROUP(scif4_ctrl_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif4_clk_c), - SH_PFC_PIN_GROUP(scif4_ctrl_c), - SH_PFC_PIN_GROUP(scif5_data_a), - SH_PFC_PIN_GROUP(scif5_clk_a), - SH_PFC_PIN_GROUP(scif5_data_b), - SH_PFC_PIN_GROUP(scif5_clk_b), - SH_PFC_PIN_GROUP(scif_clk_a), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd_a), - SH_PFC_PIN_GROUP(sdhi2_wp_a), - SH_PFC_PIN_GROUP(sdhi2_cd_b), - SH_PFC_PIN_GROUP(sdhi2_wp_b), - SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(sdhi3_ds), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi01239_ctrl), - SH_PFC_PIN_GROUP(ssi1_data_a), - SH_PFC_PIN_GROUP(ssi1_data_b), - SH_PFC_PIN_GROUP(ssi1_ctrl_a), - SH_PFC_PIN_GROUP(ssi1_ctrl_b), - SH_PFC_PIN_GROUP(ssi2_data_a), - SH_PFC_PIN_GROUP(ssi2_data_b), - SH_PFC_PIN_GROUP(ssi2_ctrl_a), - SH_PFC_PIN_GROUP(ssi2_ctrl_b), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi349_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5_data), - SH_PFC_PIN_GROUP(ssi5_ctrl), - SH_PFC_PIN_GROUP(ssi6_data), - SH_PFC_PIN_GROUP(ssi6_ctrl), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi9_data_a), - SH_PFC_PIN_GROUP(ssi9_data_b), - SH_PFC_PIN_GROUP(ssi9_ctrl_a), - SH_PFC_PIN_GROUP(ssi9_ctrl_b), - SH_PFC_PIN_GROUP(tmu_tclk1_a), - SH_PFC_PIN_GROUP(tmu_tclk1_b), - SH_PFC_PIN_GROUP(tmu_tclk2_a), - SH_PFC_PIN_GROUP(tmu_tclk2_b), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - SH_PFC_PIN_GROUP(usb2_ch3), - SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), - SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), - SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_sync), - SH_PFC_PIN_GROUP(vin4_field), - SH_PFC_PIN_GROUP(vin4_clkenb), - SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_sync), - SH_PFC_PIN_GROUP(vin5_field), - SH_PFC_PIN_GROUP(vin5_clkenb), - SH_PFC_PIN_GROUP(vin5_clk), +static const struct { + struct sh_pfc_pin_group common[320]; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 + struct sh_pfc_pin_group automotive[30]; +#endif +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk_a), + SH_PFC_PIN_GROUP(msiof1_sync_a), + SH_PFC_PIN_GROUP(msiof1_ss1_a), + SH_PFC_PIN_GROUP(msiof1_ss2_a), + SH_PFC_PIN_GROUP(msiof1_txd_a), + SH_PFC_PIN_GROUP(msiof1_rxd_a), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_txd_b), + SH_PFC_PIN_GROUP(msiof1_rxd_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_ss1_c), + SH_PFC_PIN_GROUP(msiof1_ss2_c), + SH_PFC_PIN_GROUP(msiof1_txd_c), + SH_PFC_PIN_GROUP(msiof1_rxd_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_ss2_d), + SH_PFC_PIN_GROUP(msiof1_txd_d), + SH_PFC_PIN_GROUP(msiof1_rxd_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_ss1_e), + SH_PFC_PIN_GROUP(msiof1_ss2_e), + SH_PFC_PIN_GROUP(msiof1_txd_e), + SH_PFC_PIN_GROUP(msiof1_rxd_e), + SH_PFC_PIN_GROUP(msiof1_clk_f), + SH_PFC_PIN_GROUP(msiof1_sync_f), + SH_PFC_PIN_GROUP(msiof1_ss1_f), + SH_PFC_PIN_GROUP(msiof1_ss2_f), + SH_PFC_PIN_GROUP(msiof1_txd_f), + SH_PFC_PIN_GROUP(msiof1_rxd_f), + SH_PFC_PIN_GROUP(msiof1_clk_g), + SH_PFC_PIN_GROUP(msiof1_sync_g), + SH_PFC_PIN_GROUP(msiof1_ss1_g), + SH_PFC_PIN_GROUP(msiof1_ss2_g), + SH_PFC_PIN_GROUP(msiof1_txd_g), + SH_PFC_PIN_GROUP(msiof1_rxd_g), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_ss1_c), + SH_PFC_PIN_GROUP(msiof2_ss2_c), + SH_PFC_PIN_GROUP(msiof2_txd_c), + SH_PFC_PIN_GROUP(msiof2_rxd_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_txd_d), + SH_PFC_PIN_GROUP(msiof2_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_ss2_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_c), + SH_PFC_PIN_GROUP(msiof3_sync_c), + SH_PFC_PIN_GROUP(msiof3_txd_c), + SH_PFC_PIN_GROUP(msiof3_rxd_c), + SH_PFC_PIN_GROUP(msiof3_clk_d), + SH_PFC_PIN_GROUP(msiof3_sync_d), + SH_PFC_PIN_GROUP(msiof3_ss1_d), + SH_PFC_PIN_GROUP(msiof3_txd_d), + SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_e), + SH_PFC_PIN_GROUP(msiof3_sync_e), + SH_PFC_PIN_GROUP(msiof3_ss1_e), + SH_PFC_PIN_GROUP(msiof3_ss2_e), + SH_PFC_PIN_GROUP(msiof3_txd_e), + SH_PFC_PIN_GROUP(msiof3_rxd_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_ctrl_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_ctrl_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_clk_c), + SH_PFC_PIN_GROUP(scif4_ctrl_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(usb2_ch3), + SH_PFC_PIN_GROUP(usb30), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + VIN_DATA_PIN_GROUP(vin5_data, 8), + VIN_DATA_PIN_GROUP(vin5_data, 10), + VIN_DATA_PIN_GROUP(vin5_data, 12), + VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), + }, +#ifdef CONFIG_PINCTRL_PFC_R8A7795 + .automotive = { + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), + SH_PFC_PIN_GROUP(drif0_ctrl_b), + SH_PFC_PIN_GROUP(drif0_data0_b), + SH_PFC_PIN_GROUP(drif0_data1_b), + SH_PFC_PIN_GROUP(drif0_ctrl_c), + SH_PFC_PIN_GROUP(drif0_data0_c), + SH_PFC_PIN_GROUP(drif0_data1_c), + SH_PFC_PIN_GROUP(drif1_ctrl_a), + SH_PFC_PIN_GROUP(drif1_data0_a), + SH_PFC_PIN_GROUP(drif1_data1_a), + SH_PFC_PIN_GROUP(drif1_ctrl_b), + SH_PFC_PIN_GROUP(drif1_data0_b), + SH_PFC_PIN_GROUP(drif1_data1_b), + SH_PFC_PIN_GROUP(drif1_ctrl_c), + SH_PFC_PIN_GROUP(drif1_data0_c), + SH_PFC_PIN_GROUP(drif1_data1_c), + SH_PFC_PIN_GROUP(drif2_ctrl_a), + SH_PFC_PIN_GROUP(drif2_data0_a), + SH_PFC_PIN_GROUP(drif2_data1_a), + SH_PFC_PIN_GROUP(drif2_ctrl_b), + SH_PFC_PIN_GROUP(drif2_data0_b), + SH_PFC_PIN_GROUP(drif2_data1_b), + SH_PFC_PIN_GROUP(drif3_ctrl_a), + SH_PFC_PIN_GROUP(drif3_data0_a), + SH_PFC_PIN_GROUP(drif3_data1_a), + SH_PFC_PIN_GROUP(drif3_ctrl_b), + SH_PFC_PIN_GROUP(drif3_data0_b), + SH_PFC_PIN_GROUP(drif3_data1_b), + } +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ }; static const char * const audio_clk_groups[] = { @@ -4541,6 +4588,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4582,6 +4630,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ static const char * const du_groups[] = { "du_rgb666", @@ -4947,6 +4996,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4999,63 +5055,75 @@ static const char * const vin5_groups[] = { "vin5_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(can0), - SH_PFC_FUNCTION(can1), - SH_PFC_FUNCTION(can_clk), - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), - SH_PFC_FUNCTION(drif0), - SH_PFC_FUNCTION(drif1), - SH_PFC_FUNCTION(drif2), - SH_PFC_FUNCTION(drif3), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(hscif2), - SH_PFC_FUNCTION(hscif3), - SH_PFC_FUNCTION(hscif4), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(i2c5), - SH_PFC_FUNCTION(i2c6), - SH_PFC_FUNCTION(intc_ex), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(sata0), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tmu), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(usb2_ch3), - SH_PFC_FUNCTION(usb30), - SH_PFC_FUNCTION(vin4), - SH_PFC_FUNCTION(vin5), +static const struct { + struct sh_pfc_function common[53]; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 + struct sh_pfc_function automotive[4]; +#endif +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(sata0), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(usb2_ch3), + SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), + }, +#ifdef CONFIG_PINCTRL_PFC_R8A7795 + .automotive = { + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), + SH_PFC_FUNCTION(drif3), + } +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -6186,6 +6254,32 @@ static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { .set_bias = r8a7795_pinmux_set_bias, }; +#ifdef CONFIG_PINCTRL_PFC_R8A774E1 +const struct sh_pfc_soc_info r8a774e1_pinmux_info = { + .name = "r8a774e1_pfc", + .ops = &r8a7795_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7795 const struct sh_pfc_soc_info r8a7795_pinmux_info = { .name = "r8a77951_pfc", .ops = &r8a7795_pinmux_ops, @@ -6195,10 +6289,12 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, @@ -6208,3 +6304,4 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = { .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index a92c8ad18c1..da7901ea6eb 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1841,6 +1841,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#if defined(CONFIG_PINCTRL_PFC_R8A7796) /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2055,6 +2056,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4113,7 +4115,9 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[312]; +#if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_pin_group automotive[30]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4429,6 +4433,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7796) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4461,6 +4466,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ }; static const char * const audio_clk_groups[] = { @@ -4519,6 +4525,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#if defined(CONFIG_PINCTRL_PFC_R8A7796) static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4560,6 +4567,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ static const char * const du_groups[] = { "du_rgb666", @@ -4966,7 +4974,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[49]; +#if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5019,12 +5029,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7796) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 2523904aec1..d143750c2dd 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -691,7 +691,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), @@ -1857,6 +1857,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2130,6 +2131,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4118,6 +4120,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4358,351 +4390,366 @@ static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a_a), - SH_PFC_PIN_GROUP(audio_clk_a_b), - SH_PFC_PIN_GROUP(audio_clk_a_c), - SH_PFC_PIN_GROUP(audio_clk_b_a), - SH_PFC_PIN_GROUP(audio_clk_b_b), - SH_PFC_PIN_GROUP(audio_clk_c_a), - SH_PFC_PIN_GROUP(audio_clk_c_b), - SH_PFC_PIN_GROUP(audio_clkout_a), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(audio_clkout1_a), - SH_PFC_PIN_GROUP(audio_clkout1_b), - SH_PFC_PIN_GROUP(audio_clkout2_a), - SH_PFC_PIN_GROUP(audio_clkout2_b), - SH_PFC_PIN_GROUP(audio_clkout3_a), - SH_PFC_PIN_GROUP(audio_clkout3_b), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_avtp_pps), - SH_PFC_PIN_GROUP(avb_avtp_match_a), - SH_PFC_PIN_GROUP(avb_avtp_capture_a), - SH_PFC_PIN_GROUP(avb_avtp_match_b), - SH_PFC_PIN_GROUP(avb_avtp_capture_b), - SH_PFC_PIN_GROUP(can0_data_a), - SH_PFC_PIN_GROUP(can0_data_b), - SH_PFC_PIN_GROUP(can1_data), - SH_PFC_PIN_GROUP(can_clk), - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), - SH_PFC_PIN_GROUP(drif0_ctrl_a), - SH_PFC_PIN_GROUP(drif0_data0_a), - SH_PFC_PIN_GROUP(drif0_data1_a), - SH_PFC_PIN_GROUP(drif0_ctrl_b), - SH_PFC_PIN_GROUP(drif0_data0_b), - SH_PFC_PIN_GROUP(drif0_data1_b), - SH_PFC_PIN_GROUP(drif0_ctrl_c), - SH_PFC_PIN_GROUP(drif0_data0_c), - SH_PFC_PIN_GROUP(drif0_data1_c), - SH_PFC_PIN_GROUP(drif1_ctrl_a), - SH_PFC_PIN_GROUP(drif1_data0_a), - SH_PFC_PIN_GROUP(drif1_data1_a), - SH_PFC_PIN_GROUP(drif1_ctrl_b), - SH_PFC_PIN_GROUP(drif1_data0_b), - SH_PFC_PIN_GROUP(drif1_data1_b), - SH_PFC_PIN_GROUP(drif1_ctrl_c), - SH_PFC_PIN_GROUP(drif1_data0_c), - SH_PFC_PIN_GROUP(drif1_data1_c), - SH_PFC_PIN_GROUP(drif2_ctrl_a), - SH_PFC_PIN_GROUP(drif2_data0_a), - SH_PFC_PIN_GROUP(drif2_data1_a), - SH_PFC_PIN_GROUP(drif2_ctrl_b), - SH_PFC_PIN_GROUP(drif2_data0_b), - SH_PFC_PIN_GROUP(drif2_data1_b), - SH_PFC_PIN_GROUP(drif3_ctrl_a), - SH_PFC_PIN_GROUP(drif3_data0_a), - SH_PFC_PIN_GROUP(drif3_data1_a), - SH_PFC_PIN_GROUP(drif3_ctrl_b), - SH_PFC_PIN_GROUP(drif3_data0_b), - SH_PFC_PIN_GROUP(drif3_data1_b), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync), - SH_PFC_PIN_GROUP(du_oddf), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_a), - SH_PFC_PIN_GROUP(hscif1_clk_a), - SH_PFC_PIN_GROUP(hscif1_ctrl_a), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_a), - SH_PFC_PIN_GROUP(hscif2_clk_a), - SH_PFC_PIN_GROUP(hscif2_ctrl_a), - SH_PFC_PIN_GROUP(hscif2_data_b), - SH_PFC_PIN_GROUP(hscif2_clk_b), - SH_PFC_PIN_GROUP(hscif2_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_c), - SH_PFC_PIN_GROUP(hscif2_clk_c), - SH_PFC_PIN_GROUP(hscif2_ctrl_c), - SH_PFC_PIN_GROUP(hscif3_data_a), - SH_PFC_PIN_GROUP(hscif3_clk), - SH_PFC_PIN_GROUP(hscif3_ctrl), - SH_PFC_PIN_GROUP(hscif3_data_b), - SH_PFC_PIN_GROUP(hscif3_data_c), - SH_PFC_PIN_GROUP(hscif3_data_d), - SH_PFC_PIN_GROUP(hscif4_data_a), - SH_PFC_PIN_GROUP(hscif4_clk), - SH_PFC_PIN_GROUP(hscif4_ctrl), - SH_PFC_PIN_GROUP(hscif4_data_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1_a), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c2_a), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(i2c5), - SH_PFC_PIN_GROUP(i2c6_a), - SH_PFC_PIN_GROUP(i2c6_b), - SH_PFC_PIN_GROUP(i2c6_c), - SH_PFC_PIN_GROUP(intc_ex_irq0), - SH_PFC_PIN_GROUP(intc_ex_irq1), - SH_PFC_PIN_GROUP(intc_ex_irq2), - SH_PFC_PIN_GROUP(intc_ex_irq3), - SH_PFC_PIN_GROUP(intc_ex_irq4), - SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_txd), - SH_PFC_PIN_GROUP(msiof0_rxd), - SH_PFC_PIN_GROUP(msiof1_clk_a), - SH_PFC_PIN_GROUP(msiof1_sync_a), - SH_PFC_PIN_GROUP(msiof1_ss1_a), - SH_PFC_PIN_GROUP(msiof1_ss2_a), - SH_PFC_PIN_GROUP(msiof1_txd_a), - SH_PFC_PIN_GROUP(msiof1_rxd_a), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_sync_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_txd_b), - SH_PFC_PIN_GROUP(msiof1_rxd_b), - SH_PFC_PIN_GROUP(msiof1_clk_c), - SH_PFC_PIN_GROUP(msiof1_sync_c), - SH_PFC_PIN_GROUP(msiof1_ss1_c), - SH_PFC_PIN_GROUP(msiof1_ss2_c), - SH_PFC_PIN_GROUP(msiof1_txd_c), - SH_PFC_PIN_GROUP(msiof1_rxd_c), - SH_PFC_PIN_GROUP(msiof1_clk_d), - SH_PFC_PIN_GROUP(msiof1_sync_d), - SH_PFC_PIN_GROUP(msiof1_ss1_d), - SH_PFC_PIN_GROUP(msiof1_ss2_d), - SH_PFC_PIN_GROUP(msiof1_txd_d), - SH_PFC_PIN_GROUP(msiof1_rxd_d), - SH_PFC_PIN_GROUP(msiof1_clk_e), - SH_PFC_PIN_GROUP(msiof1_sync_e), - SH_PFC_PIN_GROUP(msiof1_ss1_e), - SH_PFC_PIN_GROUP(msiof1_ss2_e), - SH_PFC_PIN_GROUP(msiof1_txd_e), - SH_PFC_PIN_GROUP(msiof1_rxd_e), - SH_PFC_PIN_GROUP(msiof1_clk_f), - SH_PFC_PIN_GROUP(msiof1_sync_f), - SH_PFC_PIN_GROUP(msiof1_ss1_f), - SH_PFC_PIN_GROUP(msiof1_ss2_f), - SH_PFC_PIN_GROUP(msiof1_txd_f), - SH_PFC_PIN_GROUP(msiof1_rxd_f), - SH_PFC_PIN_GROUP(msiof1_clk_g), - SH_PFC_PIN_GROUP(msiof1_sync_g), - SH_PFC_PIN_GROUP(msiof1_ss1_g), - SH_PFC_PIN_GROUP(msiof1_ss2_g), - SH_PFC_PIN_GROUP(msiof1_txd_g), - SH_PFC_PIN_GROUP(msiof1_rxd_g), - SH_PFC_PIN_GROUP(msiof2_clk_a), - SH_PFC_PIN_GROUP(msiof2_sync_a), - SH_PFC_PIN_GROUP(msiof2_ss1_a), - SH_PFC_PIN_GROUP(msiof2_ss2_a), - SH_PFC_PIN_GROUP(msiof2_txd_a), - SH_PFC_PIN_GROUP(msiof2_rxd_a), - SH_PFC_PIN_GROUP(msiof2_clk_b), - SH_PFC_PIN_GROUP(msiof2_sync_b), - SH_PFC_PIN_GROUP(msiof2_ss1_b), - SH_PFC_PIN_GROUP(msiof2_ss2_b), - SH_PFC_PIN_GROUP(msiof2_txd_b), - SH_PFC_PIN_GROUP(msiof2_rxd_b), - SH_PFC_PIN_GROUP(msiof2_clk_c), - SH_PFC_PIN_GROUP(msiof2_sync_c), - SH_PFC_PIN_GROUP(msiof2_ss1_c), - SH_PFC_PIN_GROUP(msiof2_ss2_c), - SH_PFC_PIN_GROUP(msiof2_txd_c), - SH_PFC_PIN_GROUP(msiof2_rxd_c), - SH_PFC_PIN_GROUP(msiof2_clk_d), - SH_PFC_PIN_GROUP(msiof2_sync_d), - SH_PFC_PIN_GROUP(msiof2_ss1_d), - SH_PFC_PIN_GROUP(msiof2_ss2_d), - SH_PFC_PIN_GROUP(msiof2_txd_d), - SH_PFC_PIN_GROUP(msiof2_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_a), - SH_PFC_PIN_GROUP(msiof3_sync_a), - SH_PFC_PIN_GROUP(msiof3_ss1_a), - SH_PFC_PIN_GROUP(msiof3_ss2_a), - SH_PFC_PIN_GROUP(msiof3_txd_a), - SH_PFC_PIN_GROUP(msiof3_rxd_a), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_ss1_b), - SH_PFC_PIN_GROUP(msiof3_ss2_b), - SH_PFC_PIN_GROUP(msiof3_txd_b), - SH_PFC_PIN_GROUP(msiof3_rxd_b), - SH_PFC_PIN_GROUP(msiof3_clk_c), - SH_PFC_PIN_GROUP(msiof3_sync_c), - SH_PFC_PIN_GROUP(msiof3_txd_c), - SH_PFC_PIN_GROUP(msiof3_rxd_c), - SH_PFC_PIN_GROUP(msiof3_clk_d), - SH_PFC_PIN_GROUP(msiof3_sync_d), - SH_PFC_PIN_GROUP(msiof3_ss1_d), - SH_PFC_PIN_GROUP(msiof3_txd_d), - SH_PFC_PIN_GROUP(msiof3_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_e), - SH_PFC_PIN_GROUP(msiof3_sync_e), - SH_PFC_PIN_GROUP(msiof3_ss1_e), - SH_PFC_PIN_GROUP(msiof3_ss2_e), - SH_PFC_PIN_GROUP(msiof3_txd_e), - SH_PFC_PIN_GROUP(msiof3_rxd_e), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm1_a), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2_a), - SH_PFC_PIN_GROUP(pwm2_b), - SH_PFC_PIN_GROUP(pwm3_a), - SH_PFC_PIN_GROUP(pwm3_b), - SH_PFC_PIN_GROUP(pwm4_a), - SH_PFC_PIN_GROUP(pwm4_b), - SH_PFC_PIN_GROUP(pwm5_a), - SH_PFC_PIN_GROUP(pwm5_b), - SH_PFC_PIN_GROUP(pwm6_a), - SH_PFC_PIN_GROUP(pwm6_b), - SH_PFC_PIN_GROUP(sata0_devslp_a), - SH_PFC_PIN_GROUP(sata0_devslp_b), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif1_data_a), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif2_data_a), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif3_data_a), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_ctrl), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif4_data_a), - SH_PFC_PIN_GROUP(scif4_clk_a), - SH_PFC_PIN_GROUP(scif4_ctrl_a), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_clk_b), - SH_PFC_PIN_GROUP(scif4_ctrl_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif4_clk_c), - SH_PFC_PIN_GROUP(scif4_ctrl_c), - SH_PFC_PIN_GROUP(scif5_data_a), - SH_PFC_PIN_GROUP(scif5_clk_a), - SH_PFC_PIN_GROUP(scif5_data_b), - SH_PFC_PIN_GROUP(scif5_clk_b), - SH_PFC_PIN_GROUP(scif_clk_a), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd_a), - SH_PFC_PIN_GROUP(sdhi2_wp_a), - SH_PFC_PIN_GROUP(sdhi2_cd_b), - SH_PFC_PIN_GROUP(sdhi2_wp_b), - SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(sdhi3_ds), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi01239_ctrl), - SH_PFC_PIN_GROUP(ssi1_data_a), - SH_PFC_PIN_GROUP(ssi1_data_b), - SH_PFC_PIN_GROUP(ssi1_ctrl_a), - SH_PFC_PIN_GROUP(ssi1_ctrl_b), - SH_PFC_PIN_GROUP(ssi2_data_a), - SH_PFC_PIN_GROUP(ssi2_data_b), - SH_PFC_PIN_GROUP(ssi2_ctrl_a), - SH_PFC_PIN_GROUP(ssi2_ctrl_b), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi349_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5_data), - SH_PFC_PIN_GROUP(ssi5_ctrl), - SH_PFC_PIN_GROUP(ssi6_data), - SH_PFC_PIN_GROUP(ssi6_ctrl), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi9_data_a), - SH_PFC_PIN_GROUP(ssi9_data_b), - SH_PFC_PIN_GROUP(ssi9_ctrl_a), - SH_PFC_PIN_GROUP(ssi9_ctrl_b), - SH_PFC_PIN_GROUP(tmu_tclk1_a), - SH_PFC_PIN_GROUP(tmu_tclk1_b), - SH_PFC_PIN_GROUP(tmu_tclk2_a), - SH_PFC_PIN_GROUP(tmu_tclk2_b), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), - SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), - SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_sync), - SH_PFC_PIN_GROUP(vin4_field), - SH_PFC_PIN_GROUP(vin4_clkenb), - SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_sync), - SH_PFC_PIN_GROUP(vin5_field), - SH_PFC_PIN_GROUP(vin5_clkenb), - SH_PFC_PIN_GROUP(vin5_clk), +static const struct { + struct sh_pfc_pin_group common[318]; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 + struct sh_pfc_pin_group automotive[30]; +#endif +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk_a), + SH_PFC_PIN_GROUP(msiof1_sync_a), + SH_PFC_PIN_GROUP(msiof1_ss1_a), + SH_PFC_PIN_GROUP(msiof1_ss2_a), + SH_PFC_PIN_GROUP(msiof1_txd_a), + SH_PFC_PIN_GROUP(msiof1_rxd_a), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_txd_b), + SH_PFC_PIN_GROUP(msiof1_rxd_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_ss1_c), + SH_PFC_PIN_GROUP(msiof1_ss2_c), + SH_PFC_PIN_GROUP(msiof1_txd_c), + SH_PFC_PIN_GROUP(msiof1_rxd_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_ss2_d), + SH_PFC_PIN_GROUP(msiof1_txd_d), + SH_PFC_PIN_GROUP(msiof1_rxd_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_ss1_e), + SH_PFC_PIN_GROUP(msiof1_ss2_e), + SH_PFC_PIN_GROUP(msiof1_txd_e), + SH_PFC_PIN_GROUP(msiof1_rxd_e), + SH_PFC_PIN_GROUP(msiof1_clk_f), + SH_PFC_PIN_GROUP(msiof1_sync_f), + SH_PFC_PIN_GROUP(msiof1_ss1_f), + SH_PFC_PIN_GROUP(msiof1_ss2_f), + SH_PFC_PIN_GROUP(msiof1_txd_f), + SH_PFC_PIN_GROUP(msiof1_rxd_f), + SH_PFC_PIN_GROUP(msiof1_clk_g), + SH_PFC_PIN_GROUP(msiof1_sync_g), + SH_PFC_PIN_GROUP(msiof1_ss1_g), + SH_PFC_PIN_GROUP(msiof1_ss2_g), + SH_PFC_PIN_GROUP(msiof1_txd_g), + SH_PFC_PIN_GROUP(msiof1_rxd_g), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_ss1_c), + SH_PFC_PIN_GROUP(msiof2_ss2_c), + SH_PFC_PIN_GROUP(msiof2_txd_c), + SH_PFC_PIN_GROUP(msiof2_rxd_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_txd_d), + SH_PFC_PIN_GROUP(msiof2_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_ss2_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_c), + SH_PFC_PIN_GROUP(msiof3_sync_c), + SH_PFC_PIN_GROUP(msiof3_txd_c), + SH_PFC_PIN_GROUP(msiof3_rxd_c), + SH_PFC_PIN_GROUP(msiof3_clk_d), + SH_PFC_PIN_GROUP(msiof3_sync_d), + SH_PFC_PIN_GROUP(msiof3_ss1_d), + SH_PFC_PIN_GROUP(msiof3_txd_d), + SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_e), + SH_PFC_PIN_GROUP(msiof3_sync_e), + SH_PFC_PIN_GROUP(msiof3_ss1_e), + SH_PFC_PIN_GROUP(msiof3_ss2_e), + SH_PFC_PIN_GROUP(msiof3_txd_e), + SH_PFC_PIN_GROUP(msiof3_rxd_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_ctrl_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_ctrl_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_clk_c), + SH_PFC_PIN_GROUP(scif4_ctrl_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb30), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + VIN_DATA_PIN_GROUP(vin5_data, 8), + VIN_DATA_PIN_GROUP(vin5_data, 10), + VIN_DATA_PIN_GROUP(vin5_data, 12), + VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), + }, +#ifdef CONFIG_PINCTRL_PFC_R8A77965 + .automotive = { + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), + SH_PFC_PIN_GROUP(drif0_ctrl_b), + SH_PFC_PIN_GROUP(drif0_data0_b), + SH_PFC_PIN_GROUP(drif0_data1_b), + SH_PFC_PIN_GROUP(drif0_ctrl_c), + SH_PFC_PIN_GROUP(drif0_data0_c), + SH_PFC_PIN_GROUP(drif0_data1_c), + SH_PFC_PIN_GROUP(drif1_ctrl_a), + SH_PFC_PIN_GROUP(drif1_data0_a), + SH_PFC_PIN_GROUP(drif1_data1_a), + SH_PFC_PIN_GROUP(drif1_ctrl_b), + SH_PFC_PIN_GROUP(drif1_data0_b), + SH_PFC_PIN_GROUP(drif1_data1_b), + SH_PFC_PIN_GROUP(drif1_ctrl_c), + SH_PFC_PIN_GROUP(drif1_data0_c), + SH_PFC_PIN_GROUP(drif1_data1_c), + SH_PFC_PIN_GROUP(drif2_ctrl_a), + SH_PFC_PIN_GROUP(drif2_data0_a), + SH_PFC_PIN_GROUP(drif2_data1_a), + SH_PFC_PIN_GROUP(drif2_ctrl_b), + SH_PFC_PIN_GROUP(drif2_data0_b), + SH_PFC_PIN_GROUP(drif2_data1_b), + SH_PFC_PIN_GROUP(drif3_ctrl_a), + SH_PFC_PIN_GROUP(drif3_data0_a), + SH_PFC_PIN_GROUP(drif3_data1_a), + SH_PFC_PIN_GROUP(drif3_ctrl_b), + SH_PFC_PIN_GROUP(drif3_data0_b), + SH_PFC_PIN_GROUP(drif3_data1_b), + } +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; static const char * const audio_clk_groups[] = { @@ -4761,6 +4808,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4802,6 +4850,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ static const char * const du_groups[] = { "du_rgb666", @@ -5166,6 +5215,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -5210,61 +5266,73 @@ static const char * const vin5_groups[] = { "vin5_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(can0), - SH_PFC_FUNCTION(can1), - SH_PFC_FUNCTION(can_clk), - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), - SH_PFC_FUNCTION(drif0), - SH_PFC_FUNCTION(drif1), - SH_PFC_FUNCTION(drif2), - SH_PFC_FUNCTION(drif3), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(hscif2), - SH_PFC_FUNCTION(hscif3), - SH_PFC_FUNCTION(hscif4), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(i2c5), - SH_PFC_FUNCTION(i2c6), - SH_PFC_FUNCTION(intc_ex), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(sata0), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tmu), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb30), - SH_PFC_FUNCTION(vin4), - SH_PFC_FUNCTION(vin5), +static const struct { + struct sh_pfc_function common[51]; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 + struct sh_pfc_function automotive[4]; +#endif +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(sata0), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), + }, +#ifdef CONFIG_PINCTRL_PFC_R8A77965 + .automotive = { + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), + SH_PFC_FUNCTION(drif3), + } +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -6393,6 +6461,32 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { .set_bias = r8a77965_pinmux_set_bias, }; +#ifdef CONFIG_PINCTRL_PFC_R8A774B1 +const struct sh_pfc_soc_info r8a774b1_pinmux_info = { + .name = "r8a774b1_pfc", + .ops = &r8a77965_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A77965 const struct sh_pfc_soc_info r8a77965_pinmux_info = { .name = "r8a77965_pfc", .ops = &r8a77965_pinmux_ops, @@ -6402,10 +6496,12 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, @@ -6415,3 +6511,4 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = { .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 7183b118088..fb811a95bc2 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -33,6 +33,8 @@ enum sh_pfc_model { SH_PFC_R8A7795, SH_PFC_R8A7796, SH_PFC_R8A774A1, + SH_PFC_R8A774B1, + SH_PFC_R8A774E1, SH_PFC_R8A77965, SH_PFC_R8A77970, SH_PFC_R8A77980, @@ -48,10 +50,6 @@ struct sh_pfc_pinctrl { struct sh_pfc *pfc; struct sh_pfc_pin_config *configs; - - const char *func_prop_name; - const char *groups_prop_name; - const char *pins_prop_name; }; struct sh_pfc_pin_range { @@ -858,6 +856,14 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A774A1) priv->pfc.info = &r8a774a1_pinmux_info; #endif +#ifdef CONFIG_PINCTRL_PFC_R8A774B1 + if (model == SH_PFC_R8A774B1) + priv->pfc.info = &r8a774b1_pinmux_info; +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A774E1 + if (model == SH_PFC_R8A774E1) + priv->pfc.info = &r8a774e1_pinmux_info; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 if (model == SH_PFC_R8A77965) priv->pfc.info = &r8a77965_pinmux_info; @@ -935,6 +941,18 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A774A1, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A774B1 + { + .compatible = "renesas,pfc-r8a774b1", + .data = SH_PFC_R8A774B1, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A774E1 + { + .compatible = "renesas,pfc-r8a774e1", + .data = SH_PFC_R8A774E1, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 { .compatible = "renesas,pfc-r8a77965", diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 81c01799482..22cc860f296 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -294,6 +294,8 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, unsigned int *bit); extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; +extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; +extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 5910926faca..02050f6f356 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -14,7 +14,7 @@ choice default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 default AXP818_POWER if MACH_SUN8I_A83T - default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I + default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S config SUNXI_NO_PMIC bool "board without a pmic" @@ -32,7 +32,7 @@ config AXP152_POWER config AXP209_POWER bool "axp209 pmic support" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S select AXP_PMIC_BUS select CMD_POWEROFF ---help--- diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index a62aa38054c..7d51510d1b8 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -98,6 +98,13 @@ config DM_PMIC_PCA9450 This config enables implementation of driver-model pmic uclass features for PMIC PCA9450. The driver implements read/write operations. +config SPL_DM_PMIC_PCA9450 + bool "Enable Driver Model for PMIC PCA9450" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC PCA9450 in SPL. The driver implements read/write operations. + config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" depends on DM_PMIC diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 0c9d9a366e8..c7f8b809540 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -80,7 +80,7 @@ static struct dm_pmic_ops pca9450_ops = { }; static const struct udevice_id pca9450_ids[] = { - { .compatible = "nxp,pca9450a", .data = 0x35, }, + { .compatible = "nxp,pca9450a", .data = 0x25, }, { .compatible = "nxp,pca9450b", .data = 0x25, }, { } }; diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index b0d5cba2c49..f48af84e179 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -201,7 +201,7 @@ int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return 0; } -int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) +int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *valp, int len) { struct udevice *dev; int ret; @@ -211,12 +211,11 @@ int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) pr_err("unable to get I2C bus. ret %d\n", ret); return ret; } - ret = dm_i2c_reg_read(dev, reg); - if (ret < 0) { + ret = dm_i2c_read(dev, reg, valp, len); + if (ret) { pr_err("reading from twl4030 failed. ret %d\n", ret); return ret; } - *valp = (u8)ret; return 0; } #endif diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index 757436b9d37..aaff9c36879 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -2724,5 +2724,5 @@ U_BOOT_DRIVER(octeon_ddr) = { .of_match = octeon_ids, .ops = &octeon_ops, .probe = octeon_ddr_probe, - .platdata_auto_alloc_size = sizeof(struct ddr_priv), + .priv_auto_alloc_size = sizeof(struct ddr_priv), }; diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c index 33b574b1bd3..dc87cb794e4 100644 --- a/drivers/remoteproc/stm32_copro.c +++ b/drivers/remoteproc/stm32_copro.c @@ -8,30 +8,21 @@ #include <errno.h> #include <fdtdec.h> #include <log.h> -#include <regmap.h> #include <remoteproc.h> #include <reset.h> -#include <syscon.h> #include <asm/io.h> #include <dm/device_compat.h> #include <linux/err.h> -#define RCC_GCR_HOLD_BOOT 0 -#define RCC_GCR_RELEASE_BOOT 1 - /** * struct stm32_copro_privdata - power processor private data * @reset_ctl: reset controller handle - * @hold_boot_regmap: regmap for remote processor reset hold boot - * @hold_boot_offset: offset of the register controlling the hold boot setting - * @hold_boot_mask: bitmask of the register for the hold boot field + * @hold_boot: hold boot controller handle * @rsc_table_addr: resource table address */ struct stm32_copro_privdata { struct reset_ctl reset_ctl; - struct regmap *hold_boot_regmap; - uint hold_boot_offset; - uint hold_boot_mask; + struct reset_ctl hold_boot; ulong rsc_table_addr; }; @@ -43,32 +34,19 @@ struct stm32_copro_privdata { static int stm32_copro_probe(struct udevice *dev) { struct stm32_copro_privdata *priv; - struct regmap *regmap; - const fdt32_t *cell; - int len, ret; + int ret; priv = dev_get_priv(dev); - regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-holdboot"); - if (IS_ERR(regmap)) { - dev_err(dev, "unable to find holdboot regmap (%ld)\n", - PTR_ERR(regmap)); - return PTR_ERR(regmap); - } - - cell = dev_read_prop(dev, "st,syscfg-holdboot", &len); - if (len < 3 * sizeof(fdt32_t)) { - dev_err(dev, "holdboot offset and mask not available\n"); - return -EINVAL; + ret = reset_get_by_name(dev, "mcu_rst", &priv->reset_ctl); + if (ret) { + dev_err(dev, "failed to get reset (%d)\n", ret); + return ret; } - priv->hold_boot_regmap = regmap; - priv->hold_boot_offset = fdtdec_get_number(cell + 1, 1); - priv->hold_boot_mask = fdtdec_get_number(cell + 2, 1); - - ret = reset_get_by_index(dev, 0, &priv->reset_ctl); + ret = reset_get_by_name(dev, "hold_boot", &priv->hold_boot); if (ret) { - dev_err(dev, "failed to get reset (%d)\n", ret); + dev_err(dev, "failed to get hold boot (%d)\n", ret); return ret; } @@ -78,35 +56,6 @@ static int stm32_copro_probe(struct udevice *dev) } /** - * stm32_copro_set_hold_boot() - Hold boot bit management - * @dev: corresponding STM32 remote processor device - * @hold: hold boot value - * @return 0 if all went ok, else corresponding -ve error - */ -static int stm32_copro_set_hold_boot(struct udevice *dev, bool hold) -{ - struct stm32_copro_privdata *priv; - uint val; - int ret; - - priv = dev_get_priv(dev); - - val = hold ? RCC_GCR_HOLD_BOOT : RCC_GCR_RELEASE_BOOT; - - /* - * Note: shall run an SMC call (STM32_SMC_RCC) if platform is secured. - * To be updated when the code for this SMC service is available which - * is not the case for the time being. - */ - ret = regmap_update_bits(priv->hold_boot_regmap, priv->hold_boot_offset, - priv->hold_boot_mask, val); - if (ret) - dev_err(dev, "failed to set hold boot\n"); - - return ret; -} - -/** * stm32_copro_device_to_virt() - Convert device address to virtual address * @dev: corresponding STM32 remote processor device * @da: device address @@ -149,9 +98,11 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) priv = dev_get_priv(dev); - ret = stm32_copro_set_hold_boot(dev, true); - if (ret) + ret = reset_assert(&priv->hold_boot); + if (ret) { + dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); return ret; + } ret = reset_assert(&priv->reset_ctl); if (ret) { @@ -180,23 +131,26 @@ static int stm32_copro_start(struct udevice *dev) priv = dev_get_priv(dev); - /* move hold boot from true to false start the copro */ - ret = stm32_copro_set_hold_boot(dev, false); - if (ret) + ret = reset_deassert(&priv->hold_boot); + if (ret) { + dev_err(dev, "Unable to deassert hold boot (ret=%d)\n", ret); return ret; + } /* * Once copro running, reset hold boot flag to avoid copro - * rebooting autonomously + * rebooting autonomously (error should never occur) */ - ret = stm32_copro_set_hold_boot(dev, true); - writel(ret ? TAMP_COPRO_STATE_OFF : TAMP_COPRO_STATE_CRUN, - TAMP_COPRO_STATE); - if (!ret) - /* Store rsc_address in bkp register */ - writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); - - return ret; + ret = reset_assert(&priv->hold_boot); + if (ret) + dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); + + /* indicates that copro is running */ + writel(TAMP_COPRO_STATE_CRUN, TAMP_COPRO_STATE); + /* Store rsc_address in bkp register */ + writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); + + return 0; } /** @@ -211,9 +165,11 @@ static int stm32_copro_reset(struct udevice *dev) priv = dev_get_priv(dev); - ret = stm32_copro_set_hold_boot(dev, true); - if (ret) + ret = reset_assert(&priv->hold_boot); + if (ret) { + dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); return ret; + } ret = reset_assert(&priv->reset_ctl); if (ret) { diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index ac3a99f9bff..2cca67dc52a 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index 64a11cfcfc0..d8902e9d9cc 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> @@ -14,6 +14,9 @@ #include <asm/io.h> #include <linux/bitops.h> +/* offset of register without set/clear management */ +#define RCC_MP_GCR_OFFSET 0x10C + /* reset clear offset for STM32MP RCC */ #define RCC_CL 0x4 @@ -40,8 +43,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) - /* reset assert is done in rcc set register */ - writel(BIT(offset), priv->base + bank); + if (bank != RCC_MP_GCR_OFFSET) + /* reset assert is done in rcc set register */ + writel(BIT(offset), priv->base + bank); + else + clrbits_le32(priv->base + bank, BIT(offset)); else setbits_le32(priv->base + bank, BIT(offset)); @@ -57,8 +63,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) - /* reset deassert is done in rcc clr register */ - writel(BIT(offset), priv->base + bank + RCC_CL); + if (bank != RCC_MP_GCR_OFFSET) + /* reset deassert is done in rcc clr register */ + writel(BIT(offset), priv->base + bank + RCC_CL); + else + setbits_le32(priv->base + bank, BIT(offset)); else clrbits_le32(priv->base + bank, BIT(offset)); diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index 33ff396bff7..91e15746388 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -3,7 +3,7 @@ * Support for Serial I/O using STMicroelectronics' on-chip ASC. * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c index 3482d2a0787..43e161c65dc 100644 --- a/drivers/sysreset/sysreset_sti.c +++ b/drivers/sysreset/sysreset_sti.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c index e6843ebb337..9d95f562fac 100644 --- a/drivers/timer/sti-timer.c +++ b/drivers/timer/sti-timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index f517d5e61f2..2f5f8f43b96 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 9a8145e6ba1..0045bedf0c6 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -30,8 +30,6 @@ #include "tpm_tis.h" #include "tpm_internal.h" -DECLARE_GLOBAL_DATA_PTR; - #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) #define TPM_STS(l) (0x0018 | ((l) << 12)) @@ -520,7 +518,6 @@ static int tpm_tis_spi_cleanup(struct udevice *dev) static int tpm_tis_spi_open(struct udevice *dev) { struct tpm_chip *chip = dev_get_priv(dev); - struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); if (chip->is_open) return -EBUSY; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 36fa16ad4e2..a936f71d2e5 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -74,7 +74,7 @@ static int dwc3_generic_probe(struct udevice *dev, } rc = dwc3_setup_phy(dev, &priv->phys); - if (rc) + if (rc && rc != -ENOTSUPP) return rc; if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index eaa5dcb9b13..8a8e2179e48 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -1014,6 +1014,9 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) platdata->force_b_session_valid = dev_read_bool(dev, "u-boot,force-b-session-valid"); + platdata->force_vbus_detection = + dev_read_bool(dev, "u-boot,force-vbus-detection"); + /* force platdata according compatible */ drvdata = dev_get_driver_data(dev); if (drvdata) { @@ -1045,7 +1048,7 @@ static int dwc2_udc_otg_reset_init(struct udevice *dev, int ret; ret = reset_get_bulk(dev, resets); - if (ret == -ENOTSUPP) + if (ret == -ENOTSUPP || ret == -ENOENT) return 0; if (ret) @@ -1106,31 +1109,45 @@ static int dwc2_udc_otg_probe(struct udevice *dev) if (ret) return ret; - if (CONFIG_IS_ENABLED(DM_REGULATOR) && - platdata->activate_stm_id_vb_detection && - !platdata->force_b_session_valid) { - ret = device_get_supply_regulator(dev, "usb33d-supply", - &priv->usb33d_supply); - if (ret) { - dev_err(dev, "can't get voltage level detector supply\n"); - return ret; + if (platdata->activate_stm_id_vb_detection) { + if (CONFIG_IS_ENABLED(DM_REGULATOR) && + (!platdata->force_b_session_valid || + platdata->force_vbus_detection)) { + ret = device_get_supply_regulator(dev, "usb33d-supply", + &priv->usb33d_supply); + if (ret) { + dev_err(dev, "can't get voltage level detector supply\n"); + return ret; + } + ret = regulator_set_enable(priv->usb33d_supply, true); + if (ret) { + dev_err(dev, "can't enable voltage level detector supply\n"); + return ret; + } } - ret = regulator_set_enable(priv->usb33d_supply, true); - if (ret) { - dev_err(dev, "can't enable voltage level detector supply\n"); - return ret; + + if (platdata->force_b_session_valid && + !platdata->force_vbus_detection) { + /* Override VBUS detection: enable then value*/ + setbits_le32(&usbotg_reg->gotgctl, VB_VALOEN); + setbits_le32(&usbotg_reg->gotgctl, VB_VALOVAL); + } else { + /* Enable VBUS sensing */ + setbits_le32(&usbotg_reg->ggpio, + GGPIO_STM32_OTG_GCCFG_VBDEN); + } + if (platdata->force_b_session_valid) { + /* Override B session bits: enable then value */ + setbits_le32(&usbotg_reg->gotgctl, A_VALOEN | B_VALOEN); + setbits_le32(&usbotg_reg->gotgctl, + A_VALOVAL | B_VALOVAL); + } else { + /* Enable ID detection */ + setbits_le32(&usbotg_reg->ggpio, + GGPIO_STM32_OTG_GCCFG_IDEN); } - /* Enable vbus sensing */ - setbits_le32(&usbotg_reg->ggpio, - GGPIO_STM32_OTG_GCCFG_VBDEN | - GGPIO_STM32_OTG_GCCFG_IDEN); } - if (platdata->force_b_session_valid) - /* Override B session bits : value and enable */ - setbits_le32(&usbotg_reg->gotgctl, - A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL); - ret = dwc2_udc_probe(platdata); if (ret) return ret; diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index 2eda5c37206..9ca6f423757 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -94,6 +94,8 @@ struct dwc2_usbotg_reg { #define B_VALOEN BIT(6) #define A_VALOVAL BIT(5) #define A_VALOEN BIT(4) +#define VB_VALOVAL BIT(3) +#define VB_VALOEN BIT(2) /* DWC2_UDC_OTG_GOTINT */ #define GOTGINT_SES_END_DET (1<<2) diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c index 3e6c1429d66..9dec0877389 100644 --- a/drivers/usb/host/dwc3-sti-glue.c +++ b/drivers/usb/host/dwc3-sti-glue.c @@ -3,7 +3,7 @@ * STiH407 family DWC3 specific Glue layer * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #include <common.h> diff --git a/drivers/video/backlight_gpio.c b/drivers/video/backlight_gpio.c index 67fed7f224a..433d0979e88 100644 --- a/drivers/video/backlight_gpio.c +++ b/drivers/video/backlight_gpio.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author: Patrick Delaunay <patrick.delaunay@st.com> + * Author: Patrick Delaunay <patrick.delaunay@foss.st.com> */ #include <common.h> diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 7b2ff94eba5..5d74f7f1a74 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -379,7 +379,9 @@ static int meson_dw_hdmi_probe(struct udevice *dev) struct meson_dw_hdmi *priv = dev_get_priv(dev); struct reset_ctl_bulk resets; struct clk_bulk clocks; +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *supply; +#endif int ret; priv->dev = dev; diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index b232ff0b76b..8ac0125b502 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao <eric.gao@rock-chips.com> diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index 68d1507cda4..9ec33e6e511 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH * Copyright (c) 2015 Google, Inc diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 113708d97e5..e5534c36e6e 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao <eric.gao@rock-chips.com> diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index d5a7aa8ac1b..55d1be0411d 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH * Copyright (c) 2015 Google, Inc diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index a032eb68895..c55f7a4f72a 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index f811913ce5e..d125a5ba737 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao <eric.gao@rock-chips.com> diff --git a/drivers/video/rockchip/rk_mipi.h b/drivers/video/rockchip/rk_mipi.h index 61920f23ad9..3d1e440b0ec 100644 --- a/drivers/video/rockchip/rk_mipi.h +++ b/drivers/video/rockchip/rk_mipi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd * Author: Eric Gao <eric.gao@rock-chips.com> diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 9032eb430e7..6475b3e2aff 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h index 8fa2f389390..53a79c04b5c 100644 --- a/drivers/video/rockchip/rk_vop.h +++ b/drivers/video/rockchip/rk_vop.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 2eae431ba6c..96285c1a9b4 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -61,7 +61,7 @@ static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) * to half value of timeout. */ clk = get_tbclk(); - writel(clk / 2 * timeout, + writel(clk / (2 * 1000) * timeout, priv->reg_control + SBSA_GWDT_WOR); /* writing WCS will cause an explicit watchdog refresh */ diff --git a/env/mmc.c b/env/mmc.c index 4e67180b23a..ee376c3e0c3 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -42,7 +42,7 @@ static inline int mmc_offset_try_partition(const char *str, int copy, s64 *val) if (ret < 0) return ret; - if (!strncmp((const char *)info.name, str, sizeof(str))) + if (!strncmp((const char *)info.name, str, sizeof(info.name))) break; } diff --git a/env/nowhere.c b/env/nowhere.c index d33fdf27d0c..d43a2d6b513 100644 --- a/env/nowhere.c +++ b/env/nowhere.c @@ -30,7 +30,7 @@ static int env_nowhere_init(void) static int env_nowhere_load(void) { /* - * for SPL, set env_valid = ENV_INVALID is enougth as env_get_char() + * for SPL, set env_valid = ENV_INVALID is enough as env_get_char() * return the default env if env_get is used * and SPL don't used env_import to reduce its size * For U-Boot proper, import the default environment to allow reload. diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c index e48972ffa21..346b2c4341c 100644 --- a/fs/btrfs/btrfs.c +++ b/fs/btrfs/btrfs.c @@ -36,7 +36,7 @@ static int show_dir(struct btrfs_root *root, struct extent_buffer *eb, char *target = NULL; char filetime[32]; time_t mtime; - int ret; + int ret = 0; btrfs_dir_item_key_to_cpu(eb, di, &key); diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index ff330280e02..019d532a1a4 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -251,7 +251,7 @@ int btrfs_lookup_path(struct btrfs_root *root, u64 ino, const char *filename, const char *cur = filename; u64 next_ino; u8 next_type; - u8 type; + u8 type = BTRFS_FT_UNKNOWN; int len; int ret = 0; @@ -335,6 +335,10 @@ next: cur += len; } + /* We haven't found anything, but still get no error? */ + if (type == BTRFS_FT_UNKNOWN && !ret) + ret = -EUCLEAN; + if (!ret) { *root_ret = root; *ino_ret = ino; diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 28aa5aaa9ff..fb6ba894664 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -926,8 +926,7 @@ static int fat_itr_next(fat_itr *itr) if (!dent) return 0; - if (dent->name[0] == DELETED_FLAG || - dent->name[0] == aRING) + if (dent->name[0] == DELETED_FLAG) continue; if (dent->attr & ATTR_VOLUME) { diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index a2682b5f465..7afc8388b23 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -260,9 +260,8 @@ fill_dir_slot(fat_itr *itr, const char *l_name) flush_dir(itr); /* allocate a cluster for more entries */ - if (!fat_itr_next(itr)) - if (!itr->dent && - (!itr->is_root || itr->fsdata->fatsize == 32) && + if (!fat_itr_next(itr) && !itr->dent) + if ((itr->is_root && itr->fsdata->fatsize != 32) || new_dir_table(itr)) return -1; } @@ -1192,7 +1191,8 @@ int file_fat_write_at(const char *filename, loff_t pos, void *buffer, } /* Set short name entry */ - fill_dentry(itr->fsdata, itr->dent, filename, 0, size, 0x20); + fill_dentry(itr->fsdata, itr->dent, filename, 0, size, + ATTR_ARCH); retdent = itr->dent; } @@ -287,6 +287,7 @@ static struct fstype_info fstypes[] = { { .fstype = FS_TYPE_SQUASHFS, .name = "squashfs", + .null_dev_desc_ok = false, .probe = sqfs_probe, .opendir = sqfs_opendir, .readdir = sqfs_readdir, @@ -295,6 +296,12 @@ static struct fstype_info fstypes[] = { .size = sqfs_size, .close = sqfs_close, .closedir = sqfs_closedir, + .exists = sqfs_exists, + .uuid = fs_uuid_unsupported, + .write = fs_write_unsupported, + .ln = fs_ln_unsupported, + .unlink = fs_unlink_unsupported, + .mkdir = fs_mkdir_unsupported, }, #endif { diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 15208b4dab0..5de69ac3ca0 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -49,6 +49,7 @@ static int sqfs_read_sblk(struct squashfs_super_block **sblk) if (sqfs_disk_read(0, 1, *sblk) != 1) { free(*sblk); + sblk = NULL; return -EINVAL; } @@ -106,6 +107,10 @@ static int sqfs_frag_lookup(u32 inode_fragment_index, int block, offset, ret; u16 header; + metadata_buffer = NULL; + entries = NULL; + table = NULL; + if (inode_fragment_index >= get_unaligned_le32(&sblk->fragments)) return -EINVAL; @@ -117,12 +122,14 @@ static int sqfs_frag_lookup(u32 inode_fragment_index, /* Allocate a proper sized buffer to store the fragment index table */ table = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); - if (!table) - return -ENOMEM; + if (!table) { + ret = -ENOMEM; + goto out; + } if (sqfs_disk_read(start, n_blks, table) < 0) { - free(table); - return -EINVAL; + ret = -EINVAL; + goto out; } block = SQFS_FRAGMENT_INDEX(inode_fragment_index); @@ -142,12 +149,12 @@ static int sqfs_frag_lookup(u32 inode_fragment_index, metadata_buffer = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); if (!metadata_buffer) { ret = -ENOMEM; - goto free_table; + goto out; } if (sqfs_disk_read(start, n_blks, metadata_buffer) < 0) { ret = -EINVAL; - goto free_buffer; + goto out; } /* Every metadata block starts with a 16-bit header */ @@ -156,13 +163,13 @@ static int sqfs_frag_lookup(u32 inode_fragment_index, if (!metadata || !header) { ret = -ENOMEM; - goto free_buffer; + goto out; } entries = malloc(SQFS_METADATA_BLOCK_SIZE); if (!entries) { ret = -ENOMEM; - goto free_buffer; + goto out; } if (SQFS_COMPRESSED_METADATA(header)) { @@ -172,7 +179,7 @@ static int sqfs_frag_lookup(u32 inode_fragment_index, src_len); if (ret) { ret = -EINVAL; - goto free_entries; + goto out; } } else { memcpy(entries, metadata, SQFS_METADATA_SIZE(header)); @@ -181,11 +188,9 @@ static int sqfs_frag_lookup(u32 inode_fragment_index, *e = entries[offset]; ret = SQFS_COMPRESSED_BLOCK(e->size); -free_entries: +out: free(entries); -free_buffer: free(metadata_buffer); -free_table: free(table); return ret; @@ -242,6 +247,9 @@ static char *sqfs_concat_tokens(char **token_list, int token_count) length = sqfs_get_tokens_length(token_list, token_count); result = malloc(length + 1); + if (!result) + return NULL; + result[length] = '\0'; for (i = 0; i < token_count; i++) { @@ -333,28 +341,31 @@ static char *sqfs_get_abs_path(const char *base, const char *rel) char **base_tokens, **rel_tokens, *resolved = NULL; int ret, bc, rc, i, updir = 0, resolved_size = 0, offset = 0; + base_tokens = NULL; + rel_tokens = NULL; + /* Memory allocation for the token lists */ bc = sqfs_count_tokens(base); rc = sqfs_count_tokens(rel); if (bc < 1 || rc < 1) return NULL; - base_tokens = malloc(bc * sizeof(char *)); + base_tokens = calloc(bc, sizeof(char *)); if (!base_tokens) return NULL; - rel_tokens = malloc(rc * sizeof(char *)); + rel_tokens = calloc(rc, sizeof(char *)); if (!rel_tokens) - goto free_b_tokens; + goto out; /* Fill token lists */ ret = sqfs_tokenize(base_tokens, bc, base); if (ret) - goto free_r_tokens; + goto out; - sqfs_tokenize(rel_tokens, rc, rel); + ret = sqfs_tokenize(rel_tokens, rc, rel); if (ret) - goto free_r_tokens; + goto out; /* count '..' occurrences in target path */ for (i = 0; i < rc; i++) { @@ -365,7 +376,7 @@ static char *sqfs_get_abs_path(const char *base, const char *rel) /* Remove the last token and the '..' occurrences */ bc = sqfs_clean_base_path(base_tokens, bc, updir); if (bc < 0) - goto free_r_tokens; + goto out; /* Calculate resolved path size */ if (!bc) @@ -376,7 +387,7 @@ static char *sqfs_get_abs_path(const char *base, const char *rel) resolved = malloc(resolved_size + 1); if (!resolved) - goto free_r_tokens_loop; + goto out; /* Set resolved path */ memset(resolved, '\0', resolved_size + 1); @@ -384,14 +395,15 @@ static char *sqfs_get_abs_path(const char *base, const char *rel) resolved[offset++] = '/'; offset += sqfs_join(rel_tokens, resolved + offset, updir, rc, '/'); -free_r_tokens_loop: - for (i = 0; i < rc; i++) - free(rel_tokens[i]); - for (i = 0; i < bc; i++) - free(base_tokens[i]); -free_r_tokens: +out: + if (rel_tokens) + for (i = 0; i < rc; i++) + free(rel_tokens[i]); + if (base_tokens) + for (i = 0; i < bc; i++) + free(base_tokens[i]); + free(rel_tokens); -free_b_tokens: free(base_tokens); return resolved; @@ -434,7 +446,7 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, { struct squashfs_super_block *sblk = ctxt.sblk; char *path, *target, **sym_tokens, *res, *rem; - int j, ret, new_inode_number, offset; + int j, ret = 0, new_inode_number, offset; struct squashfs_symlink_inode *sym; struct squashfs_ldir_inode *ldir; struct squashfs_dir_inode *dir; @@ -442,6 +454,12 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, struct fs_dirent *dent; unsigned char *table; + res = NULL; + rem = NULL; + path = NULL; + target = NULL; + sym_tokens = NULL; + dirsp = (struct fs_dir_stream *)dirs; /* Start by root inode */ @@ -477,7 +495,8 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, for (j = 0; j < token_count; j++) { if (!sqfs_is_dir(get_unaligned_le16(&dir->inode_type))) { printf("** Cannot find directory. **\n"); - return -EINVAL; + ret = -EINVAL; + goto out; } while (!sqfs_readdir(dirsp, &dent)) { @@ -485,11 +504,13 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, if (!ret) break; free(dirs->entry); + dirs->entry = NULL; } if (ret) { printf("** Cannot find directory. **\n"); - return -EINVAL; + ret = -EINVAL; + goto out; } /* Redefine inode as the found token */ @@ -506,38 +527,63 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, sym = (struct squashfs_symlink_inode *)table; /* Get first j + 1 tokens */ path = sqfs_concat_tokens(token_list, j + 1); + if (!path) { + ret = -ENOMEM; + goto out; + } /* Resolve for these tokens */ target = sqfs_resolve_symlink(sym, path); + if (!target) { + ret = -ENOMEM; + goto out; + } /* Join remaining tokens */ rem = sqfs_concat_tokens(token_list + j + 1, token_count - j - 1); + if (!rem) { + ret = -ENOMEM; + goto out; + } /* Concatenate remaining tokens and symlink's target */ res = malloc(strlen(rem) + strlen(target) + 1); + if (!res) { + ret = -ENOMEM; + goto out; + } strcpy(res, target); res[strlen(target)] = '/'; strcpy(res + strlen(target) + 1, rem); token_count = sqfs_count_tokens(res); - if (token_count < 0) - return -EINVAL; + if (token_count < 0) { + ret = -EINVAL; + goto out; + } sym_tokens = malloc(token_count * sizeof(char *)); - if (!sym_tokens) - return -EINVAL; + if (!sym_tokens) { + ret = -EINVAL; + goto out; + } /* Fill tokens list */ ret = sqfs_tokenize(sym_tokens, token_count, res); - if (ret) - return -EINVAL; + if (ret) { + ret = -EINVAL; + goto out; + } free(dirs->entry); + dirs->entry = NULL; ret = sqfs_search_dir(dirs, sym_tokens, token_count, m_list, m_count); - return ret; + goto out; } else if (!sqfs_is_dir(get_unaligned_le16(&dir->inode_type))) { printf("** Cannot find directory. **\n"); free(dirs->entry); - return -EINVAL; + dirs->entry = NULL; + ret = -EINVAL; + goto out; } /* Check if it is an extended dir. */ @@ -556,7 +602,9 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, if (sqfs_is_empty_dir(table)) { printf("Empty directory.\n"); free(dirs->entry); - return SQFS_EMPTY_DIR; + dirs->entry = NULL; + ret = SQFS_EMPTY_DIR; + goto out; } dirs->table += SQFS_DIR_HEADER_SIZE; @@ -564,6 +612,7 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, dirs->entry_count = dirs->dir_header->count + 1; dirs->size -= SQFS_DIR_HEADER_SIZE; free(dirs->entry); + dirs->entry = NULL; } offset = sqfs_dir_offset(table, m_list, m_count); @@ -574,7 +623,13 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, else memcpy(&dirs->i_ldir, ldir, sizeof(*ldir)); - return 0; +out: + free(res); + free(rem); + free(path); + free(target); + free(sym_tokens); + return ret; } /* @@ -688,6 +743,7 @@ static int sqfs_read_inode_table(unsigned char **inode_table) src_table, src_len); if (ret) { free(*inode_table); + *inode_table = NULL; goto free_itb; } @@ -722,6 +778,8 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) unsigned long dest_len = 0; bool compressed; + *dir_table = NULL; + *pos_list = NULL; /* DIRECTORY TABLE */ table_size = get_unaligned_le64(&sblk->fragment_table_start) - get_unaligned_le64(&sblk->directory_table_start); @@ -736,35 +794,31 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) return -ENOMEM; if (sqfs_disk_read(start, n_blks, dtb) < 0) - goto free_dtb; + goto out; /* Parse directory table (metadata block) header */ ret = sqfs_read_metablock(dtb, table_offset, &compressed, &src_len); if (ret) - goto free_dtb; + goto out; /* Calculate total size to store the whole decompressed table */ metablks_count = sqfs_count_metablks(dtb, table_offset, table_size); if (metablks_count < 1) - goto free_dtb; + goto out; *dir_table = malloc(metablks_count * SQFS_METADATA_BLOCK_SIZE); if (!*dir_table) - goto free_dtb; + goto out; *pos_list = malloc(metablks_count * sizeof(u32)); - if (!*pos_list) { - free(*dir_table); - goto free_dtb; - } + if (!*pos_list) + goto out; ret = sqfs_get_metablk_pos(*pos_list, dtb, table_offset, metablks_count); if (ret) { metablks_count = -1; - free(*dir_table); - free(*pos_list); - goto free_dtb; + goto out; } src_table = dtb + table_offset + SQFS_HEADER_SIZE; @@ -780,8 +834,7 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) &dest_len, src_table, src_len); if (ret) { metablks_count = -1; - free(*dir_table); - goto free_dtb; + goto out; } if (dest_len < SQFS_METADATA_BLOCK_SIZE) { @@ -803,7 +856,13 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) src_table += src_len + SQFS_HEADER_SIZE; } -free_dtb: +out: + if (metablks_count < 1) { + free(*dir_table); + free(*pos_list); + *dir_table = NULL; + *pos_list = NULL; + } free(dtb); return metablks_count; @@ -812,42 +871,57 @@ free_dtb: int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp) { unsigned char *inode_table = NULL, *dir_table = NULL; - int j, token_count, ret = 0, metablks_count; + int j, token_count = 0, ret = 0, metablks_count; struct squashfs_dir_stream *dirs; - char **token_list, *path; + char **token_list = NULL, *path = NULL; u32 *pos_list = NULL; dirs = malloc(sizeof(*dirs)); if (!dirs) return -EINVAL; + /* these should be set to NULL to prevent dangling pointers */ + dirs->dir_header = NULL; + dirs->entry = NULL; + dirs->table = NULL; + dirs->inode_table = NULL; + dirs->dir_table = NULL; + ret = sqfs_read_inode_table(&inode_table); - if (ret) - return -EINVAL; + if (ret) { + ret = -EINVAL; + goto out; + } metablks_count = sqfs_read_directory_table(&dir_table, &pos_list); - if (metablks_count < 1) - return -EINVAL; + if (metablks_count < 1) { + ret = -EINVAL; + goto out; + } /* Tokenize filename */ token_count = sqfs_count_tokens(filename); - if (token_count < 0) - return -EINVAL; + if (token_count < 0) { + ret = -EINVAL; + goto out; + } path = strdup(filename); - if (!path) - return -ENOMEM; + if (!path) { + ret = -EINVAL; + goto out; + } token_list = malloc(token_count * sizeof(char *)); if (!token_list) { ret = -EINVAL; - goto free_path; + goto out; } /* Fill tokens list */ ret = sqfs_tokenize(token_list, token_count, path); if (ret) - goto free_tokens; + goto out; /* * ldir's (extended directory) size is greater than dir, so it works as * a general solution for the malloc size, since 'i' is a union. @@ -857,7 +931,7 @@ int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp) ret = sqfs_search_dir(dirs, token_list, token_count, pos_list, metablks_count); if (ret) - goto free_tokens; + goto out; if (le16_to_cpu(dirs->i_dir.inode_type) == SQFS_DIR_TYPE) dirs->size = le16_to_cpu(dirs->i_dir.file_size); @@ -875,13 +949,16 @@ int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp) *dirsp = (struct fs_dir_stream *)dirs; -free_tokens: +out: for (j = 0; j < token_count; j++) free(token_list[j]); free(token_list); free(pos_list); -free_path: free(path); + if (ret) { + free(inode_table); + free(dirs); + } return ret; } @@ -1009,26 +1086,28 @@ int sqfs_probe(struct blk_desc *fs_dev_desc, struct disk_partition *fs_partition ret = sqfs_read_sblk(&sblk); if (ret) - return ret; + goto error; /* Make sure it has a valid SquashFS magic number*/ if (get_unaligned_le32(&sblk->s_magic) != SQFS_MAGIC_NUMBER) { printf("Bad magic number for SquashFS image.\n"); - ctxt.cur_dev = NULL; - return -EINVAL; + ret = -EINVAL; + goto error; } ctxt.sblk = sblk; ret = sqfs_decompressor_init(&ctxt); - if (ret) { - ctxt.cur_dev = NULL; - free(ctxt.sblk); - return -EINVAL; + goto error; } return 0; +error: + ctxt.cur_dev = NULL; + free(ctxt.sblk); + ctxt.sblk = NULL; + return ret; } static char *sqfs_basename(char *path) @@ -1071,15 +1150,27 @@ static int sqfs_split_path(char **file, char **dir, const char *path) char *dirc, *basec, *bname, *dname, *tmp_path; int ret = 0; + *file = NULL; + *dir = NULL; + dirc = NULL; + basec = NULL; + bname = NULL; + dname = NULL; + tmp_path = NULL; + /* check for first slash in path*/ if (path[0] == '/') { tmp_path = strdup(path); - if (!tmp_path) - return -ENOMEM; + if (!tmp_path) { + ret = -ENOMEM; + goto out; + } } else { tmp_path = malloc(strlen(path) + 2); - if (!tmp_path) - return -ENOMEM; + if (!tmp_path) { + ret = -ENOMEM; + goto out; + } tmp_path[0] = '/'; strcpy(tmp_path + 1, path); } @@ -1088,13 +1179,13 @@ static int sqfs_split_path(char **file, char **dir, const char *path) dirc = strdup(tmp_path); if (!dirc) { ret = -ENOMEM; - goto free_tmp; + goto out; } basec = strdup(tmp_path); if (!basec) { ret = -ENOMEM; - goto free_dirc; + goto out; } dname = sqfs_dirname(dirc); @@ -1104,14 +1195,14 @@ static int sqfs_split_path(char **file, char **dir, const char *path) if (!*file) { ret = -ENOMEM; - goto free_basec; + goto out; } if (*dname == '\0') { *dir = malloc(2); if (!*dir) { ret = -ENOMEM; - goto free_basec; + goto out; } (*dir)[0] = '/'; @@ -1120,15 +1211,19 @@ static int sqfs_split_path(char **file, char **dir, const char *path) *dir = strdup(dname); if (!*dir) { ret = -ENOMEM; - goto free_basec; + goto out; } } -free_basec: +out: + if (ret) { + free(*file); + free(*dir); + *dir = NULL; + *file = NULL; + } free(basec); -free_dirc: free(dirc); -free_tmp: free(tmp_path); return ret; @@ -1213,8 +1308,8 @@ static int sqfs_get_lregfile_info(struct squashfs_lreg_inode *lreg, int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, loff_t *actread) { - char *dir, *fragment_block, *datablock = NULL, *data_buffer = NULL; - char *fragment, *file, *resolved, *data; + char *dir = NULL, *fragment_block, *datablock = NULL, *data_buffer = NULL; + char *fragment = NULL, *file = NULL, *resolved, *data; u64 start, n_blks, table_size, data_offset, table_offset; int ret, j, i_number, datablk_count = 0; struct squashfs_super_block *sblk = ctxt.sblk; @@ -1232,6 +1327,14 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, *actread = 0; + if (offset) { + /* + * TODO: implement reading at an offset in file + */ + printf("Error: reading at a specific offset in a squashfs file is not supported yet.\n"); + return -EINVAL; + } + /* * sqfs_opendir will uncompress inode and directory tables, and will * return a pointer to the directory that contains the requested file. @@ -1239,8 +1342,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, sqfs_split_path(&file, &dir, filename); ret = sqfs_opendir(dir, &dirsp); if (ret) { - sqfs_closedir(dirsp); - goto free_paths; + goto out; } dirs = (struct squashfs_dir_stream *)dirsp; @@ -1252,14 +1354,14 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, break; free(dirs->entry); + dirs->entry = NULL; } if (ret) { printf("File not found.\n"); *actread = 0; - sqfs_closedir(dirsp); ret = -ENOENT; - goto free_paths; + goto out; } i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset; @@ -1274,7 +1376,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, sblk->block_size); if (datablk_count < 0) { ret = -EINVAL; - goto free_paths; + goto out; } memcpy(finfo.blk_sizes, ipos + sizeof(*reg), @@ -1287,7 +1389,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, sblk->block_size); if (datablk_count < 0) { ret = -EINVAL; - goto free_paths; + goto out; } memcpy(finfo.blk_sizes, ipos + sizeof(*lreg), @@ -1299,7 +1401,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, resolved = sqfs_resolve_symlink(symlink, filename); ret = sqfs_read(resolved, buf, offset, len, actread); free(resolved); - goto free_paths; + goto out; case SQFS_BLKDEV_TYPE: case SQFS_CHRDEV_TYPE: case SQFS_LBLKDEV_TYPE: @@ -1311,17 +1413,19 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, default: printf("Unsupported entry type\n"); ret = -EINVAL; - goto free_paths; + goto out; } /* If the user specifies a length, check its sanity */ if (len) { if (len > finfo.size) { ret = -EINVAL; - goto free_paths; + goto out; } finfo.size = len; + } else { + len = finfo.size; } if (datablk_count) { @@ -1329,7 +1433,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, datablock = malloc(get_unaligned_le32(&sblk->block_size)); if (!datablock) { ret = -ENOMEM; - goto free_paths; + goto out; } } @@ -1344,7 +1448,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, if (!data_buffer) { ret = -ENOMEM; - goto free_datablk; + goto out; } ret = sqfs_disk_read(start, n_blks, data_buffer); @@ -1355,7 +1459,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, * image with mksquashfs's -b <block_size> option. */ printf("Error: too many data blocks to be read.\n"); - goto free_buffer; + goto out; } data = data_buffer + table_offset; @@ -1366,26 +1470,32 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, ret = sqfs_decompress(&ctxt, datablock, &dest_len, data, table_size); if (ret) - goto free_buffer; + goto out; - memcpy(buf + offset + *actread, datablock, dest_len); + if ((*actread + dest_len) > len) + dest_len = len - *actread; + memcpy(buf + *actread, datablock, dest_len); *actread += dest_len; } else { - memcpy(buf + offset + *actread, data, table_size); + if ((*actread + table_size) > len) + table_size = len - *actread; + memcpy(buf + *actread, data, table_size); *actread += table_size; } data_offset += table_size; + free(data_buffer); + data_buffer = NULL; + if (*actread >= len) + break; } - free(finfo.blk_sizes); - /* * There is no need to continue if the file is not fragmented. */ if (!finfo.frag) { ret = 0; - goto free_buffer; + goto out; } start = frag_entry.start / ctxt.cur_dev->blksz; @@ -1397,12 +1507,12 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, if (!fragment) { ret = -ENOMEM; - goto free_buffer; + goto out; } ret = sqfs_disk_read(start, n_blks, fragment); if (ret < 0) - goto free_fragment; + goto out; /* File compressed and fragmented */ if (finfo.frag && finfo.comp) { @@ -1410,7 +1520,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, fragment_block = malloc(dest_len); if (!fragment_block) { ret = -ENOMEM; - goto free_fragment; + goto out; } ret = sqfs_decompress(&ctxt, fragment_block, &dest_len, @@ -1418,10 +1528,10 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, frag_entry.size); if (ret) { free(fragment_block); - goto free_fragment; + goto out; } - for (j = offset + *actread; j < finfo.size; j++) { + for (j = *actread; j < finfo.size; j++) { memcpy(buf + j, &fragment_block[finfo.offset + j], 1); (*actread)++; } @@ -1431,23 +1541,22 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, } else if (finfo.frag && !finfo.comp) { fragment_block = (void *)fragment + table_offset; - for (j = offset + *actread; j < finfo.size; j++) { + for (j = *actread; j < finfo.size; j++) { memcpy(buf + j, &fragment_block[finfo.offset + j], 1); (*actread)++; } } -free_fragment: +out: free(fragment); -free_buffer: - if (datablk_count) + if (datablk_count) { free(data_buffer); -free_datablk: - if (datablk_count) free(datablock); -free_paths: + } free(file); free(dir); + free(finfo.blk_sizes); + sqfs_closedir(dirsp); return ret; } @@ -1473,7 +1582,6 @@ int sqfs_size(const char *filename, loff_t *size) */ ret = sqfs_opendir(dir, &dirsp); if (ret) { - sqfs_closedir(dirsp); ret = -EINVAL; goto free_strings; } @@ -1485,6 +1593,7 @@ int sqfs_size(const char *filename, loff_t *size) if (!ret) break; free(dirs->entry); + dirs->entry = NULL; } if (ret) { @@ -1498,6 +1607,7 @@ int sqfs_size(const char *filename, loff_t *size) ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes, sblk->block_size); free(dirs->entry); + dirs->entry = NULL; base = (struct squashfs_base_inode *)ipos; switch (get_unaligned_le16(&base->inode_type)) { @@ -1540,11 +1650,50 @@ free_strings: return ret; } +int sqfs_exists(const char *filename) +{ + struct fs_dir_stream *dirsp = NULL; + struct squashfs_dir_stream *dirs; + char *dir, *file; + struct fs_dirent *dent; + int ret; + + sqfs_split_path(&file, &dir, filename); + /* + * sqfs_opendir will uncompress inode and directory tables, and will + * return a pointer to the directory that contains the requested file. + */ + ret = sqfs_opendir(dir, &dirsp); + if (ret) { + ret = -EINVAL; + goto free_strings; + } + + dirs = (struct squashfs_dir_stream *)dirsp; + + while (!sqfs_readdir(dirsp, &dent)) { + ret = strcmp(dent->name, file); + if (!ret) + break; + free(dirs->entry); + dirs->entry = NULL; + } + + sqfs_closedir(dirsp); + +free_strings: + free(dir); + free(file); + + return ret == 0; +} + void sqfs_close(void) { + sqfs_decompressor_cleanup(&ctxt); free(ctxt.sblk); + ctxt.sblk = NULL; ctxt.cur_dev = NULL; - sqfs_decompressor_cleanup(&ctxt); } void sqfs_closedir(struct fs_dir_stream *dirs) @@ -1555,4 +1704,5 @@ void sqfs_closedir(struct fs_dir_stream *dirs) free(sqfs_dirs->inode_table); free(sqfs_dirs->dir_table); free(sqfs_dirs->dir_header); + free(sqfs_dirs); } diff --git a/fs/squashfs/sqfs_inode.c b/fs/squashfs/sqfs_inode.c index 14d70cf6789..e76ec7cbdfd 100644 --- a/fs/squashfs/sqfs_inode.c +++ b/fs/squashfs/sqfs_inode.c @@ -49,7 +49,7 @@ int sqfs_inode_size(struct squashfs_base_inode *inode, u32 blk_size) return sizeof(*ldir); di = ldir->index; - while (l < i_count + 1) { + while (l < i_count) { sz = get_unaligned_le32(&di->size) + 1; index_list_size += sz; di = (void *)di + sizeof(*di) + sz; @@ -57,7 +57,7 @@ int sqfs_inode_size(struct squashfs_base_inode *inode, u32 blk_size) } return sizeof(*ldir) + index_list_size + - (i_count + 1) * SQFS_DIR_INDEX_BASE_LENGTH; + i_count * SQFS_DIR_INDEX_BASE_LENGTH; } case SQFS_LREG_TYPE: { diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 87d827d0f43..887b5c268de 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -196,7 +196,7 @@ struct global_data { */ struct list_head uclass_root; # if CONFIG_IS_ENABLED(OF_PLATDATA) - /** Dynamic info about the driver */ + /** @dm_driver_rt: Dynamic info about the driver */ struct driver_rt *dm_driver_rt; # endif #endif diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index ff29ef5a905..82a3a365c5b 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -118,8 +118,10 @@ "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ "fi; " #else +#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK #define BOOTENV_EFI_SET_FDTFILE_FALLBACK #endif +#endif #define BOOTENV_SHARED_EFI \ diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h new file mode 100644 index 00000000000..db31c210f50 --- /dev/null +++ b/include/configs/apalis-imx8x.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + */ + +#ifndef __APALIS_IMX8X_H +#define __APALIS_IMX8X_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include <linux/stringify.h> + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define FEC_ENET_ENABLE_TXC_DELAY +#define FEC_ENET_ENABLE_RXC_DELAY + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=0x80280000\0" \ + "fdt_addr_r=0x83100000\0" \ + "ramdisk_addr_r=0x8a000000\0" \ + "scriptaddr=0x83200000\0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define MFG_NAND_PARTITION "" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs ${consoleargs} " \ + "rdinit=/linuxrc g_mass_storage.stall=0 " \ + "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ + "g_mass_storage.idProduct=0x37FF " \ + "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ + "${vidargs} clk_ignore_unused\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ + "${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + BOOTENV \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_file=Image\0" \ + "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ + "fdt_file=imx8qxp-apalis-eval.dtb\0" \ + "fdtfile=imx8qxp-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "mmcargs=setenv bootargs ${consoleargs} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs ${consoleargs} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "${vidargs}\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \ + "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" \ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x89000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE 0x5b040000 +#define CONFIG_FEC_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME "eth0" +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define PHY_ANEG_TIMEOUT 20000 + +#endif /* __APALIS_IMX8X_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index bf0aefda2ad..f0c003d2fe0 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -12,7 +12,14 @@ #include "tegra30-common.h" -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 6e8595caad8..78fa1a969e7 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -13,14 +13,18 @@ #define CONFIG_HOSTNAME "aristainetos2" +#if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" +#endif #define CONFIG_FEC_XCV_TYPE RGMII /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 28341000 -#define CONFIG_LG4573 #include "mx6_common.h" @@ -77,6 +81,8 @@ "enable_hab_check=1\0" #else #define HAB_EXTRA_SETTINGS \ + "hab_check_addr=echo HAB check addr always returns " \ + "true;true\0" \ "hab_check_file_fit=echo HAB check FIT file always returns " \ "true;true\0" \ "hab_check_flash_fit=echo HAB check flash FIT always returns " \ @@ -86,96 +92,18 @@ "enable_hab_check=0\0" #endif -#if (CONFIG_SYS_BOARD_VERSION == 3) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" -#elif (CONFIG_SYS_BOARD_VERSION == 4) +#if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on;led led_red2 on;\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" -#elif (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "emmcpart=1\0" \ - "emmc_rescue_part=3\0" \ - "emmcdev=1\0" \ - "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ - "dead=led led_red on\0" \ - "mtdids=nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart} " \ - "emmcpart=${emmcpart}\0" \ - "mainboot=echo Booting from eMMC ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${emmcroot} rootfstype=ext4\0 " \ - "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ - "${fit_file}; " \ - "imi ${fit_addr_r}\0 " \ - "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \ - "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0" -#else + "dead=while true; do; " \ + "led led_red on; sleep 1;" \ + "led led_red off; sleep 1;" \ + "done\0" +#elif (CONFIG_SYS_BOARD_VERSION == 6) #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ - "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" + "dead=while true; do; " \ + "led led_red on; led led_red2 on; sleep 1;" \ + "led led_red off; led led_red2 off;; sleep 1;" \ + "done\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -183,17 +111,24 @@ "usb_pgood_delay=2000\0" \ "nor_bootdelay=-2\0" \ "script=u-boot.scr\0" \ - "fit_file=/boot/system.itb\0" \ - "rescue_fit_file=/boot/rescue.itb\0" \ "loadaddr=0x12000000\0" \ "fit_addr_r=0x14000000\0" \ - "uboot=/boot/u-boot.imx\0" \ "uboot_sz=d0000\0" \ "panel=lb07wv8\0" \ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "mtdids=nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor)\0" \ + "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ + "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ + "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ + "mk_pubkey_path=setenv pubkey /${sysnum}/PCR.pem\0" \ + "mk_rescue_pubkey_path=setenv pubkey /${rescue_sysnum}/PCR.pem\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} rng_core.default_quality=1000 " \ + "mmcpart=${mmcpart} emmcpart=${emmcpart} sysnum=${sysnum}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \ "get_env=mw ${loadaddr} 0 0x20000;" \ @@ -205,7 +140,7 @@ "sf protect unlock 0 0x1000000;" \ "mw ${loadaddr} 0 0x20000;" \ "env export -t ${loadaddr} serial# ethaddr " \ - "board_type panel addmisc addmiscM addmiscC addmiscD;" \ + "board_type panel;" \ "env default -a;" \ "env import -t ${loadaddr}\0" \ "loadbootscript=" \ @@ -216,28 +151,62 @@ "loadbootscriptUSBf=" \ "fatload usb 0 ${loadaddr} ${script};\0" \ "bootscriptUSB=echo Running bootscript from usb-stick ...; " \ - "source\0" \ + "source \0" \ "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ + "source \0" \ "mmcpart=1\0" \ - "mmcrescuepart=3\0" \ "mmcdev=0\0" \ + "emmcpart=1\0" \ + "emmcdev=1\0" \ + "sysnum=1\0" \ + "rescue_sysnum=0\0" \ + "rreason=18\0" \ + "mainboot=echo Booting from eMMC ...; " \ + "run mainargs addmtd addmisc;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${emmcroot} rootfstype=ext4\0 " \ + "main_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${fit_file}; " \ + "imi ${fit_addr_r}\0 " \ + "rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${rescue_fit_file}; " \ + "imi ${fit_addr_r}\0" \ + "main_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mainRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ + "mmcRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${mmcroot}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "mmc_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ "${fit_file}\0" \ - "mmc_load_uboot=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${uboot}\0" \ - "mmc_rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "imi ${fit_addr_r}\0" \ + "mmc_rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} " \ "${fit_addr_r} ${rescue_fit_file}\0" \ + "imi ${fit_addr_r}\0" \ + "mmc_load_uboot=run mk_uboot_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ "setexpr uboot_maxsize ${uboot_sz} - 400;" \ @@ -246,14 +215,19 @@ "sf write ${loadaddr} 400 ${filesize};" \ "sf read ${cmp_buf} 400 ${uboot_sz};" \ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "rescueargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/ram rw\0 " \ + "mmc_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mmc_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ "rescueboot=echo Booting rescue system ...; " \ - "run rescueargs addmtd addmisc;" \ + "run addmtd addmisc;" \ "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "if bootm ${fit_addr_r}; then ; " \ "else " \ @@ -261,50 +235,73 @@ "fi; \0" \ "r_reason_syserr=setenv rescue_reason setenv bootargs " \ "\\\\${bootargs} " \ - "rescueReason=18\0 " \ - "usb_load_fit=ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ - "usb_load_fitf=fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ - "usb_load_rescuefit=ext4load usb 0 ${fit_addr_r} " \ + "rescueReason=$rreason\0 " \ + "usb_load_fit=run mk_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_fitf=run mk_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_rescuefit=run mk_rescue_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} " \ "${rescue_fit_file}\0" \ - "usb_load_rescuefitf=fatload usb 0 ${fit_addr_r} " \ + "usb_load_rescuefitf=run mk_rescue_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} " \ "${rescue_fit_file}\0" \ + "usb_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_load_pubkeyf=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkeyf=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ "usbroot=/dev/sda1 rootwait rw\0" \ "usbboot=echo Booting from usb-stick ...; " \ "run usbargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ "usbargs=setenv bootargs console=${console},${baudrate} " \ "root=${usbroot}\0" \ + "usbRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${usbroot} rw\0 " \ "mmc_rescue_boot=" \ "run r_reason_syserr;" \ - "if run mmc_rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run mmc_rescue_load_pubkey hab_check_addr " \ + "mmc_rescue_load_fit hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \ + "run dead; " \ "fi;\0" \ "main_rescue_boot=" \ - "if run main_load_fit hab_check_flash_fit; then " \ + "if run main_load_pubkey hab_check_addr " \ + "main_load_fit hab_check_flash_fit; then " \ "if run mainboot; then ; " \ "else " \ "run r_reason_syserr;" \ - "if run rescue_load_fit hab_check_file_fit;" \ - "then run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi; " \ "else " \ "run r_reason_syserr;" \ - "if run rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi;\0" \ "usb_mmc_rescue_boot=" \ @@ -318,17 +315,21 @@ "hab_check_file_bootscript;" \ "then run bootscriptUSB; " \ "fi; " \ - "if run usb_load_fit hab_check_file_fit; then " \ + "if run usb_load_pubkey hab_check_addr " \ + "usb_load_fit hab_check_file_fit; then " \ "run usbboot; " \ "fi; " \ - "if run usb_load_fitf hab_check_file_fit; then " \ + "if run usb_load_pubkeyf hab_check_addr " \ + "usb_load_fitf hab_check_file_fit; then " \ "run usbboot; " \ "fi; "\ - "if run usb_load_rescuefit hab_check_file_fit;" \ - "then run r_reason_syserr rescueboot;" \ + "if run usb_rescue_load_pubkey hab_check_addr " \ + "usb_load_rescuefit hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf hab_check_file_fit;" \ - "then run r_reason_syserr rescueboot;" \ + "if run usb_rescue_load_pubkeyf hab_check_addr " \ + "usb_load_rescuefitf hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ "fi; " \ "run mmc_rescue_boot;" \ "fi; "\ @@ -338,48 +339,57 @@ "if test ${bootmode} -ne 0 ; then " \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ - "if run mmc_rescue_load_fit " \ - "hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run mmc_rescue_load_pubkey " \ + "hab_check_addr " \ + "mmc_rescue_load_fit " \ + "hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ "else " \ "usb start;" \ "if usb storage; then " \ - "if run usb_load_rescuefit " \ - "hab_check_file_fit;"\ - "then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf "\ - "hab_check_file_fit;"\ - "then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ "fi;" \ "fi;" \ - "run dead; " \ "echo RESCUE SYSTEM ON SD OR " \ "USB BOOT FAILURE;" \ + "run dead; " \ "else " \ "usb start;" \ "if usb storage; then " \ - "if run usb_load_rescuefit " \ - "hab_check_file_fit; then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf " \ - "hab_check_file_fit; then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ "fi;" \ - "run dead; " \ "echo RESCUE SYSTEM ON USB BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "else "\ - "if run rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi;\0" \ "ari_boot=if test ${bootmode} -ne 0 ; then " \ @@ -388,7 +398,8 @@ "if run loadbootscript hab_check_file_bootscript;" \ "then run bootscript; " \ "fi; " \ - "if run mmc_load_fit hab_check_file_fit; then " \ + "if run mmc_load_pubkey hab_check_addr " \ + "mmc_load_fit hab_check_file_fit; then " \ "if run mmcboot; then ; " \ "else " \ "run mmc_rescue_boot;" \ @@ -421,12 +432,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ @@ -444,4 +449,7 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ + "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" + #endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index dd3bdacc2c4..2c406d31866 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -28,8 +28,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 2ef6bfdba86..bdd5973cb71 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -35,7 +35,6 @@ #define CONFIG_SPI_FLASH_SST /* Thermal support */ -#define CONFIG_IMX_THERMAL /* I2C Configs */ #define CONFIG_SYS_I2C diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 07f1893d115..0ef55b77133 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -141,9 +141,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -/* Uncomment to enable iMX thermal driver support */ -/*#define CONFIG_IMX_THERMAL*/ - /* SPL */ #include "imx7_spl.h" diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index d373fda0168..2827c171c97 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -140,8 +140,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS /* USB Device Firmware Update support */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index b3601abe2cb..85dd8910553 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -208,8 +208,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS #if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index fa0fa93b030..94802a66f7a 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -14,7 +14,13 @@ /* High-level configuration options */ -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b27f7157983..4eb50f841e6 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -84,8 +84,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bd61f20a7a6..9ee7fee2d72 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -14,8 +14,6 @@ #include "mx6_common.h" -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index b18db76d2f1..ff3a849a144 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,8 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index b513b4bc68a..ca249d9d2b5 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -62,7 +62,6 @@ /* JFFS2 */ #ifdef CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_NAND #endif diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 4fdc2b65962..e5c580b3f91 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -48,7 +48,7 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_NFS_CMD +#ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ @@ -56,7 +56,7 @@ "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ - "setenv bootargs $bootargs cma=128M bootcause=POR ${videoargs} " \ + "setenv bootargs $bootargs cma=128M bootcause=${bootcause} ${videoargs} " \ "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ "networkboot=" \ @@ -74,7 +74,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ NETWORKBOOT \ - "bootcause=POR\0" \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ "devnum=2\0" \ @@ -104,7 +103,6 @@ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run hasfirstboot || setenv partnum 0; " \ "if test ${partnum} != 0; then " \ - "setenv bootcause REVERT; " \ "run swappartitions loadimage doboot; " \ "fi; " \ "run failbootcmd\0" \ @@ -130,7 +128,7 @@ #define CONFIG_USBBOOTCOMMAND \ "echo Unsupported; " \ -#ifdef CONFIG_NFS_CMD +#ifdef CONFIG_CMD_NFS #define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND #elif CONFIG_CMD_USB #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a92157d52cb..7c8abda1d26 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -32,16 +32,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -/* Init Functions */ - -/* Driver Model */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_THERMAL -#endif - -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index c1968048a7d..ad0041d8a94 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -32,9 +32,6 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -/* UBI Support for all Keymile boards */ -#define CONFIG_MTD_CONCAT - #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ "actual_bank=0\0" @@ -90,12 +87,12 @@ "set_fdthigh cramfsloadkernel flashargs add_default " \ "addpanic boot\0" \ "develop=" \ - "tftp 200000 scripts/develop-${arch}.txt && " \ - "env import -t 200000 ${filesize} && " \ + "tftp ${load_addr_r} scripts/develop-${arch}.txt && " \ + "env import -t ${load_addr_r} ${filesize} && " \ "run setup_debug_env\0" \ "ramfs=" \ - "tftp 200000 scripts/ramfs-${arch}.txt && " \ - "env import -t 200000 ${filesize} && " \ + "tftp ${load_addr_r} scripts/ramfs-${arch}.txt && " \ + "env import -t ${load_addr_r} ${filesize} && " \ "run setup_debug_env\0" \ "" diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 7bfe12fecbb..3be926c1031 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -9,8 +9,6 @@ /* Do boardspecific init for all boards */ -#define CONFIG_JFFS2_CMDLINE - /* EEprom support 24C08, 24C16, 24C64 */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 4d01f236c31..cdfb280aeee 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -51,7 +51,7 @@ /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ -#define CPM_POST_WORD_ADDR 0x00f00000 +#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index ec1254e747b..d1eb7b574b4 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -337,9 +337,6 @@ int get_scl(void); * additionnal command line configuration. */ -/* we don't need flash support */ -#undef CONFIG_JFFS2_CMDLINE - /* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index db5e6fc133b..5adbe1ca391 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -141,6 +141,4 @@ #define CONFIG_ETHPRIME "FEC" #endif -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index df2a613eaf3..c4c9b7f5019 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -102,5 +102,67 @@ #define CONFIG_PCI_SCAN_SHOW +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#endif + #include <asm/fsl_secure_boot.h> #endif /* __LS1012AQDS_H__ */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 96fdd6417ed..6584e391993 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -247,12 +247,12 @@ "kernelheader_start=0x800000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x60800000\0" \ + "kernelheader_addr=0x60600000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0017ac57734..4bd0ddbdad2 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -149,8 +149,10 @@ /* USB */ #ifdef CONFIG_USB #define CONFIG_HAS_FSL_XHCI_USB +#ifndef CONFIG_TARGET_LX2162AQDS #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#endif /* FlexSPI */ #ifdef CONFIG_NXP_FSPI @@ -230,7 +232,7 @@ unsigned long get_board_ddr_clk(void); "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ - "kernel_size_sd=0x1d000\0" \ + "kernel_size_sd=0x14000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyAMA0,38400n8\0" \ BOOTENV \ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 1cc015c1c77..ea1b1635fe9 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -8,70 +8,14 @@ #include "lx2160a_common.h" -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 - -/* SYSCLK */ -#define QIXIS_SYSCLK_100 0x0 -#define QIXIS_SYSCLK_125 0x1 -#define QIXIS_SYSCLK_133 0x2 - -/* DDRCLK */ -#define QIXIS_DDRCLK_100 0x0 -#define QIXIS_DDRCLK_125 0x1 -#define QIXIS_DDRCLK_133 0x2 - -#define BRDCFG4_EMI1SEL_MASK 0xF8 -#define BRDCFG4_EMI1SEL_SHIFT 3 -#define BRDCFG4_EMI2SEL_MASK 0x07 -#define BRDCFG4_EMI2SEL_SHIFT 0 - /* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv" #define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 925 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -#define I2C_MUX_CH_RTC 0xB /* * MMC @@ -87,26 +31,6 @@ u8 qixis_esdhc_detect_quirk(void); #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC17@rgmii-id" - -#define AQ_PHY_ADDR1 0x00 -#define AQ_PHY_ADDR2 0x01 -#define AQ_PHY_ADDR3 0x02 -#define AQ_PHY_ADDR4 0x03 - -#define CORTINA_NO_FW_UPLOAD -#define CORTINA_PHY_ADDR1 0x0 - -#define INPHI_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR2 0x1 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - #endif /* EEPROM */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index a51987e6b09..097f1224c90 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -8,47 +8,9 @@ #include "lx2160a_common.h" -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG - /* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" #define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 855 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ @@ -59,18 +21,6 @@ #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC1@xgmii" - -#define AQR107_PHY_ADDR1 0x04 -#define AQR107_PHY_ADDR2 0x05 -#define AQR107_IRQ_MASK 0x0C - -#define CORTINA_NO_FW_UPLOAD -#define CORTINA_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR1 0x0 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - #endif /* EMC2305 */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h new file mode 100644 index 00000000000..847534c5505 --- /dev/null +++ b/include/configs/lx2162aqds.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2162_QDS_H +#define __LX2162_QDS_H + +#include "lx2160a_common.h" + +/* USB */ +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +/* Voltage monitor on channel 2*/ +#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv" +#define CONFIG_VID +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#ifndef __ASSEMBLY__ +u8 qixis_esdhc_detect_quirk(void); +#endif +#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() +#endif + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS \ + "boot_scripts=lx2162aqds_boot.scr\0" \ + "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \ + "BOARD=lx2162aqds\0" \ + "xspi_bootcmd=echo Trying load from flexspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "emmc_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LX2162_QDS_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 2b412423508..bc0bf049737 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -8,24 +8,14 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include "../board/xilinx/microblaze-generic/xparameters.h" +/* Microblaze is microblaze_0 */ +#define XILINX_FSL_NUMBER 3 /* MicroBlaze CPU */ #define MICROBLAZE_V5 1 #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) -/* linear and spi flash memory */ -#ifdef XILINX_FLASH_START -#define FLASH -#undef SPIFLASH -#undef RAMENV /* hold environment in flash */ -#else -#undef FLASH -#undef SPIFLASH -#define RAMENV /* hold environment in RAM */ -#endif - /* uart */ /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ @@ -40,67 +30,17 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_F_LEN) -/* - * CFI flash memory layout - Example - * CONFIG_SYS_FLASH_BASE = 0x2200_0000; - * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB - * - * SECT_SIZE = 0x20000; 128kB is one sector - * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store - * - * 0x2200_0000 CONFIG_SYS_FLASH_BASE - * FREE 256kB - * 0x2204_0000 CONFIG_ENV_ADDR - * ENV_AREA 128kB - * 0x2206_0000 - * FREE - * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - * - */ - -#ifdef FLASH -# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START -# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE +#ifdef CONFIG_CFI_FLASH /* ?empty sector */ # define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* max number of memory banks */ # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 512 -/* hardware flash protection */ -/* use buffered writes (20x faster) */ -# ifdef RAMENV -# else /* FLASH && !RAMENV */ -/* 128K(one sector) for env */ -# endif /* FLASH && !RAMBOOT */ -#else /* !FLASH */ - -#ifdef SPIFLASH -# ifdef RAMENV -# else /* SPIFLASH && !RAMENV */ -/* 128K(two sectors) for env */ -/* Warning: adjust the offset in respect of other flash content and size */ -# endif /* SPIFLASH && !RAMBOOT */ -#else /* !SPIFLASH */ - -/* ENV in RAM */ -#endif /* !SPIFLASH */ -#endif /* !FLASH */ - -#define XILINX_USE_ICACHE 1 -#define XILINX_USE_DCACHE 1 - -#if defined(XILINX_USE_ICACHE) -# define CONFIG_ICACHE -#else -# undef CONFIG_ICACHE +# define CONFIG_SYS_MAX_FLASH_SECT 2048 #endif -#if defined(XILINX_USE_DCACHE) -# define CONFIG_DCACHE -#else -# undef CONFIG_DCACHE -#endif +#define CONFIG_ICACHE +#define CONFIG_DCACHE #ifndef XILINX_DCACHE_BYTE_SIZE #define XILINX_DCACHE_BYTE_SIZE 32768 @@ -111,12 +51,6 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -#if defined(CONFIG_MTD_PARTITIONS) -/* MTD partitions */ - -/* default mtd partition table */ -#endif - /* size of console buffer */ #define CONFIG_SYS_CBSIZE 512 /* max number of command args */ @@ -194,15 +128,12 @@ /* SPL part */ -#ifdef CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE -#endif +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE /* for booting directly linux */ +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_TEXT_BASE + \ + 0x40000) -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x40000) -#define CONFIG_SYS_FDT_SIZE (16 << 10) #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ 0x1000000) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index cfab9a7fc02..55717c77ab3 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -13,8 +13,6 @@ #include "imx6_spl.h" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) /* MMC Configs */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c4e34e9cbc7..93d00a4dc3c 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 44dadd681c0..ab32f4e151e 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -132,6 +132,4 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IMX_THERMAL - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 9533d307428..a38ce4d0977 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -123,8 +123,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IMX_THERMAL - #define CONFIG_IOMUX_LPSR /* USB Configs */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 9ad29341c14..58cc3f0ee2b 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -138,8 +138,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 42feb140197..036881f6ea3 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -170,8 +170,6 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#define CONFIG_IMX_THERMAL - #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_MXS diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index fa6b303dd4a..7d36c1e4d90 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -177,8 +177,6 @@ #endif #endif -#define CONFIG_IMX_THERMAL - #ifndef CONFIG_SPL_BUILD #if defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_MXS diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index ca2f2bd975d..23f6de9050c 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -150,8 +150,6 @@ /* environment organization */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_IMX_THERMAL - #define CONFIG_IOMUX_LPSR #define CONFIG_SOFT_SPI diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 51a7a5f4a0e..5801da0cfac 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -134,8 +134,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS #ifdef CONFIG_VIDEO diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 208779958f5..5ef16fb278e 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -50,8 +50,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index c86c4294137..6879f52a0c9 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -75,14 +75,6 @@ #define CONFIG_USBD_MANUFACTURER "Nokia" #define CONFIG_USBD_PRODUCT_NAME "N900" -/* commands to include */ - -#define CONFIG_SYS_I2C - -/* - * TWL4030 - */ - #define GPIO_SLIDE 71 /* @@ -231,10 +223,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "run attachboot;" \ "echo" -/* - * Miscellaneous configurable options - */ - /* default load address */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index bf8f7b1e1b7..ea61f92bdbb 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -74,9 +74,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif -/* Thermal support */ -#define CONFIG_IMX_THERMAL - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 2156da671b2..4f4d50131f5 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -62,8 +62,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index d7c6f8808e0..6009521c9f7 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -69,8 +69,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index 3227c4276e1..e96429083ed 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -13,9 +13,6 @@ #include "mx6_common.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 51b7359cad9..80de1158ad1 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -168,6 +168,4 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0ed4b1aaa27..6c882b6ff94 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -190,7 +190,6 @@ #endif -#define CONFIG_JFFS2_CMDLINE 1 #define CONFIG_JFFS2_NAND 1 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h index 511b1a440e8..7052d8049e4 100644 --- a/include/configs/sksimx6.h +++ b/include/configs/sksimx6.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 204818b8eb7..945d0ecc737 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -104,6 +104,4 @@ #define CONFIG_ETHPRIME "eth0" #endif -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 169b9efeec8..33b34ee0cd3 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 8390535af0a..fefdb2dd152 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 57fb6b25afd..ba9f05a61b4 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index afc98ae791b..6e10dbdfe94 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 66af8f50d90..268d39c7ad6 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index d9a2f75e738..da162cbb114 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 /* spi not partitions */ -#define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nor0" /* Timer */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 01c1143e43c..a2e59ce6185 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_IMX_THERMAL - /* Physical Memory Map */ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2b968917d34..432eceaf351 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -49,6 +49,12 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#ifdef CONFIG_ARM64 +#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index d3a70456976..9d751b67404 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -50,6 +50,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 522993b958a..0eb8f928091 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -52,6 +52,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index b4936cc731f..d5f21e09072 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -20,6 +20,12 @@ /* Generic Interrupt Controller */ #define CONFIG_GICV2 +#undef FDTFILE +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ + "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ + "fi; " + /* * Memory layout for where various images get loaded by boot scripts: * diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 1e31d82574a..fdd89969554 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -51,6 +51,7 @@ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x03000000\0" \ "ramdisk_addr_r=0x03100000\0" diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1b8e94b60cc..2226effe16a 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,6 +46,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83200000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 54bc6756abe..6c5dc24b266 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -47,6 +47,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 34a95a0283f..4935a2b363e 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -70,10 +70,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Environment organization */ - -#define CONFIG_IMX_THERMAL - /* I2C configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a851fb41a81..f97431f1354 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -73,8 +73,6 @@ #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif -#define CONFIG_IMX_THERMAL - #define CONFIG_IMX6_PWM_PER_CLK 66000000 #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 2d1ede3bc8d..8eb10602744 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -146,8 +146,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS /* USB Device Firmware Update support */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 399925a75bd..e7a26589d67 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -63,8 +63,6 @@ #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "FEC" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_UBOOT_SECTOR_START 0x2 diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index d66432c6e67..318eb15c414 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -43,8 +43,10 @@ #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ #define _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define CLK_PLL_VIDEO0 7 #define CLK_PLL_PERIPH0 11 +#define CLK_CPUX 21 #define CLK_BUS_MIPI_DSI 28 #define CLK_BUS_CE 29 #define CLK_BUS_DMA 30 @@ -129,7 +131,7 @@ #define CLK_AVS 109 #define CLK_HDMI 110 #define CLK_HDMI_DDC 111 - +#define CLK_MBUS 112 #define CLK_DSI_DPHY 113 #define CLK_GPU 114 diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h index 3bed63b524a..7768f73b051 100644 --- a/include/dt-bindings/clock/sun8i-de2.h +++ b/include/dt-bindings/clock/sun8i-de2.h @@ -15,4 +15,7 @@ #define CLK_MIXER1 7 #define CLK_WB 8 +#define CLK_BUS_ROT 9 +#define CLK_ROT 10 + #endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f0c3aaef67a..702da37a2e8 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ #define _DT_BINDINGS_STM32MP1_RESET_H_ +#define MCU_HOLD_BOOT_R 2144 #define LTDC_R 3072 #define DSI_R 3076 #define DDRPERFM_R 3080 diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h index 9526017432f..1c36a6ac86d 100644 --- a/include/dt-bindings/reset/sun8i-de2.h +++ b/include/dt-bindings/reset/sun8i-de2.h @@ -10,5 +10,6 @@ #define RST_MIXER0 0 #define RST_MIXER1 1 #define RST_WB 2 +#define RST_ROT 3 #endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h index 3989a9bb536..546ffbaf7b4 100644 --- a/include/dwc3-sti-glue.h +++ b/include/dwc3-sti-glue.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __DWC3_STI_UBOOT_H_ diff --git a/include/efi_loader.h b/include/efi_loader.h index f550ced5687..3c68b85b68e 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -59,6 +59,9 @@ extern efi_handle_t efi_root; /* Set to EFI_SUCCESS when initialized */ extern efi_status_t efi_obj_list_initialized; +/* Flag used by the selftest to avoid detaching devices in ExitBootServices() */ +extern bool efi_st_keep_devices; + /* EFI system partition */ extern struct efi_system_partition { enum if_type if_type; @@ -405,6 +408,8 @@ efi_status_t efi_console_register(void); efi_status_t efi_disk_register(void); /* Called by efi_init_obj_list() to install EFI_RNG_PROTOCOL */ efi_status_t efi_rng_register(void); +/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */ +efi_status_t efi_tcg2_register(void); /* Create handles and protocols for the partitions of a block device */ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, const char *if_typename, int diskid, diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h new file mode 100644 index 00000000000..86b8fe4c01a --- /dev/null +++ b/include/efi_tcg2.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Defines data structures and APIs that allow an OS to interact with UEFI + * firmware to query information about the device + * + * Copyright (c) 2020, Linaro Limited + */ + +#if !defined _EFI_TCG2_PROTOCOL_H_ +#define _EFI_TCG2_PROTOCOL_H_ + +#include <tpm-v2.h> + +#define EFI_TCG2_PROTOCOL_GUID \ + EFI_GUID(0x607f766c, 0x7455, 0x42be, 0x93, \ + 0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f) + +/* TPMV2 only */ +#define TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002 + +/* Algorithm Registry */ +#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001 +#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002 +#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004 +#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008 +#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 + +typedef u32 efi_tcg_event_log_bitmap; +typedef u32 efi_tcg_event_log_format; +typedef u32 efi_tcg_event_algorithm_bitmap; + +struct efi_tcg2_version { + u8 major; + u8 minor; +}; + +struct efi_tcg2_event_header { + u32 header_size; + u16 header_version; + u32 pcr_index; + u32 event_type; +} __packed; + +struct efi_tcg2_event { + u32 size; + struct efi_tcg2_event_header header; + u8 event[]; +} __packed; + +struct efi_tcg2_boot_service_capability { + u8 size; + struct efi_tcg2_version structure_version; + struct efi_tcg2_version protocol_version; + efi_tcg_event_algorithm_bitmap hash_algorithm_bitmap; + efi_tcg_event_log_bitmap supported_event_logs; + u8 tpm_present_flag; + u16 max_command_size; + u16 max_response_size; + u32 manufacturer_id; + u32 number_of_pcr_banks; + efi_tcg_event_algorithm_bitmap active_pcr_banks; +}; + +#define boot_service_capability_min \ + sizeof(struct efi_tcg2_boot_service_capability) - \ + offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks) + +struct efi_tcg2_protocol { + efi_status_t (EFIAPI * get_capability)(struct efi_tcg2_protocol *this, + struct efi_tcg2_boot_service_capability *capability); + efi_status_t (EFIAPI * get_eventlog)(struct efi_tcg2_protocol *this, + efi_tcg_event_log_format log_format, + u64 *event_log_location, u64 *event_log_last_entry, + bool *event_log_truncated); + efi_status_t (EFIAPI * hash_log_extend_event)(struct efi_tcg2_protocol *this, + u64 flags, u64 data_to_hash, + u64 data_to_hash_len, + struct efi_tcg2_event *efi_tcg_event); + efi_status_t (EFIAPI * submit_command)(struct efi_tcg2_protocol *this, + u32 input_parameter_block_size, + u8 *input_parameter_block, + u32 output_parameter_block_size, + u8 *output_parameter_block); + efi_status_t (EFIAPI * get_active_pcr_banks)(struct efi_tcg2_protocol *this, + u32 *active_pcr_banks); + efi_status_t (EFIAPI * set_active_pcr_banks)(struct efi_tcg2_protocol *this, + u32 active_pcr_banks); + efi_status_t (EFIAPI * get_result_of_set_active_pcr_banks)(struct efi_tcg2_protocol *this, + u32 *operation_present, + u32 *response); +}; +#endif diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index e6f1c75e27c..850a304bd7d 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -187,8 +187,12 @@ /* DLL config 0 register */ #define DLL_ENABLE 0x80000000 +#define DLL_RESET 0x40000000 #define DLL_FREQ_SEL 0x08000000 +/* DLL status 0 register */ +#define DLL_STS_SLV_LOCK 0x08000000 + #define MAX_TUNING_LOOP 40 #define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index fd915335b2c..e1e6214b0f7 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -52,6 +52,8 @@ /* Machine Select */ #define CSPR_MSEL 0x00000006 #define CSPR_MSEL_SHIFT 1 +/* External Transceiver Enable */ +#define CSPR_TE 0x00000010 /* NOR */ #define CSPR_MSEL_NOR 0x00000000 /* NAND */ diff --git a/include/linux/compat.h b/include/linux/compat.h index 38549baa251..3d0acbd582e 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -248,7 +248,7 @@ typedef int wait_queue_head_t; #define spin_lock_init(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0) +#define spin_lock_irqsave(lock, flags) do {} while (0) #define spin_unlock_irqrestore(lock, flags) do { flags = 0; } while (0) #define DEFINE_MUTEX(...) diff --git a/include/log.h b/include/log.h index 29f18a82dcf..6bce5606489 100644 --- a/include/log.h +++ b/include/log.h @@ -29,7 +29,7 @@ enum log_level_t { LOGL_CRIT, /** @LOGL_ERR: Error that prevents something from working */ LOGL_ERR, - /** @LOGL_WARNING: Warning may prevent optimial operation */ + /** @LOGL_WARNING: Warning may prevent optimal operation */ LOGL_WARNING, /** @LOGL_NOTICE: Normal but significant condition, printf() */ LOGL_NOTICE, @@ -96,8 +96,8 @@ enum log_category_t { LOGC_DEVRES, /** @LOGC_ACPI: Advanced Configuration and Power Interface (ACPI) */ LOGC_ACPI, - LOGC_BOOT, /* Related to boot process / boot image processing */ - + /** @LOGC_BOOT: Related to boot process / boot image processing */ + LOGC_BOOT, /** @LOGC_COUNT: Number of log categories */ LOGC_COUNT, /** @LOGC_END: Sentinel value for lists of log categories */ @@ -322,7 +322,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, * * Members marked as 'not allocated' are stored as pointers and the caller is * responsible for making sure that the data pointed to is not overwritten. - * Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log + * Members marked as 'allocated' are allocated (e.g. via strdup()) by the log * system. * * TODO(sjg@chromium.org): Compress this struct down a bit to reduce space, e.g. @@ -379,7 +379,7 @@ struct log_driver { * the run-time aspects of drivers (currently just a list of filters to apply * to records send to this device). * - * @next_filter_num: Seqence number of next filter filter added (0=no filters + * @next_filter_num: Sequence number of next filter filter added (0=no filters * yet). This increments with each new filter on the device, but never * decrements * @flags: Flags for this filter (enum log_device_flags) @@ -412,7 +412,7 @@ enum log_filter_flags { }; /** - * struct log_filter - criterial to filter out log messages + * struct log_filter - criteria to filter out log messages * * If a message matches all criteria, then it is allowed. If LOGFF_DENY is set, * then it is denied instead. diff --git a/include/mm_communication.h b/include/mm_communication.h index e464cbb48e2..e65fbde60d0 100644 --- a/include/mm_communication.h +++ b/include/mm_communication.h @@ -43,7 +43,7 @@ * To avoid confusion in interpreting frames, the communication buffer should * always begin with efi_mm_communicate_header. */ -struct efi_mm_communicate_header { +struct __packed efi_mm_communicate_header { efi_guid_t header_guid; size_t message_len; u8 data[]; diff --git a/include/squashfs.h b/include/squashfs.h index 819cf8c2da8..7489eefa1f2 100644 --- a/include/squashfs.h +++ b/include/squashfs.h @@ -19,6 +19,7 @@ int sqfs_probe(struct blk_desc *fs_dev_desc, int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, loff_t *actread); int sqfs_size(const char *filename, loff_t *size); +int sqfs_exists(const char *filename); void sqfs_close(void); void sqfs_closedir(struct fs_dir_stream *dirs); diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index a09a09ff955..b559ea77281 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #ifndef __STM32_RCC_H_ diff --git a/include/tpm-v2.h b/include/tpm-v2.h index f6c045d3548..74c14fe7c51 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -1,6 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Defines APIs and structures that allow software to interact with a + * TPM2 device + * + * Copyright (c) 2020 Linaro * Copyright (c) 2018 Bootlin + * + * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/ + * * Author: Miquel Raynal <miquel.raynal@bootlin.com> */ @@ -11,6 +18,74 @@ #define TPM2_DIGEST_LEN 32 +#define TPM2_MAX_PCRS 32 +#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8) +#define TPM2_MAX_CAP_BUFFER 1024 +#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \ + sizeof(u32)) / sizeof(struct tpms_tagged_property)) + +/* + * We deviate from this draft of the specification by increasing the value of + * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2 + * implementations that have enabled a larger than typical number of PCR + * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included + * in a future revision of the specification. + */ +#define TPM2_NUM_PCR_BANKS 16 + +/* Definition of (UINT32) TPM2_CAP Constants */ +#define TPM2_CAP_PCRS 0x00000005U +#define TPM2_CAP_TPM_PROPERTIES 0x00000006U + +/* Definition of (UINT32) TPM2_PT Constants */ +#define TPM2_PT_GROUP (u32)(0x00000100) +#define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1) +#define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5) +#define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18) +#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30) +#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31) + +/* TPMS_TAGGED_PROPERTY Structure */ +struct tpms_tagged_property { + u32 property; + u32 value; +} __packed; + +/* TPMS_PCR_SELECTION Structure */ +struct tpms_pcr_selection { + u16 hash; + u8 size_of_select; + u8 pcr_select[TPM2_PCR_SELECT_MAX]; +} __packed; + +/* TPML_PCR_SELECTION Structure */ +struct tpml_pcr_selection { + u32 count; + struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS]; +} __packed; + +/* TPML_TAGGED_TPM_PROPERTY Structure */ +struct tpml_tagged_tpm_property { + u32 count; + struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES]; +} __packed; + +/* TPMU_CAPABILITIES Union */ +union tpmu_capabilities { + /* + * Non exhaustive. Only added the structs needed for our + * current code + */ + struct tpml_pcr_selection assigned_pcr; + struct tpml_tagged_tpm_property tpm_properties; +} __packed; + +/* TPMS_CAPABILITY_DATA Structure */ +struct tpms_capability_data { + u32 capability; + union tpmu_capabilities data; +} __packed; + /** * TPM2 Structure Tags for command/response buffers. * @@ -123,11 +198,13 @@ enum tpm2_return_codes { * TPM2 algorithms. */ enum tpm2_algorithms { + TPM2_ALG_SHA1 = 0x04, TPM2_ALG_XOR = 0x0A, TPM2_ALG_SHA256 = 0x0B, TPM2_ALG_SHA384 = 0x0C, TPM2_ALG_SHA512 = 0x0D, TPM2_ALG_NULL = 0x10, + TPM2_ALG_SM3_256 = 0x12, }; /* NV index attributes */ diff --git a/include/twl4030.h b/include/twl4030.h index c27ad615eeb..ef05193996a 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -654,14 +654,20 @@ static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return i2c_write(chip_no, reg, 1, &val, 1); } -static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +static inline int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len) { - return i2c_read(chip_no, reg, 1, val, 1); + return i2c_read(chip_no, reg, 1, val, len); } #else int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val); -int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); +int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len); #endif + +static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return twl4030_i2c_read(chip_no, reg, val, 1); +} + /* * Power */ diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index a2af381a667..aa37e957b47 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -28,6 +28,7 @@ struct dwc2_plat_otg_data { unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS]; unsigned char tx_fifo_sz_nb; bool force_b_session_valid; + bool force_vbus_detection; bool activate_stm_id_vb_detection; }; diff --git a/lib/binman.c b/lib/binman.c index d395b1cf70b..f027d1b3042 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -104,6 +104,6 @@ int binman_init(void) binman->image = node; } binman_set_rom_offset(ROM_OFFSET_NONE); -\ + return 0; } diff --git a/lib/charset.c b/lib/charset.c index 5686d6fb59c..2177014ee1c 100644 --- a/lib/charset.c +++ b/lib/charset.c @@ -8,6 +8,7 @@ #include <common.h> #include <charset.h> #include <capitalization.h> +#include <efi_loader.h> #include <malloc.h> static struct capitalization_table capitalization_table[] = @@ -372,7 +373,7 @@ size_t u16_strlen(const void *in) return ret; } -size_t u16_strnlen(const u16 *in, size_t count) +size_t __efi_runtime u16_strnlen(const u16 *in, size_t count) { size_t i; for (i = 0; count-- && in[i]; i++); diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 075481428cd..7fd3a3c90c5 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -88,6 +88,7 @@ config EFI_GET_TIME config EFI_SET_TIME bool "SetTime() runtime service" depends on EFI_GET_TIME + default y if ARCH_QEMU || SANDBOX default n help Provide the SetTime() runtime service at boottime. This service @@ -184,6 +185,13 @@ config EFI_RNG_PROTOCOL Provide a EFI_RNG_PROTOCOL implementation using the hardware random number generator of the platform. +config EFI_TCG2_PROTOCOL + bool "EFI_TCG2_PROTOCOL support" + depends on TPM_V2 + help + Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware + of the platform. + config EFI_LOAD_FILE2_INITRD bool "EFI_FILE_LOAD2_PROTOCOL for Linux initial ramdisk" default n diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 8892fb01e12..cd4b252a417 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_NET) += efi_net.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o +obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_tcg2.o obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_load_initrd.o obj-y += efi_signature.o diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index dfa71b17743..246b59d3b35 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -38,6 +38,9 @@ LIST_HEAD(efi_event_queue); /* Flag to disable timer activity in ExitBootServices() */ static bool timers_enabled = true; +/* Flag used by the selftest to avoid detaching devices in ExitBootServices() */ +bool efi_st_keep_devices; + /* List of all events registered by RegisterProtocolNotify() */ LIST_HEAD(efi_register_notify_events); @@ -1996,10 +1999,12 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, list_del(&evt->link); } - if IS_ENABLED(CONFIG_USB_DEVICE) - udc_disconnect(); - board_quiesce_devices(); - dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); + if (!efi_st_keep_devices) { + if IS_ENABLED(CONFIG_USB_DEVICE) + udc_disconnect(); + board_quiesce_devices(); + dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); + } /* Patch out unsupported runtime function */ efi_runtime_detach(); diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 44fafae0586..72b7ec1e63c 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -723,7 +723,7 @@ static efi_status_t EFIAPI efi_file_setinfo(struct efi_file_handle *file, goto out; } /* Check for renaming */ - new_file_name = malloc(utf16_utf8_strlen(info->file_name)); + new_file_name = malloc(utf16_utf8_strlen(info->file_name) + 1); if (!new_file_name) { ret = EFI_OUT_OF_RESOURCES; goto out; diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c index a8a87007b65..8bdadad0a95 100644 --- a/lib/efi_loader/efi_rng.c +++ b/lib/efi_loader/efi_rng.c @@ -166,13 +166,13 @@ efi_status_t efi_rng_register(void) ret = platform_get_rng_device(&dev); if (ret != EFI_SUCCESS) { - log_warning("Missing RNG device for EFI_RNG_PROTOCOL"); + log_warning("Missing RNG device for EFI_RNG_PROTOCOL\n"); return EFI_SUCCESS; } ret = efi_add_protocol(efi_root, &efi_guid_rng_protocol, (void *)&efi_rng_protocol); if (ret != EFI_SUCCESS) - log_err("Cannot install EFI_RNG_PROTOCOL"); + log_err("Cannot install EFI_RNG_PROTOCOL\n"); return ret; } diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 45226c5c1a5..e206b60bb82 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -156,6 +156,13 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; } + + if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL)) { + ret = efi_tcg2_register(); + if (ret != EFI_SUCCESS) + goto out; + } + /* Initialize variable services */ ret = efi_init_variables(); if (ret != EFI_SUCCESS) diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c new file mode 100644 index 00000000000..62f2f9427b6 --- /dev/null +++ b/lib/efi_loader/efi_tcg2.c @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Defines APIs that allow an OS to interact with UEFI firmware to query + * information about the device. + * https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/ + * + * Copyright (c) 2020, Linaro Limited + */ + +#define LOG_CATEGORY LOGC_EFI +#include <common.h> +#include <dm.h> +#include <efi_loader.h> +#include <efi_tcg2.h> +#include <log.h> +#include <tpm-v2.h> +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * When requesting TPM2_CAP_TPM_PROPERTIES the value is on a standard offset. + * Since the current tpm2_get_capability() response buffers starts at + * 'union tpmu_capabilities data' of 'struct tpms_capability_data', calculate + * the response size and offset once for all consumers + */ +#define TPM2_RESPONSE_BUFFER_SIZE (sizeof(struct tpms_capability_data) - \ + offsetof(struct tpms_capability_data, data)) +#define properties_offset (offsetof(struct tpml_tagged_tpm_property, tpm_property) + \ + offsetof(struct tpms_tagged_property, value)) + +struct { + u16 hash_alg; + u32 hash_mask; +} hash_algo_list[] = { + { + TPM2_ALG_SHA1, + EFI_TCG2_BOOT_HASH_ALG_SHA1, + }, + { + TPM2_ALG_SHA256, + EFI_TCG2_BOOT_HASH_ALG_SHA256, + }, + { + TPM2_ALG_SHA384, + EFI_TCG2_BOOT_HASH_ALG_SHA384, + }, + { + TPM2_ALG_SHA512, + EFI_TCG2_BOOT_HASH_ALG_SHA512, + }, + { + TPM2_ALG_SM3_256, + EFI_TCG2_BOOT_HASH_ALG_SM3_256, + }, +}; + +#define MAX_HASH_COUNT ARRAY_SIZE(hash_algo_list) +/** + * alg_to_mask - Get a TCG hash mask for algorithms + * + * @hash_alg: TCG defined algorithm + * + * @Return: TCG hashing algorithm bitmaps, 0 if the algorithm is not supported + */ +static u32 alg_to_mask(u16 hash_alg) +{ + int i; + + for (i = 0; i < MAX_HASH_COUNT; i++) { + if (hash_algo_list[i].hash_alg == hash_alg) + return hash_algo_list[i].hash_mask; + } + + return 0; +} + +const efi_guid_t efi_guid_tcg2_protocol = EFI_TCG2_PROTOCOL_GUID; + +/** + * platform_get_tpm_device() - retrieve TPM device + * + * This function retrieves the udevice implementing a TPM + * + * This function may be overridden if special initialization is needed. + * + * @dev: udevice + * Return: status code + */ +__weak efi_status_t platform_get_tpm2_device(struct udevice **dev) +{ + for_each_tpm_device(*dev) { + /* Only support TPMv2 devices */ + if (tpm_get_version(*dev) == TPM_V2) + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** + * tpm2_get_max_command_size() - get the supported max command size + * + * @dev: TPM device + * @max_command_size: output buffer for the size + * + * Return: 0 on success, -1 on error + */ +static int tpm2_get_max_command_size(struct udevice *dev, u16 *max_command_size) +{ + u8 response[TPM2_RESPONSE_BUFFER_SIZE]; + u32 ret; + + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES, + TPM2_PT_MAX_COMMAND_SIZE, response, 1); + if (ret) + return -1; + + *max_command_size = (uint16_t)get_unaligned_be32(response + + properties_offset); + + return 0; +} + +/** + * tpm2_get_max_response_size() - get the supported max response size + * + * @dev: TPM device + * @max_response_size: output buffer for the size + * + * Return: 0 on success, -1 on error + */ +static int tpm2_get_max_response_size(struct udevice *dev, + u16 *max_response_size) +{ + u8 response[TPM2_RESPONSE_BUFFER_SIZE]; + u32 ret; + + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES, + TPM2_PT_MAX_RESPONSE_SIZE, response, 1); + if (ret) + return -1; + + *max_response_size = (uint16_t)get_unaligned_be32(response + + properties_offset); + + return 0; +} + +/** + * tpm2_get_manufacturer_id() - get the manufacturer ID + * + * @dev: TPM device + * @manufacturer_id: output buffer for the id + * + * Return: 0 on success, -1 on error + */ +static int tpm2_get_manufacturer_id(struct udevice *dev, u32 *manufacturer_id) +{ + u8 response[TPM2_RESPONSE_BUFFER_SIZE]; + u32 ret; + + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES, + TPM2_PT_MANUFACTURER, response, 1); + if (ret) + return -1; + + *manufacturer_id = get_unaligned_be32(response + properties_offset); + + return 0; +} + +/** + * tpm2_get_num_pcr() - get the number of PCRs + * + * @dev: TPM device + * @manufacturer_id: output buffer for the number + * + * Return: 0 on success, -1 on error + */ +static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr) +{ + u8 response[TPM2_RESPONSE_BUFFER_SIZE]; + u32 ret; + + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES, + TPM2_PT_PCR_COUNT, response, 1); + if (ret) + return -1; + + *num_pcr = get_unaligned_be32(response + properties_offset); + if (*num_pcr > TPM2_MAX_PCRS) + return -1; + + return 0; +} + +/** + * is_active_pcr() - Check if a supported algorithm is active + * + * @dev: TPM device + * @selection: struct of PCR information + * + * Return: true if PCR is active + */ +bool is_active_pcr(struct tpms_pcr_selection *selection) +{ + int i; + /* + * check the pcr_select. If at least one of the PCRs supports the + * algorithm add it on the active ones + */ + for (i = 0; i < selection->size_of_select; i++) { + if (selection->pcr_select[i]) + return true; + } + + return false; +} + +/** + * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks + * + * @dev: TPM device + * @supported_pcr: bitmask with the algorithms supported + * @active_pcr: bitmask with the active algorithms + * @pcr_banks: number of PCR banks + * + * Return: 0 on success, -1 on error + */ +static int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, + u32 *active_pcr, u32 *pcr_banks) +{ + u8 response[TPM2_RESPONSE_BUFFER_SIZE]; + struct tpml_pcr_selection pcrs; + u32 ret, num_pcr; + int i, tpm_ret; + + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1); + if (ret) + goto out; + + pcrs.count = get_unaligned_be32(response); + /* + * We only support 5 algorithms for now so check against that + * instead of TPM2_NUM_PCR_BANKS + */ + if (pcrs.count > MAX_HASH_COUNT || pcrs.count < 1) + goto out; + + tpm_ret = tpm2_get_num_pcr(dev, &num_pcr); + if (tpm_ret) + goto out; + + for (i = 0; i < pcrs.count; i++) { + /* + * Definition of TPMS_PCR_SELECTION Structure + * hash: u16 + * size_of_select: u8 + * pcr_select: u8 array + * + * The offsets depend on the number of the device PCRs + * so we have to calculate them based on that + */ + u32 hash_offset = offsetof(struct tpml_pcr_selection, selection) + + i * offsetof(struct tpms_pcr_selection, pcr_select) + + i * ((num_pcr + 7) / 8); + u32 size_select_offset = + hash_offset + offsetof(struct tpms_pcr_selection, + size_of_select); + u32 pcr_select_offset = + hash_offset + offsetof(struct tpms_pcr_selection, + pcr_select); + + pcrs.selection[i].hash = + get_unaligned_be16(response + hash_offset); + pcrs.selection[i].size_of_select = + __get_unaligned_be(response + size_select_offset); + if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX) + goto out; + /* copy the array of pcr_select */ + memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset, + pcrs.selection[i].size_of_select); + } + + for (i = 0; i < pcrs.count; i++) { + u32 hash_mask = alg_to_mask(pcrs.selection[i].hash); + + if (hash_mask) { + *supported_pcr |= hash_mask; + if (is_active_pcr(&pcrs.selection[i])) + *active_pcr |= hash_mask; + } else { + EFI_PRINT("Unknown algorithm %x\n", pcrs.selection[i].hash); + } + } + + *pcr_banks = pcrs.count; + + return 0; +out: + return -1; +} + +/** + * efi_tcg2_get_capability() - protocol capability information and state information + * + * @this: TCG2 protocol instance + * @capability: caller allocated memory with size field to the size of + * the structure allocated + + * Return: status code + */ +static efi_status_t EFIAPI +efi_tcg2_get_capability(struct efi_tcg2_protocol *this, + struct efi_tcg2_boot_service_capability *capability) +{ + struct udevice *dev; + efi_status_t efi_ret; + int ret; + + EFI_ENTRY("%p, %p", this, capability); + + if (!this || !capability) { + efi_ret = EFI_INVALID_PARAMETER; + goto out; + } + + if (capability->size < boot_service_capability_min) { + capability->size = boot_service_capability_min; + efi_ret = EFI_BUFFER_TOO_SMALL; + goto out; + } + + if (capability->size < sizeof(*capability)) { + capability->size = sizeof(*capability); + efi_ret = EFI_BUFFER_TOO_SMALL; + goto out; + } + + capability->structure_version.major = 1; + capability->structure_version.minor = 1; + capability->protocol_version.major = 1; + capability->protocol_version.minor = 1; + + efi_ret = platform_get_tpm2_device(&dev); + if (efi_ret != EFI_SUCCESS) { + capability->supported_event_logs = 0; + capability->hash_algorithm_bitmap = 0; + capability->tpm_present_flag = false; + capability->max_command_size = 0; + capability->max_response_size = 0; + capability->manufacturer_id = 0; + capability->number_of_pcr_banks = 0; + capability->active_pcr_banks = 0; + + efi_ret = EFI_SUCCESS; + goto out; + } + + /* We only allow a TPMv2 device to register the EFI protocol */ + capability->supported_event_logs = TCG2_EVENT_LOG_FORMAT_TCG_2; + + capability->tpm_present_flag = true; + + /* Supported and active PCRs */ + capability->hash_algorithm_bitmap = 0; + capability->active_pcr_banks = 0; + ret = tpm2_get_pcr_info(dev, &capability->hash_algorithm_bitmap, + &capability->active_pcr_banks, + &capability->number_of_pcr_banks); + if (ret) { + efi_ret = EFI_DEVICE_ERROR; + goto out; + } + + /* Max command size */ + ret = tpm2_get_max_command_size(dev, &capability->max_command_size); + if (ret) { + efi_ret = EFI_DEVICE_ERROR; + goto out; + } + + /* Max response size */ + ret = tpm2_get_max_response_size(dev, &capability->max_response_size); + if (ret) { + efi_ret = EFI_DEVICE_ERROR; + goto out; + } + + /* Manufacturer ID */ + ret = tpm2_get_manufacturer_id(dev, &capability->manufacturer_id); + if (ret) { + efi_ret = EFI_DEVICE_ERROR; + goto out; + } + + return EFI_EXIT(EFI_SUCCESS); +out: + return EFI_EXIT(efi_ret); +} + +/** + * efi_tcg2_get_eventlog() - retrieve the the address of an event log and its + * last entry + * + * @this: TCG2 protocol instance + * @log_format: type of event log format + * @event_log_location: pointer to the memory address of the event log + * @event_log_last_entry: pointer to the address of the start of the last + * entry in the event log in memory, if log contains + * more than 1 entry + * @event_log_truncated: set to true, if the Event Log is missing at i + * least one entry + * + * Return: status code + */ +static efi_status_t EFIAPI +efi_tcg2_get_eventlog(struct efi_tcg2_protocol *this, + efi_tcg_event_log_format log_format, + u64 *event_log_location, u64 *event_log_last_entry, + bool *event_log_truncated) +{ + return EFI_UNSUPPORTED; +} + +/** + * efi_tcg2_hash_log_extend_event() - extend and optionally log events + * + * @this: TCG2 protocol instance + * @flags: bitmap providing additional information on the + * operation + * @data_to_hash: physical address of the start of the data buffer + * to be hashed + * @data_to_hash_len: the length in bytes of the buffer referenced by + * data_to_hash + * @efi_tcg_event: pointer to data buffer containing information + * about the event + * + * Return: status code + */ +static efi_status_t EFIAPI +efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, + u64 data_to_hash, u64 data_to_hash_len, + struct efi_tcg2_event *efi_tcg_event) +{ + return EFI_UNSUPPORTED; +} + +/** + * efi_tcg2_submit_command() - Send command to the TPM + * + * @this: TCG2 protocol instance + * @input_param_block_size: size of the TPM input parameter block + * @input_param_block: pointer to the TPM input parameter block + * @output_param_block_size: size of the TPM output parameter block + * @output_param_block: pointer to the TPM output parameter block + * + * Return: status code + */ +efi_status_t EFIAPI +efi_tcg2_submit_command(struct efi_tcg2_protocol *this, + u32 input_param_block_size, u8 *input_param_block, + u32 output_param_block_size, u8 *output_param_block) +{ + return EFI_UNSUPPORTED; +} + +/** + * efi_tcg2_get_active_pcr_banks() - returns the currently active PCR banks + * + * @this: TCG2 protocol instance + * @active_pcr_banks: pointer for receiving the bitmap of currently + * active PCR banks + * + * Return: status code + */ +efi_status_t EFIAPI +efi_tcg2_get_active_pcr_banks(struct efi_tcg2_protocol *this, + u32 *active_pcr_banks) +{ + return EFI_UNSUPPORTED; +} + +/** + * efi_tcg2_set_active_pcr_banks() - sets the currently active PCR banks + * + * @this: TCG2 protocol instance + * @active_pcr_banks: bitmap of the requested active PCR banks + * + * Return: status code + */ +efi_status_t EFIAPI +efi_tcg2_set_active_pcr_banks(struct efi_tcg2_protocol *this, + u32 active_pcr_banks) +{ + return EFI_UNSUPPORTED; +} + +/** + * efi_tcg2_get_result_of_set_active_pcr_banks() - retrieve result for previous + * set_active_pcr_banks() + * + * @this: TCG2 protocol instance + * @operation_present: non-zero value to indicate a + * set_active_pcr_banks operation was + * invoked during last boot + * @response: result value could be returned + * + * Return: status code + */ +efi_status_t EFIAPI +efi_tcg2_get_result_of_set_active_pcr_banks(struct efi_tcg2_protocol *this, + u32 *operation_present, u32 *response) +{ + return EFI_UNSUPPORTED; +} + +static const struct efi_tcg2_protocol efi_tcg2_protocol = { + .get_capability = efi_tcg2_get_capability, + .get_eventlog = efi_tcg2_get_eventlog, + .hash_log_extend_event = efi_tcg2_hash_log_extend_event, + .submit_command = efi_tcg2_submit_command, + .get_active_pcr_banks = efi_tcg2_get_active_pcr_banks, + .set_active_pcr_banks = efi_tcg2_set_active_pcr_banks, + .get_result_of_set_active_pcr_banks = efi_tcg2_get_result_of_set_active_pcr_banks, +}; + +/** + * efi_tcg2_register() - register EFI_TCG2_PROTOCOL + * + * If a TPM2 device is available, the TPM TCG2 Protocol is registered + * + * Return: An error status is only returned if adding the protocol fails. + */ +efi_status_t efi_tcg2_register(void) +{ + efi_status_t ret; + struct udevice *dev; + + ret = platform_get_tpm2_device(&dev); + if (ret != EFI_SUCCESS) { + log_warning("Unable to find TPMv2 device\n"); + return EFI_SUCCESS; + } + ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol, + (void *)&efi_tcg2_protocol); + if (ret != EFI_SUCCESS) + log_err("Cannot install EFI_TCG2_PROTOCOL\n"); + + return ret; +} diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 1d2b44580f2..d155f25f60e 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -304,8 +304,8 @@ efi_get_variable_mem(u16 *variable_name, const efi_guid_t *vendor, u32 *attribut } efi_status_t __efi_runtime -efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_name, - efi_guid_t *vendor) +efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, + u16 *variable_name, efi_guid_t *vendor) { struct efi_var_entry *var; efi_uintn_t old_size; @@ -314,7 +314,12 @@ efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_na if (!variable_name_size || !variable_name || !vendor) return EFI_INVALID_PARAMETER; - efi_var_mem_find(vendor, variable_name, &var); + if (u16_strnlen(variable_name, *variable_name_size) == + *variable_name_size) + return EFI_INVALID_PARAMETER; + + if (!efi_var_mem_find(vendor, variable_name, &var) && *variable_name) + return EFI_INVALID_PARAMETER; if (!var) return EFI_NOT_FOUND; diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index aabb743ecbb..58fb43fcdfc 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_selftest_rng.o obj-$(CONFIG_EFI_GET_TIME) += efi_selftest_rtc.o obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_selftest_load_initrd.o +obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_selftest_tcg2.o ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_selftest_fdt.o diff --git a/lib/efi_selftest/efi_selftest.c b/lib/efi_selftest/efi_selftest.c index 85e819bdfa1..b8eed048c23 100644 --- a/lib/efi_selftest/efi_selftest.c +++ b/lib/efi_selftest/efi_selftest.c @@ -38,6 +38,9 @@ void efi_st_exit_boot_services(void) efi_status_t ret; struct efi_mem_desc *memory_map; + /* Do not detach devices in ExitBootServices. We need the console. */ + efi_st_keep_devices = true; + ret = boottime->get_memory_map(&map_size, NULL, &map_key, &desc_size, &desc_version); if (ret != EFI_BUFFER_TOO_SMALL) { diff --git a/lib/efi_selftest/efi_selftest_tcg2.c b/lib/efi_selftest/efi_selftest_tcg2.c new file mode 100644 index 00000000000..1399309cec7 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_tcg2.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * efi_selftest_devicepath + * + * Copyright (c) 2020 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * Test the EFI_TCG2_PROTOCOL + */ + +#include <efi_selftest.h> +#include <efi_tcg2.h> + +static struct efi_boot_services *boottime; +static const efi_guid_t guid_tcg2 = EFI_TCG2_PROTOCOL_GUID; + +/** + * efi_st_tcg2_setup() - setup test + * + * @handle: handle of the loaded image + * @systable: system table + * @return: status code + */ +static int efi_st_tcg2_setup(const efi_handle_t img_handle, + const struct efi_system_table *systable) +{ + boottime = systable->boottime; + + return EFI_ST_SUCCESS; +} + +/** + * efi_st_tcg2_execute() - execute test + * + * Call the GetCapability service of the EFI_TCG2_PROTOCOL. + * + * Return: status code + */ +static int efi_st_tcg2_execute(void) +{ + struct efi_tcg2_protocol *tcg2; + struct efi_tcg2_boot_service_capability capability; + efi_status_t ret; + + ret = boottime->locate_protocol(&guid_tcg2, NULL, (void **)&tcg2); + if (ret != EFI_SUCCESS) { + efi_st_error("TCG2 protocol is not available.\n"); + return EFI_ST_FAILURE; + } + capability.size = sizeof(struct efi_tcg2_boot_service_capability) - 1; + ret = tcg2->get_capability(tcg2, &capability); + if (ret != EFI_BUFFER_TOO_SMALL) { + efi_st_error("tcg2->get_capability on small buffer failed\n"); + return EFI_ST_FAILURE; + } + capability.size = sizeof(struct efi_tcg2_boot_service_capability); + ret = tcg2->get_capability(tcg2, &capability); + if (ret != EFI_SUCCESS) { + efi_st_error("tcg2->get_capability failed\n"); + return EFI_ST_FAILURE; + } + if (!capability.tpm_present_flag) { + efi_st_error("TPM not present\n"); + return EFI_ST_FAILURE; + } + efi_st_printf("TPM supports 0x%.8x event logs\n", + capability.supported_event_logs); + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(tcg2) = { + .name = "tcg2", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .execute = efi_st_tcg2_execute, + .setup = efi_st_tcg2_setup, +}; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0aabe7a4516..c0339dcc00d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -848,7 +848,6 @@ CONFIG_IRAM_STACK CONFIG_IRAM_TOP CONFIG_IRDA_BASE CONFIG_IS_ENABLED -CONFIG_JFFS2_CMDLINE CONFIG_JFFS2_DEV CONFIG_JFFS2_LZO CONFIG_JFFS2_NAND @@ -2170,7 +2169,6 @@ CONFIG_SYS_FCC_PSMR CONFIG_SYS_FDT_BASE CONFIG_SYS_FDT_LOAD_ADDR CONFIG_SYS_FDT_PAD -CONFIG_SYS_FDT_SIZE CONFIG_SYS_FEC0_IOBASE CONFIG_SYS_FEC1_IOBASE CONFIG_SYS_FECI2C diff --git a/scripts/dtc/libfdt/fdt.c b/scripts/dtc/libfdt/fdt.c index 8e4cce3b9be..28f4e1a5f15 100644 --- a/scripts/dtc/libfdt/fdt.c +++ b/scripts/dtc/libfdt/fdt.c @@ -131,16 +131,20 @@ int fdt_check_header(const void *fdt) const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len) { - unsigned absoffset = offset + fdt_off_dt_struct(fdt); + unsigned int uoffset = offset; + unsigned int absoffset = offset + fdt_off_dt_struct(fdt); + + if (offset < 0) + return NULL; if (fdt_chk_basic()) - if ((absoffset < offset) + if ((absoffset < uoffset) || ((absoffset + len) < absoffset) || (absoffset + len) > fdt_totalsize(fdt)) return NULL; if (!fdt_chk_version() || fdt_version(fdt) >= 0x11) - if (((offset + len) < offset) + if (((uoffset + len) < uoffset) || ((offset + len) > fdt_size_dt_struct(fdt))) return NULL; @@ -302,9 +306,12 @@ const char *fdt_find_string_(const char *strtab, int tabsize, const char *s) int fdt_move(const void *fdt, void *buf, int bufsize) { + if (fdt_chk_basic() && bufsize < 0) + return -FDT_ERR_NOSPACE; + FDT_RO_PROBE(fdt); - if (fdt_totalsize(fdt) > bufsize) + if (fdt_totalsize(fdt) > (unsigned int)bufsize) return -FDT_ERR_NOSPACE; memmove(buf, fdt, fdt_totalsize(fdt)); diff --git a/scripts/dtc/libfdt/fdt_overlay.c b/scripts/dtc/libfdt/fdt_overlay.c index bd75e3dd786..7a65c35af6f 100644 --- a/scripts/dtc/libfdt/fdt_overlay.c +++ b/scripts/dtc/libfdt/fdt_overlay.c @@ -241,6 +241,7 @@ static int overlay_update_local_node_references(void *fdto, if (fixup_len % sizeof(uint32_t)) return -FDT_ERR_BADOVERLAY; + fixup_len /= sizeof(uint32_t); tree_val = fdt_getprop(fdto, tree_node, name, &tree_len); if (!tree_val) { @@ -250,7 +251,7 @@ static int overlay_update_local_node_references(void *fdto, return tree_len; } - for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) { + for (i = 0; i < fixup_len; i++) { fdt32_t adj_val; uint32_t poffset; diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c index d9d52e0d56e..d984bab036b 100644 --- a/scripts/dtc/libfdt/fdt_ro.c +++ b/scripts/dtc/libfdt/fdt_ro.c @@ -53,7 +53,7 @@ const char *fdt_get_string(const void *fdt, int stroffset, int *lenp) err = -FDT_ERR_BADOFFSET; absoffset = stroffset + fdt_off_dt_strings(fdt); - if (absoffset >= totalsize) + if (absoffset >= (unsigned)totalsize) goto fail; len = totalsize - absoffset; @@ -61,17 +61,19 @@ const char *fdt_get_string(const void *fdt, int stroffset, int *lenp) if (stroffset < 0) goto fail; if (!fdt_chk_version() || fdt_version(fdt) >= 17) { - if (stroffset >= fdt_size_dt_strings(fdt)) + if ((unsigned)stroffset >= fdt_size_dt_strings(fdt)) goto fail; if ((fdt_size_dt_strings(fdt) - stroffset) < len) len = fdt_size_dt_strings(fdt) - stroffset; } } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { - if ((stroffset >= 0) - || (stroffset < -fdt_size_dt_strings(fdt))) + unsigned int sw_stroffset = -stroffset; + + if ((stroffset >= 0) || + (sw_stroffset > fdt_size_dt_strings(fdt))) goto fail; - if ((-stroffset) < len) - len = -stroffset; + if ((sw_stroffset) < len) + len = sw_stroffset; } else { err = -FDT_ERR_INTERNAL; goto fail; @@ -157,8 +159,8 @@ int fdt_generate_phandle(const void *fdt, uint32_t *phandle) static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n) { - int offset = n * sizeof(struct fdt_reserve_entry); - int absoffset = fdt_off_mem_rsvmap(fdt) + offset; + unsigned int offset = n * sizeof(struct fdt_reserve_entry); + unsigned int absoffset = fdt_off_mem_rsvmap(fdt) + offset; if (fdt_chk_extra()) { if (absoffset < fdt_off_mem_rsvmap(fdt)) @@ -679,7 +681,7 @@ int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) { int offset; - if ((phandle == 0) || (phandle == -1)) + if ((phandle == 0) || (phandle == ~0U)) return -FDT_ERR_BADPHANDLE; FDT_RO_PROBE(fdt); diff --git a/scripts/dtc/libfdt/fdt_strerror.c b/scripts/dtc/libfdt/fdt_strerror.c index 768db66eada..b4356931b06 100644 --- a/scripts/dtc/libfdt/fdt_strerror.c +++ b/scripts/dtc/libfdt/fdt_strerror.c @@ -40,7 +40,7 @@ static struct fdt_errtabent fdt_errtable[] = { FDT_ERRTABENT(FDT_ERR_NOPHANDLES), FDT_ERRTABENT(FDT_ERR_BADFLAGS), }; -#define FDT_ERRTABSIZE (sizeof(fdt_errtable) / sizeof(fdt_errtable[0])) +#define FDT_ERRTABSIZE ((int)(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))) const char *fdt_strerror(int errval) { @@ -48,7 +48,7 @@ const char *fdt_strerror(int errval) return "<valid offset/length>"; else if (errval == 0) return "<no error>"; - else if (errval > -FDT_ERRTABSIZE) { + else if (-errval < FDT_ERRTABSIZE) { const char *s = fdt_errtable[-errval].str; if (s) diff --git a/scripts/dtc/libfdt/fdt_sw.c b/scripts/dtc/libfdt/fdt_sw.c index a8c924675a6..d9e67fa2a61 100644 --- a/scripts/dtc/libfdt/fdt_sw.c +++ b/scripts/dtc/libfdt/fdt_sw.c @@ -96,8 +96,8 @@ static inline uint32_t sw_flags(void *fdt) static void *fdt_grab_space_(void *fdt, size_t len) { - int offset = fdt_size_dt_struct(fdt); - int spaceleft; + unsigned int offset = fdt_size_dt_struct(fdt); + unsigned int spaceleft; spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt) - fdt_size_dt_strings(fdt); @@ -111,8 +111,8 @@ static void *fdt_grab_space_(void *fdt, size_t len) int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags) { - const size_t hdrsize = FDT_ALIGN(sizeof(struct fdt_header), - sizeof(struct fdt_reserve_entry)); + const int hdrsize = FDT_ALIGN(sizeof(struct fdt_header), + sizeof(struct fdt_reserve_entry)); void *fdt = buf; if (bufsize < hdrsize) @@ -155,13 +155,16 @@ int fdt_resize(void *fdt, void *buf, int bufsize) FDT_SW_PROBE(fdt); + if (bufsize < 0) + return -FDT_ERR_NOSPACE; + headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); tailsize = fdt_size_dt_strings(fdt); if (fdt_chk_extra() && (headsize + tailsize) > fdt_totalsize(fdt)) return -FDT_ERR_INTERNAL; - if ((headsize + tailsize) > bufsize) + if ((headsize + tailsize) > (unsigned)bufsize) return -FDT_ERR_NOSPACE; oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize; @@ -249,18 +252,18 @@ int fdt_end_node(void *fdt) static int fdt_add_string_(void *fdt, const char *s) { char *strtab = (char *)fdt + fdt_totalsize(fdt); - int strtabsize = fdt_size_dt_strings(fdt); - int len = strlen(s) + 1; - int struct_top, offset; + unsigned int strtabsize = fdt_size_dt_strings(fdt); + unsigned int len = strlen(s) + 1; + unsigned int struct_top, offset; - offset = -strtabsize - len; + offset = strtabsize + len; struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); - if (fdt_totalsize(fdt) + offset < struct_top) + if (fdt_totalsize(fdt) - offset < struct_top) return 0; /* no more room :( */ - memcpy(strtab + offset, s, len); + memcpy(strtab - offset, s, len); fdt_set_size_dt_strings(fdt, strtabsize + len); - return offset; + return -offset; } /* Must only be used to roll back in case of error */ diff --git a/scripts/dtc/libfdt/fdt_wip.c b/scripts/dtc/libfdt/fdt_wip.c index f64139e0b3d..c2d7566a67d 100644 --- a/scripts/dtc/libfdt/fdt_wip.c +++ b/scripts/dtc/libfdt/fdt_wip.c @@ -23,7 +23,7 @@ int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, if (!propval) return proplen; - if (proplen < (len + idx)) + if ((unsigned)proplen < (len + idx)) return -FDT_ERR_NOSPACE; memcpy((char *)propval + idx, val, len); diff --git a/test/nokia_rx51_test.sh b/test/nokia_rx51_test.sh index b17542b8c1f..23fa935310e 100755 --- a/test/nokia_rx51_test.sh +++ b/test/nokia_rx51_test.sh @@ -1,4 +1,4 @@ -#!/bin/sh -e +#!/bin/bash -e # SPDX-License-Identifier: GPL-2.0+ # (C) 2020 Pali Rohár <pali@kernel.org> @@ -157,7 +157,7 @@ setenv bootmenu_1; setenv bootmenu_delay 1; setenv bootdelay 1; EOF -./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu -d bootmenu_emmc bootmenu_emmc.scr +./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_emmc -d bootmenu_emmc bootmenu_emmc.scr # Generate bootmenu for OneNAND booting cat > bootmenu_nand << EOF @@ -166,7 +166,7 @@ setenv bootmenu_1; setenv bootmenu_delay 1; setenv bootdelay 1; EOF -./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu -d bootmenu_nand bootmenu_nand.scr +./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_nand -d bootmenu_nand bootmenu_nand.scr # Generate combined image from u-boot and Maemo fiasco kernel dd if=kernel_2.6.28/boot/zImage-2.6.28-20103103+0m5.fiasco of=zImage-2.6.28-omap1 skip=95 bs=1 @@ -214,10 +214,11 @@ rm -f qemu_ram.log qemu_pid=$! tail -F qemu_ram.log & tail_pid=$! -{ sleep 300 || true; kill -9 $qemu_pid $tail_pid 2>/dev/null || true; } & +sleep 300 & sleep_pid=$! -wait $qemu_pid || true -kill -9 $tail_pid $sleep_pid 2>/dev/null || true +wait -n $sleep_pid $qemu_pid || true +kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true +wait || true # Run MTD image in qemu and wait for 300s if kernel from eMMC is correctly booted rm -f qemu_emmc.log @@ -225,10 +226,11 @@ rm -f qemu_emmc.log qemu_pid=$! tail -F qemu_emmc.log & tail_pid=$! -{ sleep 300 || true; kill -9 $qemu_pid $tail_pid 2>/dev/null || true; } & +sleep 300 & sleep_pid=$! -wait $qemu_pid || true -kill -9 $tail_pid $sleep_pid 2>/dev/null || true +wait -n $sleep_pid $qemu_pid || true +kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true +wait || true # Run MTD image in qemu and wait for 300s if kernel from OneNAND is correctly booted rm -f qemu_nand.log @@ -236,10 +238,11 @@ rm -f qemu_nand.log qemu_pid=$! tail -F qemu_nand.log & tail_pid=$! -{ sleep 300 || true; kill -9 $qemu_pid $tail_pid 2>/dev/null || true; } & +sleep 300 & sleep_pid=$! -wait $qemu_pid || true -kill -9 $tail_pid $sleep_pid 2>/dev/null || true +wait -n $sleep_pid $qemu_pid || true +kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true +wait || true echo echo "=============================" diff --git a/tools/.gitignore b/tools/.gitignore index 82bdce27829..a021ea95cd6 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -32,5 +32,6 @@ /spl_size_limit /sunxi-spl-image-builder /ubsha1 +/update_octeon_header /version.h /xway-swap-bytes diff --git a/tools/Makefile b/tools/Makefile index 51123fd9298..253a6b97065 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -206,6 +206,9 @@ hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela hostprogs-$(CONFIG_RISCV) += prelink-riscv +hostprogs-$(CONFIG_ARCH_OCTEON) += update_octeon_header +update_octeon_header-objs := update_octeon_header.o lib/crc32.o + hostprogs-y += fdtgrep fdtgrep-objs += $(LIBFDT_OBJS) common/fdt_region.o fdtgrep.o diff --git a/tools/image-host.c b/tools/image-host.c index 7cef78eab8f..e32cc642579 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -335,14 +335,14 @@ static int get_random_data(void *data, int size) ret = clock_gettime(CLOCK_MONOTONIC, &date); if (ret < 0) { printf("%s: clock_gettime has failed (err=%d, str=%s)\n", - __func__, ret, strerror(ret)); + __func__, ret, strerror(errno)); goto out; } - srand(date.tv_nsec); + srandom(date.tv_nsec); for (i = 0; i < size; i++) { - *tmp = rand() & 0xff; + *tmp = random() & 0xff; tmp++; } diff --git a/tools/imagetool.h b/tools/imagetool.h index acbc48e9be0..8726792c8c0 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -126,9 +126,9 @@ struct image_type_params { struct image_tool_params *); /* * This function is used by the command to retrieve a component - * (sub-image) from the image (i.e. dumpimage -i <image> -p <position> - * <sub-image-name>). - * Thus the code to extract a file from an image must be put here. + * (sub-image) from the image (i.e. dumpimage -p <position> + * -o <component-outfile> <image>). Thus the code to extract a file + * from an image must be put here. * * Returns 0 if the file was successfully retrieved from the image, * or a negative value on error. diff --git a/tools/patman/README b/tools/patman/README index 49b73590cf0..6b806632f8c 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -113,6 +113,7 @@ ignore_errors: True process_tags: False verbose: True smtp_server: /path/to/sendmail +patchwork_server: https://patchwork.ozlabs.org <<< @@ -207,6 +208,12 @@ Series-links: [id | version:id]... branch against patchwork to see what new reviews your series has collected ('patman status'). +Series-patchwork-url: url + This allows specifying the Patchwork URL for a branch. This overrides + both the setting files and the command-line argument. The URL should + include the protocol and web site, with no trailing slash, for example + 'https://patchwork.ozlabs.org/project' + Cover-letter: This is the patch set title blah blah diff --git a/tools/patman/control.py b/tools/patman/control.py index f4a6ca145d4..2330682df4a 100644 --- a/tools/patman/control.py +++ b/tools/patman/control.py @@ -177,7 +177,7 @@ def send(args): args.smtp_server) def patchwork_status(branch, count, start, end, dest_branch, force, - show_comments): + show_comments, url): """Check the status of patches in patchwork This finds the series in patchwork using the Series-link tag, checks for new @@ -196,6 +196,8 @@ def patchwork_status(branch, count, start, end, dest_branch, force, force (bool): With dest_branch, force overwriting an existing branch show_comments (bool): True to display snippets from the comments provided by reviewers + url (str): URL of patchwork server, e.g. 'https://patchwork.ozlabs.org'. + This is ignored if the series provides a Series-patchwork-url tag. Raises: ValueError: if the branch has no Series-link value @@ -224,8 +226,12 @@ def patchwork_status(branch, count, start, end, dest_branch, force, if not found: raise ValueError('Series-links has no current version (without :)') + # Allow the series to override the URL + if 'patchwork_url' in series: + url = series.patchwork_url + # Import this here to avoid failing on other commands if the dependencies # are not present from patman import status status.check_patchwork_status(series, found[0], branch, dest_branch, force, - show_comments) + show_comments, url) diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index e2adf32c739..74a144dc2d5 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -248,7 +248,7 @@ class TestFunctional(unittest.TestCase): self.assertEqual(' Cc: %s' % rick, next(lines)) expected = ('Git command: git send-email --annotate ' '--in-reply-to="%s" --to "u-boot@lists.denx.de" ' - '--cc "%s" --cc-cmd "%s --cc-cmd %s" %s %s' + '--cc "%s" --cc-cmd "%s send --cc-cmd %s" %s %s' % (in_reply_to, stefan, sys.argv[0], cc_file, cover_fname, ' '.join(args))) self.assertEqual(expected, tools.ToUnicode(next(lines))) @@ -625,11 +625,15 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c os.chdir(orig_dir) @staticmethod - def _fake_patchwork(subpath): + def _fake_patchwork(url, subpath): """Fake Patchwork server for the function below This handles accessing a series, providing a list consisting of a single patch + + Args: + url (str): URL of patchwork server + subpath (str): URL subpath to use """ re_series = re.match(r'series/(\d*)/$', subpath) if re_series: @@ -645,7 +649,7 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c series = Series() with capture_sys_output() as (_, err): - status.collect_patches(series, 1234, self._fake_patchwork) + status.collect_patches(series, 1234, None, self._fake_patchwork) self.assertIn('Warning: Patchwork reports 1 patches, series has 0', err.getvalue()) @@ -655,7 +659,8 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c series = Series() series.commits = [Commit('abcd')] - patches = status.collect_patches(series, 1234, self._fake_patchwork) + patches = status.collect_patches(series, 1234, None, + self._fake_patchwork) self.assertEqual(1, len(patches)) patch = patches[0] self.assertEqual('1', patch.id) @@ -800,11 +805,15 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c "Cannot find commit for patch 3 ('Subject 2')"], warnings) - def _fake_patchwork2(self, subpath): + def _fake_patchwork2(self, url, subpath): """Fake Patchwork server for the function below This handles accessing series, patches and comments, providing the data in self.patches to the caller + + Args: + url (str): URL of patchwork server + subpath (str): URL subpath to use """ re_series = re.match(r'series/(\d*)/$', subpath) re_patch = re.match(r'patches/(\d*)/$', subpath) @@ -861,12 +870,12 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c # Check that the tags are picked up on the first patch status.find_new_responses(new_rtag_list, review_list, 0, commit1, - patch1, self._fake_patchwork2) + patch1, None, self._fake_patchwork2) self.assertEqual(new_rtag_list[0], {'Reviewed-by': {self.joe}}) # Now the second patch status.find_new_responses(new_rtag_list, review_list, 1, commit2, - patch2, self._fake_patchwork2) + patch2, None, self._fake_patchwork2) self.assertEqual(new_rtag_list[1], { 'Reviewed-by': {self.mary, self.fred}, 'Tested-by': {self.leb}}) @@ -876,7 +885,7 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c new_rtag_list = [None] * count commit1.rtags = {'Reviewed-by': {self.joe}} status.find_new_responses(new_rtag_list, review_list, 0, commit1, - patch1, self._fake_patchwork2) + patch1, None, self._fake_patchwork2) self.assertEqual(new_rtag_list[0], {}) # For the second commit, add Ed and Fred, so only Mary should be left @@ -884,7 +893,7 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c 'Tested-by': {self.leb}, 'Reviewed-by': {self.fred}} status.find_new_responses(new_rtag_list, review_list, 1, commit2, - patch2, self._fake_patchwork2) + patch2, None, self._fake_patchwork2) self.assertEqual(new_rtag_list[1], {'Reviewed-by': {self.mary}}) # Check that the output patches expectations: @@ -900,7 +909,7 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c series.commits = [commit1, commit2] terminal.SetPrintTestMode() status.check_patchwork_status(series, '1234', None, None, False, False, - self._fake_patchwork2) + None, self._fake_patchwork2) lines = iter(terminal.GetPrintTestLines()) col = terminal.Color() self.assertEqual(terminal.PrintLine(' 1 Subject 1', col.BLUE), @@ -935,11 +944,15 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c '1 new response available in patchwork (use -d to write them to a new branch)', None), next(lines)) - def _fake_patchwork3(self, subpath): + def _fake_patchwork3(self, url, subpath): """Fake Patchwork server for the function below This handles accessing series, patches and comments, providing the data in self.patches to the caller + + Args: + url (str): URL of patchwork server + subpath (str): URL subpath to use """ re_series = re.match(r'series/(\d*)/$', subpath) re_patch = re.match(r'patches/(\d*)/$', subpath) @@ -1011,7 +1024,8 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c terminal.SetPrintTestMode() status.check_patchwork_status(series, '1234', branch, dest_branch, - False, False, self._fake_patchwork3, repo) + False, False, None, self._fake_patchwork3, + repo) lines = terminal.GetPrintTestLines() self.assertEqual(12, len(lines)) self.assertEqual( @@ -1214,7 +1228,7 @@ Reviewed-by: %s series.commits = [commit1, commit2] terminal.SetPrintTestMode() status.check_patchwork_status(series, '1234', None, None, False, True, - self._fake_patchwork2) + None, self._fake_patchwork2) lines = iter(terminal.GetPrintTestLines()) col = terminal.Color() self.assertEqual(terminal.PrintLine(' 1 Subject 1', col.BLUE), diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 3a2366bcf59..31fb3b28299 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -455,21 +455,21 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \ False, alias) 'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \ -"m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" cover p1 p2' +"m.poppins@cloud.net" --cc-cmd "./patman send --cc-cmd cc-fname" cover p1 p2' >>> EmailPatches(series, None, ['p1'], True, True, 'cc-fname', False, \ alias) 'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \ -"m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" p1' +"m.poppins@cloud.net" --cc-cmd "./patman send --cc-cmd cc-fname" p1' >>> series['cc'] = ['all'] >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \ True, alias) 'git send-email --annotate --to "this-is-me@me.com" --cc-cmd "./patman \ ---cc-cmd cc-fname" cover p1 p2' +send --cc-cmd cc-fname" cover p1 p2' >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \ False, alias) 'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \ "f.bloggs@napier.co.nz" --cc "j.bloggs@napier.co.nz" --cc \ -"m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" cover p1 p2' +"m.poppins@cloud.net" --cc-cmd "./patman send --cc-cmd cc-fname" cover p1 p2' # Restore argv[0] since we clobbered it. >>> sys.argv[0] = _old_argv0 @@ -500,7 +500,7 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, cmd += to cmd += cc - cmd += ['--cc-cmd', '"%s --cc-cmd %s"' % (sys.argv[0], cc_fname)] + cmd += ['--cc-cmd', '"%s send --cc-cmd %s"' % (sys.argv[0], cc_fname)] if cover_fname: cmd.append(cover_fname) cmd += args diff --git a/tools/patman/main.py b/tools/patman/main.py index c7f425522b2..342fd446a12 100755 --- a/tools/patman/main.py +++ b/tools/patman/main.py @@ -28,26 +28,33 @@ from patman import terminal from patman import test_util from patman import test_checkpatch -def AddCommonArgs(parser): - parser.add_argument('-b', '--branch', type=str, - help="Branch to process (by default, the current branch)") - parser.add_argument('-c', '--count', dest='count', type=int, - default=-1, help='Automatically create patches from top n commits') - parser.add_argument('-e', '--end', type=int, default=0, - help='Commits to skip at end of patch list') - parser.add_argument('-D', '--debug', action='store_true', - help='Enabling debugging (provides a full traceback on error)') - parser.add_argument('-s', '--start', dest='start', type=int, - default=0, help='Commit to start creating patches from (0 = HEAD)') - epilog = '''Create patches from commits in a branch, check them and email them as specified by tags you place in the commits. Use -n to do a dry run first.''' parser = ArgumentParser(epilog=epilog) +parser.add_argument('-b', '--branch', type=str, + help="Branch to process (by default, the current branch)") +parser.add_argument('-c', '--count', dest='count', type=int, + default=-1, help='Automatically create patches from top n commits') +parser.add_argument('-e', '--end', type=int, default=0, + help='Commits to skip at end of patch list') +parser.add_argument('-D', '--debug', action='store_true', + help='Enabling debugging (provides a full traceback on error)') +parser.add_argument('-p', '--project', default=project.DetectProject(), + help="Project name; affects default option values and " + "aliases [default: %(default)s]") +parser.add_argument('-P', '--patchwork-url', + default='https://patchwork.ozlabs.org', + help='URL of patchwork server [default: %(default)s]') +parser.add_argument('-s', '--start', dest='start', type=int, + default=0, help='Commit to start creating patches from (0 = HEAD)') +parser.add_argument('-v', '--verbose', action='store_true', dest='verbose', + default=False, help='Verbose output of errors and warnings') +parser.add_argument('-H', '--full-help', action='store_true', dest='full_help', + default=False, help='Display the README file') + subparsers = parser.add_subparsers(dest='cmd') send = subparsers.add_parser('send') -send.add_argument('-H', '--full-help', action='store_true', dest='full_help', - default=False, help='Display the README file') send.add_argument('-i', '--ignore-errors', action='store_true', dest='ignore_errors', default=False, help='Send patches email even if patch errors are found') @@ -58,15 +65,10 @@ send.add_argument('-m', '--no-maintainers', action='store_false', help="Don't cc the file maintainers automatically") send.add_argument('-n', '--dry-run', action='store_true', dest='dry_run', default=False, help="Do a dry run (create but don't email patches)") -send.add_argument('-p', '--project', default=project.DetectProject(), - help="Project name; affects default option values and " - "aliases [default: %(default)s]") send.add_argument('-r', '--in-reply-to', type=str, action='store', help="Message ID that this series is in reply to") send.add_argument('-t', '--ignore-bad-tags', action='store_true', default=False, help='Ignore bad tags / aliases') -send.add_argument('-v', '--verbose', action='store_true', dest='verbose', - default=False, help='Verbose output of errors and warnings') send.add_argument('-T', '--thread', action='store_true', dest='thread', default=False, help='Create patches as a single thread') send.add_argument('--cc-cmd', dest='cc_cmd', type=str, action='store', @@ -81,14 +83,12 @@ send.add_argument('--no-tags', action='store_false', dest='process_tags', default=True, help="Don't process subject tags as aliases") send.add_argument('--smtp-server', type=str, help="Specify the SMTP server to 'git send-email'") -AddCommonArgs(send) send.add_argument('patchfiles', nargs='*') test_parser = subparsers.add_parser('test', help='Run tests') test_parser.add_argument('testname', type=str, default=None, nargs='?', help="Specify the test to run") -AddCommonArgs(test_parser) status = subparsers.add_parser('status', help='Check status of patches in patchwork') @@ -98,16 +98,24 @@ status.add_argument('-d', '--dest-branch', type=str, help='Name of branch to create with collected responses') status.add_argument('-f', '--force', action='store_true', help='Force overwriting an existing branch') -AddCommonArgs(status) # Parse options twice: first to get the project and second to handle -# defaults properly (which depends on project). +# defaults properly (which depends on project) +# Use parse_known_args() in case 'cmd' is omitted argv = sys.argv[1:] -if len(argv) < 1 or argv[0].startswith('-'): - argv = ['send'] + argv -args = parser.parse_args(argv) +args, rest = parser.parse_known_args(argv) if hasattr(args, 'project'): - settings.Setup(gitutil, send, args.project, '') + settings.Setup(gitutil, parser, args.project, '') + args, rest = parser.parse_known_args(argv) + +# If we have a command, it is safe to parse all arguments +if args.cmd: + args = parser.parse_args(argv) +else: + # No command, so insert it after the known arguments and before the ones + # that presumably relate to the 'send' subcommand + nargs = len(rest) + argv = argv[:-nargs] + ['send'] + rest args = parser.parse_args(argv) if __name__ != "__main__": @@ -174,7 +182,7 @@ elif args.cmd == 'status': try: control.patchwork_status(args.branch, args.count, args.start, args.end, args.dest_branch, args.force, - args.show_comments) + args.show_comments, args.patchwork_url) except Exception as e: terminal.Print('patman: %s: %s' % (type(e).__name__, e), colour=terminal.Color.RED) diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 772e4b56617..cdcd50a8499 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -452,8 +452,8 @@ class PatchStream: if self.is_log: if self.commit.change_id: raise ValueError( - "%s: Two Change-Ids: '%s' vs. '%s'" % self.commit.hash, - self.commit.change_id, value) + "%s: Two Change-Ids: '%s' vs. '%s'" % + (self.commit.hash, self.commit.change_id, value)) self.commit.change_id = value self.skip_blank = True diff --git a/tools/patman/series.py b/tools/patman/series.py index 4457719f2ef..1d92bdb9103 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -16,7 +16,7 @@ from patman import tools # Series-xxx tags that we understand valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name', - 'cover_cc', 'process_log', 'links'] + 'cover_cc', 'process_log', 'links', 'patchwork_url'] class Series(dict): """Holds information about a patch series, including all tags. diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 732bd401067..8c10eab2645 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -7,6 +7,7 @@ try: except: import ConfigParser +import argparse import os import re @@ -216,10 +217,10 @@ nxp = Zhikang Zhang <zhikang.zhang@nxp.com> ''' % (name, email), file=f) f.close(); -def _UpdateDefaults(parser, config): +def _UpdateDefaults(main_parser, config): """Update the given OptionParser defaults based on config. - We'll walk through all of the settings from the parser + We'll walk through all of the settings from all parsers. For each setting we'll look for a default in the option parser. If it's found we'll update the option parser default. @@ -228,13 +229,24 @@ def _UpdateDefaults(parser, config): say. Args: - parser: An instance of an OptionParser whose defaults will be + parser: An instance of an ArgumentParser whose defaults will be updated. config: An instance of _ProjectConfigParser that we will query for settings. """ - defaults = parser.parse_known_args()[0] - defaults = vars(defaults) + # Find all the parsers and subparsers + parsers = [main_parser] + parsers += [subparser for action in main_parser._actions + if isinstance(action, argparse._SubParsersAction) + for _, subparser in action.choices.items()] + + # Collect the defaults from each parser + defaults = {} + for parser in parsers: + pdefs = parser.parse_known_args()[0] + defaults.update(vars(pdefs)) + + # Go through the settings and collect defaults for name, val in config.items('settings'): if name in defaults: default_val = defaults[name] @@ -242,10 +254,14 @@ def _UpdateDefaults(parser, config): val = config.getboolean('settings', name) elif isinstance(default_val, int): val = config.getint('settings', name) + elif isinstance(default_val, str): + val = config.get('settings', name) defaults[name] = val else: print("WARNING: Unknown setting %s" % name) - parser.set_defaults(**defaults) + + # Set all the defaults (this propagates through all subparsers) + main_parser.set_defaults(**defaults) def _ReadAliasFile(fname): """Read in the U-Boot git alias file if it exists. diff --git a/tools/patman/status.py b/tools/patman/status.py index a369d655c5e..f3fbc661b2f 100644 --- a/tools/patman/status.py +++ b/tools/patman/status.py @@ -198,10 +198,11 @@ def compare_with_series(series, patches): return patch_for_commit, commit_for_patch, warnings -def call_rest_api(subpath): +def call_rest_api(url, subpath): """Call the patchwork API and return the result as JSON Args: + url (str): URL of patchwork server, e.g. 'https://patchwork.ozlabs.org' subpath (str): URL subpath to use Returns: @@ -210,13 +211,13 @@ def call_rest_api(subpath): Raises: ValueError: the URL could not be read """ - url = 'https://patchwork.ozlabs.org/api/1.2/%s' % subpath - response = requests.get(url) + full_url = '%s/api/1.2/%s' % (url, subpath) + response = requests.get(full_url) if response.status_code != 200: - raise ValueError("Could not read URL '%s'" % url) + raise ValueError("Could not read URL '%s'" % full_url) return response.json() -def collect_patches(series, series_id, rest_api=call_rest_api): +def collect_patches(series, series_id, url, rest_api=call_rest_api): """Collect patch information about a series from patchwork Uses the Patchwork REST API to collect information provided by patchwork @@ -226,6 +227,7 @@ def collect_patches(series, series_id, rest_api=call_rest_api): series (Series): Series object corresponding to the local branch containing the series series_id (str): Patch series ID number + url (str): URL of patchwork server, e.g. 'https://patchwork.ozlabs.org' rest_api (function): API function to call to access Patchwork, for testing @@ -236,7 +238,7 @@ def collect_patches(series, series_id, rest_api=call_rest_api): ValueError: if the URL could not be read or the web page does not follow the expected structure """ - data = rest_api('series/%s/' % series_id) + data = rest_api(url, 'series/%s/' % series_id) # Get all the rows, which are patches patch_dict = data['patches'] @@ -261,7 +263,7 @@ def collect_patches(series, series_id, rest_api=call_rest_api): patches = sorted(patches, key=lambda x: x.seq) return patches -def find_new_responses(new_rtag_list, review_list, seq, cmt, patch, +def find_new_responses(new_rtag_list, review_list, seq, cmt, patch, url, rest_api=call_rest_api): """Find new rtags collected by patchwork that we don't know about @@ -279,6 +281,7 @@ def find_new_responses(new_rtag_list, review_list, seq, cmt, patch, seq (int): Position in new_rtag_list to update cmt (Commit): Commit object for this commit patch (Patch): Corresponding Patch object for this patch + url (str): URL of patchwork server, e.g. 'https://patchwork.ozlabs.org' rest_api (function): API function to call to access Patchwork, for testing """ @@ -286,14 +289,14 @@ def find_new_responses(new_rtag_list, review_list, seq, cmt, patch, return # Get the content for the patch email itself as well as all comments - data = rest_api('patches/%s/' % patch.id) + data = rest_api(url, 'patches/%s/' % patch.id) pstrm = PatchStream.process_text(data['content'], True) rtags = collections.defaultdict(set) for response, people in pstrm.commit.rtags.items(): rtags[response].update(people) - data = rest_api('patches/%s/comments/' % patch.id) + data = rest_api(url, 'patches/%s/comments/' % patch.id) reviews = [] for comment in data: @@ -407,7 +410,7 @@ def create_branch(series, new_rtag_list, branch, dest_branch, overwrite, return num_added def check_patchwork_status(series, series_id, branch, dest_branch, force, - show_comments, rest_api=call_rest_api, + show_comments, url, rest_api=call_rest_api, test_repo=None): """Check the status of a series on Patchwork @@ -421,11 +424,12 @@ def check_patchwork_status(series, series_id, branch, dest_branch, force, dest_branch (str): Name of new branch to create, or None force (bool): True to force overwriting dest_branch if it exists show_comments (bool): True to show the comments on each patch + url (str): URL of patchwork server, e.g. 'https://patchwork.ozlabs.org' rest_api (function): API function to call to access Patchwork, for testing test_repo (pygit2.Repository): Repo to use (use None unless testing) """ - patches = collect_patches(series, series_id, rest_api) + patches = collect_patches(series, series_id, url, rest_api) col = terminal.Color() count = len(series.commits) new_rtag_list = [None] * count @@ -440,7 +444,8 @@ def check_patchwork_status(series, series_id, branch, dest_branch, force, with concurrent.futures.ThreadPoolExecutor(max_workers=16) as executor: futures = executor.map( find_new_responses, repeat(new_rtag_list), repeat(review_list), - range(count), series.commits, patch_list, repeat(rest_api)) + range(count), series.commits, patch_list, repeat(url), + repeat(rest_api)) for fresponse in futures: if fresponse: raise fresponse.exception() diff --git a/tools/patman/tools.py b/tools/patman/tools.py index bbb157da873..05b1a1d4b08 100644 --- a/tools/patman/tools.py +++ b/tools/patman/tools.py @@ -333,6 +333,7 @@ def Run(name, *args, **kwargs): elif for_host: name, extra_args = GetHostCompileTool(name) args = tuple(extra_args) + args + name = os.path.expanduser(name) # Expand paths containing ~ all_args = (name,) + args result = command.RunPipe([all_args], capture=True, capture_stderr=True, env=env, raise_on_error=False, binary=binary) diff --git a/tools/update_octeon_header.c b/tools/update_octeon_header.c new file mode 100644 index 00000000000..8054ceec855 --- /dev/null +++ b/tools/update_octeon_header.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <stdio.h> +#include <stdint.h> +#include <stddef.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <stdbool.h> +#include <stdlib.h> +#include <string.h> +#include <getopt.h> +#include <arpa/inet.h> +#include <linux/compiler.h> +#include <u-boot/crc.h> + +#include "mkimage.h" + +#include "../arch/mips/mach-octeon/include/mach/cvmx-bootloader.h" + +#define BUF_SIZE (16 * 1024) +#define NAME_LEN 100 + +/* word offset */ +#define WOFFSETOF(type, elem) (offsetof(type, elem) / 4) + +static int stage2_flag; +static int stage_1_5_flag; +static int stage_1_flag; + +/* Getoptions variables must be global */ +static int failsafe_flag; +static int pciboot_flag; +static int env_flag; + +static const struct option long_options[] = { + /* These options set a flag. */ + {"failsafe", no_argument, &failsafe_flag, 1}, + {"pciboot", no_argument, &pciboot_flag, 1}, + {"nandstage2", no_argument, &stage2_flag, 1}, + {"spistage2", no_argument, &stage2_flag, 1}, + {"norstage2", no_argument, &stage2_flag, 1}, + {"stage2", no_argument, &stage2_flag, 1}, + {"stage1.5", no_argument, &stage_1_5_flag, 1}, + {"stage1", no_argument, &stage_1_flag, 1}, + {"environment", no_argument, &env_flag, 1}, + /* + * These options don't set a flag. + * We distinguish them by their indices. + */ + {"board", required_argument, 0, 0}, + {"text_base", required_argument, 0, 0}, + {0, 0, 0, 0} +}; + +static int lookup_board_type(char *board_name) +{ + int i; + int board_type = 0; + char *substr = NULL; + + /* Detect stage 2 bootloader boards */ + if (strcasestr(board_name, "_stage2")) { + printf("Stage 2 bootloader detected from substring %s in name %s\n", + "_stage2", board_name); + stage2_flag = 1; + } else { + printf("Stage 2 bootloader NOT detected from name \"%s\"\n", + board_name); + } + + if (strcasestr(board_name, "_stage1")) { + printf("Stage 1 bootloader detected from substring %s in name %s\n", + "_stage1", board_name); + stage_1_flag = 1; + } + + /* Generic is a special case since there are numerous sub-types */ + if (!strncasecmp("generic", board_name, strlen("generic"))) + return CVMX_BOARD_TYPE_GENERIC; + + /* + * If we're an eMMC stage 2 bootloader, cut off the _emmc_stage2 + * part of the name. + */ + substr = strcasestr(board_name, "_emmc_stage2"); + if (substr && (substr[strlen("_emmc_stage2")] == '\0')) { + /*return CVMX_BOARD_TYPE_GENERIC;*/ + + printf(" Converting board name %s to ", board_name); + *substr = '\0'; + printf("%s\n", board_name); + } + + /* + * If we're a NAND stage 2 bootloader, cut off the _nand_stage2 + * part of the name. + */ + substr = strcasestr(board_name, "_nand_stage2"); + if (substr && (substr[strlen("_nand_stage2")] == '\0')) { + /*return CVMX_BOARD_TYPE_GENERIC;*/ + + printf(" Converting board name %s to ", board_name); + *substr = '\0'; + printf("%s\n", board_name); + } + + /* + * If we're a SPI stage 2 bootloader, cut off the _spi_stage2 + * part of the name. + */ + substr = strcasestr(board_name, "_spi_stage2"); + if (substr && (substr[strlen("_spi_stage2")] == '\0')) { + printf(" Converting board name %s to ", board_name); + *substr = '\0'; + printf("%s\n", board_name); + } + + for (i = CVMX_BOARD_TYPE_NULL; i < CVMX_BOARD_TYPE_MAX; i++) + if (!strcasecmp(cvmx_board_type_to_string(i), board_name)) + board_type = i; + + for (i = CVMX_BOARD_TYPE_CUST_DEFINED_MIN; + i < CVMX_BOARD_TYPE_CUST_DEFINED_MAX; i++) + if (!strncasecmp(cvmx_board_type_to_string(i), board_name, + strlen(cvmx_board_type_to_string(i)))) + board_type = i; + + for (i = CVMX_BOARD_TYPE_CUST_PRIVATE_MIN; + i < CVMX_BOARD_TYPE_CUST_PRIVATE_MAX; i++) + if (!strncasecmp(cvmx_board_type_to_string(i), board_name, + strlen(cvmx_board_type_to_string(i)))) + board_type = i; + + return board_type; +} + +static void usage(void) +{ + printf("Usage: update_octeon_header <filename> <board_name> [--failsafe] [--text_base=0xXXXXX]\n"); +} + +int main(int argc, char *argv[]) +{ + int fd; + uint8_t buf[BUF_SIZE]; + uint32_t data_crc = 0; + int len; + int data_len = 0; + struct bootloader_header header; + char filename[NAME_LEN]; + int i; + int option_index = 0; /* getopt_long stores the option index here. */ + char board_name[NAME_LEN] = { 0 }; + char tmp_board_name[NAME_LEN] = { 0 }; + int c; + int board_type = 0; + unsigned long long address = 0; + ssize_t ret; + const char *type_str = NULL; + int hdr_size = sizeof(struct bootloader_header); + + /* + * Compile time check, if the size of the bootloader_header structure + * has changed. + */ + compiletime_assert(sizeof(struct bootloader_header) == 192, + "Octeon bootloader header size changed (!= 192)!"); + + /* Bail out, if argument count is incorrect */ + if (argc < 3) { + usage(); + return -1; + } + + debug("header size is: %d bytes\n", hdr_size); + + /* Parse command line options using getopt_long */ + while (1) { + c = getopt_long(argc, argv, "h", long_options, &option_index); + + /* Detect the end of the options. */ + if (c == -1) + break; + + switch (c) { + /* All long options handled in case 0 */ + case 0: + /* If this option set a flag, do nothing else now. */ + if (long_options[option_index].flag != 0) + break; + debug("option(l) %s", long_options[option_index].name); + + if (!optarg) { + usage(); + return -1; + } + debug(" with arg %s\n", optarg); + + if (!strcmp(long_options[option_index].name, "board")) { + if (strlen(optarg) >= NAME_LEN) { + printf("strncpy() issue detected!"); + exit(-1); + } + strncpy(board_name, optarg, NAME_LEN); + + printf("Using user supplied board name: %s\n", + board_name); + } else if (!strcmp(long_options[option_index].name, + "text_base")) { + address = strtoull(optarg, NULL, 0); + printf("Address of image is: 0x%llx\n", + (unsigned long long)address); + if (!(address & 0xFFFFFFFFULL << 32)) { + if (address & 1 << 31) { + address |= 0xFFFFFFFFULL << 32; + printf("Converting address to 64 bit compatibility space: 0x%llx\n", + address); + } + } + } + break; + + case 'h': + case '?': + /* getopt_long already printed an error message. */ + usage(); + return -1; + + default: + abort(); + } + } + + if (optind < argc) { + /* + * We only support one argument - an optional bootloader + * file name + */ + if (argc - optind > 2) { + fprintf(stderr, "non-option ARGV-elements: "); + while (optind < argc) + fprintf(stderr, "%s ", argv[optind++]); + fprintf(stderr, "\n"); + + usage(); + return -1; + } + } + + if (strlen(argv[optind]) >= NAME_LEN) { + fprintf(stderr, "strncpy() issue detected!"); + exit(-1); + } + strncpy(filename, argv[optind], NAME_LEN); + + if (board_name[0] == '\0') { + if (strlen(argv[optind + 1]) >= NAME_LEN) { + fprintf(stderr, "strncpy() issue detected!"); + exit(-1); + } + strncpy(board_name, argv[optind + 1], NAME_LEN); + } + + if (strlen(board_name) >= NAME_LEN) { + fprintf(stderr, "strncpy() issue detected!"); + exit(-1); + } + strncpy(tmp_board_name, board_name, NAME_LEN); + + fd = open(filename, O_RDWR); + if (fd < 0) { + fprintf(stderr, "Unable to open file: %s\n", filename); + exit(-1); + } + + if (failsafe_flag) + printf("Setting failsafe flag\n"); + + if (strlen(board_name)) { + int offset = 0; + + printf("Supplied board name of: %s\n", board_name); + + if (strstr(board_name, "failsafe")) { + failsafe_flag = 1; + printf("Setting failsafe flag based on board name\n"); + } + /* Skip leading octeon_ if present. */ + if (!strncmp(board_name, "octeon_", 7)) + offset = 7; + + /* + * Check to see if 'failsafe' is in the name. If so, set the + * failsafe flag. Also, ignore extra trailing characters on + * passed parameter when comparing against board names. + * We actually use the configuration name from u-boot, so it + * may have some other variant names. Variants other than + * failsafe _must_ be passed to this program explicitly + */ + + board_type = lookup_board_type(board_name + offset); + if (!board_type) { + /* Retry with 'cust_' prefix to catch boards that are + * in the customer section (such as nb5) + */ + sprintf(tmp_board_name, "cust_%s", board_name + offset); + board_type = lookup_board_type(tmp_board_name); + } + + /* reset to original value */ + strncpy(tmp_board_name, board_name, NAME_LEN); + if (!board_type) { + /* + * Retry with 'cust_private_' prefix to catch boards + * that are in the customer private section + */ + sprintf(tmp_board_name, "cust_private_%s", + board_name + offset); + board_type = lookup_board_type(tmp_board_name); + } + + if (!board_type) { + fprintf(stderr, + "ERROR: unable to determine board type\n"); + exit(-1); + } + printf("Board type is: %d: %s\n", board_type, + cvmx_board_type_to_string(board_type)); + } else { + fprintf(stderr, "Board name must be specified!\n"); + exit(-1); + } + + /* + * Check to see if there is either an existing header, or that there + * are zero valued bytes where we want to put the header + */ + len = read(fd, buf, BUF_SIZE); + if (len > 0) { + /* + * Copy the header, as the first word (jump instruction, needs + * to remain the same. + */ + memcpy(&header, buf, hdr_size); + /* + * Check to see if we have zero bytes (excluding first 4, which + * are the jump instruction) + */ + for (i = 1; i < hdr_size / 4; i++) { + if (((uint32_t *)buf)[i]) { + fprintf(stderr, + "ERROR: non-zero word found %x in location %d required for header, aborting\n", + ((uint32_t *)buf)[i], i); + exit(-1); + } + } + printf("Zero bytes found in header location, adding header.\n"); + + } else { + fprintf(stderr, "Unable to read from file %s\n", filename); + exit(-1); + } + + /* Read data bytes and generate CRC */ + lseek(fd, hdr_size, SEEK_SET); + + while ((len = read(fd, buf, BUF_SIZE)) > 0) { + data_crc = crc32(data_crc, buf, len); + data_len += len; + } + printf("CRC of data: 0x%x, length: %d\n", data_crc, data_len); + + /* Now create the new header */ + header.magic = htonl(BOOTLOADER_HEADER_MAGIC); + header.maj_rev = htons(BOOTLOADER_HEADER_CURRENT_MAJOR_REV); + header.min_rev = htons(BOOTLOADER_HEADER_CURRENT_MINOR_REV); + header.dlen = htonl(data_len); + header.dcrc = htonl(data_crc); + header.board_type = htons(board_type); + header.address = address; + if (failsafe_flag) + header.flags |= htonl(BL_HEADER_FLAG_FAILSAFE); + + printf("Stage 2 flag is %sset\n", stage2_flag ? "" : "not "); + printf("Stage 1 flag is %sset\n", stage_1_flag ? "" : "not "); + if (pciboot_flag) + header.image_type = htons(BL_HEADER_IMAGE_PCIBOOT); + else if (stage2_flag) + header.image_type = htons(BL_HEADER_IMAGE_STAGE2); + else if (stage_1_flag) + header.image_type = htons(BL_HEADER_IMAGE_STAGE1); + else if (env_flag) + header.image_type = htons(BL_HEADER_IMAGE_UBOOT_ENV); + else if (stage_1_5_flag || stage_1_flag) + header.image_type = htons(BL_HEADER_IMAGE_PRE_UBOOT); + else + header.image_type = htons(BL_HEADER_IMAGE_NOR); + + switch (ntohs(header.image_type)) { + case BL_HEADER_IMAGE_UNKNOWN: + type_str = "Unknown"; + break; + case BL_HEADER_IMAGE_STAGE1: + type_str = "Stage 1"; + break; + case BL_HEADER_IMAGE_STAGE2: + type_str = "Stage 2"; + break; + case BL_HEADER_IMAGE_PRE_UBOOT: + type_str = "Pre-U-Boot"; + break; + case BL_HEADER_IMAGE_STAGE3: + type_str = "Stage 3"; + break; + case BL_HEADER_IMAGE_NOR: + type_str = "NOR"; + break; + case BL_HEADER_IMAGE_PCIBOOT: + type_str = "PCI Boot"; + break; + case BL_HEADER_IMAGE_UBOOT_ENV: + type_str = "U-Boot Environment"; + break; + default: + if (ntohs(header.image_type) >= BL_HEADER_IMAGE_CUST_RESERVED_MIN && + ntohs(header.image_type) <= BL_HEADER_IMAGE_CUST_RESERVED_MAX) + type_str = "Customer Reserved"; + else + type_str = "Unsupported"; + } + printf("Header image type: %s\n", type_str); + header.hlen = htons(hdr_size); + + /* Now compute header CRC over all of the header excluding the CRC */ + header.hcrc = crc32(0, (void *)&header, 12); + header.hcrc = htonl(crc32(header.hcrc, ((void *)&(header)) + 16, + hdr_size - 16)); + + /* Seek to beginning of file */ + lseek(fd, 0, SEEK_SET); + + /* Write header to file */ + ret = write(fd, &header, hdr_size); + if (ret < 0) + perror("write"); + + close(fd); + + printf("Header CRC: 0x%x\n", ntohl(header.hcrc)); + return 0; +} |