diff options
| -rw-r--r-- | board/beagle/beagleplay/beagleplay.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 1c376dea372..2adb2517ef0 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -11,6 +11,8 @@ #include <fdt_support.h> #include <spl.h> +#include <asm/arch/hardware.h> + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -27,3 +29,38 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#ifdef CONFIG_SPL_BOARD_INIT + +/* + * Enable the 32k Crystal: needed for accurate 32k clock + * and external clock sources such as wlan 32k input clock + * supplied from the SoC to the wlan chip. + * + * The trim setup can be very highly board type specific choice of the crystal + * So this is done in the board file, though, in this case, no specific trim + * is necessary. + */ +static void crystal_32k_enable(void) +{ + /* Only mess with 32k at the start of boot from R5 */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * We have external 32k crystal, so lets enable it (0x0) + * and disable bypass (0x0) + */ + writel(0x0, MCU_CTRL_LFXOSC_CTRL); + + /* Add any crystal specific TRIM needed here.. */ + + /* Make sure to mux the SoC 32k from the crystal */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + } +} + +void spl_board_init(void) +{ + crystal_32k_enable(); +} +#endif |