diff options
35 files changed, 748 insertions, 244 deletions
@@ -599,7 +599,6 @@ config SYS_HAS_SRAM bool default y if TARGET_PIC32MZDASK default y if TARGET_DEVKIT8000 - default y if TARGET_TRICORDER help Enable this to allow support for the on board SRAM. SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. @@ -609,14 +608,12 @@ config SYS_SRAM_BASE hex default 0x80000000 if TARGET_PIC32MZDASK default 0x40200000 if TARGET_DEVKIT8000 - default 0x40200000 if TARGET_TRICORDER default 0x0 config SYS_SRAM_SIZE hex default 0x00080000 if TARGET_PIC32MZDASK default 0x10000 if TARGET_DEVKIT8000 - default 0x10000 if TARGET_TRICORDER default 0x0 config SYS_MONITOR_LEN diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index d481eadfeb0..9a5037deca2 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -129,3 +129,8 @@ reg = <0x4d>; }; }; + +&sgpio { + status = "okay"; + ngpios = <80>; +}; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 320d2e5340a..d677705fe85 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -255,6 +255,21 @@ interrupt-controller; }; + sgpio: sgpio@1e780200 { + compatible = "aspeed,ast2500-sgpio"; + reg = <0x1e780200 0x100>; + interrupts = <40>; + clocks = <&scu ASPEED_CLK_APB>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm_default>; + status = "disabled"; + }; + timer: timer@1e782000 { /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; @@ -1445,4 +1460,9 @@ function = "WDTRST2"; groups = "WDTRST2"; }; + + pinctrl_sgpm_default: sgpm_default { + function = "SGPM"; + groups = "SGPM"; + }; }; diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index 9aac0e26f28..570ba61965a 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -266,3 +266,13 @@ bootph-all; status = "okay"; }; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; +}; + +&sgpiom1 { + status = "okay"; + ngpios = <80>; +}; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 43db80edfe5..cb8ce8b6b6f 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -501,6 +501,36 @@ ngpios = <208>; }; + sgpiom0: sgpiom@1e780500 { + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780500 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scu ASPEED_CLK_APB2>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm1_default>; + status = "disabled"; + }; + + sgpiom1: sgpiom@1e780600 { + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780600 0x100>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scu ASPEED_CLK_APB2>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm2_default>; + status = "disabled"; + }; + gpio1: gpio@1e780800 { compatible = "aspeed,ast2600-gpio"; reg = <0x1e780800 0x800>; @@ -2167,4 +2197,14 @@ function = "PCIE1RC"; groups = "PCIE1RC"; }; + + pinctrl_sgpm1_default: sgpm1_default { + function = "SGPM1"; + groups = "SGPM1"; + }; + + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; }; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9eb30c2ade8..52f6c9b934d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -665,22 +665,6 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); -#ifdef CONFIG_SYS_NONCACHED_MEMORY -/** - * noncached_init() - Initialize non-cached memory region - * - * Initialize non-cached memory area. This memory region will be typically - * located right below the malloc() area and mapped uncached in the MMU. - * - * It is called during the generic post-relocation init sequence. - * - * Return: 0 if OK - */ -int noncached_init(void); - -phys_addr_t noncached_alloc(size_t size, size_t align); -#endif /* CONFIG_SYS_NONCACHED_MEMORY */ - #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h index a77538673f6..11a7384cec9 100644 --- a/arch/arm/include/asm/ti-common/ti-aemif.h +++ b/arch/arm/include/asm/ti-common/ti-aemif.h @@ -16,6 +16,7 @@ #define AEMIF_PRESERVE -1 struct aemif_config { + void *base; unsigned mode; unsigned select_strobe; unsigned extend_wait; diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 89a2ac209fc..00699c4c11a 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -286,20 +286,6 @@ static inline void instruction_hazard_barrier(void) /* 1MB granularity */ #define MMU_SECTION_SHIFT 20 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) - -/** - * noncached_init() - Initialize non-cached memory region - * - * Initialize non-cached memory area. This memory region will be typically - * located right below the malloc() area and be accessed from KSEG1. - * - * It is called during the generic post-relocation init sequence. - * - * Return: 0 if OK - */ -int noncached_init(void); - -phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_SYS_NONCACHED_MEMORY */ #endif /* _ASM_SYSTEM_H */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 48547719012..a92aa5cfc67 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -49,8 +49,10 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) - if (!(board_is_k2g_ice() || board_is_k2g_i1())) + if (!(board_is_k2g_ice() || board_is_k2g_i1())) { + aemif_configs->base = (void *)KS2_AEMIF_CNTRL_BASE; aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); + } #endif if (!(board_is_k2g_ice() || board_is_k2g_i1())) { diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 8eda521693d..3d5b6f9e2dc 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -73,7 +73,7 @@ static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags) long ret; ret = lmb_reserve_flags(addr, size, flags); - if (ret >= 0) { + if (!ret) { debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, (unsigned long long)size, flags); @@ -110,7 +110,7 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) for (i = 0; i < total; i++) { if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) continue; - boot_fdt_reserve_region(addr, size, LMB_NONE); + boot_fdt_reserve_region(addr, size, LMB_NOOVERWRITE); } /* process reserved-memory */ @@ -122,7 +122,7 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) ret = fdt_get_resource(fdt_blob, subnode, "reg", 0, &res); if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) { - flags = LMB_NONE; + flags = LMB_NOOVERWRITE; if (fdtdec_get_bool(fdt_blob, subnode, "no-map")) flags = LMB_NOMAP; diff --git a/cmd/Makefile b/cmd/Makefile index b4668eb73e5..d1f369deec0 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -127,13 +127,10 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o -ifdef CONFIG_CMD_NET -obj-$(CONFIG_NET) += net.o -obj-$(CONFIG_NET_LWIP) += net-lwip.o -obj-$(filter y,$(CONFIG_CMD_NET) $(CONFIG_CMD_NET_LWIP)) += net-common.o -lwip-includes := -I$(srctree)/lib/lwip/lwip/src/include -I$(srctree)/lib/lwip/u-boot -CFLAGS_net-lwip.o := $(lwip-includes) -CFLAGS_net-common.o := $(lwip-includes) +ifdef CONFIG_NET +obj-$(CONFIG_CMD_NET) += net.o net-common.o +else ifdef CONFIG_NET_LWIP +obj-$(CONFIG_CMD_NET) += net-lwip.o net-common.o endif obj-$(CONFIG_ENV_SUPPORT) += nvedit.o obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o diff --git a/cmd/fat.c b/cmd/fat.c index 1655e80e945..5b7484dc1af 100644 --- a/cmd/fat.c +++ b/cmd/fat.c @@ -14,7 +14,7 @@ #include <part.h> #include <asm/cache.h> -int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { return do_size(cmdtp, flag, argc, argv, FS_TYPE_FAT); } diff --git a/common/board_r.c b/common/board_r.c index 8a19817fa39..62228a723e1 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -32,6 +32,7 @@ #include <command.h> #include <console.h> #include <dm.h> +#include <efi_loader.h> #include <env.h> #include <env_internal.h> #include <fdtdec.h> @@ -63,10 +64,8 @@ #include <dm/ofnode.h> #include <linux/compiler.h> #include <linux/err.h> -#include <efi_loader.h> #include <wdt.h> #include <asm-generic/gpio.h> -#include <efi_loader.h> #include <relocate.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/disk/part_efi.c b/disk/part_efi.c index 7f04c6ecd69..bdcfcba5d51 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -216,7 +216,7 @@ int get_disk_guid(struct blk_desc *desc, char *guid) return 0; } -void part_print_efi(struct blk_desc *desc) +static void __maybe_unused part_print_efi(struct blk_desc *desc) { ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); gpt_entry *gpt_pte = NULL; @@ -258,8 +258,8 @@ void part_print_efi(struct blk_desc *desc) return; } -int part_get_info_efi(struct blk_desc *desc, int part, - struct disk_partition *info) +static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part, + struct disk_partition *info) { ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); gpt_entry *gpt_pte = NULL; diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index d05be273e7b..77acd766262 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -490,17 +490,17 @@ int of_read_u8(const struct device_node *np, const char *propname, u8 *outp) { const u8 *val; - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp)); if (IS_ERR(val)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return PTR_ERR(val); } *outp = *val; - dm_warn("%#x (%d)\n", *outp, *outp); + log_debug("%#x (%d)\n", *outp, *outp); return 0; } @@ -509,17 +509,17 @@ int of_read_u16(const struct device_node *np, const char *propname, u16 *outp) { const __be16 *val; - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp)); if (IS_ERR(val)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return PTR_ERR(val); } *outp = be16_to_cpup(val); - dm_warn("%#x (%d)\n", *outp, *outp); + log_debug("%#x (%d)\n", *outp, *outp); return 0; } @@ -534,14 +534,14 @@ int of_read_u32_array(const struct device_node *np, const char *propname, { const __be32 *val; - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); val = of_find_property_value_of_size(np, propname, sz * sizeof(*out_values)); if (IS_ERR(val)) return PTR_ERR(val); - dm_warn("size %zd\n", sz); + log_debug("size %zd\n", sz); while (sz--) *out_values++ = be32_to_cpup(val++); @@ -553,19 +553,19 @@ int of_read_u32_index(const struct device_node *np, const char *propname, { const __be32 *val; - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp) * (index + 1)); if (IS_ERR(val)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return PTR_ERR(val); } *outp = be32_to_cpup(val + index); - dm_warn("%#x (%d)\n", *outp, *outp); + log_debug("%#x (%d)\n", *outp, *outp); return 0; } @@ -575,20 +575,20 @@ int of_read_u64_index(const struct device_node *np, const char *propname, { const __be64 *val; - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp) * (index + 1)); if (IS_ERR(val)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return PTR_ERR(val); } *outp = be64_to_cpup(val + index); - dm_warn("%#llx (%lld)\n", (unsigned long long)*outp, - (unsigned long long)*outp); + log_debug("%#llx (%lld)\n", (unsigned long long)*outp, + (unsigned long long)*outp); return 0; } @@ -621,7 +621,7 @@ int of_property_match_string(const struct device_node *np, const char *propname, l = strnlen(p, end - p) + 1; if (p + l > end) return -EILSEQ; - dm_warn("comparing %s with %s\n", string, p); + log_debug("comparing %s with %s\n", string, p); if (strcmp(string, p) == 0) return i; /* Found it; return index */ } @@ -826,8 +826,8 @@ static void of_alias_add(struct alias_prop *ap, struct device_node *np, strncpy(ap->stem, stem, stem_len); ap->stem[stem_len] = 0; list_add_tail(&ap->link, &aliases_lookup); - dm_warn("adding DT alias:%s: stem=%s id=%i node=%s\n", - ap->alias, ap->stem, ap->id, of_node_full_name(np)); + log_debug("adding DT alias:%s: stem=%s id=%i node=%s\n", + ap->alias, ap->stem, ap->id, of_node_full_name(np)); } int of_alias_scan(void) diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c index 6c7b4c97d67..250dd175b55 100644 --- a/drivers/core/of_addr.c +++ b/drivers/core/of_addr.c @@ -27,7 +27,7 @@ static struct of_bus *of_match_bus(struct device_node *np); #ifdef DEBUG static void of_dump_addr(const char *s, const __be32 *addr, int na) { - dm_warn("%s", s); + pr_debug("%s", s); while (na--) pr_cont(" %08x", be32_to_cpu(*(addr++))); pr_cont("\n"); @@ -66,9 +66,9 @@ static u64 of_bus_default_map(__be32 *addr, const __be32 *range, s = of_read_number(range + na + pna, ns); da = of_read_number(addr, na); - dm_warn("default map, cp=%llx, s=%llx, da=%llx\n", - (unsigned long long)cp, (unsigned long long)s, - (unsigned long long)da); + log_debug("default map, cp=%llx, s=%llx, da=%llx\n", + (unsigned long long)cp, (unsigned long long)s, + (unsigned long long)da); if (da < cp || da >= (cp + s)) return OF_BAD_ADDR; @@ -200,11 +200,11 @@ static int of_translate_one(const struct device_node *parent, if (ranges == NULL || rlen == 0) { offset = of_read_number(addr, na); memset(addr, 0, pna * 4); - dm_warn("empty ranges; 1:1 translation\n"); + log_debug("empty ranges; 1:1 translation\n"); goto finish; } - dm_warn("walking ranges...\n"); + log_debug("walking ranges...\n"); /* Now walk through the ranges */ rlen /= 4; @@ -222,7 +222,7 @@ static int of_translate_one(const struct device_node *parent, finish: of_dump_addr("parent translation for:", addr, pna); - dm_warn("with offset: %llx\n", (unsigned long long)offset); + log_debug("with offset: %llx\n", (unsigned long long)offset); /* Translate it into parent bus space */ return pbus->translate(addr, offset, pna); @@ -247,7 +247,7 @@ static u64 __of_translate_address(const struct device_node *dev, int na, ns, pna, pns; u64 result = OF_BAD_ADDR; - dm_warn("** translation for device %s **\n", of_node_full_name(dev)); + log_debug("** translation for device %s **\n", of_node_full_name(dev)); /* Increase refcount at current level */ (void)of_node_get(dev); @@ -266,8 +266,8 @@ static u64 __of_translate_address(const struct device_node *dev, } memcpy(addr, in_addr, na * 4); - dm_warn("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns, - of_node_full_name(parent)); + log_debug("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns, + of_node_full_name(parent)); of_dump_addr("translating address:", addr, na); /* Translate */ @@ -279,7 +279,7 @@ static u64 __of_translate_address(const struct device_node *dev, /* If root, we have finished */ if (parent == NULL) { - dm_warn("reached root node\n"); + log_debug("reached root node\n"); result = of_read_number(addr, na); break; } @@ -293,8 +293,8 @@ static u64 __of_translate_address(const struct device_node *dev, break; } - dm_warn("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name, - pna, pns, of_node_full_name(parent)); + log_debug("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name, + pna, pns, of_node_full_name(parent)); /* Apply bus translation */ if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop)) diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c index bfc1e3441b1..f49187dfc1e 100644 --- a/drivers/core/of_extra.c +++ b/drivers/core/of_extra.c @@ -58,7 +58,7 @@ int ofnode_decode_region(ofnode node, const char *prop_name, fdt_addr_t *basep, const fdt_addr_t *cell; int len; - dm_warn("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name); + log_debug("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name); cell = ofnode_get_property(node, prop_name, &len); if (!cell || (len < sizeof(fdt_addr_t) * 2)) { dm_warn("cell=%p, len=%d\n", cell, len); @@ -67,8 +67,8 @@ int ofnode_decode_region(ofnode node, const char *prop_name, fdt_addr_t *basep, *basep = fdt_addr_to_cpu(*cell); *sizep = fdt_size_to_cpu(cell[1]); - dm_warn("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep, - (ulong)*sizep); + log_debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep, + (ulong)*sizep); return 0; } diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 48ae8ce830e..950895e72a9 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -315,7 +315,7 @@ int ofnode_read_u8(ofnode node, const char *propname, u8 *outp) int len; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u8(ofnode_to_np(node), propname, outp); @@ -323,11 +323,11 @@ int ofnode_read_u8(ofnode node, const char *propname, u8 *outp) cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname, &len); if (!cell || len < sizeof(*cell)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return -EINVAL; } *outp = *cell; - dm_warn("%#x (%u)\n", *outp, *outp); + log_debug("%#x (%u)\n", *outp, *outp); return 0; } @@ -346,7 +346,7 @@ int ofnode_read_u16(ofnode node, const char *propname, u16 *outp) int len; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u16(ofnode_to_np(node), propname, outp); @@ -354,11 +354,11 @@ int ofnode_read_u16(ofnode node, const char *propname, u16 *outp) cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname, &len); if (!cell || len < sizeof(*cell)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return -EINVAL; } *outp = be16_to_cpup(cell); - dm_warn("%#x (%u)\n", *outp, *outp); + log_debug("%#x (%u)\n", *outp, *outp); return 0; } @@ -391,7 +391,7 @@ int ofnode_read_u32_index(ofnode node, const char *propname, int index, int len; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u32_index(ofnode_to_np(node), propname, index, @@ -400,17 +400,17 @@ int ofnode_read_u32_index(ofnode node, const char *propname, int index, cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); if (!cell) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return -EINVAL; } if (len < (sizeof(int) * (index + 1))) { - dm_warn("(not large enough)\n"); + log_debug("(not large enough)\n"); return -EOVERFLOW; } *outp = fdt32_to_cpu(cell[index]); - dm_warn("%#x (%u)\n", *outp, *outp); + log_debug("%#x (%u)\n", *outp, *outp); return 0; } @@ -430,17 +430,17 @@ int ofnode_read_u64_index(ofnode node, const char *propname, int index, cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); if (!cell) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return -EINVAL; } if (len < (sizeof(u64) * (index + 1))) { - dm_warn("(not large enough)\n"); + log_debug("(not large enough)\n"); return -EOVERFLOW; } *outp = fdt64_to_cpu(cell[index]); - dm_warn("%#llx (%llu)\n", *outp, *outp); + log_debug("%#llx (%llu)\n", *outp, *outp); return 0; } @@ -468,7 +468,7 @@ int ofnode_read_u64(ofnode node, const char *propname, u64 *outp) int len; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u64(ofnode_to_np(node), propname, outp); @@ -476,12 +476,12 @@ int ofnode_read_u64(ofnode node, const char *propname, u64 *outp) cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); if (!cell || len < sizeof(*cell)) { - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return -EINVAL; } *outp = fdt64_to_cpu(cell[0]); - dm_warn("%#llx (%llu)\n", (unsigned long long)*outp, - (unsigned long long)*outp); + log_debug("%#llx (%llu)\n", (unsigned long long)*outp, + (unsigned long long)*outp); return 0; } @@ -499,11 +499,11 @@ bool ofnode_read_bool(ofnode node, const char *propname) bool prop; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); prop = ofnode_has_property(node, propname); - dm_warn("%s\n", prop ? "true" : "false"); + log_debug("%s\n", prop ? "true" : "false"); return prop ? true : false; } @@ -514,7 +514,7 @@ const void *ofnode_read_prop(ofnode node, const char *propname, int *sizep) int len; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) { struct property *prop = of_find_property( @@ -529,7 +529,7 @@ const void *ofnode_read_prop(ofnode node, const char *propname, int *sizep) propname, &len); } if (!val) { - dm_warn("<not found>\n"); + log_debug("<not found>\n"); if (sizep) *sizep = -FDT_ERR_NOTFOUND; return NULL; @@ -553,7 +553,7 @@ const char *ofnode_read_string(ofnode node, const char *propname) dm_warn("<invalid>\n"); return NULL; } - dm_warn("%s\n", str); + log_debug("%s\n", str); return str; } @@ -573,7 +573,7 @@ ofnode ofnode_find_subnode(ofnode node, const char *subnode_name) ofnode subnode; assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, subnode_name); + log_debug("%s: %s: ", __func__, subnode_name); if (ofnode_is_np(node)) { struct device_node *np = ofnode_to_np(node); @@ -588,8 +588,8 @@ ofnode ofnode_find_subnode(ofnode node, const char *subnode_name) ofnode_to_offset(node), subnode_name); subnode = noffset_to_ofnode(node, ooffset); } - dm_warn("%s\n", ofnode_valid(subnode) ? - ofnode_get_name(subnode) : "<none>"); + log_debug("%s\n", ofnode_valid(subnode) ? + ofnode_get_name(subnode) : "<none>"); return subnode; } @@ -598,7 +598,7 @@ int ofnode_read_u32_array(ofnode node, const char *propname, u32 *out_values, size_t sz) { assert(ofnode_valid(node)); - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) { return of_read_u32_array(ofnode_to_np(node), propname, @@ -1032,7 +1032,7 @@ ofnode ofnode_get_aliases_node(const char *name) if (!prop) return ofnode_null(); - dm_warn("%s: node_path: %s\n", __func__, prop); + log_debug("%s: node_path: %s\n", __func__, prop); return ofnode_path(prop); } @@ -1301,7 +1301,7 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, int len; int ret = -ENOENT; - dm_warn("%s: %s: ", __func__, propname); + log_debug("%s: %s: ", __func__, propname); /* * If we follow the pci bus bindings strictly, we should check @@ -1318,10 +1318,10 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, int i; for (i = 0; i < num; i++) { - dm_warn("pci address #%d: %08lx %08lx %08lx\n", i, - (ulong)fdt32_to_cpu(cell[0]), - (ulong)fdt32_to_cpu(cell[1]), - (ulong)fdt32_to_cpu(cell[2])); + log_debug("pci address #%d: %08lx %08lx %08lx\n", i, + (ulong)fdt32_to_cpu(cell[0]), + (ulong)fdt32_to_cpu(cell[1]), + (ulong)fdt32_to_cpu(cell[2])); if ((fdt32_to_cpu(*cell) & type) == type) { const unaligned_fdt64_t *ptr; @@ -1348,7 +1348,7 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, ret = -EINVAL; fail: - dm_warn("(not found)\n"); + log_debug("(not found)\n"); return ret; } @@ -1632,7 +1632,7 @@ int ofnode_write_string(ofnode node, const char *propname, const char *value) { assert(ofnode_valid(node)); - dm_warn("%s: %s = %s", __func__, propname, value); + log_debug("%s: %s = %s", __func__, propname, value); return ofnode_write_prop(node, propname, value, strlen(value) + 1, false); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1e5711663eb..92a8597420a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,13 @@ config ASPEED_GPIO is found in the AST2400, AST2500 and AST2600 BMC SoCs and provides access to over 200 GPIOs on each chip. +config ASPEED_SGPIO + bool "Aspeed SGPIO Driver" + help + Say yes here to support the Aspeed serial GPIO driver. The controller + is found in the AST2400, AST2500 and AST2600 BMC SoCs and + provides access to generate serial GPIO signal. + config ASPEED_G7_GPIO bool "Aspeed G7 GPIO Driver" help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fe81b6ba88b..3f882c065d8 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_$(XPL_)DM_PCA953X) += pca953x_gpio.o obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o +obj-$(CONFIG_ASPEED_SGPIO) += gpio-aspeed-sgpio.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c new file mode 100644 index 00000000000..4bbdec756f3 --- /dev/null +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + * Billy Tsai <billy_tsai@aspeedtech.com> + */ +#include <asm/io.h> +#include <asm/gpio.h> + +#include <config.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/sizes.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> + +#define ASPEED_SGPIO_CTRL 0x54 + +#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16) +#define ASPEED_SGPIO_ENABLE BIT(0) +#define ASPEED_SGPIO_PINS_SHIFT 6 + +struct aspeed_sgpio_priv { + void *base; + struct clk pclk; + const struct aspeed_sgpio_pdata *pdata; +}; + +struct aspeed_sgpio_pdata { + const u32 pin_mask; + const struct aspeed_sgpio_llops *llops; +}; + +struct aspeed_sgpio_bank { + u16 val_regs; + u16 rdata_reg; + u16 tolerance_regs; + const char names[4][3]; +}; + +/* + * Note: The "value" register returns the input value when the GPIO is + * configured as an input. + * + * The "rdata" register returns the output value when the GPIO is + * configured as an output. + */ +static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = { + { + .val_regs = 0x0000, + .rdata_reg = 0x0070, + .tolerance_regs = 0x0018, + .names = { "A", "B", "C", "D" }, + }, + { + .val_regs = 0x001C, + .rdata_reg = 0x0074, + .tolerance_regs = 0x0034, + .names = { "E", "F", "G", "H" }, + }, + { + .val_regs = 0x0038, + .rdata_reg = 0x0078, + .tolerance_regs = 0x0050, + .names = { "I", "J", "K", "L" }, + }, + { + .val_regs = 0x0090, + .rdata_reg = 0x007C, + .tolerance_regs = 0x00A8, + .names = { "M", "N", "O", "P" }, + }, +}; + +enum aspeed_sgpio_reg { + reg_val, + reg_rdata, + reg_tolerance, +}; + +struct aspeed_sgpio_llops { + void (*reg_bit_set)(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg, bool val); + bool (*reg_bit_get)(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg); +}; + +#define GPIO_VAL_VALUE 0x00 + +static void __iomem *bank_reg(struct aspeed_sgpio_priv *gpio, + const struct aspeed_sgpio_bank *bank, + const enum aspeed_sgpio_reg reg) +{ + switch (reg) { + case reg_val: + return gpio->base + bank->val_regs + GPIO_VAL_VALUE; + case reg_rdata: + return gpio->base + bank->rdata_reg; + case reg_tolerance: + return gpio->base + bank->tolerance_regs; + default: + /* acturally if code runs to here, it's an error case */ + BUG(); + } +} + +#define GPIO_BANK(x) ((x) >> 6) +#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0)) +#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1) + +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset) +{ + unsigned int bank; + + bank = GPIO_BANK(offset); + + WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); + return &aspeed_sgpio_banks[bank]; +} + +static bool aspeed_sgpio_is_input(unsigned int offset) +{ + return !(offset % 2); +} + +static int aspeed_sgpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct aspeed_sgpio_priv *gpio = dev_get_priv(dev); + enum aspeed_sgpio_reg reg; + + reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; + + return gpio->pdata->llops->reg_bit_get(gpio, offset, reg); +} + +static int aspeed_sgpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct aspeed_sgpio_priv *gpio = dev_get_priv(dev); + + if (aspeed_sgpio_is_input(offset)) + return -EINVAL; + + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, value); + + return 0; +} + +static int aspeed_sgpio_direction_input(struct udevice *dev, + unsigned int offset) +{ + return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; +} + +static int aspeed_sgpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags) +{ + int ret = -EOPNOTSUPP; + + if (flags & GPIOD_IS_OUT) { + bool value = flags & GPIOD_IS_OUT_ACTIVE; + + ret = aspeed_sgpio_set_value(dev, offset, value); + } else if (flags & GPIOD_IS_IN) { + ret = aspeed_sgpio_direction_input(dev, offset); + } + return ret; +} + +static int aspeed_sgpio_get_function(struct udevice *dev, unsigned int offset) +{ + return aspeed_sgpio_is_input(offset) ? GPIOF_INPUT : GPIOF_OUTPUT; +} + +static void aspeed_g4_reg_bit_set(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg, bool val) +{ + const struct aspeed_sgpio_bank *bank = to_bank(offset); + void __iomem *addr = bank_reg(gpio, bank, reg); + u32 temp; + + if (reg == reg_val) + /* Since this is an output, read the cached value from rdata, then update val. */ + temp = readl(bank_reg(gpio, bank, reg_rdata)); + else + temp = readl(addr); + + if (val) + temp |= GPIO_BIT(offset); + else + temp &= ~GPIO_BIT(offset); + + writel(temp, addr); +} + +static bool aspeed_g4_reg_bit_get(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg) +{ + const struct aspeed_sgpio_bank *bank = to_bank(offset); + void __iomem *addr = bank_reg(gpio, bank, reg); + + return !!(readl(addr) & GPIO_BIT(offset)); +} + +static const struct aspeed_sgpio_llops aspeed_g4_llops = { + .reg_bit_set = aspeed_g4_reg_bit_set, + .reg_bit_get = aspeed_g4_reg_bit_get, +}; + +static const struct dm_gpio_ops aspeed_sgpio_ops = { + .get_value = aspeed_sgpio_get_value, + .set_value = aspeed_sgpio_set_value, + .get_function = aspeed_sgpio_get_function, + .set_flags = aspeed_sgpio_set_flags, +}; + +static int aspeed_sgpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct aspeed_sgpio_priv *priv = dev_get_priv(dev); + u32 sgpio_freq, sgpio_clk_div, nr_gpios, gpio_cnt_regval, pin_mask; + ulong apb_freq; + int ret; + + priv->base = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev); + if (!priv->pdata) + return -EINVAL; + + pin_mask = priv->pdata->pin_mask; + + ret = ofnode_read_u32(dev_ofnode(dev), "ngpios", &nr_gpios); + if (ret < 0) { + dev_err(dev, "Could not read ngpios property\n"); + return -EINVAL; + } else if (nr_gpios % 8) { + dev_err(dev, "Number of GPIOs not multiple of 8: %d\n", + nr_gpios); + return -EINVAL; + } + + ret = ofnode_read_u32(dev_ofnode(dev), "bus-frequency", &sgpio_freq); + if (ret < 0) { + dev_err(dev, "Could not read bus-frequency property\n"); + return -EINVAL; + } + + ret = clk_get_by_index(dev, 0, &priv->pclk); + if (ret < 0) { + dev_err(dev, "get clock failed\n"); + return ret; + } + + apb_freq = clk_get_rate(&priv->pclk); + + /* + * From the datasheet, + * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1) + * period = 2 * (GPIO254[31:16] + 1) / PCLK + * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK) + * frequency = PCLK / (2 * (GPIO254[31:16] + 1)) + * frequency * 2 * (GPIO254[31:16] + 1) = PCLK + * GPIO254[31:16] = PCLK / (frequency * 2) - 1 + */ + if (sgpio_freq == 0) + return -EINVAL; + + sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; + + if (sgpio_clk_div > (1 << 16) - 1) + return -EINVAL; + + gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask; + writel(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval | + ASPEED_SGPIO_ENABLE, priv->base + ASPEED_SGPIO_CTRL); + + uc_priv->bank_name = dev->name; + uc_priv->gpio_count = nr_gpios * 2; + + return 0; +} + +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = { + .pin_mask = GENMASK(9, 6), + .llops = &aspeed_g4_llops, +}; + +static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = { + .pin_mask = GENMASK(10, 6), + .llops = &aspeed_g4_llops, +}; + +static const struct udevice_id aspeed_sgpio_ids[] = { + { .compatible = "aspeed,ast2400-sgpio", .data = (ulong)&ast2400_sgpio_pdata, }, + { .compatible = "aspeed,ast2500-sgpio", .data = (ulong)&ast2400_sgpio_pdata, }, + { .compatible = "aspeed,ast2600-sgpiom", .data = (ulong)&ast2600_sgpiom_pdata, }, +}; + +U_BOOT_DRIVER(sgpio_aspeed) = { + .name = "sgpio-aspeed", + .id = UCLASS_GPIO, + .of_match = aspeed_sgpio_ids, + .ops = &aspeed_sgpio_ops, + .probe = aspeed_sgpio_probe, + .priv_auto = sizeof(struct aspeed_sgpio_priv), +}; diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index d10edd27746..7c40f176987 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -39,7 +39,7 @@ config STM32_FMC2_EBI config TI_AEMIF tristate "Texas Instruments AEMIF driver" - depends on ARCH_KEYSTONE + depends on ARCH_KEYSTONE || ARCH_DAVINCI help This driver is for the AEMIF module available in Texas Instruments SoCs. AEMIF stands for Asynchronous External Memory Interface and diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 1cabf8ac9cd..fdc83e4e1c8 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -3,5 +3,5 @@ obj-$(CONFIG_MEMORY) += memory-uclass.o obj-$(CONFIG_SANDBOX_MEMORY) += memory-sandbox.o obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o obj-$(CONFIG_ATMEL_EBI) += atmel_ebi.o -obj-$(CONFIG_TI_AEMIF) += ti-aemif.o +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o ti-aemif-cs.o obj-$(CONFIG_TI_GPMC) += ti-gpmc.o diff --git a/drivers/memory/ti-aemif-cs.c b/drivers/memory/ti-aemif-cs.c new file mode 100644 index 00000000000..0fcfee6f0b4 --- /dev/null +++ b/drivers/memory/ti-aemif-cs.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DaVinci / Keystone2 : AEMIF's chip select configuration + * + */ +#include <asm/io.h> +#include <clk.h> +#include <div64.h> +#include <dm.h> +#include "ti-aemif-cs.h" + +#define AEMIF_CONFIG(cs) (0x10 + ((cs) * 4)) + +#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) +#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) +#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) +#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) +#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) +#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) +#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) +#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) +#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) +#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) + +#define SSTROBE_EN 0x1 +#define EW_EN 0x1 + +#define WSETUP_MAX 0xf +#define WSTROBE_MAX 0x3f +#define WHOLD_MAX 0x7 +#define RSETUP_MAX 0xf +#define RSTROBE_MAX 0x3f +#define RHOLD_MAX 0x7 +#define TA_MAX 0x3 + +#define WIDTH_8BITS 0x0 +#define WIDTH_16BITS 0x1 + +#define set_config_field(reg, field, val) \ + do { \ + if ((val) != -1) { \ + (reg) &= ~AEMIF_CFG_##field(0xffffffff); \ + (reg) |= AEMIF_CFG_##field((val)); \ + } \ + } while (0) + +void aemif_cs_configure(int cs, struct aemif_config *cfg) +{ + unsigned long tmp; + + tmp = __raw_readl(cfg->base + AEMIF_CONFIG(cs)); + + set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); + set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); + set_config_field(tmp, WR_SETUP, cfg->wr_setup); + set_config_field(tmp, WR_STROBE, cfg->wr_strobe); + set_config_field(tmp, WR_HOLD, cfg->wr_hold); + set_config_field(tmp, RD_SETUP, cfg->rd_setup); + set_config_field(tmp, RD_STROBE, cfg->rd_strobe); + set_config_field(tmp, RD_HOLD, cfg->rd_hold); + set_config_field(tmp, TURN_AROUND, cfg->turn_around); + set_config_field(tmp, WIDTH, cfg->width); + + __raw_writel(tmp, cfg->base + AEMIF_CONFIG(cs)); +} + +struct ti_aemif_cs { + void __iomem *base; + struct clk *clk; +}; + +static unsigned int aemif_calc_cfg(ulong rate, u64 timing_ns, u32 max_cfg) +{ + u64 result; + + if (!timing_ns) + return 0; + + result = DIV_ROUND_UP_ULL(timing_ns * rate, 1000000000ULL); + + if (result - 1 > max_cfg) + return max_cfg; + + return result - 1; +} + +static int aemif_cs_set_timings(struct udevice *dev) +{ + struct ti_aemif_cs *priv = dev_get_priv(dev); + ulong rate = clk_get_rate(priv->clk); + struct aemif_config cfg = {}; + u32 val; + u32 cs; + + if (dev_read_u32(dev, "ti,cs-chipselect", &cs)) + return -EINVAL; + +/* + * On DaVinci SoCs, chipselect is in range [2-5] + * On Keystone SoCs, chipselect is in range [0-3] + * The logic to access the configuration registers expects the CS to be in the + * Keystone range so a -2 offset is applied on DaVinci SoCs + */ + if (IS_ENABLED(CONFIG_ARCH_DAVINCI)) { + if (cs < 2 || cs > 5) + return -EINVAL; + cs -= 2; + } else if (IS_ENABLED(CONFIG_ARCH_KEYSTONE)) { + if (cs > 3) + return -EINVAL; + } + + if (dev_read_bool(dev, "ti,cs-select-strobe-mode")) + cfg.select_strobe = SSTROBE_EN; + + if (dev_read_bool(dev, "ti,cs-extended-wait-mode")) + cfg.extend_wait = EW_EN; + + val = dev_read_u32_default(dev, "ti,cs-write-setup-ns", U32_MAX); + cfg.wr_setup = aemif_calc_cfg(rate, val, WSETUP_MAX); + + val = dev_read_u32_default(dev, "ti,cs-write-strobe-ns", U32_MAX); + cfg.wr_strobe = aemif_calc_cfg(rate, val, WSTROBE_MAX); + + val = dev_read_u32_default(dev, "ti,cs-write-hold-ns", U32_MAX); + cfg.wr_hold = aemif_calc_cfg(rate, val, WHOLD_MAX); + + val = dev_read_u32_default(dev, "ti,cs-read-setup-ns", U32_MAX); + cfg.rd_setup = aemif_calc_cfg(rate, val, RSETUP_MAX); + + val = dev_read_u32_default(dev, "ti,cs-read-strobe-ns", U32_MAX); + cfg.rd_strobe = aemif_calc_cfg(rate, val, RSTROBE_MAX); + + val = dev_read_u32_default(dev, "ti,cs-read-hold-ns", U32_MAX); + cfg.rd_hold = aemif_calc_cfg(rate, val, RHOLD_MAX); + + val = dev_read_u32_default(dev, "ti,cs-min-turnaround-ns", U32_MAX); + cfg.turn_around = aemif_calc_cfg(rate, val, TA_MAX); + + val = dev_read_u32_default(dev, "ti,cs-bus-width", 8); + if (val == 16) + cfg.width = WIDTH_16BITS; + else + cfg.width = WIDTH_8BITS; + + cfg.base = priv->base; + aemif_cs_configure(cs, &cfg); + + return 0; +} + +static int aemif_cs_probe(struct udevice *dev) +{ + struct ti_aemif_cs *priv = dev_get_priv(dev); + struct udevice *aemif; + + aemif = dev_get_parent(dev); + if (!aemif) + return -ENODEV; + + priv->base = dev_read_addr_ptr(aemif); + if (!priv->base) + return -EINVAL; + + priv->clk = devm_clk_get(aemif, "aemif"); + if (IS_ERR(priv->clk)) + return -EINVAL; + + return aemif_cs_set_timings(dev); +} + +static const struct udevice_id aemif_cs_ids[] = { + { .compatible = "ti,da850-aemif-cs", }, + {}, +}; + +U_BOOT_DRIVER(ti_aemif_cs) = { + .name = "ti_aemif_cs", + .id = UCLASS_MEMORY, + .of_match = aemif_cs_ids, + .probe = aemif_cs_probe, + .priv_auto = sizeof(struct ti_aemif_cs), +}; diff --git a/drivers/memory/ti-aemif-cs.h b/drivers/memory/ti-aemif-cs.h new file mode 100644 index 00000000000..62e6c6ed1a7 --- /dev/null +++ b/drivers/memory/ti-aemif-cs.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#include <asm/ti-common/ti-aemif.h> + +void aemif_cs_configure(int cs, struct aemif_config *cfg); diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 29131f536a6..b26423c457a 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -7,61 +7,31 @@ */ #include <asm/arch/hardware.h> +#include <asm/io.h> #include <asm/ti-common/ti-aemif.h> +#include <dm.h> +#include "ti-aemif-cs.h" -#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4) -#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60) -#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c) -#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4)) - -#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) -#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) -#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~AEMIF_CFG_##field(0xffffffff); \ - reg |= AEMIF_CFG_##field(val); \ - } \ - } while (0) +#define AEMIF_WAITCYCLE_CONFIG (0x4) +#define AEMIF_NAND_CONTROL (0x60) +#define AEMIF_ONENAND_CONTROL (0x5c) static void aemif_configure(int cs, struct aemif_config *cfg) { unsigned long tmp; if (cfg->mode == AEMIF_MODE_NAND) { - tmp = __raw_readl(AEMIF_NAND_CONTROL); + tmp = __raw_readl(cfg->base + AEMIF_NAND_CONTROL); tmp |= (1 << cs); - __raw_writel(tmp, AEMIF_NAND_CONTROL); + __raw_writel(tmp, cfg->base + AEMIF_NAND_CONTROL); } else if (cfg->mode == AEMIF_MODE_ONENAND) { - tmp = __raw_readl(AEMIF_ONENAND_CONTROL); + tmp = __raw_readl(cfg->base + AEMIF_ONENAND_CONTROL); tmp |= (1 << cs); - __raw_writel(tmp, AEMIF_ONENAND_CONTROL); + __raw_writel(tmp, cfg->base + AEMIF_ONENAND_CONTROL); } - tmp = __raw_readl(AEMIF_CONFIG(cs)); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, AEMIF_CONFIG(cs)); + aemif_cs_configure(cs, cfg); } void aemif_init(int num_cs, struct aemif_config *config) @@ -76,3 +46,14 @@ void aemif_init(int num_cs, struct aemif_config *config) for (cs = 0; cs < num_cs; cs++) aemif_configure(cs, config + cs); } + +static const struct udevice_id aemif_ids[] = { + { .compatible = "ti,da850-aemif", }, + {}, +}; + +U_BOOT_DRIVER(ti_aemif) = { + .name = "ti_aemif", + .id = UCLASS_MEMORY, + .of_match = aemif_ids, +}; diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c index 9e7c347caf8..5ecd3f262b9 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c @@ -62,6 +62,7 @@ static const struct ast2500_group_config ast2500_groups[] = { { "SD2", 5, (1 << 1) }, { "FWSPICS1", 3, (1 << 24) }, { "SPI1CS1", 1, (1 << 15) }, + { "SGPM", 2, (1 << 11) | (1 << 10) | (1 << 9) | (1 << 8) }, }; static int ast2500_pinctrl_get_groups_count(struct udevice *dev) diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c index bc12590e583..f4bec6fe53c 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c @@ -454,6 +454,14 @@ static struct aspeed_sig_desc pwm15g1[] = { {0x41c, BIT(31), 0}, }; +static struct aspeed_sig_desc sgpm1[] = { + {0x414, GENMASK(27, 24), 0}, +}; + +static struct aspeed_sig_desc sgpm2[] = { + {0x6d0, GENMASK(7, 4), 0}, +}; + static const struct aspeed_group_config ast2600_groups[] = { { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, @@ -543,6 +551,8 @@ static const struct aspeed_group_config ast2600_groups[] = { { "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 }, { "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 }, { "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 }, + { "SGPM1", ARRAY_SIZE(sgpm1), sgpm1 }, + { "SGPM2", ARRAY_SIZE(sgpm2), sgpm2 }, }; static int ast2600_pinctrl_get_groups_count(struct udevice *dev) diff --git a/include/cpu_func.h b/include/cpu_func.h index 45e8a0a0577..7e81c4364a7 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -69,6 +69,20 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); +/** + * noncached_init() - Initialize non-cached memory region + * + * Initialize non-cached memory area. This memory region will be typically + * located right below the malloc() area and mapped uncached in the MMU. + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int noncached_init(void); +void noncached_set_region(void); + +phys_addr_t noncached_alloc(size_t size, size_t align); enum { /* Disable caches (else flush caches but leave them active) */ diff --git a/include/lmb.h b/include/lmb.h index e46abf400c6..2201d6f2b67 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -14,6 +14,9 @@ * Copyright (C) 2001 Peter Bergner, IBM Corp. */ +#define LMB_ALLOC_ANYWHERE 0 +#define LMB_ALIST_INITIAL_SIZE 4 + /** * enum lmb_flags - definition of memory region attributes * @LMB_NONE: no special request @@ -95,32 +98,6 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size); phys_size_t lmb_get_free_size(phys_addr_t addr); -/** - * lmb_alloc_flags() - Allocate memory region with specified attributes - * @size: Size of the region requested - * @align: Alignment of the memory region requested - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. - * - * Return: base address on success, 0 on error - */ -phys_addr_t lmb_alloc_flags(phys_size_t size, ulong align, uint flags); - -/** - * lmb_alloc_base_flags() - Allocate specified memory region with specified attributes - * @size: Size of the region requested - * @align: Alignment of the memory region requested - * @max_addr: Maximum address of the requested region - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. The max_addr parameter is used to specify the maximum address - * below which the requested region should be allocated. - * - * Return: base address on success, 0 on error - */ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, phys_addr_t max_addr, uint flags); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 3d742fa1915..9f3f0876997 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -472,7 +472,8 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, switch (type) { case EFI_ALLOCATE_ANY_PAGES: /* Any page */ - addr = (u64)lmb_alloc_flags(len, EFI_PAGE_SIZE, flags); + addr = (u64)lmb_alloc_base_flags(len, EFI_PAGE_SIZE, + LMB_ALLOC_ANYWHERE, flags); if (!addr) return EFI_OUT_OF_RESOURCES; break; diff --git a/lib/lmb.c b/lib/lmb.c index eec99c185ee..9423301cdbc 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -27,9 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; #define MAP_OP_FREE (u8)0x2 #define MAP_OP_ADD (u8)0x3 -#define LMB_ALLOC_ANYWHERE 0 -#define LMB_ALIST_INITIAL_SIZE 4 - static struct lmb lmb; static bool lmb_should_notify(enum lmb_flags flags) @@ -40,7 +37,7 @@ static bool lmb_should_notify(enum lmb_flags flags) static int __maybe_unused lmb_map_update_notify(phys_addr_t addr, phys_size_t size, - u8 op) + u8 op, enum lmb_flags flags) { u64 efi_addr; u64 pages; @@ -51,6 +48,9 @@ static int __maybe_unused lmb_map_update_notify(phys_addr_t addr, return -1; } + if (!lmb_should_notify(flags)) + return 0; + efi_addr = (uintptr_t)map_sysmem(addr, 0); pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); efi_addr &= ~EFI_PAGE_MASK; @@ -64,9 +64,9 @@ static int __maybe_unused lmb_map_update_notify(phys_addr_t addr, log_err("%s: LMB Map notify failure %lu\n", __func__, status & ~EFI_ERROR_MASK); return -1; - } else { - return 0; } + + return 0; } static void lmb_print_region_flags(enum lmb_flags flags) @@ -76,6 +76,7 @@ static void lmb_print_region_flags(enum lmb_flags flags) do { bitpos = flags ? fls(flags) - 1 : 0; + assert_noisy(bitpos < ARRAY_SIZE(flag_str)); printf("%s", flag_str[bitpos]); flags &= ~(1ull << bitpos); puts(flags ? ", " : "\n"); @@ -450,7 +451,7 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, } if (coalesced) - return coalesced; + return 0; if (alist_full(lmb_rgn_lst) && !alist_expand_by(lmb_rgn_lst, lmb_rgn_lst->alloc)) @@ -487,13 +488,10 @@ long lmb_add(phys_addr_t base, phys_size_t size) struct alist *lmb_rgn_lst = &lmb.free_mem; ret = lmb_add_region(lmb_rgn_lst, base, size); - if (ret < 0) + if (ret) return ret; - if (lmb_should_notify(LMB_NONE)) - return lmb_map_update_notify(base, size, MAP_OP_ADD); - - return 0; + return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE); } static long _lmb_free(phys_addr_t base, phys_size_t size) @@ -566,10 +564,7 @@ long lmb_free_flags(phys_addr_t base, phys_size_t size, if (ret < 0) return ret; - if (lmb_should_notify(flags)) - return lmb_map_update_notify(base, size, MAP_OP_FREE); - - return ret; + return lmb_map_update_notify(base, size, MAP_OP_FREE, flags); } long lmb_free(phys_addr_t base, phys_size_t size) @@ -583,13 +578,10 @@ long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags) struct alist *lmb_rgn_lst = &lmb.used_mem; ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags); - if (ret < 0) - return -1; - - if (lmb_should_notify(flags)) - return lmb_map_update_notify(base, size, MAP_OP_RESERVE); + if (ret) + return ret; - return ret; + return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags); } long lmb_reserve(phys_addr_t base, phys_size_t size) @@ -621,7 +613,6 @@ static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size) static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, enum lmb_flags flags) { - u8 op; int ret; long i, rgn; phys_addr_t base = 0; @@ -651,16 +642,14 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, if (rgn < 0) { /* This area isn't reserved, take it */ if (lmb_add_region_flags(&lmb.used_mem, base, - size, flags) < 0) + size, flags)) return 0; - if (lmb_should_notify(flags)) { - op = MAP_OP_RESERVE; - ret = lmb_map_update_notify(base, size, - op); - if (ret) - return ret; - } + ret = lmb_map_update_notify(base, size, + MAP_OP_RESERVE, + flags); + if (ret) + return ret; return base; } @@ -679,23 +668,6 @@ phys_addr_t lmb_alloc(phys_size_t size, ulong align) return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE); } -/** - * lmb_alloc_flags() - Allocate memory region with specified attributes - * @size: Size of the region requested - * @align: Alignment of the memory region requested - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. - * - * Return: base address on success, 0 on error - */ -phys_addr_t lmb_alloc_flags(phys_size_t size, ulong align, uint flags) -{ - return _lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, - flags); -} - phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr) { phys_addr_t alloc; diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 4b487c1d2cb..fe7a2165af2 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -25,16 +25,16 @@ obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o ifdef CONFIG_CMD_PCI obj-$(CONFIG_CMD_PCI_MPS) += pci_mps.o endif -obj-$(CONFIG_CMD_PINMUX) += pinmux.o -obj-$(CONFIG_CMD_PWM) += pwm.o obj-$(CONFIG_CMD_SEAMA) += seama.o ifdef CONFIG_SANDBOX obj-$(CONFIG_CMD_MBR) += mbr.o +obj-$(CONFIG_CMD_PINMUX) += pinmux.o +obj-$(CONFIG_CMD_PWM) += pwm.o obj-$(CONFIG_CMD_READ) += rw.o obj-$(CONFIG_CMD_SETEXPR) += setexpr.o +obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o ifdef CONFIG_NET obj-$(CONFIG_CMD_WGET) += wget.o endif obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o endif -obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o diff --git a/test/hush/Makefile b/test/hush/Makefile index a2d98815e50..4c3a0be857a 100644 --- a/test/hush/Makefile +++ b/test/hush/Makefile @@ -5,6 +5,8 @@ obj-y += cmd_ut_hush.o obj-y += if.o +ifdef CONFIG_CONSOLE_RECORD obj-y += dollar.o +endif obj-y += list.o obj-y += loop.o diff --git a/test/lib/lmb.c b/test/lib/lmb.c index b2c54fb4bcb..c917115b7b6 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -473,7 +473,7 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts) /* allocate overlapping region should return the coalesced count */ ret = lmb_reserve(0x40011000, 0x10000); - ut_asserteq(ret, 1); + ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000, 0, 0, 0, 0); /* allocate 3nd region */ @@ -748,13 +748,13 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* merge after */ ret = lmb_reserve_flags(0x40020000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, 1); + ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x20000, 0, 0, 0, 0); /* merge before */ ret = lmb_reserve_flags(0x40000000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, 1); + ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x30000, 0, 0, 0, 0); @@ -770,7 +770,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* test that old API use LMB_NONE */ ret = lmb_reserve(0x40040000, 0x10000); - ut_asserteq(ret, 1); + ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000, 0x40030000, 0x20000, 0, 0); @@ -789,7 +789,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* merge with 2 adjacent regions */ ret = lmb_reserve_flags(0x40060000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, 2); + ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40050000, 0x30000); |