diff options
452 files changed, 22235 insertions, 2367 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index cb787d32f14..01ab0c11f98 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -350,6 +350,8 @@ stages: sandbox64_clang: TEST_PY_BD: "sandbox64" OVERRIDE: "-O clang-18" + sandbox64_lwip: + TEST_PY_BD: "sandbox64_lwip" sandbox_spl: TEST_PY_BD: "sandbox_spl" TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5f3418e482f..145bdad83bf 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -290,6 +290,17 @@ sandbox64 with clang test.py: OVERRIDE: "-O clang-18" <<: *buildman_and_testpy_dfn +sandbox64_lwip test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" + tags: + - ${HOST} + variables: + TEST_PY_BD: "sandbox64_lwip" + <<: *buildman_and_testpy_dfn + sandbox_spl test.py: variables: TEST_PY_BD: "sandbox_spl" @@ -35,6 +35,7 @@ Bhupesh Sharma <bhupesh.linux@gmail.com> <bhupesh.sharma@linaro.org> Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> +Casey Connolly <casey.connolly@linaro.org> <caleb.connolly@linaro.org> Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com> Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com> Dirk Behme <dirk.behme@googlemail.com> @@ -95,7 +96,8 @@ This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@ Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com> Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> -Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> +Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com> +Paul Burton <paulburton@kernel.org> <paul.burton@mips.com> Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com> Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com> Prabhakar Kushwaha <prabhakar@freescale.com> @@ -454,6 +454,12 @@ config TOOLS_DEBUG it is possible to set breakpoints on particular lines, single-step debug through the source code, etc. +config SKIP_RELOCATE + bool "Skips relocation of U-Boot to end of RAM" + help + Skips relocation of U-Boot allowing for systems that have extremely + limited RAM to run U-Boot. + endif # EXPERT config PHYS_64BIT diff --git a/MAINTAINERS b/MAINTAINERS index a0b06e9ee24..ebbb0b6e8d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,7 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git F: drivers/ddr/altera/ F: arch/arm/mach-socfpga/ +F: configs/socfpga_agilex5_vab_defconfig F: drivers/sysreset/sysreset_socfpga* ARM AMLOGIC SOC SUPPORT @@ -1824,6 +1825,15 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci F: drivers/usb/host/xhci* F: include/usb/xhci.h +UTHREAD +M: Jerome Forissier <jerome.forissier@linaro.org> +S: Maintained +F: cmd/spawn.c +F: include/uthread.h +F: lib/uthread.c +F: test/cmd/spawn.c +F: test/lib/uthread.c + UUID testing M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> S: Maintained diff --git a/arch/Kconfig b/arch/Kconfig index 35b19f9bfdc..ea33d07c086 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -13,6 +13,13 @@ config HAVE_SETJMP help The architecture supports setjmp() and longjmp(). +config HAVE_INITJMP + bool + depends on HAVE_SETJMP + help + The architecture supports initjmp(), a non-standard companion to + setjmp() and longjmp(). + config SUPPORT_BIG_ENDIAN bool @@ -88,6 +95,7 @@ config ARC config ARM bool "ARM architecture" select HAVE_SETJMP + select HAVE_INITJMP select ARCH_SUPPORTS_LTO select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC if !ARM64 @@ -145,6 +153,7 @@ config RISCV bool "RISC-V architecture" select CREATE_ARCH_SYMLINK select HAVE_SETJMP + select HAVE_INITJMP select SUPPORT_ACPI select SUPPORT_LITTLE_ENDIAN select SUPPORT_OF_CONTROL @@ -171,6 +180,7 @@ config RISCV config SANDBOX bool "Sandbox" select HAVE_SETJMP + select HAVE_INITJMP select ARCH_SUPPORTS_LTO select BOARD_LATE_INIT select BZIP2 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d8c99d3ab19..df373d38a55 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1138,6 +1138,7 @@ config ARCH_SOCFPGA select DM_SERIAL select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64 select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL @@ -1171,8 +1172,6 @@ config ARCH_SOCFPGA imply SPL_DM_SPI_FLASH imply SPL_LIBDISK_SUPPORT imply SPL_MMC - imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI imply L2X0_CACHE diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c index 485294b88d0..5ba20efa33b 100644 --- a/arch/arm/cpu/armv8/spin_table.c +++ b/arch/arm/cpu/armv8/spin_table.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ +#include <errno.h> #include <linux/libfdt.h> #include <asm/spin_table.h> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 57d3dd98ffb..bcf3f4be36e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -303,6 +303,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb +dtb-$(CONFIG_TARGET_ZYNQ_BR) += \ + zynq-brcp1_2r.dtb \ + zynq-brcp1_1r.dtb \ + zynq-brcp1_1r_switch.dtb \ + zynq-brsmarc2.dtb \ + zynq-brcp150.dtb \ + zynq-brcp170.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi index 0316b73f3a5..a9297ca6503 100644 --- a/arch/arm/dts/an7581-u-boot.dtsi +++ b/arch/arm/dts/an7581-u-boot.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/reset/airoha,en7581-reset.h> + / { reserved-memory { #address-cells = <2>; @@ -11,6 +13,94 @@ reg = <0x0 0x80000000 0x0 0x40000>; }; }; + + clk25m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clkxtal"; + }; + + vmmc_3v3: regulator-vmmc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + chip_scu: syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + + eth: ethernet@1fb50000 { + compatible = "airoha,en7581-eth"; + reg = <0 0x1fb50000 0 0x2600>, + <0 0x1fb54000 0 0x2000>, + <0 0x1fb56000 0 0x2000>; + reg-names = "fe", "qdma0", "qdma1"; + + resets = <&scuclk EN7581_FE_RST>, + <&scuclk EN7581_FE_PDMA_RST>, + <&scuclk EN7581_FE_QDMA_RST>, + <&scuclk EN7581_DUAL_HSI0_MAC_RST>, + <&scuclk EN7581_DUAL_HSI1_MAC_RST>, + <&scuclk EN7581_HSI_MAC_RST>, + <&scuclk EN7581_XFP_MAC_RST>; + reset-names = "fe", "pdma", "qdma", + "hsi0-mac", "hsi1-mac", "hsi-mac", + "xfp-mac"; + }; + + switch: switch@1fb58000 { + compatible = "airoha,en7581-switch"; + reg = <0 0x1fb58000 0 0x8000>; + }; + + snfi: spi@1fa10000 { + compatible = "airoha,en7581-snand"; + reg = <0x0 0x1fa10000 0x0 0x140>, + <0x0 0x1fa11000 0x0 0x600>; + + clocks = <&scuclk EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <2>; + }; + }; + + mmc0: mmc@1fa0e000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0x0 0x1fa0e000 0x0 0x1000>, + <0x0 0x1fa0c000 0x0 0x60>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>; + clock-names = "source", "hclk"; + bus-width = <4>; + max-frequency = <52000000>; + vmmc-supply = <&vmmc_3v3>; + disable-wp; + cap-mmc-highspeed; + non-removable; + + assigned-clocks = <&scuclk EN7581_CLK_EMMC>; + assigned-clock-rates = <200000000>; + }; + }; +}; + +&scuclk { + compatible = "airoha,en7581-scu", "syscon"; }; &uart1 { diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 7f00014f13c..1c7f0fa6a49 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -319,6 +319,10 @@ pinctrl-0 = <&pinctrl_sdhci1>; }; +&usb0 { + status = "okay"; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi index 7dfbeb10c32..a70fc88317e 100644 --- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -100,6 +100,10 @@ bootph-all; }; +&sdhci0 { + bootph-all; +}; + &sdhci1 { bootph-all; }; diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi deleted file mode 100644 index 61b1433af91..00000000000 --- a/arch/arm/dts/px30-evb-u-boot.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * (C) Copyright 2020 Rockchip Electronics Co., Ltd - */ - -#include "px30-u-boot.dtsi" - -&rng { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index abc6b49e666..157d0ea6930 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -24,7 +24,6 @@ rng: rng@ff0b0000 { compatible = "rockchip,cryptov2-rng"; reg = <0x0 0xff0b0000 0x0 0x4000>; - status = "disabled"; }; }; diff --git a/arch/arm/dts/rk3328-generic-u-boot.dtsi b/arch/arm/dts/rk3328-generic-u-boot.dtsi new file mode 100644 index 00000000000..af890e912dd --- /dev/null +++ b/arch/arm/dts/rk3328-generic-u-boot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3328-u-boot.dtsi" + +&gpio0 { + /delete-property/ bootph-pre-ram; +}; + +&pcfg_pull_down_4ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&spi0m2_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0m2_cs0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0m2_rx { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0m2_tx { + bootph-pre-ram; + bootph-some-ram; +}; diff --git a/arch/arm/dts/rk3328-generic.dts b/arch/arm/dts/rk3328-generic.dts new file mode 100644 index 00000000000..af0da845716 --- /dev/null +++ b/arch/arm/dts/rk3328-generic.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3328 with eMMC, SD-card, SPI flash and USB OTG enabled + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Generic RK3328"; + compatible = "rockchip,rk3328"; + + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&sdmmc0m1_pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down_4ma>; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4 &sdmmc0m1_pin>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-generic-u-boot.dtsi b/arch/arm/dts/rk3399-generic-u-boot.dtsi new file mode 100644 index 00000000000..d977b642f8d --- /dev/null +++ b/arch/arm/dts/rk3399-generic-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3399-u-boot.dtsi" + +&spi1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3399-generic.dts b/arch/arm/dts/rk3399-generic.dts new file mode 100644 index 00000000000..c698f59c565 --- /dev/null +++ b/arch/arm/dts/rk3399-generic.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3399 with eMMC, SD-card, SPI flash and USB OTG enabled + */ + +/dts-v1/; +#include "rk3399.dtsi" + +/ { + model = "Generic RK3399"; + compatible = "rockchip,rk3399"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi new file mode 100644 index 00000000000..cc830b51456 --- /dev/null +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts new file mode 100644 index 00000000000..792d3e04a4c --- /dev/null +++ b/arch/arm/dts/rk3528-generic.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3528 with eMMC enabled + */ + +/dts-v1/; +#include "rk3528.dtsi" + +/ { + model = "Generic RK3528"; + compatible = "rockchip,rk3528"; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi new file mode 100644 index 00000000000..9c2f03a786c --- /dev/null +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi new file mode 100644 index 00000000000..eb6a55cd5c9 --- /dev/null +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rockchip-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + + dmc { + compatible = "rockchip,rk3528-dmc"; + bootph-all; + }; + + soc { + rng: rng@ffc50000 { + compatible = "rockchip,rkrng"; + reg = <0x0 0xffc50000 0x0 0x200>; + }; + + otp: nvmem@ffce0000 { + compatible = "rockchip,rk3528-otp"; + reg = <0x0 0xffce0000 0x0 0x4000>; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + rockchip,default-sample-phase = <90>; + status = "disabled"; + }; + }; +}; + +&cru { + bootph-all; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_strb { + bootph-pre-ram; + bootph-some-ram; +}; + +&gmac0_clk { + bootph-all; +}; + +&ioc_grf { + bootph-all; +}; + +&otp { + bootph-some-ram; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&sdhci { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&uart0 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart0m0_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 24a976cf7e2..87186973953 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -21,11 +21,6 @@ bootph-all; }; - rng: rng@fe388000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xfe388000 0x0 0x2000>; - }; - otp: nvmem@fe38c000 { compatible = "rockchip,rk3568-otp"; reg = <0x0 0xfe38c000 0x0 0x4000>; @@ -121,6 +116,10 @@ bootph-all; }; +&rng { + status = "okay"; +}; + &sdhci { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi new file mode 100644 index 00000000000..97240345ed4 --- /dev/null +++ b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Joshua Riek <jjriek@verizon.net> + * + */ + +#include "rk3576-u-boot.dtsi" + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi new file mode 100644 index 00000000000..be99a48a630 --- /dev/null +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + */ + +#include "rockchip-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + + dmc { + compatible = "rockchip,rk3576-dmc"; + bootph-all; + }; +}; + +&cru { + bootph-all; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_rstnout { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_strb { + bootph-pre-ram; + bootph-some-ram; +}; + +&ioc_grf { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up_drv_level_3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&pmu1_grf { + bootph-all; +}; + +&sdhci { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc0_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_pwren { + bootph-pre-ram; + bootph-some-ram; +}; + +&sys_grf { + bootph-all; +}; + +&uart0 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart0m0_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 8880d162b11..5eeb138f351 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -18,11 +18,6 @@ compatible = "rockchip,rk3588-dmc"; bootph-all; }; - - rng: rng@fe378000 { - compatible = "rockchip,trngv1"; - reg = <0x0 0xfe378000 0x0 0x200>; - }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 60de9140226..7631dfaa07f 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -70,6 +70,19 @@ #size-cells = <1>; ranges; + usb0: gadget@500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sam9x60-udc"; + reg = <0x500000 0x100000>, + <0xf803c000 0x400>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE 8>; + clock-names = "pclk", "hclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE 8>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 7b62fffb4ff..62191ff5d97 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -778,6 +778,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xf8048030 0x10>; clocks = <&h32ck>; + bootph-all; }; watchdog: watchdog@f8048040 { diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 8d6503dd091..874e71b5ca4 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -208,7 +208,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; @@ -218,7 +219,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; }; @@ -673,6 +675,17 @@ bootph-all; }; +&gpio1 { + /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */ + portb: gpio-controller@0{ + sdio_sel { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + &i2c0 { reset-names = "i2c"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index d7ab58267eb..8d7dc0945ab 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -25,34 +25,44 @@ /* * Both Memory base address and size default info is retrieved from HW setting. * Reconfiguration / Overwrite these info can be done with examples below. - */ - /* + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * * Example for memory size with 2GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>; * }; - */ - /* + * * Example for memory size with 8GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x1 0x80000000>; * }; - */ - /* + * * Example for memory size with 32GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x7 0x80000000>; * }; - */ - /* + * * Example for memory size with 512GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x7 0x80000000>, * <0x88 0x00000000 0x78 0x00000000>; * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; */ chosen { diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 15306db6002..93a8e0697d6 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -106,8 +106,13 @@ arch = "arm64"; os = "linux"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x86000000>; + entry = <0x86000000>; + #else load = <0x6000000>; entry = <0x6000000>; + #endif kernel_blob: blob-ext { filename = "Image"; }; diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi new file mode 100644 index 00000000000..3cc8ee8b810 --- /dev/null +++ b/arch/arm/dts/zynq-binman-brcp1.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 B&R Industrial Automation GmbH + */ + + #include <config.h> + +/ { + binman { + bootph-all; + filename = "flash.bin"; + pad-byte = <0xff>; + align-size = <16>; + align = <16>; + + blob@0 { + filename = "spl/boot.bin"; + offset = <0x0>; + }; + + fit { + description = "U-Boot BR Zynq boards"; + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + + images { + uboot { + description = "U-Boot BR Zynq"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + u-boot-nodtb { + }; + }; + + fdt-0 { + description = "DTB BR Zynq"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + u-boot-dtb { + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "BR Zynq"; + firmware = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + + blob-ext@0 { + filename = "blobs/cfg.img"; + offset = <0xC0000>; + size = <0x10000>; + optional; + }; + + blob-ext@5 { + filename = "blobs/cfg_opt.img"; + offset = <0xD0000>; + size = <0x10000>; + optional; + }; + + blob-ext@1 { + bootph-all; + filename = "blobs/bitstream.bit"; + offset = <0x100000>; + size = <0x200000>; + optional; + }; + + blob-ext@4 { + bootph-all; + filename = "blobs/bitstream_update.bit"; + offset = <0x400000>; + size = <0x200000>; + optional; + }; + + blob-ext@2 { + filename = "blobs/bootar.itb"; + offset = <0x900000>; + size = <0x600000>; + optional; + }; + + blob-ext@3 { + filename = "blobs/dtb.bin"; + offset = <0xF00000>; + size = <0x100000>; + optional; + }; + }; +}; diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi new file mode 100644 index 00000000000..ebaf42d9419 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP1 CPU"; + compatible = "br,cp1", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; + + pmic0: da9062@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + }; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi new file mode 100644 index 00000000000..1bfd5f27a7e --- /dev/null +++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; + +&rs232_en { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts new file mode 100644 index 00000000000..1b22d3793db --- /dev/null +++ b/arch/arm/dts/zynq-brcp150.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP150 CPU"; + compatible = "br,cp150", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + /* Put this pin active high to enable RS232 debug serial */ + rs232_en: rs232_enable { + compatible = "br,rs232-en"; + pin = <&gpio0 52 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_red { + label = "RDY_F_RED"; + gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user1_green { + label = "USER1_GREEN"; + gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user1_red { + label = "USER1_RED"; + gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user2_green { + label = "USER2_GREEN"; + gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user2_red { + label = "USER2_RED"; + gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <ðernet_phy>; + + ethernet_phy: emio-phy@2 { + reg = <2>; + max-speed = <100>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <16>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; + +/* Since the gem0 clock is configured EMIO this dummy entry is needed */ +&clkc { + clocks = <&clkc 16>; + clock-names = "gem0_emio_clk"; +}; diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi new file mode 100644 index 00000000000..ceea610ec17 --- /dev/null +++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts new file mode 100644 index 00000000000..eee19ce4c5f --- /dev/null +++ b/arch/arm/dts/zynq-brcp170.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP170 CPU"; + compatible = "br,cp170", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_red { + label = "RDY_F_RED"; + gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@58 { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x58>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi new file mode 100644 index 00000000000..58c4558ddff --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts new file mode 100644 index 00000000000..fd7ae5539c3 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi new file mode 120000 index 00000000000..5a31a05ea66 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi @@ -0,0 +1 @@ +zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts new file mode 100644 index 00000000000..a68d530bfe2 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "gmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +/* Since the gem0 clock is configured EMIO this dummy entry is needed */ +&clkc { + clocks = <&clkc 16>; + clock-names = "gem0_emio_clk"; +}; diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi new file mode 120000 index 00000000000..5a31a05ea66 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi @@ -0,0 +1 @@ +zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts new file mode 100644 index 00000000000..353d8a1235c --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_2r.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi new file mode 100644 index 00000000000..58c4558ddff --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts new file mode 100644 index 00000000000..32f873d1b4c --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRSMARC2 CPU"; + compatible = "br,smarc2", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + can0 = &can0; + can1 = &can1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + plk_se_red { + label = "PLK_S_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + + ethernet_phy0: ethernet-phy@1 { + ti,ledcr = <0x0480>; + ti,rgmii-rxclk-shift; + reg = <1>; + }; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy1>; + mac-address = [ 00 00 00 00 00 00 ]; + + ethernet_phy1: ethernet-phy@3{ + ti,ledcr = <0x0480>; + reg = <3>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + resetc: rststm@60 { /* reset controller */ + compatible = "bur,rststm"; + reg = <0x60>; + hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>; + cooling-min-state = <0>; + cooling-max-state = <1>; /* reset gets fired */ + #cooling-cells = <2>; /* min followed by max */ + }; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index 8307a2ef9dd..73eea372079 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -11,6 +11,10 @@ model = "Topic Miami Zynq Board"; compatible = "topic,miami", "xlnx,zynq-7000"; + config { + u-boot,spl-payload-offset = <0x20000>; + }; + aliases { serial0 = &uart0; spi0 = &qspi; @@ -35,6 +39,7 @@ status = "okay"; num-cs = <1>; flash@0 { + bootph-all; compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; reg = <0x0>; @@ -44,24 +49,12 @@ #address-cells = <1>; #size-cells = <1>; partition@0 { - label = "qspi-u-boot-spl"; - reg = <0x00000 0x10000>; - }; - partition@10000 { - label = "qspi-u-boot-img"; - reg = <0x10000 0x60000>; + label = "qspi-boot-bin"; + reg = <0x00000 0x100000>; }; - partition@70000 { - label = "qspi-device-tree"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "qspi-linux"; - reg = <0x80000 0x400000>; - }; - partition@480000 { + partition@100000 { label = "qspi-rootfs"; - reg = <0x480000 0x1b80000>; + reg = <0x100000 0>; }; }; }; @@ -74,6 +67,14 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + /* GPIO expander */ + gpioex: gpio@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-line-names = "USB_RESET", "VTT_SHDWN_N", "V_PRESENT", "DEBUG_PRESENT"; + gpio-controller; + #gpio-cells = <2>; + }; }; &clkc { diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index d5b63ef604b..a70123feead 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -2,13 +2,19 @@ /* * dts file for Xilinx ZynqMP SOMs (k24/k26) * - * (C) Copyright 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2024-2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ #include <config.h> +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) +#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#else +#define U_BOOT_ITB_FILENAME "u-boot.itb" +#endif + /dts-v1/; / { binman: binman { @@ -103,9 +109,9 @@ }; }; - /* u-boot.itb generation in a static way */ + /* Generation in a static way */ itb { - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; pad-byte = <0>; fit { @@ -227,7 +233,7 @@ }; blob-ext@2 { offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; }; fdtmap { }; diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts index 252c2ad552b..59c1388fb1d 100644 --- a/arch/arm/dts/zynqmp-binman.dts +++ b/arch/arm/dts/zynqmp-binman.dts @@ -2,22 +2,28 @@ /* * dts file for Xilinx ZynqMP platforms * - * (C) Copyright 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2024-2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ #include <config.h> +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) +#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#else +#define U_BOOT_ITB_FILENAME "u-boot.itb" +#endif + /dts-v1/; / { binman: binman { multiple-images; #ifdef CONFIG_SPL - /* u-boot.itb generation in a static way */ + /* Generation in a static way */ itb { - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; pad-byte = <0>; fit { @@ -196,7 +202,7 @@ }; blob-ext@2 { offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; }; fdtmap { }; diff --git a/arch/arm/include/asm/arch-rk3528/boot0.h b/arch/arm/include/asm/arch-rk3528/boot0.h new file mode 100644 index 00000000000..8ae46f25a87 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3528/boot0.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3528/gpio.h b/arch/arm/include/asm/arch-rk3528/gpio.h new file mode 100644 index 00000000000..5516e649b80 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3528/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3576/boot0.h b/arch/arm/include/asm/arch-rk3576/boot0.h new file mode 100644 index 00000000000..dea2b20252d --- /dev/null +++ b/arch/arm/include/asm/arch-rk3576/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3576/gpio.h b/arch/arm/include/asm/arch-rk3576/gpio.h new file mode 100644 index 00000000000..b48c0a5cf84 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3576/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 73e5283108b..3c204501f70 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -15,6 +15,13 @@ struct udevice; #define RKCLK_PLL_MODE_NORMAL 1 #define RKCLK_PLL_MODE_DEEP 2 +/* + * PLL flags + */ +#define ROCKCHIP_PLL_SYNC_RATE BIT(0) +/* normal mode only. now only for pll_rk3036, pll_rk3328 type */ +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) + enum { ROCKCHIP_SYSCON_NOC, ROCKCHIP_SYSCON_GRF, @@ -208,6 +215,26 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table, u32 reg_offset, u32 reg_number); /* + * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3528 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* + * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3576 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* * rk3588_reset_bind_lut() - Bind soft reset device as child of clock device * using dedicated RK3588 lookup table * diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h new file mode 100644 index 00000000000..b4020958a04 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h @@ -0,0 +1,388 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3528_H +#define _ASM_ARCH_CRU_RK3528_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define CPU_PVTPLL_HZ (1200 * MHz) +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (996 * MHz) +#define PPLL_HZ (1000 * MHz) + +/* RK3528 pll id */ +enum rk3528_pll_id { + APLL, + CPLL, + GPLL, + PPLL, + DPLL, + PLL_COUNT, +}; + +struct rk3528_clk_priv { + struct rk3528_cru *cru; + unsigned long ppll_hz; + unsigned long gpll_hz; + unsigned long cpll_hz; + unsigned long armclk_hz; + unsigned long armclk_enter_hz; + unsigned long armclk_init_hz; + bool sync_kernel; +}; + +struct rk3528_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000) + +struct rk3528_cru { + unsigned int apll_con[5]; + unsigned int reserved0014[3]; + unsigned int cpll_con[5]; + unsigned int reserved0034[11]; + unsigned int gpll_con[5]; + unsigned int reserved0074[51 + 32]; + unsigned int reserved01c0[48]; + unsigned int mode_con[1]; + unsigned int reserved0284[31]; + unsigned int clksel_con[91]; + unsigned int reserved046c[229]; + unsigned int gate_con[46]; + unsigned int reserved08b8[82]; + unsigned int softrst_con[47]; + unsigned int reserved0abc[81]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved0c14[6]; + unsigned int corewfi_con; + unsigned int reserved0c30[15604]; + + /* pmucru */ + unsigned int reserved10000[192]; + unsigned int pmuclksel_con[3]; + unsigned int reserved1030c[317]; + unsigned int pmugate_con[3]; + unsigned int reserved1080c[125]; + unsigned int pmusoftrst_con[3]; + unsigned int reserved10a08[7550 + 8191]; + + /* pciecru */ + unsigned int reserved20000[32]; + unsigned int ppll_con[5]; + unsigned int reserved20094[155]; + unsigned int pcieclksel_con[2]; + unsigned int reserved20308[318]; + unsigned int pciegate_con; +}; + +check_member(rk3528_cru, pciegate_con, 0x20800); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_PLL_CON(x) ((x) * 0x4) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) + +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 +#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT) +#define RK3528_DIV_PCLK_DBG_SHIFT 1 +#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT) + +enum { + /* CRU_CLKSEL_CON00 */ + CLK_MATRIX_50M_SRC_DIV_SHIFT = 2, + CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT, + CLK_MATRIX_100M_SRC_DIV_SHIFT = 7, + CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON01 */ + CLK_MATRIX_150M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT, + CLK_MATRIX_200M_SRC_DIV_SHIFT = 5, + CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_SEL_SHIFT = 15, + CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT, + + /* CRU_CLKSEL_CON02 */ + CLK_MATRIX_300M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT, + CLK_MATRIX_339M_SRC_DIV_SHIFT = 5, + CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT, + CLK_MATRIX_400M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON03 */ + CLK_MATRIX_500M_SRC_DIV_SHIFT = 6, + CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT, + CLK_MATRIX_500M_SRC_SEL_SHIFT = 11, + CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT, + + /* CRU_CLKSEL_CON04 */ + CLK_MATRIX_600M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U, + CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U, + CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U, + CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U, + + /* PMUCRU_CLKSEL_CON00 */ + CLK_I2C2_SEL_SHIFT = 0, + CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, + + /* PCIE_CRU_CLKSEL_CON01 */ + PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7, + PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT, + PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11, + PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON32 */ + DCLK_VOP_SRC0_SEL_SHIFT = 10, + DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT, + DCLK_VOP_SRC0_DIV_SHIFT = 2, + DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT, + + /* CRU_CLKSEL_CON33 */ + DCLK_VOP_SRC1_SEL_SHIFT = 8, + DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT, + DCLK_VOP_SRC1_DIV_SHIFT = 0, + DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT, + + /* CRU_CLKSEL_CON43 */ + CLK_CORE_CRYPTO_SEL_SHIFT = 14, + CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, + ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U, + ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT, + + /* CRU_CLKSEL_CON44 */ + CLK_PWM0_SEL_SHIFT = 6, + CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, + CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U, + CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U, + CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U, + CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U, + CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U, + CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U, + CLK_PKA_CRYPTO_SEL_SHIFT = 0, + CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, + CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, + CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, + + /* CRU_CLKSEL_CON60 */ + CLK_MATRIX_25M_SRC_DIV_SHIFT = 2, + CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT, + CLK_MATRIX_125M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON61 */ + SCLK_SFC_DIV_SHIFT = 6, + SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT, + SCLK_SFC_SEL_SHIFT = 12, + SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, + SCLK_SFC_SEL_CLK_GPLL_MUX = 0U, + SCLK_SFC_SEL_CLK_CPLL_MUX = 1U, + SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON62 */ + CCLK_SRC_EMMC_DIV_SHIFT = 0, + CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT, + CCLK_SRC_EMMC_SEL_SHIFT = 6, + CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_SHIFT = 8, + BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT, + + /* CRU_CLKSEL_CON63 */ + CLK_I2C3_SEL_SHIFT = 12, + CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, + CLK_I2C5_SEL_SHIFT = 14, + CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 10, + CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, + + /* CRU_CLKSEL_CON64 */ + CLK_I2C6_SEL_SHIFT = 0, + CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT, + + /* CRU_CLKSEL_CON74 */ + CLK_SARADC_DIV_SHIFT = 0, + CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, + CLK_TSADC_DIV_SHIFT = 3, + CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, + CLK_TSADC_TSEN_DIV_SHIFT = 8, + CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, + + /* CRU_CLKSEL_CON79 */ + CLK_I2C1_SEL_SHIFT = 9, + CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, + CLK_I2C0_SEL_SHIFT = 11, + CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, + CLK_SPI0_SEL_SHIFT = 13, + CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, + + /* CRU_CLKSEL_CON83 */ + ACLK_VOP_ROOT_DIV_SHIFT = 12, + ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT, + ACLK_VOP_ROOT_SEL_SHIFT = 15, + ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT, + + /* CRU_CLKSEL_CON84 */ + DCLK_VOP0_SEL_SHIFT = 0, + DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT, + DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U, + DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U, + ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U, + ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U, + DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U, + DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U, + + /* CRU_CLKSEL_CON85 */ + CLK_I2C4_SEL_SHIFT = 13, + CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, + CLK_I2C7_SEL_SHIFT = 0, + CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT, + CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U, + CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U, + CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U, + CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U, + CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U, + CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U, + CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U, + CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U, + CCLK_SRC_SDMMC0_DIV_SHIFT = 0, + CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT, + CCLK_SRC_SDMMC0_SEL_SHIFT = 6, + CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT, + CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U, + CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U, + CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U, + BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U, + BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U, + BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U, + BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U, + CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U, + CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U, + CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON04 */ + CLK_UART0_SRC_DIV_SHIFT = 5, + CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON05 */ + CLK_UART0_FRAC_DIV_SHIFT = 0, + CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON06 */ + SCLK_UART0_SRC_SEL_SHIFT = 0, + SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT, + CLK_UART1_SRC_DIV_SHIFT = 2, + CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON07 */ + CLK_UART1_FRAC_DIV_SHIFT = 0, + CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON08 */ + SCLK_UART1_SRC_SEL_SHIFT = 0, + SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT, + CLK_UART2_SRC_DIV_SHIFT = 2, + CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON09 */ + CLK_UART2_FRAC_DIV_SHIFT = 0, + CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON10 */ + SCLK_UART2_SRC_SEL_SHIFT = 0, + SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT, + CLK_UART3_SRC_DIV_SHIFT = 2, + CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON11 */ + CLK_UART3_FRAC_DIV_SHIFT = 0, + CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON12 */ + SCLK_UART3_SRC_SEL_SHIFT = 0, + SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT, + CLK_UART4_SRC_DIV_SHIFT = 2, + CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON13 */ + CLK_UART4_FRAC_DIV_SHIFT = 0, + CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON14 */ + SCLK_UART4_SRC_SEL_SHIFT = 0, + SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT, + CLK_UART5_SRC_DIV_SHIFT = 2, + CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON15 */ + CLK_UART5_FRAC_DIV_SHIFT = 0, + CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON16 */ + SCLK_UART5_SRC_SEL_SHIFT = 0, + SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT, + CLK_UART6_SRC_DIV_SHIFT = 2, + CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON17 */ + CLK_UART6_FRAC_DIV_SHIFT = 0, + CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON18 */ + SCLK_UART6_SRC_SEL_SHIFT = 0, + SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT, + CLK_UART7_SRC_DIV_SHIFT = 2, + CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON19 */ + CLK_UART7_FRAC_DIV_SHIFT = 0, + CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON20 */ + SCLK_UART7_SRC_SEL_SHIFT = 0, + SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT, + SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U, + SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U, + SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON60 */ + CLK_GMAC1_VPU_25M_DIV_SHIFT = 2, + CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT, + /* CRU_CLKSEL_CON66 */ + CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0, + CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT, + /* CRU_CLKSEL_CON84 */ + CLK_GMAC0_SRC_DIV_SHIFT = 3, + CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT, +}; + +#endif /* _ASM_ARCH_CRU_RK3528_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h new file mode 100644 index 00000000000..c51750beff2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h @@ -0,0 +1,491 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3576_H +#define _ASM_ARCH_CRU_RK3576_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define CPU_PVTPLL_HZ (1008 * MHz) +#define LPLL_HZ (816 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (1000 * MHz) +#define PPLL_HZ (1100 * MHz) +#define GMAC0_PTP_REFCLK_IN (24 * MHz) +#define GMAC1_PTP_REFCLK_IN (24 * MHz) + +/* RK3576 pll id */ +enum rk3576_pll_id { + BPLL, + LPLL, + DPLL, + CPLL, + GPLL, + VPLL, + AUPLL, + SPLL, + PPLL, + PLL_COUNT, +}; + +struct rk3576_clk_priv { + struct rk3576_cru *cru; + ulong ppll_hz; + ulong gpll_hz; + ulong cpll_hz; + ulong vpll_hz; + ulong aupll_hz; + ulong spll_hz; + ulong lpll_hz; + ulong bpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rk3576_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct rk3576_cru { + struct rk3576_pll pll[18]; + unsigned int reserved0[16];/* Address Offset: 0x0240 */ + unsigned int mode_con00;/* Address Offset: 0x0280 */ + unsigned int reserved1[31];/* Address Offset: 0x0284 */ + unsigned int clksel_con[181]; /* Address Offset: 0x0300 */ + unsigned int reserved2[139];/* Address Offset: 0x05d4 */ + unsigned int clkgate_con[80];/* Address Offset: 0x0800 */ + unsigned int reserved3[48];/* Address Offset: 0x0938 */ + unsigned int softrst_con[80];/* Address Offset: 0x0400 */ + unsigned int reserved4[48];/* Address Offset: 0x0b38 */ + unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ + unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ + unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ + unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ + unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ + unsigned int reserved5[43];/* Address Offset: 0x0c14 */ + unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */ + unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */ + unsigned int reserved8[32137];/* Address Offset: 0x0c38 */ + unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */ + unsigned int reserved9[298];/* Address Offset: 0x20358 */ + unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */ + unsigned int reserved10[32440];/* Address Offset: 0x20820 */ + unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */ +}; + +check_member(rk3576_cru, mode_con00, 0x280); +check_member(rk3576_cru, pmuclksel_con[1], 0x20304); + +struct pll_rate_table { + unsigned long rate; + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; +}; + +#define RK3576_PHP_CRU_BASE 0x8000 +#define RK3576_PMU_CRU_BASE 0x20000 +#define RK3576_BIGCORE_CRU_BASE 0x38000 +#define RK3576_LITCORE_CRU_BASE 0x40000 +#define RK3576_CCI_CRU_BASE 0x48000 +#define RK3576_CRU_BASE 0x27200000 +#define RK3576_SCRU_BASE 0x27214000 + +#define RK3576_BIGCORE_GRF_BASE 0x2600C000 +#define RK3576_LITCORE_GRF_BASE 0x2600E000 +#define RK3576_CCI_GRF_BASE 0x26010000 + +#define RK3576_PLL_CON(x) ((x) * 0x4) +#define RK3576_MODE_CON0 0x280 +#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) +#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) +#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) +#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3576_GLB_CNT_TH 0xc00 +#define RK3576_GLB_SRST_FST 0xc08 +#define RK3576_GLB_SRST_SND 0xc0c +#define RK3576_GLB_RST_CON 0xc10 +#define RK3576_GLB_RST_ST 0xc04 +#define RK3576_SDIO_CON0 0xC24 +#define RK3576_SDIO_CON1 0xC28 +#define RK3576_SDMMC_CON0 0xC30 +#define RK3576_SDMMC_CON1 0xC34 + +#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) +#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) +#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) + +#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) +#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) +#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) +#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) + +#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) +#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) +#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) + +#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) +#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) +#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) +#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) +#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) +#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) +#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) +#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) + +enum { + /* CRU_CLK_SEL8_CON */ + PCLK_TOP_SEL_SHIFT = 7, + PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, + PCLK_TOP_SEL_100M = 0, + PCLK_TOP_SEL_50M, + PCLK_TOP_SEL_OSC, + + /* CRU_CLK_SEL9_CON */ + ACLK_TOP_SEL_SHIFT = 5, + ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT, + ACLK_TOP_SEL_GPLL = 0, + ACLK_TOP_SEL_CPLL, + ACLK_TOP_SEL_AUPLL, + ACLK_TOP_DIV_SHIFT = 0, + ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT, + + /* CRU_CLK_SEL10_CON */ + ACLK_TOP_MID_SEL_SHIFT = 5, + ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT, + ACLK_TOP_MID_SEL_GPLL = 0, + ACLK_TOP_MID_SEL_CPLL, + ACLK_TOP_MID_DIV_SHIFT = 0, + ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT, + + /* CRU_CLK_SEL19_CON */ + HCLK_TOP_SEL_SHIFT = 2, + HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, + HCLK_TOP_SEL_200M = 0, + HCLK_TOP_SEL_100M, + HCLK_TOP_SEL_50M, + HCLK_TOP_SEL_OSC, + + /* CRU_CLK_SEL25_CON */ + CLK_UART_FRAC_NUMERATOR_SHIFT = 16, + CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, + CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL26_CON */ + CLK_UART_SRC_SEL_SHIFT = 0, + CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, + CLK_UART_SRC_SEL_GPLL = 0, + CLK_UART_SRC_SEL_CPLL, + CLK_UART_SRC_SEL_AUPLL, + CLK_UART_SRC_SEL_OSC, + + /* CRU_CLK_SEL27_CON */ + CLK_UART1_SRC_SEL_SHIFT = 13, + CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT, + CLK_UART1_SRC_DIV_SHIFT = 5, + CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL30_CON */ + CLK_GMAC0_125M_DIV_SHIFT = 10, + CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT, + + /* CRU_CLK_SEL31_CON */ + CLK_GMAC1_125M_DIV_SHIFT = 0, + CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT, + + /* CRU_CLK_SEL33_CON */ + REF_CLK0_OUT_PLL_SEL_SHIFT = 8, + REF_CLK0_OUT_PLL_SEL_MASK = 7 << REF_CLK0_OUT_PLL_SEL_SHIFT, + REF_CLK0_OUT_PLL_SEL_GPLL = 0, + REF_CLK0_OUT_PLL_SEL_CPLL, + REF_CLK0_OUT_PLL_SEL_SPLL, + REF_CLK0_OUT_PLL_SEL_AUPLL, + REF_CLK0_OUT_PLL_SEL_LPLL, + REF_CLK0_OUT_PLL_SEL_OSC, + REF_CLK0_OUT_PLL_DIV_SHIFT = 0, + REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, + + /* CRU_CLK_SEL55_CON */ + ACLK_BUS_ROOT_SEL_SHIFT = 9, + ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, + ACLK_BUS_ROOT_SEL_GPLL = 0, + ACLK_BUS_ROOT_SEL_CPLL, + ACLK_BUS_ROOT_DIV_SHIFT = 4, + ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, + PCLK_BUS_ROOT_SEL_SHIFT = 2, + PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT, + PCLK_BUS_ROOT_SEL_100M = 0, + PCLK_BUS_ROOT_SEL_50M, + PCLK_BUS_ROOT_SEL_OSC, + HCLK_BUS_ROOT_SEL_SHIFT = 0, + HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT, + HCLK_BUS_ROOT_SEL_200M = 0, + HCLK_BUS_ROOT_SEL_100M, + HCLK_BUS_ROOT_SEL_50M, + HCLK_BUS_ROOT_SEL_OSC, + + /* CRU_CLK_SEL57_CON */ + CLK_I2C8_SEL_SHIFT = 14, + CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT, + CLK_I2C7_SEL_SHIFT = 12, + CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT, + CLK_I2C6_SEL_SHIFT = 10, + CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT, + CLK_I2C5_SEL_SHIFT = 8, + CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT, + CLK_I2C4_SEL_SHIFT = 6, + CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT, + CLK_I2C3_SEL_SHIFT = 4, + CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT, + CLK_I2C2_SEL_SHIFT = 2, + CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT, + CLK_I2C1_SEL_SHIFT = 0, + CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT, + CLK_I2C_SEL_200M = 0, + CLK_I2C_SEL_100M, + CLK_I2C_SEL_50M, + CLK_I2C_SEL_OSC, + + /* CRU_CLK_SEL58_CON */ + CLK_SARADC_SEL_SHIFT = 12, + CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, + CLK_SARADC_SEL_GPLL = 0, + CLK_SARADC_SEL_OSC, + CLK_SARADC_DIV_SHIFT = 4, + CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, + CLK_I2C9_SEL_SHIFT = 0, + CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT, + + /* CRU_CLK_SEL59_CON */ + CLK_TSADC_DIV_SHIFT = 0, + CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, + + /* CRU_CLK_SEL60_CON */ + CLK_UART_SEL_SHIFT = 8, + CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT, + CLK_UART_SEL_GPLL = 0, + CLK_UART_SEL_CPLL, + CLK_UART_SEL_AUPLL, + CLK_UART_SEL_OSC, + CLK_UART_SEL_FRAC0, + CLK_UART_SEL_FRAC1, + CLK_UART_SEL_FRAC2, + CLK_UART_DIV_SHIFT = 0, + CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT, + + /* CRU_CLK_SEL70_CON */ + CLK_SPI0_SEL_SHIFT = 13, + CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, + CLK_SPI_SEL_200M = 0, + CLK_SPI_SEL_100M, + CLK_SPI_SEL_50M, + CLK_SPI_SEL_OSC, + + /* CRU_CLK_SEL71_CON */ + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, + CLK_SPI4_SEL_SHIFT = 6, + CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, + CLK_SPI3_SEL_SHIFT = 4, + CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, + CLK_SPI2_SEL_SHIFT = 2, + CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 0, + CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, + CLK_PWM_SEL_100M = 0, + CLK_PWM_SEL_50M, + CLK_PWM_SEL_OSC, + + /* CRU_CLK_SEL72_CON */ + DCLK_DECOM_SEL_SHIFT = 5, + DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, + DCLK_DECOM_SEL_GPLL = 0, + DCLK_DECOM_SEL_SPLL, + DCLK_DECOM_DIV_SHIFT = 0, + DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT, + + /* CRU_CLK_SEL74_CON */ + CLK_PWM2_SEL_SHIFT = 6, + CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, + + /* CRU_CLK_SEL89_CON */ + CCLK_EMMC_SEL_SHIFT = 14, + CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, + CCLK_EMMC_SEL_GPLL = 0, + CCLK_EMMC_SEL_CPLL, + CCLK_EMMC_SEL_OSC, + CCLK_EMMC_DIV_SHIFT = 8, + CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, + SCLK_FSPI_SEL_SHIFT = 6, + SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT, + SCLK_FSPI_SEL_GPLL = 0, + SCLK_FSPI_SEL_CPLL, + SCLK_FSPI_SEL_OSC, + SCLK_FSPI_DIV_SHIFT = 0, + SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT, + + /* CRU_CLK_SEL90_CON */ + BCLK_EMMC_SEL_SHIFT = 0, + BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_200M = 0, + BCLK_EMMC_SEL_100M, + BCLK_EMMC_SEL_50M, + BCLK_EMMC_SEL_OSC, + + /* CRU_CLK_SEL104_CON */ + CLK_GMAC1_PTP_SEL_SHIFT = 13, + CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT, + CLK_GMAC1_PTP_SEL_GPLL = 0, + CLK_GMAC1_PTP_SEL_CPLL, + CLK_GMAC1_PTP_SEL_REFIN, + CLK_GMAC1_PTP_DIV_SHIFT = 8, + CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT, + CCLK_SDIO_SRC_SEL_SHIFT = 6, + CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, + CCLK_SDIO_SRC_SEL_GPLL = 0, + CCLK_SDIO_SRC_SEL_CPLL, + CCLK_SDIO_SRC_SEL_OSC, + CCLK_SDIO_SRC_DIV_SHIFT = 0, + CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL105_CON */ + CCLK_SDMMC0_SRC_SEL_SHIFT = 13, + CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT, + CCLK_SDMMC0_SRC_SEL_GPLL = 0, + CCLK_SDMMC0_SRC_SEL_CPLL, + CCLK_SDMMC0_SRC_SEL_OSC, + CCLK_SDMMC0_SRC_DIV_SHIFT = 7, + CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT, + CLK_GMAC0_PTP_SEL_SHIFT = 5, + CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT, + CLK_GMAC0_PTP_SEL_GPLL = 0, + CLK_GMAC0_PTP_SEL_CPLL, + CLK_GMAC0_PTP_SEL_REFIN, + CLK_GMAC0_PTP_DIV_SHIFT = 0, + CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT, + + /* CRU_CLK_SEL123_CON */ + DCLK_EBC_SEL_SHIFT = 12, + DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT, + DCLK_EBC_SEL_GPLL = 0, + DCLK_EBC_SEL_CPLL, + DCLK_EBC_SEL_VPLL, + DCLK_EBC_SEL_AUPLL, + DCLK_EBC_SEL_LPLL, + DCLK_EBC_SEL_FRAC_SRC, + DCLK_EBC_SEL_OSC, + DCLK_EBC_DIV_SHIFT = 3, + DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT, + DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0, + DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT, + DCLK_EBC_FRAC_SRC_SEL_GPLL = 0, + DCLK_EBC_FRAC_SRC_SEL_CPLL, + DCLK_EBC_FRAC_SRC_SEL_VPLL, + DCLK_EBC_FRAC_SRC_SEL_AUPLL, + DCLK_EBC_FRAC_SRC_SEL_OSC, + + /* CRU_CLK_SEL144_CON */ + PCLK_VOP_ROOT_SEL_SHIFT = 12, + PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT, + PCLK_VOP_ROOT_SEL_100M = 0, + PCLK_VOP_ROOT_SEL_50M, + PCLK_VOP_ROOT_SEL_OSC, + HCLK_VOP_ROOT_SEL_SHIFT = 10, + HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, + HCLK_VOP_ROOT_SEL_200M = 0, + HCLK_VOP_ROOT_SEL_100M, + HCLK_VOP_ROOT_SEL_50M, + HCLK_VOP_ROOT_SEL_OSC, + ACLK_VOP_ROOT_SEL_SHIFT = 5, + ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, + ACLK_VOP_ROOT_SEL_GPLL = 0, + ACLK_VOP_ROOT_SEL_CPLL, + ACLK_VOP_ROOT_SEL_AUPLL, + ACLK_VOP_ROOT_SEL_SPLL, + ACLK_VOP_ROOT_SEL_LPLL, + ACLK_VOP_ROOT_DIV_SHIFT = 0, + ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, + + /* CRU_CLK_SEL145_CON */ + DCLK0_VOP_SRC_SEL_SHIFT = 8, + DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT, + DCLK_VOP_SRC_SEL_GPLL = 0, + DCLK_VOP_SRC_SEL_CPLL, + DCLK_VOP_SRC_SEL_VPLL, + DCLK_VOP_SRC_SEL_BPLL, + DCLK_VOP_SRC_SEL_LPLL, + DCLK0_VOP_SRC_DIV_SHIFT = 0, + DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL147_CON */ + DCLK2_VOP_SEL_SHIFT = 13, + DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT, + DCLK1_VOP_SEL_SHIFT = 12, + DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT, + DCLK0_VOP_SEL_SHIFT = 11, + DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT, + + /* CRU_CLK_SEL149_CON */ + ACLK_VO0_ROOT_SEL_SHIFT = 5, + ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT, + ACLK_VO0_ROOT_SEL_GPLL = 0, + ACLK_VO0_ROOT_SEL_CPLL, + ACLK_VO0_ROOT_SEL_LPLL, + ACLK_VO0_ROOT_SEL_BPLL, + ACLK_VO0_ROOT_DIV_SHIFT = 0, + ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT, + + /* CRU_CLK_SEL151_CON */ + CLK_DSIHOST0_SEL_SHIFT = 7, + CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT, + CLK_DSIHOST0_SEL_GPLL = 0, + CLK_DSIHOST0_SEL_CPLL, + CLK_DSIHOST0_SEL_SPLL, + CLK_DSIHOST0_SEL_VPLL, + CLK_DSIHOST0_SEL_BPLL, + CLK_DSIHOST0_SEL_LPLL, + CLK_DSIHOST0_DIV_SHIFT = 0, + CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT, + + /* PMUCRU_CLK_SEL5_CON */ + CLK_PMU1PWM_SEL_SHIFT = 2, + CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT, + + /* PMUCRU_CLK_SEL6_CON */ + CLK_I2C0_SEL_SHIFT = 7, + CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT, + + /* PMUCRU_CLK_SEL8_CON */ + CLK_UART1_SEL_SHIFT = 0, + CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT, + CLK_UART1_SEL_TOP = 0, + CLK_UART1_SEL_OSC, + + /* LITCRU_CLK_SEL0_CON */ + CLK_LITCORE_SEL_SHIFT = 12, + CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT, + CLK_LITCORE_SEL_LPLL = 0, + CLK_LITCORE_SEL_GPLL, + CLK_LITCORE_SEL_PVTPLL, + CLK_LITCORE_DIV_SHIFT = 7, + CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT, + +}; +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 849b3d0efb7..4c1b81483c9 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -428,11 +428,21 @@ void switch_to_hypervisor_ret(void); #define wfi() #endif +#if !defined(__thumb2__) +/* + * We will need to switch to ARM mode (.arm) for some instructions such as + * mrc p15 etc. + */ +#define asm_arm_or_thumb2(insn) asm volatile(".arm\n\t" insn) +#else +#define asm_arm_or_thumb2(insn) asm volatile(insn) +#endif + static inline unsigned long read_mpidr(void) { unsigned long val; - asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); + asm_arm_or_thumb2("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); return val; } @@ -461,11 +471,13 @@ static inline unsigned int get_cr(void) unsigned int val; if (is_hyp()) - asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) + asm_arm_or_thumb2("mrc p15, 4, %0, c1, c0, 0 @ get CR" + : "=r" (val) : : "cc"); else - asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) + asm_arm_or_thumb2("mrc p15, 0, %0, c1, c0, 0 @ get CR" + : "=r" (val) : : "cc"); return val; @@ -474,11 +486,11 @@ static inline unsigned int get_cr(void) static inline void set_cr(unsigned int val) { if (is_hyp()) - asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : + asm_arm_or_thumb2("mcr p15, 4, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); else - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : + asm_arm_or_thumb2("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); isb(); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index dd19bd3e4fb..ed6f15cb570 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <asm/cache.h> #include <asm/global_data.h> +#include <asm/system.h> #include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -126,8 +127,8 @@ void invalidate_l2_cache(void) { unsigned int val = 0; - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); + asm_arm_or_thumb2("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); isb(); } #endif diff --git a/arch/arm/lib/setjmp.S b/arch/arm/lib/setjmp.S index 2f041aeef01..81bef578719 100644 --- a/arch/arm/lib/setjmp.S +++ b/arch/arm/lib/setjmp.S @@ -34,3 +34,15 @@ ENTRY(longjmp) ret lr ENDPROC(longjmp) .popsection + +.pushsection .text.initjmp, "ax" +ENTRY(initjmp) + stm a1, {v1-v8} + /* a2: entry point address, a3: stack base, a4: stack size */ + add a3, a3, a4 + str a3, [a1, #32] /* where setjmp would save sp */ + str a2, [a1, #36] /* where setjmp would save lr */ + mov a1, #0 + ret lr +ENDPROC(initjmp) +.popsection diff --git a/arch/arm/lib/setjmp_aarch64.S b/arch/arm/lib/setjmp_aarch64.S index 1b8d000eb48..01193ccc426 100644 --- a/arch/arm/lib/setjmp_aarch64.S +++ b/arch/arm/lib/setjmp_aarch64.S @@ -39,3 +39,13 @@ ENTRY(longjmp) ret ENDPROC(longjmp) .popsection + +.pushsection .text.initjmp, "ax" +ENTRY(initjmp) + /* x1: entry point address, x2: stack base, x3: stack size */ + add x2, x2, x3 + stp x1, x2, [x0,#88] + mov x0, #0 + ret +ENDPROC(initjmp) +.popsection diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 52a21277227..28aee34f30b 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -216,6 +216,10 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) switch (bootmode) { case BOOT_DEVICE_EMMC: + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; return MMCSD_MODE_EMMCBOOT; case BOOT_DEVICE_MMC: if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 01e47deca94..6e3c66e5107 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -262,6 +262,10 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) switch (bootmode) { case BOOT_DEVICE_EMMC: + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; return MMCSD_MODE_EMMCBOOT; case BOOT_DEVICE_MMC: if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 361b0c0b31b..867ed173142 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -119,6 +119,9 @@ int fdt_fixup_reserved(void *blob, const char *name, { int nodeoffset, subnode; int ret; + struct fdt_memory carveout = { + .start = new_address, + }; /* Find reserved-memory */ nodeoffset = fdt_subnode_offset(blob, 0, "reserved-memory"); @@ -153,10 +156,7 @@ int fdt_fixup_reserved(void *blob, const char *name, } add_carveout: - struct fdt_memory carveout = { - .start = new_address, - .end = new_address + new_size - 1, - }; + carveout.end = new_address + new_size - 1; ret = fdtdec_add_reserved_memory(blob, name, &carveout, NULL, 0, NULL, FDTDEC_RESERVED_MEMORY_NO_MAP); if (ret < 0) diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c index 7f1b6d5b4e0..9d9a43c055b 100644 --- a/arch/arm/mach-k3/r5/am62ax/clk-data.c +++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c @@ -64,7 +64,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { @@ -200,6 +200,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -316,7 +317,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 20, "clkout0_ctrl_out0"), DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index 4b9892fe051..bc62d1d0d08 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -59,7 +59,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { @@ -193,6 +193,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -281,7 +282,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 36, "clkout0_ctrl_out0"), DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 0d97e7f5537..0b6604039f3 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -144,7 +144,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) int ret, size = 0, shut_cpu = 0; /* Release all the exclusive devices held by SPL before starting ATF */ - ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci); + ti_sci->ops.dev_ops.release_exclusive_devices(); ret = rproc_init(); if (ret) diff --git a/arch/arm/mach-k3/r5/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c index eb8436decbd..996ba2023fe 100644 --- a/arch/arm/mach-k3/r5/j7200/clk-data.c +++ b/arch/arm/mach-k3/r5/j7200/clk-data.c @@ -62,6 +62,16 @@ static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { "gluelogic_hfosc0_clkout", }; +static const char * const wkupusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv2_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_usart_mcupll_bypass_clksel_out0_parents[] = { + "wkupusart_clk_sel_out0", + "gluelogic_hfosc0_clkout", +}; + static const char * const main_pll_hfosc_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -345,6 +355,8 @@ static const struct clk_data clk_list[] = { CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("wkupusart_clk_sel_out0", wkupusart_clk_sel_out0_parents, 2, 0x43008064, 0, 1, 0), + CLK_MUX("wkup_usart_mcupll_bypass_clksel_out0", wkup_usart_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), @@ -543,6 +555,10 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(287, 2, "wkup_usart_mcupll_bypass_clksel_out0"), + DEV_CLK(287, 3, "wkupusart_clk_sel_out0"), + DEV_CLK(287, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(287, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), diff --git a/arch/arm/mach-k3/r5/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c index 8ce6796fd04..12a1386f9d1 100644 --- a/arch/arm/mach-k3/r5/j7200/dev-data.c +++ b/arch/arm/mach-k3/r5/j7200/dev-data.c @@ -66,6 +66,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(149, &soc_lpsc_list[12]), PSC_DEV(113, &soc_lpsc_list[13]), PSC_DEV(197, &soc_lpsc_list[13]), + PSC_DEV(287, &soc_lpsc_list[13]), PSC_DEV(103, &soc_lpsc_list[14]), PSC_DEV(104, &soc_lpsc_list[15]), PSC_DEV(102, &soc_lpsc_list[16]), diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 9eec786fe8f..dce190ddee2 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -85,8 +85,9 @@ struct mbus_win { static inline unsigned int readfr_extra_feature_reg(void) { unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" - (val)::"cc"); + + asm_arm_or_thumb2("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); return val; } @@ -96,8 +97,8 @@ static inline unsigned int readfr_extra_feature_reg(void) */ static inline void writefr_extra_feature_reg(unsigned int val) { - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" - (val):"cc"); + asm_arm_or_thumb2("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); isb(); } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index adb816982f8..b76510ab452 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -260,7 +260,7 @@ config DDR_LOG_LEVEL failure, RL, WL errors and other algorithm failure. At level 1, provides the D-Unit setup (SPD/Static configuration). At level 2, provides the windows margin as a results of DQS centeralization. - At level 3, rovides the windows margin of each DQ as a results of + At level 3, provides the windows margin of each DQ as a results of DQS centeralization. config DDR_IMMUTABLE_DEBUG_SETTINGS @@ -394,7 +394,6 @@ config MVEBU_SPL_BOOT_DEVICE_MMC imply SPL_LIBDISK_SUPPORT imply SPL_MMC select SUPPORT_EMMC_BOOT if SPL_MMC - select SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if SPL_MMC select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_SATA @@ -450,7 +449,7 @@ config MVEBU_EFUSE_VHV_GPIO string "VHV_Enable GPIO name for eFuse programming" depends on MVEBU_EFUSE && !ARMADA_3700 help - The eFuse programing (burning) phase requires supplying 1.8V to the + The eFuse programming (burning) phase requires supplying 1.8V to the device on the VHV power pin, while for normal operation the VHV power rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details. diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c6e347b8d9d..9210877a4a4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -15,7 +15,9 @@ config ROCKCHIP_PX30 select TPL_SERIAL select DEBUG_UART_BOARD_INIT imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR imply SPL_ROCKCHIP_COMMON_BOARD + imply TPL_LIBGENERIC_SUPPORT imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN help @@ -176,6 +178,8 @@ config ROCKCHIP_RK3308 imply OF_UPSTREAM imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL imply ROCKCHIP_OTP imply SPL_CLK imply SPL_DM_SEQ_ALIAS @@ -197,7 +201,6 @@ config ROCKCHIP_RK3328 select SUPPORT_SPL select SPL select SUPPORT_TPL - select TPL select TPL_HAVE_INIT_STACK if TPL imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN @@ -208,11 +211,14 @@ config ROCKCHIP_RK3328 imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS imply SPL_SERIAL + imply TPL if !ROCKCHIP_EXTERNAL_TPL + imply TPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. @@ -285,6 +291,7 @@ config ROCKCHIP_RK3399 imply PRE_CONSOLE_BUFFER imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_DM_SEQ_ALIAS @@ -312,6 +319,56 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3528 + bool "Support Rockchip RK3528" + select ARM64 + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply BOOTSTD_FULL + imply DM_RNG + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply OF_UPSTREAM + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ATF + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_RELOC_GD_ENV_ADDR + imply SYSRESET + imply SYSRESET_PSCI if SPL_ATF + help + The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53. + config ROCKCHIP_RK3568 bool "Support Rockchip RK3568" select ARM64 @@ -334,6 +391,8 @@ config ROCKCHIP_RK3568 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL imply ROCKCHIP_OTP imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT @@ -344,6 +403,56 @@ config ROCKCHIP_RK3568 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3576 + bool "Support Rockchip RK3576" + select ARM64 + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply BOOTSTD_FULL + imply DM_RNG + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply OF_UPSTREAM + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ATF + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_RELOC_GD_ENV_ADDR + imply SYSRESET + help + The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and + and quad-core Cortex-A53. + config ROCKCHIP_RK3588 bool "Support Rockchip RK3588" select ARM64 @@ -367,6 +476,8 @@ config ROCKCHIP_RK3588 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL imply ROCKCHIP_OTP imply SCMI_FIRMWARE imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF @@ -493,7 +604,6 @@ config TPL_ROCKCHIP_COMMON_BOARD config ROCKCHIP_EXTERNAL_TPL bool "Use external TPL binary" - default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588 help Some Rockchip SoCs require an external TPL to initialize DRAM. Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to @@ -603,17 +713,17 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE config ROCKCHIP_COMMON_STACK_ADDR bool depends on SPL_SHARES_INIT_SP_ADDR + depends on TPL || ROCKCHIP_EXTERNAL_TPL select HAS_CUSTOM_SYS_INIT_SP_ADDR imply SPL_LIBCOMMON_SUPPORT if SPL imply SPL_LIBGENERIC_SUPPORT if SPL imply SPL_ROCKCHIP_COMMON_BOARD if SPL imply SPL_SYS_MALLOC_F if SPL imply SPL_SYS_MALLOC_SIMPLE if SPL - imply TPL_LIBCOMMON_SUPPORT if TPL - imply TPL_LIBGENERIC_SUPPORT if TPL - imply TPL_ROCKCHIP_COMMON_BOARD if TPL - imply TPL_SYS_MALLOC_F if TPL - imply TPL_SYS_MALLOC_SIMPLE if TPL + imply TPL_LIBCOMMON_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD + imply TPL_LIBGENERIC_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SYS_MALLOC_F if TPL && TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SYS_MALLOC_SIMPLE if TPL && TPL_ROCKCHIP_COMMON_BOARD config NR_DRAM_BANKS default 10 if ROCKCHIP_EXTERNAL_TPL @@ -629,7 +739,9 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3528/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" +source "arch/arm/mach-rockchip/rk3576/Kconfig" source "arch/arm/mach-rockchip/rk3588/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" source "arch/arm/mach-rockchip/rv1126/Kconfig" @@ -637,40 +749,64 @@ source "arch/arm/mach-rockchip/rv1126/Kconfig" if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR config CUSTOM_SYS_INIT_SP_ADDR - default 0x3f00000 + default 0x63f00000 if SPL_TEXT_BASE = 0x60000000 + default 0x43f00000 if SPL_TEXT_BASE = 0x40000000 + default 0x03f00000 if SPL_TEXT_BASE = 0x00000000 config SYS_MALLOC_F_LEN - default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config SPL_SYS_MALLOC_F_LEN - default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TPL_SYS_MALLOC_F_LEN - default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x0800 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TEXT_BASE - default 0x00200000 if ARM64 + default 0x60200000 if SPL_TEXT_BASE = 0x60000000 + default 0x40200000 if SPL_TEXT_BASE = 0x40000000 + default 0x00200000 if SPL_TEXT_BASE = 0x00000000 config SPL_TEXT_BASE - default 0x0 if ARM64 + default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \ + ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \ + ROCKCHIP_RK322X || ROCKCHIP_RV1108 + default 0x40000000 if ROCKCHIP_RK3576 + default 0x00000000 config SPL_HAS_BSS_LINKER_SECTION default y if ARM64 config SPL_BSS_START_ADDR - default 0x3f80000 + default 0x63f80000 if SPL_TEXT_BASE = 0x60000000 + default 0x43f80000 if SPL_TEXT_BASE = 0x40000000 + default 0x03f80000 if SPL_TEXT_BASE = 0x00000000 config SPL_BSS_MAX_SIZE - default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000 + default 0x8000 if SPL_BSS_START_ADDR = 0x63f80000 + default 0x8000 if SPL_BSS_START_ADDR = 0x43f80000 + default 0x8000 if SPL_BSS_START_ADDR = 0x03f80000 config SPL_STACK_R - default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config SPL_STACK_R_ADDR - default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x63e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x43e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x03e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config SPL_STACK_R_MALLOC_SIMPLE_LEN - default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000 + default 0x200000 if SPL_STACK_R_ADDR = 0x63e00000 + default 0x200000 if SPL_STACK_R_ADDR = 0x43e00000 + default 0x200000 if SPL_STACK_R_ADDR = 0x03e00000 endif endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5e7edc99cdc..ae15a9f8a2d 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,7 +42,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ +obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/ obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index dcf9eb8144b..2b57b166894 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,9 +68,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "px30" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config SYS_MALLOC_F_LEN default 0x400 if !SPL_SHARES_INIT_SP_ADDR diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index fac966207a9..06572d545f6 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TEXT_BASE default 0x00600000 diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 03d97e1d746..6916f1a2444 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -3,15 +3,12 @@ *Copyright (c) 2018 Rockchip Electronics Co., Ltd */ #include <init.h> -#include <malloc.h> +#include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3308.h> #include <asm/arch-rockchip/hardware.h> -#include <asm/gpio.h> -#include <debug_uart.h> #include <linux/bitops.h> -#include <asm/armv8/mmu.h> static struct mm_region rk3308_mem_map[] = { { .virt = 0x0UL, @@ -38,22 +35,6 @@ struct mm_region *mem_map = rk3308_mem_map; #define SGRF_BASE 0xff2b0000 enum { - GPIO1C7_SHIFT = 8, - GPIO1C7_MASK = GENMASK(11, 8), - GPIO1C7_GPIO = 0, - GPIO1C7_UART1_RTSN, - GPIO1C7_UART2_TX_M0, - GPIO1C7_SPI2_MOSI, - GPIO1C7_JTAG_TMS, - - GPIO1C6_SHIFT = 4, - GPIO1C6_MASK = GENMASK(7, 4), - GPIO1C6_GPIO = 0, - GPIO1C6_UART1_CTSN, - GPIO1C6_UART2_RX_M0, - GPIO1C6_SPI2_MISO, - GPIO1C6_JTAG_TCLK, - GPIO4D3_SHIFT = 6, GPIO4D3_MASK = GENMASK(7, 6), GPIO4D3_GPIO = 0, @@ -116,60 +97,12 @@ enum { GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1, }; -enum { - IOVSEL3_CTRL_SHIFT = 8, - IOVSEL3_CTRL_MASK = BIT(8), - VCCIO3_SEL_BY_GPIO = 0, - VCCIO3_SEL_BY_IOVSEL3, - - IOVSEL3_SHIFT = 3, - IOVSEL3_MASK = BIT(3), - VCCIO3_3V3 = 0, - VCCIO3_1V8, -}; - -/* - * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc - * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults - * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware, - * then we can switch to io_vsel3 after system power on, and release GPIO0_A4 - * for other usage. - */ - -#define GPIO0_A4 4 - const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000", [BROM_BOOTSOURCE_SPINOR] = "/spi@ff4c0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff480000", }; -int rk_board_init(void) -{ - static struct rk3308_grf * const grf = (void *)GRF_BASE; - u32 val; - int ret; - - ret = gpio_request(GPIO0_A4, "gpio0_a4"); - if (ret < 0) { - printf("request for gpio0_a4 failed:%d\n", ret); - return 0; - } - - gpio_direction_input(GPIO0_A4); - - if (gpio_get_value(GPIO0_A4)) - val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | - VCCIO3_1V8 << IOVSEL3_SHIFT; - else - val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | - VCCIO3_3V3 << IOVSEL3_SHIFT; - rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val); - - gpio_free(GPIO0_A4); - return 0; -} - #ifdef CONFIG_DEBUG_UART_BOARD_INIT __weak void board_debug_uart_init(void) { diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 70770da5fdf..ec1dae8d413 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,9 +21,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3328" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 500cfcd87af..b2430207ee9 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -143,9 +143,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3399" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig new file mode 100644 index 00000000000..993b2dd274e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/Kconfig @@ -0,0 +1,15 @@ +if ROCKCHIP_RK3528 + +config ROCKCHIP_BOOT_MODE_REG + default 0xff370200 + +config ROCKCHIP_STIMER_BASE + default 0xff620000 + +config SYS_SOC + default "rk3528" + +config SYS_CONFIG_NAME + default "rk3528_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS new file mode 100644 index 00000000000..f343f71cf7f --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS @@ -0,0 +1,11 @@ +GENERIC-RK3528 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3528-generic* +F: configs/generic-rk3528_defconfig + +RADXA-E20C +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3528-radxa-e20c* +F: configs/radxa-e20c-rk3528_defconfig diff --git a/arch/arm/mach-rockchip/rk3528/Makefile b/arch/arm/mach-rockchip/rk3528/Makefile new file mode 100644 index 00000000000..f0c18cd39d2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += rk3528.o +obj-y += clk_rk3528.o +obj-y += syscon_rk3528.o diff --git a/arch/arm/mach-rockchip/rk3528/clk_rk3528.c b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c new file mode 100644 index 00000000000..6e77f11cbec --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <asm/arch-rockchip/cru_rk3528.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3528_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return RK3528_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c new file mode 100644 index 00000000000..4892ff6ba9d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <misc.h> +#include <asm/armv8/mmu.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> + +#define FIREWALL_DDR_BASE 0xff2e0000 +#define FW_DDR_MST6_REG 0x58 +#define FW_DDR_MST7_REG 0x5c +#define FW_DDR_MST14_REG 0x78 +#define FW_DDR_MST16_REG 0x80 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000", +}; + +static struct mm_region rk3528_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xfc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xfc000000UL, + .phys = 0xfc000000UL, + .size = 0x04000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3528_mem_map; + +void board_debug_uart_init(void) +{ +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Set the emmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG); + writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG); + + /* Set the fspi to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG); + writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG); + + /* Set the sdmmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG); + writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG); + + /* Set the usb to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + + return 0; +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +#define RK3528_OTP_CPU_CODE_OFFSET 0x02 +#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET 0x28 + +int checkboard(void) +{ + u8 cpu_code[2], chip_type; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x28 */ + ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1); + if (ret < 0) { + log_debug("Could not read chip type, ret=%d\n", ret); + return 0; + } + + suffix[0] = chip_type != 0x1 ? 'A' : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c new file mode 100644 index 00000000000..4a32a5f732e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3528_syscon_ids[] = { + { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3528_syscon) = { + .name = "rockchip_rk3528_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3528_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index ce327ed6f9e..01b53a47ddb 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -5,7 +5,6 @@ choice config TARGET_EVB_RK3568 bool "RK3568 evaluation board" - select BOARD_LATE_INIT help RK3568 EVB is a evaluation board for Rockchp RK3568. @@ -71,9 +70,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TEXT_BASE default 0x00a00000 @@ -87,4 +83,7 @@ source "board/qnap/ts433/Kconfig" source "board/radxa/zero3-rk3566/Kconfig" source "board/xunlong/orangepi-3b-rk3566/Kconfig" +config SYS_CONFIG_NAME + default "rk3568_common" + endif diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig new file mode 100644 index 00000000000..f347caf8904 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/Kconfig @@ -0,0 +1,23 @@ +if ROCKCHIP_RK3576 + +config TARGET_ROC_PC_RK3576 + bool "Firefly ROC-RK3576-PC" + help + ROC-RK3576-PC is a single board computer from Firefly + using the Rockchip RK3576. + +config ROCKCHIP_BOOT_MODE_REG + default 0x26024040 + +config ROCKCHIP_STIMER_BASE + default 0x27400000 + +config SYS_SOC + default "rk3576" + +source board/firefly/roc-pc-rk3576/Kconfig + +config SYS_CONFIG_NAME + default "rk3576_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3576/Makefile b/arch/arm/mach-rockchip/rk3576/Makefile new file mode 100644 index 00000000000..cbc58257deb --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2023 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3576.o +obj-y += clk_rk3576.o +obj-y += syscon_rk3576.o diff --git a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c new file mode 100644 index 00000000000..edda1afd0bd --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2020 Rockchip Electronics Co., Ltd. + */ + +#include <dm.h> +#include <asm/arch-rockchip/cru_rk3576.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3576_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return (void *)RK3576_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c new file mode 100644 index 00000000000..ba5c94b4b3d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + */ + +#include <asm/armv8/mmu.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> + +#define SYS_GRF_BASE 0x2600A000 +#define SYS_GRF_SOC_CON2 0x0008 +#define SYS_GRF_SOC_CON7 0x001c +#define SYS_GRF_SOC_CON11 0x002c +#define SYS_GRF_SOC_CON12 0x0030 + +#define GPIO0_IOC_BASE 0x26040000 +#define GPIO0B_PULL_L 0x0024 +#define GPIO0B_IE_L 0x002C + +#define SYS_SGRF_BASE 0x26004000 +#define SYS_SGRF_SOC_CON14 0x0058 +#define SYS_SGRF_SOC_CON15 0x005C +#define SYS_SGRF_SOC_CON20 0x0070 + +#define FW_SYS_SGRF_BASE 0x26005000 +#define SGRF_DOMAIN_CON1 0x4 +#define SGRF_DOMAIN_CON2 0x8 +#define SGRF_DOMAIN_CON3 0xc +#define SGRF_DOMAIN_CON4 0x10 +#define SGRF_DOMAIN_CON5 0x14 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", +}; + +static struct mm_region rk3576_mem_map[] = { + { + /* I/O area */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0xb080000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PMU_SRAM, CBUF, SYSTEM_SRAM */ + .virt = 0x3fe70000UL, + .phys = 0x3fe70000UL, + .size = 0x190000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* MSCH_DDR_PORT */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* PCIe 0+1 */ + .virt = 0x900000000UL, + .phys = 0x900000000UL, + .size = 0x100800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3576_mem_map; + +void board_debug_uart_init(void) +{ +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Set the emmc to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); + writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); + + /* Set the sdmmc0 to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5); + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5); + + /* Set the UFS to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3); + writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3); + + /* Set the fspi0 and fspi1 to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4); + writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4); + + /* Set the decom to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1); + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1); + + /* + * Set the GPIO0B0~B3 pull up and input enable. + * Keep consistent with other IO. + */ + writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L); + writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L); + + /* + * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0, + * keep consistent with other pwm. + */ + writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2); + + /* Enable noc slave response timeout */ + writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11); + writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12); + + /* + * Enable cci channels for below module AXI R/W + * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3) + */ + writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c new file mode 100644 index 00000000000..0dbf8f8d9c0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2023 Rockchip Electronics Co., Ltd + */ + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3576_syscon_ids[] = { + { .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3576_syscon) = { + .name = "rockchip_rk3576_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3576_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 155b8f00ca2..4e7942ada87 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -2,13 +2,11 @@ if ROCKCHIP_RK3588 config TARGET_EVB_RK3588 bool "Rockchip EVB1 v10" - select BOARD_LATE_INIT help RK3588 EVB is a evaluation board for Rockchp RK3588. config TARGET_CM3588_NAS_RK3588 bool "FriendlyElec CM3588 NAS" - select BOARD_LATE_INIT help The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. @@ -31,7 +29,6 @@ config TARGET_CM3588_NAS_RK3588 config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" - select BOARD_LATE_INIT help GeenBook is a notebook based on Rockchip RK3588, and works as a carrier board connect with CM5 SOM. @@ -49,7 +46,6 @@ config TARGET_GENBOOK_CM5_RK3588 config TARGET_JAGUAR_RK3588 bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" - select BOARD_LATE_INIT help The SBC-RK3588-AMR is a Single Board Computer designed by Theobroma Systems for autonomous mobile robots. @@ -76,7 +72,6 @@ config TARGET_JAGUAR_RK3588 config TARGET_KHADAS_EDGE2_RK3588 bool "Khadas Edge2 RK3588 board" - select BOARD_LATE_INIT help Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer) by Khadas. @@ -98,7 +93,6 @@ config TARGET_KHADAS_EDGE2_RK3588 config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" - select BOARD_LATE_INIT help The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec. @@ -143,7 +137,6 @@ config TARGET_NANOPCT6_RK3588 config TARGET_NANOPI_R6C_RK3588S bool "FriendlyElec NanoPi R6C" - select BOARD_LATE_INIT help The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip RK3588s. @@ -155,7 +148,6 @@ config TARGET_NANOPI_R6C_RK3588S config TARGET_NANOPI_R6S_RK3588S bool "FriendlyElec NanoPi R6S" - select BOARD_LATE_INIT help The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip RK3588s. @@ -167,7 +159,6 @@ config TARGET_NANOPI_R6S_RK3588S config TARGET_NOVA_RK3588 bool "Indiedroid Nova RK3588" - select BOARD_LATE_INIT help Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid. It comes in configurations from 4GB of RAM to 16GB of RAM, @@ -176,13 +167,11 @@ config TARGET_NOVA_RK3588 config TARGET_ODROID_M2_RK3588S bool "Hardkernel ODROID-M2" - select BOARD_LATE_INIT help Hardkernel ODROID-M2 single board computer with a RK3588S2 SoC. config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" - select BOARD_LATE_INIT help Neu6A: Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module @@ -204,7 +193,6 @@ config TARGET_RK3588_NEU6 config TARGET_ROCK5A_RK3588 bool "Radxa ROCK5A RK3588 board" - select BOARD_LATE_INIT help Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa. @@ -231,7 +219,6 @@ config TARGET_ROCK5A_RK3588 config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" - select BOARD_LATE_INIT help Radxa ROCK5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa. @@ -256,7 +243,6 @@ config TARGET_ROCK5B_RK3588 config TARGET_ROCK_5_ITX_RK3588 bool "Radxa ROCK-5-ITX RK3588 board" - select BOARD_LATE_INIT help Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa in the ITX formfactor. @@ -284,7 +270,6 @@ config TARGET_ROCK_5_ITX_RK3588 config TARGET_ROCK_5C_RK3588S bool "Radxa ROCK 5C RK3588S2 board" - select BOARD_LATE_INIT help Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer. @@ -304,7 +289,6 @@ config TARGET_ROCK_5C_RK3588S config TARGET_SIGE7_RK3588 bool "ArmSoM Sige7 RK3588 board" - select BOARD_LATE_INIT help ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by ArmSoM. @@ -329,14 +313,12 @@ config TARGET_SIGE7_RK3588 config TARGET_QUARTZPRO64_RK3588 bool "Pine64 QuartzPro64 RK3588 board" - select BOARD_LATE_INIT help Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board Computer) by Pine64. config TARGET_TIGER_RK3588 bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)" - select BOARD_LATE_INIT help The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the @@ -366,7 +348,6 @@ config TARGET_TIGER_RK3588 config TARGET_TURINGRK1_RK3588 bool "Turing Machines RK1 RK3588 board" - select BOARD_LATE_INIT help The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines. @@ -389,7 +370,6 @@ config TARGET_TURINGRK1_RK3588 config TARGET_TOYBRICK_RK3588 bool "Toybrick TB-RK3588X board" - select BOARD_LATE_INIT help Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board. TB-RK3588X adopts core board and mainboard design. The core board is connected @@ -420,9 +400,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TEXT_BASE default 0x00a00000 @@ -447,4 +424,7 @@ source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" source "board/theobroma-systems/tiger_rk3588/Kconfig" +config SYS_CONFIG_NAME + default "rk3588_common" + endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index c1dce3ee370..e2278ff792b 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -116,18 +116,25 @@ void board_debug_uart_init(void) } #ifdef CONFIG_XPL_BUILD + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + void rockchip_stimer_init(void) { /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4); + u32 reg = readl(HP_TIMER_BASE + HP_CTRL_REG); - if (reg & 0x1) + if (reg & TIMER_EN) return; - asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18); - writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4); + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); } #endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index f7d32829295..3bc482331c7 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -110,7 +110,9 @@ static int rockchip_dram_init_banksize(void) u8 i, j; if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && - !IS_ENABLED(CONFIG_ROCKCHIP_RK3568)) + !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) && + !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) && + !IS_ENABLED(CONFIG_ROCKCHIP_RK3528)) return -ENOTSUPP; if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL)) @@ -181,9 +183,9 @@ static int rockchip_dram_init_banksize(void) * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not * have it, so force this space as reserved. */ - if (start_addr < SZ_2M) { - size -= SZ_2M - start_addr; - start_addr = SZ_2M; + if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) { + size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr; + start_addr = CFG_SYS_SDRAM_BASE + SZ_2M; } /* @@ -228,7 +230,7 @@ static int rockchip_dram_init_banksize(void) return -EINVAL; } - size -= rsrv_end - start_addr; + size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE); start_addr = rsrv_end; break; } @@ -301,8 +303,8 @@ int dram_init_banksize(void) debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n", ret); - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; + /* Reserve 2M for ATF bl31 */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 22d48dfae1c..c43fdee4a48 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -68,6 +68,8 @@ obj-y += altera-sysmgr.o obj-y += ccu_ncore3.o obj-y += system_manager_soc64.o obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 27072e53135..8506d510413 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -195,3 +195,16 @@ void board_prep_linux(struct bootm_headers *images) } } #endif + +#if CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP) +void lmb_arch_add_memory(void) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (bd->bi_dram[i].size) + lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + } +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2b..5ac868a281b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -51,6 +51,7 @@ #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 45cc9912f94..2099c51b682 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -128,6 +128,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 /* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -385,6 +386,8 @@ enum MBOX_CFGSTAT_MINOR_ERR_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31) +#define HPS_EXECUTION_STATE_FSBL 0 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -401,6 +404,7 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 058fdd6e548..4b010be9ee8 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -10,9 +10,12 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); -void socfpga_bridges_reset(int enable); +void socfpga_bridges_reset(int enable, unsigned int mask); #define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_HDSKEN 0x10 +#define RSTMGR_SOC64_HDSKREQ 0x14 +#define RSTMGR_SOC64_HDSKACK 0x18 #define RSTMGR_SOC64_MPUMODRST 0x20 #define RSTMGR_SOC64_PER0MODRST 0x24 #define RSTMGR_SOC64_PER1MODRST 0x28 @@ -20,8 +23,17 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0) +#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1) +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2) +#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3) +#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) +#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) +#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) + +#define RSTMGR_HDSKEN_FPGAHSEN BIT(2) +#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) /* SDM, Watchdogs and MPU warm reset mask */ #define RSTMGR_STAT_SDMWARMRST 0x2 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index b69bd3e47ec..f9c34e85711 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -6,6 +6,7 @@ #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> @@ -474,6 +475,17 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); } +int mbox_hps_stage_notify(u32 execution_stage) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1, &execution_stage, + 0, 0, NULL); +#else + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +#endif +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index e0b2b4237e1..4f080f4f0b3 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -61,7 +61,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", + printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; @@ -107,5 +107,5 @@ void do_bridge_reset(int enable, unsigned int mask) return; } - socfpga_bridges_reset(enable); + socfpga_bridges_reset(enable, mask); } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index b8e40d9a788..1dc44ab4797 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -58,6 +58,20 @@ static struct mm_region socfpga_agilex5_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE, }, { + /* MEM 30GB */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x780000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* MEM 480GB */ + .virt = 0x8800000000UL, + .phys = 0x8800000000UL, + .size = 0x7800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { /* List terminator */ }, }; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index a634c11a028..abb62a9b49f 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,21 +1,34 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <errno.h> #include <hang.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/secure.h> #include <asm/arch/reset_manager.h> #include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <exports.h> #include <linux/iopoll.h> #include <linux/intel-smc.h> +#include <wait_bit.h> DECLARE_GLOBAL_DATA_PTR; +#define TIMEOUT_300MS 300 + +/* F2S manager registers */ +#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14 +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 + /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -56,66 +69,213 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } -void socfpga_bridges_reset(int enable) +static void socfpga_f2s_bridges_reset(int enable, unsigned int mask) { -#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) - u64 arg = enable; + int ret; + u32 brg_mask; + u32 flagout_idlereq = 0; + u32 flagoutset_fdrain = 0; + u32 flagoutset_en = 0; + u32 flaginstatus_idleack = 0; + u32 flaginstatus_respempty = 0; + + if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + /* Support fpga2soc and f2sdram */ + brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | + RSTMGR_BRGMODRST_F2SDRAM0_MASK | + RSTMGR_BRGMODRST_F2SDRAM1_MASK | + RSTMGR_BRGMODRST_F2SDRAM2_MASK); - int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); - if (ret) { - printf("SMC call failed with error %d in %s.\n", ret, __func__); + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) { + flagout_idlereq |= BIT(3); + flaginstatus_idleack |= BIT(5); + flagoutset_fdrain |= BIT(5); + flagoutset_en |= BIT(4); + flaginstatus_respempty |= BIT(7); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) { + flagout_idlereq |= BIT(6); + flaginstatus_idleack |= BIT(9); + flagoutset_fdrain |= BIT(8); + flagoutset_en |= BIT(7); + flaginstatus_respempty |= BIT(11); + } + } else { + /* Support fpga2soc only */ + brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK; + if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + } + + /* mask is not set, return here */ + if (!brg_mask) return; + + if (enable) { + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); + + /* Wait for mpfe noc idleack to 0 */ + wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_idleack, false, TIMEOUT_300MS, false); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagoutset_fdrain); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); + + udelay(1); /* wait 1us */ + } else { + if (readl((socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_BRGMODRST) & brg_mask)) { + /* Bridge cannot be reset twice */ + return; + } + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN, + RSTMGR_HDSKEN_FPGAHSEN); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + + /* Wait for FPGA ack the handshake request to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_HDSKACK), RSTMGR_HDSKREQ_FPGAHSREQ, + true, TIMEOUT_300MS, false); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en); + + udelay(1); + + /* Requests MPFE NoC to idle */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagout_idlereq); + + /* Force F2S bridge to drain */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_fdrain); + + /* Wait for respond queue empty status to 1 (resp idle) */ + ret = wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS, false); + + /* Confirm again */ + if (!ret) + ret = wait_for_bit_le32((u32 *) + (SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS, false); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); } -#else - u32 reg; +} + +static void socfpga_s2f_bridges_reset(int enable, unsigned int mask) +{ + unsigned int noc_mask = 0; + unsigned int brg_mask = 0; + + if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) { + noc_mask = SYSMGR_NOC_H2F_MSK; + brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK; + } + + if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) { + noc_mask |= SYSMGR_NOC_LWH2F_MSK; + brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK; + } + + /* s2f mask is not set, return here */ + if (!brg_mask) + return; if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask); - /* Release all bridges from reset state */ + /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~0); + brg_mask); - /* Poll until all idleack to 0 */ - read_poll_timeout(readl, reg, !reg, 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); + /* Wait for all NOC master ack to 0 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, false, + TIMEOUT_300MS, false); } else { /* set idle request to all bridges */ - writel(~0, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_SET); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask); /* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); - /* Poll until all idleack to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); - - /* Poll until all idlestatus to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS); - - /* Reset all bridges (except NOR DDR scheduler & F2S) */ + /* Wait for all NOC master ack to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, true, + TIMEOUT_300MS, false); + + /* Wait for all NOC master idlestatus to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLESTATUS), noc_mask, true, + TIMEOUT_300MS, false); + + /* Reset all SOC2FPGA bridges */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + brg_mask); /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } -#endif +} + +void socfpga_bridges_reset(int enable, unsigned int mask) +{ + if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + u64 arg[2]; + int ret; + + /* Set bit-1 to indicate has mask value in arg[1]. */ + arg[0] = (enable & BIT(0)) | BIT(1); + arg[1] = mask; + + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg, + ARRAY_SIZE(arg), NULL, 0); + if (ret) + printf("Failed to %s the HPS bridges, check bridges availability. Status %d.\n", + enable ? "enable" : "disable", ret); + } else { + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); + } } /* diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 52617a39cca..91c27a5543d 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -50,6 +50,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); ret = uclass_get_device(UCLASS_CLK, 0, &dev); @@ -77,8 +81,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 3451611082d..a9aad5350d2 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -62,6 +62,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { debug("Clock init failed: %d\n", ret); @@ -100,8 +104,6 @@ void board_init_f(ulong dummy) } } - mbox_init(); - if (IS_ENABLED(CONFIG_CADENCE_QSPI)) mbox_qspi_open(); diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 5ff137e5c6f..81283ef7162 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -49,6 +49,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); preloader_console_init(); @@ -84,8 +88,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 53852cb7443..fa83ff96adc 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -52,6 +52,10 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); /* configuring the HPS clocks */ @@ -84,8 +88,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 54fb93aeb53..7def7b9139a 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -45,6 +45,5 @@ config ZYNQ_SDHCI_MAX_FREQ default 200000000 source "board/xilinx/Kconfig" -source "board/xilinx/versal-net/Kconfig" endif diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 629a14129d5..5ab901c81ca 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -46,6 +46,5 @@ config VERSAL_NO_DDR access to DDR memory where DDR is not present. source "board/xilinx/Kconfig" -source "board/xilinx/versal/Kconfig" endif diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 9d1c2f0dcfc..b5f80a8e3a9 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -87,6 +87,8 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 +#define PMC_MULTI_BOOT_REG 0xF1110004 +#define PMC_MULTI_BOOT_MASK 0x1FFF #define FLASH_RESET_GPIO 0xc #define WPROT_CRP 0xF126001C diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 757bd873fbe..a6dfa556966 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -5,11 +5,11 @@ #include <linux/build_bug.h> -enum { - TCM_LOCK, - TCM_SPLIT, +enum tcm_mode { + TCM_LOCK = 0, + TCM_SPLIT = 1, }; -void initialize_tcm(bool mode); -void tcm_init(u8 mode); +void initialize_tcm(enum tcm_mode mode); +void tcm_init(enum tcm_mode mode); void mem_map_fill(void); diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 921ca49c359..7423b8dc312 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -24,7 +24,7 @@ #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 -static void set_r5_halt_mode(u8 halt, u8 mode) +static void set_r5_halt_mode(u8 halt, enum tcm_mode mode) { u32 tmp; @@ -45,7 +45,7 @@ static void set_r5_halt_mode(u8 halt, u8 mode) } } -static void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(enum tcm_mode mode) { u32 tmp; @@ -63,7 +63,7 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void release_r5_reset(u8 mode) +static void release_r5_reset(enum tcm_mode mode) { u32 tmp; @@ -87,9 +87,9 @@ static void enable_clock_r5(void) writel(tmp, &crlapb_base->cpu_r5_ctrl); } -void initialize_tcm(bool mode) +void initialize_tcm(enum tcm_mode mode) { - if (!mode) { + if (mode == TCM_LOCK) { set_r5_tcm_mode(TCM_LOCK); set_r5_halt_mode(HALT, TCM_LOCK); enable_clock_r5(); @@ -102,7 +102,7 @@ void initialize_tcm(bool mode) } } -void tcm_init(u8 mode) +void tcm_init(enum tcm_mode mode) { puts("WARNING: Initializing TCM overwrites TCM content\n"); initialize_tcm(mode); diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig index 3f18e3351aa..2a595151d6f 100644 --- a/arch/arm/mach-versal2/Kconfig +++ b/arch/arm/mach-versal2/Kconfig @@ -50,6 +50,5 @@ config ZYNQ_SDHCI_MAX_FREQ default 200000000 source "board/xilinx/Kconfig" -source "board/amd/versal2/Kconfig" endif diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 15085f941e0..7ca2bbb7550 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -68,6 +68,7 @@ struct crp_regs { #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 #define SELECTMAP_MODE 0x0000000A +#define UFS_MODE 0x0000000B #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 @@ -96,3 +97,9 @@ enum versal2_platform { #define MIO_PIN_12 0xF1060030 #define BANK0_OUTPUT 0xF1020040 #define BANK0_TRI 0xF1060200 + +#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000 +#define PMXC_SLCR_BASE_ADDRESS 0xF1061000 +#define PMXC_UFS_CAL_1_OFFSET 0xBE8 +#define PMXC_SRAM_CSR 0x4C +#define PMXC_TX_RX_CFG_RDY 0x54 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 376d1bc7131..c3f505fa15c 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -58,5 +58,6 @@ config ZYNQ_SDHCI_MAX_FREQ source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" +source "board/BuR/zynq/Kconfig" endif diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 960ffac2105..b7a4142fd54 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -113,7 +113,7 @@ u64 get_page_table_size(void) } #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode) +void tcm_init(enum tcm_mode mode) { int ret; diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 9af3ab5d6b6..b6a41df1da4 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -41,18 +41,18 @@ enum { ZYNQMP_SILICON_V4, }; -enum { - TCM_LOCK, - TCM_SPLIT, +enum tcm_mode { + TCM_LOCK = 0, + TCM_SPLIT = 1, }; unsigned int zynqmp_get_silicon_version(void); -int check_tcm_mode(bool mode); -void initialize_tcm(bool mode); +int check_tcm_mode(enum tcm_mode mode); +void initialize_tcm(enum tcm_mode mode); void mem_map_fill(void); #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode); +void tcm_init(enum tcm_mode mode); #endif #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 448bc532867..d2a7f305ccc 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -17,9 +17,6 @@ #include <linux/errno.h> #include <linux/string.h> -#define LOCK 0 -#define SPLIT 1 - #define HALT 0 #define RELEASE 1 @@ -65,11 +62,11 @@ int cpu_reset(u32 nr) return 0; } -static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) +static void set_r5_halt_mode(u32 nr, u8 halt, enum tcm_mode mode) { u32 tmp; - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) { + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) { tmp = readl(&rpu_base->rpu0_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -78,7 +75,7 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) writel(tmp, &rpu_base->rpu0_cfg); } - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) { + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) { tmp = readl(&rpu_base->rpu1_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -88,12 +85,12 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) } } -static void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(enum tcm_mode mode) { u32 tmp; tmp = readl(&rpu_base->rpu_glbl_ctrl); - if (mode == LOCK) { + if (mode == TCM_LOCK) { tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; @@ -106,12 +103,12 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void set_r5_reset(u32 nr, u8 mode) +static void set_r5_reset(u32 nr, enum tcm_mode mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK) { + if (mode == TCM_LOCK) { tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); @@ -130,16 +127,16 @@ static void set_r5_reset(u32 nr, u8 mode) writel(tmp, &crlapb_base->rst_lpd_top); } -static void release_r5_reset(u32 nr, u8 mode) +static void release_r5_reset(u32 nr, enum tcm_mode mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); @@ -165,9 +162,9 @@ static int check_r5_mode(void) tmp = readl(&rpu_base->rpu_glbl_ctrl); if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK) - return SPLIT; + return TCM_SPLIT; - return LOCK; + return TCM_LOCK; } int cpu_disable(u32 nr) @@ -249,27 +246,27 @@ static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr) } } -void initialize_tcm(bool mode) +void initialize_tcm(enum tcm_mode mode) { - if (!mode) { - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK); + if (mode == TCM_LOCK) { + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_LOCK); enable_clock_r5(); - release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); + release_r5_reset(ZYNQMP_CORE_RPU0, TCM_LOCK); } else { - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT); - set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, TCM_SPLIT); enable_clock_r5(); - release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT); - release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU0, TCM_SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU1, TCM_SPLIT); } } -int check_tcm_mode(bool mode) +int check_tcm_mode(enum tcm_mode mode) { u32 tmp, cpu_state; - bool mode_prev; + enum tcm_mode mode_prev; tmp = readl(&rpu_base->rpu_glbl_ctrl); mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp); @@ -279,7 +276,7 @@ int check_tcm_mode(bool mode) ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp); cpu_state = cpu_state ? false : true; - if ((mode_prev == SPLIT && mode == LOCK) && cpu_state) + if ((mode_prev == TCM_SPLIT && mode == TCM_LOCK) && cpu_state) return -EACCES; if (mode_prev == mode) @@ -288,11 +285,11 @@ int check_tcm_mode(bool mode) return 0; } -static void mark_r5_used(u32 nr, u8 mode) +static void mark_r5_used(u32 nr, enum tcm_mode mode) { u32 mask = 0; - if (mode == LOCK) { + if (mode == TCM_LOCK) { mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK; } else { switch (nr) { @@ -358,30 +355,30 @@ int cpu_release(u32 nr, int argc, char *const argv[]) return 1; } printf("R5 lockstep mode\n"); - set_r5_reset(nr, LOCK); - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(nr, HALT, LOCK); + set_r5_reset(nr, TCM_LOCK); + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(nr, HALT, TCM_LOCK); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(nr, LOCK); + release_r5_reset(nr, TCM_LOCK); dcache_disable(); write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(nr, RELEASE, LOCK); - mark_r5_used(nr, LOCK); + set_r5_halt_mode(nr, RELEASE, TCM_LOCK); + mark_r5_used(nr, TCM_LOCK); } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) { printf("R5 split mode\n"); - set_r5_reset(nr, SPLIT); - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(nr, HALT, SPLIT); + set_r5_reset(nr, TCM_SPLIT); + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(nr, HALT, TCM_SPLIT); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(nr, SPLIT); + release_r5_reset(nr, TCM_SPLIT); dcache_disable(); write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(nr, RELEASE, SPLIT); - mark_r5_used(nr, SPLIT); + set_r5_halt_mode(nr, RELEASE, TCM_SPLIT); + mark_r5_used(nr, TCM_SPLIT); } else { printf("Unsupported mode\n"); return 1; diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 3aa218545bb..279006b4d13 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -146,7 +146,7 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - u8 mode; + enum tcm_mode mode; if (argc != cmdtp->maxargs) return CMD_RET_USAGE; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7ea439e857c..a0317011de7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -146,7 +146,35 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R6 select SUPPORT_BIG_ENDIAN select SUPPORT_LITTLE_ENDIAN + imply OF_UPSTREAM + imply BOOTSTD_FULL + imply CLK + imply CLK_BOSTON imply CMD_DM + imply AHCI + imply AHCI_PCI + imply CFI_FLASH + imply MTD_NOR_FLASH + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply PCH_GBE + imply PCI + imply PCI_XILINX + imply PCI_INIT_R + imply SCSI + imply SCSI_AHCI + imply SYS_NS16550 + imply SYSRESET + imply SYSRESET_CMD_POWEROFF + imply SYSRESET_SYSCON + imply USB + imply USB_EHCI_HCD + imply USB_EHCI_PCI + imply USB_XHCI_HCD + imply USB_XHCI_PCI + imply CMD_USB config TARGET_XILFPGA bool "Support Imagination Xilfpga" @@ -322,6 +350,7 @@ config MIPS_CACHE_DISABLE config MIPS_RELOCATION_TABLE_SIZE hex "Relocation table size" range 0x100 0x10000 + default "0xc000" if TARGET_MALTA default "0x8000" ---help--- A table of relocation data will be appended to the U-Boot binary diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 752e771514f..7c4ee8b668b 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -3,7 +3,6 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_AP152) += ap152.dtb -dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb diff --git a/arch/mips/dts/boston-u-boot.dtsi b/arch/mips/dts/boston-u-boot.dtsi new file mode 100644 index 00000000000..1b0c0a28961 --- /dev/null +++ b/arch/mips/dts/boston-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&plat_regs { + compatible = "img,boston-platform-regs", "syscon", "simple-mfd"; + bootph-all; +}; + +&clk_boston { + bootph-all; +}; diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts deleted file mode 100644 index c1a73963037..00000000000 --- a/arch/mips/dts/img,boston.dts +++ /dev/null @@ -1,222 +0,0 @@ -/dts-v1/; - -#include <dt-bindings/clock/boston-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/mips-gic.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "img,boston"; - - chosen { - stdout-path = &uart0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "img,mips"; - reg = <0>; - clocks = <&clk_boston BOSTON_CLK_CPU>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - gic: interrupt-controller { - compatible = "mti,gic"; - - interrupt-controller; - #interrupt-cells = <3>; - - timer { - compatible = "mti,gic-timer"; - interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; - clocks = <&clk_boston BOSTON_CLK_CPU>; - }; - }; - - pci0: pci@10000000 { - status = "disabled"; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x10000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; - - ranges = <0x02000000 0 0x40000000 - 0x40000000 0 0x40000000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci0_intc 0>, - <0 0 0 2 &pci0_intc 1>, - <0 0 0 3 &pci0_intc 2>, - <0 0 0 4 &pci0_intc 3>; - - pci0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pci1: pci@12000000 { - status = "disabled"; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x12000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; - - ranges = <0x02000000 0 0x20000000 - 0x20000000 0 0x20000000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci1_intc 0>, - <0 0 0 2 &pci1_intc 1>, - <0 0 0 3 &pci1_intc 2>, - <0 0 0 4 &pci1_intc 3>; - - pci1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pci2: pci@14000000 { - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x14000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; - - ranges = <0x02000000 0 0x16000000 - 0x16000000 0 0x100000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci2_intc 0>, - <0 0 0 2 &pci2_intc 1>, - <0 0 0 3 &pci2_intc 2>, - <0 0 0 4 &pci2_intc 3>; - - pci2_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - pci2_root@0,0,0 { - compatible = "pci10ee,7021"; - reg = <0x00000000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - eg20t_bridge@1,0,0 { - compatible = "pci8086,8800"; - reg = <0x00010000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - eg20t_mac@2,0,1 { - compatible = "pci8086,8802"; - reg = <0x00020100 0 0 0 0>; - phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; - }; - - eg20t_gpio: eg20t_gpio@2,0,2 { - compatible = "pci8086,8803"; - reg = <0x00020200 0 0 0 0>; - - gpio-controller; - #gpio-cells = <2>; - }; - - eg20t_i2c@2,12,2 { - compatible = "pci8086,8817"; - reg = <0x00026200 0 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - rtc@0x68 { - compatible = "st,m41t81s"; - reg = <0x68>; - }; - }; - }; - }; - }; - - plat_regs: system-controller@17ffd000 { - compatible = "img,boston-platform-regs", "syscon"; - reg = <0x17ffd000 0x1000>; - bootph-all; - }; - - clk_boston: clock { - compatible = "img,boston-clock"; - #clock-cells = <1>; - regmap = <&plat_regs>; - bootph-all; - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&plat_regs>; - offset = <0x10>; - mask = <0x10>; - }; - - uart0: uart@17ffe000 { - compatible = "ns16550a"; - reg = <0x17ffe000 0x1000>; - reg-shift = <2>; - reg-io-width = <4>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&clk_boston BOSTON_CLK_SYS>; - - bootph-all; - }; - - lcd: lcd@17fff000 { - compatible = "img,boston-lcd"; - reg = <0x17fff000 0x8>; - }; - - flash@18000000 { - compatible = "cfi-flash"; - reg = <0x18000000 0x8000000>; - bank-width = <2>; - }; -}; diff --git a/arch/mips/include/asm/acpi_table.h b/arch/mips/include/asm/acpi_table.h new file mode 100644 index 00000000000..b4139d0ba32 --- /dev/null +++ b/arch/mips/include/asm/acpi_table.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +/* + * This file is needed by some drivers. + */ + +#endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index ce7d9e16961..a9e318c4a31 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -102,6 +102,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &syscrg { bootph-pre-ram; }; diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 99d6195827e..9e1f3d5749b 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -59,3 +59,14 @@ ENTRY(longjmp) ret ENDPROC(longjmp) .popsection + +.pushsection .text.initjmp, "ax" +ENTRY(initjmp) + /* a1: entry point address, a2: stack base, a3: stack size */ + add a2, a2, a3 + STORE_IDX(a1, 12) + STORE_IDX(a2, 13) + li a0, 0 + ret +ENDPROC(initjmp) +.popsection diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index bfcdc335d32..038ad78accc 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y := cache.o cpu.o state.o +obj-y := cache.o cpu.o state.o initjmp.o extra-y := start.o os.o extra-$(CONFIG_SANDBOX_SDL) += sdl.o obj-$(CONFIG_XPL_BUILD) += spl.o @@ -29,6 +29,15 @@ cmd_cc_eth-raw-os.o = $(CC) $(filter-out -nostdinc, \ $(obj)/eth-raw-os.o: $(src)/eth-raw-os.c FORCE $(call if_changed_dep,cc_eth-raw-os.o) +# initjmp.c is build in the system environment, so needs standard includes +# CFLAGS_REMOVE_initjmp.o cannot be used to drop header include path +quiet_cmd_cc_initjmp.o = CC $(quiet_modtag) $@ +cmd_cc_initjmp.o = $(CC) $(filter-out -nostdinc, \ + $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $< + +$(obj)/initjmp.o: $(src)/initjmp.c FORCE + $(call if_changed_dep,cc_initjmp.o) + # sdl.c fails to build with -fshort-wchar using musl cmd_cc_sdl.o = $(CC) $(filter-out -nostdinc -fshort-wchar, \ $(patsubst -I%,-idirafter%,$(c_flags))) -fno-lto -c -o $@ $< diff --git a/arch/sandbox/cpu/initjmp.c b/arch/sandbox/cpu/initjmp.c new file mode 100644 index 00000000000..6e72d32cb4b --- /dev/null +++ b/arch/sandbox/cpu/initjmp.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: LGPL-2.1-or-later +/* + * An implementation of initjmp() in C, that plays well with the system's + * setjmp() and longjmp() functions. + * Taken verbatim from arch/sandbox/os/setjmp.c in the barebox project. + * Modified so that initjmp() accepts a stack_size argument. + * + * Copyright (C) 2006 Anthony Liguori <anthony@codemonkey.ws> + * Copyright (C) 2011 Kevin Wolf <kwolf@redhat.com> + * Copyright (C) 2012 Alex Barcelo <abarcelo@ac.upc.edu> + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + * Copyright (C) 2025 Linaro Ltd. + * This file is partly based on pth_mctx.c, from the GNU Portable Threads + * Copyright (c) 1999-2006 Ralf S. Engelschall <rse@engelschall.com> + */ + +/* XXX Is there a nicer way to disable glibc's stack check for longjmp? */ +#ifdef _FORTIFY_SOURCE +#undef _FORTIFY_SOURCE +#endif + +#include <pthread.h> +#include <stdio.h> +#include <stdlib.h> +#include <setjmp.h> +#include <signal.h> + +typedef sigjmp_buf _jmp_buf __attribute__((aligned((16)))); +_Static_assert(sizeof(_jmp_buf) <= 512, "sigjmp_buf size exceeds expectation"); + +/* + * Information for the signal handler (trampoline) + */ +static struct { + _jmp_buf *reenter; + void (*entry)(void); + volatile sig_atomic_t called; +} tr_state; + +/* + * "boot" function + * This is what starts the coroutine, is called from the trampoline + * (from the signal handler when it is not signal handling, read ahead + * for more information). + */ +static void __attribute__((noinline, noreturn)) +coroutine_bootstrap(void (*entry)(void)) +{ + for (;;) + entry(); +} + +/* + * This is used as the signal handler. This is called with the brand new stack + * (thanks to sigaltstack). We have to return, given that this is a signal + * handler and the sigmask and some other things are changed. + */ +static void coroutine_trampoline(int signal) +{ + /* Get the thread specific information */ + tr_state.called = 1; + + /* + * Here we have to do a bit of a ping pong between the caller, given that + * this is a signal handler and we have to do a return "soon". Then the + * caller can reestablish everything and do a siglongjmp here again. + */ + if (!sigsetjmp(*tr_state.reenter, 0)) { + return; + } + + /* + * Ok, the caller has siglongjmp'ed back to us, so now prepare + * us for the real machine state switching. We have to jump + * into another function here to get a new stack context for + * the auto variables (which have to be auto-variables + * because the start of the thread happens later). Else with + * PIC (i.e. Position Independent Code which is used when PTH + * is built as a shared library) most platforms would + * horrible core dump as experience showed. + */ + coroutine_bootstrap(tr_state.entry); +} + +int __attribute__((weak)) initjmp(_jmp_buf jmp, void (*func)(void), + void *stack_base, size_t stack_size) +{ + struct sigaction sa; + struct sigaction osa; + stack_t ss; + stack_t oss; + sigset_t sigs; + sigset_t osigs; + + /* The way to manipulate stack is with the sigaltstack function. We + * prepare a stack, with it delivering a signal to ourselves and then + * put sigsetjmp/siglongjmp where needed. + * This has been done keeping coroutine-ucontext (from the QEMU project) + * as a model and with the pth ideas (GNU Portable Threads). + * See coroutine-ucontext for the basics of the coroutines and see + * pth_mctx.c (from the pth project) for the + * sigaltstack way of manipulating stacks. + */ + + tr_state.entry = func; + tr_state.reenter = (void *)jmp; + + /* + * Preserve the SIGUSR2 signal state, block SIGUSR2, + * and establish our signal handler. The signal will + * later transfer control onto the signal stack. + */ + sigemptyset(&sigs); + sigaddset(&sigs, SIGUSR2); + pthread_sigmask(SIG_BLOCK, &sigs, &osigs); + sa.sa_handler = coroutine_trampoline; + sigfillset(&sa.sa_mask); + sa.sa_flags = SA_ONSTACK; + if (sigaction(SIGUSR2, &sa, &osa) != 0) { + return -1; + } + + /* + * Set the new stack. + */ + ss.ss_sp = stack_base; + ss.ss_size = stack_size; + ss.ss_flags = 0; + if (sigaltstack(&ss, &oss) < 0) { + return -1; + } + + /* + * Now transfer control onto the signal stack and set it up. + * It will return immediately via "return" after the sigsetjmp() + * was performed. Be careful here with race conditions. The + * signal can be delivered the first time sigsuspend() is + * called. + */ + tr_state.called = 0; + pthread_kill(pthread_self(), SIGUSR2); + sigfillset(&sigs); + sigdelset(&sigs, SIGUSR2); + while (!tr_state.called) { + sigsuspend(&sigs); + } + + /* + * Inform the system that we are back off the signal stack by + * removing the alternative signal stack. Be careful here: It + * first has to be disabled, before it can be removed. + */ + sigaltstack(NULL, &ss); + ss.ss_flags = SS_DISABLE; + if (sigaltstack(&ss, NULL) < 0) { + return -1; + } + sigaltstack(NULL, &ss); + if (!(oss.ss_flags & SS_DISABLE)) { + sigaltstack(&oss, NULL); + } + + /* + * Restore the old SIGUSR2 signal handler and mask + */ + sigaction(SIGUSR2, &osa, NULL); + pthread_sigmask(SIG_SETMASK, &osigs, NULL); + + /* + * jmp can now be used to enter the trampoline again, but not as a + * signal handler. Instead it's longjmp'd to directly. + */ + return 0; +} + diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 53b1c147c2e..2daf54e7c33 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -19,18 +19,13 @@ int dram_init(void) void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr) { - void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r; - - if (new_gd->reloc_off) { + if (new_gd->reloc_off) memcpy((void *)new_gd->relocaddr, (void *)(new_gd->relocaddr - new_gd->reloc_off), new_gd->mon_len); - reloc_board_init_r += new_gd->reloc_off; - } - __asm__ __volatile__("mov.l %0, r15\n" : : "m" (new_gd->start_addr_sp)); while (1) - reloc_board_init_r(new_gd, 0x0); + board_init_r(new_gd, 0x0); } diff --git a/board/BuR/common/Kconfig b/board/BuR/common/Kconfig new file mode 100644 index 00000000000..490201e7407 --- /dev/null +++ b/board/BuR/common/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# B&R Industrial Automation GmbH - http://www.br-automation.com + +config BR_RESETC_I2CBUS + int "I2C Bus address of B&R reset controller" + depends on SYS_VENDOR = "BuR" && DM_I2C + default 0 diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index f5d09fef3d3..dfe2c2e0155 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -52,10 +52,16 @@ static int resetc_init(void) { struct udevice *i2cbus; int rc; +#if !defined(BR_RESETC_I2CBUS) + int busno = 0; +#else + int busno = CONFIG_BR_RESETC_I2CBUS; +#endif + + rc = uclass_get_device_by_seq(UCLASS_I2C, busno, &i2cbus); - rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus); if (rc) { - printf("Cannot find I2C bus #0!\n"); + printf("Cannot find I2C bus #%d!\n", busno); return -1; } @@ -108,9 +114,73 @@ int br_resetc_bmode(void) { int rc = 0; u16 regw; + unsigned int bmode = 0; + + if (!resetc.i2cdev) + rc = resetc_init(); + + if (rc != 0) + return rc; + + board_boot_led(1); + + rc = br_resetc_bmode_get(&bmode); + if (rc != 0) + return rc; + + LCD_SETCURSOR(1, 8); + + switch (bmode) { + case BMODE_PME: + LCD_PUTS("entering PME-Mode (netscript). "); + regw = 0x0C0C; + break; + case BMODE_DEFAULTAR: + LCD_PUTS("entering BOOT-mode. "); + regw = 0x0000; + break; + case BMODE_DIAG: + LCD_PUTS("entering DIAGNOSE-mode. "); + regw = 0x0F0F; + break; + case BMODE_SERVICE: + LCD_PUTS("entering SERVICE mode. "); + regw = 0xB4B4; + break; + case BMODE_RUN: + LCD_PUTS("loading OS... "); + regw = 0x0404; + break; + } + + board_boot_led(0); + + if (resetc.is_psoc) + rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, + (u8 *)®w, 2); + else + rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, + (u8 *)®w, 1); + + if (rc != 0) + printf("WARN: cannot write into resetcontroller!\n"); + + if (resetc.is_psoc) + printf("Reset: PSOC controller\n"); + else + printf("Reset: STM32 controller\n"); + + printf("Mode: %s\n", bootmodeascii[regw & 0x0F]); + env_set_ulong("b_mode", regw & 0x0F); + + return rc; +} + +int br_resetc_bmode_get(unsigned int *bmode) +{ + int rc = 0; u8 regb, scr; int cnt; - unsigned int bmode = 0; if (!resetc.i2cdev) rc = resetc_init(); @@ -130,13 +200,11 @@ int br_resetc_bmode(void) return -1; } - board_boot_led(1); - /* special bootmode from resetcontroller */ if (regb & 0x4) { - bmode = BMODE_DIAG; + *bmode = BMODE_DIAG; } else if (regb & 0x8) { - bmode = BMODE_DEFAULTAR; + *bmode = BMODE_DEFAULTAR; } else if (board_boot_key() != 0) { cnt = 4; do { @@ -163,68 +231,23 @@ int br_resetc_bmode(void) switch (cnt) { case 0: - bmode = BMODE_PME; + *bmode = BMODE_PME; break; case 1: - bmode = BMODE_DEFAULTAR; + *bmode = BMODE_DEFAULTAR; break; case 2: - bmode = BMODE_DIAG; + *bmode = BMODE_DIAG; break; case 3: - bmode = BMODE_SERVICE; + *bmode = BMODE_SERVICE; break; } } else if ((regb & 0x1) || scr == 0xCC) { - bmode = BMODE_PME; + *bmode = BMODE_PME; } else { - bmode = BMODE_RUN; - } - - LCD_SETCURSOR(1, 8); - - switch (bmode) { - case BMODE_PME: - LCD_PUTS("entering PME-Mode (netscript). "); - regw = 0x0C0C; - break; - case BMODE_DEFAULTAR: - LCD_PUTS("entering BOOT-mode. "); - regw = 0x0000; - break; - case BMODE_DIAG: - LCD_PUTS("entering DIAGNOSE-mode. "); - regw = 0x0F0F; - break; - case BMODE_SERVICE: - LCD_PUTS("entering SERVICE mode. "); - regw = 0xB4B4; - break; - case BMODE_RUN: - LCD_PUTS("loading OS... "); - regw = 0x0404; - break; + *bmode = BMODE_RUN; } - board_boot_led(0); - - if (resetc.is_psoc) - rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, - (u8 *)®w, 2); - else - rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, - (u8 *)®w, 1); - - if (rc != 0) - printf("WARN: cannot write into resetcontroller!\n"); - - if (resetc.is_psoc) - printf("Reset: PSOC controller\n"); - else - printf("Reset: STM32 controller\n"); - - printf("Mode: %s\n", bootmodeascii[regw & 0x0F]); - env_set_ulong("b_mode", regw & 0x0F); - return rc; } diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h index 999045b867d..3bd5ac20ae1 100644 --- a/board/BuR/common/br_resetc.h +++ b/board/BuR/common/br_resetc.h @@ -11,6 +11,7 @@ int br_resetc_regget(u8 reg, u8 *dst); int br_resetc_regset(u8 reg, u8 val); int br_resetc_bmode(void); +int br_resetc_bmode_get(unsigned int *bmode); /* reset controller register defines */ #define RSTCTRL_CTRLREG 0x01 diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 7fb61736710..3513f43a9f5 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -68,7 +68,7 @@ int brdefaultip_setup(int bus, int chip) "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;", u8buf); else - strncpy(defip, + strlcpy(defip, "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;", sizeof(defip)); diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig new file mode 100644 index 00000000000..b450a21bd98 --- /dev/null +++ b/board/BuR/zynq/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# B&R Industrial Automation GmbH - http://www.br-automation.com +if ARCH_ZYNQ + +config TARGET_ZYNQ_BR + bool "Support BR Zynq builds" + depends on SYS_VENDOR = "BuR" + select BINMAN + select SPL_BINMAN_FDT + +endif + +source "board/BuR/common/Kconfig" diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS new file mode 100644 index 00000000000..d655cae58d4 --- /dev/null +++ b/board/BuR/zynq/MAINTAINERS @@ -0,0 +1,11 @@ +ZYNQ BOARD +M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> +S: Maintained +F: board/BuR/zynq/ +F: board/BuR/common/ +F: include/configs/brzynq.h +F: arch/arm/dts/zynq-br* +F: configs/brcp1_* +F: configs/brcp150_defconfig +F: configs/brcp170_defconfig +F: configs/brsmarc2_defconfig diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile new file mode 100644 index 00000000000..fed40b0a069 --- /dev/null +++ b/board/BuR/zynq/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# B&R Industrial Automation GmbH - http://www.br-automation.com + +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//') + +obj-y := ../common/common.o +obj-y += ../common/br_resetc.o +obj-y += common/board.o +obj-y += $(hw-platform-y)/board.o + +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes diff --git a/board/BuR/zynq/brcp150/board.c b/board/BuR/zynq/brcp150/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp150/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp150/ps7_init_gpl.c b/board/BuR/zynq/brcp150/ps7_init_gpl.c new file mode 100644 index 00000000000..822bce358aa --- /dev/null +++ b/board/BuR/zynq/brcp150/ps7_init_gpl.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000801U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001001U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001003U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000802U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01403U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000801U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400800U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FF844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x000003E0U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x000003E1U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp170/board.c b/board/BuR/zynq/brcp170/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp170/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp170/ps7_init_gpl.c b/board/BuR/zynq/brcp170/ps7_init_gpl.c new file mode 100644 index 00000000000..223d13cc389 --- /dev/null +++ b/board/BuR/zynq/brcp170/ps7_init_gpl.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DF844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp1_1r/board.c b/board/BuR/zynq/brcp1_1r/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp1_1r/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c new file mode 100644 index 00000000000..be39db9caaa --- /dev/null +++ b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0003C000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000300U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x000FA240U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0003C000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00101001U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000A02U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01901U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00500800U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp1_1r_switch/board.c b/board/BuR/zynq/brcp1_1r_switch/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp1_1r_switch/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c new file mode 100644 index 00000000000..e4fc708a45c --- /dev/null +++ b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD84CDU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp1_2r/board.c b/board/BuR/zynq/brcp1_2r/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp1_2r/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c new file mode 100644 index 00000000000..4ebed8bf90f --- /dev/null +++ b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA3C0U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0002E000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c new file mode 100644 index 00000000000..7d9e13a5eec --- /dev/null +++ b/board/BuR/zynq/brsmarc2/board.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ +#include <linux/types.h> +#include <i2c.h> +#include <init.h> +#include "../../common/br_resetc.h" +#include "../../common/bur_common.h" + +int board_boot_key(void) +{ + unsigned char u8buf = 0; + int rc; + + rc = br_resetc_regget(RSTCTRL_ENHSTATUS, &u8buf); + if (rc == 0) + return (u8buf & 0x1); + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +int br_board_late_init(void) +{ + brdefaultip_setup(0, 0x57); + + return 0; +} +#endif diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c new file mode 100644 index 00000000000..51ff8bfb70f --- /dev/null +++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF6666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/common/board.c b/board/BuR/zynq/common/board.c new file mode 100644 index 00000000000..35e8ed81181 --- /dev/null +++ b/board/BuR/zynq/common/board.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for B&R brcp150, brcp170, brcp1, brsmarc2 Board + * + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ + +#include <fdtdec.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <init.h> +#include <i2c.h> +#include <dm/uclass.h> +#include <command.h> +#include <binman.h> +#include "../../common/br_resetc.h" +#include "../../common/bur_common.h" + +#include <fdt_support.h> +#include <spi_flash.h> +#include <fpga.h> +#include <zynqpl.h> + +#define RSTCTRL_CTRLSPEC_nPCIRST 0x1 + +__weak int br_board_late_init(void) +{ + return 0; +} + +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(FPGA) +const char *fpga_paths[2] = { "/binman/blob-ext@4", + "/binman/blob-ext@1"}; + +static int start_fpga(unsigned int bank) +{ + struct spi_flash *flash_dev; + ofnode fpga_node; + void *buf; + + u32 flash_offset, flash_size; + int rc; + + fpga_node = ofnode_path(fpga_paths[bank]); + + if (!ofnode_valid(fpga_node)) { + printf("WARN: binman node not found %s\n", fpga_paths[bank]); + return -ENOENT; + } + + flash_offset = ofnode_read_u32_default(fpga_node, "offset", ~0UL); + flash_size = ofnode_read_u32_default(fpga_node, "size", ~0UL); + + if (flash_offset == ~0UL || flash_size == ~0UL) { + printf("WARN: invalid fpga 'offset, size' in fdt (0x%x, 0x%x)", + flash_offset, flash_size); + return -EINVAL; + } + + printf("loading bitstream from bank #%d (0x%08x / 0x%08x)\n", bank, + flash_offset, flash_size); + + flash_dev = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); + + if (rc) { + printf("WARN: cannot probe SPI-flash for bitstream!\n"); + return -ENODEV; + } + + buf = kmalloc(flash_size, 0); + if (!buf) { + spi_flash_free(flash_dev); + return -ENOMEM; + } + + debug("using buf @ %p, flashbase: 0x%08x, len: 0x%08x\n", + buf, flash_offset, flash_size); + + rc = spi_flash_read(flash_dev, flash_offset, flash_size, buf); + + spi_flash_free(flash_dev); + + if (rc) { + printf("WARN: cannot read bitstream from spi-flash!\n"); + kfree(buf); + + return -EIO; + } + + rc = fpga_loadbitstream(0, buf, flash_size, BIT_FULL); + if (rc) { + printf("WARN: FPGA configuration from bank #%d failed!\n", bank); + kfree(buf); + + return -EIO; + } + + kfree(buf); + + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) +const char *boot_gpios[] = { "br,rs232-en", + "br,board-reset", + NULL}; + +/* spl stage */ +int board_init(void) +{ + struct gpio_desc gpio; + int node; + int rc; + + /* peripheral RESET on PSOC reset-controller */ + rc = br_resetc_regset(RSTCTRL_SPECGPIO_O, RSTCTRL_CTRLSPEC_nPCIRST); + if (rc != 0) + printf("ERROR: cannot write to resetc (nPCIRST)!\n"); + + for (int i = 0; boot_gpios[i]; i++) { + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, boot_gpios[i]); + + if (node < 0) { + printf("INFO: %s not found!\n", boot_gpios[i]); + } else { + rc = gpio_request_by_name_nodev(offset_to_ofnode(node), "pin", + 0, &gpio, GPIOD_IS_OUT); + + if (!rc) + dm_gpio_set_value(&gpio, 1); + else + printf("ERROR: failed to setup %s!\n", boot_gpios[i]); + } + } + +#if CONFIG_IS_ENABLED(FPGA) + unsigned int bmode; + unsigned int bank; + + rc = br_resetc_bmode_get(&bmode); + if (rc) { + printf("WARN: can't get Boot Mode!\n"); + return -ENODEV; + } + + /* use golden FPGA image in case of special boot flow (PME, BootAR, USB, Net ...) */ + bank = ((bmode == 0) || (bmode == 12)) ? 1 : 0; + + /* bring up FPGA */ + if (start_fpga(bank) != 0) { + printf("WARN: cannot start fpga from bank %d, trying bank %d!\n", bank, bank ^ 1); + bank ^= 1; + start_fpga(bank); + } +#endif + return 0; +} +#else +int board_init(void) +{ + return 0; +} + +/* + * PMIC buckboost regulator workaround: + * The DA9062 PMIC can switch its buckboost regulator output + * between PFM and PWM mode for eco-purpose. + * In very rare situations this transition leads into a non- + * functional buckboost regulator with zero output. + * With this workaround we prevent this with turning this + * feature off by forcing PWM-mode if auto-mode is selected. + */ +static void pmic_fixup(int addr) +{ + u8 regs[] = { 0x9E, 0x9D, 0xA0, 0x9F }; + struct udevice *i2cdev = NULL; + unsigned int i; + u8 val; + int rc; + + i2c_get_chip_for_busnum(0, addr, 1, &i2cdev); + if (!i2cdev) + return; + + printf("PMIC: fixup buckboost at i2c device 0x%x\n", addr); + + for (i = 0; i < sizeof(regs); i++) { + rc = dm_i2c_read(i2cdev, regs[i], &val, 1); + if (rc == 0 && val == 0xC0) { + val = 0x80; + dm_i2c_write(i2cdev, regs[i], &val, 1); + } + } +} + +int board_late_init(void) +{ + ofnode node; + u32 addr; + + br_resetc_bmode(); + br_board_late_init(); + + node = ofnode_by_compatible(ofnode_null(), "dlg,da9062"); + + if (!ofnode_valid(node)) + return 0; + + if (!ofnode_read_u32(node, "reg", &addr)) + pmic_fixup(addr); + else + printf("WARN: cannot read PMIC address!"); + + return 0; +} +#endif + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + zynq_ddrc_init(); + + return 0; +} diff --git a/board/BuR/zynq/env/brcp1.env b/board/BuR/zynq/env/brcp1.env new file mode 100644 index 00000000000..269e5193046 --- /dev/null +++ b/board/BuR/zynq/env/brcp1.env @@ -0,0 +1,109 @@ +autoload=0 +b_break=0 +fpgastatus=disabled +/* Memory variable */ +scradr=0xC0000 +fdtbackaddr=0x4000000 +loadaddr=CONFIG_SYS_LOAD_ADDR + +/* PREBOOT */ +preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1 + +/* SPI layout variables */ +cfg_addr= + fdt get value cfgaddr_spi /binman/blob-ext@0 offset && + fdt get value cfgsize_spi /binman/blob-ext@0 size + +fpga_addr= + fdt get value fpgaaddr_spi /binman/blob-ext@1 offset && + fdt get value fpgasize_spi /binman/blob-ext@1 size + +os_addr= + fdt get value osaddr_spi /binman/blob-ext@2 offset && + fdt get value ossize_spi /binman/blob-ext@2 size + +dtb_addr= + fdt get value dtbaddr_spi /binman/blob-ext@3 offset && + fdt get value dtbsize_spi /binman/blob-ext@3 size + +setupaddr_spi= + fdt addr ${fdtcontroladdr}; + run dtb_addr; run os_addr; + run fpga_addr; run cfg_addr + +/* IP setup */ +brdefaultip= + if test -r ${ipaddr}; then; + else + setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; + setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; + fi + +/* Boot orders */ +b_tgts_std=mmc0 mmc1 spi usb0 usb1 net +b_tgts_rcy=spi usb0 usb1 net +b_tgts_pme=net usb0 usb1 mmc spi + +/* Boot targets */ +b_mmc0= + run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg.itb && + run vxargs && bootm ${loadaddr} + +b_mmc1= + run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg && + run vxargs && + sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} && + fdt addr ${fdtbackaddr} && + bootm ${loadaddr} - ${fdtbackaddr} + +b_spi= + run fpga; sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} && + run vxargs && bootm ${loadaddr} + +b_net=run fpga; tftp ${scradr} netscript.img && source ${scradr} +b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr} +b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr} + +/* FPGA setup */ +fpga= + setenv fpgastatus disabled; + sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} && + fpga loadb 0 ${loadaddr} ${fpgasize_spi} && + setenv fpgastatus okay + +/* Configuration preboot*/ +cfgscr= + sf probe && + sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} && + source ${scradr} + +/* OS Boot */ +fdt_fixup= + run cfgscr; run vxfdt + +vxargs= + setenv bootargs gem(0,0)host:vxWorks h=${serverip} + e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1 + +vxfdt= + fdt set /fpga/pci status ${fpgastatus}; + fdt set /fpga status ${fpgastatus} + +/* Boot code */ +b_default= + run b_deftgts; + for target in ${b_tgts}; do + run b_${target}; + if test ${b_break} = 1; then; + exit; + fi; + done + +b_deftgts= + if test ${b_mode} = 12; then + setenv b_tgts ${b_tgts_pme}; + elif test ${b_mode} = 0; then + setenv b_tgts ${b_tgts_rcy}; + else + setenv b_tgts ${b_tgts_std}; + fi diff --git a/board/BuR/zynq/env/brcp150.env b/board/BuR/zynq/env/brcp150.env new file mode 100644 index 00000000000..9c27f0fa325 --- /dev/null +++ b/board/BuR/zynq/env/brcp150.env @@ -0,0 +1,119 @@ +autoload=0 +b_break=0 +fpgastatus=disabled +/* Memory variable */ +scradr=0xC0000 +fdtbackaddr=0x4000000 +loadaddr=CONFIG_SYS_LOAD_ADDR + +/* PREBOOT */ +preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1 + +/* SPI layout variables */ +cfg_addr= + fdt get value cfgaddr_spi /binman/blob-ext@0 offset && + fdt get value cfgsize_spi /binman/blob-ext@0 size + +fpga_addr= + fdt get value fpgaaddr_spi /binman/blob-ext@1 offset && + fdt get value fpgasize_spi /binman/blob-ext@1 size + +os_addr= + fdt get value osaddr_spi /binman/blob-ext@2 offset && + fdt get value ossize_spi /binman/blob-ext@2 size + +dtb_addr= + fdt get value dtbaddr_spi /binman/blob-ext@3 offset && + fdt get value dtbsize_spi /binman/blob-ext@3 size + +opt_addr= + fdt get value optaddr_spi /binman/blob-ext@5 offset && + fdt get value optsize_spi /binman/blob-ext@5 size + +setupaddr_spi= + fdt addr ${fdtcontroladdr}; + run dtb_addr; run os_addr; + run fpga_addr; run cfg_addr; + run opt_addr + +/* IP setup */ +brdefaultip= + if test -r ${ipaddr}; then; + else + setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; + setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; + fi + +/* Boot orders */ +b_tgts_std=mmc0 mmc1 fpga spi usb0 usb1 net +b_tgts_rcy=spi usb0 usb1 net +b_tgts_pme=net usb0 usb1 mmc spi + +/* Boot targets */ +b_mmc0= + mmc dev 0; load mmc 0 ${loadaddr} arimg.itb && + run vxargs && bootm ${loadaddr} + +b_mmc1= + mmc dev 0; load mmc 0 ${loadaddr} arimg && + run vxargs && + sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} && + fdt addr ${fdtbackaddr} && + bootm ${loadaddr} - ${fdtbackaddr} + +b_spi= + sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} && + run vxargs && bootm ${loadaddr} + +b_net=tftp ${scradr} netscript.img && source ${scradr} +b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr} +b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr} + +/* FPGA setup */ +b_fpga= + setenv fpgastatus disabled; + sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} && + fpga loadb 0 ${loadaddr} ${fpgasize_spi} && + setenv fpgastatus okay + +/* Configuration preboot*/ +cfgscr= + sf probe && + sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} && + source ${scradr} + +cfgoptsct= + sf probe && + sf read ${scradr} ${optaddr_spi} ${optsize_spi} && + source ${scradr} + +/* OS Boot */ +fdt_fixup= + run cfgscr; run cfgoptsct; run vxfdt + +vxargs= + setenv bootargs gem(0,0)host:vxWorks h=${serverip} + e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1 + +vxfdt= + fdt set /fpga/pci status ${fpgastatus}; + fdt set /fpga status ${fpgastatus} + +/* Boot code */ +b_default= + run b_deftgts; + for target in ${b_tgts}; do + run b_${target}; + if test ${b_break} = 1; then; + exit; + fi; + done + +b_deftgts= + if test ${b_mode} = 12; then + setenv b_tgts ${b_tgts_pme}; + elif test ${b_mode} = 0; then + setenv b_tgts ${b_tgts_rcy}; + else + setenv b_tgts ${b_tgts_std}; + fi diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig deleted file mode 100644 index ab46af6935e..00000000000 --- a/board/amd/versal2/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 - 2022, Xilinx, Inc. -# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. -# -if ARCH_VERSAL2 - -config CMD_VERSAL2 - bool "Enable Versal Gen 2 specific commands" - default y - depends on ZYNQMP_FIRMWARE - help - Select this to enable AMD Versal Gen 2 specific commands. - Commands like versal2 loadpdi are enabled by this. - -endif diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile index 3a044517f0c..1673be4a6df 100644 --- a/board/amd/versal2/Makefile +++ b/board/amd/versal2/Makefile @@ -8,4 +8,3 @@ obj-y := board.o -obj-$(CONFIG_CMD_VERSAL2) += cmds.o diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 5651d516a9e..72967e69a84 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -20,6 +20,7 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <versalpl.h> #include "../../xilinx/common/board.h" #include <linux/bitfield.h> @@ -28,10 +29,25 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_FPGA_VERSALPL) +static xilinx_desc versalpl = { + xilinx_versal2, csu_dma, 1, &versal_op, 0, &versal_op, NULL, + FPGA_LEGACY +}; +#endif + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); +#if defined(CONFIG_FPGA_VERSALPL) + fpga_init(); + fpga_add(fpga_xilinx, &versalpl); +#endif + + if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) + xilinx_read_eeprom(); + return 0; } @@ -149,7 +165,7 @@ int board_early_init_r(void) return 0; } -static u8 versal_net_get_bootmode(void) +static u8 versal2_get_bootmode(void) { u8 bootmode; u32 reg = 0; @@ -175,7 +191,7 @@ static int boot_targets_setup(void) char *new_targets; char *env_targets; - bootmode = versal_net_get_bootmode(); + bootmode = versal2_get_bootmode(); puts("Bootmode: "); switch (bootmode) { @@ -252,6 +268,16 @@ static int boot_targets_setup(void) mode = "mmc"; bootseq = dev_seq(dev); break; + case UFS_MODE: + puts("UFS_MODE\n"); + if (uclass_get_device(UCLASS_UFS, 0, &dev)) { + debug("UFS driver for UFS device is not present\n"); + break; + } + debug("ufs device found at %p\n", dev); + + mode = "ufs"; + break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; @@ -284,6 +310,7 @@ static int boot_targets_setup(void) env_targets ? env_targets : ""); env_set("boot_targets", new_targets); + free(new_targets); } return 0; @@ -341,3 +368,35 @@ int dram_init(void) void reset_cpu(void) { } + +#if defined(CONFIG_ENV_IS_NOWHERE) +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 bootmode = versal2_get_bootmode(); + + if (prio) + return ENVL_UNKNOWN; + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT)) + return ENVL_FAT; + if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) + return ENVL_EXT4; + return ENVL_NOWHERE; + case OSPI_MODE: + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + return ENVL_NOWHERE; + case JTAG_MODE: + case SELECTMAP_MODE: + default: + return ENVL_NOWHERE; + } +} +#endif diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c deleted file mode 100644 index 56ae39bc6a1..00000000000 --- a/board/amd/versal2/cmds.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2024, Advanced Micro Devices, Inc. - * - * Michal Simek <michal.simek@amd.com> - */ - -#include <cpu_func.h> -#include <command.h> -#include <log.h> -#include <memalign.h> -#include <versalpl.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> - -/** - * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the versal2 load pdi command - * - * Return: return 0 on success, Error value if command fails. - * CMD_RET_USAGE incase of incorrect/missing parameters. - */ -static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 buf_lo, buf_hi; - u32 ret_payload[PAYLOAD_ARG_CNT]; - ulong addr, *pdi_buf; - size_t len; - int ret; - - if (argc != cmdtp->maxargs) { - debug("pdi_load: incorrect parameters passed\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtol(argv[1], NULL, 16); - if (!addr) { - debug("pdi_load: zero pdi_data address\n"); - return CMD_RET_USAGE; - } - - len = hextoul(argv[2], NULL); - if (!len) { - debug("pdi_load: zero size\n"); - return CMD_RET_USAGE; - } - - pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); - if ((ulong)addr != (ulong)pdi_buf) { - memcpy((void *)pdi_buf, (void *)addr, len); - debug("Pdi addr:0x%lx aligned to 0x%lx\n", - addr, (ulong)pdi_buf); - } - - flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); - - buf_lo = lower_32_bits((ulong)pdi_buf); - buf_hi = upper_32_bits((ulong)pdi_buf); - - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); - if (ret) - printf("PDI load failed with err: 0x%08x\n", ret); - - return cmd_process_error(cmdtp, ret); -} - -U_BOOT_LONGHELP(versal2, - "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); - -U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text, - U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, - do_versal2_load_pdi)); diff --git a/board/emulation/qemu-arm/MAINTAINERS b/board/emulation/qemu-arm/MAINTAINERS index 7bc0ee698c5..538769f8040 100644 --- a/board/emulation/qemu-arm/MAINTAINERS +++ b/board/emulation/qemu-arm/MAINTAINERS @@ -5,6 +5,5 @@ F: board/emulation/qemu-arm/ F: board/emulation/common/ F: include/configs/qemu-arm.h F: include/configs/qemu-sbsa.h -F: configs/qemu_arm_defconfig -F: configs/qemu_arm64_defconfig +F: configs/qemu_arm* F: configs/qemu-arm-sbsa_defconfig diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index 3d7453f1b43..d75d1b5f190 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -4,9 +4,4 @@ S: Maintained F: board/emulation/qemu-riscv/ F: board/emulation/common/ F: include/configs/qemu-riscv.h -F: configs/qemu-riscv32_defconfig -F: configs/qemu-riscv32_smode_defconfig -F: configs/qemu-riscv32_spl_defconfig -F: configs/qemu-riscv64_defconfig -F: configs/qemu-riscv64_smode_defconfig -F: configs/qemu-riscv64_spl_defconfig +F: configs/qemu-riscv* diff --git a/board/firefly/roc-pc-rk3576/Kconfig b/board/firefly/roc-pc-rk3576/Kconfig new file mode 100644 index 00000000000..2fc0f913c37 --- /dev/null +++ b/board/firefly/roc-pc-rk3576/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROC_PC_RK3576 + +config SYS_BOARD + default "roc-pc-rk3576" + +config SYS_VENDOR + default "firefly" + +config SYS_CONFIG_NAME + default "roc-pc-rk3576" + +endif diff --git a/board/firefly/roc-pc-rk3576/MAINTAINERS b/board/firefly/roc-pc-rk3576/MAINTAINERS new file mode 100644 index 00000000000..aa8897c16fc --- /dev/null +++ b/board/firefly/roc-pc-rk3576/MAINTAINERS @@ -0,0 +1,7 @@ +ROC-RK3576-PC +M: Heiko Stuebner <heiko@sntech.de> +S: Maintained +F: board/firefly/roc-pc-rk3576 +F: include/configs/roc-pc-rk3576.h +F: configs/roc-pc-rk3576_defconfig +F: arch/arm/dts/rk3576-roc-pc* diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig index 5537788001a..965847d9650 100644 --- a/board/imgtec/boston/Kconfig +++ b/board/imgtec/boston/Kconfig @@ -9,6 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "boston" + +config ENV_SOURCE_FILE + default "boston" + config TEXT_BASE default 0x9fc00000 if 32BIT default 0xffffffff9fc00000 if 64BIT diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS index 07f6156ffcb..b03a6487db2 100644 --- a/board/imgtec/boston/MAINTAINERS +++ b/board/imgtec/boston/MAINTAINERS @@ -1,6 +1,7 @@ BOSTON BOARD -M: Paul Burton <paul.burton@mips.com> +M: Paul Burton <paulburton@kernel.org> S: Maintained +F: arch/mips/dts/boston-u-boot.dtsi F: board/imgtec/boston/ F: include/configs/boston.h F: configs/boston32r2_defconfig diff --git a/board/imgtec/boston/boston.env b/board/imgtec/boston/boston.env new file mode 100644 index 00000000000..796e0fd6bf9 --- /dev/null +++ b/board/imgtec/boston/boston.env @@ -0,0 +1,9 @@ +#ifdef CONFIG_64BIT +fdt_addr_r=0xffffffff80001000 +kernel_addr_r=0xffffffff88000000 +ramdisk_addr_r=0xffffffff8b000000 +#else +fdt_addr_r=0x80001000 +kernel_addr_r=0x88000000 +ramdisk_addr_r=0x8b000000 +#endif diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS index b1cf297f4fa..252c5e45ab5 100644 --- a/board/imgtec/malta/MAINTAINERS +++ b/board/imgtec/malta/MAINTAINERS @@ -1,5 +1,5 @@ MALTA BOARD -M: Paul Burton <paul.burton@mips.com> +M: Paul Burton <paulburton@kernel.org> S: Maintained F: board/imgtec/malta/ F: include/configs/malta.h diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index 4c8407bb676..7714076edf1 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -73,7 +73,11 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ - {0} /* timing parameters */ + {0}, /* timing parameters */ + { {0} }, /* electrical configuration */ + {0,}, /* electrical parameters */ + 0x30000, /* ODT configuration */ + 0x3, /* clock enable mask */ }; struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 1f2213902ed..4d7c9b9f80f 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -295,17 +295,16 @@ static int phytec_get_product_name(struct phytec_eeprom_data *data, switch (api2->som_type) { case 0: + case 1: + case 2: + case 3: som_type = api2->som_type; break; case 4: - som_type = 0; - break; case 5: som_type = 0; break; case 6: - som_type = 1; - break; case 7: som_type = 1; break; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6ecd3eb120f..1b0b664fa2b 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -359,9 +359,6 @@ static void set_fdtfile(void) */ static void set_fdt_addr(void) { - if (env_get("fdt_addr")) - return; - if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) return; @@ -602,6 +599,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) /* Bluetooth device address as provided by the firmware */ copy_property(fdt, fw_fdt, "/soc/serial@7e201000/bluetooth", "local-bd-address"); + + /* copy uart clk as provided by the firmware */ + copy_property(fdt, fw_fdt, "/clocks/clk-uart", "clock-frequency"); } int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/raspberrypi/rpi/rpi.env b/board/raspberrypi/rpi/rpi.env index 30228285edd..9ac9d6768ca 100644 --- a/board/raspberrypi/rpi/rpi.env +++ b/board/raspberrypi/rpi/rpi.env @@ -48,30 +48,33 @@ dfu_alt_info+=zImage fat 0 1 * * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't * conflict with something else. Reserving 1M for each of them at - * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty. + * 0x05400000-0x05500000 and 0x05500000-0x05600000 should be plenty. * * On ARM, both the DTB and any possible initrd must be loaded such that they * fit inside the lowmem mapping in Linux. In practice, this usually means not * more than ~700M away from the start of the kernel image but this number can * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line * parameter given to the kernel. So reserving memory from low to high - * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for - * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000. - * Even with the smallest possible CPU-GPU memory split of the CPU getting - * only 64M, the remaining 25M starting at 0x02700000 should allow quite - * large initrds before they start colliding with U-Boot. + * satisfies this constraint again. Reserving 1M at 0x05600000-0x05700000 for + * the DTB leaves rest of the free RAM to the initrd starting at 0x05700000. + * This means that the board must have at least 128MB of RAM available to + * U-Boot, more if the initrd is large. + * + * For compressed kernels, the maximum size is just under 32MB, with an area for + * decompression at 0x02000000 with space for 52MB, which is plenty for current + * kernels. + * + * limit bootm_size to 512MB so that all boot images stay within the bottom + * 512MB of memory */ -#ifdef CONFIG_ARM64 -fdt_high=ffffffffffffffff -initrd_high=ffffffffffffffff -#else -fdt_high=ffffffff -initrd_high=ffffffff -#endif +bootm_size=0x20000000 + kernel_addr_r=0x00080000 -scriptaddr=0x02400000 -pxefile_addr_r=0x02500000 -fdt_addr_r=0x02600000 -ramdisk_addr_r=0x02700000 +kernel_comp_addr_r=0x02000000 +kernel_comp_size=0x03400000 +scriptaddr=0x05400000 +pxefile_addr_r=0x05500000 +fdt_addr_r=0x05600000 +ramdisk_addr_r=0x05700000 boot_targets=mmc usb pxe dhcp diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 5f81be55b8e..8c9b42fe2bb 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -7,6 +7,12 @@ F: configs/evb-rk3328_defconfig F: arch/arm/dts/rk3328-evb.dts F: arch/arm/dts/rk3328-evb-u-boot.dtsi +GENERIC-RK3328 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/generic-rk3328_defconfig +F: arch/arm/dts/rk3328-generic* + NANOPI-R2C-RK3328 M: Tianling Shen <cnsztl@gmail.com> S: Maintained diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 8dab3fa70f5..8319db2e976 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -14,6 +14,12 @@ S: Maintained F: configs/eaidk-610-rk3399_defconfig F: arch/arm/dts/rk3399-eaidk-610* +GENERIC-RK3399 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/generic-rk3399_defconfig +F: arch/arm/dts/rk3399-generic* + KHADAS-EDGE M: Nick Xie <nick@khadas.com> S: Maintained diff --git a/board/sandbox/sandbox.env b/board/sandbox/sandbox.env index a2c19702d64..29197f56e95 100644 --- a/board/sandbox/sandbox.env +++ b/board/sandbox/sandbox.env @@ -8,6 +8,11 @@ stderr=serial,vidconsole ethaddr=02:00:11:22:33:44 eth6addr=02:00:11:22:33:47 ipaddr=192.0.2.1 +ipaddr2=192.0.2.3 +ipaddr3=192.0.2.4 +ipaddr5=192.0.2.6 +ipaddr6=192.0.2.7 +ipaddr7=192.0.2.8 /* * These are used for distro boot which is not supported. But once bootmethod diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c index 26031795b09..a8b111477ef 100644 --- a/board/socionext/developerbox/fwu_plat.c +++ b/board/socionext/developerbox/fwu_plat.c @@ -18,7 +18,7 @@ void set_dfu_alt_info(char *interface, char *devstr) struct mtd_info *mtd; int ret; - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); mtd_probe_devices(); diff --git a/board/theobroma-systems/common/Makefile b/board/theobroma-systems/common/Makefile new file mode 100644 index 00000000000..c1cadb4b913 --- /dev/null +++ b/board/theobroma-systems/common/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2025 Cherry Embedded Solutions GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifneq ($(CONFIG_XPL_BUILD),y) +obj-y += common.o +endif diff --git a/board/theobroma-systems/jaguar_rk3588/Makefile b/board/theobroma-systems/jaguar_rk3588/Makefile index d43bf194b68..38b73d2846c 100644 --- a/board/theobroma-systems/jaguar_rk3588/Makefile +++ b/board/theobroma-systems/jaguar_rk3588/Makefile @@ -5,6 +5,3 @@ # obj-y += jaguar_rk3588.o -ifneq ($(CONFIG_XPL_BUILD),y) -obj-y += ../common/common.o -endif diff --git a/board/theobroma-systems/puma_rk3399/Makefile b/board/theobroma-systems/puma_rk3399/Makefile index 2256e72cda1..d962b56f111 100644 --- a/board/theobroma-systems/puma_rk3399/Makefile +++ b/board/theobroma-systems/puma_rk3399/Makefile @@ -5,6 +5,3 @@ # obj-y += puma-rk3399.o -ifneq ($(CONFIG_XPL_BUILD),y) -obj-y += ../common/common.o -endif diff --git a/board/theobroma-systems/ringneck_px30/Makefile b/board/theobroma-systems/ringneck_px30/Makefile index 4d108f2d011..31ada1a6942 100644 --- a/board/theobroma-systems/ringneck_px30/Makefile +++ b/board/theobroma-systems/ringneck_px30/Makefile @@ -5,6 +5,3 @@ # obj-y += ringneck-px30.o -ifneq ($(CONFIG_XPL_BUILD),y) -obj-y += ../common/common.o -endif diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile index 94b0859eb35..900647735fb 100644 --- a/board/theobroma-systems/tiger_rk3588/Makefile +++ b/board/theobroma-systems/tiger_rk3588/Makefile @@ -5,6 +5,3 @@ # obj-y += tiger_rk3588.o -ifneq ($(CONFIG_XPL_BUILD),y) -obj-y += ../common/common.o -endif diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index c03aa3a368f..b5978acdded 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -41,6 +41,8 @@ config TI_COMMON_CMD_OPTIONS imply CMD_I2C imply CMD_MII imply CMD_MMC + imply CMD_MMC_REG + imply MMC_SPEED_MODE_SET imply CMD_NFS imply CMD_PART imply CMD_PING diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index deea6c71103..8ffe7429901 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -80,7 +80,7 @@ struct xilinx_board_description { }; static int highest_id = -1; -static struct xilinx_board_description *board_info; +static struct xilinx_board_description *board_info __section(".data"); #define XILINX_I2C_DETECTION_BITS sizeof(struct fru_common_hdr) @@ -468,6 +468,9 @@ int board_late_init_xilinx(void) ret |= env_set_addr("bootm_size", (void *)bootm_size); for (id = 0; id <= highest_id; id++) { + if (!board_info) + break; + desc = &board_info[id]; if (desc && desc->header == EEPROM_HEADER_MAGIC) { if (desc->manufacturer[0]) diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig deleted file mode 100644 index 2484429d3cb..00000000000 --- a/board/xilinx/versal-net/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 - 2022, Xilinx, Inc. -# Copyright (C) 2022, Advanced Micro Devices, Inc. -# - -if ARCH_VERSAL_NET - -config CMD_VERSAL_NET - bool "Enable Versal NET specific commands" - default y - depends on ZYNQMP_FIRMWARE - help - Select this to enable Versal NET specific commands. - Commands like versalnet loadpdi are enabled by this. - -endif diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile index f9ff07c11c6..2008d4e231c 100644 --- a/board/xilinx/versal-net/Makefile +++ b/board/xilinx/versal-net/Makefile @@ -7,4 +7,3 @@ # obj-y := board.o -obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 4d5913cff1d..65b2a451ad7 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -21,6 +21,8 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <zynqmp_firmware.h> +#include <versalpl.h> #include "../common/board.h" #include <linux/bitfield.h> @@ -29,10 +31,21 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_FPGA_VERSALPL) +static xilinx_desc versalpl = { + xilinx_versal_net, csu_dma, 1, &versal_op, 0, &versal_op, NULL, + FPGA_LEGACY +}; +#endif + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); +#if defined(CONFIG_FPGA_VERSALPL) + fpga_init(); + fpga_add(fpga_xilinx, &versalpl); +#endif return 0; } @@ -184,7 +197,11 @@ static u8 versal_net_get_bootmode(void) u8 bootmode; u32 reg = 0; - reg = readl(&crp_base->boot_mode_usr); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { + reg = zynqmp_pm_get_bootmode_reg(); + } else { + reg = readl(&crp_base->boot_mode_usr); + } if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c deleted file mode 100644 index e8b669f0fd4..00000000000 --- a/board/xilinx/versal-net/cmds.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023, Advanced Micro Devices, Inc. - * - * Michal Simek <michal.simek@amd.com> - */ - -#include <cpu_func.h> -#include <command.h> -#include <log.h> -#include <memalign.h> -#include <versalpl.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> - -/** - * do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the Versal NET load pdi command - * - * Return: return 0 on success, Error value if command fails. - * CMD_RET_USAGE incase of incorrect/missing parameters. - */ -static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 buf_lo, buf_hi; - u32 ret_payload[PAYLOAD_ARG_CNT]; - ulong addr, *pdi_buf; - size_t len; - int ret; - - if (argc != cmdtp->maxargs) { - debug("pdi_load: incorrect parameters passed\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtol(argv[1], NULL, 16); - if (!addr) { - debug("pdi_load: zero pdi_data address\n"); - return CMD_RET_USAGE; - } - - len = hextoul(argv[2], NULL); - if (!len) { - debug("pdi_load: zero size\n"); - return CMD_RET_USAGE; - } - - pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); - if ((ulong)addr != (ulong)pdi_buf) { - memcpy((void *)pdi_buf, (void *)addr, len); - debug("Pdi addr:0x%lx aligned to 0x%lx\n", - addr, (ulong)pdi_buf); - } - - flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); - - buf_lo = lower_32_bits((ulong)pdi_buf); - buf_hi = upper_32_bits((ulong)pdi_buf); - - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); - if (ret) - printf("PDI load failed with err: 0x%08x\n", ret); - - return cmd_process_error(cmdtp, ret); -} - -U_BOOT_LONGHELP(versalnet, - "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); - -U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text, - U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, - do_versalnet_load_pdi)); diff --git a/board/xilinx/versal/Kconfig b/board/xilinx/versal/Kconfig deleted file mode 100644 index c0cccc2068b..00000000000 --- a/board/xilinx/versal/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2020, Xilinx, Inc. -# -# SPDX-License-Identifier: GPL-2.0 - -if ARCH_VERSAL - -config CMD_VERSAL - bool "Enable Versal specific commands" - default y - depends on ZYNQMP_FIRMWARE - help - Enable Versal specific commands. - -endif diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index d912f2e74f3..761e084e77c 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -5,4 +5,3 @@ # obj-y := board.o -obj-$(CONFIG_CMD_VERSAL) += cmds.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 05530736751..9371c30ea27 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -27,6 +27,7 @@ #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> +#include <zynqmp_firmware.h> #include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,7 +44,11 @@ static u8 versal_get_bootmode(void) u8 bootmode; u32 reg = 0; - reg = readl(&crp_base->boot_mode_usr); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { + reg = zynqmp_pm_get_bootmode_reg(); + } else { + reg = readl(&crp_base->boot_mode_usr); + } if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; @@ -56,12 +61,18 @@ static u8 versal_get_bootmode(void) static u32 versal_multi_boot(void) { u8 bootmode = versal_get_bootmode(); + u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - return readl(0xF1110004); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) + reg = zynqmp_pm_get_pmc_multi_boot_reg(); + else + reg = readl(PMC_MULTI_BOOT_REG); + + return reg & PMC_MULTI_BOOT_MASK; } int board_init(void) @@ -272,6 +283,7 @@ static int boot_targets_setup(void) env_targets ? env_targets : ""); env_set("boot_targets", new_targets); + free(new_targets); } return 0; @@ -395,7 +407,7 @@ void configure_capsule_updates(void) ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); multiboot = env_get_hex("multiboot", multiboot); diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c deleted file mode 100644 index c78793573e8..00000000000 --- a/board/xilinx/versal/cmds.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek <michal.simek@amd.com> - */ - -#include <cpu_func.h> -#include <command.h> -#include <log.h> -#include <memalign.h> -#include <versalpl.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> - -static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 buf_lo, buf_hi; - u32 ret_payload[PAYLOAD_ARG_CNT]; - ulong addr, *pdi_buf; - size_t len; - int ret; - - if (argc != cmdtp->maxargs) { - debug("pdi_load: incorrect parameters passed\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtol(argv[2], NULL, 16); - if (!addr) { - debug("pdi_load: zero pdi_data address\n"); - return CMD_RET_USAGE; - } - - len = hextoul(argv[3], NULL); - if (!len) { - debug("pdi_load: zero size\n"); - return CMD_RET_USAGE; - } - - pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); - if ((ulong)addr != (ulong)pdi_buf) { - memcpy((void *)pdi_buf, (void *)addr, len); - debug("Pdi addr:0x%lx aligned to 0x%lx\n", - addr, (ulong)pdi_buf); - } - - flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); - - buf_lo = lower_32_bits((ulong)pdi_buf); - buf_hi = upper_32_bits((ulong)pdi_buf); - - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); - if (ret) - printf("PDI load failed with err: 0x%08x\n", ret); - - return ret; -} - -static struct cmd_tbl cmd_versal_sub[] = { - U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""), -}; - -/** - * do_versal - Handle the "versal" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the versal specific commands - * - * Return: return 0 on success, Error value if command fails. - * CMD_RET_USAGE incase of incorrect/missing parameters. - */ -static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct cmd_tbl *c; - int ret = CMD_RET_USAGE; - - if (argc < 2) - return CMD_RET_USAGE; - - c = find_cmd_tbl(argv[1], &cmd_versal_sub[0], - ARRAY_SIZE(cmd_versal_sub)); - if (c) - ret = c->cmd(c, flag, argc, argv); - - return cmd_process_error(c, ret); -} - -U_BOOT_LONGHELP(versal, - "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); - -U_BOOT_CMD(versal, 4, 1, do_versal, - "versal sub-system", - versal_help_text -); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5efef61fa8f..04dee1b8269 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -175,7 +175,7 @@ void configure_capsule_updates(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { #if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 33205d4cf1d..735ef3cd1be 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -668,7 +668,7 @@ void configure_capsule_updates(void) ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); multiboot = multi_boot(); if (multiboot < 0) diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 75b604a1f76..89f48c03586 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -42,7 +42,7 @@ script_offset_f=0x3e80000 script_size_f=0x80000 scriptaddr=0x20000000 usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi -preboot=setenv boot_targets; setenv modeboot; run board_setup +preboot=setenv boot_targets; setenv modeboot; run board_setup; usb start usb_pgood_delay=1000 # SOM specific boot methods diff --git a/cmd/Kconfig b/cmd/Kconfig index c2ce519d1e3..2d31abcef73 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -3081,4 +3081,21 @@ config CMD_MESON help Enable useful commands for the Meson Soc family developed by Amlogic Inc. +config CMD_SPAWN + bool "spawn and wait commands" + depends on UTHREAD + help + spawn runs a command in the background and sets the job_id environment + variable. wait is used to suspend the shell execution until one or more + jobs are complete. + +config CMD_SPAWN_NUM_JOBS + int "Maximum number of simultaneous jobs for spawn" + default 16 + help + Job identifiers are in the range 1..CMD_SPAWN_NUM_JOBS. In other words + there can be no more that CMD_SPAWN_NUM_JOBS running simultaneously. + When a jobs exits, its identifier is available to be re-used by the next + spawn command. + endif diff --git a/cmd/Makefile b/cmd/Makefile index 8f0cee8d714..80cf70b7fe8 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -239,6 +239,8 @@ obj-$(CONFIG_CMD_SCP03) += scp03.o obj-$(CONFIG_HUSH_SELECTABLE) += cli.o +obj-$(CONFIG_CMD_SPAWN) += spawn.o + obj-$(CONFIG_ARM) += arm/ obj-$(CONFIG_RISCV) += riscv/ obj-$(CONFIG_SANDBOX) += sandbox/ diff --git a/cmd/bootefi.c b/cmd/bootefi.c index dce8285b047..cea6d356ee6 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -38,6 +38,9 @@ static efi_status_t bootefi_run_prepare(const char *load_options_path, if (ret != EFI_SUCCESS) return ret; + (*image_objp)->auth_status = EFI_IMAGE_AUTH_PASSED; + (*image_objp)->entry = efi_selftest; + /* Transfer environment variable as load options */ return efi_env_set_load_options((efi_handle_t)*image_objp, load_options_path, @@ -106,8 +109,8 @@ static int do_efi_selftest(void) return CMD_RET_FAILURE; /* Execute the test */ - ret = EFI_CALL(efi_selftest(&image_obj->header, &systab)); - free(loaded_image_info->load_options); + ret = do_bootefi_exec(&image_obj->header, + loaded_image_info->load_options); efi_free_pool(test_device_path); efi_free_pool(test_image_path); if (ret != EFI_SUCCESS) diff --git a/cmd/cls.c b/cmd/cls.c index 4bee8a18305..b1e0619334b 100644 --- a/cmd/cls.c +++ b/cmd/cls.c @@ -18,4 +18,4 @@ static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } -U_BOOT_CMD(cls, 1, 1, do_video_clear, "clear screen", ""); +U_BOOT_CMD(cls, 1, 0, do_video_clear, "clear screen", ""); diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index e08b6ba4a5d..629bf1b82c7 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -2283,26 +2283,11 @@ static efi_status_t eficonfig_init(void) { efi_status_t ret = EFI_SUCCESS; static bool init; - struct efi_handler *handler; unsigned long columns, rows; if (!init) { - ret = efi_search_protocol(efi_root, &efi_guid_text_input_protocol, &handler); - if (ret != EFI_SUCCESS) - return ret; - - ret = efi_protocol_open(handler, (void **)&cin, efi_root, NULL, - EFI_OPEN_PROTOCOL_GET_PROTOCOL); - if (ret != EFI_SUCCESS) - return ret; - ret = efi_search_protocol(efi_root, &efi_guid_text_output_protocol, &handler); - if (ret != EFI_SUCCESS) - return ret; - - ret = efi_protocol_open(handler, (void **)&cout, efi_root, NULL, - EFI_OPEN_PROTOCOL_GET_PROTOCOL); - if (ret != EFI_SUCCESS) - return ret; + cout = systab.con_out; + cin = systab.con_in; cout->query_mode(cout, cout->mode->mode, &columns, &rows); avail_row = rows - (EFICONFIG_MENU_HEADER_ROW_NUM + diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 5e4ffc40d72..6b7d9ee061d 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -931,7 +931,7 @@ static int check_image_header(void) size = le32_to_cpu(hdr->blocksize); if (hdr->blockid == 0x78) { /* SATA id */ - struct blk_desc *blk_dev = IS_ENABLED(BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL; + struct blk_desc *blk_dev = IS_ENABLED(CONFIG_BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL; unsigned long blksz = blk_dev ? blk_dev->blksz : 512; offset *= blksz; } diff --git a/cmd/net.c b/cmd/net.c index 79525f73a51..eaa1de5295f 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -456,8 +456,7 @@ static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc, } #if defined(CONFIG_CMD_PING) -static int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { if (argc < 2) return CMD_RET_USAGE; diff --git a/cmd/pxe.c b/cmd/pxe.c index 37b8dea6ad6..0f26b3b4219 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -13,7 +13,6 @@ #include "pxe_utils.h" -#ifdef CONFIG_CMD_NET const char *pxe_default_paths[] = { #ifdef CONFIG_SYS_SOC #ifdef CONFIG_SYS_BOARD @@ -331,5 +330,3 @@ U_BOOT_CMD(pxe, 4, 1, do_pxe, "get [" USE_IP6_CMD_PARAM "] - try to retrieve a pxe file using tftp\n" "pxe boot [pxefile_addr_r] [-ipv6] - boot from the pxe file at pxefile_addr_r\n" ); - -#endif /* CONFIG_CMD_NET */ diff --git a/cmd/spawn.c b/cmd/spawn.c new file mode 100644 index 00000000000..eddbcb792b3 --- /dev/null +++ b/cmd/spawn.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#include <command.h> +#include <console.h> +#include <malloc.h> +#include <vsprintf.h> +#include <uthread.h> + +/* Spawn arguments and job index */ +struct spa { + int argc; + char **argv; + unsigned int job_idx; +}; + +/* + * uthread group identifiers for each running job + * 0: job slot available, != 0: uthread group id + * Note that job[0] is job_id 1, job[1] is job_id 2 etc. + */ +static unsigned int job[CONFIG_CMD_SPAWN_NUM_JOBS]; +/* Return values of the commands run as jobs */ +static enum command_ret_t job_ret[CONFIG_CMD_SPAWN_NUM_JOBS]; + +static void spa_free(struct spa *spa) +{ + int i; + + if (!spa) + return; + + for (i = 0; i < spa->argc; i++) + free(spa->argv[i]); + free(spa->argv); + free(spa); +} + +static struct spa *spa_create(int argc, char *const argv[]) +{ + struct spa *spa; + int i; + + spa = calloc(1, sizeof(*spa)); + if (!spa) + return NULL; + spa->argc = argc; + spa->argv = malloc(argc * sizeof(char *)); + if (!spa->argv) + goto err; + for (i = 0; i < argc; i++) { + spa->argv[i] = strdup(argv[i]); + if (!spa->argv[i]) + goto err; + } + return spa; +err: + spa_free(spa); + return NULL; +} + +static void spawn_thread(void *arg) +{ + struct spa *spa = (struct spa *)arg; + ulong cycles = 0; + int repeatable = 0; + + job_ret[spa->job_idx] = cmd_process(0, spa->argc, spa->argv, + &repeatable, &cycles); + spa_free(spa); +} + +static unsigned int next_job_id(void) +{ + int i; + + for (i = 0; i < CONFIG_CMD_SPAWN_NUM_JOBS; i++) + if (!job[i]) + return i + 1; + + /* No job available */ + return 0; +} + +static void refresh_jobs(void) +{ + int i; + + for (i = 0; i < CONFIG_CMD_SPAWN_NUM_JOBS; i++) + if (job[i] && uthread_grp_done(job[i])) + job[i] = 0; + +} + +static int do_spawn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + unsigned int id; + unsigned int idx; + struct spa *spa; + int ret; + + if (argc == 1) + return CMD_RET_USAGE; + + spa = spa_create(argc - 1, argv + 1); + if (!spa) + return CMD_RET_FAILURE; + + refresh_jobs(); + + id = next_job_id(); + if (!id) + return CMD_RET_FAILURE; + idx = id - 1; + + job[idx] = uthread_grp_new_id(); + + ret = uthread_create(NULL, spawn_thread, spa, 0, job[idx]); + if (ret) { + job[idx] = 0; + return CMD_RET_FAILURE; + } + + ret = env_set_ulong("job_id", id); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(spawn, CONFIG_SYS_MAXARGS, 0, do_spawn, + "run commands and summarize execution time", + "command [args...]\n"); + +static enum command_ret_t wait_job(unsigned int idx) +{ + int prev = disable_ctrlc(false); + + while (!uthread_grp_done(job[idx])) { + if (ctrlc()) { + puts("<INTERRUPT>\n"); + disable_ctrlc(prev); + return CMD_RET_FAILURE; + } + uthread_schedule(); + } + + job[idx] = 0; + disable_ctrlc(prev); + + return job_ret[idx]; +} + +static int do_wait(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + enum command_ret_t ret = CMD_RET_SUCCESS; + unsigned long id; + unsigned int idx; + int i; + + if (argc == 1) { + for (i = 0; i < CONFIG_CMD_SPAWN_NUM_JOBS; i++) + if (job[i]) + ret = wait_job(i); + } else { + for (i = 1; i < argc; i++) { + id = dectoul(argv[i], NULL); + if (id < 0 || id > CONFIG_CMD_SPAWN_NUM_JOBS) + return CMD_RET_USAGE; + idx = (int)id - 1; + ret = wait_job(idx); + } + } + + return ret; +} + +U_BOOT_CMD(wait, CONFIG_SYS_MAXARGS, 0, do_wait, + "wait for one or more jobs to complete", + "[job_id ...]\n" + " - Wait until all specified jobs have exited and return the\n" + " exit status of the last job waited for. When no job_id is\n" + " given, wait for all the background jobs.\n"); diff --git a/common/board_f.c b/common/board_f.c index c4561874496..bff465d9cb2 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -38,6 +38,7 @@ #include <spl.h> #include <status_led.h> #include <sysreset.h> +#include <time.h> #include <timer.h> #include <trace.h> #include <upl.h> @@ -476,6 +477,13 @@ static int reserve_trace(void) static int reserve_uboot(void) { + /* + * This should be the first place GD_FLG_SKIP_RELOC is read from. + * Set GD_FLG_SKIP_RELOC flag if CONFIG_SKIP_RELOCATE is enabled. + */ + if (CONFIG_IS_ENABLED(SKIP_RELOCATE)) + gd->flags |= GD_FLG_SKIP_RELOC; + if (!(gd->flags & GD_FLG_SKIP_RELOC)) { /* * reserve memory for U-Boot code, data & bss @@ -753,7 +761,7 @@ static int setup_reloc(void) return 0; } -#ifdef CONFIG_OF_BOARD_FIXUP +#if CONFIG_IS_ENABLED(OF_BOARD_FIXUP) static int fix_fdt(void) { return board_fix_fdt((void *)gd->fdt_blob); @@ -881,81 +889,86 @@ static int initf_upl(void) return 0; } -static const init_fnc_t init_sequence_f[] = { - setup_mon_len, -#ifdef CONFIG_OF_CONTROL - fdtdec_setup, +static void initcall_run_f(void) +{ + /* + * Please do not add logic to this function (variables, if (), etc.). + * For simplicity it should remain an ordered list of function calls. + */ + INITCALL(setup_mon_len); +#if CONFIG_IS_ENABLED(OF_CONTROL) + INITCALL(fdtdec_setup); #endif -#ifdef CONFIG_TRACE_EARLY - trace_early_init, +#if CONFIG_IS_ENABLED(TRACE_EARLY) + INITCALL(trace_early_init); #endif - initf_malloc, - initf_upl, - log_init, - initf_bootstage, /* uses its own timer, so does not need DM */ - event_init, - bloblist_maybe_init, - setup_spl_handoff, -#if defined(CONFIG_CONSOLE_RECORD_INIT_F) - console_record_init, + INITCALL(initf_malloc); + INITCALL(initf_upl); + INITCALL(log_init); + INITCALL(initf_bootstage); /* uses its own timer, so does not need DM */ + INITCALL(event_init); + INITCALL(bloblist_maybe_init); + INITCALL(setup_spl_handoff); +#if CONFIG_IS_ENABLED(CONSOLE_RECORD_INIT_F) + INITCALL(console_record_init); #endif - INITCALL_EVENT(EVT_FSP_INIT_F), - arch_cpu_init, /* basic arch cpu dependent setup */ - mach_cpu_init, /* SoC/machine dependent CPU setup */ - initf_dm, -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, + INITCALL_EVT(EVT_FSP_INIT_F); + INITCALL(arch_cpu_init); /* basic arch cpu dependent setup */ + INITCALL(mach_cpu_init); /* SoC/machine dependent CPU setup */ + INITCALL(initf_dm); +#if CONFIG_IS_ENABLED(BOARD_EARLY_INIT_F) + INITCALL(board_early_init_f); #endif #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) /* get CPU and bus clocks according to the environment variable */ - get_clocks, /* get CPU and bus clocks (etc.) */ + INITCALL(get_clocks); /* get CPU and bus clocks (etc.) */ #endif #if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR)) - timer_init, /* initialize timer */ + INITCALL(timer_init); /* initialize timer */ #endif -#if defined(CONFIG_BOARD_POSTCLK_INIT) - board_postclk_init, +#if CONFIG_IS_ENABLED(BOARD_POSTCLK_INIT) + INITCALL(board_postclk_init); #endif - env_init, /* initialize environment */ - init_baud_rate, /* initialze baudrate settings */ - serial_init, /* serial communications setup */ - console_init_f, /* stage 1 init of console */ - display_options, /* say that we are here */ - display_text_info, /* show debugging info if required */ - checkcpu, -#if defined(CONFIG_SYSRESET) - print_resetinfo, + INITCALL(env_init); /* initialize environment */ + INITCALL(init_baud_rate); /* initialze baudrate settings */ + INITCALL(serial_init); /* serial communications setup */ + INITCALL(console_init_f); /* stage 1 init of console */ + INITCALL(display_options); /* say that we are here */ + INITCALL(display_text_info); /* show debugging info if required */ + INITCALL(checkcpu); +#if CONFIG_IS_ENABLED(SYSRESET) + INITCALL(print_resetinfo); #endif -#if defined(CONFIG_DISPLAY_CPUINFO) - print_cpuinfo, /* display cpu info (and speed) */ + /* display cpu info (and speed) */ +#if CONFIG_IS_ENABLED(DISPLAY_CPUINFO) + INITCALL(print_cpuinfo); #endif -#if defined(CONFIG_DTB_RESELECT) - embedded_dtb_select, +#if CONFIG_IS_ENABLED(DTB_RESELECT) + INITCALL(embedded_dtb_select); #endif -#if defined(CONFIG_DISPLAY_BOARDINFO) - show_board_info, +#if CONFIG_IS_ENABLED(DISPLAY_BOARDINFO) + INITCALL(show_board_info); #endif - INIT_FUNC_WATCHDOG_INIT - INITCALL_EVENT(EVT_MISC_INIT_F), - INIT_FUNC_WATCHDOG_RESET + WATCHDOG_INIT(); + INITCALL_EVT(EVT_MISC_INIT_F); + WATCHDOG_RESET(); #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - init_func_i2c, + INITCALL(init_func_i2c); #endif - announce_dram_init, - dram_init, /* configure available RAM banks */ -#ifdef CONFIG_POST - post_init_f, + INITCALL(announce_dram_init); + INITCALL(dram_init); /* configure available RAM banks */ +#if CONFIG_IS_ENABLED(POST) + INITCALL(post_init_f); #endif - INIT_FUNC_WATCHDOG_RESET + WATCHDOG_RESET(); #if defined(CFG_SYS_DRAM_TEST) - testdram, + INITCALL(testdram); #endif /* CFG_SYS_DRAM_TEST */ - INIT_FUNC_WATCHDOG_RESET - -#ifdef CONFIG_POST - init_post, + WATCHDOG_RESET(); +#if CONFIG_IS_ENABLED(POST) + INITCALL(init_post); #endif - INIT_FUNC_WATCHDOG_RESET + WATCHDOG_RESET(); /* * Now that we have DRAM mapped and working, we can * relocate the code and continue running from DRAM. @@ -968,48 +981,51 @@ static const init_fnc_t init_sequence_f[] = { * - monitor code * - board info struct */ - setup_dest_addr, -#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_OF_INITIAL_DTB_READONLY) - fix_fdt, + INITCALL(setup_dest_addr); +#if CONFIG_IS_ENABLED(OF_BOARD_FIXUP) && \ + !CONFIG_IS_ENABLED(OF_INITIAL_DTB_READONLY) + INITCALL(fix_fdt); #endif #ifdef CFG_PRAM - reserve_pram, + INITCALL(reserve_pram); #endif - reserve_round_4k, - setup_relocaddr_from_bloblist, - arch_reserve_mmu, - reserve_video, - reserve_trace, - reserve_uboot, - reserve_malloc, - reserve_board, - reserve_global_data, - reserve_fdt, -#if defined(CONFIG_OF_BOARD_FIXUP) && defined(CONFIG_OF_INITIAL_DTB_READONLY) - reloc_fdt, - fix_fdt, + INITCALL(reserve_round_4k); + INITCALL(setup_relocaddr_from_bloblist); + INITCALL(arch_reserve_mmu); + INITCALL(reserve_video); + INITCALL(reserve_trace); + INITCALL(reserve_uboot); + INITCALL(reserve_malloc); + INITCALL(reserve_board); + INITCALL(reserve_global_data); + INITCALL(reserve_fdt); +#if CONFIG_IS_ENABLED(OF_BOARD_FIXUP) && \ + CONFIG_IS_ENABLED(OF_INITIAL_DTB_READONLY) + INITCALL(reloc_fdt); + INITCALL(fix_fdt); #endif - reserve_bootstage, - reserve_bloblist, - reserve_arch, - reserve_stacks, - dram_init_banksize, - show_dram_config, - INIT_FUNC_WATCHDOG_RESET - setup_bdinfo, - display_new_sp, - INIT_FUNC_WATCHDOG_RESET -#if !defined(CONFIG_OF_BOARD_FIXUP) || !defined(CONFIG_OF_INITIAL_DTB_READONLY) - reloc_fdt, + INITCALL(reserve_bootstage); + INITCALL(reserve_bloblist); + INITCALL(reserve_arch); + INITCALL(reserve_stacks); + INITCALL(dram_init_banksize); + INITCALL(show_dram_config); + WATCHDOG_RESET(); + INITCALL(setup_bdinfo); + INITCALL(display_new_sp); + WATCHDOG_RESET(); +#if !CONFIG_IS_ENABLED(OF_BOARD_FIXUP) || \ + !CONFIG_IS_ENABLED(INITIAL_DTB_READONLY) + INITCALL(reloc_fdt); #endif - reloc_bootstage, - reloc_bloblist, - setup_reloc, -#if defined(CONFIG_X86) || defined(CONFIG_ARC) - copy_uboot_to_ram, - do_elf_reloc_fixups, + INITCALL(reloc_bootstage); + INITCALL(reloc_bloblist); + INITCALL(setup_reloc); +#if CONFIG_IS_ENABLED(X86) || CONFIG_IS_ENABLED(ARC) + INITCALL(copy_uboot_to_ram); + INITCALL(do_elf_reloc_fixups); #endif - clear_bss, + INITCALL(clear_bss); /* * Deregister all cyclic functions before relocation, so that * gd->cyclic_list does not contain any references to pre-relocation @@ -1019,12 +1035,11 @@ static const init_fnc_t init_sequence_f[] = { * This should happen as late as possible so that the window where a * watchdog device is not serviced is as small as possible. */ - cyclic_unregister_all, -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) - jump_to_copy, + INITCALL(cyclic_unregister_all); +#if !CONFIG_IS_ENABLED(ARM) && !CONFIG_IS_ENABLED(SANDBOX) + INITCALL(jump_to_copy); #endif - NULL, -}; +} void board_init_f(ulong boot_flags) { @@ -1034,8 +1049,7 @@ void board_init_f(ulong boot_flags) gd->flags &= ~GD_FLG_HAVE_CONSOLE; gd->boardf = &boardf; - if (initcall_run_list(init_sequence_f)) - hang(); + initcall_run_f(); #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ @@ -1049,8 +1063,8 @@ void board_init_f(ulong boot_flags) /* * For now this code is only used on x86. * - * init_sequence_f_r is the list of init functions which are run when - * U-Boot is executing from Flash with a semi-limited 'C' environment. + * Run init functions which are run when U-Boot is executing from Flash with a + * semi-limited 'C' environment. * The following limitations must be considered when implementing an * '_f_r' function: * - 'static' variables are read-only @@ -1063,18 +1077,16 @@ void board_init_f(ulong boot_flags) * NOTE: At present only x86 uses this route, but it is intended that * all archs will move to this when generic relocation is implemented. */ -static const init_fnc_t init_sequence_f_r[] = { -#if !CONFIG_IS_ENABLED(X86_64) - init_cache_f_r, +static void initcall_run_f_r(void) +{ +#if CONFIG_IS_ENABLED(X86_64) + INITCALL(init_cache_f_r); #endif - - NULL, -}; +} void board_init_f_r(void) { - if (initcall_run_list(init_sequence_f_r)) - hang(); + initcall_run_f_r(); /* * The pre-relocation drivers may be using memory that has now gone diff --git a/common/board_r.c b/common/board_r.c index f12e0c848e7..bc6fd6448c2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -509,7 +509,7 @@ static int initr_boot_led_on(void) return 0; } -#if defined(CONFIG_CMD_NET) +#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP) static int initr_net(void) { puts("Net: "); @@ -603,21 +603,24 @@ static int run_main_loop(void) } /* - * Over time we hope to remove these functions with code fragments and - * stub functions, and instead call the relevant function directly. - * - * We also hope to remove most of the driver-related init and do it if/when - * the driver is later used. + * Over time we hope to remove most of the driver-related init and do it + * if/when the driver is later used. * * TODO: perhaps reset the watchdog in the initcall function after each call? */ -static init_fnc_t init_sequence_r[] = { - initr_trace, - initr_reloc, - event_init, + +static void initcall_run_r(void) +{ + /* + * Please do not add logic to this function (variables, if (), etc.). + * For simplicity it should remain an ordered list of function calls. + */ + INITCALL(initr_trace); + INITCALL(initr_reloc); + INITCALL(event_init); /* TODO: could x86/PPC have this also perhaps? */ -#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) - initr_caches, +#if CONFIG_IS_ENABLED(ARM) || CONFIG_IS_ENABLED(RISCV) + INITCALL(initr_caches); /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. * A temporary mapping of IFC high region is since removed, * so environmental variables in NOR flash is not available @@ -625,29 +628,30 @@ static init_fnc_t init_sequence_r[] = { * region. */ #endif - initr_reloc_global_data, -#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) - initr_unlock_ram_in_cache, + INITCALL(initr_reloc_global_data); +#if CONFIG_IS_ENABLED(SYS_INIT_RAM_LOCK) && CONFIG_IS_ENABLED(E500) + INITCALL(initr_unlock_ram_in_cache); #endif - initr_barrier, - initr_malloc, - log_init, - initr_bootstage, /* Needs malloc() but has its own timer */ -#if defined(CONFIG_CONSOLE_RECORD) - console_record_init, + INITCALL(initr_barrier); + INITCALL(initr_malloc); + INITCALL(log_init); + INITCALL(initr_bootstage); /* Needs malloc() but has its own timer */ +#if CONFIG_IS_ENABLED(CONSOLE_RECORD) + INITCALL(console_record_init); #endif -#ifdef CONFIG_SYS_NONCACHED_MEMORY - noncached_init, +#if CONFIG_IS_ENABLED(SYS_NONCACHED_MEMORY) + INITCALL(noncached_init); #endif - initr_of_live, -#ifdef CONFIG_DM - initr_dm, + INITCALL(initr_of_live); +#if CONFIG_IS_ENABLED(DM) + INITCALL(initr_dm); #endif -#ifdef CONFIG_ADDR_MAP - init_addr_map, +#if CONFIG_IS_ENABLED(ADDR_MAP) + INITCALL(init_addr_map); #endif -#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) || defined(CONFIG_SANDBOX) - board_init, /* Setup chipselects */ +#if CONFIG_IS_ENABLED(ARM) || CONFIG_IS_ENABLED(RISCV) || \ + CONFIG_IS_ENABLED(SANDBOX) + INITCALL(board_init); /* Setup chipselects */ #endif /* * TODO: printing of the clock inforamtion of the board is now @@ -655,139 +659,141 @@ static init_fnc_t init_sequence_r[] = { * davinci SOC's is added. Remove this check once all the board * implement this. */ -#ifdef CONFIG_CLOCKS - set_cpu_clk_info, /* Setup clock information */ +#if CONFIG_IS_ENABLED(CLOCKS) + INITCALL(set_cpu_clk_info); #endif - initr_lmb, -#ifdef CONFIG_EFI_LOADER - efi_memory_init, + INITCALL(initr_lmb); +#if CONFIG_IS_ENABLED(EFI_LOADER) + INITCALL(efi_memory_init); #endif -#ifdef CONFIG_BINMAN_FDT - initr_binman, +#if CONFIG_IS_ENABLED(BINMAN_FDT) + INITCALL(initr_binman); #endif -#ifdef CONFIG_FSP_VERSION2 - arch_fsp_init_r, +#if CONFIG_IS_ENABLED(FSP_VERSION2) + INITCALL(arch_fsp_init_r); #endif - initr_dm_devices, - stdio_init_tables, - serial_initialize, - initr_announce, - dm_announce, + INITCALL(initr_dm_devices); + INITCALL(stdio_init_tables); + INITCALL(serial_initialize); + INITCALL(initr_announce); + INITCALL(dm_announce); #if CONFIG_IS_ENABLED(WDT) - initr_watchdog, + INITCALL(initr_watchdog); #endif - INIT_FUNC_WATCHDOG_RESET - arch_initr_trap, -#if defined(CONFIG_BOARD_EARLY_INIT_R) - board_early_init_r, + WATCHDOG_RESET(); + INITCALL(arch_initr_trap); +#if CONFIG_IS_ENABLED(BOARD_EARLY_INIT_R) + INITCALL(board_early_init_r); #endif - INIT_FUNC_WATCHDOG_RESET -#ifdef CONFIG_POST - post_output_backlog, + WATCHDOG_RESET(); +#if CONFIG_IS_ENABLED(POST) + INITCALL(post_output_backlog); #endif - INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PCI_INIT_R) && defined(CONFIG_SYS_EARLY_PCI_INIT) + WATCHDOG_RESET(); +#if CONFIG_IS_ENABLED(PCI_INIT_R) && CONFIG_IS_ENABLED(SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, * because PCU resources are crucial for flash access on some boards. */ - pci_init, + INITCALL(pci_init); #endif -#ifdef CONFIG_ARCH_EARLY_INIT_R - arch_early_init_r, +#if CONFIG_IS_ENABLED(ARCH_EARLY_INIT_R) + INITCALL(arch_early_init_r); #endif - power_init_board, -#ifdef CONFIG_MTD_NOR_FLASH - initr_flash, + INITCALL(power_init_board); +#if CONFIG_IS_ENABLED(MTD_NOR_FLASH) + INITCALL(initr_flash); #endif - INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) + WATCHDOG_RESET(); +#if CONFIG_IS_ENABLED(PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86) /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r, + INITCALL(cpu_init_r); #endif -#ifdef CONFIG_EFI_LOADER - efi_init_early, +#if CONFIG_IS_ENABLED(EFI_LOADER) + INITCALL(efi_init_early); #endif -#ifdef CONFIG_CMD_NAND - initr_nand, +#if CONFIG_IS_ENABLED(CMD_NAND) + INITCALL(initr_nand); #endif -#ifdef CONFIG_CMD_ONENAND - initr_onenand, +#if CONFIG_IS_ENABLED(CMD_ONENAND) + INITCALL(initr_onenand); #endif -#ifdef CONFIG_MMC - initr_mmc, +#if CONFIG_IS_ENABLED(MMC) + INITCALL(initr_mmc); #endif -#ifdef CONFIG_XEN - xen_init, +#if CONFIG_IS_ENABLED(XEN) + INITCALL(xen_init); #endif -#ifdef CONFIG_PVBLOCK - initr_pvblock, +#if CONFIG_IS_ENABLED(PVBLOCK) + INITCALL(initr_pvblock); #endif - initr_env, -#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS - initr_malloc_bootparams, + INITCALL(initr_env); +#if CONFIG_IS_ENABLED(SYS_MALLOC_BOOTPARAMS) + INITCALL(initr_malloc_bootparams); #endif - INIT_FUNC_WATCHDOG_RESET - cpu_secondary_init_r, -#if defined(CONFIG_ID_EEPROM) - mac_read_from_eeprom, + WATCHDOG_RESET(); + INITCALL(cpu_secondary_init_r); +#if CONFIG_IS_ENABLED(ID_EEPROM) + INITCALL(mac_read_from_eeprom); #endif - INITCALL_EVENT(EVT_SETTINGS_R), - INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PCI_INIT_R) && !defined(CONFIG_SYS_EARLY_PCI_INIT) + INITCALL_EVT(EVT_SETTINGS_R); + WATCHDOG_RESET(); +#if CONFIG_IS_ENABLED(PCI_INIT_R) && !CONFIG_IS_ENABLED(SYS_EARLY_PCI_INIT) /* * Do pci configuration */ - pci_init, + INITCALL(pci_init); #endif - stdio_add_devices, - jumptable_init, -#ifdef CONFIG_API - api_init, + INITCALL(stdio_add_devices); + INITCALL(jumptable_init); +#if CONFIG_IS_ENABLED(API) + INITCALL(api_init); #endif - console_init_r, /* fully init console as a device */ -#ifdef CONFIG_DISPLAY_BOARDINFO_LATE - console_announce_r, - show_board_info, + INITCALL(console_init_r); /* fully init console as a device */ +#if CONFIG_IS_ENABLED(DISPLAY_BOARDINFO_LATE) + INITCALL(console_announce_r); + INITCALL(show_board_info); #endif -#ifdef CONFIG_ARCH_MISC_INIT - arch_misc_init, /* miscellaneous arch-dependent init */ + /* miscellaneous arch-dependent init */ +#if CONFIG_IS_ENABLED(ARCH_MISC_INIT) + INITCALL(arch_misc_init); #endif -#ifdef CONFIG_MISC_INIT_R - misc_init_r, /* miscellaneous platform-dependent init */ + /* miscellaneous platform-dependent init */ +#if CONFIG_IS_ENABLED(MISC_INIT_R) + INITCALL(misc_init_r); #endif - INIT_FUNC_WATCHDOG_RESET -#ifdef CONFIG_CMD_KGDB - kgdb_init, + WATCHDOG_RESET(); +#if CONFIG_IS_ENABLED(CMD_KGDB) + INITCALL(kgdb_init); #endif - interrupt_init, + INITCALL(interrupt_init); #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) - timer_init, /* initialize timer */ + INITCALL(timer_init); /* initialize timer */ #endif - initr_status_led, - initr_boot_led_blink, + INITCALL(initr_status_led); + INITCALL(initr_boot_led_blink); /* PPC has a udelay(20) here dating from 2002. Why? */ -#ifdef CONFIG_BOARD_LATE_INIT - board_late_init, +#if CONFIG_IS_ENABLED(BOARD_LATE_INIT) + INITCALL(board_late_init); #endif -#ifdef CONFIG_PCI_ENDPOINT - pci_ep_init, +#if CONFIG_IS_ENABLED(PCI_ENDPOINT) + INITCALL(pci_ep_init); #endif -#if defined(CONFIG_CMD_NET) - INIT_FUNC_WATCHDOG_RESET - initr_net, +#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP) + WATCHDOG_RESET(); + INITCALL(initr_net); #endif -#ifdef CONFIG_POST - initr_post, +#if CONFIG_IS_ENABLED(POST) + INITCALL(initr_post); #endif - INIT_FUNC_WATCHDOG_RESET - INITCALL_EVENT(EVT_LAST_STAGE_INIT), + WATCHDOG_RESET(); + INITCALL_EVT(EVT_LAST_STAGE_INIT); #if defined(CFG_PRAM) - initr_mem, + INITCALL(initr_mem); #endif - initr_boot_led_on, - run_main_loop, -}; + INITCALL(initr_boot_led_on); + INITCALL(run_main_loop); +} void board_init_r(gd_t *new_gd, ulong dest_addr) { @@ -814,8 +820,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) #endif gd->flags &= ~GD_FLG_LOG_READY; - if (initcall_run_list(init_sequence_r)) - hang(); + initcall_run_r(); /* NOTREACHED - run_main_loop() does not return */ hang(); diff --git a/common/cyclic.c b/common/cyclic.c index fad071a39c6..b695f092f52 100644 --- a/common/cyclic.c +++ b/common/cyclic.c @@ -16,6 +16,7 @@ #include <linux/list.h> #include <asm/global_data.h> #include <u-boot/schedule.h> +#include <uthread.h> DECLARE_GLOBAL_DATA_PTR; @@ -100,6 +101,8 @@ void schedule(void) */ if (gd) cyclic_run(); + + uthread_schedule(); } int cyclic_unregister_all(void) diff --git a/common/iomux.c b/common/iomux.c index 1224c15eb71..4844df51fbe 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -131,7 +131,7 @@ int iomux_doenv(const int console, const char *arg) /* Stop dropped consoles */ for (i = 0; i < repeat; i++) { j = iomux_match_device(cons_set, cs_idx, old_set[i]); - if (j == cs_idx) + if (j == -ENOENT) console_stop(console, old_set[i]); } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index c08045f9c8d..b076f49ac00 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -270,6 +270,8 @@ config SPL_TEXT_BASE default 0x40200000 if OMAP34XX default 0x402F4000 if AM43XX default 0x402F0400 if AM33XX + default 0x80080000 if ARCH_K3 && ARM64 + default 0x43c00000 if ARCH_K3 && !ARM64 default 0x00908000 if ARCH_MX6 default 0x00912000 if ARCH_MX7 default 0x40301350 if OMAP54XX @@ -537,6 +539,7 @@ if SPL_SYS_MMCSD_RAW_MODE choice prompt "Method for locating next phase of boot (e.g. U-Boot)" + default SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if MVEBU_SPL_BOOT_DEVICE_MMC config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool "MMC raw mode: by sector" diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index d77ff2d7221..3667a0656ed 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +16,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 @@ -39,8 +39,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_MMC=y -CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index cbdc219e25e..4ea551b509b 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index dae87c3b788..fa857e51137 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -13,7 +14,6 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y @@ -55,20 +55,12 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y -CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 39b6a83ab42..f2e1f31ef0f 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c4b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index cedd0f75378..f61e701e3c9 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -11,7 +11,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-beagleplay" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 5a465bff158..7ca5f58ea0c 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 130ff392438..2c04d32195d 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -12,7 +13,6 @@ CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y @@ -55,12 +55,10 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y -CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_CMD_EFIDEBUG=y -CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 8eb59400eb2..4e3ed7801e6 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 22288655bfd..73ebe115819 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -3,6 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -16,7 +17,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-evm" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y @@ -65,22 +65,12 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x300000 CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y -CONFIG_CMD_ASKENV=y CONFIG_CMD_NVEDIT_EFI=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y -CONFIG_CMD_TIME=y CONFIG_CMD_UBI=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 12c4cb96815..a41f67a43fe 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -3,6 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_AM654=y @@ -19,7 +20,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 @@ -35,9 +35,10 @@ CONFIG_PCI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_BOOTCOMMAND=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -59,15 +60,7 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)" CONFIG_CMD_UBI=y diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig index b6571186030..d224583f56a 100644 --- a/configs/amd_versal2_mini_defconfig +++ b/configs/amd_versal2_mini_defconfig @@ -13,12 +13,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_EXPERT is not set @@ -71,9 +68,6 @@ CONFIG_NO_NET=y # CONFIG_INPUT is not set # CONFIG_MMC is not set # CONFIG_POWER is not set -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y # CONFIG_GZIP is not set diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig index da3eebe3fdf..3afc6cb2736 100644 --- a/configs/amd_versal2_mini_emmc_defconfig +++ b/configs/amd_versal2_mini_emmc_defconfig @@ -10,11 +10,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_EFI_LOADER is not set @@ -60,9 +57,6 @@ CONFIG_NO_NET=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_FAT_WRITE=y diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig index 8b9c44017eb..54328e85784 100644 --- a/configs/amd_versal2_mini_ospi_defconfig +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -13,12 +13,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set @@ -72,9 +69,6 @@ CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y # CONFIG_POWER is not set -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_SPI=y diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index e17ca865725..48fb7ae0e7f 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -13,12 +13,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set @@ -65,9 +62,6 @@ CONFIG_NO_NET=y # CONFIG_INPUT is not set # CONFIG_MMC is not set # CONFIG_POWER is not set -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_SPI=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 9911caa0e46..6ec7dd317fd 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -3,17 +3,15 @@ CONFIG_COUNTER_FREQUENCY=375000 CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL2=y -CONFIG_TEXT_BASE=0x8000000 +CONFIG_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 +CONFIG_NR_DRAM_BANKS=36 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_SYS_LOAD_ADDR=0x8000000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_CMD_FRU=y -CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y @@ -28,6 +26,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="versal2> " +CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -64,8 +63,9 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_BOARD=y -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y @@ -75,6 +75,8 @@ CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_VERSALPL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y @@ -82,6 +84,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y @@ -113,11 +116,10 @@ CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y +CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_SCMI=y +CONFIG_RESET_ZYNQMP=y CONFIG_SCSI=y -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig index f09b5b603a2..c74247e13db 100644 --- a/configs/an7581_evb_defconfig +++ b/configs/an7581_evb_defconfig @@ -76,3 +76,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SHA512=y +CONFIG_AIROHA_ETH=y +CONFIG_MMC_MTK=y +CONFIG_AIROHA_SNFI_SPI=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index 6f4dfad5a31..5556148f3cf 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index cdf13c8332f..d23eb99518e 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index d8fb956914c..56738e955e3 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index b6d3102cf2a..ddc6655dd7c 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 6b23d180f84..fa234b62305 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index ff4b52615a6..58bf8817ab6 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index a7446ec5555..eb3ec0064dc 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 0dab8efb875..332c2ba39e9 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig new file mode 100644 index 00000000000..d619f71f37b --- /dev/null +++ b/configs/brcp150_defconfig @@ -0,0 +1,121 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp150" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp150" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_FPGA=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig new file mode 100644 index 00000000000..06cd64ad4bc --- /dev/null +++ b/configs/brcp170_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp170" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig new file mode 100644 index 00000000000..ed2eb86545c --- /dev/null +++ b/configs/brcp1_1r_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig new file mode 100644 index 00000000000..38427da7b51 --- /dev/null +++ b/configs/brcp1_1r_switch_defconfig @@ -0,0 +1,121 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r_switch" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_FIXED=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig new file mode 100644 index 00000000000..2bc8eab14a8 --- /dev/null +++ b/configs/brcp1_2r_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_2r" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig new file mode 100644 index 00000000000..0b57042424b --- /dev/null +++ b/configs/brsmarc2_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index d9314ed1e15..4adf8cc84bd 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig index d5f90d06ca6..8154125b4ac 100644 --- a/configs/clearfog_sata_defconfig +++ b/configs/clearfog_sata_defconfig @@ -62,7 +62,6 @@ CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig index 8868c7fde5e..e9e3e8cdec4 100644 --- a/configs/clearfog_spi_defconfig +++ b/configs/clearfog_spi_defconfig @@ -62,7 +62,6 @@ CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index b7f4a76ce68..2c69e913394 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_LICENSE=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMINFO=y diff --git a/configs/generic-rk3328_defconfig b/configs/generic-rk3328_defconfig new file mode 100644 index 00000000000..8d34a293fd4 --- /dev/null +++ b/configs/generic-rk3328_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-generic" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_EXTERNAL_TPL=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NO_NET=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_ADC is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +# CONFIG_ROCKCHIP_IODOMAIN is not set +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3399_defconfig b/configs/generic-rk3399_defconfig new file mode 100644 index 00000000000..3abe65bcd68 --- /dev/null +++ b/configs/generic-rk3399_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-generic" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_EXTERNAL_TPL=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT_VERBOSE=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NO_NET=y +# CONFIG_ADC is not set +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +# CONFIG_ROCKCHIP_IODOMAIN is not set +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3528_defconfig b/configs/generic-rk3528_defconfig new file mode 100644 index 00000000000..e19c7bc4801 --- /dev/null +++ b/configs/generic-rk3528_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rk3528-generic" +CONFIG_ROCKCHIP_RK3528=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFF9F0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +# CONFIG_ADC is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index f79f0e84400..76418ba7032 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -28,6 +28,8 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y @@ -35,6 +37,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index 51e31dce3a9..2075584cf56 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -22,6 +22,8 @@ CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y @@ -29,6 +31,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 6927e20abd1..3fb5f677ce8 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 59c4da7fa2b..d03895ed6ea 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -129,3 +129,5 @@ CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y CONFIG_LZO=y CONFIG_BZIP2=y +CONFIG_UTHREAD=y +CONFIG_CMD_SPAWN=y diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 72d4b8e3695..5bb692ef3ad 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -21,7 +21,6 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 3126ba3d771..fbdec74d872 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index fad01c27104..e3cd59343f0 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -14,7 +14,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-beagleboneai64" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6bc716650cf..99461cf6007 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -14,7 +14,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-common-proc-board" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 5e84abf8f21..084deea28d0 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index 5d2bb52b440..19f4a3b0e92 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -19,7 +19,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index d96392db479..40db0da9f62 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c7b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 1280194c7a7..56af0230860 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig index 6f1a66f5f1d..1cbeee8fcb7 100644 --- a/configs/mvebu_espressobin_ultra-88f3720_defconfig +++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index d86e19d914f..94176929f9a 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index 25d2d9babba..7bcfbe94850 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 3622e1a7cf2..4ad399893ff 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x83000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index f157103be4a..a5d494cf87a 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 72936865132..d4842939096 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig index 8c5d3eb4be8..3819670defe 100644 --- a/configs/qemu-arm-sbsa_defconfig +++ b/configs/qemu-arm-sbsa_defconfig @@ -9,3 +9,4 @@ CONFIG_EFI_PARTITION=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_EFI_MEDIA=y CONFIG_FS_FAT=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 9f20b3fcd73..a444899db33 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -66,3 +66,4 @@ CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_ADDR_MAP=y CONFIG_PANIC_HANG=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 1cd80f5769e..b9f28873c15 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -16,7 +16,10 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set +CONFIG_CMD_SPAWN=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 +CONFIG_UTHREAD=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 6f871c83644..cd89571e40c 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -17,7 +17,10 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set +CONFIG_CMD_SPAWN=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 +CONFIG_UTHREAD=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 9906f8b2dad..8d5f9d9f5cc 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -26,3 +26,4 @@ CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 # CONFIG_BINMAN_FDT is not set +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index cdd511b0e72..c67fb9a3352 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -16,7 +16,10 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set +CONFIG_CMD_SPAWN=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 +CONFIG_UTHREAD=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-riscv64_smode_acpi_defconfig b/configs/qemu-riscv64_smode_acpi_defconfig new file mode 100644 index 00000000000..e78e5ffb390 --- /dev/null +++ b/configs/qemu-riscv64_smode_acpi_defconfig @@ -0,0 +1,2 @@ +#include <configs/qemu-riscv64_smode_defconfig> +#include <board/emulation/configs/acpi.config> diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 2f62f17bc8c..d28e9fbeceb 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -19,7 +19,10 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set +CONFIG_CMD_SPAWN=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 +CONFIG_UTHREAD=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 27e092bd208..18b7e049d86 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -25,3 +25,4 @@ CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 # CONFIG_BINMAN_FDT is not set +CONFIG_UNIT_TEST=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 58b1fbf132d..47075dc265a 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -93,3 +93,4 @@ CONFIG_SPL_VIDEO=y CONFIG_GENERATE_ACPI_TABLE=y CONFIG_CMD_DHRYSTONE=y # CONFIG_GZIP is not set +CONFIG_UNIT_TEST=y diff --git a/configs/qemu_arm64_acpi_defconfig b/configs/qemu_arm64_acpi_defconfig new file mode 100644 index 00000000000..f85f2913530 --- /dev/null +++ b/configs/qemu_arm64_acpi_defconfig @@ -0,0 +1,2 @@ +#include <configs/qemu_arm64_defconfig> +#include <board/emulation/configs/acpi.config> diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 6c9d2505a69..b1371d4258f 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TPM=y CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_SPAWN=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -75,3 +76,5 @@ CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_TPM_PCR_ALLOCATE=y CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y +CONFIG_UTHREAD=y +CONFIG_UNIT_TEST=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 2d642f86ba6..97d2f2f2e49 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_TPM=y CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_SPAWN=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -67,4 +68,5 @@ CONFIG_TPM2_MMIO=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_TPM=y +CONFIG_UTHREAD=y CONFIG_UNIT_TEST=y diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig new file mode 100644 index 00000000000..08f3a13af3b --- /dev/null +++ b/configs/radxa-e20c-rk3528_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c" +CONFIG_ROCKCHIP_RK3528=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFF9F0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 324581b4082..b6b3d3e2b3f 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set diff --git a/configs/roc-pc-rk3576_defconfig b/configs/roc-pc-rk3576_defconfig new file mode 100644 index 00000000000..af2c1026636 --- /dev/null +++ b/configs/roc-pc-rk3576_defconfig @@ -0,0 +1,45 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-roc-pc" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_TARGET_ROC_PC_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-roc-pc.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_ERRNO_STR=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 42c40077823..23df4c3b635 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -99,6 +99,7 @@ CONFIG_CMD_CBFS=y CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_SPAWN=y CONFIG_MAC_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_OF_CONTROL=y @@ -275,6 +276,7 @@ CONFIG_TPM=y CONFIG_ERRNO_STR=y CONFIG_GETOPT=y CONFIG_TEST_FDTDEC=y +CONFIG_UTHREAD=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/sandbox64_lwip_defconfig b/configs/sandbox64_lwip_defconfig new file mode 100644 index 00000000000..0e92728533f --- /dev/null +++ b/configs/sandbox64_lwip_defconfig @@ -0,0 +1,5 @@ +#include <configs/sandbox64_defconfig> + +CONFIG_SANDBOX=y + +CONFIG_NET_LWIP=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 87f21fdbd12..c4b1b8114d6 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -143,6 +143,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_STACKPROTECTOR_TEST=y +CONFIG_CMD_SPAWN=y CONFIG_MAC_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_OF_LIVE=y @@ -364,6 +365,7 @@ CONFIG_TPM=y CONFIG_ERRNO_STR=y CONFIG_GETOPT=y CONFIG_TEST_FDTDEC=y +CONFIG_UTHREAD=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 8f327e5f2ab..4ac0a5d9b99 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 @@ -31,6 +32,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_FIXED=y +CONFIG_BLOBLIST_ADDR=0x7e000 CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_HANDOFF=y @@ -73,6 +76,8 @@ CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y @@ -82,6 +87,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y CONFIG_DWC_ETH_XGMAC=y CONFIG_RGMII=y CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/socfpga_agilex5_vab_defconfig b/configs/socfpga_agilex5_vab_defconfig new file mode 100644 index 00000000000..a5f4b335760 --- /dev/null +++ b/configs/socfpga_agilex5_vab_defconfig @@ -0,0 +1,3 @@ +#include <configs/socfpga_agilex5_defconfig> + +CONFIG_SOCFPGA_SECURE_VAB_AUTH=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 6bfcaab37dc..1be8d892070 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -28,9 +28,9 @@ CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=0 -CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot" CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2077 +# CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -41,15 +41,25 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_SPL is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y +# CONFIG_CMD_SAVEENV is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_SQUASHFS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:0x100000(qspi-boot-bin),-(qspi-rootfs)" +CONFIG_CMD_UBI=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -57,14 +67,18 @@ CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_MTD=y +CONFIG_MTD_BLOCK=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_BEB_LIMIT=0 +CONFIG_UBI_BLOCK=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y @@ -80,3 +94,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +CONFIG_LZ4=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index ecd3284faaf..4bdcb4b6c46 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 9ac4b534f6c..f9580e697ff 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 -CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index e1cdc186fb4..af9ce499169 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x500 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFFFE00 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE1000 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 1604b5915db..a82ccdc9a0c 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -74,6 +74,8 @@ CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_VERSALPL=y CONFIG_ZYNQ_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y @@ -121,7 +123,6 @@ CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y CONFIG_SOC_XILINX_VERSAL_NET=y CONFIG_SPI=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index baa4b8e412e..ba4519ce303 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -133,7 +133,6 @@ CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -CONFIG_XILINX_UARTLITE=y CONFIG_SOC_XILINX_VERSAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 1f8e8c348eb..ae79f101701 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -187,7 +187,6 @@ CONFIG_DM_RTC=y CONFIG_RTC_ZYNQMP=y CONFIG_SCSI=y CONFIG_ARM_DCC=y -CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y @@ -228,3 +227,4 @@ CONFIG_PANIC_HANG=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_SPL_GZIP=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index abd1e1bb574..29aa5891b23 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -199,7 +199,6 @@ CONFIG_RTC_EMULATION=y CONFIG_RTC_ZYNQMP=y CONFIG_SCSI=y CONFIG_ARM_DCC=y -CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y diff --git a/doc/api/index.rst b/doc/api/index.rst index a108718ea99..506843ed74a 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -25,6 +25,8 @@ U-Boot API documentation rng sandbox serial + setjmp sysreset timer unicode + uthread diff --git a/doc/api/setjmp.rst b/doc/api/setjmp.rst new file mode 100644 index 00000000000..c30e51c2b55 --- /dev/null +++ b/doc/api/setjmp.rst @@ -0,0 +1,20 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Long jump API +============= + +.. kernel-doc:: include/setjmp.h + :doc: Overview + +.. kernel-doc:: include/setjmp.h + :internal: + +Example +------- + +Here is an example showing how to use the a long jump functions and +initjmp() in particular: + +.. literalinclude:: ../../test/lib/initjmp.c + :language: c + :linenos: diff --git a/doc/api/uthread.rst b/doc/api/uthread.rst new file mode 100644 index 00000000000..8b25cc1ff80 --- /dev/null +++ b/doc/api/uthread.rst @@ -0,0 +1,19 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Uthread API +=========== + +.. kernel-doc:: include/uthread.h + :doc: Overview + +.. kernel-doc:: include/uthread.h + :internal: + +Example +------- + +Here is an example of how to use this API: + +.. literalinclude:: ../../test/lib/uthread.c + :language: c + :linenos: diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1407080f1f4..b06f87b137c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -66,6 +66,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328) - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328) - FriendlyElec NanoPi R2S Plus (nanopi-r2s-plus-rk3328) + - Generic RK3328 (generic-rk3328) - Pine64 Rock64 (rock64-rk3328) - Radxa ROCK Pi E (rock-pi-e-rk3328) - Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328) @@ -83,6 +84,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi M4 (nanopi-m4-rk3399) - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399) - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399) + - Generic RK3399 (generic-rk3399) - Google Bob (chromebook_bob) - Google Kevin (chromebook_kevin) - Khadas Edge (khadas-edge-rk3399) @@ -97,6 +99,10 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3399 (evb_rk3399) - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399) +* rk3528 + - Generic RK3528 (generic-rk3528) + - Radxa E20C (radxa-e20c-rk3528) + * rk3566 - Anbernic RGxx3 (anbernic-rgxx3-rk3566) - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566) @@ -126,6 +132,9 @@ List of mainline supported Rockchip boards: - Radxa ROCK 3A (rock-3a-rk3568) - Radxa ROCK 3B (rock-3b-rk3568) +* rk3576 + - Firefly ROC-RK3576-PC (roc-pc-rk3576) + * rk3588 - ArmSoM Sige7 (sige7-rk3588) - Rockchip EVB (evb-rk3588) @@ -258,6 +267,15 @@ To build rk3399 boards: make evb-rk3399_defconfig make CROSS_COMPILE=aarch64-linux-gnu- +To build rk3528 boards: + +.. code-block:: bash + + export BL31=../rkbin/bin/rk35/rk3528_bl31_v1.18.elf + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3528_ddr_1056MHz_v1.10.bin + make generic-rk3528_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- + To build rk3568 boards: .. code-block:: bash @@ -268,6 +286,15 @@ To build rk3568 boards: make evb-rk3568_defconfig make CROSS_COMPILE=aarch64-linux-gnu- +To build rk3576 boards: + +.. code-block:: bash + + export BL31=../rkbin/bin/rk35/rk3576_bl31_v1.04.elf + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.03.bin + make roc-pc-rk3576_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- + To build rk3588 boards: .. code-block:: bash diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst index e5a1be50c4f..edc29a4f9e4 100644 --- a/doc/board/ti/j722s_evm.rst +++ b/doc/board/ti/j722s_evm.rst @@ -74,7 +74,6 @@ Set the variables corresponding to this platform: $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig $ export TFA_BOARD=lite $ export OPTEE_PLATFORM=k3-am62x - $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" .. j722s_evm_rst_include_start_build_steps diff --git a/doc/develop/devicetree/dt_qemu.rst b/doc/develop/devicetree/dt_qemu.rst index 8ba2b225590..b452e2a997a 100644 --- a/doc/develop/devicetree/dt_qemu.rst +++ b/doc/develop/devicetree/dt_qemu.rst @@ -16,15 +16,22 @@ Obtaining the QEMU devicetree Where QEMU generates its own devicetree to pass to U-Boot you can use `-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version. -To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`, -e.g.:: - - qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb - - qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb - - qemu-system-riscv64 -machine virt -machine dumpdtb=qemu.dtb - +To obtain the devicetree that QEMU generates, add `dumpdtb=qemu.dtb` to the +`-machine` argument, e.g. + +.. code-block:: bash + + qemu-system-aarch64 \ + -machine virt,gic-version=3,dumpdtb=qemu.dtb \ + -cpu cortex-a57 \ + -smp 4 \ + -memory 8G \ + -chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=tpm0,chardev=chrtpm \ + -device tpm-tis-device,tpmdev=tpm0 + +Except for the dumpdtb=qemu.dtb sub-parameter use the same qemu-system-<arch> +invocation that you would use to start U-Boot to to get a complete device-tree. Merging in U-Boot nodes/properties ---------------------------------- diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index cbbc2bad0eb..50948c00927 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -1,3 +1,5 @@ +.. |next_ver| replace:: v2025.07 + Release Cycle ============= @@ -53,13 +55,13 @@ Current Status * U-Boot v2025.04 was released on Monday, 07 April 2025. -* The Merge Window for the next release (v2025.07) is **open** until the -rc1 +* The Merge Window for the next release (|next_ver|) is **open** until the -rc1 release on Monday, 28 April 2025. * The next branch is now **closed** until the -rc2 release on Monday, 12 May 2025. -* Release "v2025.07" is scheduled for Monday, 07 July 2025. +* Release "|next_ver|" is scheduled for Monday, 07 July 2025. Future Releases --------------- @@ -69,15 +71,15 @@ Future Releases .. For the next scheduled release, release candidates were made on:: -.. * U-Boot v2025.07-rc1 was released on Mon 21 April 2025. +.. * U-Boot |next_ver|-rc1 was released on Mon 21 April 2025. -.. * U-Boot v2025.07-rc2 was released on Mon 12 May 2025. +.. * U-Boot |next_ver|-rc2 was released on Mon 12 May 2025. -.. * U-Boot v2025.07-rc3 was released on Mon 26 May 2025. +.. * U-Boot |next_ver|-rc3 was released on Mon 26 May 2025. -.. * U-Boot v2025.07-rc4 was released on Mon 09 June 2025. +.. * U-Boot |next_ver|-rc4 was released on Mon 09 June 2025. -.. * U-Boot v2025.07-rc5 was released on Mon 23 June 2025. +.. * U-Boot |next_ver|-rc5 was released on Mon 23 June 2025. Please note that the following dates are planned only and may be deviated from as needed. diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 7cf9735f60d..1515951403c 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -339,6 +339,14 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { .stop = rockchip_saradc_stop_v1, }; +static const struct rockchip_saradc_data rk3528_saradc_data = { + .num_bits = 10, + .num_channels = 4, + .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v2, + .start_channel = rockchip_saradc_start_channel_v2, +}; + static const struct rockchip_saradc_data rk3588_saradc_data = { .num_bits = 12, .num_channels = 8, @@ -354,6 +362,8 @@ static const struct udevice_id rockchip_saradc_ids[] = { .data = (ulong)&rk3066_tsadc_data }, { .compatible = "rockchip,rk3399-saradc", .data = (ulong)&rk3399_saradc_data }, + { .compatible = "rockchip,rk3528-saradc", + .data = (ulong)&rk3528_saradc_data }, { .compatible = "rockchip,rk3588-saradc", .data = (ulong)&rk3588_saradc_data }, { } diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index b532b3b7339..38e953ee79c 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -420,7 +420,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) { - phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl); + phys_addr_t pa = virt_to_phys(pp->cmd_tbl); pp->cmd_slot->opts = cpu_to_le32(opts); pp->cmd_slot->status = 0; @@ -449,7 +449,7 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) { struct ahci_ioports *pp = &(uc_priv->port[port]); void __iomem *port_mmio = pp->port_mmio; - u64 dma_addr; + phys_addr_t dma_addr; u32 port_status; void __iomem *mem; @@ -472,34 +472,32 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ - pp->cmd_slot = - (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); - debug("cmd_slot = %p\n", pp->cmd_slot); - mem += (AHCI_CMD_SLOT_SZ + 224); + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT; /* * Second item: Received-FIS area */ - pp->rx_fis = virt_to_phys((void *)mem); + pp->rx_fis = mem; mem += AHCI_RX_FIS_SZ; /* * Third item: data area for storing a single command * and its scatter-gather table */ - pp->cmd_tbl = virt_to_phys((void *)mem); - debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); + pp->cmd_tbl = mem; mem += AHCI_CMD_TBL_HDR; - pp->cmd_tbl_sg = - (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - - dma_addr = (ulong)pp->cmd_slot; - writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR); - writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI); - dma_addr = (ulong)pp->rx_fis; - writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR); - writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI); + pp->cmd_tbl_sg = (struct ahci_sg *)(mem); + + dma_addr = virt_to_phys(pp->cmd_slot); + debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_LST_ADDR); + writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_LST_ADDR_HI); + dma_addr = virt_to_phys(pp->rx_fis); + debug("rx_fis_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR); + writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR_HI); #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio); diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index 203f98edffc..d225289fe6e 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -7,6 +7,7 @@ #include <ahci.h> #include <blk.h> #include <bootdev.h> +#include <clk.h> #include <cpu_func.h> #include <dm.h> #include <dwc_ahsata.h> @@ -19,9 +20,11 @@ #include <sata.h> #include <asm/cache.h> #include <asm/io.h> +#if IS_ENABLED(CONFIG_ARCH_MX5) || IS_ENABLED(CONFIG_ARCH_MX6) #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/sata.h> +#endif #include <linux/bitops.h> #include <linux/ctype.h> #include <linux/delay.h> @@ -116,13 +119,12 @@ static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) return 0; } -static int ahci_host_init(struct ahci_uc_priv *uc_priv) +static int ahci_host_init(struct ahci_uc_priv *uc_priv, int clk) { u32 tmp, cap_save, num_ports; int i, j, timeout = 1000; struct sata_port_regs *port_mmio = NULL; struct sata_host_regs *host_mmio = uc_priv->mmio_base; - int clk = mxc_get_clock(MXC_SATA_CLK); cap_save = readl(&host_mmio->cap); cap_save |= SATA_HOST_CAP_SSS; @@ -330,6 +332,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, { struct ahci_ioports *pp = &uc_priv->port[port]; struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + phys_addr_t pa = virt_to_phys(buf); u32 sg_count, max_bytes; int i; @@ -341,9 +344,8 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, } for (i = 0; i < sg_count; i++) { - ahci_sg->addr = - cpu_to_le32((u32)buf + i * max_bytes); - ahci_sg->addr_hi = 0; + ahci_sg->addr = cpu_to_le32(lower_32_bits(pa)); + ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa)); ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < max_bytes ? (buf_len - 1) @@ -359,14 +361,14 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) { struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + AHCI_CMD_SLOT_SZ * cmd_slot); + phys_addr_t pa = virt_to_phys(pp->cmd_tbl); memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); cmd_hdr->opts = cpu_to_le32(opts); cmd_hdr->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa)); #ifdef CONFIG_PHYS_64BIT - pp->cmd_slot->tbl_addr_hi = - cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); + pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa)); #endif } @@ -404,7 +406,7 @@ static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, } ahci_fill_cmd_slot(pp, cmd_slot, opts); - flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); + flush_cache((ulong)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); writel_with_flush(1 << cmd_slot, &port_mmio->ci); if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, @@ -412,8 +414,8 @@ static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, printf("timeout exit!\n"); return -1; } - invalidate_dcache_range((int)(pp->cmd_slot), - (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); + invalidate_dcache_range((ulong)(pp->cmd_slot), + (ulong)(pp->cmd_slot) + AHCI_PORT_PRIV_DMA_SZ); debug("ahci_exec_ata_cmd: %d byte transferred.\n", pp->cmd_slot->status); if (!is_write) @@ -441,8 +443,9 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) { struct ahci_ioports *pp = &uc_priv->port[port]; struct sata_port_regs *port_mmio = pp->port_mmio; + phys_addr_t dma_addr; u32 port_status; - u32 mem; + void *mem; int timeout = 10000000; debug("Enter start port: %d\n", port); @@ -453,22 +456,20 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) return -1; } - mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); + mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); if (!mem) { printf("No mem for table!\n"); return -ENOMEM; } - mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ - memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ pp->cmd_slot = (struct ahci_cmd_hdr *)mem; - debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); - mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); + mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT; /* * Second item: Received-FIS area, 256-Byte aligned @@ -481,14 +482,19 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) * and its scatter-gather table */ pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); - mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; writel_with_flush(0x00004444, &port_mmio->dmacr); - pp->cmd_tbl_sg = (struct ahci_sg *)mem; - writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); - writel_with_flush(pp->rx_fis, &port_mmio->fb); + dma_addr = virt_to_phys(pp->cmd_slot); + debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), &port_mmio->clb); + writel_with_flush(upper_32_bits(dma_addr), &port_mmio->clbu); + dma_addr = virt_to_phys(pp->cmd_slot); + debug("rx_fis_slot_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), &port_mmio->fb); + writel_with_flush(upper_32_bits(dma_addr), &port_mmio->fbu); + /* Enable FRE */ writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), @@ -910,17 +916,41 @@ int dwc_ahsata_scan(struct udevice *dev) int dwc_ahsata_probe(struct udevice *dev) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk_bulk clk_bulk __maybe_unused; + struct clk clk __maybe_unused; + int sataclk; int ret; -#if defined(CONFIG_MX6) +#if IS_ENABLED(CONFIG_MX6) setup_sata(); #endif +#if IS_ENABLED(CONFIG_MX5) || IS_ENABLED(CONFIG_MX6) + sataclk = mxc_get_clock(MXC_SATA_CLK); +#else + ret = clk_get_bulk(dev, &clk_bulk); + if (ret) + return ret; + + ret = clk_enable_bulk(&clk_bulk); + if (ret) + return ret; + + ret = clk_get_by_name(dev, "sata", &clk); + if (ret) + return ret; + + sataclk = clk_get_rate(&clk); +#endif + if (IS_ERR_VALUE(sataclk)) { + log_err("Unable to get SATA clock rate\n"); + return -EINVAL; + } uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; uc_priv->mmio_base = dev_read_addr_ptr(dev); /* initialize adapter */ - ret = ahci_host_init(uc_priv); + ret = ahci_host_init(uc_priv, sataclk); if (ret) return ret; @@ -962,7 +992,6 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = { .ops = &dwc_ahsata_blk_ops, }; -#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI) struct ahci_ops dwc_ahsata_ahci_ops = { .port_status = dwc_ahsata_port_status, .reset = dwc_ahsata_bus_reset, @@ -970,7 +999,9 @@ struct ahci_ops dwc_ahsata_ahci_ops = { }; static const struct udevice_id dwc_ahsata_ahci_ids[] = { + { .compatible = "fsl,imx53-ahci" }, { .compatible = "fsl,imx6q-ahci" }, + { .compatible = "fsl,imx6qp-ahci" }, { } }; @@ -981,4 +1012,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = { .ops = &dwc_ahsata_ahci_ops, .probe = dwc_ahsata_probe, }; -#endif diff --git a/drivers/ata/dwc_ahsata_priv.h b/drivers/ata/dwc_ahsata_priv.h index 5b0579ae115..0c2cd5446b5 100644 --- a/drivers/ata/dwc_ahsata_priv.h +++ b/drivers/ata/dwc_ahsata_priv.h @@ -7,8 +7,6 @@ #ifndef __DWC_AHSATA_PRIV_H__ #define __DWC_AHSATA_PRIV_H__ -#define DWC_AHSATA_MAX_CMD_SLOTS 32 - /* Max host controller numbers */ #define SATA_HC_MAX_NUM 4 /* Max command queue depth per host controller */ diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c index 030ff7cc58e..71e030f463e 100644 --- a/drivers/clk/clk_boston.c +++ b/drivers/clk/clk_boston.c @@ -58,17 +58,21 @@ const struct clk_ops clk_boston_ops = { .get_rate = clk_boston_get_rate, }; -static int clk_boston_of_to_plat(struct udevice *dev) +static int clk_boston_probe(struct udevice *dev) { struct clk_boston *state = dev_get_plat(dev); struct udevice *syscon; int err; - err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, - "regmap", &syscon); - if (err) { - pr_err("unable to find syscon device\n"); - return err; + if (dev->parent && device_get_uclass_id(dev->parent) == UCLASS_SYSCON) { + syscon = dev->parent; + } else { + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "regmap", &syscon); + if (err) { + pr_err("unable to find syscon device\n"); + return err; + } } state->regmap = syscon_get_regmap(syscon); @@ -91,7 +95,8 @@ U_BOOT_DRIVER(clk_boston) = { .name = "boston_clock", .id = UCLASS_CLK, .of_match = clk_boston_match, - .of_to_plat = clk_boston_of_to_plat, + .probe = clk_boston_probe, .plat_auto = sizeof(struct clk_boston), .ops = &clk_boston_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 9e379cc2e3b..34b63d4df34 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -15,7 +15,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 44c6f14618d..9dec40b1fe8 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -309,9 +309,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, * When power on or changing PLL setting, * we must force PLL into slow mode to ensure output stable clock. */ - rk_clrsetreg(base + pll->mode_offset, - pll->mode_mask << pll->mode_shift, - RKCLK_PLL_MODE_SLOW << pll->mode_shift); + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { + rk_clrsetreg(base + pll->mode_offset, + pll->mode_mask << pll->mode_shift, + RKCLK_PLL_MODE_SLOW << pll->mode_shift); + } /* Power down */ rk_setreg(base + pll->con_offset + 0x4, @@ -345,8 +347,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) udelay(1); - rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, - RKCLK_PLL_MODE_NORMAL << pll->mode_shift); + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { + rk_clrsetreg(base + pll->mode_offset, + pll->mode_mask << pll->mode_shift, + RKCLK_PLL_MODE_NORMAL << pll->mode_shift); + } debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", pll, readl(base + pll->con_offset), readl(base + pll->con_offset + 0x4), @@ -362,12 +367,18 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; u32 con = 0, shift, mask; ulong rate; + int mode; con = readl(base + pll->mode_offset); shift = pll->mode_shift; mask = pll->mode_mask << shift; - switch ((con & mask) >> shift) { + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) + mode = (con & mask) >> shift; + else + mode = RKCLK_PLL_MODE_NORMAL; + + switch (mode) { case RKCLK_PLL_MODE_SLOW: return OSC_HZ; case RKCLK_PLL_MODE_NORMAL: diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c new file mode 100644 index 00000000000..06f20895acc --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -0,0 +1,1754 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#include <bitfield.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3528.h> +#include <asm/arch-rockchip/hardware.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rk3528-cru.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +/* + * PLL attention. + * + * [FRAC PLL]: GPLL, PPLL, DPLL + * - frac mode: refdiv can be 1 or 2 only + * - int mode: refdiv has no special limit + * - VCO range: [950, 3800] MHZ + * + * [INT PLL]: CPLL, APLL + * - int mode: refdiv can be 1 or 2 only + * - VCO range: [475, 1900] MHZ + * + * [PPLL]: normal mode only. + * + */ +static struct rockchip_pll_rate_table rk3528_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ + RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ + RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ + RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rk3528_pll_clks[] = { + [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0), + RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates), + + [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8), + RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates), + + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24), + RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates), + + [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32), + RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), + + [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16), + RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates), +}; + +#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \ +{ \ + .rate = _rate##U, \ + .aclk_div = (_aclk_m_core), \ + .pclk_div = (_pclk_dbg), \ +} + +/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */ +static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = { + RK3528_CPUCLK_RATE(1896000000, 1, 13), + RK3528_CPUCLK_RATE(1800000000, 1, 12), + RK3528_CPUCLK_RATE(1704000000, 1, 11), + RK3528_CPUCLK_RATE(1608000000, 1, 11), + RK3528_CPUCLK_RATE(1512000000, 1, 11), + RK3528_CPUCLK_RATE(1416000000, 1, 9), + RK3528_CPUCLK_RATE(1296000000, 1, 8), + RK3528_CPUCLK_RATE(1200000000, 1, 8), + RK3528_CPUCLK_RATE(1188000000, 1, 8), + RK3528_CPUCLK_RATE(1092000000, 1, 7), + RK3528_CPUCLK_RATE(1008000000, 1, 6), + RK3528_CPUCLK_RATE(1000000000, 1, 6), + RK3528_CPUCLK_RATE(996000000, 1, 6), + RK3528_CPUCLK_RATE(960000000, 1, 6), + RK3528_CPUCLK_RATE(912000000, 1, 6), + RK3528_CPUCLK_RATE(816000000, 1, 5), + RK3528_CPUCLK_RATE(600000000, 1, 3), + RK3528_CPUCLK_RATE(594000000, 1, 3), + RK3528_CPUCLK_RATE(408000000, 1, 2), + RK3528_CPUCLK_RATE(312000000, 1, 2), + RK3528_CPUCLK_RATE(216000000, 1, 1), + RK3528_CPUCLK_RATE(96000000, 1, 0), +}; + +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + +static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate) +{ + const struct rockchip_cpu_rate_table *rate; + struct rk3528_cru *cru = priv->cru; + ulong old_rate; + + rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate); + if (!rate) { + printf("%s unsupported rate\n", __func__); + return -EINVAL; + } + + /* + * set up dependent divisors for DBG and ACLK clocks. + */ + old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL); + if (old_rate > new_rate) { + if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL], + priv->cru, APLL, new_rate)) + return -EINVAL; + + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, + rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); + + rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK, + rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); + } else if (old_rate < new_rate) { + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, + rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); + + rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK, + rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); + + if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL], + priv->cru, APLL, new_rate)) + return -EINVAL; + } + + return 0; +} + +static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv, + ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, mask, shift; + void *reg; + + switch (clk_id) { + case CLK_PPLL_50M_MATRIX: + case CLK_GMAC1_RMII_VPU: + mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK; + shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT; + reg = &cru->pcieclksel_con[1]; + break; + + case CLK_PPLL_100M_MATRIX: + mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK; + shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT; + reg = &cru->pcieclksel_con[1]; + break; + + case CLK_PPLL_125M_MATRIX: + case CLK_GMAC1_SRC_VPU: + mask = CLK_MATRIX_125M_SRC_DIV_MASK; + shift = CLK_MATRIX_125M_SRC_DIV_SHIFT; + reg = &cru->clksel_con[60]; + break; + + case CLK_GMAC1_VPU_25M: + mask = CLK_MATRIX_25M_SRC_DIV_MASK; + shift = CLK_MATRIX_25M_SRC_DIV_SHIFT; + reg = &cru->clksel_con[60]; + break; + default: + return -ENOENT; + } + + div = (readl(reg) & mask) >> shift; + + return DIV_TO_RATE(priv->ppll_hz, div); +} + +static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, div, mask, shift; + u8 is_pciecru = 0; + + switch (clk_id) { + case CLK_PPLL_50M_MATRIX: + id = 1; + mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK; + shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT; + is_pciecru = 1; + break; + + case CLK_PPLL_100M_MATRIX: + id = 1; + mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK; + shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT; + is_pciecru = 1; + break; + + case CLK_PPLL_125M_MATRIX: + id = 60; + mask = CLK_MATRIX_125M_SRC_DIV_MASK; + shift = CLK_MATRIX_125M_SRC_DIV_SHIFT; + break; + case CLK_GMAC1_VPU_25M: + id = 60; + mask = CLK_MATRIX_25M_SRC_DIV_MASK; + shift = CLK_MATRIX_25M_SRC_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + div = DIV_ROUND_UP(priv->ppll_hz, rate); + if (is_pciecru) + rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift); + else + rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift); + + return rk3528_ppll_matrix_get_rate(priv, clk_id); +} + +static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv, + ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 sel, div, mask, shift, con; + u32 sel_mask = 0, sel_shift; + u8 is_gpll_parent = 1; + u8 is_halfdiv = 0; + ulong prate; + + switch (clk_id) { + case CLK_MATRIX_50M_SRC: + con = 0; + mask = CLK_MATRIX_50M_SRC_DIV_MASK; + shift = CLK_MATRIX_50M_SRC_DIV_SHIFT; + is_gpll_parent = 0; + break; + + case CLK_MATRIX_100M_SRC: + con = 0; + mask = CLK_MATRIX_100M_SRC_DIV_MASK; + shift = CLK_MATRIX_100M_SRC_DIV_SHIFT; + is_gpll_parent = 0; + break; + + case CLK_MATRIX_150M_SRC: + con = 1; + mask = CLK_MATRIX_150M_SRC_DIV_MASK; + shift = CLK_MATRIX_150M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_200M_SRC: + con = 1; + mask = CLK_MATRIX_200M_SRC_DIV_MASK; + shift = CLK_MATRIX_200M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_250M_SRC: + con = 1; + mask = CLK_MATRIX_250M_SRC_DIV_MASK; + shift = CLK_MATRIX_250M_SRC_DIV_SHIFT; + sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK; + sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT; + break; + + case CLK_MATRIX_300M_SRC: + con = 2; + mask = CLK_MATRIX_300M_SRC_DIV_MASK; + shift = CLK_MATRIX_300M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_339M_SRC: + con = 2; + mask = CLK_MATRIX_339M_SRC_DIV_MASK; + shift = CLK_MATRIX_339M_SRC_DIV_SHIFT; + is_halfdiv = 1; + break; + + case CLK_MATRIX_400M_SRC: + con = 2; + mask = CLK_MATRIX_400M_SRC_DIV_MASK; + shift = CLK_MATRIX_400M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_500M_SRC: + con = 3; + mask = CLK_MATRIX_500M_SRC_DIV_MASK; + shift = CLK_MATRIX_500M_SRC_DIV_SHIFT; + sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK; + sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT; + break; + + case CLK_MATRIX_600M_SRC: + con = 4; + mask = CLK_MATRIX_600M_SRC_DIV_MASK; + shift = CLK_MATRIX_600M_SRC_DIV_SHIFT; + break; + + case ACLK_BUS_VOPGL_ROOT: + case ACLK_BUS_VOPGL_BIU: + con = 43; + mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK; + shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + if (sel_mask) { + sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift; + if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO + prate = priv->gpll_hz; + else + prate = priv->cpll_hz; + } else { + if (is_gpll_parent) + prate = priv->gpll_hz; + else + prate = priv->cpll_hz; + } + + div = (readl(&cru->clksel_con[con]) & mask) >> shift; + + /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */ + return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div); +} + +static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 sel, div, mask, shift, con; + u32 sel_mask = 0, sel_shift; + u8 is_gpll_parent = 1; + u8 is_halfdiv = 0; + ulong prate = 0; + + switch (clk_id) { + case CLK_MATRIX_50M_SRC: + con = 0; + mask = CLK_MATRIX_50M_SRC_DIV_MASK; + shift = CLK_MATRIX_50M_SRC_DIV_SHIFT; + is_gpll_parent = 0; + break; + + case CLK_MATRIX_100M_SRC: + con = 0; + mask = CLK_MATRIX_100M_SRC_DIV_MASK; + shift = CLK_MATRIX_100M_SRC_DIV_SHIFT; + is_gpll_parent = 0; + break; + + case CLK_MATRIX_150M_SRC: + con = 1; + mask = CLK_MATRIX_150M_SRC_DIV_MASK; + shift = CLK_MATRIX_150M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_200M_SRC: + con = 1; + mask = CLK_MATRIX_200M_SRC_DIV_MASK; + shift = CLK_MATRIX_200M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_250M_SRC: + con = 1; + mask = CLK_MATRIX_250M_SRC_DIV_MASK; + shift = CLK_MATRIX_250M_SRC_DIV_SHIFT; + sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK; + sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT; + break; + + case CLK_MATRIX_300M_SRC: + con = 2; + mask = CLK_MATRIX_300M_SRC_DIV_MASK; + shift = CLK_MATRIX_300M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_339M_SRC: + con = 2; + mask = CLK_MATRIX_339M_SRC_DIV_MASK; + shift = CLK_MATRIX_339M_SRC_DIV_SHIFT; + is_halfdiv = 1; + break; + + case CLK_MATRIX_400M_SRC: + con = 2; + mask = CLK_MATRIX_400M_SRC_DIV_MASK; + shift = CLK_MATRIX_400M_SRC_DIV_SHIFT; + break; + + case CLK_MATRIX_500M_SRC: + con = 3; + mask = CLK_MATRIX_500M_SRC_DIV_MASK; + shift = CLK_MATRIX_500M_SRC_DIV_SHIFT; + sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK; + sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT; + break; + + case CLK_MATRIX_600M_SRC: + con = 4; + mask = CLK_MATRIX_600M_SRC_DIV_MASK; + shift = CLK_MATRIX_600M_SRC_DIV_SHIFT; + break; + + case ACLK_BUS_VOPGL_ROOT: + case ACLK_BUS_VOPGL_BIU: + con = 43; + mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK; + shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + if (sel_mask) { + if (priv->gpll_hz % rate == 0) { + sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO + prate = priv->gpll_hz; + } else { + sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX; + prate = priv->cpll_hz; + } + } else { + if (is_gpll_parent) + prate = priv->gpll_hz; + else + prate = priv->cpll_hz; + } + + if (is_halfdiv) + /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */ + div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1; + else + div = DIV_ROUND_UP(prate, rate); + + rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift); + if (sel_mask) + rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift); + + return rk3528_cgpll_matrix_get_rate(priv, clk_id); +} + +static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, sel, con, mask, shift; + u8 is_pmucru = 0; + ulong rate; + + switch (clk_id) { + case CLK_I2C0: + id = 79; + mask = CLK_I2C0_SEL_MASK; + shift = CLK_I2C0_SEL_SHIFT; + break; + + case CLK_I2C1: + id = 79; + mask = CLK_I2C1_SEL_MASK; + shift = CLK_I2C1_SEL_SHIFT; + break; + + case CLK_I2C2: + id = 0; + mask = CLK_I2C2_SEL_MASK; + shift = CLK_I2C2_SEL_SHIFT; + is_pmucru = 1; + break; + + case CLK_I2C3: + id = 63; + mask = CLK_I2C3_SEL_MASK; + shift = CLK_I2C3_SEL_SHIFT; + break; + + case CLK_I2C4: + id = 85; + mask = CLK_I2C4_SEL_MASK; + shift = CLK_I2C4_SEL_SHIFT; + break; + + case CLK_I2C5: + id = 63; + mask = CLK_I2C5_SEL_MASK; + shift = CLK_I2C5_SEL_SHIFT; + break; + + case CLK_I2C6: + id = 64; + mask = CLK_I2C6_SEL_MASK; + shift = CLK_I2C6_SEL_SHIFT; + break; + + case CLK_I2C7: + id = 86; + mask = CLK_I2C7_SEL_MASK; + shift = CLK_I2C7_SEL_SHIFT; + break; + + default: + return -ENOENT; + } + + if (is_pmucru) + con = readl(&cru->pmuclksel_con[id]); + else + con = readl(&cru->clksel_con[id]); + sel = (con & mask) >> shift; + if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC) + rate = 200 * MHz; + else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC) + rate = 100 * MHz; + else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC) + rate = 50 * MHz; + else + rate = OSC_HZ; + + return rate; +} + +static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, sel, mask, shift; + u8 is_pmucru = 0; + + if (rate >= 198 * MHz) + sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC; + else if (rate >= 99 * MHz) + sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC; + else if (rate >= 50 * MHz) + sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC; + else + sel = CLK_I2C3_SEL_XIN_OSC0_FUNC; + + switch (clk_id) { + case CLK_I2C0: + id = 79; + mask = CLK_I2C0_SEL_MASK; + shift = CLK_I2C0_SEL_SHIFT; + break; + + case CLK_I2C1: + id = 79; + mask = CLK_I2C1_SEL_MASK; + shift = CLK_I2C1_SEL_SHIFT; + break; + + case CLK_I2C2: + id = 0; + mask = CLK_I2C2_SEL_MASK; + shift = CLK_I2C2_SEL_SHIFT; + is_pmucru = 1; + break; + + case CLK_I2C3: + id = 63; + mask = CLK_I2C3_SEL_MASK; + shift = CLK_I2C3_SEL_SHIFT; + break; + + case CLK_I2C4: + id = 85; + mask = CLK_I2C4_SEL_MASK; + shift = CLK_I2C4_SEL_SHIFT; + break; + + case CLK_I2C5: + id = 63; + mask = CLK_I2C5_SEL_MASK; + shift = CLK_I2C5_SEL_SHIFT; + break; + + case CLK_I2C6: + id = 64; + mask = CLK_I2C6_SEL_MASK; + shift = CLK_I2C6_SEL_SHIFT; + break; + + case CLK_I2C7: + id = 86; + mask = CLK_I2C7_SEL_MASK; + shift = CLK_I2C7_SEL_SHIFT; + break; + + default: + return -ENOENT; + } + + if (is_pmucru) + rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift); + else + rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); + + return rk3528_i2c_get_clk(priv, clk_id); +} + +static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, sel, con, mask, shift; + ulong rate; + + switch (clk_id) { + case CLK_SPI0: + id = 79; + mask = CLK_SPI0_SEL_MASK; + shift = CLK_SPI0_SEL_SHIFT; + break; + + case CLK_SPI1: + id = 63; + mask = CLK_SPI1_SEL_MASK; + shift = CLK_SPI1_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[id]); + sel = (con & mask) >> shift; + if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC) + rate = 200 * MHz; + else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC) + rate = 100 * MHz; + else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC) + rate = 50 * MHz; + else + rate = OSC_HZ; + + return rate; +} + +static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, sel, mask, shift; + + if (rate >= 198 * MHz) + sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC; + else if (rate >= 99 * MHz) + sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC; + else if (rate >= 50 * MHz) + sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC; + else + sel = CLK_SPI1_SEL_XIN_OSC0_FUNC; + + switch (clk_id) { + case CLK_SPI0: + id = 79; + mask = CLK_SPI0_SEL_MASK; + shift = CLK_SPI0_SEL_SHIFT; + break; + + case CLK_SPI1: + id = 63; + mask = CLK_SPI1_SEL_MASK; + shift = CLK_SPI1_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); + + return rk3528_spi_get_clk(priv, clk_id); +} + +static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, sel, con, mask, shift; + ulong rate; + + switch (clk_id) { + case CLK_PWM0: + id = 44; + mask = CLK_PWM0_SEL_MASK; + shift = CLK_PWM0_SEL_SHIFT; + break; + + case CLK_PWM1: + id = 44; + mask = CLK_PWM1_SEL_MASK; + shift = CLK_PWM1_SEL_SHIFT; + break; + + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[id]); + sel = (con & mask) >> shift; + if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC) + rate = 100 * MHz; + if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC) + rate = 50 * MHz; + else + rate = OSC_HZ; + + return rate; +} + +static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 id, sel, mask, shift; + + if (rate >= 99 * MHz) + sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC; + else if (rate >= 50 * MHz) + sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC; + else + sel = CLK_PWM0_SEL_XIN_OSC0_FUNC; + + switch (clk_id) { + case CLK_PWM0: + id = 44; + mask = CLK_PWM0_SEL_MASK; + shift = CLK_PWM0_SEL_SHIFT; + break; + + case CLK_PWM1: + id = 44; + mask = CLK_PWM1_SEL_MASK; + shift = CLK_PWM1_SEL_SHIFT; + break; + + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); + + return rk3528_pwm_get_clk(priv, clk_id); +} + +static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, con; + + con = readl(&cru->clksel_con[74]); + switch (clk_id) { + case CLK_SARADC: + div = (con & CLK_SARADC_DIV_MASK) >> + CLK_SARADC_DIV_SHIFT; + break; + + case CLK_TSADC_TSEN: + div = (con & CLK_TSADC_TSEN_DIV_MASK) >> + CLK_TSADC_TSEN_DIV_SHIFT; + break; + + case CLK_TSADC: + div = (con & CLK_TSADC_DIV_MASK) >> + CLK_TSADC_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, mask, shift; + + switch (clk_id) { + case CLK_SARADC: + mask = CLK_SARADC_DIV_MASK; + shift = CLK_SARADC_DIV_SHIFT; + break; + + case CLK_TSADC_TSEN: + mask = CLK_TSADC_TSEN_DIV_MASK; + shift = CLK_TSADC_TSEN_DIV_SHIFT; + break; + + case CLK_TSADC: + mask = CLK_TSADC_DIV_MASK; + shift = CLK_TSADC_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + div = DIV_ROUND_UP(OSC_HZ, rate); + rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift); + + return rk3528_adc_get_clk(priv, clk_id); +} + +static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, sel, con; + ulong prate; + + con = readl(&cru->clksel_con[85]); + div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >> + CCLK_SRC_SDMMC0_DIV_SHIFT; + sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >> + CCLK_SRC_SDMMC0_SEL_SHIFT; + + if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX) + prate = priv->gpll_hz; + else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, sel; + + if (OSC_HZ % rate == 0) { + div = DIV_ROUND_UP(OSC_HZ, rate); + sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC; + } else if ((priv->cpll_hz % rate) == 0) { + div = DIV_ROUND_UP(priv->cpll_hz, rate); + sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX; + } else { + div = DIV_ROUND_UP(priv->gpll_hz, rate); + sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX; + } + + assert(div - 1 <= 63); + rk_clrsetreg(&cru->clksel_con[85], + CCLK_SRC_SDMMC0_SEL_MASK | + CCLK_SRC_SDMMC0_DIV_MASK, + sel << CCLK_SRC_SDMMC0_SEL_SHIFT | + (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT); + + return rk3528_sdmmc_get_clk(priv, clk_id); +} + +static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[61]); + div = (con & SCLK_SFC_DIV_MASK) >> + SCLK_SFC_DIV_SHIFT; + sel = (con & SCLK_SFC_SEL_MASK) >> + SCLK_SFC_SEL_SHIFT; + if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX) + parent = priv->gpll_hz; + else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX) + parent = priv->cpll_hz; + else + parent = OSC_HZ; + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + int div, sel; + + if (OSC_HZ % rate == 0) { + div = DIV_ROUND_UP(OSC_HZ, rate); + sel = SCLK_SFC_SEL_XIN_OSC0_FUNC; + } else if ((priv->cpll_hz % rate) == 0) { + div = DIV_ROUND_UP(priv->cpll_hz, rate); + sel = SCLK_SFC_SEL_CLK_CPLL_MUX; + } else { + div = DIV_ROUND_UP(priv->gpll_hz, rate); + sel = SCLK_SFC_SEL_CLK_GPLL_MUX; + } + + assert(div - 1 <= 63); + rk_clrsetreg(&cru->clksel_con[61], + SCLK_SFC_SEL_MASK | + SCLK_SFC_DIV_MASK, + sel << SCLK_SFC_SEL_SHIFT | + (div - 1) << SCLK_SFC_DIV_SHIFT); + + return rk3528_sfc_get_clk(priv); +} + +static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[62]); + div = (con & CCLK_SRC_EMMC_DIV_MASK) >> + CCLK_SRC_EMMC_DIV_SHIFT; + sel = (con & CCLK_SRC_EMMC_SEL_MASK) >> + CCLK_SRC_EMMC_SEL_SHIFT; + + if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX) + parent = priv->gpll_hz; + else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX) + parent = priv->cpll_hz; + else + parent = OSC_HZ; + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 div, sel; + + if (OSC_HZ % rate == 0) { + div = DIV_ROUND_UP(OSC_HZ, rate); + sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC; + } else if ((priv->cpll_hz % rate) == 0) { + div = DIV_ROUND_UP(priv->cpll_hz, rate); + sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX; + } else { + div = DIV_ROUND_UP(priv->gpll_hz, rate); + sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX; + } + + assert(div - 1 <= 63); + rk_clrsetreg(&cru->clksel_con[62], + CCLK_SRC_EMMC_SEL_MASK | + CCLK_SRC_EMMC_DIV_MASK, + sel << CCLK_SRC_EMMC_SEL_SHIFT | + (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT); + + return rk3528_emmc_get_clk(priv); +} + +static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 div_mask, div_shift; + u32 sel_mask, sel_shift; + u32 id, con, sel, div; + ulong prate; + + switch (clk_id) { + case DCLK_VOP0: + id = 32; + sel_mask = DCLK_VOP_SRC0_SEL_MASK; + sel_shift = DCLK_VOP_SRC0_SEL_SHIFT; + /* FIXME if need src: clk_hdmiphy_pixel_io */ + div_mask = DCLK_VOP_SRC0_DIV_MASK; + div_shift = DCLK_VOP_SRC0_DIV_SHIFT; + break; + + case DCLK_VOP1: + id = 33; + sel_mask = DCLK_VOP_SRC1_SEL_MASK; + sel_shift = DCLK_VOP_SRC1_SEL_SHIFT; + div_mask = DCLK_VOP_SRC1_DIV_MASK; + div_shift = DCLK_VOP_SRC1_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[id]); + div = (con & div_mask) >> div_shift; + sel = (con & sel_mask) >> sel_shift; + if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX) + prate = priv->gpll_hz; + else + prate = priv->cpll_hz; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 div_mask, div_shift; + u32 sel_mask, sel_shift; + u32 id, sel, div; + ulong prate; + + switch (clk_id) { + case DCLK_VOP0: + id = 32; + sel_mask = DCLK_VOP_SRC0_SEL_MASK; + sel_shift = DCLK_VOP_SRC0_SEL_SHIFT; + /* FIXME if need src: clk_hdmiphy_pixel_io */ + div_mask = DCLK_VOP_SRC0_DIV_MASK; + div_shift = DCLK_VOP_SRC0_DIV_SHIFT; + break; + + case DCLK_VOP1: + id = 33; + sel_mask = DCLK_VOP_SRC1_SEL_MASK; + sel_shift = DCLK_VOP_SRC1_SEL_SHIFT; + div_mask = DCLK_VOP_SRC1_DIV_MASK; + div_shift = DCLK_VOP_SRC1_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + if ((priv->gpll_hz % rate) == 0) { + prate = priv->gpll_hz; + sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask; + } else { + prate = priv->cpll_hz; + sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask; + } + + div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; + rk_clrsetreg(&cru->clksel_con[id], sel, div); + + return rk3528_dclk_vop_get_clk(priv, clk_id); +} + +static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id) +{ + struct rk3528_cru *cru = priv->cru; + u32 sel_shift, sel_mask, div_shift, div_mask; + u32 sel, id, con, frac_div, div; + ulong m, n, rate; + + switch (clk_id) { + case SCLK_UART0: + id = 6; + sel_shift = SCLK_UART0_SRC_SEL_SHIFT; + sel_mask = SCLK_UART0_SRC_SEL_MASK; + div_shift = CLK_UART0_SRC_DIV_SHIFT; + div_mask = CLK_UART0_SRC_DIV_MASK; + break; + + case SCLK_UART1: + id = 8; + sel_shift = SCLK_UART1_SRC_SEL_SHIFT; + sel_mask = SCLK_UART1_SRC_SEL_MASK; + div_shift = CLK_UART1_SRC_DIV_SHIFT; + div_mask = CLK_UART1_SRC_DIV_MASK; + break; + + case SCLK_UART2: + id = 10; + sel_shift = SCLK_UART2_SRC_SEL_SHIFT; + sel_mask = SCLK_UART2_SRC_SEL_MASK; + div_shift = CLK_UART2_SRC_DIV_SHIFT; + div_mask = CLK_UART2_SRC_DIV_MASK; + break; + + case SCLK_UART3: + id = 12; + sel_shift = SCLK_UART3_SRC_SEL_SHIFT; + sel_mask = SCLK_UART3_SRC_SEL_MASK; + div_shift = CLK_UART3_SRC_DIV_SHIFT; + div_mask = CLK_UART3_SRC_DIV_MASK; + break; + + case SCLK_UART4: + id = 14; + sel_shift = SCLK_UART4_SRC_SEL_SHIFT; + sel_mask = SCLK_UART4_SRC_SEL_MASK; + div_shift = CLK_UART4_SRC_DIV_SHIFT; + div_mask = CLK_UART4_SRC_DIV_MASK; + break; + + case SCLK_UART5: + id = 16; + sel_shift = SCLK_UART5_SRC_SEL_SHIFT; + sel_mask = SCLK_UART5_SRC_SEL_MASK; + div_shift = CLK_UART5_SRC_DIV_SHIFT; + div_mask = CLK_UART5_SRC_DIV_MASK; + break; + + case SCLK_UART6: + id = 18; + sel_shift = SCLK_UART6_SRC_SEL_SHIFT; + sel_mask = SCLK_UART6_SRC_SEL_MASK; + div_shift = CLK_UART6_SRC_DIV_SHIFT; + div_mask = CLK_UART6_SRC_DIV_MASK; + break; + + case SCLK_UART7: + id = 20; + sel_shift = SCLK_UART7_SRC_SEL_SHIFT; + sel_mask = SCLK_UART7_SRC_SEL_MASK; + div_shift = CLK_UART7_SRC_DIV_SHIFT; + div_mask = CLK_UART7_SRC_DIV_MASK; + break; + + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[id - 2]); + div = (con & div_mask) >> div_shift; + + con = readl(&cru->clksel_con[id]); + sel = (con & sel_mask) >> sel_shift; + + if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) { + rate = DIV_TO_RATE(priv->gpll_hz, div); + } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) { + frac_div = readl(&cru->clksel_con[id - 1]); + n = (frac_div & 0xffff0000) >> 16; + m = frac_div & 0x0000ffff; + rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m; + } else { + rate = OSC_HZ; + } + + return rate; +} + +static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 sel_shift, sel_mask, div_shift, div_mask; + u32 sel, id, div; + ulong m = 0, n = 0, val; + + if (rate == OSC_HZ) { + sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->gpll_hz % rate == 0) { + sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } else { + sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC; + div = 2; + rational_best_approximation(rate, priv->gpll_hz / div, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &n, &m); + } + + switch (clk_id) { + case SCLK_UART0: + id = 6; + sel_shift = SCLK_UART0_SRC_SEL_SHIFT; + sel_mask = SCLK_UART0_SRC_SEL_MASK; + div_shift = CLK_UART0_SRC_DIV_SHIFT; + div_mask = CLK_UART0_SRC_DIV_MASK; + break; + + case SCLK_UART1: + id = 8; + sel_shift = SCLK_UART1_SRC_SEL_SHIFT; + sel_mask = SCLK_UART1_SRC_SEL_MASK; + div_shift = CLK_UART1_SRC_DIV_SHIFT; + div_mask = CLK_UART1_SRC_DIV_MASK; + break; + + case SCLK_UART2: + id = 10; + sel_shift = SCLK_UART2_SRC_SEL_SHIFT; + sel_mask = SCLK_UART2_SRC_SEL_MASK; + div_shift = CLK_UART2_SRC_DIV_SHIFT; + div_mask = CLK_UART2_SRC_DIV_MASK; + break; + + case SCLK_UART3: + id = 12; + sel_shift = SCLK_UART3_SRC_SEL_SHIFT; + sel_mask = SCLK_UART3_SRC_SEL_MASK; + div_shift = CLK_UART3_SRC_DIV_SHIFT; + div_mask = CLK_UART3_SRC_DIV_MASK; + break; + + case SCLK_UART4: + id = 14; + sel_shift = SCLK_UART4_SRC_SEL_SHIFT; + sel_mask = SCLK_UART4_SRC_SEL_MASK; + div_shift = CLK_UART4_SRC_DIV_SHIFT; + div_mask = CLK_UART4_SRC_DIV_MASK; + break; + + case SCLK_UART5: + id = 16; + sel_shift = SCLK_UART5_SRC_SEL_SHIFT; + sel_mask = SCLK_UART5_SRC_SEL_MASK; + div_shift = CLK_UART5_SRC_DIV_SHIFT; + div_mask = CLK_UART5_SRC_DIV_MASK; + break; + + case SCLK_UART6: + id = 18; + sel_shift = SCLK_UART6_SRC_SEL_SHIFT; + sel_mask = SCLK_UART6_SRC_SEL_MASK; + div_shift = CLK_UART6_SRC_DIV_SHIFT; + div_mask = CLK_UART6_SRC_DIV_MASK; + break; + + case SCLK_UART7: + id = 20; + sel_shift = SCLK_UART7_SRC_SEL_SHIFT; + sel_mask = SCLK_UART7_SRC_SEL_MASK; + div_shift = CLK_UART7_SRC_DIV_SHIFT; + div_mask = CLK_UART7_SRC_DIV_MASK; + break; + + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift); + rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift); + if (m && n) { + val = n << 16 | m; + writel(val, &cru->clksel_con[id - 1]); + } + + return rk3528_uart_get_rate(priv, clk_id); +} + +static ulong rk3528_clk_get_rate(struct clk *clk) +{ + struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz || !priv->cpll_hz) { + printf("%s: gpll=%lu, cpll=%ld\n", + __func__, priv->gpll_hz, priv->cpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, + APLL); + break; + case PLL_CPLL: + rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, + CPLL); + break; + case PLL_GPLL: + rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, + GPLL); + break; + + case PLL_PPLL: + rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, + PPLL); + break; + case PLL_DPLL: + rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru, + DPLL); + break; + + case TCLK_EMMC: + case TCLK_WDT_NS: + rate = OSC_HZ; + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C6: + case CLK_I2C7: + rate = rk3528_i2c_get_clk(priv, clk->id); + break; + case CLK_SPI0: + case CLK_SPI1: + rate = rk3528_spi_get_clk(priv, clk->id); + break; + case CLK_PWM0: + case CLK_PWM1: + rate = rk3528_pwm_get_clk(priv, clk->id); + break; + case CLK_SARADC: + case CLK_TSADC: + case CLK_TSADC_TSEN: + rate = rk3528_adc_get_clk(priv, clk->id); + break; + case CCLK_SRC_EMMC: + rate = rk3528_emmc_get_clk(priv); + break; + case HCLK_SDMMC0: + case CCLK_SRC_SDMMC0: + rate = rk3528_sdmmc_get_clk(priv, clk->id); + break; + case SCLK_SFC: + rate = rk3528_sfc_get_clk(priv); + break; + case DCLK_VOP0: + case DCLK_VOP1: + rate = rk3528_dclk_vop_get_clk(priv, clk->id); + break; + case DCLK_CVBS: + rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4; + break; + case DCLK_4X_CVBS: + rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1); + break; + case SCLK_UART0: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + rate = rk3528_uart_get_rate(priv, clk->id); + break; + case CLK_MATRIX_50M_SRC: + case CLK_MATRIX_100M_SRC: + case CLK_MATRIX_150M_SRC: + case CLK_MATRIX_200M_SRC: + case CLK_MATRIX_250M_SRC: + case CLK_MATRIX_300M_SRC: + case CLK_MATRIX_339M_SRC: + case CLK_MATRIX_400M_SRC: + case CLK_MATRIX_500M_SRC: + case CLK_MATRIX_600M_SRC: + case ACLK_BUS_VOPGL_BIU: + rate = rk3528_cgpll_matrix_get_rate(priv, clk->id); + break; + case CLK_PPLL_50M_MATRIX: + case CLK_PPLL_100M_MATRIX: + case CLK_PPLL_125M_MATRIX: + case CLK_GMAC1_VPU_25M: + case CLK_GMAC1_RMII_VPU: + case CLK_GMAC1_SRC_VPU: + rate = rk3528_ppll_matrix_get_rate(priv, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +}; + +static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + if (priv->armclk_hz) + rk3528_armclk_set_clk(priv, rate); + priv->armclk_hz = rate; + break; + case PLL_CPLL: + ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, + CPLL, rate); + priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], + priv->cru, CPLL); + break; + case PLL_GPLL: + ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, + GPLL, rate); + priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], + priv->cru, GPLL); + break; + case PLL_PPLL: + ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, + PPLL, rate); + priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], + priv->cru, PPLL); + break; + case TCLK_EMMC: + case TCLK_WDT_NS: + return (rate == OSC_HZ) ? 0 : -EINVAL; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C6: + case CLK_I2C7: + ret = rk3528_i2c_set_clk(priv, clk->id, rate); + break; + case CLK_SPI0: + case CLK_SPI1: + ret = rk3528_spi_set_clk(priv, clk->id, rate); + break; + case CLK_PWM0: + case CLK_PWM1: + ret = rk3528_pwm_set_clk(priv, clk->id, rate); + break; + case CLK_SARADC: + case CLK_TSADC: + case CLK_TSADC_TSEN: + ret = rk3528_adc_set_clk(priv, clk->id, rate); + break; + case HCLK_SDMMC0: + case CCLK_SRC_SDMMC0: + ret = rk3528_sdmmc_set_clk(priv, clk->id, rate); + break; + case SCLK_SFC: + ret = rk3528_sfc_set_clk(priv, rate); + break; + case CCLK_SRC_EMMC: + ret = rk3528_emmc_set_clk(priv, rate); + break; + case DCLK_VOP0: + case DCLK_VOP1: + ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate); + break; + case SCLK_UART0: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + ret = rk3528_uart_set_rate(priv, clk->id, rate); + break; + case CLK_MATRIX_50M_SRC: + case CLK_MATRIX_100M_SRC: + case CLK_MATRIX_150M_SRC: + case CLK_MATRIX_200M_SRC: + case CLK_MATRIX_250M_SRC: + case CLK_MATRIX_300M_SRC: + case CLK_MATRIX_339M_SRC: + case CLK_MATRIX_400M_SRC: + case CLK_MATRIX_500M_SRC: + case CLK_MATRIX_600M_SRC: + case ACLK_BUS_VOPGL_BIU: + ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate); + break; + case CLK_PPLL_50M_MATRIX: + case CLK_PPLL_100M_MATRIX: + case CLK_PPLL_125M_MATRIX: + case CLK_GMAC1_VPU_25M: + ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate); + break; + case CLK_GMAC1_RMII_VPU: + case CLK_GMAC1_SRC_VPU: + /* dummy set */ + ret = rk3528_ppll_matrix_get_rate(priv, clk->id); + break; + + /* Might occur in cru assigned-clocks, can be ignored here */ + case ACLK_BUS_VOPGL_ROOT: + case BCLK_EMMC: + case XIN_OSC0_DIV: + ret = 0; + break; + default: + return -ENOENT; + } + + return ret; +}; + +static struct clk_ops rk3528_clk_ops = { + .get_rate = rk3528_clk_get_rate, + .set_rate = rk3528_clk_set_rate, +}; + +#ifdef CONFIG_XPL_BUILD + +#define COREGRF_BASE 0xff300000 +#define PVTPLL_CON0_L 0x0 +#define PVTPLL_CON0_H 0x4 + +static int rk3528_cpu_pvtpll_set_rate(struct rk3528_clk_priv *priv, ulong rate) +{ + struct rk3528_cru *cru = priv->cru; + u32 length; + + if (rate >= 1200000000) + length = 8; + else if (rate >= 1008000000) + length = 11; + else + length = 17; + + /* set pclk dbg div to 9 */ + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, + 9 << RK3528_DIV_PCLK_DBG_SHIFT); + /* set aclk_m_core div to 1 */ + rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK, + 1 << RK3528_DIV_ACLK_M_CORE_SHIFT); + + /* set ring sel = 1 */ + writel(0x07000000 | (1 << 8), COREGRF_BASE + PVTPLL_CON0_L); + /* set length */ + writel(0x007f0000 | length, COREGRF_BASE + PVTPLL_CON0_H); + /* enable pvtpll */ + writel(0x00020002, COREGRF_BASE + PVTPLL_CON0_L); + /* start monitor */ + writel(0x00010001, COREGRF_BASE + PVTPLL_CON0_L); + + /* set core mux pvtpll */ + writel(0x00010001, &cru->clksel_con[40]); + writel(0x00100010, &cru->clksel_con[39]); + + /* set pclk dbg div to 8 */ + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, + 8 << RK3528_DIV_PCLK_DBG_SHIFT); + + return 0; +} +#endif + +static int rk3528_clk_init(struct rk3528_clk_priv *priv) +{ + int ret; + + priv->sync_kernel = false; + +#ifdef CONFIG_XPL_BUILD + /* + * BOOTROM: + * CPU 1902/2(postdiv1)=546M + * CPLL 996/2(postdiv1)=498M + * GPLL 1188/2(postdiv1)=594M + * |-- clk_matrix_200m_src_div=1 => rate: 300M + * |-- clk_matrix_300m_src_div=2 => rate: 200M + * + * Avoid overclocking when change GPLL rate: + * Change clk_matrix_200m_src_div to 5. + * Change clk_matrix_300m_src_div to 3. + */ + writel(0x01200120, &priv->cru->clksel_con[1]); + writel(0x00030003, &priv->cru->clksel_con[2]); + + if (!priv->armclk_enter_hz) { + priv->armclk_enter_hz = + rockchip_pll_get_rate(&rk3528_pll_clks[APLL], + priv->cru, APLL); + priv->armclk_init_hz = priv->armclk_enter_hz; + } + + if (priv->armclk_init_hz != APLL_HZ) { + ret = rk3528_armclk_set_clk(priv, APLL_HZ); + if (!ret) + priv->armclk_init_hz = APLL_HZ; + } + + if (!rk3528_cpu_pvtpll_set_rate(priv, CPU_PVTPLL_HZ)) { + debug("cpu pvtpll %d KHz\n", CPU_PVTPLL_HZ / 1000); + priv->armclk_init_hz = CPU_PVTPLL_HZ; + } +#endif + + if (priv->cpll_hz != CPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, + CPLL, CPLL_HZ); + if (!ret) + priv->cpll_hz = CPLL_HZ; + } + + if (priv->gpll_hz != GPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, + GPLL, GPLL_HZ); + if (!ret) + priv->gpll_hz = GPLL_HZ; + } + + if (priv->ppll_hz != PPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, + PPLL, PPLL_HZ); + if (!ret) + priv->ppll_hz = PPLL_HZ; + } + +#ifdef CONFIG_XPL_BUILD + /* Init to override bootrom config */ + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000); + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000); + rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000); + + /* The default rate is 100Mhz, it's not friendly for remote IR module */ + rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000); + rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000); +#endif + return 0; +} + +static int rk3528_clk_probe(struct udevice *dev) +{ + struct rk3528_clk_priv *priv = dev_get_priv(dev); + int ret; + + ret = rk3528_clk_init(priv); + if (ret) + return ret; + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + debug("%s clk_set_defaults failed %d\n", __func__, ret); + else + priv->sync_kernel = true; + + return 0; +} + +static int rk3528_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3528_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rk3528_clk_bind(struct udevice *dev) +{ + struct udevice *sys_child; + struct sysreset_reg *priv; + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3528_cru, + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rk3528_cru, + glb_srst_snd); + dev_set_priv(sys_child, priv); + } + +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + ret = offsetof(struct rk3528_cru, softrst_con[0]); + ret = rk3528_reset_bind_lut(dev, ret, 47); + if (ret) + debug("Warning: software reset driver bind failed\n"); +#endif + + return 0; +} + +static const struct udevice_id rk3528_clk_ids[] = { + { .compatible = "rockchip,rk3528-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3528_cru) = { + .name = "rockchip_rk3528_cru", + .id = UCLASS_CLK, + .of_match = rk3528_clk_ids, + .priv_auto = sizeof(struct rk3528_clk_priv), + .of_to_plat = rk3528_clk_ofdata_to_platdata, + .ops = &rk3528_clk_ops, + .bind = rk3528_clk_bind, + .probe = rk3528_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c new file mode 100644 index 00000000000..e84a0943a94 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -0,0 +1,2513 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <bitfield.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch-rockchip/cru_rk3576.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rk3576-cru.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = { + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(1500000000, 2, 250, 1, 0), + RK3588_PLL_RATE(1200000000, 1, 100, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1150000000, 3, 575, 2, 0), + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), + RK3588_PLL_RATE(850000000, 3, 425, 2, 0), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(742500000, 4, 495, 2, 0), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), + RK3588_PLL_RATE(200000000, 3, 400, 4, 0), + RK3588_PLL_RATE(100000000, 3, 400, 5, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rk3576_pll_clks[] = { + [BPLL] = PLL(pll_rk3588, PLL_BPLL, RK3576_PLL_CON(0), + RK3576_BPLL_MODE_CON0, 0, 15, 0, + rk3576_24m_pll_rates), + [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16), + RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_24m_pll_rates), + [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88), + RK3576_LPLL_MODE_CON0, 4, 15, 0, rk3576_24m_pll_rates), + [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96), + RK3576_MODE_CON0, 6, 15, 0, rk3576_24m_pll_rates), + [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104), + RK3576_MODE_CON0, 8, 15, 0, rk3576_24m_pll_rates), + [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112), + RK3576_MODE_CON0, 2, 15, 0, rk3576_24m_pll_rates), + [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128), + RK3576_MODE_CON0, 10, 15, 0, rk3576_24m_pll_rates), +}; + +#ifdef CONFIG_SPL_BUILD +#ifndef BITS_WITH_WMASK +#define BITS_WITH_WMASK(bits, msk, shift) \ + ((bits) << (shift)) | ((msk) << ((shift) + 16)) +#endif +#endif + +#ifndef CONFIG_SPL_BUILD +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} +#endif + +static ulong rk3576_bus_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 con, sel, div, rate; + + switch (clk_id) { + case ACLK_BUS_ROOT: + con = readl(&cru->clksel_con[55]); + sel = (con & ACLK_BUS_ROOT_SEL_MASK) >> + ACLK_BUS_ROOT_SEL_SHIFT; + div = (con & ACLK_BUS_ROOT_DIV_MASK) >> + ACLK_BUS_ROOT_DIV_SHIFT; + if (sel == ACLK_BUS_ROOT_SEL_CPLL) + rate = DIV_TO_RATE(priv->cpll_hz, div); + else + rate = DIV_TO_RATE(priv->gpll_hz, div); + break; + case HCLK_BUS_ROOT: + con = readl(&cru->clksel_con[55]); + sel = (con & HCLK_BUS_ROOT_SEL_MASK) >> + HCLK_BUS_ROOT_SEL_SHIFT; + if (sel == HCLK_BUS_ROOT_SEL_200M) + rate = 198 * MHz; + else if (sel == HCLK_BUS_ROOT_SEL_100M) + rate = 100 * MHz; + else if (sel == HCLK_BUS_ROOT_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + break; + case PCLK_BUS_ROOT: + con = readl(&cru->clksel_con[55]); + sel = (con & PCLK_BUS_ROOT_SEL_MASK) >> + PCLK_BUS_ROOT_SEL_SHIFT; + if (sel == PCLK_BUS_ROOT_SEL_100M) + rate = 100 * MHz; + else if (sel == PCLK_BUS_ROOT_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3576_bus_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk, src_clk_div; + + switch (clk_id) { + case ACLK_BUS_ROOT: + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_BUS_ROOT_SEL_CPLL; + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_BUS_ROOT_SEL_GPLL; + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + rk_clrsetreg(&cru->clksel_con[55], + ACLK_BUS_ROOT_SEL_MASK, + src_clk << ACLK_BUS_ROOT_SEL_SHIFT); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[55], + ACLK_BUS_ROOT_DIV_MASK | + ACLK_BUS_ROOT_SEL_MASK, + (src_clk << + ACLK_BUS_ROOT_SEL_SHIFT) | + (src_clk_div - 1) << ACLK_BUS_ROOT_DIV_SHIFT); + break; + case HCLK_BUS_ROOT: + if (rate >= 198 * MHz) + src_clk = HCLK_BUS_ROOT_SEL_200M; + else if (rate >= 99 * MHz) + src_clk = HCLK_BUS_ROOT_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = HCLK_BUS_ROOT_SEL_50M; + else + src_clk = HCLK_BUS_ROOT_SEL_OSC; + rk_clrsetreg(&cru->clksel_con[55], + HCLK_BUS_ROOT_SEL_MASK, + src_clk << HCLK_BUS_ROOT_SEL_SHIFT); + break; + case PCLK_BUS_ROOT: + if (rate >= 99 * MHz) + src_clk = PCLK_BUS_ROOT_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = PCLK_BUS_ROOT_SEL_50M; + else + src_clk = PCLK_BUS_ROOT_SEL_OSC; + rk_clrsetreg(&cru->clksel_con[55], + PCLK_BUS_ROOT_SEL_MASK, + src_clk << PCLK_BUS_ROOT_SEL_SHIFT); + break; + default: + printf("do not support this center freq\n"); + return -EINVAL; + } + + return rk3576_bus_get_clk(priv, clk_id); +} + +static ulong rk3576_top_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 con, sel, div, rate, prate; + + switch (clk_id) { + case ACLK_TOP: + con = readl(&cru->clksel_con[9]); + div = (con & ACLK_TOP_DIV_MASK) >> + ACLK_TOP_DIV_SHIFT; + sel = (con & ACLK_TOP_SEL_MASK) >> + ACLK_TOP_SEL_SHIFT; + if (sel == ACLK_TOP_SEL_CPLL) + prate = priv->cpll_hz; + else if (sel == ACLK_TOP_SEL_AUPLL) + prate = priv->aupll_hz; + else + prate = priv->gpll_hz; + return DIV_TO_RATE(prate, div); + case ACLK_TOP_MID: + con = readl(&cru->clksel_con[10]); + div = (con & ACLK_TOP_MID_DIV_MASK) >> + ACLK_TOP_MID_DIV_SHIFT; + sel = (con & ACLK_TOP_MID_SEL_MASK) >> + ACLK_TOP_MID_SEL_SHIFT; + if (sel == ACLK_TOP_MID_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = priv->gpll_hz; + return DIV_TO_RATE(prate, div); + case PCLK_TOP_ROOT: + con = readl(&cru->clksel_con[8]); + sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT; + if (sel == PCLK_TOP_SEL_100M) + rate = 100 * MHz; + else if (sel == PCLK_TOP_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + break; + case HCLK_TOP: + con = readl(&cru->clksel_con[19]); + sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT; + if (sel == HCLK_TOP_SEL_200M) + rate = 200 * MHz; + else if (sel == HCLK_TOP_SEL_100M) + rate = 100 * MHz; + else if (sel == HCLK_TOP_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3576_top_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk, src_clk_div; + + switch (clk_id) { + case ACLK_TOP: + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_TOP_SEL_CPLL; + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_TOP_SEL_GPLL; + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[9], + ACLK_TOP_DIV_MASK | + ACLK_TOP_SEL_MASK, + (src_clk << + ACLK_TOP_SEL_SHIFT) | + (src_clk_div - 1) << ACLK_TOP_SEL_SHIFT); + break; + case ACLK_TOP_MID: + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_TOP_MID_SEL_CPLL; + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_TOP_MID_SEL_GPLL; + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + rk_clrsetreg(&cru->clksel_con[10], + ACLK_TOP_MID_DIV_MASK | + ACLK_TOP_MID_SEL_MASK, + (ACLK_TOP_MID_SEL_GPLL << + ACLK_TOP_MID_SEL_SHIFT) | + (src_clk_div - 1) << ACLK_TOP_MID_DIV_SHIFT); + break; + case PCLK_TOP_ROOT: + if (rate >= 99 * MHz) + src_clk = PCLK_TOP_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = PCLK_TOP_SEL_50M; + else + src_clk = PCLK_TOP_SEL_OSC; + rk_clrsetreg(&cru->clksel_con[8], + PCLK_TOP_SEL_MASK, + src_clk << PCLK_TOP_SEL_SHIFT); + break; + case HCLK_TOP: + if (rate >= 198 * MHz) + src_clk = HCLK_TOP_SEL_200M; + else if (rate >= 99 * MHz) + src_clk = HCLK_TOP_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = HCLK_TOP_SEL_50M; + else + src_clk = HCLK_TOP_SEL_OSC; + rk_clrsetreg(&cru->clksel_con[19], + HCLK_TOP_SEL_MASK, + src_clk << HCLK_TOP_SEL_SHIFT); + break; + default: + printf("do not support this top freq\n"); + return -EINVAL; + } + + return rk3576_top_get_clk(priv, clk_id); +} + +static ulong rk3576_i2c_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 sel, con; + ulong rate; + + switch (clk_id) { + case CLK_I2C0: + con = readl(&cru->pmuclksel_con[6]); + sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT; + break; + case CLK_I2C1: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT; + break; + case CLK_I2C2: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; + break; + case CLK_I2C3: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT; + break; + case CLK_I2C4: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT; + break; + case CLK_I2C5: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT; + break; + case CLK_I2C6: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT; + break; + case CLK_I2C7: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT; + break; + case CLK_I2C8: + con = readl(&cru->clksel_con[57]); + sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT; + break; + case CLK_I2C9: + con = readl(&cru->clksel_con[58]); + sel = (con & CLK_I2C9_SEL_MASK) >> CLK_I2C9_SEL_SHIFT; + break; + + default: + return -ENOENT; + } + if (sel == CLK_I2C_SEL_200M) + rate = 200 * MHz; + else if (sel == CLK_I2C_SEL_100M) + rate = 100 * MHz; + else if (sel == CLK_I2C_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + + return rate; +} + +static ulong rk3576_i2c_set_clk(struct rk3576_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk; + + if (rate >= 198 * MHz) + src_clk = CLK_I2C_SEL_200M; + else if (rate >= 99 * MHz) + src_clk = CLK_I2C_SEL_100M; + if (rate >= 50 * MHz) + src_clk = CLK_I2C_SEL_50M; + else + src_clk = CLK_I2C_SEL_OSC; + + switch (clk_id) { + case CLK_I2C0: + rk_clrsetreg(&cru->pmuclksel_con[6], CLK_I2C0_SEL_MASK, + src_clk << CLK_I2C0_SEL_SHIFT); + break; + case CLK_I2C1: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C1_SEL_MASK, + src_clk << CLK_I2C1_SEL_SHIFT); + break; + case CLK_I2C2: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C2_SEL_MASK, + src_clk << CLK_I2C2_SEL_SHIFT); + break; + case CLK_I2C3: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C3_SEL_MASK, + src_clk << CLK_I2C3_SEL_SHIFT); + break; + case CLK_I2C4: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C4_SEL_MASK, + src_clk << CLK_I2C4_SEL_SHIFT); + break; + case CLK_I2C5: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C5_SEL_MASK, + src_clk << CLK_I2C5_SEL_SHIFT); + break; + case CLK_I2C6: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C6_SEL_MASK, + src_clk << CLK_I2C6_SEL_SHIFT); + break; + case CLK_I2C7: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C7_SEL_MASK, + src_clk << CLK_I2C7_SEL_SHIFT); + break; + case CLK_I2C8: + rk_clrsetreg(&cru->clksel_con[57], CLK_I2C8_SEL_MASK, + src_clk << CLK_I2C8_SEL_SHIFT); + case CLK_I2C9: + rk_clrsetreg(&cru->clksel_con[58], CLK_I2C9_SEL_MASK, + src_clk << CLK_I2C9_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3576_i2c_get_clk(priv, clk_id); +} + +static ulong rk3576_spi_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 sel, con; + + switch (clk_id) { + case CLK_SPI0: + con = readl(&cru->clksel_con[70]); + sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; + break; + case CLK_SPI1: + con = readl(&cru->clksel_con[71]); + sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; + break; + case CLK_SPI2: + con = readl(&cru->clksel_con[71]); + sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT; + break; + case CLK_SPI3: + con = readl(&cru->clksel_con[71]); + sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT; + break; + case CLK_SPI4: + con = readl(&cru->clksel_con[71]); + sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + switch (sel) { + case CLK_SPI_SEL_200M: + return 200 * MHz; + case CLK_SPI_SEL_100M: + return 100 * MHz; + case CLK_SPI_SEL_50M: + return 50 * MHz; + case CLK_SPI_SEL_OSC: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3576_spi_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk; + + if (rate >= 198 * MHz) + src_clk = CLK_SPI_SEL_200M; + else if (rate >= 99 * MHz) + src_clk = CLK_SPI_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = CLK_SPI_SEL_50M; + else + src_clk = CLK_SPI_SEL_OSC; + + switch (clk_id) { + case CLK_SPI0: + rk_clrsetreg(&cru->clksel_con[70], + CLK_SPI0_SEL_MASK, + src_clk << CLK_SPI0_SEL_SHIFT); + break; + case CLK_SPI1: + rk_clrsetreg(&cru->clksel_con[71], + CLK_SPI1_SEL_MASK, + src_clk << CLK_SPI1_SEL_SHIFT); + break; + case CLK_SPI2: + rk_clrsetreg(&cru->clksel_con[71], + CLK_SPI2_SEL_MASK, + src_clk << CLK_SPI2_SEL_SHIFT); + break; + case CLK_SPI3: + rk_clrsetreg(&cru->clksel_con[71], + CLK_SPI3_SEL_MASK, + src_clk << CLK_SPI3_SEL_SHIFT); + break; + case CLK_SPI4: + rk_clrsetreg(&cru->clksel_con[71], + CLK_SPI4_SEL_MASK, + src_clk << CLK_SPI4_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3576_spi_get_clk(priv, clk_id); +} + +static ulong rk3576_pwm_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 sel, con; + + switch (clk_id) { + case CLK_PWM1: + con = readl(&cru->clksel_con[71]); + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; + break; + case CLK_PWM2: + con = readl(&cru->clksel_con[74]); + sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; + break; + case CLK_PMU1PWM: + con = readl(&cru->pmuclksel_con[5]); + sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + switch (sel) { + case CLK_PWM_SEL_100M: + return 100 * MHz; + case CLK_PWM_SEL_50M: + return 50 * MHz; + case CLK_PWM_SEL_OSC: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3576_pwm_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk; + + if (rate >= 99 * MHz) + src_clk = CLK_PWM_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = CLK_PWM_SEL_50M; + else + src_clk = CLK_PWM_SEL_OSC; + + switch (clk_id) { + case CLK_PWM1: + rk_clrsetreg(&cru->clksel_con[71], + CLK_PWM1_SEL_MASK, + src_clk << CLK_PWM1_SEL_SHIFT); + break; + case CLK_PWM2: + rk_clrsetreg(&cru->clksel_con[74], + CLK_PWM2_SEL_MASK, + src_clk << CLK_PWM2_SEL_SHIFT); + break; + case CLK_PMU1PWM: + rk_clrsetreg(&cru->pmuclksel_con[5], + CLK_PMU1PWM_SEL_MASK, + src_clk << CLK_PMU1PWM_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3576_pwm_get_clk(priv, clk_id); +} + +static ulong rk3576_adc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 div, sel, con, prate; + + switch (clk_id) { + case CLK_SARADC: + con = readl(&cru->clksel_con[58]); + div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; + sel = (con & CLK_SARADC_SEL_MASK) >> + CLK_SARADC_SEL_SHIFT; + if (sel == CLK_SARADC_SEL_OSC) + prate = OSC_HZ; + else + prate = priv->gpll_hz; + return DIV_TO_RATE(prate, div); + case CLK_TSADC: + con = readl(&cru->clksel_con[59]); + div = (con & CLK_TSADC_DIV_MASK) >> + CLK_TSADC_DIV_SHIFT; + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + default: + return -ENOENT; + } +} + +static ulong rk3576_adc_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk_div; + + switch (clk_id) { + case CLK_SARADC: + if (!(OSC_HZ % rate)) { + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); + assert(src_clk_div - 1 <= 255); + rk_clrsetreg(&cru->clksel_con[58], + CLK_SARADC_SEL_MASK | + CLK_SARADC_DIV_MASK, + (CLK_SARADC_SEL_OSC << + CLK_SARADC_SEL_SHIFT) | + (src_clk_div - 1) << + CLK_SARADC_DIV_SHIFT); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 255); + rk_clrsetreg(&cru->clksel_con[59], + CLK_SARADC_SEL_MASK | + CLK_SARADC_DIV_MASK, + (CLK_SARADC_SEL_GPLL << + CLK_SARADC_SEL_SHIFT) | + (src_clk_div - 1) << + CLK_SARADC_DIV_SHIFT); + } + break; + case CLK_TSADC: + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); + assert(src_clk_div - 1 <= 255); + rk_clrsetreg(&cru->clksel_con[58], + CLK_TSADC_DIV_MASK, + (src_clk_div - 1) << + CLK_TSADC_DIV_SHIFT); + break; + default: + return -ENOENT; + } + return rk3576_adc_get_clk(priv, clk_id); +} + +static ulong rk3576_mmc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 sel, con, prate, div = 0; + + switch (clk_id) { + case CCLK_SRC_SDIO: + case HCLK_SDIO: + con = readl(&cru->clksel_con[104]); + div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT; + sel = (con & CCLK_SDIO_SRC_SEL_MASK) >> + CCLK_SDIO_SRC_SEL_SHIFT; + if (sel == CCLK_SDIO_SRC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CCLK_SDIO_SRC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case CCLK_SRC_SDMMC0: + case HCLK_SDMMC0: + con = readl(&cru->clksel_con[105]); + div = (con & CCLK_SDMMC0_SRC_DIV_MASK) >> CCLK_SDMMC0_SRC_DIV_SHIFT; + sel = (con & CCLK_SDMMC0_SRC_SEL_MASK) >> + CCLK_SDMMC0_SRC_SEL_SHIFT; + if (sel == CCLK_SDMMC0_SRC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CCLK_SDMMC0_SRC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case CCLK_SRC_EMMC: + case HCLK_EMMC: + con = readl(&cru->clksel_con[89]); + div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT; + sel = (con & CCLK_EMMC_SEL_MASK) >> + CCLK_EMMC_SEL_SHIFT; + if (sel == CCLK_EMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CCLK_EMMC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case BCLK_EMMC: + con = readl(&cru->clksel_con[90]); + sel = (con & BCLK_EMMC_SEL_MASK) >> + BCLK_EMMC_SEL_SHIFT; + if (sel == BCLK_EMMC_SEL_200M) + prate = 200 * MHz; + else if (sel == BCLK_EMMC_SEL_100M) + prate = 100 * MHz; + else if (sel == BCLK_EMMC_SEL_50M) + prate = 50 * MHz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case SCLK_FSPI_X2: + con = readl(&cru->clksel_con[89]); + div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT; + sel = (con & SCLK_FSPI_SEL_MASK) >> + SCLK_FSPI_SEL_SHIFT; + if (sel == SCLK_FSPI_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == SCLK_FSPI_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case SCLK_FSPI1_X2: + con = readl(&cru->clksel_con[106]); + div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT; + sel = (con & SCLK_FSPI_SEL_MASK) >> + SCLK_FSPI_SEL_SHIFT; + if (sel == SCLK_FSPI_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == SCLK_FSPI_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case DCLK_DECOM: + con = readl(&cru->clksel_con[72]); + div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; + sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; + if (sel == DCLK_DECOM_SEL_SPLL) + prate = priv->spll_hz; + else + prate = priv->gpll_hz; + return DIV_TO_RATE(prate, div); + + default: + return -ENOENT; + } +} + +static ulong rk3576_mmc_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk, div = 0; + + switch (clk_id) { + case CCLK_SRC_SDIO: + case CCLK_SRC_SDMMC0: + case CCLK_SRC_EMMC: + case SCLK_FSPI_X2: + case SCLK_FSPI1_X2: + case HCLK_SDMMC0: + case HCLK_EMMC: + case HCLK_SDIO: + if (!(OSC_HZ % rate)) { + src_clk = SCLK_FSPI_SEL_OSC; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (!(priv->cpll_hz % rate)) { + src_clk = SCLK_FSPI_SEL_CPLL; + div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = SCLK_FSPI_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + break; + case BCLK_EMMC: + if (rate >= 198 * MHz) + src_clk = BCLK_EMMC_SEL_200M; + else if (rate >= 99 * MHz) + src_clk = BCLK_EMMC_SEL_100M; + else if (rate >= 50 * MHz) + src_clk = BCLK_EMMC_SEL_50M; + else + src_clk = BCLK_EMMC_SEL_OSC; + break; + case DCLK_DECOM: + if (!(priv->spll_hz % rate)) { + src_clk = DCLK_DECOM_SEL_SPLL; + div = DIV_ROUND_UP(priv->spll_hz, rate); + } else { + src_clk = DCLK_DECOM_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + break; + default: + return -ENOENT; + } + + switch (clk_id) { + case CCLK_SRC_SDIO: + case HCLK_SDIO: + rk_clrsetreg(&cru->clksel_con[104], + CCLK_SDIO_SRC_SEL_MASK | + CCLK_SDIO_SRC_DIV_MASK, + (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) | + (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT); + break; + case CCLK_SRC_SDMMC0: + case HCLK_SDMMC0: + rk_clrsetreg(&cru->clksel_con[105], + CCLK_SDMMC0_SRC_SEL_MASK | + CCLK_SDMMC0_SRC_DIV_MASK, + (src_clk << CCLK_SDMMC0_SRC_SEL_SHIFT) | + (div - 1) << CCLK_SDMMC0_SRC_DIV_SHIFT); + break; + case CCLK_SRC_EMMC: + case HCLK_EMMC: + rk_clrsetreg(&cru->clksel_con[89], + CCLK_EMMC_DIV_MASK | + CCLK_EMMC_SEL_MASK, + (src_clk << CCLK_EMMC_SEL_SHIFT) | + (div - 1) << CCLK_EMMC_DIV_SHIFT); + break; + case SCLK_FSPI_X2: + rk_clrsetreg(&cru->clksel_con[89], + SCLK_FSPI_DIV_MASK | + SCLK_FSPI_SEL_MASK, + (src_clk << SCLK_FSPI_SEL_SHIFT) | + (div - 1) << SCLK_FSPI_DIV_SHIFT); + break; + case SCLK_FSPI1_X2: + rk_clrsetreg(&cru->clksel_con[106], + SCLK_FSPI_DIV_MASK | + SCLK_FSPI_SEL_MASK, + (src_clk << SCLK_FSPI_SEL_SHIFT) | + (div - 1) << SCLK_FSPI_DIV_SHIFT); + break; + case BCLK_EMMC: + rk_clrsetreg(&cru->clksel_con[90], + BCLK_EMMC_SEL_MASK, + src_clk << BCLK_EMMC_SEL_SHIFT); + break; + case DCLK_DECOM: + rk_clrsetreg(&cru->clksel_con[72], + DCLK_DECOM_DIV_MASK | + DCLK_DECOM_SEL_MASK, + (src_clk << DCLK_DECOM_SEL_SHIFT) | + (div - 1) << DCLK_DECOM_DIV_SHIFT); + break; + + default: + return -ENOENT; + } + + return rk3576_mmc_get_clk(priv, clk_id); +} + +#ifndef CONFIG_SPL_BUILD + +static ulong rk3576_aclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 div, sel, con, parent = 0; + + switch (clk_id) { + case ACLK_VOP_ROOT: + case ACLK_VOP: + con = readl(&cru->clksel_con[144]); + div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT; + sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT; + if (sel == ACLK_VOP_ROOT_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_VOP_ROOT_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == ACLK_VOP_ROOT_SEL_AUPLL) + parent = priv->aupll_hz; + else if (sel == ACLK_VOP_ROOT_SEL_SPLL) + parent = priv->spll_hz; + else if (sel == ACLK_VOP_ROOT_SEL_LPLL) + parent = priv->lpll_hz / 2; + return DIV_TO_RATE(parent, div); + case ACLK_VO0_ROOT: + con = readl(&cru->clksel_con[149]); + div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT; + sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT; + if (sel == ACLK_VO0_ROOT_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_VO0_ROOT_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == ACLK_VO0_ROOT_SEL_LPLL) + parent = priv->lpll_hz / 2; + else if (sel == ACLK_VO0_ROOT_SEL_BPLL) + parent = priv->bpll_hz / 4; + return DIV_TO_RATE(parent, div); + case ACLK_VO1_ROOT: + con = readl(&cru->clksel_con[158]); + div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT; + sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT; + if (sel == ACLK_VO0_ROOT_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_VO0_ROOT_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == ACLK_VO0_ROOT_SEL_LPLL) + parent = priv->lpll_hz / 2; + else if (sel == ACLK_VO0_ROOT_SEL_BPLL) + parent = priv->bpll_hz / 4; + return DIV_TO_RATE(parent, div); + case HCLK_VOP_ROOT: + con = readl(&cru->clksel_con[144]); + sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT; + if (sel == HCLK_VOP_ROOT_SEL_200M) + return 200 * MHz; + else if (sel == HCLK_VOP_ROOT_SEL_100M) + return 100 * MHz; + else if (sel == HCLK_VOP_ROOT_SEL_50M) + return 50 * MHz; + else + return OSC_HZ; + case PCLK_VOP_ROOT: + con = readl(&cru->clksel_con[144]); + sel = (con & PCLK_VOP_ROOT_SEL_MASK) >> PCLK_VOP_ROOT_SEL_SHIFT; + if (sel == PCLK_VOP_ROOT_SEL_100M) + return 100 * MHz; + else if (sel == PCLK_VOP_ROOT_SEL_50M) + return 50 * MHz; + else + return OSC_HZ; + + default: + return -ENOENT; + } +} + +static ulong rk3576_aclk_vop_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int src_clk, div; + + switch (clk_id) { + case ACLK_VOP_ROOT: + case ACLK_VOP: + if (rate == 700 * MHz) { + src_clk = ACLK_VOP_ROOT_SEL_SPLL; + div = 1; + } else if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_VOP_ROOT_SEL_CPLL; + div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_VOP_ROOT_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + rk_clrsetreg(&cru->clksel_con[144], + ACLK_VOP_ROOT_DIV_MASK | + ACLK_VOP_ROOT_SEL_MASK, + (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) | + (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT); + break; + case ACLK_VO0_ROOT: + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_VO0_ROOT_SEL_CPLL; + div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_VO0_ROOT_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + rk_clrsetreg(&cru->clksel_con[149], + ACLK_VO0_ROOT_DIV_MASK | + ACLK_VO0_ROOT_SEL_MASK, + (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) | + (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT); + break; + case ACLK_VO1_ROOT: + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_VO0_ROOT_SEL_CPLL; + div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_VO0_ROOT_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + rk_clrsetreg(&cru->clksel_con[158], + ACLK_VO0_ROOT_DIV_MASK | + ACLK_VO0_ROOT_SEL_MASK, + (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) | + (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT); + break; + case HCLK_VOP_ROOT: + if (rate == 200 * MHz) + src_clk = HCLK_VOP_ROOT_SEL_200M; + else if (rate == 100 * MHz) + src_clk = HCLK_VOP_ROOT_SEL_100M; + else if (rate == 50 * MHz) + src_clk = HCLK_VOP_ROOT_SEL_50M; + else + src_clk = HCLK_VOP_ROOT_SEL_OSC; + rk_clrsetreg(&cru->clksel_con[144], + HCLK_VOP_ROOT_SEL_MASK, + src_clk << HCLK_VOP_ROOT_SEL_SHIFT); + break; + case PCLK_VOP_ROOT: + if (rate == 100 * MHz) + src_clk = PCLK_VOP_ROOT_SEL_100M; + else if (rate == 50 * MHz) + src_clk = PCLK_VOP_ROOT_SEL_50M; + else + src_clk = PCLK_VOP_ROOT_SEL_OSC; + rk_clrsetreg(&cru->clksel_con[144], + PCLK_VOP_ROOT_SEL_MASK, + src_clk << PCLK_VOP_ROOT_SEL_SHIFT); + break; + + default: + return -ENOENT; + } + + return rk3576_aclk_vop_get_clk(priv, clk_id); +} + +static ulong rk3576_dclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 div, sel, con, parent; + + switch (clk_id) { + case DCLK_VP0: + case DCLK_VP0_SRC: + con = readl(&cru->clksel_con[145]); + div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; + break; + case DCLK_VP1: + case DCLK_VP1_SRC: + con = readl(&cru->clksel_con[146]); + div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; + break; + case DCLK_VP2: + case DCLK_VP2_SRC: + con = readl(&cru->clksel_con[147]); + div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + if (sel == DCLK_VOP_SRC_SEL_VPLL) + parent = priv->vpll_hz; + else if (sel == DCLK_VOP_SRC_SEL_BPLL) + parent = priv->bpll_hz / 4; + else if (sel == DCLK_VOP_SRC_SEL_LPLL) + parent = priv->lpll_hz / 2; + else if (sel == DCLK_VOP_SRC_SEL_GPLL) + parent = priv->gpll_hz; + else + parent = priv->cpll_hz; + + return DIV_TO_RATE(parent, div); +} + +#define RK3576_VOP_PLL_LIMIT_FREQ 600000000 + +static ulong rk3576_dclk_vop_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + ulong pll_rate, now, best_rate = 0; + u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; + u32 mask, div_shift, sel_shift; + + switch (clk_id) { + case DCLK_VP0: + case DCLK_VP0_SRC: + conid = 145; + con = readl(&cru->clksel_con[conid]); + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; + mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK; + div_shift = DCLK0_VOP_SRC_DIV_SHIFT; + sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; + break; + case DCLK_VP1: + case DCLK_VP1_SRC: + conid = 146; + con = readl(&cru->clksel_con[conid]); + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; + mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK; + div_shift = DCLK0_VOP_SRC_DIV_SHIFT; + sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; + break; + case DCLK_VP2: + case DCLK_VP2_SRC: + conid = 147; + con = readl(&cru->clksel_con[conid]); + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; + mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK; + div_shift = DCLK0_VOP_SRC_DIV_SHIFT; + sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + if (sel == DCLK_VOP_SRC_SEL_VPLL) { + pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], + priv->cru, VPLL); + if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { + div = DIV_ROUND_UP(pll_rate, rate); + rk_clrsetreg(&cru->clksel_con[conid], + mask, + DCLK_VOP_SRC_SEL_VPLL << sel_shift | + ((div - 1) << div_shift)); + } else { + div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ, rate); + if (div % 2) + div = div + 1; + rk_clrsetreg(&cru->clksel_con[conid], + mask, + DCLK_VOP_SRC_SEL_VPLL << sel_shift | + ((div - 1) << div_shift)); + rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], + priv->cru, VPLL, div * rate); + priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], + priv->cru, VPLL); + } + } else { + for (i = 0; i <= DCLK_VOP_SRC_SEL_LPLL; i++) { + switch (i) { + case DCLK_VOP_SRC_SEL_GPLL: + pll_rate = priv->gpll_hz; + break; + case DCLK_VOP_SRC_SEL_CPLL: + pll_rate = priv->cpll_hz; + break; + case DCLK_VOP_SRC_SEL_BPLL: + pll_rate = 0; + break; + case DCLK_VOP_SRC_SEL_LPLL: + pll_rate = 0; + break; + case DCLK_VOP_SRC_SEL_VPLL: + pll_rate = 0; + break; + default: + printf("do not support this vop pll sel\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(pll_rate, rate); + if (div > 255) + continue; + now = pll_rate / div; + if (abs(rate - now) < abs(rate - best_rate)) { + best_rate = now; + best_div = div; + best_sel = i; + } + debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n", + pll_rate, best_rate, best_div, best_sel); + } + + if (best_rate) { + rk_clrsetreg(&cru->clksel_con[conid], + mask, + best_sel << sel_shift | + (best_div - 1) << div_shift); + } else { + printf("do not support this vop freq %lu\n", rate); + return -EINVAL; + } + } + + return rk3576_dclk_vop_get_clk(priv, clk_id); +} + +static ulong rk3576_clk_csihost_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 div, sel, con, parent; + + switch (clk_id) { + case CLK_DSIHOST0: + con = readl(&cru->clksel_con[151]); + div = (con & CLK_DSIHOST0_DIV_MASK) >> CLK_DSIHOST0_DIV_SHIFT; + sel = (con & CLK_DSIHOST0_SEL_MASK) >> CLK_DSIHOST0_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + if (sel == CLK_DSIHOST0_SEL_VPLL) + parent = priv->vpll_hz; + else if (sel == CLK_DSIHOST0_SEL_BPLL) + parent = priv->bpll_hz / 4; + else if (sel == CLK_DSIHOST0_SEL_LPLL) + parent = priv->lpll_hz / 2; + else if (sel == CLK_DSIHOST0_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_DSIHOST0_SEL_SPLL) + parent = priv->spll_hz; + else + parent = priv->cpll_hz; + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3576_clk_csihost_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + ulong pll_rate, now, best_rate = 0; + u32 i, con, div, best_div = 0, best_sel = 0; + u32 mask, div_shift, sel_shift; + + switch (clk_id) { + case CLK_DSIHOST0: + con = 151; + mask = CLK_DSIHOST0_SEL_MASK | CLK_DSIHOST0_DIV_MASK; + div_shift = CLK_DSIHOST0_DIV_SHIFT; + sel_shift = CLK_DSIHOST0_SEL_SHIFT; + break; + default: + return -ENOENT; + } + for (i = 0; i <= CLK_DSIHOST0_SEL_LPLL; i++) { + switch (i) { + case CLK_DSIHOST0_SEL_GPLL: + pll_rate = priv->gpll_hz; + break; + case CLK_DSIHOST0_SEL_CPLL: + pll_rate = priv->cpll_hz; + break; + case CLK_DSIHOST0_SEL_BPLL: + pll_rate = 0; + break; + case CLK_DSIHOST0_SEL_LPLL: + pll_rate = 0; + break; + case CLK_DSIHOST0_SEL_VPLL: + pll_rate = 0; + break; + case CLK_DSIHOST0_SEL_SPLL: + pll_rate = priv->spll_hz; + break; + default: + printf("do not support this vop pll sel\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(pll_rate, rate); + if (div > 255) + continue; + now = pll_rate / div; + if (abs(rate - now) < abs(rate - best_rate)) { + best_rate = now; + best_div = div; + best_sel = i; + } + debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n", + pll_rate, best_rate, best_div, best_sel); + } + + if (best_rate) { + rk_clrsetreg(&cru->clksel_con[con], + mask, + best_sel << sel_shift | + (best_div - 1) << div_shift); + } else { + printf("do not support this vop freq %lu\n", rate); + return -EINVAL; + } + + return rk3576_clk_csihost_get_clk(priv, clk_id); +} + +static ulong rk3576_dclk_ebc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 div, sel, con, parent; + unsigned long m = 0, n = 0; + + switch (clk_id) { + case DCLK_EBC: + con = readl(&cru->clksel_con[123]); + div = (con & DCLK_EBC_DIV_MASK) >> DCLK_EBC_DIV_SHIFT; + sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; + if (sel == DCLK_EBC_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == DCLK_EBC_SEL_VPLL) + parent = priv->vpll_hz; + else if (sel == DCLK_EBC_SEL_AUPLL) + parent = priv->aupll_hz; + else if (sel == DCLK_EBC_SEL_LPLL) + parent = priv->lpll_hz / 2; + else if (sel == DCLK_EBC_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_EBC_SEL_FRAC_SRC) + parent = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC); + else + parent = OSC_HZ; + return DIV_TO_RATE(parent, div); + case DCLK_EBC_FRAC_SRC: + con = readl(&cru->clksel_con[123]); + div = readl(&cru->clksel_con[122]); + sel = (con & DCLK_EBC_FRAC_SRC_SEL_MASK) >> DCLK_EBC_FRAC_SRC_SEL_SHIFT; + if (sel == DCLK_EBC_FRAC_SRC_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_EBC_FRAC_SRC_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == DCLK_EBC_FRAC_SRC_SEL_VPLL) + parent = priv->vpll_hz; + else if (sel == DCLK_EBC_FRAC_SRC_SEL_AUPLL) + parent = priv->aupll_hz; + else + parent = OSC_HZ; + + n = div & CLK_UART_FRAC_NUMERATOR_MASK; + n >>= CLK_UART_FRAC_NUMERATOR_SHIFT; + m = div & CLK_UART_FRAC_DENOMINATOR_MASK; + m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT; + return parent * n / m; + default: + return -ENOENT; + } +} + +static ulong rk3576_dclk_ebc_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + ulong pll_rate, now, best_rate = 0; + u32 i, con, sel, div, best_div = 0, best_sel = 0; + unsigned long m = 0, n = 0, val; + + switch (clk_id) { + case DCLK_EBC: + con = readl(&cru->clksel_con[123]); + sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; + if (sel == DCLK_EBC_SEL_VPLL) { + pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], + priv->cru, VPLL); + if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && + pll_rate % rate == 0) { + div = DIV_ROUND_UP(pll_rate, rate); + rk_clrsetreg(&cru->clksel_con[123], + DCLK_EBC_DIV_MASK, + (div - 1) << DCLK_EBC_DIV_SHIFT); + } else { + div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ, + rate); + if (div % 2) + div = div + 1; + rk_clrsetreg(&cru->clksel_con[123], + DCLK_EBC_DIV_MASK, + (div - 1) << DCLK_EBC_DIV_SHIFT); + rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], + priv->cru, + VPLL, div * rate); + priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], + priv->cru, + VPLL); + } + } else if (sel == DCLK_EBC_SEL_FRAC_SRC) { + rk3576_dclk_ebc_set_clk(priv, DCLK_EBC_FRAC_SRC, rate); + div = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC) / rate; + rk_clrsetreg(&cru->clksel_con[123], + DCLK_EBC_DIV_MASK, + (div - 1) << DCLK_EBC_DIV_SHIFT); + } else { + for (i = 0; i <= DCLK_EBC_SEL_LPLL; i++) { + switch (i) { + case DCLK_EBC_SEL_GPLL: + pll_rate = priv->gpll_hz; + break; + case DCLK_EBC_SEL_CPLL: + pll_rate = priv->cpll_hz; + break; + case DCLK_EBC_SEL_VPLL: + pll_rate = 0; + break; + case DCLK_EBC_SEL_AUPLL: + pll_rate = priv->aupll_hz; + break; + case DCLK_EBC_SEL_LPLL: + pll_rate = 0; + break; + default: + printf("not support ebc pll sel\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(pll_rate, rate); + if (div > 255) + continue; + now = pll_rate / div; + if (abs(rate - now) < abs(rate - best_rate)) { + best_rate = now; + best_div = div; + best_sel = i; + } + } + + if (best_rate) { + rk_clrsetreg(&cru->clksel_con[123], + DCLK_EBC_DIV_MASK | + DCLK_EBC_SEL_MASK, + best_sel << + DCLK_EBC_SEL_SHIFT | + (best_div - 1) << + DCLK_EBC_DIV_SHIFT); + } else { + printf("do not support this vop freq %lu\n", + rate); + return -EINVAL; + } + } + break; + case DCLK_EBC_FRAC_SRC: + sel = DCLK_EBC_FRAC_SRC_SEL_GPLL; + div = 1; + rational_best_approximation(rate, priv->gpll_hz, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + + if (m < 4 && m != 0) { + if (n % 2 == 0) + val = 1; + else + val = DIV_ROUND_UP(4, m); + + n *= val; + m *= val; + if (n > 0xffff) + n = 0xffff; + } + + rk_clrsetreg(&cru->clksel_con[123], + DCLK_EBC_FRAC_SRC_SEL_MASK, + (sel << DCLK_EBC_FRAC_SRC_SEL_SHIFT)); + if (m && n) { + val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n; + writel(val, &cru->clksel_con[122]); + } + break; + default: + return -ENOENT; + } + return rk3576_dclk_ebc_get_clk(priv, clk_id); +} + +static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 con, div, src, p_rate; + + switch (clk_id) { + case CLK_GMAC0_PTP_REF_SRC: + case CLK_GMAC0_PTP_REF: + con = readl(&cru->clksel_con[105]); + div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; + src = (con & CLK_GMAC0_PTP_SEL_MASK) >> CLK_GMAC0_PTP_SEL_SHIFT; + if (src == CLK_GMAC0_PTP_SEL_GPLL) + p_rate = priv->gpll_hz; + else if (src == CLK_GMAC0_PTP_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = GMAC0_PTP_REFCLK_IN; + return DIV_TO_RATE(p_rate, div); + case CLK_GMAC1_PTP_REF_SRC: + case CLK_GMAC1_PTP_REF: + con = readl(&cru->clksel_con[104]); + div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; + src = (con & CLK_GMAC1_PTP_SEL_MASK) >> CLK_GMAC1_PTP_SEL_SHIFT; + if (src == CLK_GMAC1_PTP_SEL_GPLL) + p_rate = priv->gpll_hz; + else if (src == CLK_GMAC1_PTP_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = GMAC1_PTP_REFCLK_IN; + return DIV_TO_RATE(p_rate, div); + case CLK_GMAC0_125M_SRC: + con = readl(&cru->clksel_con[30]); + div = (con & CLK_GMAC0_125M_DIV_MASK) >> CLK_GMAC0_125M_DIV_SHIFT; + return DIV_TO_RATE(priv->cpll_hz, div); + case CLK_GMAC1_125M_SRC: + con = readl(&cru->clksel_con[31]); + div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT; + return DIV_TO_RATE(priv->cpll_hz, div); + default: + return -ENOENT; + } +} + +static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + int div, src; + + div = DIV_ROUND_UP(priv->cpll_hz, rate); + + switch (clk_id) { + case CLK_GMAC0_PTP_REF_SRC: + case CLK_GMAC0_PTP_REF: + if (rate == GMAC0_PTP_REFCLK_IN) { + src = CLK_GMAC0_PTP_SEL_REFIN; + div = 1; + } else if (!(priv->gpll_hz % rate)) { + src = CLK_GMAC0_PTP_SEL_GPLL; + div = priv->gpll_hz / rate; + } else { + src = CLK_GMAC0_PTP_SEL_CPLL; + div = priv->cpll_hz / rate; + } + rk_clrsetreg(&cru->clksel_con[105], + CLK_GMAC0_PTP_DIV_MASK | CLK_GMAC0_PTP_SEL_MASK, + src << CLK_GMAC0_PTP_SEL_SHIFT | + (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT); + break; + case CLK_GMAC1_PTP_REF_SRC: + case CLK_GMAC1_PTP_REF: + if (rate == GMAC1_PTP_REFCLK_IN) { + src = CLK_GMAC1_PTP_SEL_REFIN; + div = 1; + } else if (!(priv->gpll_hz % rate)) { + src = CLK_GMAC1_PTP_SEL_GPLL; + div = priv->gpll_hz / rate; + } else { + src = CLK_GMAC1_PTP_SEL_CPLL; + div = priv->cpll_hz / rate; + } + rk_clrsetreg(&cru->clksel_con[104], + CLK_GMAC1_PTP_DIV_MASK | CLK_GMAC1_PTP_SEL_MASK, + src << CLK_GMAC1_PTP_SEL_SHIFT | + (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT); + break; + + case CLK_GMAC0_125M_SRC: + rk_clrsetreg(&cru->clksel_con[30], + CLK_GMAC0_125M_DIV_MASK, + (div - 1) << CLK_GMAC0_125M_DIV_SHIFT); + break; + case CLK_GMAC1_125M_SRC: + rk_clrsetreg(&cru->clksel_con[31], + CLK_GMAC1_125M_DIV_MASK, + (div - 1) << CLK_GMAC1_125M_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3576_gmac_get_clk(priv, clk_id); +} + +static ulong rk3576_uart_frac_get_rate(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 reg, con, fracdiv, p_src, p_rate; + unsigned long m, n; + + switch (clk_id) { + case CLK_UART_FRAC_0: + reg = 21; + break; + case CLK_UART_FRAC_1: + reg = 23; + break; + case CLK_UART_FRAC_2: + reg = 25; + break; + default: + return -ENOENT; + } + con = readl(&cru->clksel_con[reg + 1]); + p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT; + if (p_src == CLK_UART_SRC_SEL_GPLL) + p_rate = priv->gpll_hz; + else if (p_src == CLK_UART_SRC_SEL_CPLL) + p_rate = priv->cpll_hz; + else if (p_src == CLK_UART_SRC_SEL_AUPLL) + p_rate = priv->aupll_hz; + else + p_rate = OSC_HZ; + + fracdiv = readl(&cru->clksel_con[reg]); + n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK; + n >>= CLK_UART_FRAC_NUMERATOR_SHIFT; + m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK; + m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT; + return p_rate * n / m; +} + +static ulong rk3576_uart_frac_set_rate(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + u32 reg, clk_src, p_rate; + unsigned long m = 0, n = 0, val; + + if (priv->cpll_hz % rate == 0) { + clk_src = CLK_UART_SRC_SEL_CPLL; + p_rate = priv->cpll_hz; + } else if (rate == OSC_HZ) { + clk_src = CLK_UART_SRC_SEL_OSC; + p_rate = OSC_HZ; + } else { + clk_src = CLK_UART_SRC_SEL_GPLL; + p_rate = priv->cpll_hz; + } + + rational_best_approximation(rate, p_rate, GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), &m, &n); + + if (m < 4 && m != 0) { + if (n % 2 == 0) + val = 1; + else + val = DIV_ROUND_UP(4, m); + + n *= val; + m *= val; + if (n > 0xffff) + n = 0xffff; + } + + switch (clk_id) { + case CLK_UART_FRAC_0: + reg = 21; + break; + case CLK_UART_FRAC_1: + reg = 23; + break; + case CLK_UART_FRAC_2: + reg = 25; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[reg + 1], + CLK_UART_SRC_SEL_MASK, + (clk_src << CLK_UART_SRC_SEL_SHIFT)); + if (m && n) { + val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n; + writel(val, &cru->clksel_con[reg]); + } + + return rk3576_uart_frac_get_rate(priv, clk_id); +} + +static ulong rk3576_uart_get_rate(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 con, div, src, p_rate; + + switch (clk_id) { + case SCLK_UART0: + con = readl(&cru->clksel_con[60]); + break; + case SCLK_UART1: + con = readl(&cru->pmuclksel_con[8]); + src = (con & CLK_UART1_SEL_MASK) >> CLK_UART1_SEL_SHIFT; + if (src == CLK_UART1_SEL_OSC) + return OSC_HZ; + con = readl(&cru->clksel_con[27]); + break; + case SCLK_UART2: + con = readl(&cru->clksel_con[61]); + break; + case SCLK_UART3: + con = readl(&cru->clksel_con[62]); + break; + case SCLK_UART4: + con = readl(&cru->clksel_con[63]); + break; + case SCLK_UART5: + con = readl(&cru->clksel_con[64]); + break; + case SCLK_UART6: + con = readl(&cru->clksel_con[65]); + break; + case SCLK_UART7: + con = readl(&cru->clksel_con[66]); + break; + case SCLK_UART8: + con = readl(&cru->clksel_con[67]); + break; + case SCLK_UART9: + con = readl(&cru->clksel_con[68]); + break; + case SCLK_UART10: + con = readl(&cru->clksel_con[69]); + break; + case SCLK_UART11: + con = readl(&cru->clksel_con[70]); + break; + default: + return -ENOENT; + } + if (clk_id == SCLK_UART1) { + src = (con & CLK_UART1_SRC_SEL_SHIFT) >> CLK_UART1_SRC_SEL_SHIFT; + div = (con & CLK_UART1_SRC_DIV_MASK) >> CLK_UART1_SRC_DIV_SHIFT; + } else { + src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT; + div = (con & CLK_UART_DIV_MASK) >> CLK_UART_DIV_SHIFT; + } + if (src == CLK_UART_SEL_GPLL) + p_rate = priv->gpll_hz; + else if (src == CLK_UART_SEL_CPLL) + p_rate = priv->cpll_hz; + else if (src == CLK_UART_SEL_AUPLL) + p_rate = priv->aupll_hz; + else if (src == CLK_UART_SEL_FRAC0) + p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0); + else if (src == CLK_UART_SEL_FRAC1) + p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1); + else if (src == CLK_UART_SEL_FRAC2) + p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2); + else + p_rate = OSC_HZ; + + return DIV_TO_RATE(p_rate, div); +} + +static ulong rk3576_uart_set_rate(struct rk3576_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3576_cru *cru = priv->cru; + u32 reg, clk_src = 0, div = 0; + + if (!(priv->gpll_hz % rate)) { + clk_src = CLK_UART_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } else if (!(priv->cpll_hz % rate)) { + clk_src = CLK_UART_SEL_CPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0) % rate)) { + clk_src = CLK_UART_SEL_FRAC0; + div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0), rate); + } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1) % rate)) { + clk_src = CLK_UART_SEL_FRAC1; + div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1), rate); + } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2) % rate)) { + clk_src = CLK_UART_SEL_FRAC2; + div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2), rate); + } else if (!(OSC_HZ % rate)) { + clk_src = CLK_UART_SEL_OSC; + div = DIV_ROUND_UP(OSC_HZ, rate); + } + + switch (clk_id) { + case SCLK_UART0: + reg = 60; + break; + case SCLK_UART1: + if (rate == OSC_HZ) { + rk_clrsetreg(&cru->pmuclksel_con[8], + CLK_UART1_SEL_MASK, + CLK_UART1_SEL_OSC << CLK_UART1_SEL_SHIFT); + return 0; + } + + rk_clrsetreg(&cru->clksel_con[27], + CLK_UART1_SRC_SEL_MASK | CLK_UART1_SRC_DIV_MASK, + (clk_src << CLK_UART1_SRC_SEL_SHIFT) | + ((div - 1) << CLK_UART1_SRC_DIV_SHIFT)); + rk_clrsetreg(&cru->pmuclksel_con[8], + CLK_UART1_SEL_MASK, + CLK_UART1_SEL_TOP << CLK_UART1_SEL_SHIFT); + return 0; + case SCLK_UART2: + reg = 61; + break; + case SCLK_UART3: + reg = 62; + break; + case SCLK_UART4: + reg = 63; + break; + case SCLK_UART5: + reg = 64; + break; + case SCLK_UART6: + reg = 65; + break; + case SCLK_UART7: + reg = 66; + break; + case SCLK_UART8: + reg = 67; + break; + case SCLK_UART9: + reg = 68; + break; + case SCLK_UART10: + reg = 69; + break; + case SCLK_UART11: + reg = 70; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[reg], + CLK_UART_SEL_MASK | + CLK_UART_DIV_MASK, + (clk_src << CLK_UART_SEL_SHIFT) | + ((div - 1) << CLK_UART_DIV_SHIFT)); + + return rk3576_uart_get_rate(priv, clk_id); +} +#endif + +static ulong rk3576_ufs_ref_get_rate(struct rk3576_clk_priv *priv, ulong clk_id) +{ + struct rk3576_cru *cru = priv->cru; + u32 src, div; + + src = readl(&cru->pmuclksel_con[3]) & 0x3; + div = readl(&cru->pmuclksel_con[1]) & 0xff; + if (src == 0) + return OSC_HZ; + else if (src == 2) + return priv->ppll_hz / (div + 1); + else + return 26000000; +} + +static ulong rk3576_clk_get_rate(struct clk *clk) +{ + struct rk3576_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + if (!priv->ppll_hz) { + priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], + priv->cru, PPLL); + } + + switch (clk->id) { + case PLL_LPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[LPLL], priv->cru, + LPLL); + priv->lpll_hz = rate; + break; + case PLL_BPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[BPLL], priv->cru, + BPLL); + priv->bpll_hz = rate; + break; + case PLL_GPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL], priv->cru, + GPLL); + break; + case PLL_CPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL], priv->cru, + CPLL); + break; + case PLL_VPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], priv->cru, + VPLL); + break; + case PLL_AUPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL], priv->cru, + AUPLL); + break; + case PLL_PPLL: + rate = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], priv->cru, + PPLL) * 2; + break; + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + case PCLK_BUS_ROOT: + rate = rk3576_bus_get_clk(priv, clk->id); + break; + case ACLK_TOP: + case HCLK_TOP: + case PCLK_TOP_ROOT: + case ACLK_TOP_MID: + rate = rk3576_top_get_clk(priv, clk->id); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C6: + case CLK_I2C7: + case CLK_I2C8: + case CLK_I2C9: + rate = rk3576_i2c_get_clk(priv, clk->id); + break; + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + case CLK_SPI4: + rate = rk3576_spi_get_clk(priv, clk->id); + break; + case CLK_PWM1: + case CLK_PWM2: + case CLK_PMU1PWM: + rate = rk3576_pwm_get_clk(priv, clk->id); + break; + case CLK_SARADC: + case CLK_TSADC: + rate = rk3576_adc_get_clk(priv, clk->id); + break; + case CCLK_SRC_SDIO: + case CCLK_SRC_SDMMC0: + case CCLK_SRC_EMMC: + case BCLK_EMMC: + case SCLK_FSPI_X2: + case SCLK_FSPI1_X2: + case DCLK_DECOM: + case HCLK_SDMMC0: + case HCLK_EMMC: + case HCLK_SDIO: + rate = rk3576_mmc_get_clk(priv, clk->id); + break; + case TCLK_EMMC: + case TCLK_WDT0: + rate = OSC_HZ; + break; +#ifndef CONFIG_SPL_BUILD + case ACLK_VOP_ROOT: + case ACLK_VOP: + case ACLK_VO0_ROOT: + case ACLK_VO1_ROOT: + case HCLK_VOP_ROOT: + case PCLK_VOP_ROOT: + rate = rk3576_aclk_vop_get_clk(priv, clk->id); + break; + case DCLK_VP0: + case DCLK_VP0_SRC: + case DCLK_VP1: + case DCLK_VP1_SRC: + case DCLK_VP2: + case DCLK_VP2_SRC: + rate = rk3576_dclk_vop_get_clk(priv, clk->id); + break; + case CLK_GMAC0_PTP_REF_SRC: + case CLK_GMAC1_PTP_REF_SRC: + case CLK_GMAC0_PTP_REF: + case CLK_GMAC1_PTP_REF: + case CLK_GMAC0_125M_SRC: + case CLK_GMAC1_125M_SRC: + rate = rk3576_gmac_get_clk(priv, clk->id); + break; + case CLK_UART_FRAC_0: + case CLK_UART_FRAC_1: + case CLK_UART_FRAC_2: + rate = rk3576_uart_frac_get_rate(priv, clk->id); + break; + case SCLK_UART0: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + case SCLK_UART8: + case SCLK_UART9: + case SCLK_UART10: + case SCLK_UART11: + rate = rk3576_uart_get_rate(priv, clk->id); + break; + case CLK_DSIHOST0: + rate = rk3576_clk_csihost_get_clk(priv, clk->id); + break; + case DCLK_EBC: + case DCLK_EBC_FRAC_SRC: + rate = rk3576_dclk_ebc_get_clk(priv, clk->id); + break; +#endif + case CLK_REF_UFS_CLKOUT: + case CLK_REF_OSC_MPHY: + rate = rk3576_ufs_ref_get_rate(priv, clk->id); + break; + + default: + return -ENOENT; + } + + return rate; +}; + +static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3576_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->ppll_hz) { + priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], + priv->cru, PPLL); + } + if (!priv->aupll_hz) { + priv->aupll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL], + priv->cru, AUPLL); + } + + switch (clk->id) { + case PLL_CPLL: + ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru, + CPLL, rate); + priv->cpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL], + priv->cru, CPLL); + break; + case PLL_GPLL: + ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru, + GPLL, rate); + priv->gpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL], + priv->cru, GPLL); + break; + case PLL_VPLL: + ret = rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], priv->cru, + VPLL, rate); + priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], + priv->cru, VPLL); + break; + case PLL_AUPLL: + ret = rockchip_pll_set_rate(&rk3576_pll_clks[AUPLL], priv->cru, + AUPLL, rate); + priv->aupll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL], + priv->cru, AUPLL); + break; + case PLL_PPLL: + ret = rockchip_pll_set_rate(&rk3576_pll_clks[PPLL], priv->cru, + PPLL, rate); + priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], + priv->cru, PPLL) * 2; + break; + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + case PCLK_BUS_ROOT: + ret = rk3576_bus_set_clk(priv, clk->id, rate); + break; + case ACLK_TOP: + case HCLK_TOP: + case PCLK_TOP_ROOT: + case ACLK_TOP_MID: + ret = rk3576_top_set_clk(priv, clk->id, rate); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C6: + case CLK_I2C7: + case CLK_I2C8: + case CLK_I2C9: + ret = rk3576_i2c_set_clk(priv, clk->id, rate); + break; + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + case CLK_SPI4: + ret = rk3576_spi_set_clk(priv, clk->id, rate); + break; + case CLK_PWM1: + case CLK_PWM2: + case CLK_PMU1PWM: + ret = rk3576_pwm_set_clk(priv, clk->id, rate); + break; + case CLK_SARADC: + case CLK_TSADC: + ret = rk3576_adc_set_clk(priv, clk->id, rate); + break; + case CCLK_SRC_SDIO: + case CCLK_SRC_SDMMC0: + case CCLK_SRC_EMMC: + case BCLK_EMMC: + case SCLK_FSPI_X2: + case SCLK_FSPI1_X2: + case DCLK_DECOM: + case HCLK_SDMMC0: + case HCLK_EMMC: + case HCLK_SDIO: + ret = rk3576_mmc_set_clk(priv, clk->id, rate); + break; + case TCLK_EMMC: + case TCLK_WDT0: + ret = OSC_HZ; + break; + + /* Might occur in cru assigned-clocks, can be ignored here */ + case CLK_AUDIO_FRAC_0: + case CLK_AUDIO_FRAC_1: + case CLK_AUDIO_FRAC_0_SRC: + case CLK_AUDIO_FRAC_1_SRC: + case CLK_CPLL_DIV2: + case CLK_CPLL_DIV4: + case CLK_CPLL_DIV10: + case FCLK_DDR_CM0_CORE: + case ACLK_PHP_ROOT: + ret = 0; + break; +#ifndef CONFIG_SPL_BUILD + case ACLK_VOP_ROOT: + case ACLK_VOP: + case ACLK_VO0_ROOT: + case ACLK_VO1_ROOT: + case HCLK_VOP_ROOT: + case PCLK_VOP_ROOT: + ret = rk3576_aclk_vop_set_clk(priv, clk->id, rate); + break; + case DCLK_VP0: + case DCLK_VP0_SRC: + case DCLK_VP1: + case DCLK_VP1_SRC: + case DCLK_VP2: + case DCLK_VP2_SRC: + ret = rk3576_dclk_vop_set_clk(priv, clk->id, rate); + break; + case CLK_GMAC0_PTP_REF_SRC: + case CLK_GMAC1_PTP_REF_SRC: + case CLK_GMAC0_PTP_REF: + case CLK_GMAC1_PTP_REF: + case CLK_GMAC0_125M_SRC: + case CLK_GMAC1_125M_SRC: + ret = rk3576_gmac_set_clk(priv, clk->id, rate); + break; + case CLK_UART_FRAC_0: + case CLK_UART_FRAC_1: + case CLK_UART_FRAC_2: + ret = rk3576_uart_frac_set_rate(priv, clk->id, rate); + break; + case SCLK_UART0: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + case SCLK_UART8: + case SCLK_UART9: + case SCLK_UART10: + case SCLK_UART11: + ret = rk3576_uart_set_rate(priv, clk->id, rate); + break; + case CLK_DSIHOST0: + ret = rk3576_clk_csihost_set_clk(priv, clk->id, rate); + break; + case DCLK_EBC: + case DCLK_EBC_FRAC_SRC: + ret = rk3576_dclk_ebc_set_clk(priv, clk->id, rate); + break; +#endif + default: + return -ENOENT; + } + + return ret; +}; + +#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA)) +static int __maybe_unused rk3576_dclk_vop_set_parent(struct clk *clk, + struct clk *parent) +{ + struct rk3576_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3576_cru *cru = priv->cru; + u32 sel; + const char *clock_dev_name = parent->dev->name; + + if (parent->id == PLL_VPLL) + sel = 2; + else if (parent->id == PLL_GPLL) + sel = 0; + else if (parent->id == PLL_CPLL) + sel = 1; + else if (parent->id == PLL_BPLL) + sel = 3; + else + sel = 4; + + switch (clk->id) { + case DCLK_VP0_SRC: + rk_clrsetreg(&cru->clksel_con[145], DCLK0_VOP_SRC_SEL_MASK, + sel << DCLK0_VOP_SRC_SEL_SHIFT); + break; + case DCLK_VP1_SRC: + rk_clrsetreg(&cru->clksel_con[146], DCLK0_VOP_SRC_SEL_MASK, + sel << DCLK0_VOP_SRC_SEL_SHIFT); + break; + case DCLK_VP2_SRC: + rk_clrsetreg(&cru->clksel_con[147], DCLK0_VOP_SRC_SEL_MASK, + sel << DCLK0_VOP_SRC_SEL_SHIFT); + break; + case DCLK_VP0: + if (!strcmp(clock_dev_name, "hdmiphypll_clk0")) + sel = 1; + else + sel = 0; + rk_clrsetreg(&cru->clksel_con[147], DCLK0_VOP_SEL_MASK, + sel << DCLK0_VOP_SEL_SHIFT); + break; + case DCLK_VP1: + if (!strcmp(clock_dev_name, "hdmiphypll_clk0")) + sel = 1; + else + sel = 0; + rk_clrsetreg(&cru->clksel_con[147], DCLK1_VOP_SEL_MASK, + sel << DCLK1_VOP_SEL_SHIFT); + break; + case DCLK_VP2: + if (!strcmp(clock_dev_name, "hdmiphypll_clk0")) + sel = 1; + else + sel = 0; + rk_clrsetreg(&cru->clksel_con[147], DCLK2_VOP_SEL_MASK, + sel << DCLK2_VOP_SEL_SHIFT); + break; + case DCLK_EBC: + if (parent->id == PLL_GPLL) + sel = 0; + else if (parent->id == PLL_CPLL) + sel = 1; + else if (parent->id == PLL_VPLL) + sel = 2; + else if (parent->id == PLL_AUPLL) + sel = 3; + else if (parent->id == PLL_LPLL) + sel = 4; + else if (parent->id == DCLK_EBC_FRAC_SRC) + sel = 5; + else + sel = 6; + rk_clrsetreg(&cru->clksel_con[123], DCLK_EBC_SEL_MASK, + sel << DCLK_EBC_SEL_SHIFT); + break; + default: + return -EINVAL; + } + return 0; +} + +static int __maybe_unused rk3576_ufs_ref_set_parent(struct clk *clk, + struct clk *parent) +{ + struct rk3576_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3576_cru *cru = priv->cru; + u32 sel; + const char *clock_dev_name = parent->dev->name; + + if (parent->id == CLK_REF_MPHY_26M) + sel = 2; + else if (!strcmp(clock_dev_name, "xin24m")) + sel = 0; + else + sel = 1; + + rk_clrsetreg(&cru->pmuclksel_con[3], 0x3, sel << 0); + return 0; +} + +static int rk3576_clk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case DCLK_VP0_SRC: + case DCLK_VP1_SRC: + case DCLK_VP2_SRC: + case DCLK_VP0: + case DCLK_VP1: + case DCLK_VP2: + case DCLK_EBC: + return rk3576_dclk_vop_set_parent(clk, parent); + case CLK_REF_OSC_MPHY: + return rk3576_ufs_ref_set_parent(clk, parent); + case CLK_AUDIO_FRAC_0_SRC: + case CLK_AUDIO_FRAC_1_SRC: + /* Might occur in cru assigned-clocks, can be ignored here */ + return 0; + default: + return -ENOENT; + } + + return 0; +} +#endif + +static struct clk_ops rk3576_clk_ops = { + .get_rate = rk3576_clk_get_rate, + .set_rate = rk3576_clk_set_rate, +#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA)) + .set_parent = rk3576_clk_set_parent, +#endif +}; + +static void rk3576_clk_init(struct rk3576_clk_priv *priv) +{ + int ret; + + priv->spll_hz = 702000000; + + if (priv->cpll_hz != CPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru, + CPLL, CPLL_HZ); + if (!ret) + priv->cpll_hz = CPLL_HZ; + } + if (priv->gpll_hz != GPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru, + GPLL, GPLL_HZ); + if (!ret) + priv->gpll_hz = GPLL_HZ; + } + rk_clrsetreg(&priv->cru->clksel_con[123], + DCLK_EBC_FRAC_SRC_SEL_MASK, + (DCLK_EBC_FRAC_SRC_SEL_GPLL << + DCLK_EBC_FRAC_SRC_SEL_SHIFT)); +} + +static int rk3576_clk_probe(struct udevice *dev) +{ + struct rk3576_clk_priv *priv = dev_get_priv(dev); + int ret; + + priv->sync_kernel = false; + +#ifdef CONFIG_SPL_BUILD + /* relase presetn_bigcore_biu/cru/grf */ + writel(0x1c001c00, 0x26010010); + /* set spll to normal mode */ + writel(BITS_WITH_WMASK(2, 0x7U, 6), + RK3576_SCRU_BASE + RK3576_PLL_CON(137)); + writel(BITS_WITH_WMASK(1, 0x3U, 0), + RK3576_SCRU_BASE + RK3576_MODE_CON0); + /* fix ppll\aupll\cpll */ + writel(BITS_WITH_WMASK(2, 0x7U, 6), + RK3576_CRU_BASE + RK3576_PMU_PLL_CON(129)); + writel(BITS_WITH_WMASK(2, 0x7U, 6), + RK3576_CRU_BASE + RK3576_PLL_CON(97)); + writel(BITS_WITH_WMASK(2, 0x7U, 6), + RK3576_CRU_BASE + RK3576_PLL_CON(105)); + writel(BITS_WITH_WMASK(1, 0x3U, 6), + RK3576_CRU_BASE + RK3576_MODE_CON0); + writel(BITS_WITH_WMASK(1, 0x3U, 8), + RK3576_CRU_BASE + RK3576_MODE_CON0); + /* init cci */ + writel(0xffff0000, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4)); + rockchip_pll_set_rate(&rk3576_pll_clks[BPLL], priv->cru, + BPLL, LPLL_HZ); + if (!priv->armclk_enter_hz) { + ret = rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru, + LPLL, LPLL_HZ); + priv->armclk_enter_hz = + rockchip_pll_get_rate(&rk3576_pll_clks[LPLL], + priv->cru, LPLL); + priv->armclk_init_hz = priv->armclk_enter_hz; + rk_clrsetreg(&priv->cru->litclksel_con[0], CLK_LITCORE_DIV_MASK, + 0 << CLK_LITCORE_DIV_SHIFT); + } + /* init cci */ + writel(0xffff20cb, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4)); + + /* Change bigcore rm from 4 to 3 */ + writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x3c); + writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x44); + writel(0x00020002, RK3576_BIGCORE_GRF_BASE + 0x38); + udelay(1); + writel(0x00020000, RK3576_BIGCORE_GRF_BASE + 0x38); + /* Change litcore rm from 4 to 3 */ + writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x3c); + writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x44); + writel(0x00020002, RK3576_LITCORE_GRF_BASE + 0x38); + udelay(1); + writel(0x00020000, RK3576_LITCORE_GRF_BASE + 0x38); + /* Change cci rm form 4 to 3 */ + writel(0x001c000c, RK3576_CCI_GRF_BASE + 0x54); +#endif + + rk3576_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + debug("%s clk_set_defaults failed %d\n", __func__, ret); + else + priv->sync_kernel = true; + + return 0; +} + +static int rk3576_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3576_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rk3576_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3576_cru, + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rk3576_cru, + glb_srsr_snd); + dev_set_priv(sys_child, priv); + } + +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + ret = offsetof(struct rk3576_cru, softrst_con[0]); + ret = rk3576_reset_bind_lut(dev, ret, 32776); + if (ret) + debug("Warning: software reset driver bind failed\n"); +#endif + + return 0; +} + +static const struct udevice_id rk3576_clk_ids[] = { + { .compatible = "rockchip,rk3576-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3576_cru) = { + .name = "rockchip_rk3576_cru", + .id = UCLASS_CLK, + .of_match = rk3576_clk_ids, + .priv_auto = sizeof(struct rk3576_clk_priv), + .of_to_plat = rk3576_clk_ofdata_to_platdata, + .ops = &rk3576_clk_ops, + .bind = rk3576_clk_bind, + .probe = rk3576_clk_probe, +}; diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index db9435db657..fc09dde3f9e 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -10,6 +10,7 @@ #include <asm/arch/base_addr_soc64.h> #include <asm/io.h> #include <linux/bitfield.h> +#include <linux/sizes.h> #include "iossm_mailbox.h" #define TIMEOUT_120000MS 120000 @@ -87,6 +88,7 @@ /* offset info of ECC_ENABLE_INTF */ #define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0) +#define INTF_ECC_TYPE_MASK BIT(8) /* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */ #define BIST_FULL_MEM BIT(6) @@ -96,6 +98,7 @@ /* offset info of ECC_ERR_STATUS */ #define ECC_ERR_COUNTER_MASK GENMASK(15, 0) +#define ECC_ERR_OVERFLOW_MASK GENMASK(31, 16) /* offset info of ECC_ERR_DATA */ #define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22) @@ -104,9 +107,15 @@ #define ECC_ERR_TYPE_MASK GENMASK(9, 6) #define ECC_ERR_ADDR_UPPER_MASK GENMASK(5, 0) #define ECC_ERR_ADDR_LOWER_MASK GENMASK(31, 0) +#define ECC_FULL_ADDR_UPPER_MASK GENMASK(63, 32) +#define ECC_FULL_ADDR_LOWER_MASK GENMASK(31, 0) #define MAX_ECC_ERR_INFO_COUNT 16 +#define BIST_START_ADDR_SPACE_MASK GENMASK(5, 0) +#define BIST_START_ADDR_LOW_MASK GENMASK(31, 0) +#define BIST_START_ADDR_HIGH_MASK GENMASK(37, 32) + #define IO96B_MB_REQ_SETUP(v, w, x, y, z) \ usr_req.ip_type = v; \ usr_req.ip_id = w; \ @@ -161,6 +170,24 @@ struct ecc_err_info { u32 addr_lower; }; +struct ecc_overflow_error_desc { + int bit; + const char *msg; +}; + +static const struct ecc_overflow_error_desc ecc_overflow_errors[] = { + { 0, " - Single-bit error\n" }, + { 1, " - Multiple single-bit errors\n" }, + { 2, " - Double-bit error\n" }, + { 3, " - Multiple double-bit errors\n" }, + { 8, " - Single-bit error during ECC scrubbing\n" }, + { 9, " - Write link ECC single-bit error (LPDDR5 only)\n" }, + { 10, " - Write link ECC double-bit error (LPDDR5 only)\n" }, + { 11, " - Read link ECC single-bit error (LPDDR5 only)\n" }, + { 12, " - Read link ECC double-bit error (LPDDR5 only)\n" }, + { 13, " - RMW read link ECC double-bit error (LPDDR5 only)\n" }, +}; + static int is_ddr_csr_clkgen_locked(u8 io96b_pll) { int ret = 0; @@ -512,7 +539,7 @@ int get_mem_width_info(struct io96b_info *io96b_ctrl) { int i, j, ret = 0; u32 mem_width_info; - u16 memory_size, total_memory_size = 0; + phys_size_t memory_size, total_memory_size = 0; u32 mem_total_capacity_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET, @@ -526,8 +553,11 @@ int get_mem_width_info(struct io96b_info *io96b_ctrl) mem_width_info = readl(io96b_ctrl->io96b[i].io96b_csr_addr + mem_total_capacity_intf_offset[j]); - memory_size = memory_size + - FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info); + io96b_ctrl->io96b[i].mb_ctrl.memory_size[j] = + FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info) * SZ_1G / SZ_8; + + if (io96b_ctrl->io96b[i].mb_ctrl.memory_size[j] != 0) + memory_size += io96b_ctrl->io96b[i].mb_ctrl.memory_size[j]; } if (!memory_size) { @@ -536,8 +566,6 @@ int get_mem_width_info(struct io96b_info *io96b_ctrl) goto err; } - io96b_ctrl->io96b[i].size = memory_size; - total_memory_size = total_memory_size + memory_size; } @@ -556,7 +584,7 @@ int ecc_enable_status(struct io96b_info *io96b_ctrl) { int i, j, ret = 0; u32 ecc_enable_intf; - bool ecc_stat, ecc_stat_set = false; + bool ecc_status, ecc_status_set = false, inline_ecc = false; u32 ecc_enable_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { IOSSM_ECC_ENABLE_INTF0_OFFSET, @@ -565,6 +593,7 @@ int ecc_enable_status(struct io96b_info *io96b_ctrl) /* Initialize ECC status */ io96b_ctrl->ecc_status = false; + io96b_ctrl->inline_ecc = false; /* Get and ensure all memory interface(s) same ECC status */ for (i = 0; i < io96b_ctrl->num_instance; i++) { @@ -572,15 +601,21 @@ int ecc_enable_status(struct io96b_info *io96b_ctrl) ecc_enable_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr + ecc_enable_intf_offset[j]); - ecc_stat = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf) + ecc_status = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf) == 0) ? false : true; + inline_ecc = FIELD_GET(INTF_ECC_TYPE_MASK, ecc_enable_intf); + + if (!ecc_status_set) { + io96b_ctrl->ecc_status = ecc_status; + + if (io96b_ctrl->ecc_status) + io96b_ctrl->inline_ecc = inline_ecc; - if (!ecc_stat_set) { - io96b_ctrl->ecc_status = ecc_stat; - ecc_stat_set = true; + ecc_status_set = true; } - if (ecc_stat != io96b_ctrl->ecc_status) { + if (ecc_status != io96b_ctrl->ecc_status || + (io96b_ctrl->ecc_status && inline_ecc != io96b_ctrl->inline_ecc)) { printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i); ret = -EINVAL; @@ -614,16 +649,28 @@ bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) { int i, j; u32 ecc_err_status; - u16 ecc_err_counter; + u16 ecc_err_counter, ecc_overflow_status; bool ecc_error_flag = false; /* Get ECC double-bit error status */ for (i = 0; i < io96b_ctrl->num_instance; i++) { ecc_err_status = readl(io96b_ctrl->io96b[i].io96b_csr_addr + IOSSM_ECC_ERR_STATUS_OFFSET); + ecc_err_counter = FIELD_GET(ECC_ERR_COUNTER_MASK, ecc_err_status); - debug("%s: ECC error number detected on IO96B_%d: %d\n", - __func__, i, ecc_err_counter); + log_err("%s: ECC error number detected on IO96B_%d: %d\n", + __func__, i, ecc_err_counter); + + ecc_overflow_status = FIELD_GET(ECC_ERR_OVERFLOW_MASK, ecc_err_status); + if (ecc_overflow_status != 0) { + log_err("ECC Error Overflow Flags:\n"); + + for (int i = 0; i < ARRAY_SIZE(ecc_overflow_errors); i++) { + if (ecc_overflow_status & BIT(ecc_overflow_errors[i].bit)) { + log_err("%s", ecc_overflow_errors[i].msg); + } + } + } if (ecc_err_counter != 0) { phys_addr_t address; @@ -647,15 +694,20 @@ bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) ecc_err_data); err_info.addr_lower = readl(address + sizeof(u32)); - debug("%s: ECC double-bit error detected on IO96B_%d:\n", - __func__, i); - debug("- error info address :0x%llx\n", address); - debug("- error ip type: %d\n", err_info.ip_type); - debug("- error instance id: %d\n", err_info.instance_id); - debug("- error source id: %d\n", err_info.source_id); - debug("- error type: %d\n", err_info.err_type); - debug("- error address upper: 0x%x\n", err_info.addr_upper); - debug("- error address lower: 0x%x\n", err_info.addr_lower); + log_err(" %s: DDR ECC Error Detected on IO96B_%d number:%d\n", + __func__, i, j); + log_err(" - error info address :0x%llx\n", address); + log_err(" - error ip type: %d\n", err_info.ip_type); + log_err(" - error instance id: %d\n", err_info.instance_id); + log_err(" - error source id: %d\n", err_info.source_id); + log_err(" - error type: %s\n", + is_double_bit_error(err_info.err_type) ? + "Double-bit error" : "Single-bit error"); + log_err(" - error address: 0x%016llx\n", + (u64)FIELD_PREP(ECC_FULL_ADDR_UPPER_MASK, + err_info.addr_upper) | + FIELD_PREP(ECC_FULL_ADDR_LOWER_MASK, + err_info.addr_lower)); if (is_double_bit_error(err_info.err_type)) { if (!ecc_error_flag) @@ -668,12 +720,12 @@ bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) } if (ecc_error_flag) - printf("\n%s: ECC double-bit error detected!\n", __func__); + log_err("\n%s: ECC double-bit error detected!\n", __func__); return ecc_error_flag; } -int bist_mem_init_start(struct io96b_info *io96b_ctrl) +int out_of_band_bist_mem_init_start(struct io96b_info *io96b_ctrl) { struct io96b_mb_req usr_req; struct io96b_mb_resp usr_resp; @@ -746,3 +798,126 @@ int bist_mem_init_start(struct io96b_info *io96b_ctrl) err: return ret; } + +int bist_mem_init_by_addr(struct io96b_info *io96b_ctrl, int inst_id, int intf_id, + phys_addr_t base_addr, phys_size_t size) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int n, ret = 0; + bool bist_start, bist_success; + u32 mem_exp, mem_init_status_intf, start; + phys_size_t chunk_size; + + u32 mem_init_status_offset[MAX_MEM_INTERFACE_SUPPORTED] = { + IOSSM_MEM_INIT_STATUS_INTF0_OFFSET, + IOSSM_MEM_INIT_STATUS_INTF1_OFFSET + }; + + /* Check if size is a power of 2 */ + if (size == 0 || (size & (size - 1)) != 0) { + ret = -EINVAL; + goto err; + } + + mem_exp = 0; + chunk_size = size; + + while (chunk_size >>= 1) + mem_exp++; + + /* Start memory initialization BIST on the specified address range */ + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[inst_id].mb_ctrl.ip_type[intf_id], + io96b_ctrl->io96b[inst_id].mb_ctrl.ip_id[intf_id], + CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0); + + /* CMD_PARAM_0 bit[5:0] = mem_exp */ + /* CMD_PARAM_0 bit[6]: 0 - on the specified address range */ + usr_req.cmd_param[0] = FIELD_PREP(BIST_START_ADDR_SPACE_MASK, mem_exp); + /* Extract address fields START_ADDR[31:0] */ + usr_req.cmd_param[1] = FIELD_GET(BIST_START_ADDR_LOW_MASK, base_addr); + /* Extract address fields START_ADDR[37:32] */ + usr_req.cmd_param[2] = FIELD_GET(BIST_START_ADDR_HIGH_MASK, base_addr); + /* Initialize memory to all zeros */ + usr_req.cmd_param[3] = 0; + + bist_start = false; + bist_success = false; + + /* Send request to DDR controller */ + debug("%s:Initializing memory: Addr=0x%llx, Size=2^%u\n", __func__, + base_addr, mem_exp); + ret = io96b_mb_req(io96b_ctrl->io96b[inst_id].io96b_csr_addr, + usr_req, 0, &usr_resp); + if (ret) + goto err; + + bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_start) { + printf("%s: Failed to initialize memory on IO96B_%d\n", __func__, + inst_id); + printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -EINVAL; + goto err; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + udelay(1); + + mem_init_status_intf = readl(io96b_ctrl->io96b[inst_id].io96b_csr_addr + + mem_init_status_offset[intf_id]); + + bist_success = FIELD_GET(INTF_BIST_STATUS_MASK, mem_init_status_intf); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_%d\n", + __func__, inst_id); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n", + __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -ETIMEDOUT; + goto err; + } + } + + debug("%s:DDR memory initializationat 0x%llx completed.\n", __func__, base_addr); + +err: + return ret; +} + +int inline_ecc_bist_mem_init(struct io96b_info *io96b_ctrl) +{ + int i, j, ret = 0; + + /* Memory initialization BIST performed on all memory interfaces */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + ret = bist_mem_init_by_addr(io96b_ctrl, i, j, 0, + io96b_ctrl->io96b[i].mb_ctrl.memory_size[j]); + if (ret) { + printf("Error: Memory init failed at Instance %d, Interface %d\n", + i, j); + goto err; + } + } + } + +err: + return ret; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + if (io96b_ctrl->inline_ecc) + return inline_ecc_bist_mem_init(io96b_ctrl); + else + return out_of_band_bist_mem_init_start(io96b_ctrl); +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h index 6f794781d30..02d1db28e20 100644 --- a/drivers/ddr/altera/iossm_mailbox.h +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -40,11 +40,13 @@ enum iossm_mailbox_cmd_opcode { * @num_mem_interface: Number of memory interfaces instantiated * @ip_type: IP type implemented on the IO96B * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + * @memory_size[2]: Memory size for every IP instance implemented on the IO96B */ struct io96b_mb_ctrl { u32 num_mem_interface; u32 ip_type[2]; u32 ip_id[2]; + phys_size_t memory_size[2]; }; /* CMD_REQ Register Definition */ @@ -53,6 +55,9 @@ struct io96b_mb_ctrl { #define CMD_TYPE_MASK GENMASK(23, 16) #define CMD_OPCODE_MASK GENMASK(15, 0) +/* Computes the Inline ECC data region size */ +#define CALC_INLINE_ECC_HW_SIZE(size) (((size) * 7) / 8) + /* * IOSSM mailbox request * @ip_type: IP type for the specified memory interface @@ -83,13 +88,11 @@ struct io96b_mb_resp { /* * IO96B instance specific information * - * @size: Memory size * @io96b_csr_addr: IO96B instance CSR address * @cal_status: IO96B instance calibration status * @mb_ctrl: IOSSM mailbox required information */ struct io96b_instance { - u16 size; phys_addr_t io96b_csr_addr; bool cal_status; struct io96b_mb_ctrl mb_ctrl; @@ -102,6 +105,7 @@ struct io96b_instance { * @overall_cal_status: Overall calibration status for all IO96B instance(s) * @ddr_type: DDR memory type * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @inline_ecc: Inline ECC or Out of Band ECC (false = Out of Band ECC, true = Inline ECC) * @overall_size: Total DDR memory size * @io96b[]: IO96B instance specific information * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked) @@ -115,7 +119,8 @@ struct io96b_info { bool overall_cal_status; const char *ddr_type; bool ecc_status; - u16 overall_size; + bool inline_ecc; + phys_size_t overall_size; struct io96b_instance io96b[MAX_IO96B_SUPPORTED]; bool ckgen_lock; u8 num_port; diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index 801a6bbab46..ee66c72157a 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -291,7 +291,14 @@ int sdram_mmr_init_full(struct udevice *dev) goto err; } - hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get ECC enabled status\n"); + + goto err; + } + + hw_size = io96b_ctrl->overall_size; /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, @@ -303,6 +310,9 @@ int sdram_mmr_init_full(struct udevice *dev) goto err; } + if (io96b_ctrl->inline_ecc) + hw_size = CALC_INLINE_ECC_HW_SIZE(hw_size); + if (gd->ram_size > hw_size) { printf("DDR: Warning: DRAM size from device tree (%lld MiB) exceeds\n", gd->ram_size >> 20); @@ -355,13 +365,6 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20); - ret = ecc_enable_status(io96b_ctrl); - if (ret) { - printf("DDR: Failed to get ECC enabled status\n"); - - goto err; - } - /* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC * enabled to preserve memory content */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index c8c9211adce..27fbe80ed41 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -185,35 +185,51 @@ void sdram_init_ecc_bits(struct bd_info *bd) void sdram_size_check(struct bd_info *bd) { phys_size_t total_ram_check = 0; - phys_size_t ram_check = 0; - phys_addr_t start = 0; - phys_size_t size, remaining_size; int bank; /* Sanity check ensure correct SDRAM size specified */ debug("DDR: Running SDRAM size sanity check\n"); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + phys_size_t ram_check = 0; + phys_addr_t start = 0; + phys_size_t remaining_size; + start = bd->bi_dram[bank].start; remaining_size = bd->bi_dram[bank].size; + debug("Checking bank %d: start=0x%llx, size=0x%llx\n", + bank, start, remaining_size); + while (ram_check < bd->bi_dram[bank].size) { - size = min((phys_addr_t)SZ_1G, - (phys_addr_t)remaining_size); - - /* - * Ensure the size is power of two, this is requirement - * to run get_ram_size() / memory test - */ - if (size != 0 && ((size & (size - 1)) == 0)) { - ram_check += get_ram_size((void *) - (start + ram_check), size); - remaining_size = bd->bi_dram[bank].size - - ram_check; - } else { - puts("DDR: Memory test requires SDRAM size "); - puts("in power of two!\n"); + phys_size_t size, test_size, detected_size; + + size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); + + if (size < SZ_8) { + puts("Invalid size: Memory size required to be multiple\n"); + puts("of 64-Bit word!\n"); hang(); } + + /* Adjust size to the nearest power of two to support get_ram_size() */ + test_size = SZ_8; + + while (test_size * 2 <= size) + test_size *= 2; + + debug("Testing memory at 0x%llx with size 0x%llx\n", + start + ram_check, test_size); + detected_size = get_ram_size((void *)(start + ram_check), test_size); + + if (detected_size != test_size) { + debug("Detected size 0x%llx doesn’t match the test size 0x%llx!\n", + detected_size, test_size); + puts("Memory testing failed!\n"); + hang(); + } + + ram_check += detected_size; + remaining_size = bd->bi_dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -249,7 +265,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); - size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + size *= ((phys_size_t)2 << (hmc_ecc_readl(plat, DDRIOCTRL) & DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); return size; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 4b1b80d7abe..2940181e83e 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -5,6 +5,8 @@ * Copyright (C) 2018-2019 Xilinx, Inc. */ +#include <asm/arch/hardware.h> +#include <asm/io.h> #include <cpu_func.h> #include <dm.h> #include <dm/device_compat.h> @@ -169,6 +171,32 @@ unsigned int zynqmp_firmware_version(void) return pm_api_version; }; +#if defined(CONFIG_ARCH_VERSAL2) +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value) +{ + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY); + return 0; +} + +int zynqmp_pm_ufs_sram_csr_read(u32 *value) +{ + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + return 0; +} + +int zynqmp_pm_ufs_sram_csr_write(u32 *value) +{ + writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + return 0; +} + +int zynqmp_pm_ufs_cal_reg(u32 *value) +{ + *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); + return 0; +} +#endif + int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) { int ret; @@ -195,6 +223,52 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value) return ret; } +u32 zynqmp_pm_get_bootmode_reg(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n" + , __func__, ret); + return 0; + } + + ret = xilinx_pm_request(PM_IOCTL, CRP_BOOT_MODE_REG_NODE, IOCTL_READ_REG, + CRP_BOOT_MODE_REG_OFFSET, 0, ret_payload); + if (ret) { + printf("%s: node 0x%x: get_bootmode 0x%x failed\n", + __func__, CRP_BOOT_MODE_REG_NODE, CRP_BOOT_MODE_REG_OFFSET); + return 0; + } + + return ret_payload[1]; +} + +u32 zynqmp_pm_get_pmc_multi_boot_reg(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n" + , __func__, ret); + return 0; + } + + ret = xilinx_pm_request(PM_IOCTL, PM_REG_PMC_GLOBAL_NODE, IOCTL_READ_REG, + PMC_MULTI_BOOT_MODE_REG_OFFSET, 0, ret_payload); + if (ret) { + printf("%s: node 0x%x: get_bootmode 0x%x failed\n", + __func__, PM_REG_PMC_GLOBAL_NODE, PMC_MULTI_BOOT_MODE_REG_OFFSET); + return 0; + } + + return ret_payload[1]; +} + int zynqmp_pm_feature(const u32 api_id) { int ret; diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index 9f253b0fd40..96c2922b067 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -163,5 +163,4 @@ U_BOOT_DRIVER(sandbox_scmi_devices) = { .priv_auto = sizeof(struct sandbox_scmi_device_priv), .remove = sandbox_scmi_devices_remove, .probe = sandbox_scmi_devices_probe, - .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 8c907c3b032..e6e43ae936a 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -427,14 +427,8 @@ static int scmi_bind_protocols(struct udevice *dev) break; case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN: if (IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) && - scmi_protocol_is_supported(dev, protocol_id)) { - node = ofnode_find_subnode(node, "regulators"); - if (!ofnode_valid(node)) { - dev_err(dev, "no regulators node\n"); - return -ENXIO; - } + scmi_protocol_is_supported(dev, protocol_id)) drv = DM_DRIVER_GET(scmi_voltage_domain); - } break; default: break; diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 190a1e3f5fc..54d6689ce78 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -696,20 +696,25 @@ static int ti_sci_cmd_put_device(const struct ti_sci_handle *handle, u32 id) MSG_DEVICE_SW_STATE_AUTO_OFF); } -static -int ti_sci_cmd_release_exclusive_devices(const struct ti_sci_handle *handle) +static int ti_sci_cmd_release_exclusive_devices(void) { struct ti_sci_exclusive_dev *dev, *tmp; struct ti_sci_info *info; int i, cnt; - info = handle_to_ti_sci_info(handle); - - list_for_each_entry_safe(dev, tmp, &info->dev_list, list) { - cnt = dev->count; - debug("%s: id = %d, cnt = %d\n", __func__, dev->id, cnt); - for (i = 0; i < cnt; i++) - ti_sci_cmd_put_device(handle, dev->id); + /* + * Scan all ti_sci_list registrations, since with FIT images, we could + * have started with one device tree registration and switched over + * to a final version. This prevents exclusive devices identified + * during the first probe to be left orphan. + */ + list_for_each_entry(info, &ti_sci_list, list) { + list_for_each_entry_safe(dev, tmp, &info->dev_list, list) { + cnt = dev->count; + debug("%s: id = %d, cnt = %d\n", __func__, dev->id, cnt); + for (i = 0; i < cnt; i++) + ti_sci_cmd_put_device(&info->handle, dev->id); + } } return 0; diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index ae06f0123a0..64fda3a307c 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,6 +12,10 @@ /* * Altera FPGA support */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/misc.h> +#endif #include <errno.h> #include <ACEX1K.h> #include <log.h> @@ -47,6 +51,43 @@ static const struct altera_fpga { #endif }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +int fpga_is_partial_data(int devnum, size_t img_len) +{ + /* + * The FPGA data (full or partial) is checked by + * the SDM hardware, for Intel SDM Mailbox based + * devices. Hence always return full bitstream. + * + * For Cyclone V and Arria 10 family, the bitstream + * type parameter is not handled by the driver. + */ + return 0; +} + +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) +{ + int ret_val; + int flags = 0; + + ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags); + + /* + * Enable the HPS to FPGA bridges when FPGA load is completed + * successfully. This is to ensure the FPGA is accessible + * by the HPS. + */ + if (!ret_val) { + printf("Enable FPGA bridges\n"); + do_bridge_reset(1, ~0); + } + + return ret_val; +} +#endif + static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) { diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 1957e8dcaca..d691f135e89 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -41,8 +41,15 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits(bin_buf); buf_hi = upper_32_bits(bin_buf); - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); + + if (desc->family == xilinx_versal2) { + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi, + buf_lo, 0, ret_payload); + } else { + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + buf_hi, 0, ret_payload); + } + if (ret) printf("PL FPGA LOAD failed with err: 0x%08x\n", ret); diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 46e76385961..146bc621c7e 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -510,6 +510,15 @@ config SYS_I2C_OMAP24XX help Add support for the OMAP2+ I2C driver. +config SYS_I2C_OMAP24XX_REPEATED_START + bool "Enable I2C repeated start" + depends on SYS_I2C_OMAP24XX + default y if ARCH_K3 + help + Enable support for repeated start. Updates driver defaults to not + send a Stop condition and issue Repeated Start (Sr) for subsequent + i2c msgs. + config SYS_I2C_RCAR_I2C bool "Renesas R-Car I2C driver" depends on (RCAR_GEN2 || RCAR_64) && DM_I2C diff --git a/drivers/i2c/mtk_i2c.c b/drivers/i2c/mtk_i2c.c index 3450177741a..55381dbeced 100644 --- a/drivers/i2c/mtk_i2c.c +++ b/drivers/i2c/mtk_i2c.c @@ -143,7 +143,6 @@ static const uint mt_i2c_regs_v1[] = { [REG_RSV_DEBUG] = 0x44, [REG_HS] = 0x48, [REG_SOFTRESET] = 0x50, - [REG_SOFTRESET] = 0x50, [REG_DCM_EN] = 0x54, [REG_DEBUGSTAT] = 0x64, [REG_DEBUGCTRL] = 0x68, @@ -879,7 +878,7 @@ static const struct udevice_id mtk_i2c_ids[] = { }, { .compatible = "mediatek,mt8518-i2c", .data = (ulong)&mt8518_soc_data, - } + }, {} }; U_BOOT_DRIVER(mtk_i2c) = { diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index ebe472e20cd..a6361d3d17d 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -535,12 +535,16 @@ pr_exit: return res; } +#if !CONFIG_IS_ENABLED(DM_I2C) +/* + * The legacy I2C functions. These need to get removed once + * all users of this driver are converted to DM. + */ + /* * i2c_read: Function now uses a single I2C read transaction with bulk transfer * of the requested number of bytes (note that the 'i2c md' command - * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is - * defined in the board config header, this transaction shall be with - * Repeated Start (Sr) between the address and data phases; otherwise + * limits this to 16 bytes anyway). * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). * The address (reg offset) may be 0, 1 or 2 bytes long. * Function now reads correctly from chips that return more than one @@ -608,16 +612,10 @@ static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay, if (alen) { /* Must write reg offset first */ -#ifdef CONFIG_I2C_REPEATED_START - /* No stop bit, use Repeated Start (Sr) */ - omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | - I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG); -#else /* Stop - Start (P-S) */ omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, OMAP_I2C_CON_REG); -#endif /* Send register offset */ while (1) { status = wait_for_event(i2c_base, ip_rev, waitdelay); @@ -836,11 +834,6 @@ wr_exit: return i2c_error; } -#if !CONFIG_IS_ENABLED(DM_I2C) -/* - * The legacy I2C functions. These need to get removed once - * all users of this driver are converted to DM. - */ static void __iomem *omap24_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { @@ -971,28 +964,140 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, #else /* CONFIG_DM_I2C */ +static int __omap24_i2c_xfer_msg(void __iomem *i2c_base, int ip_rev, int waitdelay, + uchar chip, uchar *buffer, int len, u16 i2c_con_reg) +{ + int i; + u16 status; + int i2c_error = 0; + int timeout = I2C_TIMEOUT; + + if (len < 0) { + printf("%s: data len < 0\n", __func__); + return -EINVAL; + } + + if (!buffer) { + printf("%s: NULL pointer passed\n", __func__); + return -EINVAL; + } + + if (!(i2c_con_reg & I2C_CON_EN)) { + printf("%s: I2C_CON_EN not set\n", __func__); + return -EINVAL; + } + + /* Set slave address */ + omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); + /* Read/Write len bytes data */ + omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG); + /* Configure the I2C_CON register */ + omap_i2c_write_reg(i2c_base, ip_rev, i2c_con_reg, OMAP_I2C_CON_REG); + + /* read/write data bytewise */ + for (i = 0; i < len; i++) { + status = wait_for_event(i2c_base, ip_rev, waitdelay); + /* Ignore I2C_STAT_RRDY in transmitter mode */ + if (i2c_con_reg & I2C_CON_TRX) + status &= ~I2C_STAT_RRDY; + else + status &= ~I2C_STAT_XRDY; + + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = -EREMOTEIO; + printf("%s: pads on bus probably not configured (status=0x%x)\n", + __func__, status); + goto xfer_exit; + } + if (status == 0 || (status & I2C_STAT_NACK)) { + i2c_error = -EREMOTEIO; + printf("%s: error waiting for ACK (status=0x%x)\n", + __func__, status); + goto xfer_exit; + } + if (status & I2C_STAT_XRDY) { + /* Transmit data */ + omap_i2c_write_reg(i2c_base, ip_rev, + buffer[i], OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_XRDY, OMAP_I2C_STAT_REG); + } + if (status & I2C_STAT_RRDY) { + /* Receive data */ + *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev, + OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_RRDY, OMAP_I2C_STAT_REG); + } + } + + /* + * poll ARDY bit for making sure that last byte really has been + * transferred on the bus. + */ + do { + status = wait_for_event(i2c_base, ip_rev, waitdelay); + } while (!(status & I2C_STAT_ARDY) && timeout--); + if (timeout <= 0) { + printf("%s: timed out on last byte!\n", __func__); + i2c_error = -EREMOTEIO; + goto xfer_exit; + } else { + omap_i2c_write_reg(i2c_base, ip_rev, I2C_STAT_ARDY, OMAP_I2C_STAT_REG); + } + + /* If Stop bit set, flush FIFO. */ + if (i2c_con_reg & I2C_CON_STP) + goto xfer_exit; + + return 0; + +xfer_exit: + flush_fifo(i2c_base, ip_rev); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); + return i2c_error; +} + static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { struct omap_i2c *priv = dev_get_priv(bus); int ret; + u16 i2c_con_reg = 0; - debug("i2c_xfer: %d messages\n", nmsgs); - for (; nmsgs > 0; nmsgs--, msg++) { - debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); - if (msg->flags & I2C_M_RD) { - ret = __omap24_i2c_read(priv->regs, priv->ip_rev, - priv->waitdelay, - msg->addr, 0, 0, msg->buf, - msg->len); - } else { - ret = __omap24_i2c_write(priv->regs, priv->ip_rev, - priv->waitdelay, - msg->addr, 0, 0, msg->buf, - msg->len); - } + debug("%s: %d messages\n", __func__, nmsgs); + for (int i = 0; i < nmsgs; i++, msg++) { + /* + * If previous msg sent a Stop or if this is the first msg + * Wait until bus not busy + */ + if ((i2c_con_reg & I2C_CON_STP) || (i == 0)) + if (wait_for_bb(priv->regs, priv->ip_rev, priv->waitdelay)) + return -EREMOTEIO; + + /* Set Controller mode with Start bit */ + i2c_con_reg = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT; + /* Set Transmitter/Receiver mode if it is a write/read msg */ + if (msg->flags & I2C_M_RD) + i2c_con_reg &= ~I2C_CON_TRX; + else + i2c_con_reg |= I2C_CON_TRX; + /* Send Stop condition (P) by default */ + if (!IS_ENABLED(CONFIG_SYS_I2C_OMAP24XX_REPEATED_START)) + i2c_con_reg |= I2C_CON_STP; + /* Send Stop if explicitly requested or if this is the last msg */ + if ((msg->flags & I2C_M_STOP) || (i == nmsgs - 1)) + i2c_con_reg |= I2C_CON_STP; + + debug("%s: chip=0x%x, len=0x%x, i2c_con_reg=0x%x\n", + __func__, msg->addr, msg->len, i2c_con_reg); + + ret = __omap24_i2c_xfer_msg(priv->regs, priv->ip_rev, priv->waitdelay, + msg->addr, msg->buf, msg->len, + i2c_con_reg); if (ret) { - debug("i2c_write: error sending\n"); - return -EREMOTEIO; + printf("%s: errored out at msg %d: %d\n", __func__, i, ret); + return ret; } } diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c index 2123c31038f..46820425a84 100644 --- a/drivers/misc/rockchip-otp.c +++ b/drivers/misc/rockchip-otp.c @@ -361,6 +361,13 @@ static const struct rockchip_otp_data rk3568_data = { .block_size = 2, }; +static const struct rockchip_otp_data rk3576_data = { + .read = rockchip_rk3588_otp_read, + .offset = 0x700, + .size = 0x100, + .block_size = 4, +}; + static const struct rockchip_otp_data rk3588_data = { .read = rockchip_rk3588_otp_read, .offset = 0xC00, @@ -384,10 +391,18 @@ static const struct udevice_id rockchip_otp_ids[] = { .data = (ulong)&px30_data, }, { + .compatible = "rockchip,rk3528-otp", + .data = (ulong)&rk3568_data, + }, + { .compatible = "rockchip,rk3568-otp", .data = (ulong)&rk3568_data, }, { + .compatible = "rockchip,rk3576-otp", + .data = (ulong)&rk3576_data, + }, + { .compatible = "rockchip,rk3588-otp", .data = (ulong)&rk3588_data, }, diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 3ea665d974d..38867f30a7e 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -871,7 +871,7 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" - depends on ARCH_MEDIATEK || ARCH_MTMIPS + depends on ARCH_MEDIATEK || ARCH_MTMIPS || ARCH_AIROHA depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index b4c60a48d2e..0df3568f073 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -125,12 +125,15 @@ static const struct timing_data td[] = { [MMC_LEGACY] = {"ti,otap-del-sel-legacy", "ti,itap-del-sel-legacy", 0}, - [MMC_HS] = {"ti,otap-del-sel-mmc-hs", - "ti,itap-del-sel-mms-hs", + [MMC_HS] = {"ti,otap-del-sel-mmc-hs26", + "ti,itap-del-sel-mmc-hs26", MMC_CAP(MMC_HS)}, [SD_HS] = {"ti,otap-del-sel-sd-hs", "ti,itap-del-sel-sd-hs", MMC_CAP(SD_HS)}, + [MMC_HS_52] = {"ti,otap-del-sel-mmc-hs", + "ti,itap-del-sel-mmc-hs", + MMC_CAP(MMC_HS_52)}, [UHS_SDR12] = {"ti,otap-del-sel-sdr12", "ti,itap-del-sel-sdr12", MMC_CAP(UHS_SDR12)}, @@ -409,8 +412,7 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg) */ case SD_HS: case MMC_HS: - case UHS_SDR12: - case UHS_SDR25: + case MMC_HS_52: val &= ~SDHCI_CTRL_HISPD; default: break; @@ -521,13 +523,24 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) return 0; } #endif + +void am654_sdhci_set_control_reg(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + + sdhci_set_voltage(host); + + if (mmc->selected_mode > MMC_HS_52) + sdhci_set_uhs_timing(host); +} + const struct sdhci_ops am654_sdhci_ops = { #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .platform_execute_tuning = am654_sdhci_execute_tuning, #endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &am654_sdhci_set_ios_post, - .set_control_reg = sdhci_set_control_reg, + .set_control_reg = am654_sdhci_set_control_reg, .write_b = am654_sdhci_write_b, }; @@ -587,7 +600,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = { #endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &j721e_4bit_sdhci_set_ios_post, - .set_control_reg = sdhci_set_control_reg, + .set_control_reg = am654_sdhci_set_control_reg, .write_b = am654_sdhci_write_b, }; diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 9af84da1599..2f4dc5bd887 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -83,6 +83,19 @@ int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us) return dm_mmc_wait_dat0(mmc->dev, state, timeout_us); } +void dm_mmc_send_init_stream(struct udevice *dev) +{ + struct dm_mmc_ops *ops = mmc_get_ops(dev); + + if (ops->send_init_stream) + ops->send_init_stream(dev); +} + +void mmc_send_init_stream(struct mmc *mmc) +{ + dm_mmc_send_init_stream(mmc->dev); +} + static int dm_mmc_get_wp(struct udevice *dev) { struct dm_mmc_ops *ops = mmc_get_ops(dev); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 47139e0a911..cdcf2e0c8fe 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1663,6 +1663,10 @@ static int mmc_execute_tuning(struct mmc *mmc, uint opcode) } #endif +static void mmc_send_init_stream(struct mmc *mmc) +{ +} + static int mmc_set_ios(struct mmc *mmc) { int ret = 0; @@ -2550,7 +2554,7 @@ static int mmc_startup(struct mmc *mmc) /* * For MMC cards, set the Relative Address. - * For SD cards, get the Relatvie Address. + * For SD cards, get the Relative Address. * This also puts the cards into Standby State */ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ @@ -2929,6 +2933,8 @@ int mmc_get_op_cond(struct mmc *mmc, bool quiet) retry: mmc_set_initial_state(mmc); + mmc_send_init_stream(mmc); + /* Reset the Card */ err = mmc_go_idle(mmc); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index e66ab25d02a..92bc72b267c 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -780,6 +780,14 @@ tuning_error: return ret; } #endif + +static void omap_hsmmc_send_init_stream(struct udevice *dev) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct hsmmc *mmc_base = priv->base_addr; + + mmc_init_stream(mmc_base); +} #endif static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) @@ -1515,9 +1523,10 @@ static const struct dm_mmc_ops omap_hsmmc_ops = { .get_wp = omap_hsmmc_getwp, #endif #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) - .execute_tuning = omap_hsmmc_execute_tuning, + .execute_tuning = omap_hsmmc_execute_tuning, #endif - .wait_dat0 = omap_hsmmc_wait_dat0, + .send_init_stream = omap_hsmmc_send_init_stream, + .wait_dat0 = omap_hsmmc_wait_dat0, }; #else static const struct mmc_ops omap_hsmmc_ops = { diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 422b8f7e4c8..7a72abaa38a 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -171,6 +171,7 @@ static int rockchip_dwmmc_bind(struct udevice *dev) static const struct udevice_id rockchip_dwmmc_ids[] = { { .compatible = "rockchip,rk2928-dw-mshc" }, { .compatible = "rockchip,rk3288-dw-mshc" }, + { .compatible = "rockchip,rk3576-dw-mshc" }, { } }; diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index da630b9d97a..761e3619329 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -50,6 +50,10 @@ #define DWCMSHC_EMMC_EMMC_CTRL 0x52c #define DWCMSHC_CARD_IS_EMMC BIT(0) #define DWCMSHC_ENHANCED_STROBE BIT(8) +#define DWCMSHC_EMMC_AT_CTRL 0x540 +#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16) +#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17 +#define EMMC_AT_CTRL_POST_CHANGE_DLY 19 #define DWCMSHC_EMMC_DLL_CTRL 0x800 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) #define DWCMSHC_EMMC_DLL_RXCLK 0x804 @@ -156,6 +160,9 @@ struct sdhci_data { u32 flags; u8 hs200_txclk_tapnum; u8 hs400_txclk_tapnum; + u8 hs400_cmdout_tapnum; + u8 hs400_strbin_tapnum; + u8 ddr50_strbin_delay_num; }; static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) @@ -323,6 +330,11 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab udelay(1); sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); + extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY | + 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY | + EMMC_AT_CTRL_TUNE_CLK_STOP_EN; + sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL); + /* Init DLL settings */ extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | @@ -348,7 +360,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab extra = DLL_CMDOUT_SRC_CLK_NEG | DLL_CMDOUT_BOTH_CLK_EDGE | DWCMSHC_EMMC_DLL_DLYENA | - DLL_CMDOUT_TAPNUM_90_DEGREES | + data->hs400_cmdout_tapnum | DLL_CMDOUT_TAPNUM_FROM_SW; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT); } @@ -360,7 +372,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); extra = DWCMSHC_EMMC_DLL_DLYENA | - DLL_STRBIN_TAPNUM_DEFAULT | + data->hs400_strbin_tapnum | DLL_STRBIN_TAPNUM_FROM_SW; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } else { @@ -380,7 +392,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab */ extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_STRBIN_DELAY_NUM_SEL | - DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; + data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } @@ -647,6 +659,17 @@ static const struct sdhci_data rk3399_data = { .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe, }; +static const struct sdhci_data rk3528_data = { + .set_ios_post = rk3568_sdhci_set_ios_post, + .set_clock = rk3568_sdhci_set_clock, + .config_dll = rk3568_sdhci_config_dll, + .hs200_txclk_tapnum = 0xc, + .hs400_txclk_tapnum = 0x6, + .hs400_cmdout_tapnum = 0x6, + .hs400_strbin_tapnum = 0x3, + .ddr50_strbin_delay_num = 0xa, +}; + static const struct sdhci_data rk3568_data = { .set_ios_post = rk3568_sdhci_set_ios_post, .set_clock = rk3568_sdhci_set_clock, @@ -654,6 +677,20 @@ static const struct sdhci_data rk3568_data = { .flags = FLAG_INVERTER_FLAG_IN_RXCLK, .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, .hs400_txclk_tapnum = 0x8, + .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES, + .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT, + .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT, +}; + +static const struct sdhci_data rk3576_data = { + .set_ios_post = rk3568_sdhci_set_ios_post, + .set_clock = rk3568_sdhci_set_clock, + .config_dll = rk3568_sdhci_config_dll, + .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, + .hs400_txclk_tapnum = 0x7, + .hs400_cmdout_tapnum = 0x7, + .hs400_strbin_tapnum = 0x5, + .ddr50_strbin_delay_num = 0xa, }; static const struct sdhci_data rk3588_data = { @@ -662,6 +699,9 @@ static const struct sdhci_data rk3588_data = { .config_dll = rk3568_sdhci_config_dll, .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, .hs400_txclk_tapnum = 0x9, + .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES, + .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT, + .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT, }; static const struct udevice_id sdhci_ids[] = { @@ -670,10 +710,18 @@ static const struct udevice_id sdhci_ids[] = { .data = (ulong)&rk3399_data, }, { + .compatible = "rockchip,rk3528-dwcmshc", + .data = (ulong)&rk3528_data, + }, + { .compatible = "rockchip,rk3568-dwcmshc", .data = (ulong)&rk3568_data, }, { + .compatible = "rockchip,rk3576-dwcmshc", + .data = (ulong)&rk3576_data, + }, + { .compatible = "rockchip,rk3588-dwcmshc", .data = (ulong)&rk3588_data, }, diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index dc7f0724a7b..648dfa4b5ef 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -549,7 +549,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host) sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); } -static void sdhci_set_voltage(struct sdhci_host *host) +void sdhci_set_voltage(struct sdhci_host *host) { if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) { struct mmc *mmc = (struct mmc *)host->mmc; diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index f5ddfbf4b83..3a1e7e18736 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -941,6 +941,19 @@ spinand_select_op_variant(struct spinand_device *spinand, return NULL; } +static int spinand_setup_slave(struct spinand_device *spinand, + const struct spinand_info *spinand_info) +{ + struct spi_slave *slave = spinand->slave; + struct udevice *bus = slave->dev->parent; + struct dm_spi_ops *ops = spi_get_ops(bus); + + if (!ops->setup_for_spinand) + return 0; + + return ops->setup_for_spinand(slave, spinand_info); +} + /** * spinand_match_and_init() - Try to find a match between a device ID and an * entry in a spinand_info table @@ -964,6 +977,7 @@ int spinand_match_and_init(struct spinand_device *spinand, u8 *id = spinand->id.data; struct nand_device *nand = spinand_to_nand(spinand); unsigned int i; + int ret; for (i = 0; i < table_size; i++) { const struct spinand_info *info = &table[i]; @@ -975,6 +989,10 @@ int spinand_match_and_init(struct spinand_device *spinand, if (memcmp(id + 1, info->devid.id, info->devid.len)) continue; + ret = spinand_setup_slave(spinand, info); + if (ret) + return ret; + nand->memorg = table[i].memorg; nand->eccreq = table[i].eccreq; spinand->eccinfo = table[i].eccinfo; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 3db784faedd..4434d364777 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -48,7 +48,6 @@ config DM_DSA bool "Enable Driver Model for DSA switches" depends on DM_MDIO depends on PHY_FIXED - depends on !NET_LWIP help Enable driver model for DSA switches @@ -122,6 +121,14 @@ config AG7XXX This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips. +config AIROHA_ETH + bool "Airoha Ethernet QDMA Driver" + depends on ARCH_AIROHA + select PHYLIB + select DM_RESET + help + This Driver support Airoha Ethernet QDMA Driver + Say Y to enable support for the Airoha Ethernet QDMA. config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" @@ -350,7 +357,7 @@ config ESSEDMA config ETH_SANDBOX depends on SANDBOX - depends on NET + depends on NET || NET_LWIP default y bool "Sandbox: Mocked Ethernet driver" help @@ -359,17 +366,6 @@ config ETH_SANDBOX This driver is particularly useful in the test/dm/eth.c tests -config ETH_SANDBOX_LWIP - depends on SANDBOX - depends on NET_LWIP - default y - bool "Sandbox: Mocked Ethernet driver (for NET_LWIP)" - help - This driver is meant as a replacement for ETH_SANDBOX when - the network stack is NET_LWIP rather than NET. It currently - does nothing, i.e. it drops the sent packets and never receives - data. - config ETH_SANDBOX_RAW depends on SANDBOX depends on NET diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d919d437c08..67bba3a8536 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o +obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o @@ -40,7 +41,6 @@ obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_ETH_SANDBOX) += sandbox.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o -obj-$(CONFIG_ETH_SANDBOX_LWIP) += sandbox-lwip.o obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c new file mode 100644 index 00000000000..7e35e1fd41d --- /dev/null +++ b/drivers/net/airoha_eth.c @@ -0,0 +1,948 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Based on Linux airoha_eth.c majorly rewritten + * and simplified for U-Boot usage for single TX/RX ring. + * + * Copyright (c) 2024 AIROHA Inc + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Christian Marangi <ansuelsmth@gmail.org> + */ + +#include <dm.h> +#include <dm/devres.h> +#include <mapmem.h> +#include <net.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/time.h> + +#define AIROHA_MAX_NUM_GDM_PORTS 1 +#define AIROHA_MAX_NUM_QDMA 1 +#define AIROHA_MAX_NUM_RSTS 3 +#define AIROHA_MAX_NUM_XSI_RSTS 4 + +#define AIROHA_MAX_PACKET_SIZE 2048 +#define AIROHA_NUM_TX_RING 1 +#define AIROHA_NUM_RX_RING 1 +#define AIROHA_NUM_TX_IRQ 1 +#define HW_DSCP_NUM 32 +#define IRQ_QUEUE_LEN 1 +#define TX_DSCP_NUM 16 +#define RX_DSCP_NUM PKTBUFSRX + +/* SCU */ +#define SCU_SHARE_FEMEM_SEL 0x958 + +/* SWITCH */ +#define SWITCH_MFC 0x10 +#define SWITCH_BC_FFP GENMASK(31, 24) +#define SWITCH_UNM_FFP GENMASK(23, 16) +#define SWITCH_UNU_FFP GENMASK(15, 8) +#define SWITCH_PMCR(_n) 0x3000 + ((_n) * 0x100) +#define SWITCH_IPG_CFG GENMASK(19, 18) +#define SWITCH_IPG_CFG_NORMAL FIELD_PREP(SWITCH_IPG_CFG, 0x0) +#define SWITCH_IPG_CFG_SHORT FIELD_PREP(SWITCH_IPG_CFG, 0x1) +#define SWITCH_IPG_CFG_SHRINK FIELD_PREP(SWITCH_IPG_CFG, 0x2) +#define SWITCH_MAC_MODE BIT(16) +#define SWITCH_FORCE_MODE BIT(15) +#define SWITCH_MAC_TX_EN BIT(14) +#define SWITCH_MAC_RX_EN BIT(13) +#define SWITCH_BKOFF_EN BIT(9) +#define SWITCH_BKPR_EN BIT(8) +#define SWITCH_FORCE_RX_FC BIT(5) +#define SWITCH_FORCE_TX_FC BIT(4) +#define SWITCH_FORCE_SPD GENMASK(3, 2) +#define SWITCH_FORCE_SPD_10 FIELD_PREP(SWITCH_FORCE_SPD, 0x0) +#define SWITCH_FORCE_SPD_100 FIELD_PREP(SWITCH_FORCE_SPD, 0x1) +#define SWITCH_FORCE_SPD_1000 FIELD_PREP(SWITCH_FORCE_SPD, 0x2) +#define SWITCH_FORCE_DPX BIT(1) +#define SWITCH_FORCE_LNK BIT(0) +#define SWITCH_SMACCR0 0x30e4 +#define SMACCR0_MAC2 GENMASK(31, 24) +#define SMACCR0_MAC3 GENMASK(23, 16) +#define SMACCR0_MAC4 GENMASK(15, 8) +#define SMACCR0_MAC5 GENMASK(7, 0) +#define SWITCH_SMACCR1 0x30e8 +#define SMACCR1_MAC0 GENMASK(15, 8) +#define SMACCR1_MAC1 GENMASK(7, 0) +#define SWITCH_PHY_POLL 0x7018 +#define SWITCH_PHY_AP_EN GENMASK(30, 24) +#define SWITCH_EEE_POLL_EN GENMASK(22, 16) +#define SWITCH_PHY_PRE_EN BIT(15) +#define SWITCH_PHY_END_ADDR GENMASK(12, 8) +#define SWITCH_PHY_ST_ADDR GENMASK(4, 0) + +/* FE */ +#define PSE_BASE 0x0100 +#define CSR_IFC_BASE 0x0200 +#define CDM1_BASE 0x0400 +#define GDM1_BASE 0x0500 +#define PPE1_BASE 0x0c00 + +#define CDM2_BASE 0x1400 +#define GDM2_BASE 0x1500 + +#define GDM3_BASE 0x1100 +#define GDM4_BASE 0x2500 + +#define GDM_BASE(_n) \ + ((_n) == 4 ? GDM4_BASE : \ + (_n) == 3 ? GDM3_BASE : \ + (_n) == 2 ? GDM2_BASE : GDM1_BASE) + +#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) +#define GDM_DROP_CRC_ERR BIT(23) +#define GDM_IP4_CKSUM BIT(22) +#define GDM_TCP_CKSUM BIT(21) +#define GDM_UDP_CKSUM BIT(20) +#define GDM_UCFQ_MASK GENMASK(15, 12) +#define GDM_BCFQ_MASK GENMASK(11, 8) +#define GDM_MCFQ_MASK GENMASK(7, 4) +#define GDM_OCFQ_MASK GENMASK(3, 0) + +/* QDMA */ +#define REG_QDMA_GLOBAL_CFG 0x0004 +#define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31) +#define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29) +#define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28) +#define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27) +#define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26) +#define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25) +#define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24) +#define GLOBAL_CFG_RESET_MASK BIT(23) +#define GLOBAL_CFG_RESET_DONE_MASK BIT(22) +#define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21) +#define GLOBAL_CFG_IRQ1_EN_MASK BIT(20) +#define GLOBAL_CFG_IRQ0_EN_MASK BIT(19) +#define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18) +#define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17) +#define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16) +#define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8) +#define GLOBAL_CFG_CHECK_DONE_MASK BIT(7) +#define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6) +#define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4) +#define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3) +#define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2) +#define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1) +#define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0) + +#define REG_FWD_DSCP_BASE 0x0010 +#define REG_FWD_BUF_BASE 0x0014 + +#define REG_HW_FWD_DSCP_CFG 0x0018 +#define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28) +#define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16) +#define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0) + +#define REG_INT_STATUS(_n) \ + (((_n) == 4) ? 0x0730 : \ + ((_n) == 3) ? 0x0724 : \ + ((_n) == 2) ? 0x0720 : \ + ((_n) == 1) ? 0x0024 : 0x0020) + +#define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050) + +#define REG_TX_IRQ_CFG(_n) ((_n) ? 0x004c : 0x0054) +#define TX_IRQ_THR_MASK GENMASK(27, 16) +#define TX_IRQ_DEPTH_MASK GENMASK(11, 0) + +#define REG_IRQ_CLEAR_LEN(_n) ((_n) ? 0x0064 : 0x0058) +#define IRQ_CLEAR_LEN_MASK GENMASK(7, 0) + +#define REG_TX_RING_BASE(_n) \ + (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5)) + +#define REG_TX_CPU_IDX(_n) \ + (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5)) + +#define TX_RING_CPU_IDX_MASK GENMASK(15, 0) + +#define REG_TX_DMA_IDX(_n) \ + (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5)) + +#define TX_RING_DMA_IDX_MASK GENMASK(15, 0) + +#define IRQ_RING_IDX_MASK GENMASK(20, 16) +#define IRQ_DESC_IDX_MASK GENMASK(15, 0) + +#define REG_RX_RING_BASE(_n) \ + (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5)) + +#define REG_RX_RING_SIZE(_n) \ + (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5)) + +#define RX_RING_THR_MASK GENMASK(31, 16) +#define RX_RING_SIZE_MASK GENMASK(15, 0) + +#define REG_RX_CPU_IDX(_n) \ + (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5)) + +#define RX_RING_CPU_IDX_MASK GENMASK(15, 0) + +#define REG_RX_DMA_IDX(_n) \ + (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5)) + +#define REG_RX_DELAY_INT_IDX(_n) \ + (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5)) + +#define RX_DELAY_INT_MASK GENMASK(15, 0) + +#define RX_RING_DMA_IDX_MASK GENMASK(15, 0) + +#define REG_LMGR_INIT_CFG 0x1000 +#define LMGR_INIT_START BIT(31) +#define LMGR_SRAM_MODE_MASK BIT(30) +#define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20) +#define HW_FWD_DESC_NUM_MASK GENMASK(16, 0) + +/* CTRL */ +#define QDMA_DESC_DONE_MASK BIT(31) +#define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */ +#define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */ +#define QDMA_DESC_DEI_MASK BIT(25) +#define QDMA_DESC_NO_DROP_MASK BIT(24) +#define QDMA_DESC_LEN_MASK GENMASK(15, 0) +/* DATA */ +#define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0) +/* TX MSG0 */ +#define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30) +#define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14) +#define QDMA_ETH_TXMSG_ICO_MASK BIT(13) +#define QDMA_ETH_TXMSG_UCO_MASK BIT(12) +#define QDMA_ETH_TXMSG_TCO_MASK BIT(11) +#define QDMA_ETH_TXMSG_TSO_MASK BIT(10) +#define QDMA_ETH_TXMSG_FAST_MASK BIT(9) +#define QDMA_ETH_TXMSG_OAM_MASK BIT(8) +#define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3) +#define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0) +/* TX MSG1 */ +#define QDMA_ETH_TXMSG_NO_DROP BIT(31) +#define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */ +#define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20) +#define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15) +#define QDMA_ETH_TXMSG_HWF_MASK BIT(14) +#define QDMA_ETH_TXMSG_HOP_MASK BIT(13) +#define QDMA_ETH_TXMSG_PTP_MASK BIT(12) +#define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */ +#define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */ + +/* RX MSG1 */ +#define QDMA_ETH_RXMSG_DEI_MASK BIT(31) +#define QDMA_ETH_RXMSG_IP6_MASK BIT(30) +#define QDMA_ETH_RXMSG_IP4_MASK BIT(29) +#define QDMA_ETH_RXMSG_IP4F_MASK BIT(28) +#define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27) +#define QDMA_ETH_RXMSG_L4F_MASK BIT(26) +#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21) +#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16) +#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0) + +struct airoha_qdma_desc { + __le32 rsv; + __le32 ctrl; + __le32 addr; + __le32 data; + __le32 msg0; + __le32 msg1; + __le32 msg2; + __le32 msg3; +}; + +struct airoha_qdma_fwd_desc { + __le32 addr; + __le32 ctrl0; + __le32 ctrl1; + __le32 ctrl2; + __le32 msg0; + __le32 msg1; + __le32 rsv0; + __le32 rsv1; +}; + +struct airoha_queue { + struct airoha_qdma_desc *desc; + u16 head; + + int ndesc; +}; + +struct airoha_tx_irq_queue { + struct airoha_qdma *qdma; + + int size; + u32 *q; +}; + +struct airoha_qdma { + struct airoha_eth *eth; + void __iomem *regs; + + struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; + + struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; + struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; + + /* descriptor and packet buffers for qdma hw forward */ + struct { + void *desc; + void *q; + } hfwd; +}; + +struct airoha_gdm_port { + struct airoha_qdma *qdma; + int id; +}; + +struct airoha_eth { + void __iomem *fe_regs; + void __iomem *switch_regs; + + struct reset_ctl_bulk rsts; + struct reset_ctl_bulk xsi_rsts; + + struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; + struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; +}; + +static u32 airoha_rr(void __iomem *base, u32 offset) +{ + return readl(base + offset); +} + +static void airoha_wr(void __iomem *base, u32 offset, u32 val) +{ + writel(val, base + offset); +} + +static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) +{ + val |= (airoha_rr(base, offset) & ~mask); + airoha_wr(base, offset, val); + + return val; +} + +#define airoha_fe_rr(eth, offset) \ + airoha_rr((eth)->fe_regs, (offset)) +#define airoha_fe_wr(eth, offset, val) \ + airoha_wr((eth)->fe_regs, (offset), (val)) +#define airoha_fe_rmw(eth, offset, mask, val) \ + airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) +#define airoha_fe_set(eth, offset, val) \ + airoha_rmw((eth)->fe_regs, (offset), 0, (val)) +#define airoha_fe_clear(eth, offset, val) \ + airoha_rmw((eth)->fe_regs, (offset), (val), 0) + +#define airoha_qdma_rr(qdma, offset) \ + airoha_rr((qdma)->regs, (offset)) +#define airoha_qdma_wr(qdma, offset, val) \ + airoha_wr((qdma)->regs, (offset), (val)) +#define airoha_qdma_rmw(qdma, offset, mask, val) \ + airoha_rmw((qdma)->regs, (offset), (mask), (val)) +#define airoha_qdma_set(qdma, offset, val) \ + airoha_rmw((qdma)->regs, (offset), 0, (val)) +#define airoha_qdma_clear(qdma, offset, val) \ + airoha_rmw((qdma)->regs, (offset), (val), 0) + +#define airoha_switch_wr(eth, offset, val) \ + airoha_wr((eth)->switch_regs, (offset), (val)) + +static void airoha_fe_maccr_init(struct airoha_eth *eth) +{ + int p; + + for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) { + /* Disable any kind of CRC drop or offload */ + airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), 0); + } +} + +static int airoha_fe_init(struct airoha_eth *eth) +{ + airoha_fe_maccr_init(eth); + + return 0; +} + +static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index, + uchar *rx_packet) +{ + struct airoha_qdma_desc *desc; + u32 val; + + desc = &q->desc[index]; + index = (index + 1) % q->ndesc; + + dma_map_single(rx_packet, PKTSIZE_ALIGN, DMA_TO_DEVICE); + + WRITE_ONCE(desc->msg0, cpu_to_le32(0)); + WRITE_ONCE(desc->msg1, cpu_to_le32(0)); + WRITE_ONCE(desc->msg2, cpu_to_le32(0)); + WRITE_ONCE(desc->msg3, cpu_to_le32(0)); + WRITE_ONCE(desc->addr, cpu_to_le32(virt_to_phys(rx_packet))); + WRITE_ONCE(desc->data, cpu_to_le32(index)); + val = FIELD_PREP(QDMA_DESC_LEN_MASK, PKTSIZE_ALIGN); + WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); + + dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE); +} + +static void airoha_qdma_init_rx_desc(struct airoha_queue *q) +{ + int i; + + for (i = 0; i < q->ndesc; i++) + airoha_qdma_reset_rx_desc(q, i, net_rx_packets[i]); +} + +static int airoha_qdma_init_rx_queue(struct airoha_queue *q, + struct airoha_qdma *qdma, int ndesc) +{ + int qid = q - &qdma->q_rx[0]; + unsigned long dma_addr; + + q->ndesc = ndesc; + q->head = 0; + + q->desc = dma_alloc_coherent(q->ndesc * sizeof(*q->desc), &dma_addr); + if (!q->desc) + return -ENOMEM; + + memset(q->desc, 0, q->ndesc * sizeof(*q->desc)); + dma_map_single(q->desc, q->ndesc * sizeof(*q->desc), DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); + airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), + RX_RING_SIZE_MASK, + FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); + + airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, + FIELD_PREP(RX_RING_THR_MASK, 0)); + airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, + FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 1)); + airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, + FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); + + return 0; +} + +static int airoha_qdma_init_rx(struct airoha_qdma *qdma) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { + int err; + + err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, + RX_DSCP_NUM); + if (err) + return err; + } + + return 0; +} + +static int airoha_qdma_init_tx_queue(struct airoha_queue *q, + struct airoha_qdma *qdma, int size) +{ + int qid = q - &qdma->q_tx[0]; + unsigned long dma_addr; + + q->ndesc = size; + q->head = 0; + + q->desc = dma_alloc_coherent(q->ndesc * sizeof(*q->desc), &dma_addr); + if (!q->desc) + return -ENOMEM; + + memset(q->desc, 0, q->ndesc * sizeof(*q->desc)); + dma_map_single(q->desc, q->ndesc * sizeof(*q->desc), DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); + airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, + FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); + airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, + FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head)); + + return 0; +} + +static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, + struct airoha_qdma *qdma, int size) +{ + int id = irq_q - &qdma->q_tx_irq[0]; + unsigned long dma_addr; + + irq_q->q = dma_alloc_coherent(size * sizeof(u32), &dma_addr); + if (!irq_q->q) + return -ENOMEM; + + memset(irq_q->q, 0xffffffff, size * sizeof(u32)); + irq_q->size = size; + irq_q->qdma = qdma; + + dma_map_single(irq_q->q, size * sizeof(u32), DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); + airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, + FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); + + return 0; +} + +static int airoha_qdma_init_tx(struct airoha_qdma *qdma) +{ + int i, err; + + for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { + err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, + IRQ_QUEUE_LEN); + if (err) + return err; + } + + for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { + err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, + TX_DSCP_NUM); + if (err) + return err; + } + + return 0; +} + +static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) +{ + unsigned long dma_addr; + u32 status; + int size; + + size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc); + qdma->hfwd.desc = dma_alloc_coherent(size, &dma_addr); + if (!qdma->hfwd.desc) + return -ENOMEM; + + memset(qdma->hfwd.desc, 0, size); + dma_map_single(qdma->hfwd.desc, size, DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); + + size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM; + qdma->hfwd.q = dma_alloc_coherent(size, &dma_addr); + if (!qdma->hfwd.q) + return -ENOMEM; + + memset(qdma->hfwd.q, 0, size); + dma_map_single(qdma->hfwd.q, size, DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); + + airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, + HW_FWD_DSCP_PAYLOAD_SIZE_MASK | + HW_FWD_DSCP_MIN_SCATTER_LEN_MASK, + FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0) | + FIELD_PREP(HW_FWD_DSCP_MIN_SCATTER_LEN_MASK, 1)); + airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, + LMGR_INIT_START | LMGR_SRAM_MODE_MASK | + HW_FWD_DESC_NUM_MASK, + FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) | + LMGR_INIT_START); + + udelay(1000); + return read_poll_timeout(airoha_qdma_rr, status, + !(status & LMGR_INIT_START), USEC_PER_MSEC, + 30 * USEC_PER_MSEC, qdma, + REG_LMGR_INIT_CFG); +} + +static int airoha_qdma_hw_init(struct airoha_qdma *qdma) +{ + int i; + + /* clear pending irqs */ + for (i = 0; i < 2; i++) + airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); + + airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, + GLOBAL_CFG_CPU_TXR_RR_MASK | + GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | + GLOBAL_CFG_IRQ0_EN_MASK | + GLOBAL_CFG_TX_WB_DONE_MASK | + FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 3)); + + /* disable qdma rx delay interrupt */ + for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { + if (!qdma->q_rx[i].ndesc) + continue; + + airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), + RX_DELAY_INT_MASK); + } + + return 0; +} + +static int airoha_qdma_init(struct udevice *dev, + struct airoha_eth *eth, + struct airoha_qdma *qdma) +{ + int err; + + qdma->eth = eth; + qdma->regs = dev_remap_addr_name(dev, "qdma0"); + if (IS_ERR(qdma->regs)) + return PTR_ERR(qdma->regs); + + err = airoha_qdma_init_rx(qdma); + if (err) + return err; + + err = airoha_qdma_init_tx(qdma); + if (err) + return err; + + err = airoha_qdma_init_hfwd_queues(qdma); + if (err) + return err; + + return airoha_qdma_hw_init(qdma); +} + +static int airoha_hw_init(struct udevice *dev, + struct airoha_eth *eth) +{ + int ret, i; + + /* disable xsi */ + ret = reset_assert_bulk(ð->xsi_rsts); + if (ret) + return ret; + + ret = reset_assert_bulk(ð->rsts); + if (ret) + return ret; + + mdelay(20); + + ret = reset_deassert_bulk(ð->rsts); + if (ret) + return ret; + + mdelay(20); + + ret = airoha_fe_init(eth); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { + ret = airoha_qdma_init(dev, eth, ð->qdma[i]); + if (ret) + return ret; + } + + return 0; +} + +static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth) +{ + ofnode switch_node; + fdt_addr_t addr; + + switch_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-switch"); + if (!ofnode_valid(switch_node)) + return -EINVAL; + + addr = ofnode_get_addr(switch_node); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + /* Switch doesn't have a DEV, gets address and setup Flood and CPU port */ + eth->switch_regs = map_sysmem(addr, 0); + + /* Set FLOOD, no CPU switch register */ + airoha_switch_wr(eth, SWITCH_MFC, SWITCH_BC_FFP | SWITCH_UNM_FFP | + SWITCH_UNU_FFP); + + /* Set CPU 6 PMCR */ + airoha_switch_wr(eth, SWITCH_PMCR(6), + SWITCH_IPG_CFG_SHORT | SWITCH_MAC_MODE | + SWITCH_FORCE_MODE | SWITCH_MAC_TX_EN | + SWITCH_MAC_RX_EN | SWITCH_BKOFF_EN | SWITCH_BKPR_EN | + SWITCH_FORCE_RX_FC | SWITCH_FORCE_TX_FC | + SWITCH_FORCE_SPD_1000 | SWITCH_FORCE_DPX | + SWITCH_FORCE_LNK); + + /* Sideband signal error for Port 3, which need the auto polling */ + airoha_switch_wr(eth, SWITCH_PHY_POLL, + FIELD_PREP(SWITCH_PHY_AP_EN, 0x7f) | + FIELD_PREP(SWITCH_EEE_POLL_EN, 0x7f) | + SWITCH_PHY_PRE_EN | + FIELD_PREP(SWITCH_PHY_END_ADDR, 0xc) | + FIELD_PREP(SWITCH_PHY_ST_ADDR, 0x8)); + + return 0; +} + +static int airoha_eth_probe(struct udevice *dev) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct regmap *scu_regmap; + ofnode scu_node; + int ret; + + scu_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu"); + if (!ofnode_valid(scu_node)) + return -EINVAL; + + scu_regmap = syscon_node_to_regmap(scu_node); + if (IS_ERR(scu_regmap)) + return PTR_ERR(scu_regmap); + + /* It seems by default the FEMEM_SEL is set to Memory (0x1) + * preventing any access to any QDMA and FrameEngine register + * reporting all 0xdeadbeef (poor cow :( ) + */ + regmap_write(scu_regmap, SCU_SHARE_FEMEM_SEL, 0x0); + + eth->fe_regs = dev_remap_addr_name(dev, "fe"); + if (!eth->fe_regs) + return -ENOMEM; + + eth->rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_RSTS, + sizeof(struct reset_ctl), GFP_KERNEL); + if (!eth->rsts.resets) + return -ENOMEM; + eth->rsts.count = AIROHA_MAX_NUM_RSTS; + + eth->xsi_rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_XSI_RSTS, + sizeof(struct reset_ctl), GFP_KERNEL); + if (!eth->xsi_rsts.resets) + return -ENOMEM; + eth->xsi_rsts.count = AIROHA_MAX_NUM_XSI_RSTS; + + ret = reset_get_by_name(dev, "fe", ð->rsts.resets[0]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "pdma", ð->rsts.resets[1]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "qdma", ð->rsts.resets[2]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "hsi0-mac", ð->xsi_rsts.resets[0]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "hsi1-mac", ð->xsi_rsts.resets[1]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "hsi-mac", ð->xsi_rsts.resets[2]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "xfp-mac", ð->xsi_rsts.resets[3]); + if (ret) + return ret; + + ret = airoha_hw_init(dev, eth); + if (ret) + return ret; + + return airoha_switch_init(dev, eth); +} + +static int airoha_eth_init(struct udevice *dev) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_queue *q; + int qid; + + qid = 0; + q = &qdma->q_rx[qid]; + + airoha_qdma_init_rx_desc(q); + + airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, + GLOBAL_CFG_TX_DMA_EN_MASK | + GLOBAL_CFG_RX_DMA_EN_MASK); + + return 0; +} + +static void airoha_eth_stop(struct udevice *dev) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + + airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, + GLOBAL_CFG_TX_DMA_EN_MASK | + GLOBAL_CFG_RX_DMA_EN_MASK); +} + +static int airoha_eth_send(struct udevice *dev, void *packet, int length) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_qdma_desc *desc; + struct airoha_queue *q; + dma_addr_t dma_addr; + u32 msg0, msg1; + int qid, index; + u8 fport; + u32 val; + int i; + + dma_addr = dma_map_single(packet, length, DMA_TO_DEVICE); + + qid = 0; + q = &qdma->q_tx[qid]; + desc = &q->desc[q->head]; + index = (q->head + 1) % q->ndesc; + + fport = 1; + + msg0 = 0; + msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | + FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); + + val = FIELD_PREP(QDMA_DESC_LEN_MASK, length); + WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); + WRITE_ONCE(desc->addr, cpu_to_le32(dma_addr)); + val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); + WRITE_ONCE(desc->data, cpu_to_le32(val)); + WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); + WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); + WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); + + dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE); + + airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, + FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); + + for (i = 0; i < 100; i++) { + dma_unmap_single(virt_to_phys(desc), sizeof(*desc), + DMA_FROM_DEVICE); + if (desc->ctrl & QDMA_DESC_DONE_MASK) + break; + + udelay(1); + } + + /* Return error if for some reason the descriptor never ACK */ + if (!(desc->ctrl & QDMA_DESC_DONE_MASK)) + return -EAGAIN; + + q->head = index; + airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(0), + IRQ_CLEAR_LEN_MASK, 1); + + return 0; +} + +static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_qdma_desc *desc; + struct airoha_queue *q; + u16 length; + int qid; + + qid = 0; + q = &qdma->q_rx[qid]; + desc = &q->desc[q->head]; + + dma_unmap_single(virt_to_phys(desc), sizeof(*desc), + DMA_FROM_DEVICE); + + if (!(desc->ctrl & QDMA_DESC_DONE_MASK)) + return -EAGAIN; + + length = FIELD_GET(QDMA_DESC_LEN_MASK, desc->ctrl); + dma_unmap_single(desc->addr, length, + DMA_FROM_DEVICE); + + *packetp = phys_to_virt(desc->addr); + + return length; +} + +static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_queue *q; + int qid; + + if (!packet) + return 0; + + qid = 0; + q = &qdma->q_rx[qid]; + + dma_map_single(packet, length, DMA_TO_DEVICE); + + airoha_qdma_reset_rx_desc(q, q->head, packet); + + airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, + FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); + q->head = (q->head + 1) % q->ndesc; + + return 0; +} + +static int arht_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct airoha_eth *eth = dev_get_priv(dev); + unsigned char *mac = pdata->enetaddr; + u32 macaddr_lsb, macaddr_msb; + + macaddr_lsb = FIELD_PREP(SMACCR0_MAC2, mac[2]) | + FIELD_PREP(SMACCR0_MAC3, mac[3]) | + FIELD_PREP(SMACCR0_MAC4, mac[4]) | + FIELD_PREP(SMACCR0_MAC5, mac[5]); + macaddr_msb = FIELD_PREP(SMACCR1_MAC1, mac[1]) | + FIELD_PREP(SMACCR1_MAC0, mac[0]); + + /* Set MAC for Switch */ + airoha_switch_wr(eth, SWITCH_SMACCR0, macaddr_lsb); + airoha_switch_wr(eth, SWITCH_SMACCR1, macaddr_msb); + + return 0; +} + +static const struct udevice_id airoha_eth_ids[] = { + { .compatible = "airoha,en7581-eth" }, +}; + +static const struct eth_ops airoha_eth_ops = { + .start = airoha_eth_init, + .stop = airoha_eth_stop, + .send = airoha_eth_send, + .recv = airoha_eth_recv, + .free_pkt = arht_eth_free_pkt, + .write_hwaddr = arht_eth_write_hwaddr, +}; + +U_BOOT_DRIVER(airoha_eth) = { + .name = "airoha-eth", + .id = UCLASS_ETH, + .of_match = airoha_eth_ids, + .probe = airoha_eth_probe, + .ops = &airoha_eth_ops, + .priv_auto = sizeof(struct airoha_eth), + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index b4ec3614696..0cfe09333f7 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1173,7 +1173,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) eqos->config->ops->eqos_inval_buffer(packet, length); - if ((eqos->rx_desc_idx & idx_mask) == idx_mask) { + if (eqos->started && (eqos->rx_desc_idx & idx_mask) == idx_mask) { for (idx = eqos->rx_desc_idx - idx_mask; idx <= eqos->rx_desc_idx; idx++) { @@ -1612,10 +1612,18 @@ static const struct udevice_id eqos_ids[] = { #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP) { + .compatible = "rockchip,rk3528-gmac", + .data = (ulong)&eqos_rockchip_config + }, + { .compatible = "rockchip,rk3568-gmac", .data = (ulong)&eqos_rockchip_config }, { + .compatible = "rockchip,rk3576-gmac", + .data = (ulong)&eqos_rockchip_config + }, + { .compatible = "rockchip,rk3588-gmac", .data = (ulong)&eqos_rockchip_config }, diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index f3a0f63003e..d646d3ebac8 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -50,6 +50,132 @@ struct rockchip_platform_data { (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) +#define RK3528_VO_GRF_GMAC_CON 0x0018 +#define RK3528_VPU_GRF_GMAC_CON5 0x0018 +#define RK3528_VPU_GRF_GMAC_CON6 0x001c + +#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) +#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) +#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) +#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) + +#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) +#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) + +#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) +#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) +#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) + +#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) +#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) + +#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) +#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) +#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) +#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) + +#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) +#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) +#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) + +#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) +#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) +#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) +#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) + +static int rk3528_set_to_rgmii(struct udevice *dev, + int tx_delay, int rx_delay) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_PHY_INTF_SEL_RGMII); + + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, + DELAY_ENABLE(RK3528, tx_delay, rx_delay)); + + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON6, + RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | + RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); + + return 0; +} + +static int rk3528_set_to_rmii(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + + if (data->id == 1) + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_PHY_INTF_SEL_RMII); + else + regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON, + RK3528_GMAC0_PHY_INTF_SEL_RMII | + RK3528_GMAC0_CLK_RMII_DIV2); + + return 0; +} + +static int rk3528_set_gmac_speed(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val, reg; + + switch (eqos->phy->speed) { + case SPEED_10: + if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) + val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 : + RK3528_GMAC0_CLK_RMII_DIV20; + else + val = RK3528_GMAC1_CLK_RGMII_DIV50; + break; + case SPEED_100: + if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) + val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 : + RK3528_GMAC0_CLK_RMII_DIV2; + else + val = RK3528_GMAC1_CLK_RGMII_DIV5; + break; + case SPEED_1000: + if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) + val = RK3528_GMAC1_CLK_RGMII_DIV1; + else + return -EINVAL; + break; + default: + return -EINVAL; + } + + reg = data->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 : + RK3528_VO_GRF_GMAC_CON; + regmap_write(data->grf, reg, val); + + return 0; +} + +static void rk3528_set_clock_selection(struct udevice *dev, bool enable) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val; + + if (data->id == 1) { + val = data->clock_input ? RK3528_GMAC1_CLK_SELECT_IO : + RK3528_GMAC1_CLK_SELECT_CRU; + val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : + RK3528_GMAC1_CLK_RMII_GATE; + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, val); + } else { + val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : + RK3528_GMAC0_CLK_RMII_GATE; + regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON, val); + } +} + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -134,6 +260,145 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; } +/* VCCIO0_1_3_IOC */ +#define RK3576_VCCIO0_1_3_IOC_CON2 0x6408 +#define RK3576_VCCIO0_1_3_IOC_CON3 0x640c +#define RK3576_VCCIO0_1_3_IOC_CON4 0x6410 +#define RK3576_VCCIO0_1_3_IOC_CON5 0x6414 + +#define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) +#define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) +#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) +#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) + +#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) +#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) + +/* SDGMAC_GRF */ +#define RK3576_GRF_GMAC_CON0 0x0020 +#define RK3576_GRF_GMAC_CON1 0x0024 + +#define RK3576_GMAC_RMII_MODE GRF_BIT(3) +#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) + +#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) +#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) + +#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) +#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) + +#define RK3576_GMAC_CLK_RGMII_DIV1 \ + (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) +#define RK3576_GMAC_CLK_RGMII_DIV5 \ + (GRF_BIT(6) | GRF_BIT(5)) +#define RK3576_GMAC_CLK_RGMII_DIV50 \ + (GRF_BIT(6) | GRF_CLR_BIT(5)) + +#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) +#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) + +static int rk3576_set_to_rgmii(struct udevice *dev, + int tx_delay, int rx_delay) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 offset_con; + + offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 : + RK3576_GRF_GMAC_CON0; + + regmap_write(data->grf, offset_con, RK3576_GMAC_RGMII_MODE); + + offset_con = data->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : + RK3576_VCCIO0_1_3_IOC_CON2; + + /* m0 && m1 delay enabled */ + regmap_write(data->php_grf, offset_con, + DELAY_ENABLE(RK3576, tx_delay, rx_delay)); + regmap_write(data->php_grf, offset_con + 0x4, + DELAY_ENABLE(RK3576, tx_delay, rx_delay)); + + /* m0 && m1 delay value */ + regmap_write(data->php_grf, offset_con, + RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | + RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); + regmap_write(data->php_grf, offset_con + 0x4, + RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | + RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); + + return 0; +} + +static int rk3576_set_to_rmii(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 offset_con; + + offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 : + RK3576_GRF_GMAC_CON0; + + regmap_write(data->grf, offset_con, RK3576_GMAC_RMII_MODE); + + return 0; +} + +static int rk3576_set_gmac_speed(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val = 0, offset_con; + + switch (eqos->phy->speed) { + case SPEED_10: + if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) + val = RK3576_GMAC_CLK_RMII_DIV20; + else + val = RK3576_GMAC_CLK_RGMII_DIV50; + break; + case SPEED_100: + if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) + val = RK3576_GMAC_CLK_RMII_DIV2; + else + val = RK3576_GMAC_CLK_RGMII_DIV5; + break; + case SPEED_1000: + if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) + val = RK3576_GMAC_CLK_RGMII_DIV1; + else + return -EINVAL; + break; + default: + return -EINVAL; + } + + offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 : + RK3576_GRF_GMAC_CON0; + + regmap_write(data->grf, offset_con, val); + + return 0; +} + +static void rk3576_set_clock_selection(struct udevice *dev, bool enable) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + + u32 val = data->clock_input ? RK3576_GMAC_CLK_SELECT_IO : + RK3576_GMAC_CLK_SELECT_CRU; + u32 offset_con; + + val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : + RK3576_GMAC_CLK_RMII_GATE; + + offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 : + RK3576_GRF_GMAC_CON0; + + regmap_write(data->grf, offset_con, val); +} + #define RK3588_DELAY_ENABLE(id, tx, rx) \ (((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \ ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id))) @@ -270,6 +535,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable) static const struct rk_gmac_ops rk_gmac_ops[] = { { + .compatible = "rockchip,rk3528-gmac", + .set_to_rgmii = rk3528_set_to_rgmii, + .set_to_rmii = rk3528_set_to_rmii, + .set_gmac_speed = rk3528_set_gmac_speed, + .set_clock_selection = rk3528_set_clock_selection, + .regs = { + 0xffbd0000, /* gmac0 */ + 0xffbe0000, /* gmac1 */ + 0x0, /* sentinel */ + }, + }, + { .compatible = "rockchip,rk3568-gmac", .set_to_rgmii = rk3568_set_to_rgmii, .set_to_rmii = rk3568_set_to_rmii, @@ -281,6 +558,18 @@ static const struct rk_gmac_ops rk_gmac_ops[] = { }, }, { + .compatible = "rockchip,rk3576-gmac", + .set_to_rgmii = rk3576_set_to_rgmii, + .set_to_rmii = rk3576_set_to_rmii, + .set_gmac_speed = rk3576_set_gmac_speed, + .set_clock_selection = rk3576_set_clock_selection, + .regs = { + 0x2a220000, /* gmac0 */ + 0x2a230000, /* gmac1 */ + 0x0, /* sentinel */ + }, + }, + { .compatible = "rockchip,rk3588-gmac", .set_to_rgmii = rk3588_set_to_rgmii, .set_to_rmii = rk3588_set_to_rmii, @@ -357,7 +646,8 @@ static int eqos_probe_resources_rk(struct udevice *dev) goto err_free; } - if (device_is_compatible(dev, "rockchip,rk3588-gmac")) { + if (device_is_compatible(dev, "rockchip,rk3588-gmac") || + device_is_compatible(dev, "rockchip,rk3576-gmac")) { data->php_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf"); if (IS_ERR(data->php_grf)) { diff --git a/drivers/net/sandbox-lwip.c b/drivers/net/sandbox-lwip.c deleted file mode 100644 index 3721033c310..00000000000 --- a/drivers/net/sandbox-lwip.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 National Instruments - * - * (C) Copyright 2015 - * Joe Hershberger <joe.hershberger@ni.com> - */ - -#include <dm.h> -#include <log.h> -#include <malloc.h> -#include <net.h> -#include <asm/eth.h> -#include <asm/global_data.h> -#include <asm/test.h> - -DECLARE_GLOBAL_DATA_PTR; - -static int sb_lwip_eth_start(struct udevice *dev) -{ - debug("eth_sandbox_lwip: Start\n"); - - return 0; -} - -static int sb_lwip_eth_send(struct udevice *dev, void *packet, int length) -{ - debug("eth_sandbox_lwip: Send packet %d\n", length); - - return -ENOTSUPP; -} - -static int sb_lwip_eth_recv(struct udevice *dev, int flags, uchar **packetp) -{ - return -EAGAIN; -} - -static int sb_lwip_eth_free_pkt(struct udevice *dev, uchar *packet, int length) -{ - return 0; -} - -static void sb_lwip_eth_stop(struct udevice *dev) -{ -} - -static int sb_lwip_eth_write_hwaddr(struct udevice *dev) -{ - return 0; -} - -static const struct eth_ops sb_eth_ops = { - .start = sb_lwip_eth_start, - .send = sb_lwip_eth_send, - .recv = sb_lwip_eth_recv, - .free_pkt = sb_lwip_eth_free_pkt, - .stop = sb_lwip_eth_stop, - .write_hwaddr = sb_lwip_eth_write_hwaddr, -}; - -static int sb_lwip_eth_remove(struct udevice *dev) -{ - return 0; -} - -static int sb_lwip_eth_of_to_plat(struct udevice *dev) -{ - return 0; -} - -static const struct udevice_id sb_eth_ids[] = { - { .compatible = "sandbox,eth" }, - { } -}; - -U_BOOT_DRIVER(eth_sandbox) = { - .name = "eth_lwip_sandbox", - .id = UCLASS_ETH, - .of_match = sb_eth_ids, - .of_to_plat = sb_lwip_eth_of_to_plat, - .remove = sb_lwip_eth_remove, - .ops = &sb_eth_ops, - .priv_auto = 0, - .plat_auto = sizeof(struct eth_pdata), -}; diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index fe3627db6e3..2011fd31f41 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -9,13 +9,84 @@ #include <dm.h> #include <log.h> #include <malloc.h> -#include <net.h> #include <asm/eth.h> #include <asm/global_data.h> #include <asm/test.h> +#include <asm/types.h> + +/* + * Structure definitions for network protocols. Since this file is used for + * both NET and NET_LWIP, and given that the two network stacks do have + * conflicting types (for instance struct icmp_hdr), it is on purpose that the + * structures are defined locally with minimal dependencies -- <asm/types.h> is + * included for the bit types and that's it. + */ + +#define ETHADDR_LEN 6 +#define IP4_LEN 4 + +struct ethhdr { + u8 dst[ETHADDR_LEN]; + u8 src[ETHADDR_LEN]; + u16 protlen; +} __attribute__((packed)); + +#define ETHHDR_SIZE (sizeof(struct ethhdr)) + +struct arphdr { + u16 htype; + u16 ptype; + u8 hlen; + u8 plen; + u16 op; +} __attribute__((packed)); + +#define ARPHDR_SIZE (sizeof(struct arphdr)) + +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +struct arpdata { + u8 sha[ETHADDR_LEN]; + u32 spa; + u8 tha[ETHADDR_LEN]; + u32 tpa; +} __attribute__((packed)); + +#define ARPDATA_SIZE (sizeof(struct arpdata)) + +struct iphdr { + u8 hl_v; + u8 tos; + u16 len; + u16 id; + u16 off; + u8 ttl; + u8 prot; + u16 sum; + u32 src; + u32 dst; +} __attribute__((packed)); + +#define IPHDR_SIZE (sizeof(struct iphdr)) + +struct icmphdr { + u8 type; + u8 code; + u16 checksum; + u16 id; + u16 sequence; +} __attribute__((packed)); + +#define ICMPHDR_SIZE (sizeof(struct icmphdr)) + +#define ICMP_ECHO_REQUEST 8 +#define ICMP_ECHO_REPLY 0 +#define IPPROTO_ICMP 1 DECLARE_GLOBAL_DATA_PTR; +static const u8 null_ethaddr[6]; static bool skip_timeout; /* @@ -59,17 +130,19 @@ int sandbox_eth_arp_req_to_reply(struct udevice *dev, void *packet, unsigned int len) { struct eth_sandbox_priv *priv = dev_get_priv(dev); - struct ethernet_hdr *eth = packet; - struct arp_hdr *arp; - struct ethernet_hdr *eth_recv; - struct arp_hdr *arp_recv; - - if (ntohs(eth->et_protlen) != PROT_ARP) + struct ethhdr *eth = packet; + struct arphdr *arp; + struct arpdata *arpd; + struct ethhdr *eth_recv; + struct arphdr *arp_recv; + struct arpdata *arp_recvd; + + if (ntohs(eth->protlen) != PROT_ARP) return -EAGAIN; - arp = packet + ETHER_HDR_SIZE; + arp = packet + ETHHDR_SIZE; - if (ntohs(arp->ar_op) != ARPOP_REQUEST) + if (ntohs(arp->op) != ARP_REQUEST) return -EAGAIN; /* Don't allow the buffer to overrun */ @@ -77,27 +150,29 @@ int sandbox_eth_arp_req_to_reply(struct udevice *dev, void *packet, return 0; /* store this as the assumed IP of the fake host */ - priv->fake_host_ipaddr = net_read_ip(&arp->ar_tpa); + arpd = (struct arpdata *)(arp + 1); + priv->fake_host_ipaddr.s_addr = arpd->tpa; /* Formulate a fake response */ eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets]; - memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN); - memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN); - eth_recv->et_protlen = htons(PROT_ARP); - - arp_recv = (void *)eth_recv + ETHER_HDR_SIZE; - arp_recv->ar_hrd = htons(ARP_ETHER); - arp_recv->ar_pro = htons(PROT_IP); - arp_recv->ar_hln = ARP_HLEN; - arp_recv->ar_pln = ARP_PLEN; - arp_recv->ar_op = htons(ARPOP_REPLY); - memcpy(&arp_recv->ar_sha, priv->fake_host_hwaddr, ARP_HLEN); - net_write_ip(&arp_recv->ar_spa, priv->fake_host_ipaddr); - memcpy(&arp_recv->ar_tha, &arp->ar_sha, ARP_HLEN); - net_copy_ip(&arp_recv->ar_tpa, &arp->ar_spa); - - priv->recv_packet_length[priv->recv_packets] = - ETHER_HDR_SIZE + ARP_HDR_SIZE; + memcpy(eth_recv->dst, eth->src, ETHADDR_LEN); + memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN); + eth_recv->protlen = htons(PROT_ARP); + + arp_recv = (void *)eth_recv + ETHHDR_SIZE; + arp_recv->htype = htons(ARP_ETHER); + arp_recv->ptype = htons(PROT_IP); + arp_recv->hlen = ETHADDR_LEN; + arp_recv->plen = IP4_LEN; + arp_recv->op = htons(ARP_REPLY); + arp_recvd = (struct arpdata *)(arp_recv + 1); + memcpy(&arp_recvd->sha, priv->fake_host_hwaddr, ETHADDR_LEN); + arp_recvd->spa = priv->fake_host_ipaddr.s_addr; + memcpy(&arp_recvd->tha, &arpd->sha, ETHADDR_LEN); + arp_recvd->tpa = arpd->spa; + + priv->recv_packet_length[priv->recv_packets] = ETHHDR_SIZE + + ARPHDR_SIZE + ARPDATA_SIZE; ++priv->recv_packets; return 0; @@ -114,22 +189,22 @@ int sandbox_eth_ping_req_to_reply(struct udevice *dev, void *packet, unsigned int len) { struct eth_sandbox_priv *priv = dev_get_priv(dev); - struct ethernet_hdr *eth = packet; - struct ip_udp_hdr *ip; - struct icmp_hdr *icmp; - struct ethernet_hdr *eth_recv; - struct ip_udp_hdr *ipr; - struct icmp_hdr *icmpr; - - if (ntohs(eth->et_protlen) != PROT_IP) + struct ethhdr *eth = packet; + struct iphdr *ip; + struct icmphdr *icmp; + struct ethhdr *eth_recv; + struct iphdr *ipr; + struct icmphdr *icmpr; + + if (ntohs(eth->protlen) != PROT_IP) return -EAGAIN; - ip = packet + ETHER_HDR_SIZE; + ip = packet + ETHHDR_SIZE; - if (ip->ip_p != IPPROTO_ICMP) + if (ip->prot != IPPROTO_ICMP) return -EAGAIN; - icmp = (struct icmp_hdr *)&ip->udp_src; + icmp = (struct icmphdr *)(ip + 1); if (icmp->type != ICMP_ECHO_REQUEST) return -EAGAIN; @@ -141,19 +216,19 @@ int sandbox_eth_ping_req_to_reply(struct udevice *dev, void *packet, /* reply to the ping */ eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets]; memcpy(eth_recv, packet, len); - ipr = (void *)eth_recv + ETHER_HDR_SIZE; - icmpr = (struct icmp_hdr *)&ipr->udp_src; - memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN); - memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN); - ipr->ip_sum = 0; - ipr->ip_off = 0; - net_copy_ip((void *)&ipr->ip_dst, &ip->ip_src); - net_write_ip((void *)&ipr->ip_src, priv->fake_host_ipaddr); - ipr->ip_sum = compute_ip_checksum(ipr, IP_HDR_SIZE); + ipr = (void *)eth_recv + ETHHDR_SIZE; + icmpr = (struct icmphdr *)(ipr + 1); + memcpy(eth_recv->dst, eth->src, ETHADDR_LEN); + memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN); + ipr->sum = 0; + ipr->off = 0; + ipr->dst = ip->src; + ipr->src = priv->fake_host_ipaddr.s_addr; + ipr->sum = compute_ip_checksum(ipr, IPHDR_SIZE); icmpr->type = ICMP_ECHO_REPLY; icmpr->checksum = 0; - icmpr->checksum = compute_ip_checksum(icmpr, ICMP_HDR_SIZE); + icmpr->checksum = compute_ip_checksum(icmpr, ICMPHDR_SIZE); priv->recv_packet_length[priv->recv_packets] = len; ++priv->recv_packets; @@ -171,8 +246,9 @@ int sandbox_eth_ping_req_to_reply(struct udevice *dev, void *packet, int sandbox_eth_recv_arp_req(struct udevice *dev) { struct eth_sandbox_priv *priv = dev_get_priv(dev); - struct ethernet_hdr *eth_recv; - struct arp_hdr *arp_recv; + struct ethhdr *eth_recv; + struct arphdr *arp_recv; + struct arpdata *arp_recvd; /* Don't allow the buffer to overrun */ if (priv->recv_packets >= PKTBUFSRX) @@ -180,23 +256,24 @@ int sandbox_eth_recv_arp_req(struct udevice *dev) /* Formulate a fake request */ eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets]; - memcpy(eth_recv->et_dest, net_bcast_ethaddr, ARP_HLEN); - memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN); - eth_recv->et_protlen = htons(PROT_ARP); - - arp_recv = (void *)eth_recv + ETHER_HDR_SIZE; - arp_recv->ar_hrd = htons(ARP_ETHER); - arp_recv->ar_pro = htons(PROT_IP); - arp_recv->ar_hln = ARP_HLEN; - arp_recv->ar_pln = ARP_PLEN; - arp_recv->ar_op = htons(ARPOP_REQUEST); - memcpy(&arp_recv->ar_sha, priv->fake_host_hwaddr, ARP_HLEN); - net_write_ip(&arp_recv->ar_spa, priv->fake_host_ipaddr); - memcpy(&arp_recv->ar_tha, net_null_ethaddr, ARP_HLEN); - net_write_ip(&arp_recv->ar_tpa, net_ip); + memcpy(eth_recv->dst, net_bcast_ethaddr, ETHADDR_LEN); + memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN); + eth_recv->protlen = htons(PROT_ARP); + + arp_recv = (void *)eth_recv + ETHHDR_SIZE; + arp_recv->htype = htons(ARP_ETHER); + arp_recv->ptype = htons(PROT_IP); + arp_recv->hlen = ETHADDR_LEN; + arp_recv->plen = IP4_LEN; + arp_recv->op = htons(ARP_REQUEST); + arp_recvd = (struct arpdata *)(arp_recv + 1); + memcpy(&arp_recvd->sha, priv->fake_host_hwaddr, ETHADDR_LEN); + arp_recvd->spa = priv->fake_host_ipaddr.s_addr; + memcpy(&arp_recvd->tha, null_ethaddr, ETHADDR_LEN); + arp_recvd->tpa = net_ip.s_addr; priv->recv_packet_length[priv->recv_packets] = - ETHER_HDR_SIZE + ARP_HDR_SIZE; + ETHHDR_SIZE + ARPHDR_SIZE + ARPDATA_SIZE; ++priv->recv_packets; return 0; @@ -212,9 +289,10 @@ int sandbox_eth_recv_arp_req(struct udevice *dev) int sandbox_eth_recv_ping_req(struct udevice *dev) { struct eth_sandbox_priv *priv = dev_get_priv(dev); - struct ethernet_hdr *eth_recv; - struct ip_udp_hdr *ipr; - struct icmp_hdr *icmpr; + struct eth_pdata *pdata = dev_get_plat(dev); + struct ethhdr *eth_recv; + struct iphdr *ipr; + struct icmphdr *icmpr; /* Don't allow the buffer to overrun */ if (priv->recv_packets >= PKTBUFSRX) @@ -223,31 +301,31 @@ int sandbox_eth_recv_ping_req(struct udevice *dev) /* Formulate a fake ping */ eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets]; - memcpy(eth_recv->et_dest, net_ethaddr, ARP_HLEN); - memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN); - eth_recv->et_protlen = htons(PROT_IP); + memcpy(eth_recv->dst, pdata->enetaddr, ETHADDR_LEN); + memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN); + eth_recv->protlen = htons(PROT_IP); - ipr = (void *)eth_recv + ETHER_HDR_SIZE; - ipr->ip_hl_v = 0x45; - ipr->ip_len = htons(IP_ICMP_HDR_SIZE); - ipr->ip_off = htons(IP_FLAGS_DFRAG); - ipr->ip_p = IPPROTO_ICMP; - ipr->ip_sum = 0; - net_write_ip(&ipr->ip_src, priv->fake_host_ipaddr); - net_write_ip(&ipr->ip_dst, net_ip); - ipr->ip_sum = compute_ip_checksum(ipr, IP_HDR_SIZE); + ipr = (void *)eth_recv + ETHHDR_SIZE; + ipr->hl_v = 0x45; + ipr->len = htons(IPHDR_SIZE + ICMPHDR_SIZE); + ipr->off = htons(IP_FLAGS_DFRAG); + ipr->prot = IPPROTO_ICMP; + ipr->sum = 0; + ipr->src = priv->fake_host_ipaddr.s_addr; + ipr->dst = net_ip.s_addr; + ipr->sum = compute_ip_checksum(ipr, IPHDR_SIZE); - icmpr = (struct icmp_hdr *)&ipr->udp_src; + icmpr = (struct icmphdr *)(ipr + 1); icmpr->type = ICMP_ECHO_REQUEST; icmpr->code = 0; icmpr->checksum = 0; - icmpr->un.echo.id = 0; - icmpr->un.echo.sequence = htons(1); - icmpr->checksum = compute_ip_checksum(icmpr, ICMP_HDR_SIZE); + icmpr->id = 0; + icmpr->sequence = htons(1); + icmpr->checksum = compute_ip_checksum(icmpr, ICMPHDR_SIZE); priv->recv_packet_length[priv->recv_packets] = - ETHER_HDR_SIZE + IP_ICMP_HDR_SIZE; + ETHHDR_SIZE + IPHDR_SIZE + ICMPHDR_SIZE; ++priv->recv_packets; return 0; @@ -398,7 +476,7 @@ static int sb_eth_write_hwaddr(struct udevice *dev) debug("eth_sandbox %s: Write HW ADDR - %pM\n", dev->name, pdata->enetaddr); - memcpy(priv->fake_host_hwaddr, pdata->enetaddr, ARP_HLEN); + memcpy(priv->fake_host_hwaddr, pdata->enetaddr, ETHADDR_LEN); return 0; } diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 4f876d39875..409049137cc 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -67,6 +67,7 @@ config PCI_CONFIG_HOST_BRIDGE config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" depends on MIPS + default y if !ARCH_MAP_SYSMEM help Say Y if base address of system memory is being used as a virtual address instead of a physical address (e.g. on MIPS). The PCI core will then remap @@ -75,6 +76,15 @@ config PCI_MAP_SYSTEM_MEMORY This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still being used as virtual address. +config PCI_BRIDGE_MEM_ALIGNMENT + hex "Alignment boundary of PCI memory resource allocation" + default 0x10000 if TARGET_BOSTON + default 0x100000 + help + Specify a boundary for alignment of PCI memory resource allocation, + this is normally 0x100000 (1MB) but can be reduced to accommodate + hardware with tight bridge range if hardware allows. + config PCI_SRIOV bool "Enable Single Root I/O Virtualization support for PCI" help diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index e68e31a8227..4a1c782be36 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -373,8 +373,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_mem, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); /* * Set up memory and I/O filter limits, assume 32-bit @@ -388,8 +388,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) } if (pci_prefetch) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_prefetch, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); /* * Set up memory and I/O filter limits, assume 32-bit @@ -466,8 +466,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr)); if (pci_mem) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_mem, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, ((pci_mem->bus_lower - 1) >> 16) & @@ -481,8 +481,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_prefetch, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, (((pci_prefetch->bus_lower - 1) >> 16) & diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index a674ab04bee..63058e8e7c5 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -18,14 +18,19 @@ */ struct xilinx_pcie { void *cfg_base; + pci_size_t size; + int first_busno; }; /* Register definitions */ -#define XILINX_PCIE_REG_PSCR 0x144 -#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) -#define XILINX_PCIE_REG_RPSC 0x148 -#define XILINX_PCIE_REG_RPSC_BEN BIT(0) - +#define XILINX_PCIE_REG_BRIDGE_INFO 0x130 +#define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_SHIFT 16 +#define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_MASK (0x7 << 16) +#define XILINX_PCIE_REG_INT_MASK 0x13c +#define XILINX_PCIE_REG_PSCR 0x144 +#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) +#define XILINX_PCIE_REG_RPSC 0x148 +#define XILINX_PCIE_REG_RPSC_BEN BIT(0) /** * pcie_xilinx_link_up() - Check whether the PCIe link is up * @pcie: Pointer to the PCI controller state @@ -61,14 +66,18 @@ static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf, uint offset, void **paddress) { struct xilinx_pcie *pcie = dev_get_priv(udev); - unsigned int bus = PCI_BUS(bdf); + unsigned int bus = PCI_BUS(bdf) - pcie->first_busno; unsigned int dev = PCI_DEV(bdf); unsigned int func = PCI_FUNC(bdf); + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); void *addr; if ((bus > 0) && !pcie_xilinx_link_up(pcie)) return -ENODEV; + if (bus > num_buses) + return -ENODEV; + /* * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are * limited to a single device each. @@ -142,20 +151,37 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev) struct xilinx_pcie *pcie = dev_get_priv(dev); fdt_addr_t addr; fdt_size_t size; - u32 rpsc; addr = dev_read_addr_size(dev, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; - pcie->cfg_base = devm_ioremap(dev, addr, size); - if (IS_ERR(pcie->cfg_base)) - return PTR_ERR(pcie->cfg_base); + pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE); + if (!pcie->cfg_base) + return -ENOMEM; + pcie->size = size; + return 0; +} - /* Enable the Bridge enable bit */ - rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC); +static int pci_xilinx_probe(struct udevice *dev) +{ + struct xilinx_pcie *pcie = dev_get_priv(dev); + u32 rpsc; + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); + + pcie->first_busno = dev_seq(dev); + + /* Disable all interrupts */ + writel(0, pcie->cfg_base + XILINX_PCIE_REG_INT_MASK); + + /* Enable the bridge */ + rpsc = readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC); rpsc |= XILINX_PCIE_REG_RPSC_BEN; - __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC); + writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC); + + /* Enable access to all possible subordinate buses */ + writel((0 << 0) | (1 << 8) | (num_buses << 16), + pcie->cfg_base + PCI_PRIMARY_BUS); return 0; } @@ -176,5 +202,6 @@ U_BOOT_DRIVER(pcie_xilinx) = { .of_match = pcie_xilinx_ids, .ops = &pcie_xilinx_ops, .of_to_plat = pcie_xilinx_of_to_plat, + .probe = pci_xilinx_probe, .priv_auto = sizeof(struct xilinx_pcie), }; diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 43f6e020a6a..88b33de1b2a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -40,11 +40,13 @@ struct rockchip_usb2phy_port_cfg { struct rockchip_usb2phy_cfg { unsigned int reg; struct usb2phy_reg clkout_ctl; + struct usb2phy_reg clkout_ctl_phy; const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; }; struct rockchip_usb2phy { struct regmap *reg_base; + struct regmap *phy_base; struct clk phyclk; const struct rockchip_usb2phy_cfg *phy_cfg; }; @@ -165,6 +167,22 @@ static struct phy_ops rockchip_usb2phy_ops = { .of_xlate = rockchip_usb2phy_of_xlate, }; +static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, + const struct usb2phy_reg **clkout_ctl) +{ + struct udevice *parent = dev_get_parent(clk->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; + + if (priv->phy_cfg->clkout_ctl_phy.enable) { + *base = priv->phy_base; + *clkout_ctl = &phy_cfg->clkout_ctl_phy; + } else { + *base = priv->reg_base; + *clkout_ctl = &phy_cfg->clkout_ctl; + } +} + /** * round_rate() - Adjust a rate to the exact rate a clock can provide. * @clk: The clock to manipulate. @@ -185,13 +203,14 @@ ulong rockchip_usb2phy_clk_round_rate(struct clk *clk, ulong rate) */ int rockchip_usb2phy_clk_enable(struct clk *clk) { - struct udevice *parent = dev_get_parent(clk->dev); - struct rockchip_usb2phy *priv = dev_get_priv(parent); - const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; + const struct usb2phy_reg *clkout_ctl; + struct regmap *base; + + rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); /* turn on 480m clk output if it is off */ - if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) { - property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true); + if (!property_enabled(base, clkout_ctl)) { + property_enable(base, clkout_ctl, true); /* waiting for the clk become stable */ usleep_range(1200, 1300); @@ -208,12 +227,13 @@ int rockchip_usb2phy_clk_enable(struct clk *clk) */ int rockchip_usb2phy_clk_disable(struct clk *clk) { - struct udevice *parent = dev_get_parent(clk->dev); - struct rockchip_usb2phy *priv = dev_get_priv(parent); - const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; + const struct usb2phy_reg *clkout_ctl; + struct regmap *base; + + rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); /* turn off 480m clk output */ - property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false); + property_enable(base, clkout_ctl, false); return 0; } @@ -281,7 +301,10 @@ static int rockchip_usb2phy_probe(struct udevice *dev) return ret; } - return 0; + if (priv->phy_cfg->clkout_ctl_phy.enable) + ret = regmap_init_mem_index(dev_ofnode(dev), &priv->phy_base, 0); + + return ret; } static int rockchip_usb2phy_bind(struct udevice *dev) @@ -389,6 +412,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { + { + .reg = 0xffdf0000, + .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x004c, 1, 0, 2, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x005c, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { .reg = 0xfe8a0000, @@ -471,6 +510,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .data = (ulong)&rk3399_usb2phy_cfgs, }, { + .compatible = "rockchip,rk3528-usb2phy", + .data = (ulong)&rk3528_phy_cfgs, + }, + { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs, }, diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index c91f650b043..e17415e1ca6 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -14,7 +14,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3528.c b/drivers/pinctrl/rockchip/pinctrl-rk3528.c new file mode 100644 index 00000000000..a3e1f0b2c9d --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3528.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" +#include <dt-bindings/pinctrl/rockchip.h> + +static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, mask; + u8 bit; + u32 data, rmask; + + regmap = priv->regmap_base; + reg = bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + + data = (mask << (bit + 16)); + rmask = data | (data >> 16); + data |= (mux & mask) << bit; + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3528_DRV_BITS_PER_PIN 8 +#define RK3528_DRV_PINS_PER_REG 2 +#define RK3528_DRV_GPIO0_OFFSET 0x100 +#define RK3528_DRV_GPIO1_OFFSET 0x20120 +#define RK3528_DRV_GPIO2_OFFSET 0x30160 +#define RK3528_DRV_GPIO3_OFFSET 0x20190 +#define RK3528_DRV_GPIO4_OFFSET 0x101C0 + +static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + + if (bank->bank_num == 0) { + *reg = RK3528_DRV_GPIO0_OFFSET; + } else if (bank->bank_num == 1) { + *reg = RK3528_DRV_GPIO1_OFFSET; + } else if (bank->bank_num == 2) { + *reg = RK3528_DRV_GPIO2_OFFSET; + } else if (bank->bank_num == 3) { + *reg = RK3528_DRV_GPIO3_OFFSET; + } else if (bank->bank_num == 4) { + *reg = RK3528_DRV_GPIO4_OFFSET; + } else { + *reg = 0; + debug("unsupported bank_num %d\n", bank->bank_num); + } + + *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_DRV_PINS_PER_REG; + *bit *= RK3528_DRV_BITS_PER_PIN; +} + +static int rk3528_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg; + u32 data, rmask; + u8 bit; + int drv = (1 << (strength + 1)) - 1; + + rk3528_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (drv << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3528_PULL_BITS_PER_PIN 2 +#define RK3528_PULL_PINS_PER_REG 8 +#define RK3528_PULL_GPIO0_OFFSET 0x200 +#define RK3528_PULL_GPIO1_OFFSET 0x20210 +#define RK3528_PULL_GPIO2_OFFSET 0x30220 +#define RK3528_PULL_GPIO3_OFFSET 0x20230 +#define RK3528_PULL_GPIO4_OFFSET 0x10240 + +static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + + if (bank->bank_num == 0) { + *reg = RK3528_PULL_GPIO0_OFFSET; + } else if (bank->bank_num == 1) { + *reg = RK3528_PULL_GPIO1_OFFSET; + } else if (bank->bank_num == 2) { + *reg = RK3528_PULL_GPIO2_OFFSET; + } else if (bank->bank_num == 3) { + *reg = RK3528_PULL_GPIO3_OFFSET; + } else if (bank->bank_num == 4) { + *reg = RK3528_PULL_GPIO4_OFFSET; + } else { + *reg = 0; + debug("unsupported bank_num %d\n", bank->bank_num); + } + + *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_PULL_PINS_PER_REG; + *bit *= RK3528_PULL_BITS_PER_PIN; +} + +static int rk3528_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data, rmask; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -EOPNOTSUPP; + + rk3528_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (ret << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3528_SMT_BITS_PER_PIN 1 +#define RK3528_SMT_PINS_PER_REG 8 +#define RK3528_SMT_GPIO0_OFFSET 0x400 +#define RK3528_SMT_GPIO1_OFFSET 0x20410 +#define RK3528_SMT_GPIO2_OFFSET 0x30420 +#define RK3528_SMT_GPIO3_OFFSET 0x20430 +#define RK3528_SMT_GPIO4_OFFSET 0x10440 + +static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + + if (bank->bank_num == 0) { + *reg = RK3528_SMT_GPIO0_OFFSET; + } else if (bank->bank_num == 1) { + *reg = RK3528_SMT_GPIO1_OFFSET; + } else if (bank->bank_num == 2) { + *reg = RK3528_SMT_GPIO2_OFFSET; + } else if (bank->bank_num == 3) { + *reg = RK3528_SMT_GPIO3_OFFSET; + } else if (bank->bank_num == 4) { + *reg = RK3528_SMT_GPIO4_OFFSET; + } else { + *reg = 0; + debug("unsupported bank_num %d\n", bank->bank_num); + } + + *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_SMT_PINS_PER_REG; + *bit *= RK3528_SMT_BITS_PER_PIN; + + return 0; +} + +static int rk3528_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u32 data, rmask; + u8 bit; + + rk3528_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (enable << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +static struct rockchip_pin_bank rk3528_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20020, 0x20028, 0x20030, 0x20038), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x30040, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20060, 0x20068, 0x20070, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10080, 0x10088, 0x10090, 0x10098), +}; + +static const struct rockchip_pin_ctrl rk3528_pin_ctrl = { + .pin_banks = rk3528_pin_banks, + .nr_banks = ARRAY_SIZE(rk3528_pin_banks), + .grf_mux_offset = 0x0, + .set_mux = rk3528_set_mux, + .set_pull = rk3528_set_pull, + .set_drive = rk3528_set_drive, + .set_schmitt = rk3528_set_schmitt, +}; + +static const struct udevice_id rk3528_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3528-pinctrl", + .data = (ulong)&rk3528_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = { + .name = "rockchip_rk3528_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3528_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3576.c b/drivers/pinctrl/rockchip/pinctrl-rk3576.c new file mode 100644 index 00000000000..66e1142ac1f --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3576.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd + */ + +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" +#include <dt-bindings/pinctrl/rockchip.h> + +static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, mask; + u8 bit; + u32 data, rmask; + + regmap = priv->regmap_base; + reg = bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + + data = (mask << (bit + 16)); + rmask = data | (data >> 16); + data |= (mux & mask) << bit; + + if (bank->bank_num == 0 && pin >= RK_PB4 && pin <= RK_PB7) + reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3576_DRV_BITS_PER_PIN 4 +#define RK3576_DRV_PINS_PER_REG 4 +#define RK3576_DRV_GPIO0_AL_OFFSET 0x10 +#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014 +#define RK3576_DRV_GPIO1_OFFSET 0x6020 +#define RK3576_DRV_GPIO2_OFFSET 0x6040 +#define RK3576_DRV_GPIO3_OFFSET 0x6060 +#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080 +#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090 +#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098 + +static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + if (bank->bank_num == 0 && pin_num < 12) { + *reg = RK3576_DRV_GPIO0_AL_OFFSET; + } else if (bank->bank_num == 0) { + *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; + } else if (bank->bank_num == 1) { + *reg = RK3576_DRV_GPIO1_OFFSET; + } else if (bank->bank_num == 2) { + *reg = RK3576_DRV_GPIO2_OFFSET; + } else if (bank->bank_num == 3) { + *reg = RK3576_DRV_GPIO3_OFFSET; + } else if (bank->bank_num == 4 && pin_num < 16) { + *reg = RK3576_DRV_GPIO4_AL_OFFSET; + } else if (bank->bank_num == 4 && pin_num < 24) { + *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; + } else if (bank->bank_num == 4) { + *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; + } else { + *reg = 0; + debug("unsupported bank_num %d\n", bank->bank_num); + } + + *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3576_DRV_PINS_PER_REG; + *bit *= RK3576_DRV_BITS_PER_PIN; +} + +static int rk3576_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg; + u32 data, rmask; + u8 bit; + int drv = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); + + rk3576_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3576_DRV_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (drv << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3576_PULL_BITS_PER_PIN 2 +#define RK3576_PULL_PINS_PER_REG 8 +#define RK3576_PULL_GPIO0_AL_OFFSET 0x20 +#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028 +#define RK3576_PULL_GPIO1_OFFSET 0x6110 +#define RK3576_PULL_GPIO2_OFFSET 0x6120 +#define RK3576_PULL_GPIO3_OFFSET 0x6130 +#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140 +#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148 +#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C + +static void rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + if (bank->bank_num == 0 && pin_num < 12) { + *reg = RK3576_PULL_GPIO0_AL_OFFSET; + } else if (bank->bank_num == 0) { + *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; + } else if (bank->bank_num == 1) { + *reg = RK3576_PULL_GPIO1_OFFSET; + } else if (bank->bank_num == 2) { + *reg = RK3576_PULL_GPIO2_OFFSET; + } else if (bank->bank_num == 3) { + *reg = RK3576_PULL_GPIO3_OFFSET; + } else if (bank->bank_num == 4 && pin_num < 16) { + *reg = RK3576_PULL_GPIO4_AL_OFFSET; + } else if (bank->bank_num == 4 && pin_num < 24) { + *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; + } else if (bank->bank_num == 4) { + *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; + } else { + *reg = 0; + debug("unsupported bank_num %d\n", bank->bank_num); + } + + *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3576_PULL_PINS_PER_REG; + *bit *= RK3576_PULL_BITS_PER_PIN; +} + +static int rk3576_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data, rmask; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3576_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = 1; /* FIXME: was always set to 1 in vendor kernel */ + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3576_PULL_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (ret << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3576_SMT_BITS_PER_PIN 1 +#define RK3576_SMT_PINS_PER_REG 8 +#define RK3576_SMT_GPIO0_AL_OFFSET 0x30 +#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040 +#define RK3576_SMT_GPIO1_OFFSET 0x6210 +#define RK3576_SMT_GPIO2_OFFSET 0x6220 +#define RK3576_SMT_GPIO3_OFFSET 0x6230 +#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240 +#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248 +#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C + +static void rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + if (bank->bank_num == 0 && pin_num < 12) { + *reg = RK3576_SMT_GPIO0_AL_OFFSET; + } else if (bank->bank_num == 0) { + *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; + } else if (bank->bank_num == 1) { + *reg = RK3576_SMT_GPIO1_OFFSET; + } else if (bank->bank_num == 2) { + *reg = RK3576_SMT_GPIO2_OFFSET; + } else if (bank->bank_num == 3) { + *reg = RK3576_SMT_GPIO3_OFFSET; + } else if (bank->bank_num == 4 && pin_num < 16) { + *reg = RK3576_SMT_GPIO4_AL_OFFSET; + } else if (bank->bank_num == 4 && pin_num < 24) { + *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; + } else if (bank->bank_num == 4) { + *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; + } else { + *reg = 0; + debug("unsupported bank_num %d\n", bank->bank_num); + } + + *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3576_SMT_PINS_PER_REG; + *bit *= RK3576_SMT_BITS_PER_PIN; +} + +static int rk3576_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u32 data, rmask; + u8 bit; + + rk3576_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3576_SMT_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (enable << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +static struct rockchip_pin_bank rk3576_pin_banks[] = { + RK3576_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_4BIT, + 0, 0x8, 0x2004, 0x200C), + RK3576_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, + 0x4020, 0x4028, 0x4030, 0x4038), + RK3576_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, + 0x4040, 0x4048, 0x4050, 0x4058), + RK3576_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, + 0x4060, 0x4068, 0x4070, 0x4078), + RK3576_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, + 0x4080, 0x4088, 0xA390, 0xB398), +}; + +static const struct rockchip_pin_ctrl rk3576_pin_ctrl = { + .pin_banks = rk3576_pin_banks, + .nr_banks = ARRAY_SIZE(rk3576_pin_banks), + .grf_mux_offset = 0x0, + .set_mux = rk3576_set_mux, + .set_pull = rk3576_set_pull, + .set_drive = rk3576_set_drive, + .set_schmitt = rk3576_set_schmitt, +}; + +static const struct udevice_id rk3576_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3576-pinctrl", + .data = (ulong)&rk3576_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3576) = { + .name = "rockchip_rk3576_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3576_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index df7bc684d29..5e3c9c90760 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -458,6 +458,9 @@ struct rockchip_pin_bank { #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) +#define RK3576_PIN_BANK_FLAGS(ID, PIN, LABEL, M, O1, O2, O3, O4) \ + PIN_BANK_IOMUX_FLAGS_OFFSET(ID, PIN, LABEL, M, M, M, M, O1, O2, O3, O4) + #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index a6e5f9ed036..938bd8cbc9f 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -12,10 +12,6 @@ #include <power-domain-uclass.h> #include <dm/device-internal.h> -struct power_domain_priv { - int on_count; -}; - static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev) { return (struct power_domain_ops *)dev->driver->ops; @@ -111,49 +107,22 @@ int power_domain_free(struct power_domain *power_domain) return ops->rfree ? ops->rfree(power_domain) : 0; } -int power_domain_on_lowlevel(struct power_domain *power_domain) +int power_domain_on(struct power_domain *power_domain) { - struct power_domain_priv *priv = dev_get_uclass_priv(power_domain->dev); struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); - int ret; debug("%s(power_domain=%p)\n", __func__, power_domain); - if (priv->on_count++ > 0) - return -EALREADY; - - ret = ops->on ? ops->on(power_domain) : 0; - if (ret) { - priv->on_count--; - return ret; - } - - return 0; + return ops->on ? ops->on(power_domain) : 0; } -int power_domain_off_lowlevel(struct power_domain *power_domain) +int power_domain_off(struct power_domain *power_domain) { - struct power_domain_priv *priv = dev_get_uclass_priv(power_domain->dev); struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); - int ret; debug("%s(power_domain=%p)\n", __func__, power_domain); - if (priv->on_count <= 0) { - debug("Power domain %s already off.\n", power_domain->dev->name); - return -EALREADY; - } - - if (priv->on_count-- > 1) - return -EBUSY; - - ret = ops->off ? ops->off(power_domain) : 0; - if (ret) { - priv->on_count++; - return ret; - } - - return 0; + return ops->off ? ops->off(power_domain) : 0; } #if CONFIG_IS_ENABLED(OF_REAL) @@ -211,5 +180,4 @@ int dev_power_domain_off(struct udevice *dev) UCLASS_DRIVER(power_domain) = { .id = UCLASS_POWER_DOMAIN, .name = "power_domain", - .per_device_auto = sizeof(struct power_domain_priv), }; diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c index 5b530974e94..08c15ef342b 100644 --- a/drivers/power/domain/sandbox-power-domain-test.c +++ b/drivers/power/domain/sandbox-power-domain-test.c @@ -51,5 +51,4 @@ U_BOOT_DRIVER(sandbox_power_domain_test) = { .id = UCLASS_MISC, .of_match = sandbox_power_domain_test_ids, .priv_auto = sizeof(struct sandbox_power_domain_test), - .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 99f6506f162..79db1a6a8aa 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -175,12 +175,19 @@ U_BOOT_DRIVER(scmi_regulator) = { static int scmi_regulator_bind(struct udevice *dev) { struct driver *drv; + ofnode regul_node; ofnode node; int ret; + regul_node = ofnode_find_subnode(dev_ofnode(dev), "regulators"); + if (!ofnode_valid(regul_node)) { + dev_err(dev, "no regulators node\n"); + return -ENXIO; + } + drv = DM_DRIVER_GET(scmi_regulator); - ofnode_for_each_subnode(node, dev_ofnode(dev)) { + ofnode_for_each_subnode(node, regul_node) { ret = device_bind(dev, drv, ofnode_get_name(node), NULL, node, NULL); if (ret) diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 36dc0500dab..fd94aad0cd4 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -13,7 +13,9 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o diff --git a/drivers/ram/rockchip/sdram_rk3528.c b/drivers/ram/rockchip/sdram_rk3528.c new file mode 100644 index 00000000000..89d325bea66 --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3528.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <ram.h> +#include <asm/arch-rockchip/sdram.h> + +#define PMUGRF_BASE 0xff370000 +#define OS_REG18_REG 0x248 + +static int rk3528_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = CFG_SYS_SDRAM_BASE; + info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG18_REG); + + return 0; +} + +static struct ram_ops rk3528_dmc_ops = { + .get_info = rk3528_dmc_get_info, +}; + +static const struct udevice_id rk3528_dmc_ids[] = { + { .compatible = "rockchip,rk3528-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3528_dmc) = { + .name = "rockchip_rk3528_dmc", + .id = UCLASS_RAM, + .of_match = rk3528_dmc_ids, + .ops = &rk3528_dmc_ops, +}; diff --git a/drivers/ram/rockchip/sdram_rk3576.c b/drivers/ram/rockchip/sdram_rk3576.c new file mode 100644 index 00000000000..5a66032ef8f --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3576.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd. + */ + +#include <dm.h> +#include <ram.h> +#include <asm/arch-rockchip/sdram.h> + +#define PMU1GRF_BASE 0x26026000 +#define OS_REG2_REG 0x208 + +static int rk3576_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = CFG_SYS_SDRAM_BASE; + info->size = rockchip_sdram_size(PMU1GRF_BASE + OS_REG2_REG); + + return 0; +} + +static struct ram_ops rk3576_dmc_ops = { + .get_info = rk3576_dmc_get_info, +}; + +static const struct udevice_id rk3576_dmc_ids[] = { + { .compatible = "rockchip,rk3576-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3576_dmc) = { + .name = "rockchip_rk3576_dmc", + .id = UCLASS_RAM, + .of_match = rk3576_dmc_ids, + .ops = &rk3576_dmc_ops, +}; diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index b9494396013..1dd3cd99a14 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 76d108080d9..e57729f0ef9 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -23,6 +23,7 @@ #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> +#include <linux/kconfig.h> #define BANK_INCREMENT 4 #define NR_BANKS 8 @@ -114,6 +115,8 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + writel(0, data->modrst_base + 8); } return 0; diff --git a/drivers/reset/rst-rk3528.c b/drivers/reset/rst-rk3528.c new file mode 100644 index 00000000000..f6e760d468d --- /dev/null +++ b/drivers/reset/rst-rk3528.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Based on Sebastian Reichel's implementation for RK3588 + */ + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> +#include <dt-bindings/reset/rockchip,rk3528-cru.h> + +/* 0xFF4A0000 + 0x0A00 */ +#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3528_register_offset[] = { + /* CRU_SOFTRST_CON03 */ + RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0), + RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1), + RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2), + RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3), + RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4), + RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5), + RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6), + RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7), + RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8), + RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9), + RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10), + + /* CRU_SOFTRST_CON05 */ + RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13), + RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14), + RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15), + + /* CRU_SOFTRST_CON06 */ + RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2), + RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4), + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7), + + /* CRU_SOFTRST_CON08 */ + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1), + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3), + RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8), + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10), + RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15), + + /* CRU_SOFTRST_CON09 */ + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0), + RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1), + RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2), + RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5), + RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6), + RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7), + RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8), + RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9), + RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10), + RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12), + RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15), + + /* CRU_SOFTRST_CON10 */ + RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0), + RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7), + RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8), + RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11), + RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13), + RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14), + + /* CRU_SOFTRST_CON11 */ + RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4), + RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7), + RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12), + + /* CRU_SOFTRST_CON25 */ + RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6), + RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7), + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8), + RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9), + RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12), + RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13), + RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14), + RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15), + + /* CRU_SOFTRST_CON26 */ + RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0), + RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1), + RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2), + RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5), + RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13), + + /* CRU_SOFTRST_CON27 */ + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4), + RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7), + RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9), + RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11), + RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13), + RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15), + + /* CRU_SOFTRST_CON28 */ + RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1), + RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3), + RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4), + RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5), + + /* CRU_SOFTRST_CON30 */ + RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1), + RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2), + RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7), + + /* CRU_SOFTRST_CON32 */ + RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2), + RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4), + RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5), + RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7), + RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9), + RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11), + RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12), + RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14), + RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15), + + /* CRU_SOFTRST_CON33 */ + RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1), + + /* CRU_SOFTRST_CON34 */ + RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5), + RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8), + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9), + + /* CRU_SOFTRST_CON36 */ + RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5), + RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7), + RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11), + RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13), + RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14), + + /* CRU_SOFTRST_CON37 */ + RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2), + RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9), + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10), + RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14), + RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15), + + /* CRU_SOFTRST_CON38 */ + RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0), + RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2), + RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4), + RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7), + RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9), + RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10), + + /* CRU_SOFTRST_CON39 */ + RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3), + RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5), + RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7), + RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8), + RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9), + RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11), + RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15), + + /* CRU_SOFTRST_CON40 */ + RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1), + RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2), + RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3), + RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4), + RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6), + RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7), + RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14), + RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15), + + /* CRU_SOFTRST_CON41 */ + RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0), + RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2), + RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3), + RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4), + RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5), + RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6), + RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7), + RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9), + RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10), + + /* CRU_SOFTRST_CON42 */ + RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2), + RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7), + RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9), + RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11), + RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12), + RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13), + + /* CRU_SOFTRST_CON43 */ + RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2), + RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3), + RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4), + RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7), + RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9), + RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11), + RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13), + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14), + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15), + + /* CRU_SOFTRST_CON44 */ + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4), + RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8), + RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9), + RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11), + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12), + + /* CRU_SOFTRST_CON45 */ + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3), + RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9), + RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11), + RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12), + RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13), + RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14), + RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15), + + /* CRU_SOFTRST_CON46 */ + RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0), +}; + +int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + return rockchip_reset_bind_lut(pdev, rk3528_register_offset, + reg_offset, reg_number); +} diff --git a/drivers/reset/rst-rk3576.c b/drivers/reset/rst-rk3576.c new file mode 100644 index 00000000000..a6b83a2fd74 --- /dev/null +++ b/drivers/reset/rst-rk3576.c @@ -0,0 +1,647 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Collabora Ltd. + * Author: Detlev Casanova <detlev.casanova@collabora.com> + * Based on Sebastian Reichel's implementation for RK3588 + */ + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> +#include <dt-bindings/reset/rockchip,rk3576-cru.h> + +/* 0x27200000 + 0x0A00 */ +#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + (reg) * 16 + (bit)) +/* 0x27208000 + 0x0A00 */ +#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000 * 4 + (reg) * 16 + (bit)) +/* 0x27210000 + 0x0A00 */ +#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + (reg) * 16 + (bit)) +/* 0x27220000 + 0x0A00 */ +#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + (reg) * 16 + (bit)) + +/* mapping table for reset ID to register offset */ +static const int rk3576_register_offset[] = { + /* SOFTRST_CON01 */ + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14), + + /* SOFTRST_CON02 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1), + + /* SOFTRST_CON06 */ + RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2), + + /* SOFTRST_CON07 */ + RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15), + + /* SOFTRST_CON08 */ + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14), + + /* SOFTRST_CON09 */ + RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2), + RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3), + RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4), + RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7), + RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12), + + /* SOFTRST_CON11 */ + RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6), + RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8), + RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12), + RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14), + RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15), + + /* SOFTRST_CON12 */ + RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9), + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11), + RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12), + RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13), + RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14), + RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15), + + /* SOFTRST_CON13 */ + RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0), + RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1), + RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2), + RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3), + RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6), + RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8), + RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12), + RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15), + + /* SOFTRST_CON14 */ + RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4), + RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5), + RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6), + RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9), + RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12), + RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15), + + /* SOFTRST_CON15 */ + RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2), + RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5), + RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8), + RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9), + RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10), + RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15), + + /* SOFTRST_CON16 */ + RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1), + RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2), + RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3), + RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4), + RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5), + RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7), + RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10), + RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11), + + /* SOFTRST_CON17 */ + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4), + RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6), + RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7), + RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8), + RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9), + RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10), + RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12), + RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15), + + /* SOFTRST_CON18 */ + RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1), + RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3), + RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5), + RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8), + RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9), + RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11), + RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12), + RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13), + RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14), + RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15), + + /* SOFTRST_CON19 */ + RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4), + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9), + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11), + RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12), + RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13), + + /* SOFTRST_CON20 */ + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4), + RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5), + RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8), + RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9), + RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12), + RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13), + + /* SOFTRST_CON21 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3), + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5), + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6), + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15), + + /* SOFTRST_CON22 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0), + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1), + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4), + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6), + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9), + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14), + RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15), + + /* SOFTRST_CON23 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2), + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4), + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5), + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8), + RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11), + + /* SOFTRST_CON25 */ + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6), + + /* SOFTRST_CON26 */ + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6), + + /* SOFTRST_CON27 */ + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1), + + /* SOFTRST_CON28 */ + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9), + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11), + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12), + + /* SOFTRST_CON29 */ + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2), + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3), + + /* SOFTRST_CON31 */ + RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0), + RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10), + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12), + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14), + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15), + + /* SOFTRST_CON32 */ + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3), + RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6), + RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7), + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8), + RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11), + RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13), + + /* SOFTRST_CON33 */ + RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3), + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6), + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7), + RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9), + RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10), + RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11), + RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12), + + /* SOFTRST_CON34 */ + RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13), + RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15), + + /* SOFTRST_CON35 */ + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11), + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13), + RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14), + + /* SOFTRST_CON36 */ + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7), + RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9), + + /* SOFTRST_CON37 */ + RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0), + RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1), + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2), + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5), + RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6), + RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7), + + /* SOFTRST_CON40 */ + RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2), + RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3), + + /* SOFTRST_CON42 */ + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7), + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10), + RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12), + + /* SOFTRST_CON43 */ + RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2), + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10), + RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11), + RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13), + + /* SOFTRST_CON45 */ + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6), + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8), + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9), + + /* SOFTRST_CON47 */ + RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12), + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13), + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15), + + /* SOFTRST_CON48 */ + RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2), + + /* SOFTRST_CON49 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7), + RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11), + RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13), + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14), + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15), + + /* SOFTRST_CON50 */ + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0), + RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1), + RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3), + RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6), + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11), + RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12), + + /* SOFTRST_CON51 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5), + RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6), + + /* SOFTRST_CON53 */ + RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5), + RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8), + RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10), + RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11), + + /* SOFTRST_CON54 */ + RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8), + + /* SOFTRST_CON59 */ + RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5), + + /* SOFTRST_CON61 */ + RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8), + RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9), + RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13), + + /* SOFTRST_CON62 */ + RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0), + RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3), + + /* SOFTRST_CON63 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13), + RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14), + + /* SOFTRST_CON64 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5), + RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7), + RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13), + RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14), + + /* SOFTRST_CON65 */ + RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15), + + /* SOFTRST_CON66 */ + RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2), + + /* SOFTRST_CON67 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14), + + /* SOFTRST_CON68 */ + RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5), + RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13), + + /* SOFTRST_CON69 */ + RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13), + RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15), + + /* SOFTRST_CON72 */ + RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12), + + /* SOFTRST_CON75 */ + RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1), + + /* SOFTRST_CON78 */ + RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1), + RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2), + RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3), + RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4), + + /* SOFTRST_CON79 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2), + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4), + RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5), + + /* PPLL_SOFTRST_CON00 */ + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8), + + /* PPLL_SOFTRST_CON01 */ + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5), + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8), + + /* SECURENS_SOFTRST_CON00 */ + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3), + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4), + RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8), + RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9), + + /* PMU1_SOFTRST_CON00 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15), + + /* PMU1_SOFTRST_CON01 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2), + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3), + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7), + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13), + + /* PMU1_SOFTRST_CON02 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3), + + /* PMU1_SOFTRST_CON03 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13), + + /* PMU1_SOFTRST_CON04 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12), + + /* PMU1_SOFTRST_CON05 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2), + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13), + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15), + + /* PMU1_SOFTRST_CON06 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1), + + /* PMU1_SOFTRST_CON07 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7), +}; + +int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + return rockchip_reset_bind_lut(pdev, rk3576_register_offset, + reg_offset, reg_number); +} diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c index 2426648fbd5..d854ea90044 100644 --- a/drivers/rng/rockchip_rng.c +++ b/drivers/rng/rockchip_rng.c @@ -70,6 +70,27 @@ #define TRNG_v1_VERSION_CODE 0x46BC /* end of TRNG V1 register define */ +/* start of RKRNG register define */ +#define RKRNG_CTRL 0x0010 +#define RKRNG_CTRL_INST_REQ BIT(0) +#define RKRNG_CTRL_RESEED_REQ BIT(1) +#define RKRNG_CTRL_TEST_REQ BIT(2) +#define RKRNG_CTRL_SW_DRNG_REQ BIT(3) +#define RKRNG_CTRL_SW_TRNG_REQ BIT(4) + +#define RKRNG_STATE 0x0014 +#define RKRNG_STATE_INST_ACK BIT(0) +#define RKRNG_STATE_RESEED_ACK BIT(1) +#define RKRNG_STATE_TEST_ACK BIT(2) +#define RKRNG_STATE_SW_DRNG_ACK BIT(3) +#define RKRNG_STATE_SW_TRNG_ACK BIT(4) + +/* DRNG_DATA_0 ~ DNG_DATA_7 */ +#define RKRNG_DRNG_DATA_0 0x0070 +#define RKRNG_DRNG_DATA_7 0x008C + +/* end of RKRNG register define */ + #define RK_RNG_TIME_OUT 50000 /* max 50ms */ #define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos)) @@ -228,6 +249,49 @@ exit: return retval; } +static int rkrng_init(struct udevice *dev) +{ + struct rk_rng_plat *pdata = dev_get_priv(dev); + u32 reg = 0; + + rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff); + + reg = trng_read(pdata, RKRNG_STATE); + trng_write(pdata, RKRNG_STATE, reg); + + return 0; +} + +static int rkrng_rng_read(struct udevice *dev, void *data, size_t len) +{ + struct rk_rng_plat *pdata = dev_get_priv(dev); + u32 reg = 0; + int retval; + + if (len > RK_HW_RNG_MAX) + return -EINVAL; + + reg = RKRNG_CTRL_SW_DRNG_REQ; + + rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg); + + retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg, + (reg & RKRNG_STATE_SW_DRNG_ACK), + RK_RNG_TIME_OUT); + if (retval) + goto exit; + + trng_write(pdata, RKRNG_STATE, reg); + + rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len); + +exit: + /* close TRNG */ + rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff); + + return retval; +} + static int rockchip_rng_read(struct udevice *dev, void *data, size_t len) { unsigned char *buf = data; @@ -295,6 +359,11 @@ static const struct rk_rng_soc_data rk_trngv1_soc_data = { .rk_rng_read = rk_trngv1_rng_read, }; +static const struct rk_rng_soc_data rkrng_soc_data = { + .rk_rng_init = rkrng_init, + .rk_rng_read = rkrng_rng_read, +}; + static const struct dm_rng_ops rockchip_rng_ops = { .read = rockchip_rng_read, }; @@ -313,13 +382,21 @@ static const struct udevice_id rockchip_rng_match[] = { .data = (ulong)&rk_cryptov1_soc_data, }, { + .compatible = "rockchip,rk3568-rng", + .data = (ulong)&rk_cryptov2_soc_data, + }, + { .compatible = "rockchip,cryptov2-rng", .data = (ulong)&rk_cryptov2_soc_data, }, { - .compatible = "rockchip,trngv1", + .compatible = "rockchip,rk3588-rng", .data = (ulong)&rk_trngv1_soc_data, }, + { + .compatible = "rockchip,rkrng", + .data = (ulong)&rkrng_soc_data, + }, {}, }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 84130524c2d..589b526381f 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -519,6 +519,8 @@ config DEBUG_UART_BASE default 0x0 if DEBUG_UART_SANDBOX default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ + default 0xff000000 if DEBUG_UART_PL011 && ARCH_VERSAL + default 0xf1920000 if DEBUG_UART_PL011 && (ARCH_VERSAL_NET || ARCH_VERSAL2) help This is the base address of your UART for memory-mapped UARTs. @@ -554,6 +556,7 @@ config DEBUG_UART_CLOCK default 0 if DEBUG_MVEBU_A3700_UART default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ + default 100000000 if DEBUG_UART_PL011 && (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f475f341c9c..a3513f0a3ef 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -59,6 +59,15 @@ config ADI_SPI3 Enable the ADI (Analog Devices) SPI controller driver. This driver enables the support for SC5XX spi controller. +config AIROHA_SNFI_SPI + bool "Airoha SPI memory controller driver" + depends on SPI_MEM + help + Enable the Airoha SPI memory controller driver. This driver is + originally based on the Airoha SNFI IP core. It can only be + used to access SPI memory devices like SPI-NOR or SPI-NAND on + platforms embedding this IP core, like AN7581. + config ALTERA_SPI bool "Altera SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 21895d46429..da91b18b6ed 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o endif obj-$(CONFIG_ADI_SPI3) += adi_spi3.o +obj-$(CONFIG_AIROHA_SNFI_SPI) += airoha_snfi_spi.o obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_APPLE_SPI) += apple_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c new file mode 100644 index 00000000000..3ea25b293d1 --- /dev/null +++ b/drivers/spi/airoha_snfi_spi.c @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 AIROHA Inc + * + * Based on spi-airoha-snfi.c on Linux + * + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Ray Liu <ray.liu@airoha.com> + */ + +#include <asm/unaligned.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/bitfield.h> +#include <linux/dma-mapping.h> +#include <linux/mtd/spinand.h> +#include <linux/time.h> +#include <regmap.h> +#include <spi.h> +#include <spi-mem.h> + +/* SPI */ +#define REG_SPI_CTRL_READ_MODE 0x0000 +#define REG_SPI_CTRL_READ_IDLE_EN 0x0004 +#define REG_SPI_CTRL_SIDLY 0x0008 +#define REG_SPI_CTRL_CSHEXT 0x000c +#define REG_SPI_CTRL_CSLEXT 0x0010 + +#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014 +#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0) + +#define REG_SPI_CTRL_RDCTL_FSM 0x0018 +#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0) + +#define REG_SPI_CTRL_MACMUX_SEL 0x001c + +#define REG_SPI_CTRL_MANUAL_EN 0x0020 +#define SPI_CTRL_MANUAL_EN BIT(0) + +#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024 +#define SPI_CTRL_OPFIFO_EMPTY BIT(0) + +#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028 +#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0) +#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9) + +#define REG_SPI_CTRL_OPFIFO_FULL 0x002c +#define SPI_CTRL_OPFIFO_FULL BIT(0) + +#define REG_SPI_CTRL_OPFIFO_WR 0x0030 +#define SPI_CTRL_OPFIFO_WR BIT(0) + +#define REG_SPI_CTRL_DFIFO_FULL 0x0034 +#define SPI_CTRL_DFIFO_FULL BIT(0) + +#define REG_SPI_CTRL_DFIFO_WDATA 0x0038 +#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0) + +#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c +#define SPI_CTRL_DFIFO_EMPTY BIT(0) + +#define REG_SPI_CTRL_DFIFO_RD 0x0040 +#define SPI_CTRL_DFIFO_RD BIT(0) + +#define REG_SPI_CTRL_DFIFO_RDATA 0x0044 +#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0) + +#define REG_SPI_CTRL_DUMMY 0x0080 +#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0) + +#define REG_SPI_CTRL_PROBE_SEL 0x0088 +#define REG_SPI_CTRL_INTERRUPT 0x0090 +#define REG_SPI_CTRL_INTERRUPT_EN 0x0094 +#define REG_SPI_CTRL_SI_CK_SEL 0x009c +#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c +#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110 +#define REG_SPI_CTRL_SFC_STRAP 0x0114 + +#define REG_SPI_CTRL_NFI2SPI_EN 0x0130 +#define SPI_CTRL_NFI2SPI_EN BIT(0) + +/* NFI2SPI */ +#define REG_SPI_NFI_CNFG 0x0000 +#define SPI_NFI_DMA_MODE BIT(0) +#define SPI_NFI_READ_MODE BIT(1) +#define SPI_NFI_DMA_BURST_EN BIT(2) +#define SPI_NFI_HW_ECC_EN BIT(8) +#define SPI_NFI_AUTO_FDM_EN BIT(9) +#define SPI_NFI_OPMODE GENMASK(14, 12) + +#define REG_SPI_NFI_PAGEFMT 0x0004 +#define SPI_NFI_PAGE_SIZE GENMASK(1, 0) +#define SPI_NFI_SPARE_SIZE GENMASK(5, 4) + +#define REG_SPI_NFI_CON 0x0008 +#define SPI_NFI_FIFO_FLUSH BIT(0) +#define SPI_NFI_RST BIT(1) +#define SPI_NFI_RD_TRIG BIT(8) +#define SPI_NFI_WR_TRIG BIT(9) +#define SPI_NFI_SEC_NUM GENMASK(15, 12) + +#define REG_SPI_NFI_INTR_EN 0x0010 +#define SPI_NFI_RD_DONE_EN BIT(0) +#define SPI_NFI_WR_DONE_EN BIT(1) +#define SPI_NFI_RST_DONE_EN BIT(2) +#define SPI_NFI_ERASE_DONE_EN BIT(3) +#define SPI_NFI_BUSY_RETURN_EN BIT(4) +#define SPI_NFI_ACCESS_LOCK_EN BIT(5) +#define SPI_NFI_AHB_DONE_EN BIT(6) +#define SPI_NFI_ALL_IRQ_EN \ + (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \ + SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \ + SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \ + SPI_NFI_AHB_DONE_EN) + +#define REG_SPI_NFI_INTR 0x0014 +#define SPI_NFI_AHB_DONE BIT(6) + +#define REG_SPI_NFI_CMD 0x0020 + +#define REG_SPI_NFI_ADDR_NOB 0x0030 +#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4) + +#define REG_SPI_NFI_STA 0x0060 +#define REG_SPI_NFI_FIFOSTA 0x0064 +#define REG_SPI_NFI_STRADDR 0x0080 +#define REG_SPI_NFI_FDM0L 0x00a0 +#define REG_SPI_NFI_FDM0M 0x00a4 +#define REG_SPI_NFI_FDM7L 0x00d8 +#define REG_SPI_NFI_FDM7M 0x00dc +#define REG_SPI_NFI_FIFODATA0 0x0190 +#define REG_SPI_NFI_FIFODATA1 0x0194 +#define REG_SPI_NFI_FIFODATA2 0x0198 +#define REG_SPI_NFI_FIFODATA3 0x019c +#define REG_SPI_NFI_MASTERSTA 0x0224 + +#define REG_SPI_NFI_SECCUS_SIZE 0x022c +#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0) +#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16) + +#define REG_SPI_NFI_RD_CTL2 0x0510 +#define REG_SPI_NFI_RD_CTL3 0x0514 + +#define REG_SPI_NFI_PG_CTL1 0x0524 +#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8) + +#define REG_SPI_NFI_PG_CTL2 0x0528 +#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c +#define REG_SPI_NFI_NOR_RD_ADDR 0x0534 + +#define REG_SPI_NFI_SNF_MISC_CTL 0x0538 +#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16) + +#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c +#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0) +#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16) + +#define REG_SPI_NFI_SNF_STA_CTL1 0x0550 +#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25) +#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26) + +#define REG_SPI_NFI_SNF_STA_CTL2 0x0554 + +#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c +#define SPI_NFI_SPI_MODE BIT(0) + +/* SPI NAND Protocol OP */ +#define SPI_NAND_OP_GET_FEATURE 0x0f +#define SPI_NAND_OP_SET_FEATURE 0x1f +#define SPI_NAND_OP_PAGE_READ 0x13 +#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03 +#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b +#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b +#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b +#define SPI_NAND_OP_WRITE_ENABLE 0x06 +#define SPI_NAND_OP_WRITE_DISABLE 0x04 +#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02 +#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32 +#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84 +#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34 +#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10 +#define SPI_NAND_OP_READ_ID 0x9f +#define SPI_NAND_OP_BLOCK_ERASE 0xd8 +#define SPI_NAND_OP_RESET 0xff +#define SPI_NAND_OP_DIE_SELECT 0xc2 + +#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256) +#define SPI_MAX_TRANSFER_SIZE 511 + +enum airoha_snand_mode { + SPI_MODE_AUTO, + SPI_MODE_MANUAL, + SPI_MODE_DMA, +}; + +enum airoha_snand_cs { + SPI_CHIP_SEL_HIGH, + SPI_CHIP_SEL_LOW, +}; + +struct airoha_snand_priv { + struct regmap *regmap_ctrl; + struct regmap *regmap_nfi; + struct clk *spi_clk; + + struct { + size_t page_size; + size_t sec_size; + u8 sec_num; + u8 spare_size; + } nfi_cfg; +}; + +static int airoha_snand_set_fifo_op(struct airoha_snand_priv *priv, + u8 op_cmd, int op_len) +{ + int err; + u32 val; + + err = regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA, + FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) | + FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd)); + if (err) + return err; + + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_OPFIFO_FULL, + val, !(val & SPI_CTRL_OPFIFO_FULL), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR, + SPI_CTRL_OPFIFO_WR); + if (err) + return err; + + return regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_OPFIFO_EMPTY, + val, (val & SPI_CTRL_OPFIFO_EMPTY), + 0, 250 * USEC_PER_MSEC); +} + +static int airoha_snand_set_cs(struct airoha_snand_priv *priv, u8 cs) +{ + return airoha_snand_set_fifo_op(priv, cs, sizeof(cs)); +} + +static int airoha_snand_write_data_to_fifo(struct airoha_snand_priv *priv, + const u8 *data, int len) +{ + int i; + + for (i = 0; i < len; i++) { + int err; + u32 val; + + /* 1. Wait until dfifo is not full */ + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_FULL, val, + !(val & SPI_CTRL_DFIFO_FULL), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + /* 2. Write data to register DFIFO_WDATA */ + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_WDATA, + FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i])); + if (err) + return err; + + /* 3. Wait until dfifo is not full */ + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_FULL, val, + !(val & SPI_CTRL_DFIFO_FULL), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + } + + return 0; +} + +static int airoha_snand_read_data_from_fifo(struct airoha_snand_priv *priv, + u8 *ptr, int len) +{ + int i; + + for (i = 0; i < len; i++) { + int err; + u32 val; + + /* 1. wait until dfifo is not empty */ + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_EMPTY, val, + !(val & SPI_CTRL_DFIFO_EMPTY), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + /* 2. read from dfifo to register DFIFO_RDATA */ + err = regmap_read(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_RDATA, &val); + if (err) + return err; + + ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val); + /* 3. enable register DFIFO_RD to read next byte */ + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD); + if (err) + return err; + } + + return 0; +} + +static int airoha_snand_set_mode(struct airoha_snand_priv *priv, + enum airoha_snand_mode mode) +{ + int err; + + switch (mode) { + case SPI_MODE_MANUAL: { + u32 val; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_NFI2SPI_EN, 0); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_READ_IDLE_EN, 0); + if (err) + return err; + + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_RDCTL_FSM, val, + !(val & SPI_CTRL_RDCTL_FSM), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MTX_MODE_TOG, 9); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN); + if (err) + return err; + break; + } + case SPI_MODE_DMA: + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_NFI2SPI_EN, + SPI_CTRL_MANUAL_EN); + if (err < 0) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MTX_MODE_TOG, 0x0); + if (err < 0) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MANUAL_EN, 0x0); + if (err < 0) + return err; + break; + case SPI_MODE_AUTO: + default: + break; + } + + return regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0); +} + +static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd, + const u8 *data, int len) +{ + int i, data_len; + + for (i = 0; i < len; i += data_len) { + int err; + + data_len = min(len - i, SPI_MAX_TRANSFER_SIZE); + err = airoha_snand_set_fifo_op(priv, cmd, data_len); + if (err) + return err; + + err = airoha_snand_write_data_to_fifo(priv, &data[i], + data_len); + if (err < 0) + return err; + } + + return 0; +} + +static int airoha_snand_read_data(struct airoha_snand_priv *priv, u8 *data, + int len) +{ + int i, data_len; + + for (i = 0; i < len; i += data_len) { + int err; + + data_len = min(len - i, SPI_MAX_TRANSFER_SIZE); + err = airoha_snand_set_fifo_op(priv, 0xc, data_len); + if (err) + return err; + + err = airoha_snand_read_data_from_fifo(priv, &data[i], + data_len); + if (err < 0) + return err; + } + + return 0; +} + +static int airoha_snand_nfi_init(struct airoha_snand_priv *priv) +{ + int err; + + /* switch to SNFI mode */ + err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG, + SPI_NFI_SPI_MODE); + if (err) + return err; + + /* Enable DMA */ + return regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_INTR_EN, + SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN); +} + +static int airoha_snand_nfi_config(struct airoha_snand_priv *priv) +{ + int err; + u32 val; + + err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON, + SPI_NFI_FIFO_FLUSH | SPI_NFI_RST); + if (err) + return err; + + /* auto FDM */ + err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG, + SPI_NFI_AUTO_FDM_EN); + if (err) + return err; + + /* HW ECC */ + err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG, + SPI_NFI_HW_ECC_EN); + if (err) + return err; + + /* DMA Burst */ + err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG, + SPI_NFI_DMA_BURST_EN); + if (err) + return err; + + /* page format */ + switch (priv->nfi_cfg.spare_size) { + case 26: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1); + break; + case 27: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2); + break; + case 28: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3); + break; + default: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0); + break; + } + + err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT, + SPI_NFI_SPARE_SIZE, val); + if (err) + return err; + + switch (priv->nfi_cfg.page_size) { + case 2048: + val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1); + break; + case 4096: + val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2); + break; + default: + val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0); + break; + } + + err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT, + SPI_NFI_PAGE_SIZE, val); + if (err) + return err; + + /* sec num */ + val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num); + err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON, + SPI_NFI_SEC_NUM, val); + if (err) + return err; + + /* enable cust sec size */ + err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, + SPI_NFI_CUS_SEC_SIZE_EN); + if (err) + return err; + + /* set cust sec size */ + val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, priv->nfi_cfg.sec_size); + return regmap_update_bits(priv->regmap_nfi, + REG_SPI_NFI_SECCUS_SIZE, + SPI_NFI_CUS_SEC_SIZE, val); +} + +static int airoha_snand_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + size_t max_len; + + max_len = 1 + op->addr.nbytes + op->dummy.nbytes; + if (max_len >= 160) + return -EOPNOTSUPP; + + if (op->data.nbytes > 160 - max_len) + op->data.nbytes = 160 - max_len; + + return 0; +} + +static bool airoha_snand_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + if (!spi_mem_default_supports_op(slave, op)) + return false; + + if (op->cmd.buswidth != 1) + return false; + + return (!op->addr.nbytes || op->addr.buswidth == 1) && + (!op->dummy.nbytes || op->dummy.buswidth == 1) && + (!op->data.nbytes || op->data.buswidth == 1); +} + +static int airoha_snand_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + u8 data[8], cmd, opcode = op->cmd.opcode; + struct udevice *bus = slave->dev->parent; + struct airoha_snand_priv *priv; + int i, err; + + priv = dev_get_priv(bus); + + /* switch to manual mode */ + err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL); + if (err < 0) + return err; + + err = airoha_snand_set_cs(priv, SPI_CHIP_SEL_LOW); + if (err < 0) + return err; + + /* opcode */ + err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode)); + if (err) + return err; + + /* addr part */ + cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8; + put_unaligned_be64(op->addr.val, data); + + for (i = ARRAY_SIZE(data) - op->addr.nbytes; + i < ARRAY_SIZE(data); i++) { + err = airoha_snand_write_data(priv, cmd, &data[i], + sizeof(data[0])); + if (err) + return err; + } + + /* dummy */ + data[0] = 0xff; + for (i = 0; i < op->dummy.nbytes; i++) { + err = airoha_snand_write_data(priv, 0x8, &data[0], + sizeof(data[0])); + if (err) + return err; + } + + /* data */ + if (op->data.dir == SPI_MEM_DATA_IN) { + err = airoha_snand_read_data(priv, op->data.buf.in, + op->data.nbytes); + if (err) + return err; + } else { + err = airoha_snand_write_data(priv, 0x8, op->data.buf.out, + op->data.nbytes); + if (err) + return err; + } + + return airoha_snand_set_cs(priv, SPI_CHIP_SEL_HIGH); +} + +static int airoha_snand_probe(struct udevice *dev) +{ + struct airoha_snand_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_ctrl, 0); + if (ret) { + dev_err(dev, "failed to init spi ctrl regmap\n"); + return ret; + } + + ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_nfi, 1); + if (ret) { + dev_err(dev, "failed to init spi nfi regmap\n"); + return ret; + } + + priv->spi_clk = devm_clk_get(dev, "spi"); + if (IS_ERR(priv->spi_clk)) { + dev_err(dev, "unable to get spi clk\n"); + return PTR_ERR(priv->regmap_ctrl); + } + clk_enable(priv->spi_clk); + + return airoha_snand_nfi_init(priv); +} + +static int airoha_snand_nfi_set_speed(struct udevice *bus, uint speed) +{ + struct airoha_snand_priv *priv = dev_get_priv(bus); + int ret; + + ret = clk_set_rate(priv->spi_clk, speed); + if (ret < 0) + return ret; + + return 0; +} + +static int airoha_snand_nfi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int airoha_snand_nfi_setup(struct spi_slave *slave, + const struct spinand_info *spinand_info) +{ + struct udevice *bus = slave->dev->parent; + struct airoha_snand_priv *priv; + u32 sec_size, sec_num; + int pagesize, oobsize; + + priv = dev_get_priv(bus); + + pagesize = spinand_info->memorg.pagesize; + oobsize = spinand_info->memorg.oobsize; + + if (pagesize == 2 * 1024) + sec_num = 4; + else if (pagesize == 4 * 1024) + sec_num = 8; + else + sec_num = 1; + + sec_size = (pagesize + oobsize) / sec_num; + + /* init default value */ + priv->nfi_cfg.sec_size = sec_size; + priv->nfi_cfg.sec_num = sec_num; + priv->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024); + priv->nfi_cfg.spare_size = 16; + + return airoha_snand_nfi_config(priv); +} + +static const struct spi_controller_mem_ops airoha_snand_mem_ops = { + .adjust_op_size = airoha_snand_adjust_op_size, + .supports_op = airoha_snand_supports_op, + .exec_op = airoha_snand_exec_op, +}; + +static const struct dm_spi_ops airoha_snfi_spi_ops = { + .mem_ops = &airoha_snand_mem_ops, + .set_speed = airoha_snand_nfi_set_speed, + .set_mode = airoha_snand_nfi_set_mode, + .setup_for_spinand = airoha_snand_nfi_setup, +}; + +static const struct udevice_id airoha_snand_ids[] = { + { .compatible = "airoha,en7581-snand" }, + { } +}; + +U_BOOT_DRIVER(airoha_snfi_spi) = { + .name = "airoha-snfi-spi", + .id = UCLASS_SPI, + .of_match = airoha_snand_ids, + .ops = &airoha_snfi_spi_ops, + .priv_auto = sizeof(struct airoha_snand_priv), + .probe = airoha_snand_probe, +}; diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 816916de16d..fbeb0c6a85c 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -204,3 +204,22 @@ void cadence_qspi_apb_enable_linear_mode(bool enable) ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); } } + +int cadence_device_reset(struct udevice *bus) +{ + struct cadence_spi_priv *priv = dev_get_priv(bus); + u32 reg; + + reg = readl(priv->regbase + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK; + writel(reg, priv->regbase + CQSPI_REG_CONFIG); + + writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG); + udelay(5); + writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG); + udelay(150); + writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG); + udelay(1200); + + return 0; +} diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 623904ecdad..9edbfaa821b 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -27,12 +27,20 @@ #define CQSPI_READ 2 #define CQSPI_WRITE 3 +/* Quirks */ +#define CQSPI_DISABLE_STIG_MODE BIT(0) + __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { return 0; } +__weak int cadence_device_reset(struct udevice *dev) +{ + return 0; +} + __weak int cadence_qspi_flash_reset(struct udevice *dev) { return 0; @@ -217,6 +225,7 @@ static int cadence_spi_probe(struct udevice *bus) priv->tsd2d_ns = plat->tsd2d_ns; priv->tchsh_ns = plat->tchsh_ns; priv->tslch_ns = plat->tslch_ns; + priv->quirks = plat->quirks; if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, @@ -251,6 +260,9 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); + if (device_is_compatible(bus, "amd,versal2-ospi")) + return cadence_device_reset(bus); + /* Reset ospi flash device */ return cadence_qspi_flash_reset(bus); @@ -307,12 +319,16 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, * which is unsupported on some flash devices during register * reads, prefer STIG mode for such small reads. */ - if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) + if (!op->addr.nbytes || + (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && + !(priv->quirks & CQSPI_DISABLE_STIG_MODE))) mode = CQSPI_STIG_READ; else mode = CQSPI_READ; } else { - if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) + if (!op->addr.nbytes || !op->data.buf.out || + (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && + !(priv->quirks & CQSPI_DISABLE_STIG_MODE))) mode = CQSPI_STIG_WRITE; else mode = CQSPI_WRITE; @@ -427,6 +443,10 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay", -1); + const struct cqspi_driver_platdata *drvdata = + (struct cqspi_driver_platdata *)dev_get_driver_data(bus); + plat->quirks = drvdata->quirks; + debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, plat->page_size); @@ -449,9 +469,21 @@ static const struct dm_spi_ops cadence_spi_ops = { */ }; +static const struct cqspi_driver_platdata cdns_qspi = { + .quirks = CQSPI_DISABLE_STIG_MODE, +}; + static const struct udevice_id cadence_spi_ids[] = { - { .compatible = "cdns,qspi-nor" }, - { .compatible = "ti,am654-ospi" }, + { + .compatible = "cdns,qspi-nor", + .data = (ulong)&cdns_qspi, + }, + { + .compatible = "ti,am654-ospi" + }, + { + .compatible = "amd,versal2-ospi" + }, { } }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1f9125cd239..80510f2542b 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -45,6 +45,8 @@ #define CQSPI_REG_CONFIG_CLK_POL BIT(1) #define CQSPI_REG_CONFIG_CLK_PHA BIT(2) #define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) +#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5) +#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6) #define CQSPI_REG_CONFIG_DIRECT BIT(7) #define CQSPI_REG_CONFIG_DECODE BIT(9) #define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) @@ -220,6 +222,7 @@ struct cadence_spi_plat { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + u32 quirks; bool is_dma; }; @@ -251,6 +254,7 @@ struct cadence_spi_priv { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + u32 quirks; u8 edge_mode; u8 dll_mode; bool extra_dummy; @@ -266,6 +270,11 @@ struct cadence_spi_priv { bool dtr; }; +struct cqspi_driver_platdata { + u32 hwcaps_mask; + u32 quirks; +}; + /* Functions call declaration */ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv); void cadence_qspi_apb_controller_enable(void *reg_base_addr); @@ -310,5 +319,6 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_flash_reset(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); +int cadence_device_reset(struct udevice *dev); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 08ec179346e..5b2d5ccb146 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -737,9 +737,13 @@ static int cr50_i2c_report_state(struct udevice *dev, char *str, int str_max) static int cr50_i2c_open(struct udevice *dev) { + struct cr50_priv *priv = dev_get_priv(dev); char buf[80]; int ret; + if (priv->locality != -1) + return -EBUSY; + ret = process_reset(dev); if (ret) return log_msg_ret("reset", ret); diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index bfd844e4193..1c5ed538370 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -19,8 +19,6 @@ #include "ufshcd-dwc.h" #include "ufshci-dwc.h" -#define VERSAL2_UFS_DEVICE_ID 4 - #define SRAM_CSR_INIT_DONE_MASK BIT(0) #define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) #define SRAM_CSR_BYPASS_MASK BIT(2) @@ -32,19 +30,12 @@ #define TIMEOUT_MICROSEC 1000000L -#define IOCTL_UFS_TXRX_CFGRDY_GET 40 -#define IOCTL_UFS_SRAM_CSR_SEL 41 - -#define PM_UFS_SRAM_CSR_WRITE 0 -#define PM_UFS_SRAM_CSR_READ 1 - struct ufs_versal2_priv { struct ufs_hba *hba; struct reset_ctl *rstc; struct reset_ctl *rstphy; u32 phy_mode; u32 host_clk; - u32 pd_dev_id; u8 attcompval0; u8 attcompval1; u8 ctlecompval0; @@ -102,41 +93,6 @@ static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) return 0; } -int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value) -{ - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - if (!value) - return -EINVAL; - - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET, - 0, 0, ret_payload); - *value = ret_payload[1]; - - return ret; -} - -int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value) -{ - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - if (!value) - return -EINVAL; - - if (type == PM_UFS_SRAM_CSR_READ) { - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, - type, 0, ret_payload); - *value = ret_payload[1]; - } else { - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, - type, *value, 0); - } - - return ret; -} - static int ufs_versal2_enable_phy(struct ufs_hba *hba) { u32 offset, reg; @@ -281,7 +237,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) time_left = TIMEOUT_MICROSEC; do { time_left--; - ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®); + ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®); if (ret) return ret; @@ -312,8 +268,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) time_left = TIMEOUT_MICROSEC; do { time_left--; - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, - PM_UFS_SRAM_CSR_READ, ®); + ret = zynqmp_pm_ufs_sram_csr_read(®); if (ret) return ret; @@ -341,10 +296,10 @@ static int ufs_versal2_init(struct ufs_hba *hba) struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); struct clk clk; unsigned long core_clk_rate = 0; + u32 cal; int ret = 0; priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM; - priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID; ret = clk_get_by_name(hba->dev, "core_clk", &clk); if (ret) { @@ -371,6 +326,15 @@ static int ufs_versal2_init(struct ufs_hba *hba) return PTR_ERR(priv->rstphy); } + ret = zynqmp_pm_ufs_cal_reg(&cal); + if (ret) + return ret; + + priv->attcompval0 = (u8)cal; + priv->attcompval1 = (u8)(cal >> 8); + priv->ctlecompval0 = (u8)(cal >> 16); + priv->ctlecompval1 = (u8)(cal >> 24); + return ret; } @@ -397,8 +361,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, return ret; } - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, - PM_UFS_SRAM_CSR_READ, &sram_csr); + ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr); if (ret) return ret; @@ -410,8 +373,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, return -EINVAL; } - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, - PM_UFS_SRAM_CSR_WRITE, &sram_csr); + ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr); if (ret) return ret; diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c815764c2bc..46a83141481 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -85,6 +85,7 @@ config USB_GADGET_PRODUCT_NUM default 0x330e if ROCKCHIP_RK3308 default 0x350a if ROCKCHIP_RK3568 default 0x350b if ROCKCHIP_RK3588 + default 0x350c if ROCKCHIP_RK3528 default 0x0 help Product ID of the USB device emulated, reported to the host device. diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c index f18c6a0a761..8f7256069f5 100644 --- a/drivers/usb/gadget/f_acm.c +++ b/drivers/usb/gadget/f_acm.c @@ -238,18 +238,21 @@ static int acm_bind(struct usb_configuration *c, struct usb_function *f) return -ENODEV; f_acm->ep_in = ep; + ep->driver_data = c->cdev; /* claim */ ep = usb_ep_autoconfig(gadget, &acm_fs_out_desc); if (!ep) return -ENODEV; f_acm->ep_out = ep; + ep->driver_data = c->cdev; /* claim */ ep = usb_ep_autoconfig(gadget, &acm_fs_notify_desc); if (!ep) return -ENODEV; f_acm->ep_notify = ep; + ep->driver_data = c->cdev; /* claim */ if (gadget_is_dualspeed(gadget)) { /* Assume endpoint addresses are the same for both speeds */ @@ -660,6 +663,7 @@ static int acm_stdio_stop(struct stdio_dev *dev) { g_dnl_unregister(); g_dnl_clear_detach(); + dev->priv = NULL; return 0; } diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index bfec303e7af..7247245a702 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_USB #include <bootdev.h> +#include <uthread.h> #include <dm.h> #include <errno.h> #include <log.h> @@ -17,6 +18,7 @@ #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/uclass-internal.h> +#include <time.h> static bool asynch_allowed; @@ -172,6 +174,10 @@ int usb_get_max_xfer_size(struct usb_device *udev, size_t *size) return ops->get_max_xfer_size(bus, size); } +#if CONFIG_IS_ENABLED(UTHREAD) +static struct uthread_mutex mutex = UTHREAD_MUTEX_INITIALIZER; +#endif + int usb_stop(void) { struct udevice *bus; @@ -180,10 +186,14 @@ int usb_stop(void) struct usb_uclass_priv *uc_priv; int err = 0, ret; + uthread_mutex_lock(&mutex); + /* De-activate any devices that have been activated */ ret = uclass_get(UCLASS_USB, &uc); - if (ret) + if (ret) { + uthread_mutex_unlock(&mutex); return ret; + } uc_priv = uclass_get_priv(uc); @@ -218,28 +228,23 @@ int usb_stop(void) uc_priv->companion_device_count = 0; usb_started = 0; + uthread_mutex_unlock(&mutex); + return err; } -static void usb_scan_bus(struct udevice *bus, bool recurse) +static void _usb_scan_bus(void *arg) { + struct udevice *bus = (struct udevice *)arg; struct usb_bus_priv *priv; struct udevice *dev; int ret; priv = dev_get_uclass_priv(bus); - assert(recurse); /* TODO: Support non-recusive */ - - printf("scanning bus %s for devices... ", bus->name); - debug("\n"); ret = usb_scan_device(bus, 0, USB_SPEED_FULL, &dev); if (ret) - printf("failed, error %d\n", ret); - else if (priv->next_addr == 0) - printf("No USB Device found\n"); - else - printf("%d USB Device(s) found\n", priv->next_addr); + printf("Scanning bus %s failed, error %d\n", bus->name, ret); } static void remove_inactive_children(struct uclass *uc, struct udevice *bus) @@ -287,64 +292,127 @@ static int usb_probe_companion(struct udevice *bus) return 0; } +static void _usb_init_bus(void *arg) +{ + struct udevice *bus = (struct udevice *)arg; + int ret; + + /* init low_level USB */ + + /* + * For Sandbox, we need scan the device tree each time when we + * start the USB stack, in order to re-create the emulated USB + * devices and bind drivers for them before we actually do the + * driver probe. + * + * For USB onboard HUB, we need to do some non-trivial init + * like enabling a power regulator, before enumeration. + */ + if (IS_ENABLED(CONFIG_SANDBOX) || + IS_ENABLED(CONFIG_USB_ONBOARD_HUB)) { + ret = dm_scan_fdt_dev(bus); + if (ret) { + printf("Bus %s: USB device scan from fdt failed (%d)\n", + bus->name, ret); + return; + } + } + + ret = device_probe(bus); + if (ret == -ENODEV) { /* No such device. */ + printf("Bus %s: Port not available.\n", bus->name); + return; + } + + if (ret) { /* Other error. */ + printf("Bus %s: probe failed, error %d\n", bus->name, ret); + return; + } + + usb_probe_companion(bus); +} + +static int nthr; +static int grp_id; + +static void usb_init_bus(struct udevice *bus) +{ + if (!grp_id) + grp_id = uthread_grp_new_id(); + if (!uthread_create(NULL, _usb_init_bus, (void *)bus, 0, grp_id)) + nthr++; +} + +static void usb_scan_bus(struct udevice *bus, bool recurse) +{ + if (!grp_id) + grp_id = uthread_grp_new_id(); + if (!uthread_create(NULL, _usb_scan_bus, (void *)bus, 0, grp_id)) + nthr++; +} + +static void usb_report_devices(struct uclass *uc) +{ + struct usb_bus_priv *priv; + struct udevice *bus; + + uclass_foreach_dev(bus, uc) { + if (!device_active(bus)) + continue; + priv = dev_get_uclass_priv(bus); + printf("Bus %s: ", bus->name); + if (priv->next_addr == 0) + printf("No USB Device found\n"); + else + printf("%d USB Device(s) found\n", priv->next_addr); + } +} + +static void run_threads(void) +{ +#if CONFIG_IS_ENABLED(UTHREAD) + if (!nthr) + return; + while (!uthread_grp_done(grp_id)) + uthread_schedule(); + nthr = 0; + grp_id = 0; +#endif +} + int usb_init(void) { int controllers_initialized = 0; + unsigned long t0 = timer_get_us(); struct usb_uclass_priv *uc_priv; struct usb_bus_priv *priv; struct udevice *bus; struct uclass *uc; int ret; + uthread_mutex_lock(&mutex); + + if (usb_started) { + ret = 0; + goto out; + } + asynch_allowed = 1; ret = uclass_get(UCLASS_USB, &uc); if (ret) - return ret; + goto out; uc_priv = uclass_get_priv(uc); uclass_foreach_dev(bus, uc) { - /* init low_level USB */ - printf("Bus %s: ", bus->name); - - /* - * For Sandbox, we need scan the device tree each time when we - * start the USB stack, in order to re-create the emulated USB - * devices and bind drivers for them before we actually do the - * driver probe. - * - * For USB onboard HUB, we need to do some non-trivial init - * like enabling a power regulator, before enumeration. - */ - if (IS_ENABLED(CONFIG_SANDBOX) || - IS_ENABLED(CONFIG_USB_ONBOARD_HUB)) { - ret = dm_scan_fdt_dev(bus); - if (ret) { - printf("USB device scan from fdt failed (%d)", ret); - continue; - } - } - - ret = device_probe(bus); - if (ret == -ENODEV) { /* No such device. */ - puts("Port not available.\n"); - controllers_initialized++; - continue; - } - - if (ret) { /* Other error. */ - printf("probe failed, error %d\n", ret); - continue; - } + usb_init_bus(bus); + } - ret = usb_probe_companion(bus); - if (ret) - continue; + if (CONFIG_IS_ENABLED(UTHREAD)) + run_threads(); - controllers_initialized++; - usb_started = true; - } + usb_started = true; /* * lowlevel init done, now scan the bus for devices i.e. search HUBs @@ -354,11 +422,16 @@ int usb_init(void) if (!device_active(bus)) continue; + controllers_initialized++; + priv = dev_get_uclass_priv(bus); if (!priv->companion) usb_scan_bus(bus, true); } + if (CONFIG_IS_ENABLED(UTHREAD)) + run_threads(); + /* * Now that the primary controllers have been scanned and have handed * over any devices they do not understand to their companions, scan @@ -375,21 +448,34 @@ int usb_init(void) } } - debug("scan end\n"); + if (CONFIG_IS_ENABLED(UTHREAD)) + run_threads(); + + usb_report_devices(uc); /* Remove any devices that were not found on this scan */ remove_inactive_children(uc, bus); ret = uclass_get(UCLASS_USB_HUB, &uc); if (ret) - return ret; + goto out; + remove_inactive_children(uc, bus); /* if we were not able to find at least one working bus, bail out */ if (controllers_initialized == 0) printf("No USB controllers found\n"); + debug("USB initialized in %ld ms\n", + (timer_get_us() - t0) / 1000); + + uthread_mutex_unlock(&mutex); + return usb_started ? 0 : -ENOENT; +out: + uthread_mutex_unlock(&mutex); + + return ret; } int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp) diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml index 522a6f0450e..0f4ca08d9ae 100644 --- a/dts/upstream/Bindings/arm/rockchip.yaml +++ b/dts/upstream/Bindings/arm/rockchip.yaml @@ -236,6 +236,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly ROC-RK3576-PC + items: + - const: firefly,roc-rk3576-pc + - const: rockchip,rk3576 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc diff --git a/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 00000000000..5a3ec902351 --- /dev/null +++ b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi <ziyao@disroot.org> + +description: | + The RK3528 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to specify + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + const: rockchip,rk3528-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + - description: > + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. + + clock-names: + items: + - const: xin24m + - const: gmac0 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0xff4a0000 0x30000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h new file mode 100644 index 00000000000..55a448f5ed6 --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 0 +#define PLL_CPLL 1 +#define PLL_GPLL 2 +#define PLL_PPLL 3 +#define PLL_DPLL 4 +#define ARMCLK 5 +#define XIN_OSC0_HALF 6 +#define CLK_MATRIX_50M_SRC 7 +#define CLK_MATRIX_100M_SRC 8 +#define CLK_MATRIX_150M_SRC 9 +#define CLK_MATRIX_200M_SRC 10 +#define CLK_MATRIX_250M_SRC 11 +#define CLK_MATRIX_300M_SRC 12 +#define CLK_MATRIX_339M_SRC 13 +#define CLK_MATRIX_400M_SRC 14 +#define CLK_MATRIX_500M_SRC 15 +#define CLK_MATRIX_600M_SRC 16 +#define CLK_UART0_SRC 17 +#define CLK_UART0_FRAC 18 +#define SCLK_UART0 19 +#define CLK_UART1_SRC 20 +#define CLK_UART1_FRAC 21 +#define SCLK_UART1 22 +#define CLK_UART2_SRC 23 +#define CLK_UART2_FRAC 24 +#define SCLK_UART2 25 +#define CLK_UART3_SRC 26 +#define CLK_UART3_FRAC 27 +#define SCLK_UART3 28 +#define CLK_UART4_SRC 29 +#define CLK_UART4_FRAC 30 +#define SCLK_UART4 31 +#define CLK_UART5_SRC 32 +#define CLK_UART5_FRAC 33 +#define SCLK_UART5 34 +#define CLK_UART6_SRC 35 +#define CLK_UART6_FRAC 36 +#define SCLK_UART6 37 +#define CLK_UART7_SRC 38 +#define CLK_UART7_FRAC 39 +#define SCLK_UART7 40 +#define CLK_I2S0_2CH_SRC 41 +#define CLK_I2S0_2CH_FRAC 42 +#define MCLK_I2S0_2CH_SAI_SRC 43 +#define CLK_I2S3_8CH_SRC 44 +#define CLK_I2S3_8CH_FRAC 45 +#define MCLK_I2S3_8CH_SAI_SRC 46 +#define CLK_I2S1_8CH_SRC 47 +#define CLK_I2S1_8CH_FRAC 48 +#define MCLK_I2S1_8CH_SAI_SRC 49 +#define CLK_I2S2_2CH_SRC 50 +#define CLK_I2S2_2CH_FRAC 51 +#define MCLK_I2S2_2CH_SAI_SRC 52 +#define CLK_SPDIF_SRC 53 +#define CLK_SPDIF_FRAC 54 +#define MCLK_SPDIF_SRC 55 +#define DCLK_VOP_SRC0 56 +#define DCLK_VOP_SRC1 57 +#define CLK_HSM 58 +#define CLK_CORE_SRC_ACS 59 +#define CLK_CORE_SRC_PVTMUX 60 +#define CLK_CORE_SRC 61 +#define CLK_CORE 62 +#define ACLK_M_CORE_BIU 63 +#define CLK_CORE_PVTPLL_SRC 64 +#define PCLK_DBG 65 +#define SWCLKTCK 66 +#define CLK_SCANHS_CORE 67 +#define CLK_SCANHS_ACLKM_CORE 68 +#define CLK_SCANHS_PCLK_DBG 69 +#define CLK_SCANHS_PCLK_CPU_BIU 70 +#define PCLK_CPU_ROOT 71 +#define PCLK_CORE_GRF 72 +#define PCLK_DAPLITE_BIU 73 +#define PCLK_CPU_BIU 74 +#define CLK_REF_PVTPLL_CORE 75 +#define ACLK_BUS_VOPGL_ROOT 76 +#define ACLK_BUS_VOPGL_BIU 77 +#define ACLK_BUS_H_ROOT 78 +#define ACLK_BUS_H_BIU 79 +#define ACLK_BUS_ROOT 80 +#define HCLK_BUS_ROOT 81 +#define PCLK_BUS_ROOT 82 +#define ACLK_BUS_M_ROOT 83 +#define ACLK_SYSMEM_BIU 84 +#define CLK_TIMER_ROOT 85 +#define ACLK_BUS_BIU 86 +#define HCLK_BUS_BIU 87 +#define PCLK_BUS_BIU 88 +#define PCLK_DFT2APB 89 +#define PCLK_BUS_GRF 90 +#define ACLK_BUS_M_BIU 91 +#define ACLK_GIC 92 +#define ACLK_SPINLOCK 93 +#define ACLK_DMAC 94 +#define PCLK_TIMER 95 +#define CLK_TIMER0 96 +#define CLK_TIMER1 97 +#define CLK_TIMER2 98 +#define CLK_TIMER3 99 +#define CLK_TIMER4 100 +#define CLK_TIMER5 101 +#define PCLK_JDBCK_DAP 102 +#define CLK_JDBCK_DAP 103 +#define PCLK_WDT_NS 104 +#define TCLK_WDT_NS 105 +#define HCLK_TRNG_NS 106 +#define PCLK_UART0 107 +#define PCLK_DMA2DDR 108 +#define ACLK_DMA2DDR 109 +#define PCLK_PWM0 110 +#define CLK_PWM0 111 +#define CLK_CAPTURE_PWM0 112 +#define PCLK_PWM1 113 +#define CLK_PWM1 114 +#define CLK_CAPTURE_PWM1 115 +#define PCLK_SCR 116 +#define ACLK_DCF 117 +#define PCLK_INTMUX 118 +#define CLK_PPLL_I 119 +#define CLK_PPLL_MUX 120 +#define CLK_PPLL_100M_MATRIX 121 +#define CLK_PPLL_50M_MATRIX 122 +#define CLK_REF_PCIE_INNER_PHY 123 +#define CLK_REF_PCIE_100M_PHY 124 +#define ACLK_VPU_L_ROOT 125 +#define CLK_GMAC1_VPU_25M 126 +#define CLK_PPLL_125M_MATRIX 127 +#define ACLK_VPU_ROOT 128 +#define HCLK_VPU_ROOT 129 +#define PCLK_VPU_ROOT 130 +#define ACLK_VPU_BIU 131 +#define HCLK_VPU_BIU 132 +#define PCLK_VPU_BIU 133 +#define ACLK_VPU 134 +#define HCLK_VPU 135 +#define PCLK_CRU_PCIE 136 +#define PCLK_VPU_GRF 137 +#define HCLK_SFC 138 +#define SCLK_SFC 139 +#define CCLK_SRC_EMMC 140 +#define HCLK_EMMC 141 +#define ACLK_EMMC 142 +#define BCLK_EMMC 143 +#define TCLK_EMMC 144 +#define PCLK_GPIO1 145 +#define DBCLK_GPIO1 146 +#define ACLK_VPU_L_BIU 147 +#define PCLK_VPU_IOC 148 +#define HCLK_SAI_I2S0 149 +#define MCLK_SAI_I2S0 150 +#define HCLK_SAI_I2S2 151 +#define MCLK_SAI_I2S2 152 +#define PCLK_ACODEC 153 +#define MCLK_ACODEC_TX 154 +#define PCLK_GPIO3 155 +#define DBCLK_GPIO3 156 +#define PCLK_SPI1 157 +#define CLK_SPI1 158 +#define SCLK_IN_SPI1 159 +#define PCLK_UART2 160 +#define PCLK_UART5 161 +#define PCLK_UART6 162 +#define PCLK_UART7 163 +#define PCLK_I2C3 164 +#define CLK_I2C3 165 +#define PCLK_I2C5 166 +#define CLK_I2C5 167 +#define PCLK_I2C6 168 +#define CLK_I2C6 169 +#define ACLK_MAC_VPU 170 +#define PCLK_MAC_VPU 171 +#define CLK_GMAC1_RMII_VPU 172 +#define CLK_GMAC1_SRC_VPU 173 +#define PCLK_PCIE 174 +#define CLK_PCIE_AUX 175 +#define ACLK_PCIE 176 +#define HCLK_PCIE_SLV 177 +#define HCLK_PCIE_DBI 178 +#define PCLK_PCIE_PHY 179 +#define PCLK_PIPE_GRF 180 +#define CLK_PIPE_USB3OTG_COMBO 181 +#define CLK_UTMI_USB3OTG 182 +#define CLK_PCIE_PIPE_PHY 183 +#define CCLK_SRC_SDIO0 184 +#define HCLK_SDIO0 185 +#define CCLK_SRC_SDIO1 186 +#define HCLK_SDIO1 187 +#define CLK_TS_0 188 +#define CLK_TS_1 189 +#define PCLK_CAN2 190 +#define CLK_CAN2 191 +#define PCLK_CAN3 192 +#define CLK_CAN3 193 +#define PCLK_SARADC 194 +#define CLK_SARADC 195 +#define PCLK_TSADC 196 +#define CLK_TSADC 197 +#define CLK_TSADC_TSEN 198 +#define ACLK_USB3OTG 199 +#define CLK_REF_USB3OTG 200 +#define CLK_SUSPEND_USB3OTG 201 +#define ACLK_GPU_ROOT 202 +#define PCLK_GPU_ROOT 203 +#define ACLK_GPU_BIU 204 +#define PCLK_GPU_BIU 205 +#define ACLK_GPU 206 +#define CLK_GPU_PVTPLL_SRC 207 +#define ACLK_GPU_MALI 208 +#define HCLK_RKVENC_ROOT 209 +#define ACLK_RKVENC_ROOT 210 +#define PCLK_RKVENC_ROOT 211 +#define HCLK_RKVENC_BIU 212 +#define ACLK_RKVENC_BIU 213 +#define PCLK_RKVENC_BIU 214 +#define HCLK_RKVENC 215 +#define ACLK_RKVENC 216 +#define CLK_CORE_RKVENC 217 +#define HCLK_SAI_I2S1 218 +#define MCLK_SAI_I2S1 219 +#define PCLK_I2C1 220 +#define CLK_I2C1 221 +#define PCLK_I2C0 222 +#define CLK_I2C0 223 +#define CLK_UART_JTAG 224 +#define PCLK_SPI0 225 +#define CLK_SPI0 226 +#define SCLK_IN_SPI0 227 +#define PCLK_GPIO4 228 +#define DBCLK_GPIO4 229 +#define PCLK_RKVENC_IOC 230 +#define HCLK_SPDIF 231 +#define MCLK_SPDIF 232 +#define HCLK_PDM 233 +#define MCLK_PDM 234 +#define PCLK_UART1 235 +#define PCLK_UART3 236 +#define PCLK_RKVENC_GRF 237 +#define PCLK_CAN0 238 +#define CLK_CAN0 239 +#define PCLK_CAN1 240 +#define CLK_CAN1 241 +#define ACLK_VO_ROOT 242 +#define HCLK_VO_ROOT 243 +#define PCLK_VO_ROOT 244 +#define ACLK_VO_BIU 245 +#define HCLK_VO_BIU 246 +#define PCLK_VO_BIU 247 +#define HCLK_RGA2E 248 +#define ACLK_RGA2E 249 +#define CLK_CORE_RGA2E 250 +#define HCLK_VDPP 251 +#define ACLK_VDPP 252 +#define CLK_CORE_VDPP 253 +#define PCLK_VO_GRF 254 +#define PCLK_CRU 255 +#define ACLK_VOP_ROOT 256 +#define ACLK_VOP_BIU 257 +#define HCLK_VOP 258 +#define DCLK_VOP0 259 +#define DCLK_VOP1 260 +#define ACLK_VOP 261 +#define PCLK_HDMI 262 +#define CLK_SFR_HDMI 263 +#define CLK_CEC_HDMI 264 +#define CLK_SPDIF_HDMI 265 +#define CLK_HDMIPHY_TMDSSRC 266 +#define CLK_HDMIPHY_PREP 267 +#define PCLK_HDMIPHY 268 +#define HCLK_HDCP_KEY 269 +#define ACLK_HDCP 270 +#define HCLK_HDCP 271 +#define PCLK_HDCP 272 +#define HCLK_CVBS 273 +#define DCLK_CVBS 274 +#define DCLK_4X_CVBS 275 +#define ACLK_JPEG_DECODER 276 +#define HCLK_JPEG_DECODER 277 +#define ACLK_VO_L_ROOT 278 +#define ACLK_VO_L_BIU 279 +#define ACLK_MAC_VO 280 +#define PCLK_MAC_VO 281 +#define CLK_GMAC0_SRC 282 +#define CLK_GMAC0_RMII_50M 283 +#define CLK_GMAC0_TX 284 +#define CLK_GMAC0_RX 285 +#define ACLK_JPEG_ROOT 286 +#define ACLK_JPEG_BIU 287 +#define HCLK_SAI_I2S3 288 +#define MCLK_SAI_I2S3 289 +#define CLK_MACPHY 290 +#define PCLK_VCDCPHY 291 +#define PCLK_GPIO2 292 +#define DBCLK_GPIO2 293 +#define PCLK_VO_IOC 294 +#define CCLK_SRC_SDMMC0 295 +#define HCLK_SDMMC0 296 +#define PCLK_OTPC_NS 297 +#define CLK_SBPI_OTPC_NS 298 +#define CLK_USER_OTPC_NS 299 +#define CLK_HDMIHDP0 300 +#define HCLK_USBHOST 301 +#define HCLK_USBHOST_ARB 302 +#define CLK_USBHOST_OHCI 303 +#define CLK_USBHOST_UTMI 304 +#define PCLK_UART4 305 +#define PCLK_I2C4 306 +#define CLK_I2C4 307 +#define PCLK_I2C7 308 +#define CLK_I2C7 309 +#define PCLK_USBPHY 310 +#define CLK_REF_USBPHY 311 +#define HCLK_RKVDEC_ROOT 312 +#define ACLK_RKVDEC_ROOT_NDFT 313 +#define PCLK_DDRPHY_CRU 314 +#define HCLK_RKVDEC_BIU 315 +#define ACLK_RKVDEC_BIU 316 +#define ACLK_RKVDEC 317 +#define HCLK_RKVDEC 318 +#define CLK_HEVC_CA_RKVDEC 319 +#define ACLK_RKVDEC_PVTMUX_ROOT 320 +#define CLK_RKVDEC_PVTPLL_SRC 321 +#define PCLK_DDR_ROOT 322 +#define PCLK_DDR_BIU 323 +#define PCLK_DDRC 324 +#define PCLK_DDRMON 325 +#define CLK_TIMER_DDRMON 326 +#define PCLK_MSCH_BIU 327 +#define PCLK_DDR_GRF 328 +#define PCLK_DDR_HWLP 329 +#define PCLK_DDRPHY 330 +#define CLK_MSCH_BIU 331 +#define ACLK_DDR_UPCTL 332 +#define CLK_DDR_UPCTL 333 +#define CLK_DDRMON 334 +#define ACLK_DDR_SCRAMBLE 335 +#define ACLK_SPLIT 336 +#define CLK_DDRC_SRC 337 +#define CLK_DDR_PHY 338 +#define PCLK_OTPC_S 339 +#define CLK_SBPI_OTPC_S 340 +#define CLK_USER_OTPC_S 341 +#define PCLK_KEYREADER 342 +#define PCLK_BUS_SGRF 343 +#define PCLK_STIMER 344 +#define CLK_STIMER0 345 +#define CLK_STIMER1 346 +#define PCLK_WDT_S 347 +#define TCLK_WDT_S 348 +#define HCLK_TRNG_S 349 +#define HCLK_BOOTROM 350 +#define PCLK_DCF 351 +#define ACLK_SYSMEM 352 +#define HCLK_TSP 353 +#define ACLK_TSP 354 +#define CLK_CORE_TSP 355 +#define CLK_OTPC_ARB 356 +#define PCLK_OTP_MASK 357 +#define CLK_PMC_OTP 358 +#define PCLK_PMU_ROOT 359 +#define HCLK_PMU_ROOT 360 +#define PCLK_I2C2 361 +#define CLK_I2C2 362 +#define HCLK_PMU_BIU 363 +#define PCLK_PMU_BIU 364 +#define FCLK_MCU 365 +#define RTC_CLK_MCU 366 +#define PCLK_OSCCHK 367 +#define CLK_PMU_MCU_JTAG 368 +#define PCLK_PMU 369 +#define PCLK_GPIO0 370 +#define DBCLK_GPIO0 371 +#define XIN_OSC0_DIV 372 +#define CLK_DEEPSLOW 373 +#define CLK_DDR_FAIL_SAFE 374 +#define PCLK_PMU_HP_TIMER 375 +#define CLK_PMU_HP_TIMER 376 +#define CLK_PMU_32K_HP_TIMER 377 +#define PCLK_PMU_IOC 378 +#define PCLK_PMU_CRU 379 +#define PCLK_PMU_GRF 380 +#define PCLK_PMU_WDT 381 +#define TCLK_PMU_WDT 382 +#define PCLK_PMU_MAILBOX 383 +#define PCLK_SCRKEYGEN 384 +#define CLK_SCRKEYGEN 385 +#define CLK_PVTM_OSCCHK 386 +#define CLK_REFOUT 387 +#define CLK_PVTM_PMU 388 +#define PCLK_PVTM_PMU 389 +#define PCLK_PMU_SGRF 390 +#define HCLK_PMU_SRAM 391 +#define CLK_UART0 392 +#define CLK_UART1 393 +#define CLK_UART2 394 +#define CLK_UART3 395 +#define CLK_UART4 396 +#define CLK_UART5 397 +#define CLK_UART6 398 +#define CLK_UART7 399 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 +#define MCLK_SDPDIF_SRC_PRE 404 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h new file mode 100644 index 00000000000..6b024c5f2e1 --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H + +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_NL2 8 +#define SRST_CORE_BIU 9 +#define SRST_CORE_CRYPTO 10 +#define SRST_P_DBG 11 +#define SRST_POT_DBG 12 +#define SRST_NT_DBG 13 +#define SRST_P_CORE_GRF 14 +#define SRST_P_DAPLITE_BIU 15 +#define SRST_P_CPU_BIU 16 +#define SRST_REF_PVTPLL_CORE 17 +#define SRST_A_BUS_VOPGL_BIU 18 +#define SRST_A_BUS_H_BIU 19 +#define SRST_A_SYSMEM_BIU 20 +#define SRST_A_BUS_BIU 21 +#define SRST_H_BUS_BIU 22 +#define SRST_P_BUS_BIU 23 +#define SRST_P_DFT2APB 24 +#define SRST_P_BUS_GRF 25 +#define SRST_A_BUS_M_BIU 26 +#define SRST_A_GIC 27 +#define SRST_A_SPINLOCK 28 +#define SRST_A_DMAC 29 +#define SRST_P_TIMER 30 +#define SRST_TIMER0 31 +#define SRST_TIMER1 32 +#define SRST_TIMER2 33 +#define SRST_TIMER3 34 +#define SRST_TIMER4 35 +#define SRST_TIMER5 36 +#define SRST_P_JDBCK_DAP 37 +#define SRST_JDBCK_DAP 38 +#define SRST_P_WDT_NS 39 +#define SRST_T_WDT_NS 40 +#define SRST_H_TRNG_NS 41 +#define SRST_P_UART0 42 +#define SRST_S_UART0 43 +#define SRST_PKA_CRYPTO 44 +#define SRST_A_CRYPTO 45 +#define SRST_H_CRYPTO 46 +#define SRST_P_DMA2DDR 47 +#define SRST_A_DMA2DDR 48 +#define SRST_P_PWM0 49 +#define SRST_PWM0 50 +#define SRST_P_PWM1 51 +#define SRST_PWM1 52 +#define SRST_P_SCR 53 +#define SRST_A_DCF 54 +#define SRST_P_INTMUX 55 +#define SRST_A_VPU_BIU 56 +#define SRST_H_VPU_BIU 57 +#define SRST_P_VPU_BIU 58 +#define SRST_A_VPU 59 +#define SRST_H_VPU 60 +#define SRST_P_CRU_PCIE 61 +#define SRST_P_VPU_GRF 62 +#define SRST_H_SFC 63 +#define SRST_S_SFC 64 +#define SRST_C_EMMC 65 +#define SRST_H_EMMC 66 +#define SRST_A_EMMC 67 +#define SRST_B_EMMC 68 +#define SRST_T_EMMC 69 +#define SRST_P_GPIO1 70 +#define SRST_DB_GPIO1 71 +#define SRST_A_VPU_L_BIU 72 +#define SRST_P_VPU_IOC 73 +#define SRST_H_SAI_I2S0 74 +#define SRST_M_SAI_I2S0 75 +#define SRST_H_SAI_I2S2 76 +#define SRST_M_SAI_I2S2 77 +#define SRST_P_ACODEC 78 +#define SRST_P_GPIO3 79 +#define SRST_DB_GPIO3 80 +#define SRST_P_SPI1 81 +#define SRST_SPI1 82 +#define SRST_P_UART2 83 +#define SRST_S_UART2 84 +#define SRST_P_UART5 85 +#define SRST_S_UART5 86 +#define SRST_P_UART6 87 +#define SRST_S_UART6 88 +#define SRST_P_UART7 89 +#define SRST_S_UART7 90 +#define SRST_P_I2C3 91 +#define SRST_I2C3 92 +#define SRST_P_I2C5 93 +#define SRST_I2C5 94 +#define SRST_P_I2C6 95 +#define SRST_I2C6 96 +#define SRST_A_MAC 97 +#define SRST_P_PCIE 98 +#define SRST_PCIE_PIPE_PHY 99 +#define SRST_PCIE_POWER_UP 100 +#define SRST_P_PCIE_PHY 101 +#define SRST_P_PIPE_GRF 102 +#define SRST_H_SDIO0 103 +#define SRST_H_SDIO1 104 +#define SRST_TS_0 105 +#define SRST_TS_1 106 +#define SRST_P_CAN2 107 +#define SRST_CAN2 108 +#define SRST_P_CAN3 109 +#define SRST_CAN3 110 +#define SRST_P_SARADC 111 +#define SRST_SARADC 112 +#define SRST_SARADC_PHY 113 +#define SRST_P_TSADC 114 +#define SRST_TSADC 115 +#define SRST_A_USB3OTG 116 +#define SRST_A_GPU_BIU 117 +#define SRST_P_GPU_BIU 118 +#define SRST_A_GPU 119 +#define SRST_REF_PVTPLL_GPU 120 +#define SRST_H_RKVENC_BIU 121 +#define SRST_A_RKVENC_BIU 122 +#define SRST_P_RKVENC_BIU 123 +#define SRST_H_RKVENC 124 +#define SRST_A_RKVENC 125 +#define SRST_CORE_RKVENC 126 +#define SRST_H_SAI_I2S1 127 +#define SRST_M_SAI_I2S1 128 +#define SRST_P_I2C1 129 +#define SRST_I2C1 130 +#define SRST_P_I2C0 131 +#define SRST_I2C0 132 +#define SRST_P_SPI0 133 +#define SRST_SPI0 134 +#define SRST_P_GPIO4 135 +#define SRST_DB_GPIO4 136 +#define SRST_P_RKVENC_IOC 137 +#define SRST_H_SPDIF 138 +#define SRST_M_SPDIF 139 +#define SRST_H_PDM 140 +#define SRST_M_PDM 141 +#define SRST_P_UART1 142 +#define SRST_S_UART1 143 +#define SRST_P_UART3 144 +#define SRST_S_UART3 145 +#define SRST_P_RKVENC_GRF 146 +#define SRST_P_CAN0 147 +#define SRST_CAN0 148 +#define SRST_P_CAN1 149 +#define SRST_CAN1 150 +#define SRST_A_VO_BIU 151 +#define SRST_H_VO_BIU 152 +#define SRST_P_VO_BIU 153 +#define SRST_H_RGA2E 154 +#define SRST_A_RGA2E 155 +#define SRST_CORE_RGA2E 156 +#define SRST_H_VDPP 157 +#define SRST_A_VDPP 158 +#define SRST_CORE_VDPP 159 +#define SRST_P_VO_GRF 160 +#define SRST_P_CRU 161 +#define SRST_A_VOP_BIU 162 +#define SRST_H_VOP 163 +#define SRST_D_VOP0 164 +#define SRST_D_VOP1 165 +#define SRST_A_VOP 166 +#define SRST_P_HDMI 167 +#define SRST_HDMI 168 +#define SRST_P_HDMIPHY 169 +#define SRST_H_HDCP_KEY 170 +#define SRST_A_HDCP 171 +#define SRST_H_HDCP 172 +#define SRST_P_HDCP 173 +#define SRST_H_CVBS 174 +#define SRST_D_CVBS_VOP 175 +#define SRST_D_4X_CVBS_VOP 176 +#define SRST_A_JPEG_DECODER 177 +#define SRST_H_JPEG_DECODER 178 +#define SRST_A_VO_L_BIU 179 +#define SRST_A_MAC_VO 180 +#define SRST_A_JPEG_BIU 181 +#define SRST_H_SAI_I2S3 182 +#define SRST_M_SAI_I2S3 183 +#define SRST_MACPHY 184 +#define SRST_P_VCDCPHY 185 +#define SRST_P_GPIO2 186 +#define SRST_DB_GPIO2 187 +#define SRST_P_VO_IOC 188 +#define SRST_H_SDMMC0 189 +#define SRST_P_OTPC_NS 190 +#define SRST_SBPI_OTPC_NS 191 +#define SRST_USER_OTPC_NS 192 +#define SRST_HDMIHDP0 193 +#define SRST_H_USBHOST 194 +#define SRST_H_USBHOST_ARB 195 +#define SRST_HOST_UTMI 196 +#define SRST_P_UART4 197 +#define SRST_S_UART4 198 +#define SRST_P_I2C4 199 +#define SRST_I2C4 200 +#define SRST_P_I2C7 201 +#define SRST_I2C7 202 +#define SRST_P_USBPHY 203 +#define SRST_USBPHY_POR 204 +#define SRST_USBPHY_OTG 205 +#define SRST_USBPHY_HOST 206 +#define SRST_P_DDRPHY_CRU 207 +#define SRST_H_RKVDEC_BIU 208 +#define SRST_A_RKVDEC_BIU 209 +#define SRST_A_RKVDEC 210 +#define SRST_H_RKVDEC 211 +#define SRST_HEVC_CA_RKVDEC 212 +#define SRST_REF_PVTPLL_RKVDEC 213 +#define SRST_P_DDR_BIU 214 +#define SRST_P_DDRC 215 +#define SRST_P_DDRMON 216 +#define SRST_TIMER_DDRMON 217 +#define SRST_P_MSCH_BIU 218 +#define SRST_P_DDR_GRF 219 +#define SRST_P_DDR_HWLP 220 +#define SRST_P_DDRPHY 221 +#define SRST_MSCH_BIU 222 +#define SRST_A_DDR_UPCTL 223 +#define SRST_DDR_UPCTL 224 +#define SRST_DDRMON 225 +#define SRST_A_DDR_SCRAMBLE 226 +#define SRST_A_SPLIT 227 +#define SRST_DDR_PHY 228 + +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi new file mode 100644 index 00000000000..ea051362fb2 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi @@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + arm { + /omit-if-no-ref/ + arm_pins: arm-pins { + rockchip,pins = + /* arm_avs */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clkm0_32k_out: clkm0-32k-out { + rockchip,pins = + /* clkm0_32k_out */ + <3 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clkm1_32k_out: clkm1-32k-out { + rockchip,pins = + /* clkm1_32k_out */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PD6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + eth_pins: eth-pins { + rockchip,pins = + /* eth_clk_25m_out */ + <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + fephy { + /omit-if-no-ref/ + fephym0_led_dpx: fephym0-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_link: fephym0-led_link { + rockchip,pins = + /* fephy_led_link_m0 */ + <4 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_spd: fephym0-led_spd { + rockchip,pins = + /* fephy_led_spd_m0 */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_dpx: fephym1-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_link: fephym1-led_link { + rockchip,pins = + /* fephy_led_link_m1 */ + <2 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_spd: fephym1-led_spd { + rockchip,pins = + /* fephy_led_spd_m1 */ + <2 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD5 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmi_pins: hdmi-pins { + rockchip,pins = + /* hdmi_tx_cec */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* hdmi_tx_hpd */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* hdmi_tx_scl */ + <0 RK_PA4 1 &pcfg_pull_none>, + /* hdmi_tx_sda */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + hsm { + /omit-if-no-ref/ + hsmm0_pins: hsmm0-pins { + rockchip,pins = + /* hsm_clk_out_m0 */ + <2 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hsmm1_pins: hsmm1-pins { + rockchip,pins = + /* hsm_clk_out_m1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <4 RK_PC4 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <4 RK_PC3 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PA1 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PA0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <4 RK_PA3 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <4 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PC5 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PC6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <1 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <1 RK_PA6 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PA0 2 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PA1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PC1 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4_xfer: i2c4-xfer { + rockchip,pins = + /* i2c4_scl */ + <2 RK_PA0 4 &pcfg_pull_none_smt>, + /* i2c4_sda */ + <2 RK_PA1 4 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <1 RK_PB2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <1 RK_PB3 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PD2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <3 RK_PB2 5 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <3 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PD4 3 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PD7 3 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7_xfer: i2c7-xfer { + rockchip,pins = + /* i2c7_scl */ + <2 RK_PA5 4 &pcfg_pull_none_smt>, + /* i2c7_sda */ + <2 RK_PA6 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi: i2s0m0-sdi { + rockchip,pins = + /* i2s0m0_sdi */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m0_sdo: i2s0m0-sdo { + rockchip,pins = + /* i2s0m0_sdo */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi: i2s0m1-sdi { + rockchip,pins = + /* i2s0m1_sdi */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m1_sdo: i2s0m1-sdo { + rockchip,pins = + /* i2s0m1_sdo */ + <1 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1_lrck: i2s1-lrck { + rockchip,pins = + /* i2s1_lrck */ + <4 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_mclk: i2s1-mclk { + rockchip,pins = + /* i2s1_mclk */ + <4 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sclk: i2s1-sclk { + rockchip,pins = + /* i2s1_sclk */ + <4 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sdi0: i2s1-sdi0 { + rockchip,pins = + /* i2s1_sdi0 */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi1: i2s1-sdi1 { + rockchip,pins = + /* i2s1_sdi1 */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi2: i2s1-sdi2 { + rockchip,pins = + /* i2s1_sdi2 */ + <4 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi3: i2s1-sdi3 { + rockchip,pins = + /* i2s1_sdi3 */ + <4 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo0: i2s1-sdo0 { + rockchip,pins = + /* i2s1_sdo0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo1: i2s1-sdo1 { + rockchip,pins = + /* i2s1_sdo1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo2: i2s1-sdo2 { + rockchip,pins = + /* i2s1_sdo2 */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo3: i2s1-sdo3 { + rockchip,pins = + /* i2s1_sdo3 */ + <4 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_tck_m0 */ + <2 RK_PA2 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m0 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* jtag_mcu_tms_m0 */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_tck_m1 */ + <4 RK_PD0 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m1 */ + <4 RK_PC7 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m1 */ + <4 RK_PD0 3 &pcfg_pull_none>, + /* jtag_mcu_tms_m1 */ + <4 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + pcie { + /omit-if-no-ref/ + pciem0_pins: pciem0-pins { + rockchip,pins = + /* pcie_clkreqn_m0 */ + <3 RK_PA6 5 &pcfg_pull_none>, + /* pcie_perstn_m0 */ + <3 RK_PB0 5 &pcfg_pull_none>, + /* pcie_waken_m0 */ + <3 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pciem1_pins: pciem1-pins { + rockchip,pins = + /* pcie_clkreqn_m1 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie_perstn_m1 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie_waken_m1 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdm_clk0: pdm-clk0 { + rockchip,pins = + /* pdm_clk0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_clk1: pdm-clk1 { + rockchip,pins = + /* pdm_clk1 */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi0: pdm-sdi0 { + rockchip,pins = + /* pdm_sdi0 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + /* pdm_sdi1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + /* pdm_sdi2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + /* pdm_sdi3 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <4 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + refm0_pins: refm0-pins { + rockchip,pins = + /* ref_clk_out_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + refm1_pins: refm1-pins { + rockchip,pins = + /* ref_clk_out_m1 */ + <3 RK_PC3 6 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmii_miim: rgmii-miim { + rockchip,pins = + /* rgmii_mdc */ + <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_mdio */ + <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rx_bus2: rgmii-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_rxd1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_rxdv_crs */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_tx_bus2: rgmii-tx_bus2 { + rockchip,pins = + /* rgmii_txd0 */ + <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd1 */ + <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txen */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_clk: rgmii-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_txclk */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_bus: rgmii-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_rxd3 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_txd2 */ + <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd3 */ + <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_clk: rgmii-clk { + rockchip,pins = + /* rgmii_clk */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmii_txer: rgmii-txer { + rockchip,pins = + /* rgmii_txer */ + <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scrm0_pins: scrm0-pins { + rockchip,pins = + /* scr_clk_m0 */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_data_m0 */ + <1 RK_PA1 3 &pcfg_pull_none>, + /* scr_detn_m0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* scr_rstn_m0 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + scrm1_pins: scrm1-pins { + rockchip,pins = + /* scr_clk_m1 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* scr_data_m1 */ + <2 RK_PA3 4 &pcfg_pull_none>, + /* scr_detn_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* scr_rstn_m1 */ + <2 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + sdio0 { + /omit-if-no-ref/ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + /* sdio0_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_clk: sdio0-clk { + rockchip,pins = + /* sdio0_clk */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_cmd: sdio0-cmd { + rockchip,pins = + /* sdio0_cmd */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_det: sdio0-det { + rockchip,pins = + /* sdio0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio0_pwren: sdio0-pwren { + rockchip,pins = + /* sdio0_pwren */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sdio1 { + /omit-if-no-ref/ + sdio1_bus4: sdio1-bus4 { + rockchip,pins = + /* sdio1_d0 */ + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d1 */ + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d2 */ + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d3 */ + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_clk: sdio1-clk { + rockchip,pins = + /* sdio1_clk */ + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_cmd: sdio1-cmd { + rockchip,pins = + /* sdio1_cmd */ + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_det: sdio1-det { + rockchip,pins = + /* sdio1_det */ + <3 RK_PB3 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio1_pwren: sdio1-pwren { + rockchip,pins = + /* sdio1_pwren */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_detn */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <4 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <4 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0_pins: spi0-pins { + rockchip,pins = + /* spi0_clk */ + <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>, + /* spi0_miso */ + <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>, + /* spi0_mosi */ + <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi0_csn0: spi0-csn0 { + rockchip,pins = + /* spi0_csn0 */ + <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi0_csn1: spi0-csn1 { + rockchip,pins = + /* spi0_csn1 */ + <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1_pins: spi1-pins { + rockchip,pins = + /* spi1_clk */ + <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* spi1_miso */ + <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>, + /* spi1_mosi */ + <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi1_csn0: spi1-csn0 { + rockchip,pins = + /* spi1_csn0 */ + <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi1_csn1: spi1-csn1 { + rockchip,pins = + /* spi1_csn1 */ + <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>; + }; + }; + + tsi0 { + /omit-if-no-ref/ + tsi0_pins: tsi0-pins { + rockchip,pins = + /* tsi0_clkin */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* tsi0_d0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* tsi0_d1 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* tsi0_d2 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* tsi0_d3 */ + <3 RK_PB7 3 &pcfg_pull_none>, + /* tsi0_d4 */ + <3 RK_PA3 3 &pcfg_pull_none>, + /* tsi0_d5 */ + <3 RK_PA2 3 &pcfg_pull_none>, + /* tsi0_d6 */ + <3 RK_PA1 3 &pcfg_pull_none>, + /* tsi0_d7 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* tsi0_fail */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* tsi0_sync */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* tsi0_valid */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + tsi1 { + /omit-if-no-ref/ + tsi1_pins: tsi1-pins { + rockchip,pins = + /* tsi1_clkin */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* tsi1_d0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* tsi1_sync */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* tsi1_valid */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <4 RK_PC7 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <4 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <2 RK_PA0 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <2 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <4 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <4 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PC6 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PC5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1_ctsn: uart1-ctsn { + rockchip,pins = + /* uart1_ctsn */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1_rtsn: uart1-rtsn { + rockchip,pins = + /* uart1_rtsn */ + <4 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <3 RK_PA0 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <3 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <3 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <1 RK_PB0 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <1 RK_PB1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB0 2 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <4 RK_PB7 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <4 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4_xfer: uart4-xfer { + rockchip,pins = + /* uart4_rx */ + <2 RK_PA2 3 &pcfg_pull_up>, + /* uart4_tx */ + <2 RK_PA3 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PA2 2 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PA3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PA6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <1 RK_PD4 2 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <1 RK_PD7 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <3 RK_PC1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6_ctsn: uart6-ctsn { + rockchip,pins = + /* uart6_ctsn */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6_rtsn: uart6-rtsn { + rockchip,pins = + /* uart6_rtsn */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <1 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts index d2cdb63d4a9..57a446b5cbd 100644 --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts @@ -6,17 +6,150 @@ */ /dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "rk3528.dtsi" / { model = "Radxa E20C"; compatible = "radxa,e20c", "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + }; + chosen { stdout-path = "serial0:1500000n8"; }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_key>; + + button-user { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "USER"; + linux,code = <BTN_1>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>; + + led-lan { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_LAN; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-sys { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-wan { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_WAN; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&pinctrl { + gpio-keys { + user_key: user-key { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + lan_led_g: lan-led-g { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_g: sys-led-g { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_g: wan-led-g { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi index e58faa985aa..26c3559d6a6 100644 --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi @@ -4,8 +4,12 @@ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> */ +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rockchip,rk3528-cru.h> +#include <dt-bindings/reset/rockchip,rk3528-cru.h> / { compatible = "rockchip,rk3528"; @@ -15,6 +19,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -51,6 +60,7 @@ reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu1: cpu@1 { @@ -58,6 +68,7 @@ reg = <0x1>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu2: cpu@2 { @@ -65,6 +76,7 @@ reg = <0x2>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu3: cpu@3 { @@ -72,6 +84,22 @@ reg = <0x3>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; }; }; @@ -80,6 +108,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -95,6 +135,13 @@ #clock-cells = <0>; }; + gmac0_clk: clock-gmac50m { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "gmac0"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; @@ -114,10 +161,219 @@ #interrupt-cells = <3>; }; + qos_crypto_a: qos@ff200000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200000 0x0 0x20>; + }; + + qos_crypto_p: qos@ff200080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200080 0x0 0x20>; + }; + + qos_dcf: qos@ff200100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200100 0x0 0x20>; + }; + + qos_dft2apb: qos@ff200200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200200 0x0 0x20>; + }; + + qos_dma2ddr: qos@ff200280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200280 0x0 0x20>; + }; + + qos_dmac: qos@ff200300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200300 0x0 0x20>; + }; + + qos_keyreader: qos@ff200380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200380 0x0 0x20>; + }; + + qos_cpu: qos@ff210000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210000 0x0 0x20>; + }; + + qos_debug: qos@ff210080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210080 0x0 0x20>; + }; + + qos_gpu_m0: qos@ff220000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220000 0x0 0x20>; + }; + + qos_gpu_m1: qos@ff220080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220080 0x0 0x20>; + }; + + qos_pmu_mcu: qos@ff240000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff240000 0x0 0x20>; + }; + + qos_rkvdec: qos@ff250000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff250000 0x0 0x20>; + }; + + qos_rkvenc: qos@ff260000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff260000 0x0 0x20>; + }; + + qos_gmac0: qos@ff270000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270000 0x0 0x20>; + }; + + qos_hdcp: qos@ff270080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270080 0x0 0x20>; + }; + + qos_jpegdec: qos@ff270100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270100 0x0 0x20>; + }; + + qos_rga2_m0ro: qos@ff270200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270200 0x0 0x20>; + }; + + qos_rga2_m0wo: qos@ff270280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270280 0x0 0x20>; + }; + + qos_sdmmc0: qos@ff270300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270300 0x0 0x20>; + }; + + qos_usb2host: qos@ff270380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270380 0x0 0x20>; + }; + + qos_vdpp: qos@ff270480 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270480 0x0 0x20>; + }; + + qos_vop: qos@ff270500 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270500 0x0 0x20>; + }; + + qos_emmc: qos@ff280000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280000 0x0 0x20>; + }; + + qos_fspi: qos@ff280080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280080 0x0 0x20>; + }; + + qos_gmac1: qos@ff280100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280100 0x0 0x20>; + }; + + qos_pcie: qos@ff280180 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280180 0x0 0x20>; + }; + + qos_sdio0: qos@ff280200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280200 0x0 0x20>; + }; + + qos_sdio1: qos@ff280280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280280 0x0 0x20>; + }; + + qos_tsp: qos@ff280300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280300 0x0 0x20>; + }; + + qos_usb3otg: qos@ff280380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280380 0x0 0x20>; + }; + + qos_vpu: qos@ff280400 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280400 0x0 0x20>; + }; + + cru: clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0x0 0xff4a0000 0x0 0x30000>; + assigned-clocks = + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>; + assigned-clock-rates = + <32768>, <1188000000>, + <1000000000>, <996000000>, + <408000000>, <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ioc_grf: syscon@ff540000 { + compatible = "rockchip,rk3528-ioc-grf", "syscon"; + reg = <0x0 0xff540000 0x0 0x40000>; + }; + uart0: serial@ff9f0000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f0000 0x0 0x100>; - clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -127,6 +383,8 @@ uart1: serial@ff9f8000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f8000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -136,6 +394,8 @@ uart2: serial@ffa00000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa00000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -144,6 +404,8 @@ uart3: serial@ffa08000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; reg = <0x0 0xffa08000 0x0 0x100>; reg-io-width = <4>; reg-shift = <2>; @@ -153,6 +415,8 @@ uart4: serial@ffa10000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa10000 0x0 0x100>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -162,6 +426,8 @@ uart5: serial@ffa18000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa18000 0x0 0x100>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -171,6 +437,8 @@ uart6: serial@ffa20000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa20000 0x0 0x100>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -180,10 +448,118 @@ uart7: serial@ffa28000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa28000 0x0 0x100>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; + + saradc: adc@ffae0000 { + compatible = "rockchip,rk3528-saradc"; + reg = <0x0 0xffae0000 0x0 0x10000>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sdhci: mmc@ffbf0000 { + compatible = "rockchip,rk3528-dwcmshc", + "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xffbf0000 0x0 0x10000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_SRC_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, + <200000000>; + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_strb>; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3528-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff610000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffaf0000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ffb00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb00000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffb10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffb20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; }; + +#include "rk3528-pinctrl.dtsi" diff --git a/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts new file mode 100644 index 00000000000..612b7bb0b74 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Firefly Technology Co. Ltd + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "rk3576.dtsi" + +/ { + model = "Firefly ROC-RK3576-PC"; + compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <17000>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <17000>; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren_h>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v0_device_s0: regulator-vcc5v0-device-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5vd_en>; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_host_pwren_h>; + regulator-name = "vcc5v0_host1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + phy-handle = <&rgmii_phy0>; + tx_delay = <0x21>; + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + /* Reset time is 20ms, 100ms for rtl8211f */ + reset-delay-us = <20000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <100000>; + }; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys_s5>; + vcc2-supply = <&vcc5v0_sys_s5>; + vcc3-supply = <&vcc5v0_sys_s5>; + vcc4-supply = <&vcc5v0_sys_s5>; + vcc5-supply = <&vcc5v0_sys_s5>; + vcc6-supply = <&vcc5v0_sys_s5>; + vcc7-supply = <&vcc5v0_sys_s5>; + vcc8-supply = <&vcc5v0_sys_s5>; + vcc9-supply = <&vcc5v0_sys_s5>; + vcc10-supply = <&vcc5v0_sys_s5>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys_s5>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys_s5>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + /* hnyetek,husb311 typec-portc@4e */ + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc5vd_en: vcc5vd-en { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + hub_reset_h: hub-reset-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb3_host_pwren_h: usb3-host-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren_h: usb-otg0-pwren-h { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int_l: usbc0-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + watchdog { + wd_en: wd-en { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>; + status = "okay"; +}; + +/* On the extension pin header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m3_xfer>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi index 4dde954043e..29b47799849 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi @@ -1260,6 +1260,45 @@ status = "disabled"; }; + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names = "otp", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpub_leakage: cpub-leakage@1e { + reg = <0x1e 0x1>; + }; + cpul_leakage: cpul-leakage@1f { + reg = <0x1f 0x1>; + }; + npu_leakage: npu-leakage@20 { + reg = <0x20 0x1>; + }; + gpu_leakage: gpu-leakage@21 { + reg = <0x21 0x1>; + }; + log_leakage: log-leakage@22 { + reg = <0x22 0x1>; + }; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi index c3abdfb04f8..2623afa7963 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi @@ -1921,6 +1921,14 @@ status = "disabled"; }; + rng@fe378000 { + compatible = "rockchip,rk3588-rng"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset 48>; + }; + i2s0_8ch: i2s@fe470000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfe470000 0x0 0x1000>; diff --git a/dts/upstream/src/mips/Makefile b/dts/upstream/src/mips/Makefile new file mode 100644 index 00000000000..9a8f6aa3584 --- /dev/null +++ b/dts/upstream/src/mips/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/scripts/Makefile.dts + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += -a 0x8 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := */*.dtb */*.dtbo diff --git a/env/Kconfig b/env/Kconfig index 4438f0b392c..9507aeed12a 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -485,7 +485,7 @@ config ENV_FAT_DEVICE_AND_PART string "Device and partition for where to store the environemt in FAT" depends on ENV_IS_IN_FAT default "0:1" if TI_COMMON_CMD_OPTIONS - default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET + default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default ":auto" if ARCH_SUNXI default "0" if ARCH_AT91 help diff --git a/fs/exfat/io.c b/fs/exfat/io.c index 81e82829c72..c56f5675987 100644 --- a/fs/exfat/io.c +++ b/fs/exfat/io.c @@ -597,15 +597,13 @@ ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node, } #ifdef __UBOOT__ +#define PATH_MAX FS_DIRENT_NAME_LEN + struct exfat_dir_stream { + char dirname[PATH_MAX]; struct fs_dir_stream fs_dirs; struct fs_dirent dirent; - - struct exfat_node* node; - struct exfat_iterator it; - /* State tracker flags for emulated . and .. dirents */ - bool dot; - bool dotdot; + int offset; }; int exfat_fs_probe(struct blk_desc *fs_dev_desc, @@ -626,8 +624,6 @@ error: return ret; } -#define PATH_MAX FS_DIRENT_NAME_LEN - /* Adapted from uclibc 1.0.35 */ static char *exfat_realpath(const char *path, char got_path[]) { @@ -721,31 +717,31 @@ int exfat_lookup_realpath(struct exfat* ef, struct exfat_node** node, int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp) { struct exfat_dir_stream *dirs; + struct exfat_node *dnode; int err; - dirs = calloc(1, sizeof(*dirs)); - if (!dirs) - return -ENOMEM; - - err = exfat_lookup_realpath(&ctxt.ef, &dirs->node, filename); + err = exfat_lookup_realpath(&ctxt.ef, &dnode, filename); if (err) - goto err_out; + return err; - if (!(dirs->node->attrib & EXFAT_ATTRIB_DIR)) { + if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) err = -ENOTDIR; - goto err_out; - } - err = exfat_opendir(&ctxt.ef, dirs->node, &dirs->it); + exfat_put_node(&ctxt.ef, dnode); + if (err) - goto err_out; + return err; + + dirs = calloc(1, sizeof(*dirs)); + if (!dirs) + return -ENOMEM; + + strcpy(dirs->dirname, filename); + dirs->offset = -1; *dirsp = &dirs->fs_dirs; return 0; -err_out: - free(dirs); - return err; } int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) @@ -753,50 +749,77 @@ int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) struct exfat_dir_stream *dirs = container_of(fs_dirs, struct exfat_dir_stream, fs_dirs); struct fs_dirent *dent = &dirs->dirent; - struct exfat_node* node; + struct exfat_node *dnode, *node; + struct exfat_iterator it; + int offset = 0; + int err; + + err = exfat_lookup_realpath(&ctxt.ef, &dnode, dirs->dirname); + if (err) + return err; + + if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) { + err = -ENOTDIR; + goto err_out; + } /* Emulate current directory ./ */ - if (!dirs->dot) { - dirs->dot = true; + if (dirs->offset == -1) { + dirs->offset++; snprintf(dent->name, FS_DIRENT_NAME_LEN, "."); dent->type = FS_DT_DIR; *dentp = dent; - return 0; + goto err_out; } /* Emulate parent directory ../ */ - if (!dirs->dotdot) { - dirs->dotdot = true; + if (dirs->offset == 0) { + dirs->offset++; snprintf(dent->name, FS_DIRENT_NAME_LEN, ".."); dent->type = FS_DT_DIR; *dentp = dent; - return 0; + goto err_out; } + err = exfat_opendir(&ctxt.ef, dnode, &it); + if (err) + goto err_out; + + *dentp = NULL; + /* Read actual directory content */ - node = exfat_readdir(&dirs->it); - if (!node) { /* No more content, reset . and .. emulation */ - dirs->dot = false; - dirs->dotdot = false; - return 1; - } + while ((node = exfat_readdir(&it))) { + if (dirs->offset != ++offset) { + exfat_put_node(&ctxt.ef, node); + continue; + } - exfat_get_name(node, dent->name); - if (node->attrib & EXFAT_ATTRIB_DIR) { - dent->type = FS_DT_DIR; - } else { - dent->type = FS_DT_REG; - dent->size = node->size; + exfat_get_name(node, dent->name); + if (node->attrib & EXFAT_ATTRIB_DIR) { + dent->type = FS_DT_DIR; + } else { + dent->type = FS_DT_REG; + dent->size = node->size; + } + exfat_put_node(&ctxt.ef, node); + *dentp = dent; + dirs->offset++; + break; } - *dentp = dent; + exfat_closedir(&ctxt.ef, &it); - return 0; +err_out: + exfat_put_node(&ctxt.ef, dnode); + return err; } void exfat_fs_closedir(struct fs_dir_stream *fs_dirs) { - free(fs_dirs); + struct exfat_dir_stream *dirs = + container_of(fs_dirs, struct exfat_dir_stream, fs_dirs); + + free(dirs); } int exfat_fs_ls(const char *dirname) @@ -852,11 +875,11 @@ int exfat_fs_exists(const char *filename) err = exfat_lookup_realpath(&ctxt.ef, &node, filename); if (err) - return err; + return 0; exfat_put_node(&ctxt.ef, node); - return 0; + return 1; } int exfat_fs_size(const char *filename, loff_t *size) @@ -898,9 +921,7 @@ int exfat_fs_read(const char *filename, void *buf, loff_t offset, loff_t len, *actread = sz; - exfat_put_node(&ctxt.ef, node); - - return exfat_flush_node(&ctxt.ef, node); + err = exfat_flush_node(&ctxt.ef, node); exit: exfat_put_node(&ctxt.ef, node); return err; @@ -992,6 +1013,11 @@ exit: return err; } +int exfat_fs_rename(const char *old_path, const char *new_path) +{ + return exfat_rename(&ctxt.ef, old_path, new_path); +} + void exfat_fs_close(void) { exfat_unmount(&ctxt.ef); diff --git a/fs/exfat/lookup.c b/fs/exfat/lookup.c index 9867aab95f3..1d9aae9e036 100644 --- a/fs/exfat/lookup.c +++ b/fs/exfat/lookup.c @@ -218,8 +218,9 @@ int exfat_split(struct exfat* ef, struct exfat_node** parent, exfat_put_node(ef, *parent); *parent = *node; } +#ifndef __UBOOT__ exfat_bug("impossible"); -#ifdef __UBOOT__ +#else return 0; #endif } @@ -401,6 +401,7 @@ static struct fstype_info fstypes[] = { .ln = fs_ln_unsupported, .unlink = exfat_fs_unlink, .mkdir = exfat_fs_mkdir, + .rename = exfat_fs_rename, }, #endif { diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 7c364686f14..2dcdd60f683 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -949,7 +949,7 @@ static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp) goto out; } - token_list = malloc(token_count * sizeof(char *)); + token_list = calloc(token_count, sizeof(char *)); if (!token_list) { ret = -EINVAL; goto out; @@ -987,9 +987,11 @@ static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp) *dirsp = (struct fs_dir_stream *)dirs; out: - for (j = 0; j < token_count; j++) - free(token_list[j]); - free(token_list); + if (token_list) { + for (j = 0; j < token_count; j++) + free(token_list[j]); + free(token_list); + } free(pos_list); free(path); if (ret) { diff --git a/include/ahci.h b/include/ahci.h index d4f0f3ce0e7..eb05cc687f6 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -137,8 +137,8 @@ struct ahci_ioports { void __iomem *port_mmio; struct ahci_cmd_hdr *cmd_slot; struct ahci_sg *cmd_tbl_sg; - ulong cmd_tbl; - u32 rx_fis; + void *cmd_tbl; + void *rx_fis; }; /** diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 19d3c72a6f1..cf43fc05025 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -138,11 +138,10 @@ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi; " \ - "if test $board_name = A335_ICE; then " \ - "setenv fdtfile am335x-icev2.dtb; " \ - "if test $ice_mii = mii; then " \ - "setenv pxe_label_override Pruss; fi;" \ - "fi; " \ + "if test $board_name = A335_ICE && test $ice_mii = rmii; then " \ + "setenv fdtfile am335x-icev2.dtb; fi; " \ + "if test $board_name = A335_ICE && test $ice_mii = mii; then " \ + "setenv fdtfile am335x-icev2-prueth.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "init_console=" \ diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 6a40bbdf3a7..1ade6adfa0b 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -105,6 +105,14 @@ #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " +#define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0) + +#define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0" + +#define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \ + "ufs " + #define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ @@ -117,11 +125,19 @@ #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ "" +#if defined(CONFIG_USB_STORAGE) +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_UFS(func) \ BOOT_TARGET_DEVICES_XSPI(func) \ BOOT_TARGET_DEVICES_DFU_USB(func) \ + BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_PXE(func) \ BOOT_TARGET_DEVICES_DHCP(func) diff --git a/include/configs/anbernic-rgxx3-rk3566.h b/include/configs/anbernic-rgxx3-rk3566.h index 3c4ea4e7d84..3d9e05a976a 100644 --- a/include/configs/anbernic-rgxx3-rk3566.h +++ b/include/configs/anbernic-rgxx3-rk3566.h @@ -3,10 +3,10 @@ #ifndef __ANBERNIC_RGXX3_RK3566_H #define __ANBERNIC_RGXX3_RK3566_H -#include <configs/rk3568_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3568_common.h> + #endif diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h new file mode 100644 index 00000000000..e2ebb2f1004 --- /dev/null +++ b/include/configs/brzynq.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BR Zynq board + * + * Copyright (C) 2024 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ + +#ifndef __CONFIG_BRZYNQ_H__ +#define __CONFIG_BRZYNQ_H__ + +/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */ +#if IS_ENABLED(CONFIG_SPL_FPGA) +#define PHY_ANEG_TIMEOUT 8000 +#endif + +/* Use top mapped SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 + +#endif /* __CONFIG_BRZYNQ_H__ */ diff --git a/include/configs/evb_rk3568.h b/include/configs/evb_rk3568.h index a0f2383bf2f..9070160cf58 100644 --- a/include/configs/evb_rk3568.h +++ b/include/configs/evb_rk3568.h @@ -6,10 +6,10 @@ #ifndef __EVB_RK3568_H #define __EVB_RK3568_H -#include <configs/rk3568_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3568_common.h> + #endif diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h index 4568e2cace6..5ff1ddbfcbe 100644 --- a/include/configs/evb_rk3588.h +++ b/include/configs/evb_rk3588.h @@ -6,10 +6,10 @@ #ifndef __EVB_RK3588_H #define __EVB_RK3588_H -#include <configs/rk3588_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3588_common.h> + #endif diff --git a/include/configs/khadas-edge2-rk3588s.h b/include/configs/khadas-edge2-rk3588s.h index d279cf3826a..fe8461d6362 100644 --- a/include/configs/khadas-edge2-rk3588s.h +++ b/include/configs/khadas-edge2-rk3588s.h @@ -6,10 +6,10 @@ #ifndef __KHADAS_EDGE2_RK3588_H #define __KHADAS_EDGE2_RK3588_H -#include <configs/rk3588_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3588_common.h> + #endif /* __KHADAS_EDGE2_RK3588_H */ diff --git a/include/configs/powkiddy-x55-rk3566.h b/include/configs/powkiddy-x55-rk3566.h index 4b25c6a8774..8ace435434f 100644 --- a/include/configs/powkiddy-x55-rk3566.h +++ b/include/configs/powkiddy-x55-rk3566.h @@ -3,10 +3,10 @@ #ifndef __POWKIDDY_X55_RK3566_H #define __POWKIDDY_X55_RK3566_H -#include <configs/rk3568_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3568_common.h> + #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 13ed9011764..d0539003fd5 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -20,6 +20,7 @@ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x08300000\0" \ + "fdtoverlay_addr_r=0x08400000\0" \ "kernel_addr_r=0x00280000\0" \ "ramdisk_addr_r=0x0a200000\0" \ "kernel_comp_addr_r=0x03e80000\0" \ diff --git a/include/configs/rk3528_common.h b/include/configs/rk3528_common.h new file mode 100644 index 00000000000..f7dc6ecd594 --- /dev/null +++ b/include/configs/rk3528_common.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __CONFIG_RK3528_COMMON_H +#define __CONFIG_RK3528_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0xfe480000 + +#define CFG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xfc000000 + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00c00000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00e00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "kernel_comp_addr_r=0x0a000000\0" \ + "fdt_addr_r=0x12000000\0" \ + "fdtoverlay_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12180000\0" \ + "kernel_comp_size=0x8000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3528_COMMON_H */ diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 09b7b71c6af..b2a35db0b94 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -15,6 +15,10 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "script_offset_f=0xffe000\0" \ @@ -29,7 +33,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" diff --git a/include/configs/rk3576_common.h b/include/configs/rk3576_common.h new file mode 100644 index 00000000000..14d1d863609 --- /dev/null +++ b/include/configs/rk3576_common.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3576_COMMON_H +#define __CONFIG_RK3576_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0x3ff80000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +/* Used by board_get_usable_ram_top(), space below the 4G address boundary */ +#define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE) + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x40c00000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x40e00000\0" \ + "kernel_addr_r=0x42000000\0" \ + "kernel_comp_addr_r=0x4a000000\0" \ + "fdt_addr_r=0x52000000\0" \ + "fdtoverlay_addr_r=0x52100000\0" \ + "ramdisk_addr_r=0x52180000\0" \ + "kernel_comp_size=0x8000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3576_COMMON_H */ diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index e6654c275ac..2f0d40deb64 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -14,6 +14,10 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "script_offset_f=0xffe000\0" \ @@ -28,7 +32,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" diff --git a/include/configs/roc-pc-rk3576.h b/include/configs/roc-pc-rk3576.h new file mode 100644 index 00000000000..77c95f0c560 --- /dev/null +++ b/include/configs/roc-pc-rk3576.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#ifndef __ROC_PC_RK3576_H +#define __ROC_PC_RK3576_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3576_common.h> + +#endif diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 06276175455..5530d36339c 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -9,75 +9,67 @@ #ifndef __CONFIG_TOPIC_MIAMI_H #define __CONFIG_TOPIC_MIAMI_H -/* Speed up boot time by ignoring the environment which we never used */ +#ifndef CONFIG_XPL_BUILD -#include "zynq-common.h" +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif -/* Fixup settings */ +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif -/* Setup proper boot sequences for Miami boards */ +#if defined(CONFIG_ZYNQ_QSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif -#if defined(CONFIG_USB_HOST) -# define EXTRA_ENV_USB \ - "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\ - "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \ - "usbboot=run usbreset && if usb start; then " \ - "echo Booting from USB... && " \ - "if load usb 0 0x1900000 ${bootscript}; then "\ - "source 0x1900000; fi; " \ - "load usb 0 ${kernel_addr} ${kernel_image} && " \ - "load usb 0 ${devicetree_addr} ${devicetree_image} && " \ - "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \ - "bootm ${kernel_addr} ${ramdisk_load_address} "\ - "${devicetree_addr}; " \ - "fi\0" - /* Note that addresses here should match the addresses in the env */ -# define DFU_ALT_INFO \ - "dfu_alt_info=" \ - "uImage ram 0x2080000 0x500000;" \ - "devicetree.dtb ram 0x2000000 0x20000;" \ - "uramdisk.image.gz ram 0x4000000 0x10000000\0" \ - "dfu_ram=run usbreset && dfu 0 ram 0\0" \ - "thor_ram=run usbreset && thordown 0 ram 0\0" +#ifdef CONFIG_CMD_UBIFS +# define BOOT_TARGET_DEVICES_UBIFS(func) func(UBIFS, ubifs, 0, qspi-rootfs, qspi-rootfs) #else -# define EXTRA_ENV_USB +# define BOOT_TARGET_DEVICES_UBIFS(func) #endif -#undef CFG_EXTRA_ENV_SETTINGS +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_UBIFS(func) \ + BOOT_TARGET_DEVICES_QSPI(func) + +#include <config_distro_bootcmd.h> + +#endif /* CONFIG_XPL_BUILD */ + +/* Default environment */ +#ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_image=uImage\0" \ - "kernel_addr=0x2080000\0" \ - "ramdisk_image=uramdisk.image.gz\0" \ - "ramdisk_load_address=0x4000000\0" \ - "devicetree_image=devicetree.dtb\0" \ - "devicetree_addr=0x2000000\0" \ - "bitstream_image=fpga.bin\0" \ - "bootscript=autorun.scr\0" \ - "loadbit_addr=0x100000\0" \ - "loadbootenv_addr=0x2000000\0" \ - "kernel_size=0x440000\0" \ - "devicetree_size=0x10000\0" \ - "boot_size=0xF00000\0" \ - "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ - "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ - "mmcinfo && " \ - "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ - "fpga load 0 ${loadbit_addr} ${filesize}\0" \ - "qspiboot=echo Booting from QSPI flash... && " \ - "sf probe && " \ - "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \ - "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \ - "bootm ${kernel_addr} - ${devicetree_addr}\0" \ - "sdboot=if mmcinfo; then " \ - "setenv bootargs console=ttyPS0,115200 " \ - "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \ - "rootwait quiet ; " \ - "load mmc 0 ${kernel_addr} ${kernel_image}&& " \ - "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \ - "bootm ${kernel_addr} - ${devicetree_addr}; " \ - "fi\0" \ - EXTRA_ENV_USB \ - DFU_ALT_INFO + "scriptaddr=0x3000000\0" \ + "script_offset_f=0xf0000\0" \ + "script_size_f=0x10000\0" \ + "fdt_addr_r=0x1f00000\0" \ + "pxefile_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "ramdisk_addr_r=0x3100000\0" \ + BOOTENV +#endif + +#include "zynq-common.h" + +/* Detect RAM size */ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #endif /* __CONFIG_TOPIC_MIAMI_H */ diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h index faa2e6c19c3..00565089676 100644 --- a/include/configs/toybrick_rk3588.h +++ b/include/configs/toybrick_rk3588.h @@ -6,10 +6,10 @@ #ifndef __TOYBRICK_RK3588_H #define __TOYBRICK_RK3588_H -#include <configs/rk3588_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3588_common.h> + #endif diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 93ae5891a07..94273d0deb9 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -46,7 +46,10 @@ #ifdef CONFIG_XPL_BUILD #define BOOTENV -#else +#endif + +/* Only use this section if no BOOTENV has been configured yet */ +#ifndef BOOTENV #ifdef CONFIG_CMD_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) @@ -167,7 +170,8 @@ BOOT_TARGET_DEVICES_DHCP(func) #include <config_distro_bootcmd.h> -#endif /* CONFIG_XPL_BUILD */ + +#endif /* BOOTENV */ /* Default environment */ #ifndef CFG_EXTRA_ENV_SETTINGS diff --git a/include/exfat.h b/include/exfat.h index 7e43beeb348..75fce5b6566 100644 --- a/include/exfat.h +++ b/include/exfat.h @@ -20,5 +20,6 @@ int exfat_fs_unlink(const char *filename); int exfat_fs_mkdir(const char *dirname); int exfat_fs_write(const char *filename, void *buf, loff_t offset, loff_t len, loff_t *actwrite); +int exfat_fs_rename(const char *old_path, const char *new_path); #endif /* _EXFAT_H */ diff --git a/include/initcall.h b/include/initcall.h index 62d3bb67f08..220a55ad84d 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -8,31 +8,34 @@ #include <asm/types.h> #include <event.h> +#include <hang.h> _Static_assert(EVT_COUNT < 256, "Can only support 256 event types with 8 bits"); -/** - * init_fnc_t - Init function - * - * Return: 0 if OK -ve on error - */ -typedef int (*init_fnc_t)(void); - -/* Top bit indicates that the initcall is an event */ -#define INITCALL_IS_EVENT GENMASK(BITS_PER_LONG - 1, 8) -#define INITCALL_EVENT_TYPE GENMASK(7, 0) - -#define INITCALL_EVENT(_type) (void *)((_type) | INITCALL_IS_EVENT) - -/** - * initcall_run_list() - Run through a list of function calls - * - * This calls functions one after the other, stopping at the first error, or - * when NULL is obtained. - * - * @init_sequence: NULL-terminated init sequence to run - * Return: 0 if OK, or -ve error code from the first failure - */ -int initcall_run_list(const init_fnc_t init_sequence[]); +#define INITCALL(_call) \ + do { \ + if (_call()) { \ + printf("%s(): initcall %s() failed\n", __func__, \ + #_call); \ + hang(); \ + } \ + } while (0) + +#define INITCALL_EVT(_evt) \ + do { \ + if (event_notify_null(_evt)) { \ + printf("%s(): event %d/%s failed\n", __func__, _evt, \ + event_type_name(_evt)) ; \ + hang(); \ + } \ + } while (0) + +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) +#define WATCHDOG_INIT() INITCALL(init_func_watchdog_init) +#define WATCHDOG_RESET() INITCALL(init_func_watchdog_reset) +#else +#define WATCHDOG_INIT() +#define WATCHDOG_RESET() +#endif #endif diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index a54eff43add..6455335bae4 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef __INTEL_SMC_H @@ -482,10 +483,16 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * Call register usage: * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES * a1 Set bridges status: - * 0 - Disable - * 1 - Enable - * a2-7 not used - * + * Bit 0: 0 - Disable, 1 - Enable + * Bit 1: 1 - Has mask value in a2 + * a2 Mask value + * Bit 0: soc2fpga + * Bit 1: lwhps2fpga + * Bit 2: fpga2soc + * Bit 3: f2sdram0 (For Stratix 10 only) + * Bit 4: f2sdram1 (For Stratix 10 only) + * Bit 5: f2sdram2 (For Stratix 10 only) + * a3-7 not used * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 13b5a52f8b9..6fe6fd520a4 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -17,7 +17,7 @@ #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #else -#include <spi.h> +#include <linux/bitops.h> #include <spi-mem.h> #include <linux/mtd/nand.h> #endif diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 8e4c43cef31..aa4d105ee98 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -143,7 +143,7 @@ struct ti_sci_dev_ops { u32 reset_state); int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id, u32 *reset_state); - int (*release_exclusive_devices)(const struct ti_sci_handle *handle); + int (*release_exclusive_devices)(void); }; /** diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index c7927df15aa..fe79bf64a0e 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -179,6 +179,7 @@ struct usb_ep { const struct usb_ep_ops *ops; struct list_head ep_list; struct usb_ep_caps caps; + bool enabled; unsigned maxpacket:16; unsigned maxpacket_limit:16; unsigned max_streams:16; @@ -230,7 +231,18 @@ static inline void usb_ep_set_maxpacket_limit(struct usb_ep *ep, static inline int usb_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc) { - return ep->ops->enable(ep, desc); + int ret; + + if (ep->enabled) + return 0; + + ret = ep->ops->enable(ep, desc); + if (ret) + return ret; + + ep->enabled = true; + + return 0; } /** @@ -247,7 +259,18 @@ static inline int usb_ep_enable(struct usb_ep *ep, */ static inline int usb_ep_disable(struct usb_ep *ep) { - return ep->ops->disable(ep); + int ret; + + if (!ep->enabled) + return 0; + + ret = ep->ops->disable(ep); + if (ret) + return ret; + + ep->enabled = false; + + return 0; } /** diff --git a/include/mmc.h b/include/mmc.h index 52cacfd0eab..eead666ae44 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -494,6 +494,14 @@ struct dm_mmc_ops { int (*set_ios)(struct udevice *dev); /** + * send_init_stream() - send the initialization stream: 74 clock cycles + * This is used after power up before sending the first command + * + * @dev: Device to update + */ + void (*send_init_stream)(struct udevice *dev); + + /** * get_cd() - See whether a card is present * * @dev: Device to check @@ -572,6 +580,7 @@ struct dm_mmc_ops { /* Transition functions for compatibility */ int mmc_set_ios(struct mmc *mmc); +void mmc_send_init_stream(struct mmc *mmc); int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); int mmc_execute_tuning(struct mmc *mmc, uint opcode); diff --git a/include/net-common.h b/include/net-common.h index 30860f5975a..e536968a92b 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -471,6 +471,9 @@ static inline struct in_addr env_get_ip(char *var) int net_init(void); +/* Called when a network operation fails to know if it should be re-tried */ +int net_start_again(void); + /* NET compatibility */ enum proto_t; int net_loop(enum proto_t protocol); @@ -490,6 +493,18 @@ int net_loop(enum proto_t protocol); */ int dhcp_run(ulong addr, const char *fname, bool autoload); + +/** + * do_ping - Run the ping command + * + * @cmdtp: Unused + * @flag: Command flags (CMD_FLAG_...) + * @argc: Number of arguments + * @argv: List of arguments + * Return: result (see enum command_ret_t) + */ +int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); + /** * do_tftpb - Run the tftpboot command * diff --git a/include/net-legacy.h b/include/net-legacy.h index bc0f0cde9fe..51780999a88 100644 --- a/include/net-legacy.h +++ b/include/net-legacy.h @@ -347,9 +347,6 @@ extern int net_ntp_time_offset; /* offset time from UTC */ int net_loop(enum proto_t); -/* Load failed. Start again. */ -int net_start_again(void); - /* Get size of the ethernet header when we send */ int net_eth_hdr_size(void); diff --git a/include/net-lwip.h b/include/net-lwip.h index 64e5c720560..b762956e8fd 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -10,7 +10,14 @@ enum proto_t { TFTPGET }; -void net_lwip_set_current(void); +static inline int eth_is_on_demand_init(void) +{ + return 1; +} + +int eth_init_state_only(void); /* Set active state */ + +int net_lwip_eth_start(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); @@ -27,7 +34,6 @@ bool wget_validate_uri(char *uri); int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); -int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); #endif /* __NET_LWIP_H__ */ diff --git a/include/net6.h b/include/net6.h index 1ed989e584a..2ceeaba0639 100644 --- a/include/net6.h +++ b/include/net6.h @@ -90,6 +90,16 @@ struct udp_hdr { 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x02 } } } +/* + * With IPv6, the broadcast MAC address is not used. Instead, it should use + * the multicast address (see RFC RFC2464 section 7) + */ +#define IPV6_ALL_NODE_ETH_ADDR(_ip6_addr) {0x33, \ + 0x33, \ + _ip6_addr.in6_u.u6_addr8[12], \ + _ip6_addr.in6_u.u6_addr8[13], \ + _ip6_addr.in6_u.u6_addr8[14], \ + _ip6_addr.in6_u.u6_addr8[15]} #define IPV6_LINK_LOCAL_PREFIX 0xfe80 #define IPV6_LINK_LOCAL_MASK 0xffb0 /* The first 10-bit of address mask. */ diff --git a/include/power-domain.h b/include/power-domain.h index ad33dea76ce..18525073e5e 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -147,82 +147,38 @@ static inline int power_domain_free(struct power_domain *power_domain) #endif /** - * power_domain_on_lowlevel - Enable power to a power domain (with refcounting) + * power_domain_on - Enable power to a power domain. * * @power_domain: A power domain struct that was previously successfully * requested by power_domain_get(). - * Return: 0 if the transition has been performed correctly, - * -EALREADY if the domain is already on, - * a negative error code otherwise. + * Return: 0 if OK, or a negative error code. */ #if CONFIG_IS_ENABLED(POWER_DOMAIN) -int power_domain_on_lowlevel(struct power_domain *power_domain); +int power_domain_on(struct power_domain *power_domain); #else -static inline int power_domain_on_lowlevel(struct power_domain *power_domain) +static inline int power_domain_on(struct power_domain *power_domain) { return -ENOSYS; } #endif /** - * power_domain_on - Enable power to a power domain (ignores the actual state - * of the power domain) - * - * @power_domain: A power domain struct that was previously successfully - * requested by power_domain_get(). - * Return: a negative error code upon error during the transition, 0 otherwise. - */ -static inline int power_domain_on(struct power_domain *power_domain) -{ - int ret; - - ret = power_domain_on_lowlevel(power_domain); - if (ret == -EALREADY) - ret = 0; - - return ret; -} - -/** - * power_domain_off_lowlevel - Disable power to a power domain (with refcounting) + * power_domain_off - Disable power to a power domain. * * @power_domain: A power domain struct that was previously successfully * requested by power_domain_get(). - * Return: 0 if the transition has been performed correctly, - * -EALREADY if the domain is already off, - * -EBUSY if another device is keeping the domain on (but the refcounter - * is decremented), - * a negative error code otherwise. + * Return: 0 if OK, or a negative error code. */ #if CONFIG_IS_ENABLED(POWER_DOMAIN) -int power_domain_off_lowlevel(struct power_domain *power_domain); +int power_domain_off(struct power_domain *power_domain); #else -static inline int power_domain_off_lowlevel(struct power_domain *power_domain) +static inline int power_domain_off(struct power_domain *power_domain) { return -ENOSYS; } #endif /** - * power_domain_off - Disable power to a power domain (ignores the actual state - * of the power domain) - * - * @power_domain: A power domain struct that was previously successfully - * requested by power_domain_get(). - * Return: a negative error code upon error during the transition, 0 otherwise. - */ -static inline int power_domain_off(struct power_domain *power_domain) -{ - int ret; - - ret = power_domain_off_lowlevel(power_domain); - if (ret == -EALREADY || ret == -EBUSY) - ret = 0; - - return ret; -} - -/** * dev_power_domain_on - Enable power domains for a device . * * @dev: The client device. diff --git a/include/regmap.h b/include/regmap.h index 22b043408ac..8c6f7c1c9b1 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -362,6 +362,34 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val); /** + * regmap_set_bits() - Set bits to a regmap + * + * @map: Regmap to write bits to + * @offset: Offset in the regmap to write to + * @bits: Bits to set to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +static inline int regmap_set_bits(struct regmap *map, uint offset, uint bits) +{ + return regmap_update_bits(map, offset, bits, bits); +} + +/** + * regmap_clear_bits() - Clear bits to a regmap + * + * @map: Regmap to write bits to + * @offset: Offset in the regmap to write to + * @bits: Bits to clear to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +static inline int regmap_clear_bits(struct regmap *map, uint offset, uint bits) +{ + return regmap_update_bits(map, offset, bits, 0); +} + +/** * regmap_init_mem() - Set up a new register map that uses memory access * * @node: Device node that uses this map diff --git a/include/sdhci.h b/include/sdhci.h index 31a49ca6a2f..2372697b743 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -518,6 +518,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host); /* Export the operations to drivers */ int sdhci_probe(struct udevice *dev); int sdhci_set_clock(struct mmc *mmc, unsigned int clock); +void sdhci_set_voltage(struct sdhci_host *host); /** * sdhci_set_control_reg - Set control registers diff --git a/include/setjmp.h b/include/setjmp.h index 37d3a8af85d..32dd48803e9 100644 --- a/include/setjmp.h +++ b/include/setjmp.h @@ -3,12 +3,27 @@ #ifndef _SETJMP_H_ #define _SETJMP_H_ 1 +/** + * DOC: Overview + * + * The long jump API allows to perform nonlocal gotos, that is jump from one + * function to another typically further down in the stack, while properly + * restoring the stack's state (unwinding). The two functions needed to do this + * are setjmp() and longjmp(). + * + * In addition to these two standard POSIX.1-2001/C89 functions, a third one is + * present in U-Boot: initjmp(). It is an extension which allows to implement + * user-mode threads. + */ + #ifdef CONFIG_HAVE_SETJMP #include <asm/setjmp.h> #else struct jmp_buf_data { }; #endif +#include <linux/compiler_attributes.h> +#include <stddef.h> /** * typedef jmp_buf - information needed to restore a calling environment @@ -37,4 +52,21 @@ int setjmp(jmp_buf env); */ void longjmp(jmp_buf env, int val); +/** + * initjmp() - prepare for a long jump to a given function with a given stack + * + * This function sets up a jump buffer for later use with longjmp(). It allows + * to branch to a specific function with a specific stack. Please note that + * @func MUST NOT return. It shall typically restore the main stack and resume + * execution by doing a long jump to a jump buffer initialized by setjmp() + * before the long jump. initjmp() allows to implement multithreading. + * + * @env: jump buffer + * @func: function to be called on longjmp(), MUST NOT RETURN + * @stack_base: the stack to be used by @func (lower address) + * @stack_sz: the stack size in bytes + */ +int initjmp(jmp_buf env, void __noreturn (*func)(void), void *stack_base, + size_t stack_sz); + #endif /* _SETJMP_H_ */ diff --git a/include/spi.h b/include/spi.h index 6944773b596..2783200d663 100644 --- a/include/spi.h +++ b/include/spi.h @@ -11,6 +11,8 @@ #include <linux/bitops.h> +struct spinand_info; + /* SPI mode flags */ #define SPI_CPHA BIT(0) /* clock phase (1 = SPI_CLOCK_PHASE_SECOND) */ #define SPI_CPOL BIT(1) /* clock polarity (1 = SPI_POLARITY_HIGH) */ @@ -537,6 +539,16 @@ struct dm_spi_ops { */ int (*get_mmap)(struct udevice *dev, ulong *map_basep, uint *map_sizep, uint *offsetp); + + /** + * setup_for_spinand() - Setup the SPI for attached SPI NAND + * + * @dev: The SPI flash slave device + * @spinand_info: The SPI NAND info to configure for + * @return 0 if OK, -ve value on error + */ + int (*setup_for_spinand)(struct spi_slave *slave, + const struct spinand_info *spinand_info); }; struct dm_spi_emul_ops { diff --git a/include/u-boot/schedule.h b/include/u-boot/schedule.h index 4fd34c41229..4605971fdcb 100644 --- a/include/u-boot/schedule.h +++ b/include/u-boot/schedule.h @@ -3,6 +3,8 @@ #ifndef _U_BOOT_SCHEDULE_H #define _U_BOOT_SCHEDULE_H +#include <uthread.h> + #if CONFIG_IS_ENABLED(CYCLIC) /** * schedule() - Schedule all potentially waiting tasks @@ -17,6 +19,7 @@ void schedule(void); static inline void schedule(void) { + uthread_schedule(); } #endif diff --git a/include/uthread.h b/include/uthread.h new file mode 100644 index 00000000000..89fa552a6f6 --- /dev/null +++ b/include/uthread.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Linaro Limited + */ + +#include <linux/list.h> +#include <linux/types.h> +#include <setjmp.h> + +#ifndef _UTHREAD_H_ +#define _UTHREAD_H_ + +/** + * DOC: Overview + * + * The uthread framework is a basic task scheduler that allows to run functions + * "in parallel" on a single CPU core. The scheduling is cooperative, not + * preemptive -- meaning that context switches from one task to another task is + * voluntary, via a call to uthread_schedule(). This characteristic makes thread + * synchronization much easier, because a thread cannot be interrupted in the + * middle of a critical section (reading from or writing to shared state, for + * instance). + * + * CONFIG_UTHREAD in lib/Kconfig enables the uthread framework. When disabled, + * the uthread_create() and uthread_schedule() functions may still be used so + * that code differences between uthreads enabled and disabled can be reduced to + * a minimum. + */ + +/** + * struct uthread - a thread object + * + * @fn: thread entry point + * @arg: argument passed to the entry point when the thread is started + * @ctx: context to resume execution of this thread (via longjmp()) + * @stack: initial stack pointer for the thread + * @done: true once @fn has returned, false otherwise + * @grp_id: user-supplied identifier for this thread and possibly others. A + * thread can belong to zero or one group (not more), and a group may contain + * any number of threads. + * @list: link in the global scheduler list + */ +struct uthread { + void (*fn)(void *arg); + void *arg; + jmp_buf ctx; + void *stack; + bool done; + unsigned int grp_id; + struct list_head list; +}; + +/** + * Internal state of a struct uthread_mutex + */ +enum uthread_mutex_state { + UTHREAD_MUTEX_UNLOCKED = 0, + UTHREAD_MUTEX_LOCKED = 1 +}; + +/** + * Uthread mutex + */ +struct uthread_mutex { + enum uthread_mutex_state state; +}; + +#define UTHREAD_MUTEX_INITIALIZER { .state = UTHREAD_MUTEX_UNLOCKED } + +#ifdef CONFIG_UTHREAD + +/** + * uthread_create() - Create a uthread object and make it ready for execution + * + * Threads are automatically deleted when they return from their entry point. + * + * @uthr: a pointer to a user-allocated uthread structure to store information + * about the new thread, or NULL to let the framework allocate and manage its + * own structure. + * @fn: the thread's entry point + * @arg: argument passed to the thread's entry point + * @stack_sz: stack size for the new thread (in bytes). The stack is allocated + * on the heap. + * @grp_id: an optional thread group ID that the new thread should belong to + * (zero for no group) + */ +int uthread_create(struct uthread *uthr, void (*fn)(void *), void *arg, + size_t stack_sz, unsigned int grp_id); +/** + * uthread_schedule() - yield the CPU to the next runnable thread + * + * This function is called either by the main thread or any secondary thread + * (that is, any thread created via uthread_create()) to switch execution to + * the next runnable thread. + * + * Return: true if a thread was scheduled, false if no runnable thread was found + */ +bool uthread_schedule(void); +/** + * uthread_grp_new_id() - return a new ID for a thread group + * + * Return: the new thread group ID + */ +unsigned int uthread_grp_new_id(void); +/** + * uthread_grp_done() - test if all threads in a group are done + * + * @grp_id: the ID of the thread group that should be considered + * Return: false if the group contains at least one runnable thread (i.e., one + * thread which entry point has not returned yet), true otherwise + */ +bool uthread_grp_done(unsigned int grp_id); + +/** + * uthread_mutex_lock() - lock a mutex + * + * If the cwmutexlock is available (i.e., not owned by any other thread), then + * it is locked for use by the current thread. Otherwise the current thread + * blocks: it enters a wait loop by scheduling other threads until the mutex + * becomes unlocked. + * + * @mutex: pointer to the mutex to lock + * Return: 0 on success, in which case the lock is owned by the calling thread. + * != 0 otherwise (the lock is not owned by the calling thread). + */ +int uthread_mutex_lock(struct uthread_mutex *mutex); + +/** + * uthread_mutex_trylock() - lock a mutex if not currently locked + * + * Similar to uthread_mutex_lock() except return immediately if the mutex is + * locked already. + * + * @mutex: pointer to the mutex to lock + * Return: 0 on success, in which case the lock is owned by the calling thread. + * EBUSY if the mutex is already locked by another thread. Any other non-zero + * value on error. + */ +int uthread_mutex_trylock(struct uthread_mutex *mutex); + +/** + * uthread_mutex_unlock() - unlock a mutex + * + * The mutex is assumed to be owned by the calling thread on entry. On exit, it + * is unlocked. + * + * @mutex: pointer to the mutex to unlock + * Return: 0 on success, != 0 on error + */ +int uthread_mutex_unlock(struct uthread_mutex *mutex); + +#else + +static inline int uthread_create(struct uthread *uthr, void (*fn)(void *), + void *arg, size_t stack_sz, + unsigned int grp_id) +{ + fn(arg); + return 0; +} + +static inline bool uthread_schedule(void) +{ + return false; +} + +static inline unsigned int uthread_grp_new_id(void) +{ + return 0; +} + +static inline bool uthread_grp_done(unsigned int grp_id) +{ + return true; +} + +/* These are macros for convenience on the caller side */ +#define uthread_mutex_lock(_mutex) ({ 0; }) +#define uthread_mutex_trylock(_mutex) ({ 0 }) +#define uthread_mutex_unlock(_mutex) ({ 0; }) + +#endif /* CONFIG_UTHREAD */ +#endif /* _UTHREAD_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index e4e29797988..c54d6dc1453 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -34,6 +34,8 @@ typedef enum { /* typedef xilinx_family */ xilinx_zynq, /* Zynq Family */ xilinx_zynqmp, /* ZynqMP Family */ xilinx_versal, /* Versal Family */ + xilinx_versal_net, /* Versal NET Family */ + xilinx_versal2, /* Versal Gen 2 Family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 73198a6a6ea..dc06abc52fc 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -457,6 +457,12 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_pm_feature(const u32 api_id); +u32 zynqmp_pm_get_bootmode_reg(void); +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); +int zynqmp_pm_ufs_sram_csr_read(u32 *value); +int zynqmp_pm_ufs_sram_csr_write(u32 *value); +int zynqmp_pm_ufs_cal_reg(u32 *value); +u32 zynqmp_pm_get_pmc_multi_boot_reg(void); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U @@ -500,4 +506,10 @@ struct zynqmp_ipi_msg { u32 *buf; }; +#define CRP_BOOT_MODE_REG_NODE 0x30000001 +#define CRP_BOOT_MODE_REG_OFFSET 0x200 + +#define PM_REG_PMC_GLOBAL_NODE 0x30000004 +#define PMC_MULTI_BOOT_MODE_REG_OFFSET 0x4 + #endif /* _ZYNQMP_FIRMWARE_H_ */ diff --git a/lib/Kconfig b/lib/Kconfig index ac34ec45bb1..b2aecd8a49e 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1258,6 +1258,27 @@ config PHANDLE_CHECK_SEQ enable this config option to distinguish them using phandles in fdtdec_get_alias_seq() function. +config UTHREAD + bool "Enable thread support" + depends on HAVE_INITJMP + help + Implement a simple form of cooperative multi-tasking based on + context-switching via initjmp(), setjmp() and longjmp(). The + uthread_ interface enables the main thread of execution to create + one or more secondary threads and schedule them until they all have + returned. At any point a thread may suspend its execution and + schedule another thread, which allows for the efficient multiplexing + of leghthy operations. + +config UTHREAD_STACK_SIZE + int "Default uthread stack size" + depends on UTHREAD + default 32768 + help + The default stack size for uthreads. Each uthread has its own stack. + When the stack_sz argument to uthread_create() is zero then this + value is used. + endmenu source "lib/fwu_updates/Kconfig" diff --git a/lib/Makefile b/lib/Makefile index 24876bc2622..18ae0cd87bf 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -43,7 +43,6 @@ endif obj-$(CONFIG_SMBIOS_PARSER) += smbios-parser.o obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o -obj-y += initcall.o obj-y += ldiv.o obj-$(CONFIG_XXHASH) += xxhash.o obj-y += net_utils.o @@ -160,6 +159,8 @@ obj-$(CONFIG_LIB_ELF) += elf.o obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_UTHREAD) += uthread.o + # # Build a fast OID lookup registry from include/linux/oid_registry.h # diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 17fbfad116f..d78bf7d6191 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -51,6 +51,7 @@ efi_selftest_variables_runtime.o \ efi_selftest_watchdog.o obj-$(CONFIG_EFI_ECPT) += efi_selftest_ecpt.o +obj-$(CONFIG_ARM64) += efi_selftest_el.o obj-$(CONFIG_NETDEVICES) += efi_selftest_snp.o obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_http.o obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_ipconfig.o diff --git a/lib/efi_selftest/efi_selftest_el.c b/lib/efi_selftest/efi_selftest_el.c new file mode 100644 index 00000000000..f9941caf22d --- /dev/null +++ b/lib/efi_selftest/efi_selftest_el.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Check current exception level on ARMv8. + */ +#include <efi_loader.h> +#include <efi_selftest.h> + +/** + * current_exception_level() + * + * Return: current exception level, 0 - 3 + */ +static unsigned int current_exception_level(void) +{ + unsigned long el; + + asm volatile ( + "MRS %0, CurrentEL" + : "=r" (el) : : ); + + return (el >> 2) & 0x3; +} + +/** + * execute() - execute test + * + * Check that the exception level is not EL3. + */ +static int execute(void) +{ + unsigned int el = current_exception_level(); + + efi_st_printf("Exception level EL%u\n", el); + if (el != 1 && el != 2) { + efi_st_error("EL1 or EL2 expected"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(el) = { + .name = "exception level", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .execute = execute, +}; diff --git a/lib/initcall.c b/lib/initcall.c deleted file mode 100644 index 2686b9aed5c..00000000000 --- a/lib/initcall.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2013 The Chromium OS Authors. - */ - -#include <efi.h> -#include <initcall.h> -#include <log.h> -#include <relocate.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -static ulong calc_reloc_ofs(void) -{ -#ifdef CONFIG_EFI_APP - return (ulong)image_base; -#endif - /* - * Sandbox is relocated by the OS, so symbols always appear at - * the relocated address. - */ - if (IS_ENABLED(CONFIG_SANDBOX) || (gd->flags & GD_FLG_RELOC)) - return gd->reloc_off; - - return 0; -} - -/** - * initcall_is_event() - Get the event number for an initcall - * - * func: Function pointer to check - * Return: Event number, if this is an event, else 0 - */ -static int initcall_is_event(init_fnc_t func) -{ - ulong val = (ulong)func; - - if ((val & INITCALL_IS_EVENT) == INITCALL_IS_EVENT) - return val & INITCALL_EVENT_TYPE; - - return 0; -} - -/* - * To enable debugging. add #define DEBUG at the top of the including file. - * - * To find a symbol, use grep on u-boot.map - */ -int initcall_run_list(const init_fnc_t init_sequence[]) -{ - ulong reloc_ofs; - const init_fnc_t *ptr; - enum event_t type; - init_fnc_t func; - int ret = 0; - - for (ptr = init_sequence; func = *ptr, func; ptr++) { - reloc_ofs = calc_reloc_ofs(); - type = initcall_is_event(func); - - if (type) { - if (!CONFIG_IS_ENABLED(EVENT)) - continue; - debug("initcall: event %d/%s\n", type, - event_type_name(type)); - } else if (reloc_ofs) { - debug("initcall: %p (relocated to %p)\n", - (char *)func - reloc_ofs, (char *)func); - } else { - debug("initcall: %p\n", (char *)func - reloc_ofs); - } - - ret = type ? event_notify_null(type) : func(); - if (ret) - break; - } - - if (ret) { - if (CONFIG_IS_ENABLED(EVENT)) { - char buf[60]; - - /* don't worry about buf size as we are dying here */ - if (type) { - sprintf(buf, "event %d/%s", type, - event_type_name(type)); - } else { - sprintf(buf, "call %p", - (char *)func - reloc_ofs); - } - - printf("initcall failed at %s (err=%dE)\n", buf, ret); - } else { - printf("initcall failed at call %p (err=%d)\n", - (char *)func - reloc_ofs, ret); - } - - return ret; - } - - return 0; -} diff --git a/lib/smbios.c b/lib/smbios.c index 7c9701a57f9..b8c2846277a 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -950,7 +950,7 @@ ulong write_smbios_table(ulong addr) ctx.subnode_name = NULL; if (method->subnode_name) { ctx.subnode_name = method->subnode_name; - if (IS_ENABLED(CONFIG_OF_CONTROL)) + if (ofnode_valid(parent_node)) ctx.node = ofnode_find_subnode(parent_node, method->subnode_name); } diff --git a/lib/time.c b/lib/time.c index d88edafb196..0e9b079f9cf 100644 --- a/lib/time.c +++ b/lib/time.c @@ -17,6 +17,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <linux/delay.h> +#include <uthread.h> #ifndef CFG_WD_PERIOD # define CFG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */ @@ -197,7 +198,13 @@ void udelay(unsigned long usec) do { schedule(); kv = usec > CFG_WD_PERIOD ? CFG_WD_PERIOD : usec; - __udelay(kv); + if (CONFIG_IS_ENABLED(UTHREAD)) { + ulong t0 = timer_get_us(); + while (timer_get_us() - t0 < kv) + uthread_schedule(); + } else { + __udelay(kv); + } usec -= kv; } while(usec); } diff --git a/lib/uthread.c b/lib/uthread.c new file mode 100644 index 00000000000..062fca7d209 --- /dev/null +++ b/lib/uthread.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + * Copyright (C) 2025 Linaro Limited + * + * An implementation of cooperative multi-tasking inspired from barebox threads + * https://github.com/barebox/barebox/blob/master/common/bthread.c + */ + +#include <compiler.h> +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <malloc.h> +#include <setjmp.h> +#include <stdint.h> +#include <uthread.h> + +static struct uthread main_thread = { + .list = LIST_HEAD_INIT(main_thread.list), +}; + +static struct uthread *current = &main_thread; + +/** + * uthread_trampoline() - Call the current thread's entry point then resume the + * main thread. + * + * This is a helper function which is used as the @func argument to the + * initjmp() function, and ultimately invoked via setjmp(). It does not return + * but instead longjmp()'s back to the main thread. + */ +static void __noreturn uthread_trampoline(void) +{ + struct uthread *curr = current; + + curr->fn(curr->arg); + curr->done = true; + current = &main_thread; + longjmp(current->ctx, 1); + /* Not reached */ + while (true) + ; +} + +/** + * uthread_free() - Free memory used by a uthread object. + */ +static void uthread_free(struct uthread *uthread) +{ + if (!uthread) + return; + free(uthread->stack); + free(uthread); +} + +int uthread_create(struct uthread *uthr, void (*fn)(void *), void *arg, + size_t stack_sz, unsigned int grp_id) +{ + bool user_allocated = false; + + if (!stack_sz) + stack_sz = CONFIG_UTHREAD_STACK_SIZE; + + if (uthr) { + user_allocated = true; + } else { + uthr = calloc(1, sizeof(*uthr)); + if (!uthr) + return -1; + } + + uthr->stack = memalign(16, stack_sz); + if (!uthr->stack) + goto err; + + uthr->fn = fn; + uthr->arg = arg; + uthr->grp_id = grp_id; + + list_add_tail(&uthr->list, ¤t->list); + + initjmp(uthr->ctx, uthread_trampoline, uthr->stack, stack_sz); + + return 0; +err: + if (!user_allocated) + free(uthr); + return -1; +} + +/** + * uthread_resume() - switch execution to a given thread + * + * @uthread: the thread object that should be resumed + */ +static void uthread_resume(struct uthread *uthread) +{ + if (!setjmp(current->ctx)) { + current = uthread; + longjmp(uthread->ctx, 1); + } +} + +bool uthread_schedule(void) +{ + struct uthread *next; + struct uthread *tmp; + + list_for_each_entry_safe(next, tmp, ¤t->list, list) { + if (!next->done) { + uthread_resume(next); + return true; + } + /* Found a 'done' thread, free its resources */ + list_del(&next->list); + uthread_free(next); + } + return false; +} + +unsigned int uthread_grp_new_id(void) +{ + static unsigned int id; + + return ++id; +} + +bool uthread_grp_done(unsigned int grp_id) +{ + struct uthread *next; + + list_for_each_entry(next, &main_thread.list, list) { + if (next->grp_id == grp_id && !next->done) + return false; + } + + return true; +} + +int uthread_mutex_lock(struct uthread_mutex *mutex) +{ + while (mutex->state == UTHREAD_MUTEX_LOCKED) + uthread_schedule(); + + mutex->state = UTHREAD_MUTEX_LOCKED; + return 0; +} + +int uthread_mutex_trylock(struct uthread_mutex *mutex) +{ + if (mutex->state == UTHREAD_MUTEX_UNLOCKED) { + mutex->state = UTHREAD_MUTEX_LOCKED; + return 0; + } + + return -EBUSY; +} + +int uthread_mutex_unlock(struct uthread_mutex *mutex) +{ + mutex->state = UTHREAD_MUTEX_UNLOCKED; + + return 0; +} diff --git a/lib/uuid.c b/lib/uuid.c index 75658778044..6abbcf27b1f 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -67,8 +67,11 @@ static const struct { efi_guid_t guid; } list_guid[] = { #ifndef USE_HOSTCC +#if defined(CONFIG_PARTITION_TYPE_GUID) || defined(CONFIG_CMD_EFIDEBUG) || \ + defined(CONFIG_EFI) + {"EFI System Partition", PARTITION_SYSTEM_GUID}, +#endif #ifdef CONFIG_PARTITION_TYPE_GUID - {"system", PARTITION_SYSTEM_GUID}, {"mbr", LEGACY_MBR_PARTITION_GUID}, {"msft", PARTITION_MSFT_RESERVED_GUID}, {"data", PARTITION_BASIC_DATA_GUID}, @@ -182,10 +185,6 @@ static const struct { { "TCG2", EFI_TCG2_PROTOCOL_GUID, - }, - { - "System Partition", - PARTITION_SYSTEM_GUID }, { "Firmware Management", diff --git a/net/Makefile b/net/Makefile index 41edbacabc9..d63f62b7c8a 100644 --- a/net/Makefile +++ b/net/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_NET) += arp.o obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o obj-$(CONFIG_CMD_DNS) += dns.o -obj-$(CONFIG_DM_DSA) += dsa-uclass.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_IPV6) += ndisc.o obj-$(CONFIG_$(PHASE_)DM_ETH) += net.o @@ -39,6 +38,7 @@ CFLAGS_eth_common.o += -Wno-format-extra-args endif ifeq ($(filter y,$(CONFIG_NET) $(CONFIG_NET_LWIP)),y) +obj-$(CONFIG_DM_DSA) += dsa-uclass.o obj-$(CONFIG_$(PHASE_)DM_ETH) += eth-uclass.o obj-$(CONFIG_$(PHASE_)BOOTDEV_ETH) += eth_bootdev.o obj-$(CONFIG_DM_MDIO) += mdio-uclass.o diff --git a/net/dhcpv6.c b/net/dhcpv6.c index 54619ee6983..0c2de75ba1d 100644 --- a/net/dhcpv6.c +++ b/net/dhcpv6.c @@ -29,6 +29,10 @@ int updated_sol_max_rt_ms = SOL_MAX_RT_MS; /* state machine parameters/variables */ struct dhcp6_sm_params sm_params; +/* DHCPv6 all server IP6 address */ +const struct in6_addr dhcp_mcast_ip6 = DHCP6_MULTICAST_ADDR; +/* IPv6 multicast ethernet address */ +const u8 net_dhcp6_mcast_ethaddr[6] = IPV6_ALL_NODE_ETH_ADDR(dhcp_mcast_ip6); static void dhcp6_state_machine(bool timeout, uchar *rx_pkt, unsigned int len); @@ -171,7 +175,6 @@ static int dhcp6_add_option(int option_id, uchar *pkt) */ static void dhcp6_send_solicit_packet(void) { - struct in6_addr dhcp_bcast_ip6; int len = 0; uchar *pkt; uchar *dhcp_pkt_start_ptr; @@ -200,9 +203,8 @@ static void dhcp6_send_solicit_packet(void) len = pkt - dhcp_pkt_start_ptr; /* send UDP packet to DHCP6 multicast address */ - string_to_ip6(DHCP6_MULTICAST_ADDR, sizeof(DHCP6_MULTICAST_ADDR), &dhcp_bcast_ip6); net_set_udp_handler(dhcp6_handler); - net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6, + net_send_udp_packet6((uchar *)net_dhcp6_mcast_ethaddr, (struct in6_addr *)&dhcp_mcast_ip6, PORT_DHCP6_S, PORT_DHCP6_C, len); } @@ -218,7 +220,6 @@ static void dhcp6_send_solicit_packet(void) */ static void dhcp6_send_request_packet(void) { - struct in6_addr dhcp_bcast_ip6; int len = 0; uchar *pkt; uchar *dhcp_pkt_start_ptr; @@ -252,9 +253,8 @@ static void dhcp6_send_request_packet(void) len = pkt - dhcp_pkt_start_ptr; /* send UDP packet to DHCP6 multicast address */ - string_to_ip6(DHCP6_MULTICAST_ADDR, strlen(DHCP6_MULTICAST_ADDR), &dhcp_bcast_ip6); net_set_udp_handler(dhcp6_handler); - net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6, + net_send_udp_packet6((uchar *)net_dhcp6_mcast_ethaddr, (struct in6_addr *)&dhcp_mcast_ip6, PORT_DHCP6_S, PORT_DHCP6_C, len); } @@ -473,8 +473,7 @@ static int dhcp6_check_advertise_packet(uchar *rx_pkt, unsigned int len) * server UID, save the new server UID and preference */ if (!sm_params.server_uid.uid_ptr || - (sm_params.server_uid.uid_ptr && - sm_params.server_uid.preference < sm_params.rx_status.preference)) { + sm_params.server_uid.preference < sm_params.rx_status.preference) { rx_uid_size = sm_params.rx_status.server_uid_size; if (sm_params.server_uid.uid_ptr) free(sm_params.server_uid.uid_ptr); diff --git a/net/dhcpv6.h b/net/dhcpv6.h index 65c8e4c71d3..d41a3c30615 100644 --- a/net/dhcpv6.h +++ b/net/dhcpv6.h @@ -40,7 +40,13 @@ /* vendor-class-data to send in vendor clas option */ #define DHCP6_VCI_STRING "U-Boot" -#define DHCP6_MULTICAST_ADDR "ff02::1:2" /* DHCP multicast address */ +/* + * All-DHCPv6 server multicast address + */ +#define DHCP6_MULTICAST_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x01, 0x00, 0x02 } } } /* DHCP6 States supported */ enum dhcp6_state { diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index 3b7e4700c6e..92bd7067a7f 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -115,7 +115,8 @@ int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int ret; struct udevice *dev; - net_lwip_set_current(); + if (net_lwip_eth_start() < 0) + return CMD_RET_FAILURE; dev = eth_get_dev(); if (!dev) { diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 149bdb784dc..19172ac959a 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -121,7 +121,8 @@ int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc == 3) var = argv[2]; - net_lwip_set_current(); + if (net_lwip_eth_start() < 0) + return CMD_RET_FAILURE; return dns_loop(eth_get_dev(), name, var); } diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index 6b7b696dbf0..f05c4cd3f64 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -14,6 +14,7 @@ #include <lwip/init.h> #include <lwip/prot/etharp.h> #include <net.h> +#include <timer.h> /* xx:xx:xx:xx:xx:xx\0 */ #define MAC_ADDR_STRLEN 18 @@ -21,6 +22,8 @@ #if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER) void (*push_packet)(void *, int len) = 0; #endif +static int net_try_count; +static int net_restarted; int net_restart_wrap; static uchar net_pkt_buf[(PKTBUFSRX) * PKTSIZE_ALIGN + PKTALIGN]; uchar *net_rx_packets[PKTBUFSRX]; @@ -134,18 +137,27 @@ static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip, return 0; } -/* Initialize the lwIP stack and the ethernet devices and set current device */ -void net_lwip_set_current(void) +/* + * Initialize the network stack if needed and start the current device if valid + */ +int net_lwip_eth_start(void) { - static bool init_done; - - if (!init_done) { - eth_init_rings(); - eth_init(); - lwip_init(); - init_done = true; + int ret; + + net_init(); + if (eth_is_on_demand_init()) { + eth_halt(); + eth_set_current(); + ret = eth_init(); + if (ret < 0) { + eth_halt(); + return ret; + } + } else { + eth_init_state_only(); } - eth_set_current(); + + return 0; } static struct netif *new_netif(struct udevice *udev, bool with_ip) @@ -224,11 +236,20 @@ void net_lwip_remove_netif(struct netif *netif) free(netif); } +/* + * Initialize the network buffers, an ethernet device, and the lwIP stack + * (once). + */ int net_init(void) { - eth_set_current(); + static bool init_done; - net_lwip_new_netif(eth_get_dev()); + if (!init_done) { + eth_init_rings(); + eth_init(); + lwip_init(); + init_done = true; + } return 0; } @@ -319,5 +340,48 @@ int net_loop(enum proto_t protocol) u32_t sys_now(void) { +#if CONFIG_IS_ENABLED(SANDBOX_TIMER) + return timer_early_get_count(); +#else return get_timer(0); +#endif +} + +int net_start_again(void) +{ + char *nretry; + int retry_forever = 0; + unsigned long retrycnt = 0; + + nretry = env_get("netretry"); + if (nretry) { + if (!strcmp(nretry, "yes")) + retry_forever = 1; + else if (!strcmp(nretry, "no")) + retrycnt = 0; + else if (!strcmp(nretry, "once")) + retrycnt = 1; + else + retrycnt = simple_strtoul(nretry, NULL, 0); + } else { + retrycnt = 0; + retry_forever = 0; + } + + if ((!retry_forever) && (net_try_count > retrycnt)) { + eth_halt(); + /* + * We don't provide a way for the protocol to return an error, + * but this is almost always the reason. + */ + return -ETIMEDOUT; + } + + net_try_count++; + + eth_halt(); +#if !defined(CONFIG_NET_DO_NOT_TRY_ANOTHER) + eth_try_another(!net_restarted); +#endif + return eth_init(); } diff --git a/net/lwip/ping.c b/net/lwip/ping.c index c586a96806d..d8042ceecf9 100644 --- a/net/lwip/ping.c +++ b/net/lwip/ping.c @@ -168,10 +168,13 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (!ipaddr_aton(argv[1], &addr)) return CMD_RET_USAGE; - net_lwip_set_current(); - - if (ping_loop(eth_get_dev(), &addr) < 0) - return CMD_RET_FAILURE; +restart: + if (net_lwip_eth_start() < 0 || ping_loop(eth_get_dev(), &addr) < 0) { + if (net_start_again() == 0) + goto restart; + else + return CMD_RET_FAILURE; + } return CMD_RET_SUCCESS; } diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c index 123d66b5dba..4f9b2049187 100644 --- a/net/lwip/tftp.c +++ b/net/lwip/tftp.c @@ -280,7 +280,10 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) goto out; } - net_lwip_set_current(); + if (net_lwip_eth_start() < 0) { + ret = CMD_RET_FAILURE; + goto out; + } if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0) ret = CMD_RET_FAILURE; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index ec098148835..a3b82908877 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -471,7 +471,11 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) int wget_do_request(ulong dst_addr, char *uri) { - net_lwip_set_current(); + int ret; + + ret = net_lwip_eth_start(); + if (ret < 0) + return ret; if (!wget_info) wget_info = &default_wget_info; diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index d5499918249..9af94786870 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -392,8 +392,7 @@ static int bootdev_test_hunter(struct unit_test_state *uts) ut_assert_console_end(); ut_assertok(bootdev_hunt("usb1", false)); - ut_assert_nextline( - "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found"); + ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); ut_assert_console_end(); /* USB is 7th in the list, so bit 8 */ @@ -448,8 +447,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("scanning bus for devices..."); ut_assert_skip_to_line("Hunting with: spi_flash"); ut_assert_nextline("Hunting with: usb"); - ut_assert_nextline( - "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found"); + ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); ut_assert_nextline("Hunting with: virtio"); ut_assert_console_end(); @@ -551,8 +549,7 @@ static int bootdev_test_hunt_prio(struct unit_test_state *uts) ut_assertok(bootdev_hunt_prio(BOOTDEVP_5_SCAN_SLOW, true)); ut_assert_nextline("Hunting with: ide"); ut_assert_nextline("Hunting with: usb"); - ut_assert_nextline( - "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found"); + ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); ut_assert_console_end(); return 0; @@ -604,7 +601,7 @@ static int bootdev_test_hunt_label(struct unit_test_state *uts) ut_assertnonnull(dev); ut_asserteq_str("usb_mass_storage.lun0.bootdev", dev->name); ut_asserteq(BOOTFLOW_METHF_SINGLE_UCLASS, mflags); - ut_assert_nextlinen("Bus usb@1: scanning bus usb@1"); + ut_assert_nextline("Bus usb@1: 5 USB Device(s) found"); ut_assert_console_end(); return 0; diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 5f9c037ff53..b261bd5f620 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -1290,7 +1290,7 @@ static int bootflow_efi(struct unit_test_state *uts) ut_assertok(run_command("bootflow scan", 0)); ut_assert_skip_to_line( - "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found"); + "Bus usb@1: 5 USB Device(s) found"); ut_assertok(run_command("bootflow list", 0)); diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 8596c5ad753..595e4cfcada 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_CMD_WGET) += wget.o endif obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o endif +obj-$(CONFIG_CMD_SPAWN) += spawn.o diff --git a/test/cmd/command.c b/test/cmd/command.c index 5ec93d490ba..5b1e5a77e5d 100644 --- a/test/cmd/command.c +++ b/test/cmd/command.c @@ -45,31 +45,32 @@ static int command_test(struct unit_test_state *uts) "setenv list ${list}3", strlen("setenv list 1"), 0); ut_assert(!strcmp("1", env_get("list"))); - ut_asserteq(1, run_command("false", 0)); ut_assertok(run_command("echo", 0)); - ut_asserteq(1, run_command_list("false", -1, 0)); ut_assertok(run_command_list("echo", -1, 0)); -#ifdef CONFIG_HUSH_PARSER - run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0); - run_command("run foo", 0); - ut_assertnonnull(env_get("black")); - ut_asserteq(0, strcmp("1", env_get("black"))); - ut_assertnonnull(env_get("adder")); - ut_asserteq(0, strcmp("2", env_get("adder"))); -#endif - - ut_assertok(run_command("", 0)); - ut_assertok(run_command(" ", 0)); + if (IS_ENABLED(CONFIG_HUSH_PARSER)) { + ut_asserteq(1, run_command("false", 0)); + ut_asserteq(1, run_command_list("false", -1, 0)); + run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0); + run_command("run foo", 0); + ut_assertnonnull(env_get("black")); + ut_asserteq(0, strcmp("1", env_get("black"))); + ut_assertnonnull(env_get("adder")); + ut_asserteq(0, strcmp("2", env_get("adder"))); + ut_assertok(run_command("", 0)); + ut_assertok(run_command(" ", 0)); + } ut_asserteq(1, run_command("'", 0)); /* Variadic function test-cases */ + if (IS_ENABLED(CONFIG_HUSH_PARSER)) { #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wformat-zero-length" - ut_assertok(run_commandf("")); + ut_assertok(run_commandf("")); #pragma GCC diagnostic pop - ut_assertok(run_commandf(" ")); + ut_assertok(run_commandf(" ")); + } ut_asserteq(1, run_commandf("'")); ut_assertok(run_commandf("env %s %s", "delete -f", "list")); diff --git a/test/cmd/spawn.c b/test/cmd/spawn.c new file mode 100644 index 00000000000..8f48f5ee25c --- /dev/null +++ b/test/cmd/spawn.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Tests for spawn and wait commands + * + * Copyright 2025, Linaro Ltd. + */ + +#include <command.h> +#include <test/cmd.h> +#include <test/test.h> +#include <test/ut.h> + +static int test_cmd_spawn(struct unit_test_state *uts) +{ + ut_assertok(run_command("wait; spawn sleep 2; setenv j ${job_id}; " + "spawn setenv spawned true; " + "setenv jj ${job_id}; wait; " + "echo ${j} ${jj} ${spawned}", 0)); + console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + ut_asserteq_ptr(uts->actual_str, + strstr(uts->actual_str, "1 2 true")); + + ut_assertok(run_command("spawn true; wait; setenv t $?; spawn false; " + "wait; setenv f $?; wait; echo $t $f $?", 0)); + console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + ut_asserteq_ptr(uts->actual_str, + strstr(uts->actual_str, "0 1 0")); + ut_assert_console_end(); + + return 0; +} +CMD_TEST(test_cmd_spawn, UTF_CONSOLE); diff --git a/test/common/print.c b/test/common/print.c index e3711b10809..c48efc2783f 100644 --- a/test/common/print.c +++ b/test/common/print.c @@ -45,11 +45,11 @@ static int print_guid(struct unit_test_state *uts) sprintf(str, "%pUL", guid); ut_asserteq_str("04030201-0605-0807-090A-0B0C0D0E0F10", str); sprintf(str, "%pUs", guid_esp); - if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) { /* brace needed */ - ut_asserteq_str("system", str); - } else { + if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) || + IS_ENABLED(CONFIG_CMD_EFIDEBUG) || IS_ENABLED(CONFIG_EFI)) + ut_asserteq_str("EFI System Partition", str); + else ut_asserteq_str("c12a7328-f81f-11d2-ba4b-00a0c93ec93b", str); - } ret = snprintf(str, 4, "%pUL", guid); ut_asserteq(0, str[3]); ut_asserteq(36, ret); diff --git a/test/dm/Makefile b/test/dm/Makefile index 3afcc26ca57..917dafe7d22 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -46,9 +46,7 @@ obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o obj-$(CONFIG_DM_DSA) += dsa.o obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o -ifdef CONFIG_NET obj-$(CONFIG_DM_ETH) += eth.o -endif obj-$(CONFIG_EXTCON) += extcon.o ifneq ($(CONFIG_EFI_PARTITION),) obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o diff --git a/test/dm/dsa.c b/test/dm/dsa.c index c6b4e12a758..9a31ae39d95 100644 --- a/test/dm/dsa.c +++ b/test/dm/dsa.c @@ -63,15 +63,15 @@ DM_TEST(dm_test_dsa_probe, UTF_SCAN_FDT); */ static int dm_test_dsa(struct unit_test_state *uts) { - net_ping_ip = string_to_ip("1.2.3.5"); + char *argv[] = { "ping", "1.1.2.2" }; env_set("ethact", "eth2"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); env_set("ethact", "lan0"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); env_set("ethact", "lan1"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); env_set("ethact", ""); diff --git a/test/dm/eth.c b/test/dm/eth.c index 467495863e1..1087ae9572d 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -171,18 +171,18 @@ DM_TEST(dm_test_ip6_make_lladdr, UTF_SCAN_FDT); static int dm_test_eth(struct unit_test_state *uts) { - net_ping_ip = string_to_ip("1.1.2.2"); + char *argv[] = { "ping", "1.1.2.2" }; env_set("ethact", "eth@10002000"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10002000", env_get("ethact")); env_set("ethact", "eth@10003000"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10003000", env_get("ethact")); env_set("ethact", "eth@10004000"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10004000", env_get("ethact")); return 0; @@ -191,22 +191,23 @@ DM_TEST(dm_test_eth, UTF_SCAN_FDT); static int dm_test_eth_alias(struct unit_test_state *uts) { - net_ping_ip = string_to_ip("1.1.2.2"); + char *argv[] = { "ping", "1.1.2.2" }; + env_set("ethact", "eth0"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10002000", env_get("ethact")); env_set("ethact", "eth6"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10004000", env_get("ethact")); /* Expected to fail since eth1 is not defined in the device tree */ env_set("ethact", "eth1"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10002000", env_get("ethact")); env_set("ethact", "eth5"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10003000", env_get("ethact")); return 0; @@ -215,18 +216,18 @@ DM_TEST(dm_test_eth_alias, UTF_SCAN_FDT); static int dm_test_eth_prime(struct unit_test_state *uts) { - net_ping_ip = string_to_ip("1.1.2.2"); + char *argv[] = { "ping", "1.1.2.2" }; /* Expected to be "eth@10003000" because of ethprime variable */ env_set("ethact", NULL); env_set("ethprime", "eth5"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10003000", env_get("ethact")); /* Expected to be "eth@10002000" because it is first */ env_set("ethact", NULL); env_set("ethprime", NULL); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10002000", env_get("ethact")); return 0; @@ -249,6 +250,7 @@ DM_TEST(dm_test_eth_prime, UTF_SCAN_FDT); */ static int dm_test_eth_act(struct unit_test_state *uts) { + char *argv[] = { "ping", "1.1.2.2" }; struct udevice *dev[DM_TEST_ETH_NUM]; const char *ethname[DM_TEST_ETH_NUM] = {"eth@10002000", "eth@10003000", "sbe5", "eth@10004000"}; @@ -258,7 +260,6 @@ static int dm_test_eth_act(struct unit_test_state *uts) int i; memset(ethaddr, '\0', sizeof(ethaddr)); - net_ping_ip = string_to_ip("1.1.2.2"); /* Prepare the test scenario */ for (i = 0; i < DM_TEST_ETH_NUM; i++) { @@ -281,7 +282,7 @@ static int dm_test_eth_act(struct unit_test_state *uts) env_set("ethact", ethname[0]); /* Segment fault might happen if something is wrong */ - ut_asserteq(-ENODEV, net_loop(PING)); + ut_asserteq(CMD_RET_FAILURE, do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); for (i = 0; i < DM_TEST_ETH_NUM; i++) { /* Restore the env */ @@ -334,15 +335,17 @@ DM_TEST(dm_test_ethaddr, UTF_SCAN_FDT); /* The asserts include a return on fail; cleanup in the caller */ static int _dm_test_eth_rotate1(struct unit_test_state *uts) { + char *argv[] = { "ping", "1.1.2.2" }; + /* Make sure that the default is to rotate to the next interface */ env_set("ethact", "eth@10004000"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10002000", env_get("ethact")); /* If ethrotate is no, then we should fail on a bad MAC */ env_set("ethact", "eth@10004000"); env_set("ethrotate", "no"); - ut_asserteq(-EINVAL, net_loop(PING)); + ut_asserteq(CMD_RET_FAILURE, do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10004000", env_get("ethact")); return 0; @@ -350,14 +353,16 @@ static int _dm_test_eth_rotate1(struct unit_test_state *uts) static int _dm_test_eth_rotate2(struct unit_test_state *uts) { + char *argv[] = { "ping", "1.1.2.2" }; + /* Make sure we can skip invalid devices */ env_set("ethact", "eth@10004000"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("eth@10004000", env_get("ethact")); /* Make sure we can handle device name which is not eth# */ env_set("ethact", "sbe5"); - ut_assertok(net_loop(PING)); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); ut_asserteq_str("sbe5", env_get("ethact")); return 0; @@ -368,9 +373,6 @@ static int dm_test_eth_rotate(struct unit_test_state *uts) char ethaddr[18]; int retval; - /* Set target IP to mock ping */ - net_ping_ip = string_to_ip("1.1.2.2"); - /* Invalidate eth1's MAC address */ memset(ethaddr, '\0', sizeof(ethaddr)); strncpy(ethaddr, env_get("eth6addr"), 17); @@ -396,6 +398,7 @@ static int dm_test_eth_rotate(struct unit_test_state *uts) /* Restore the env */ env_set("ethaddr", ethaddr); } + /* Restore the env */ env_set(".flags", NULL); @@ -406,26 +409,28 @@ DM_TEST(dm_test_eth_rotate, UTF_SCAN_FDT); /* The asserts include a return on fail; cleanup in the caller */ static int _dm_test_net_retry(struct unit_test_state *uts) { + char *argv[] = { "ping", "1.1.2.2" }; + /* - * eth1 is disabled and netretry is yes, so the ping should succeed and - * the active device should be eth0 + * eth0 is disabled and netretry is yes, so the ping should succeed and + * the active device should be eth1 */ - sandbox_eth_disable_response(1, true); - env_set("ethact", "lan1"); + sandbox_eth_disable_response(0, true); + env_set("ethact", "eth@10002000"); env_set("netretry", "yes"); sandbox_eth_skip_timeout(); - ut_assertok(net_loop(PING)); - ut_asserteq_str("eth@10002000", env_get("ethact")); + ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); + ut_asserteq_str("eth@10003000", env_get("ethact")); /* - * eth1 is disabled and netretry is no, so the ping should fail and the - * active device should be eth1 + * eth0 is disabled and netretry is no, so the ping should fail and the + * active device should be eth0 */ - env_set("ethact", "lan1"); + env_set("ethact", "eth@10002000"); env_set("netretry", "no"); sandbox_eth_skip_timeout(); - ut_asserteq(-ENONET, net_loop(PING)); - ut_asserteq_str("lan1", env_get("ethact")); + ut_asserteq(CMD_RET_FAILURE, do_ping(NULL, 0, ARRAY_SIZE(argv), argv)); + ut_asserteq_str("eth@10002000", env_get("ethact")); return 0; } @@ -434,8 +439,6 @@ static int dm_test_net_retry(struct unit_test_state *uts) { int retval; - net_ping_ip = string_to_ip("1.1.2.2"); - retval = _dm_test_net_retry(uts); /* Restore the env */ @@ -446,6 +449,7 @@ static int dm_test_net_retry(struct unit_test_state *uts) } DM_TEST(dm_test_net_retry, UTF_SCAN_FDT); +#if CONFIG_IS_ENABLED(NET) static int sb_check_arp_reply(struct udevice *dev, void *packet, unsigned int len) { @@ -511,7 +515,9 @@ static int sb_with_async_arp_handler(struct udevice *dev, void *packet, return sb_check_arp_reply(dev, packet, len); } +#endif +#if CONFIG_IS_ENABLED(NET) static int dm_test_eth_async_arp_reply(struct unit_test_state *uts) { net_ping_ip = string_to_ip("1.1.2.2"); @@ -529,7 +535,9 @@ static int dm_test_eth_async_arp_reply(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_eth_async_arp_reply, UTF_SCAN_FDT); +#endif +#if CONFIG_IS_ENABLED(NET) static int sb_check_ping_reply(struct udevice *dev, void *packet, unsigned int len) { @@ -613,6 +621,7 @@ static int dm_test_eth_async_ping_reply(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_eth_async_ping_reply, UTF_SCAN_FDT); +#endif #if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY) diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c index 8a95f6bdb90..896cf5b2ae9 100644 --- a/test/dm/power-domain.c +++ b/test/dm/power-domain.c @@ -27,7 +27,7 @@ static int dm_test_power_domain(struct unit_test_state *uts) ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test", &dev_test)); - ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, + ut_asserteq(1, sandbox_power_domain_query(dev_power_domain, TEST_POWER_DOMAIN)); ut_assertok(sandbox_power_domain_test_get(dev_test)); diff --git a/test/lib/Makefile b/test/lib/Makefile index 97ab71ba5d1..d620510f998 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SANDBOX) += kconfig.o obj-y += lmb.o obj-$(CONFIG_HAVE_SETJMP) += longjmp.o obj-$(CONFIG_SANDBOX) += membuf.o +obj-$(CONFIG_HAVE_INITJMP) += initjmp.o obj-$(CONFIG_CONSOLE_RECORD) += test_print.o obj-$(CONFIG_SSCANF) += sscanf.o obj-$(CONFIG_$(PHASE_)STRTO) += str.o @@ -31,6 +32,7 @@ obj-$(CONFIG_CRC8) += test_crc8.o obj-$(CONFIG_UT_LIB_CRYPT) += test_crypt.o obj-$(CONFIG_UT_TIME) += time.o obj-$(CONFIG_$(PHASE_)UT_UNICODE) += unicode.o +obj-$(CONFIG_UTHREAD) += uthread.o obj-$(CONFIG_LIB_UUID) += uuid.o else obj-$(CONFIG_SANDBOX) += kconfig_spl.o diff --git a/test/lib/initjmp.c b/test/lib/initjmp.c new file mode 100644 index 00000000000..5b4b50b3f0f --- /dev/null +++ b/test/lib/initjmp.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2025 Linaro Limited + * + * Unit test for initjmp() + */ + +#include <compiler.h> +#include <setjmp.h> +#include <stdbool.h> +#include <test/lib.h> +#include <test/ut.h> +#include <vsprintf.h> + +static bool ep_entered; +static jmp_buf return_buf; + +static void __noreturn entrypoint(void) +{ + ep_entered = true; + + /* Jump back to the main routine */ + longjmp(return_buf, 1); + + /* Not reached */ + panic("longjmp failed\n"); +} + +static int lib_initjmp(struct unit_test_state *uts) +{ + int ret; + void *stack; + jmp_buf buf; + /* Arbitrary but smaller values (< page size?) fail on SANDBOX */ + size_t stack_sz = 8192; + + (void)entrypoint; + + ep_entered = false; + + stack = malloc(stack_sz); + ut_assertnonnull(stack); + + /* + * Prepare return_buf so that entrypoint may jump back just after the + * if() + */ + if (!setjmp(return_buf)) { + /* return_buf initialized, entrypoint not yet called */ + + /* + * Prepare another jump buffer to jump into entrypoint with the + * given stack + */ + ret = initjmp(buf, entrypoint, stack, stack_sz); + ut_assertok(ret); + + /* Jump into entrypoint */ + longjmp(buf, 1); + /* + * Not reached since entrypoint is expected to branch after + * the if() + */ + ut_assert(false); + } + + ut_assert(ep_entered); + + free(stack); + + return 0; +} +LIB_TEST(lib_initjmp, 0); diff --git a/test/lib/uthread.c b/test/lib/uthread.c new file mode 100644 index 00000000000..10a94d1c560 --- /dev/null +++ b/test/lib/uthread.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Linaro Limited + * + * Unit test for uthread + */ + +#include <stdbool.h> +#include <test/lib.h> +#include <test/ut.h> +#include <uthread.h> + +static int count; + +/* A thread entry point */ +static void worker(void *arg) +{ + int loops = (int)(unsigned long)arg; + int i; + + for (i = 0; i < loops; i++) { + count++; + uthread_schedule(); + } +} + +/* + * uthread() - testing the uthread API + * + * This function creates two threads with the same entry point. The first one + * receives 5 as an argument, the second one receives 10. The number indicates + * the number of time the worker thread should loop on uthread_schedule() + * before returning. The workers increment a global counter each time they loop. + * As a result the main thread knows how many times it should call + * uthread_schedule() to let the two threads proceed, and it also knows which + * value the counter should have at any moment. + */ +static int uthread(struct unit_test_state *uts) +{ + int i; + int id1, id2; + + count = 0; + id1 = uthread_grp_new_id(); + ut_assert(id1 != 0); + id2 = uthread_grp_new_id(); + ut_assert(id2 != 0); + ut_assert(id1 != id2); + ut_assertok(uthread_create(NULL, worker, (void *)5, 0, id1)); + ut_assertok(uthread_create(NULL, worker, (void *)10, 0, 0)); + /* + * The first call is expected to schedule the first worker, which will + * schedule the second one, which will schedule back to the main thread + * (here). Therefore count should be 2. + */ + ut_assert(uthread_schedule()); + ut_asserteq(2, count); + ut_assert(!uthread_grp_done(id1)); + /* Four more calls should bring the count to 10 */ + for (i = 0; i < 4; i++) { + ut_assert(!uthread_grp_done(id1)); + ut_assert(uthread_schedule()); + } + ut_asserteq(10, count); + /* This one allows the first worker to exit */ + ut_assert(uthread_schedule()); + /* At this point there should be no runnable thread in group 'id1' */ + ut_assert(uthread_grp_done(id1)); + /* Five more calls for the second worker to finish incrementing */ + for (i = 0; i < 5; i++) + ut_assert(uthread_schedule()); + ut_asserteq(15, count); + /* Plus one call to let the second worker return from its entry point */ + ut_assert(uthread_schedule()); + /* Now both tasks should be done, schedule should return false */ + ut_assert(!uthread_schedule()); + + return 0; +} +LIB_TEST(uthread, 0); + +struct mw_args { + struct unit_test_state *uts; + struct uthread_mutex *m; + int flag; +}; + +static int mutex_worker_ret; + +static int _mutex_worker(struct mw_args *args) +{ + struct unit_test_state *uts = args->uts; + + ut_asserteq(-EBUSY, uthread_mutex_trylock(args->m)); + ut_assertok(uthread_mutex_lock(args->m)); + args->flag = 1; + ut_assertok(uthread_mutex_unlock(args->m)); + + return 0; +} + +static void mutex_worker(void *arg) +{ + mutex_worker_ret = _mutex_worker((struct mw_args *)arg); +} + +/* + * thread_mutex() - testing uthread mutex operations + * + */ +static int uthread_mutex(struct unit_test_state *uts) +{ + struct uthread_mutex m = UTHREAD_MUTEX_INITIALIZER; + struct mw_args args = { .uts = uts, .m = &m, .flag = 0 }; + int id; + int i; + + id = uthread_grp_new_id(); + ut_assert(id != 0); + /* Take the mutex */ + ut_assertok(uthread_mutex_lock(&m)); + /* Start a thread */ + ut_assertok(uthread_create(NULL, mutex_worker, (void *)&args, 0, + id)); + /* Let the thread run for a bit */ + for (i = 0; i < 100; i++) + ut_assert(uthread_schedule()); + /* Thread should not have set the flag due to the mutex */ + ut_asserteq(0, args.flag); + /* Release the mutex */ + ut_assertok(uthread_mutex_unlock(&m)); + /* Schedule the thread until it is done */ + while (uthread_schedule()) + ; + /* Now the flag should be set */ + ut_asserteq(1, args.flag); + /* And the mutex should be available */ + ut_assertok(uthread_mutex_trylock(&m)); + ut_assertok(uthread_mutex_unlock(&m)); + + /* Of course no error are expected from the thread routine */ + ut_assertok(mutex_worker_ret); + + return 0; +} +LIB_TEST(uthread_mutex, 0); diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index c73fb4abbcb..0205048e73a 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -17,7 +17,7 @@ supported_fs_fat = ['fat12', 'fat16'] supported_fs_mkdir = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic'] supported_fs_unlink = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic'] supported_fs_symlink = ['ext4'] -supported_fs_rename = ['fat12', 'fat16', 'fat32'] +supported_fs_rename = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic'] # # Filesystem test specific setup diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py index 64a3b50f52a..88b163ce305 100644 --- a/test/py/tests/test_fs/test_basic.py +++ b/test/py/tests/test_fs/test_basic.py @@ -35,6 +35,19 @@ class TestFsBasic(object): '%sls host 0:0 invalid_d' % fs_cmd_prefix) assert('' == output) + with ubman.log.section('Test Case 1c - test -e'): + # Test Case 1 - test -e + output = ubman.run_command_list([ + 'host bind 0 %s' % fs_img, + 'test -e host 0:0 1MB.file && echo PASS']) + assert('PASS' in ''.join(output)) + + with ubman.log.section('Test Case 1d - test -e (invalid file)'): + # In addition, test with a nonexistent file to see if we crash. + output = ubman.run_command( + 'test -e host 0:0 2MB.file || echo PASS') + assert('PASS' in ''.join(output)) + def test_fs2(self, ubman, fs_obj_basic): """ Test Case 2 - size command for a small file diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py index dd767528dbf..09174f91e98 100644 --- a/test/py/tests/test_spi.py +++ b/test/py/tests/test_spi.py @@ -703,4 +703,33 @@ def test_spi_negative(ubman): ubman, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ ) + # Start reading from the reserved area + m = re.search(r'reserved\[0\]\s*\[(0x.+)-(0x.+)\]', output) + if not m or int(m.group(1), 16) == 0: + ubman.log.info('No reserved area is defined or start addr is 0x0!') + else: + rstart_area = int(m.group(1), 16) + rend_area = int(m.group(2), 16) + + # Case 1: Start reading from the middle of the reserved area + r_size = rend_area - rstart_area + r_area = rstart_area + r_size + flash_ops( + ubman, 'read', start, size, r_area, 1, error_msg, EXPECTED_READ + ) + + # Case 2: Start reading from before the reserved area to cross-over + # the reserved area + rstart_area = rstart_area - int(size/2) + flash_ops( + ubman, 'read', start, size, rstart_area, 1, error_msg, EXPECTED_READ + ) + + # Case 3: Start reading till after the reserved area to cross-over + # the reserved area + rend_area = rend_area - int(size/2) + flash_ops( + ubman, 'read', start, size, rend_area, 1, error_msg, EXPECTED_READ + ) + i = i + 1 diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py index 6ac1b225465..fcdcbe2c6db 100644 --- a/test/py/tests/test_trace.py +++ b/test/py/tests/test_trace.py @@ -201,7 +201,7 @@ def check_funcgraph(ubman, fname, proftool, map_fname, trace_dat): # Then look for this: # u-boot-1 0..... 282.101375: funcgraph_exit: 0.006 us | } # Then check for this: - # u-boot-1 0..... 282.101375: funcgraph_entry: 0.000 us | calc_reloc_ofs(); + # u-boot-1 0..... 282.101375: funcgraph_entry: 0.000 us | event_init(); expected_indent = None found_start = False @@ -224,8 +224,8 @@ def check_funcgraph(ubman, fname, proftool, map_fname, trace_dat): found_end = True # The next function after initf_bootstage() exits should be - # initcall_is_event() - assert upto == 'calc_reloc_ofs()' + # event_init() + assert upto == 'event_init()' # Now look for initf_dm() and dm_timer_init() so we can check the bootstage # time @@ -274,7 +274,7 @@ def check_flamegraph(ubman, fname, proftool, map_fname, trace_fg): # We expect dm_timer_init() to be called twice: once before relocation and # once after look1 = 'initf_dm;dm_timer_init 1' - look2 = 'board_init_r;initcall_run_list;initr_dm_devices;dm_timer_init 1' + look2 = 'board_init_r;initcall_run_r;initr_dm_devices;dm_timer_init 1' found = 0 with open(trace_fg, 'r') as fd: for line in fd: diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 5d051e005da..f4c832be8d3 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -531,7 +531,7 @@ class Toolchains: if arch == 'aarch64': arch = 'arm64' base = 'https://www.kernel.org/pub/tools/crosstool/files/bin' - versions = ['13.2.0', '12.2.0'] + versions = ['14.2.0', '13.2.0'] links = [] for version in versions: url = '%s/%s/%s/' % (base, arch, version) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 3e52236b15a..a0caa029cc0 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -134,7 +134,9 @@ static struct spl_info spl_infos[] = { { "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 }, { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 }, { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 }, + { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 }, { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 }, + { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 }, { "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 }, }; 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