diff options
150 files changed, 3310 insertions, 659 deletions
@@ -344,7 +344,7 @@ config FIT_SIGNATURE check the legacy image format is disabled by default, so that unsigned images cannot be loaded. If a board needs the legacy image format support in this case, enable it using - CONFIG_IMAGE_FORMAT_LEGACY. + CONFIG_LEGACY_IMAGE_FORMAT. config FIT_SIGNATURE_MAX_SIZE hex "Max size of signed FIT structures" @@ -473,7 +473,7 @@ endif # SPL endif # FIT -config IMAGE_FORMAT_LEGACY +config LEGACY_IMAGE_FORMAT bool "Enable support for the legacy image format" default y if !FIT_SIGNATURE help diff --git a/MAINTAINERS b/MAINTAINERS index bea3122f2b6..e91684191fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -633,6 +633,12 @@ M: Simon Glass <sjg@chromium.org> S: Maintained F: tools/patman/ +PCI Endpoint +M: Ramon Fried <rfried.dev@gmail.com> +S: Maintained +F: drivers/pci_endpoint/ +F: include/pci_ep.h + POWER M: Jaehoon Chung <jh80.chung@samsung.com> S: Maintained @@ -874,7 +874,7 @@ ifneq ($(CONFIG_BUILD_TARGET),) ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) endif -ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) +ifdef CONFIG_INIT_SP_RELATIVE ALL-y += init_sp_bss_offset_check endif @@ -1155,7 +1155,7 @@ binary_size_check: u-boot-nodtb.bin FORCE fi \ fi -ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) +ifdef CONFIG_INIT_SP_RELATIVE ifneq ($(CONFIG_SYS_MALLOC_F_LEN),) subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN))) else diff --git a/arch/Kconfig b/arch/Kconfig index 28afe398016..355d2145223 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -90,6 +90,7 @@ config SANDBOX select DM_SPI_FLASH select HAVE_BLOCK_DEVICE select LZO + select PCI_ENDPOINT select SPI select SUPPORT_OF_CONTROL imply BITREVERSE @@ -120,6 +121,7 @@ config SANDBOX imply VIRTIO_BLK imply VIRTIO_NET imply DM_SOUND + imply PCI_SANDBOX_EP imply PCH config SH diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f5a7630e4f9..87541977259 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -20,15 +20,25 @@ config POSITION_INDEPENDENT information that is embedded into the binary to support U-Boot relocating itself to the top-of-RAM later during execution. -config SYS_INIT_SP_BSS_OFFSET - int +config INIT_SP_RELATIVE + bool "Specify the early stack pointer relative to the .bss section" help U-Boot typically uses a hard-coded value for the stack pointer - before relocation. Define this option to instead calculate the + before relocation. Enable this option to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that can be loaded and executed at arbitrary - addresses and thus avoid using arbitrary addresses at runtime. This - option's value is the offset added to &_bss_start in order to + addresses and thus avoid using arbitrary addresses at runtime. + + If this option is enabled, the early stack pointer is set to + &_bss_start with a offset value added. The offset is specified by + SYS_INIT_SP_BSS_OFFSET. + +config SYS_INIT_SP_BSS_OFFSET + int "Early stack offset from the .bss base address" + depends on INIT_SP_RELATIVE + default 524288 + help + This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c index d2bddb589ae..fc332fb6269 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl.c +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -16,6 +16,12 @@ #include <asm/arch/spr_syscntl.h> #include <linux/mtd/st_smi.h> +/* Reserve some space to store the BootROM's stack pointer during SPL operation. + * The BSS cannot be used for this purpose because it will be zeroed after + * having stored the pointer, so force the location to the data section. + */ +u32 bootrom_stash_sp __attribute__((section(".data"))); + static void ddr_clock_init(void) { struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; @@ -223,8 +229,9 @@ u32 spl_boot_device(void) { u32 mode = 0; - /* Currently only SNOR is supported as the only */ - if (snor_boot_selected()) { + if (usb_boot_selected()) { + mode = BOOT_DEVICE_BOOTROM; + } else if (snor_boot_selected()) { /* SNOR-SMI initialization */ snor_init(); @@ -234,6 +241,18 @@ u32 spl_boot_device(void) return mode; } +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + + /* + * If the main boot device (eg. NOR) is empty, try to jump back into the + * BootROM for USB boot process. + */ + if (USB_BOOT_SUPPORTED) + spl_boot_list[1] = BOOT_DEVICE_BOOTROM; +} + void board_init_f(ulong dummy) { struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; @@ -251,6 +270,28 @@ void board_init_f(ulong dummy) puts("Configure DDR\n"); mpmc_init(); spear_late_init(); +} - board_init_r(NULL, 0); +/* + * In a few cases (Ethernet, UART or USB boot, we might want to go back into the + * BootROM code right after having initialized a few components like the DRAM). + * The following function is called from SPL common code (board_init_r). + */ +void board_return_to_bootrom(void) +{ + /* + * Retrieve the BootROM's stack pointer and jump back to the start of + * the SPL, where we can easily branch back into the BootROM. Don't do + * it right here because SPL might be compiled in Thumb mode while the + * BootROM expects ARM mode. + */ + asm volatile ("ldr r0, =bootrom_stash_sp;" + "ldr r0, [r0];" + "mov sp, r0;" +#if defined(CONFIG_SPL_SYS_THUMB_BUILD) + "blx back_to_bootrom;" +#else + "bl back_to_bootrom;" +#endif + ); } diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S index 1cab4ca6fb0..9ac96291b70 100644 --- a/arch/arm/cpu/arm926ejs/spear/start.S +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -21,51 +21,35 @@ * * Startup Code (reset vector) * - * Below are the critical initializations already taken place in BootROM. - * So, these are not taken care in Xloader - * 1. Relocation to RAM - * 2. Initializing stacks + * The BootROM already initialized its own stack in the [0-0xb00] reserved + * range of the SRAM. The SPL (in _main) will update the stack pointer to + * its own SRAM area (right before the gd section). * ************************************************************************* */ .globl reset + .globl back_to_bootrom reset: -/* - * Xloader has to return back to BootROM in a few cases. - * eg. Ethernet boot, UART boot, USB boot - * Saving registers for returning back - */ - stmdb sp!, {r0-r12,r14} - bl cpu_init_crit -/* - * Clearing bss area is not done in Xloader. - * BSS area lies in the DDR location which is not yet initialized - * bss is assumed to be uninitialized. - */ - ldmia sp!, {r0-r12,pc} + /* + * SPL has to return back to BootROM in a few cases (eg. Ethernet boot, + * UART boot, USB boot): save registers in BootROM's stack and then the + * BootROM's stack pointer in the SPL's data section. + */ + push {r0-r12,lr} + ldr r0, =bootrom_stash_sp + str sp, [r0] -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -cpu_init_crit: /* - * flush v4 I/D caches + * Flush v4 I/D caches */ mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */ /* - * enable instruction cache + * Enable instruction cache */ mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ @@ -73,7 +57,9 @@ cpu_init_crit: /* * Go setup Memory and board specific bits prior to relocation. + * This call is not supposed to return. */ - stmdb sp!, {lr} - bl _main /* _main will call board_init_f */ - ldmia sp!, {pc} + b _main /* _main will call board_init_f */ + +back_to_bootrom: + pop {r0-r12,pc} diff --git a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h index fa6e86d1c24..b4220e4936f 100644 --- a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h +++ b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h @@ -48,7 +48,7 @@ #define __MAX(a, b) (((a) > (b)) ? (a) : (b)) #define __CODE_DATA_SIZE (__bss_start - _start) #define __BSS_SIZE (__bss_end - __bss_start) -#ifdef CONFIG_SYS_INIT_SP_BSS_OFFSET +#ifdef CONFIG_INIT_SP_RELATIVE #define __MAX_EXTRA_RAM_USAGE __MAX(__BSS_SIZE, CONFIG_SYS_INIT_SP_BSS_OFFSET) #else #define __MAX_EXTRA_RAM_USAGE __BSS_SIZE diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index a3cd475b48d..337a3537ed2 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -8,8 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-ld11"; #address-cells = <2>; @@ -110,6 +108,17 @@ <1 10 4>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index baf23268366..3721110b17a 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/gpio/uniphier-gpio.h> #include <dt-bindings/thermal/thermal.h> -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-ld20"; #address-cells = <2>; @@ -215,6 +213,17 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index 961d4d3621f..b1aff285c8b 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -8,8 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-pxs3"; #address-cells = <2>; @@ -138,6 +136,17 @@ <1 10 4>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index d6b632aa87d..e76b25a03e8 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -72,7 +72,7 @@ ENTRY(_main) ldr x0, =(CONFIG_TPL_STACK) #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) -#elif defined(CONFIG_SYS_INIT_SP_BSS_OFFSET) +#elif defined(CONFIG_INIT_SP_RELATIVE) adr x0, __bss_start add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET #else diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 24d16299e8d..ce50dbe907c 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -310,7 +310,7 @@ static ulong get_image_ivt_offset(ulong img_addr) buf = map_sysmem(img_addr, 0); switch (genimg_get_format(buf)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: return (image_get_image_size((image_header_t *)img_addr) + 0x1000 - 1) & ~(0x1000 - 1); diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 5507348981b..03460c3eb7e 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -375,8 +375,8 @@ void update_rtc_magic(void) */ int board_early_init_f(void) { - prcm_init(); set_mux_conf_regs(); + prcm_init(); #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) update_rtc_magic(); #endif diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 97e22ead598..ff9f29f2d5d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -86,6 +86,7 @@ config TEGRA_ARMV7_COMMON config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" select ARM64 + select INIT_SP_RELATIVE select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT select TEGRA_COMMON diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig index 479c0955eec..b2e53b58caf 100644 --- a/arch/arm/mach-tegra/tegra186/Kconfig +++ b/arch/arm/mach-tegra/tegra186/Kconfig @@ -21,9 +21,6 @@ endchoice config SYS_SOC default "tegra186" -config SYS_INIT_SP_BSS_OFFSET - default 524288 - source "board/nvidia/p2771-0000/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 250738aed31..3637473051b 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -40,9 +40,6 @@ endchoice config SYS_SOC default "tegra210" -config SYS_INIT_SP_BSS_OFFSET - default 524288 - source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2371-0000/Kconfig" source "board/nvidia/p2371-2180/Kconfig" diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index d0c39d42737..115af244cd5 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -13,18 +13,20 @@ else obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-y += dram_init.o obj-y += board_init.o +obj-$(CONFIG_ARCH_UNIPHIER_V8_MULTI) += base-address.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o ifndef CONFIG_SYSRESET obj-y += reset.o endif -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-y += pinctrl-glue.o obj-$(CONFIG_MMC) += mmc-first-dev.o obj-y += fdt-fixup.o endif +obj-y += sbc/ obj-y += soc-info.o obj-y += boot-device/ obj-y += clk/ diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index e56e1f679ca..3fed7985fcd 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -22,7 +22,7 @@ #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd - ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) + ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) ldr \rd, [\ra] and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) @@ -30,7 +30,7 @@ .endm ENTRY(debug_ll_init) - ldr r0, =SG_REVISION + ldr r0, =(SG_BASE + SG_REVISION) ldr r1, [r0] and r1, r1, #SG_REVISION_TYPE_MASK mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT @@ -40,7 +40,7 @@ ENTRY(debug_ll_init) cmp r1, #0x26 bne ld4_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -59,11 +59,11 @@ ld4_end: sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 - ldr r0, =SG_LOADPINCTRL + ldr r0, =(SG_BASE + SG_LOADPINCTRL) mov r1, #1 str r1, [r0] - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] @@ -78,7 +78,7 @@ pro4_end: cmp r1, #0x29 bne sld8_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -100,11 +100,11 @@ sld8_end: sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 - ldr r0, =SG_LOADPINCTRL + ldr r0, =(SG_BASE + SG_LOADPINCTRL) mov r1, #1 str r1, [r0] - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] @@ -119,7 +119,7 @@ pro5_end: cmp r1, #0x2E bne pxs2_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -129,7 +129,7 @@ pro5_end: sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] @@ -144,7 +144,7 @@ pxs2_end: cmp r1, #0x2F bne ld6b_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -153,7 +153,7 @@ pxs2_end: sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c index 35e75e2ab2d..7653bd2d3c6 100644 --- a/arch/arm/mach-uniphier/arm64/mem_map.c +++ b/arch/arm/mach-uniphier/arm64/mem_map.c @@ -7,6 +7,8 @@ #include <linux/types.h> #include <asm/armv8/mmu.h> +#include "../init.h" + static struct mm_region uniphier_mem_map[] = { { .virt = 0x00000000, @@ -27,3 +29,11 @@ static struct mm_region uniphier_mem_map[] = { }; struct mm_region *mem_map = uniphier_mem_map; + +void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size) +{ + uniphier_mem_map[0].size = dram_base; + uniphier_mem_map[1].virt = dram_base; + uniphier_mem_map[1].phys = dram_base; + uniphier_mem_map[1].size = dram_size; +} diff --git a/arch/arm/mach-uniphier/base-address.c b/arch/arm/mach-uniphier/base-address.c new file mode 100644 index 00000000000..5ee742e363f --- /dev/null +++ b/arch/arm/mach-uniphier/base-address.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (C) 2019 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> + +#include <common.h> +#include <dm/of.h> +#include <fdt_support.h> +#include <linux/io.h> +#include <linux/libfdt.h> +#include <linux/sizes.h> +#include <asm/global_data.h> + +#include "base-address.h" +#include "sc64-regs.h" +#include "sg-regs.h" + +/* + * Dummy initializers are needed to allocate these to .data section instead of + * .bss section. The .bss section is unusable before relocation because the + * .bss section and DT share the same address. Without the initializers, + * DT would be broken. + */ +void __iomem *sc_base = (void *)0xdeadbeef; +void __iomem *sg_base = (void *)0xdeadbeef; + +static u64 uniphier_base_address_get(const char *compat_tail) +{ + DECLARE_GLOBAL_DATA_PTR; + const void *fdt = gd->fdt_blob; + int offset, len, i; + const char *str; + + for (offset = fdt_next_node(fdt, 0, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + for (i = 0; + (str = fdt_stringlist_get(fdt, offset, "compatible", i, &len)); + i++) { + if (!memcmp(compat_tail, + str + len - strlen(compat_tail), + strlen(compat_tail))) + return fdt_get_base_address(fdt, offset); + } + } + + return OF_BAD_ADDR; +} + +int uniphier_base_address_init(void) +{ + u64 base; + + base = uniphier_base_address_get("-soc-glue"); + if (base == OF_BAD_ADDR) + return -EINVAL; + + sg_base = ioremap(base, SZ_8K); + + base = uniphier_base_address_get("-sysctrl"); + if (base == OF_BAD_ADDR) + return -EINVAL; + + sc_base = ioremap(base, SZ_64K); + + return 0; +} diff --git a/arch/arm/mach-uniphier/base-address.h b/arch/arm/mach-uniphier/base-address.h new file mode 100644 index 00000000000..6158ce7d66a --- /dev/null +++ b/arch/arm/mach-uniphier/base-address.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Socionext Inc. + */ + +#ifndef __UNIPHIER_BASE_ADDRESS_H +#define __UNIPHIER_BASE_ADDRESS_H + +#ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI +int uniphier_base_address_init(void); +#else +static inline int uniphier_base_address_init(void) +{ + return 0; +} +#endif + +#endif /* __UNIPHIER_BASE_ADDRESS_H */ diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 972dbe8ae55..3180b24330b 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -31,24 +31,25 @@ static void nand_denali_wp_disable(void) #endif } -static int uniphier_set_fdt_file(void) +static void uniphier_set_env_fdt_file(void) { DECLARE_GLOBAL_DATA_PTR; const char *compat; char dtb_name[256]; int buf_len = sizeof(dtb_name); + int ret; if (env_get("fdtfile")) - return 0; /* do nothing if it is already set */ + return; /* do nothing if it is already set */ compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL); if (!compat) - return -EINVAL; + goto fail; /* rip off the vendor prefix "socionext," */ compat = strchr(compat, ','); if (!compat) - return -EINVAL; + goto fail; compat++; strncpy(dtb_name, compat, buf_len); @@ -56,7 +57,43 @@ static int uniphier_set_fdt_file(void) strncat(dtb_name, ".dtb", buf_len); - return env_set("fdtfile", dtb_name); + ret = env_set("fdtfile", dtb_name); + if (ret) + goto fail; + + return; +fail: + pr_warn("\"fdt_file\" environment variable was not set correctly\n"); +} + +static void uniphier_set_env_addr(const char *env, const char *offset_env) +{ + unsigned long offset = 0; + const char *str; + char *end; + int ret; + + if (env_get(env)) + return; /* do nothing if it is already set */ + + if (offset_env) { + str = env_get(offset_env); + if (!str) + goto fail; + + offset = simple_strtoul(str, &end, 16); + if (*end) + goto fail; + } + + ret = env_set_hex(env, gd->ram_base + offset); + if (ret) + goto fail; + + return; + +fail: + pr_warn("\"%s\" environment variable was not set correctly\n", env); } int board_late_init(void) @@ -68,6 +105,10 @@ int board_late_init(void) printf("eMMC Boot"); env_set("bootdev", "emmc"); break; + case BOOT_DEVICE_MMC2: + printf("SD Boot"); + env_set("bootdev", "sd"); + break; case BOOT_DEVICE_NAND: printf("NAND Boot"); env_set("bootdev", "nand"); @@ -92,8 +133,15 @@ int board_late_init(void) printf("\n"); - if (uniphier_set_fdt_file()) - pr_warn("fdt_file environment was not set correctly\n"); + uniphier_set_env_fdt_file(); + + uniphier_set_env_addr("dram_base", NULL); + + uniphier_set_env_addr("loadaddr", "loadaddr_offset"); + + uniphier_set_env_addr("kernel_addr_r", "kernel_addr_r_offset"); + uniphier_set_env_addr("ramdisk_addr_r", "ramdisk_addr_r_offset"); + uniphier_set_env_addr("fdt_addr_r", "fdt_addr_r_offset"); return 0; } diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c index 10093be0e43..11e70a926fc 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c @@ -58,11 +58,3 @@ int uniphier_ld20_boot_device_is_usb(u32 pinmon) { return !!(~pinmon & 0x00000780); } - -unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode) -{ - if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB) - mode = BOOT_DEVICE_BOARD; - - return mode; -} diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c index 01a72c03505..2edf66d5c10 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c @@ -36,5 +36,5 @@ const unsigned uniphier_pxs3_boot_device_count = int uniphier_pxs3_boot_device_is_usb(u32 pinmon) { - return !!(readl(SG_PINMON2) & BIT(31)); + return !!(readl(sg_base + SG_PINMON2) & BIT(31)); } diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 23be8cfcf00..83f8c6a428c 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -7,6 +7,7 @@ #include <common.h> #include <spl.h> #include <stdio.h> +#include <linux/io.h> #include <linux/log2.h> #include "../init.h" @@ -20,9 +21,11 @@ struct uniphier_boot_device_info { unsigned int boot_device_sel_shift; const struct uniphier_boot_device *boot_device_table; const unsigned int *boot_device_count; + int (*boot_device_is_sd)(u32 pinmon); int (*boot_device_is_usb)(u32 pinmon); unsigned int (*boot_device_fixup)(unsigned int mode); - int have_internal_stm; + int (*boot_is_swapped)(void); + bool have_internal_stm; }; static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { @@ -32,7 +35,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, - .have_internal_stm = 1, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) @@ -41,7 +45,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, - .have_internal_stm = 0, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = false, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) @@ -50,7 +55,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, - .have_internal_stm = 1, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) @@ -59,7 +65,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_pro5_boot_device_table, .boot_device_count = &uniphier_pro5_boot_device_count, - .have_internal_stm = 0, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = false, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) @@ -70,7 +77,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, - .have_internal_stm = 0, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = false, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) @@ -81,7 +89,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, - .have_internal_stm = 1, /* STM on A-chip */ + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = true, /* STM on A-chip */ }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) @@ -91,8 +100,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld11_boot_device_is_usb, - .boot_device_fixup = uniphier_ld11_boot_device_fixup, - .have_internal_stm = 1, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) @@ -102,8 +111,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld20_boot_device_is_usb, - .boot_device_fixup = uniphier_ld11_boot_device_fixup, - .have_internal_stm = 1, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS3) @@ -113,7 +122,8 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_pxs3_boot_device_table, .boot_device_count = &uniphier_pxs3_boot_device_count, .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb, - .have_internal_stm = 0, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, + .have_internal_stm = false, }, #endif }; @@ -126,10 +136,13 @@ static unsigned int __uniphier_boot_device_raw( u32 pinmon; unsigned int boot_sel; - if (boot_is_swapped()) + if (info->boot_is_swapped && info->boot_is_swapped()) return BOOT_DEVICE_NOR; - pinmon = readl(SG_PINMON0); + pinmon = readl(sg_base + SG_PINMON0); + + if (info->boot_device_is_sd && info->boot_device_is_sd(pinmon)) + return BOOT_DEVICE_MMC2; if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon)) return BOOT_DEVICE_USB; @@ -187,7 +200,7 @@ int uniphier_have_internal_stm(void) int uniphier_boot_from_backend(void) { - return !!(readl(SG_PINMON0) & BIT(27)); + return !!(readl(sg_base + SG_PINMON0) & BIT(27)); } #ifndef CONFIG_SPL_BUILD @@ -209,9 +222,15 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("STB Micon: %s\n", uniphier_boot_from_backend() ? "OFF" : "ON"); - printf("Boot Swap: %s\n", boot_is_swapped() ? "ON" : "OFF"); + if (info->boot_is_swapped) + printf("Boot Swap: %s\n", + info->boot_is_swapped() ? "ON" : "OFF"); + + pinmon = readl(sg_base + SG_PINMON0); - pinmon = readl(SG_PINMON0); + if (info->boot_device_is_sd) + printf("SD Boot: %s\n", + info->boot_device_is_sd(pinmon) ? "ON" : "OFF"); if (info->boot_device_is_usb) printf("USB Boot: %s\n", diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h index 44579f17d3e..bbb634316b3 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.h +++ b/arch/arm/mach-uniphier/boot-device/boot-device.h @@ -30,6 +30,5 @@ int uniphier_ld20_boot_device_is_usb(u32 pinmon); int uniphier_pxs3_boot_device_is_usb(u32 pinmon); unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode); -unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode); #endif /* _UNIPHIER_BOOT_DEVICE_H_ */ diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 3d741b4c4d1..d12f49e5230 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -17,12 +17,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-base-ld20.o pll-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-base-ld20.o pll-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-base-ld20.o pll-pxs3.o endif - -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c index 39cde4400b4..c796d364bb1 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c @@ -16,14 +16,14 @@ void uniphier_ld4_dram_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_UMC; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c index 7674ceb885f..808d1ebfe19 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c @@ -18,17 +18,17 @@ void uniphier_pro5_dram_clk_init(void) * UMCA1, UMC31: Ch0 (WIO1) * UMCA0, UMC30: Ch0 (WIO0) */ - tmp = readl(SC_RSTCTRL4); + tmp = readl(sc_base + SC_RSTCTRL4); tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; - writel(tmp, SC_RSTCTRL4); - readl(SC_RSTCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL4); + readl(sc_base + SC_RSTCTRL4); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL4); + tmp = readl(sc_base + SC_CLKCTRL4); tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0; - writel(tmp, SC_CLKCTRL4); - readl(SC_CLKCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL4); + readl(sc_base + SC_CLKCTRL4); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c index ad4e83a84a2..b78bd016721 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c @@ -15,18 +15,18 @@ void uniphier_pxs2_dram_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL4); + tmp = readl(sc_base + SC_RSTCTRL4); tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; - writel(tmp, SC_RSTCTRL4); - readl(SC_RSTCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL4); + readl(sc_base + SC_RSTCTRL4); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL4); + tmp = readl(sc_base + SC_CLKCTRL4); tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 | SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0; - writel(tmp, SC_CLKCTRL4); - readl(SC_CLKCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL4); + readl(sc_base + SC_CLKCTRL4); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c index eb36a9e7ae4..f32f78dd26d 100644 --- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c @@ -17,14 +17,14 @@ void uniphier_ld4_early_clk_init(void) /* deassert reset */ if (spl_boot_device() != BOOT_DEVICE_NAND) { - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); tmp &= ~SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); + writel(tmp, sc_base + SC_RSTCTRL); }; /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index e997acf1b7d..0917b33c254 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -17,16 +17,16 @@ void uniphier_ld11_clk_init(void) { /* if booted from a device other than USB, without stand-by MPU */ - if ((readl(SG_PINMON0) & BIT(27)) && + if ((readl(sg_base + SG_PINMON0) & BIT(27)) && uniphier_boot_device_raw() != BOOT_DEVICE_USB) { - writel(1, SG_ETPHYPSHUT); - writel(1, SG_ETPHYCNT); + writel(1, sg_base + SG_ETPHYPSHUT); + writel(1, sg_base + SG_ETPHYCNT); udelay(1); /* wait for regulator level 1.1V -> 2.5V */ - writel(3, SG_ETPHYCNT); - writel(3, SG_ETPHYPSHUT); - writel(7, SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYPSHUT); + writel(7, sg_base + SG_ETPHYCNT); } /* TODO: use "mmc-pwrseq-emmc" */ @@ -37,7 +37,7 @@ void uniphier_ld11_clk_init(void) int ch; for (ch = 0; ch < 3; ch++) { - void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL; + void __iomem *phyctrl = sg_base + SG_USBPHYCTRL; writel(0x82280600, phyctrl + 8 * ch); writel(0x00000106, phyctrl + 8 * ch + 4); diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c index 02a14ddfb8b..397b2d7384f 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld20.c +++ b/arch/arm/mach-uniphier/clk/clk-ld20.c @@ -15,13 +15,13 @@ void uniphier_ld20_clk_init(void) { u32 tmp; - tmp = readl(SC_RSTCTRL6); + tmp = readl(sc_base + SC_RSTCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_RSTCTRL6); + writel(tmp, sc_base + SC_RSTCTRL6); - tmp = readl(SC_CLKCTRL6); + tmp = readl(sc_base + SC_CLKCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_CLKCTRL6); + writel(tmp, sc_base + SC_CLKCTRL6); /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c index 9c88cde5e25..03939425039 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ld4.c @@ -15,18 +15,18 @@ void uniphier_ld4_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 32d44c0b667..2b364dca410 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -15,7 +15,7 @@ void uniphier_pro4_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | SC_RSTCTRL_NRST_GIO; @@ -23,18 +23,18 @@ void uniphier_pro4_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ #ifdef CONFIG_USB_DWC3_UNIPHIER - tmp = readl(SC_RSTCTRL2); + tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL2); + readl(sc_base + SC_RSTCTRL2); /* dummy read */ #endif /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; @@ -42,6 +42,6 @@ void uniphier_pro4_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c index 338d73d0708..874964b2d5b 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-pro5.c @@ -13,25 +13,25 @@ void uniphier_pro5_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ #ifdef CONFIG_USB_DWC3_UNIPHIER - tmp = readl(SC_RSTCTRL2); + tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL2); + readl(sc_base + SC_RSTCTRL2); /* dummy read */ #endif /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; @@ -39,6 +39,6 @@ void uniphier_pro5_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index afa12fa071e..8cb4f87ae54 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -14,29 +14,29 @@ void uniphier_pxs2_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ #ifdef CONFIG_USB_DWC3_UNIPHIER - tmp = readl(SC_RSTCTRL2); + tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL2); + readl(sc_base + SC_RSTCTRL2); /* dummy read */ - tmp = readl(SC_RSTCTRL6); + tmp = readl(sc_base + SC_RSTCTRL6); tmp |= 0x37; - writel(tmp, SC_RSTCTRL6); + writel(tmp, sc_base + SC_RSTCTRL6); #endif /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; @@ -44,6 +44,6 @@ void uniphier_pxs2_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c index 73824e9ace6..33b9c5b73d1 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs3.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c @@ -15,13 +15,13 @@ void uniphier_pxs3_clk_init(void) { u32 tmp; - tmp = readl(SC_RSTCTRL6); + tmp = readl(sc_base + SC_RSTCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_RSTCTRL6); + writel(tmp, sc_base + SC_RSTCTRL6); - tmp = readl(SC_CLKCTRL6); + tmp = readl(sc_base + SC_CLKCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_CLKCTRL6); + writel(tmp, sc_base + SC_CLKCTRL6); /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c index 4b9ec075a84..72fe8db8dd1 100644 --- a/arch/arm/mach-uniphier/clk/dpll-ld4.c +++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c @@ -23,7 +23,7 @@ int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) * to FOUT (DPLLCTRL.bit[29:20]) */ - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp &= ~0x000f0000; switch (dram_freq) { case 1333: @@ -42,11 +42,11 @@ int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) #else tmp |= SC_DPLLCTRL_SSC_RATE; #endif - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); - tmp = readl(SC_DPLLCTRL2); + tmp = readl(sc_base + SC_DPLLCTRL2); tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); + writel(tmp, sc_base + SC_DPLLCTRL2); /* Wait 500 usec until dpll gets stable */ udelay(500); diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c index 29659464b57..62594954848 100644 --- a/arch/arm/mach-uniphier/clk/dpll-pro4.c +++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c @@ -23,7 +23,7 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) * to FOUT ( DPLLCTRL.bit[29:20] ) */ - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp &= ~(0x000f0000); switch (dram_freq) { case 1333: @@ -46,11 +46,11 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) #else tmp |= 0x00008000; #endif - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); - tmp = readl(SC_DPLLCTRL2); + tmp = readl(sc_base + SC_DPLLCTRL2); tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); + writel(tmp, sc_base + SC_DPLLCTRL2); /* Wait until dpll gets stable */ udelay(500); diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c index 1d7b7521984..1ac52d11f34 100644 --- a/arch/arm/mach-uniphier/clk/dpll-sld8.c +++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c @@ -22,10 +22,10 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) * [4] ICPD_TEST 0x1 * [3:0] ICPD 0xb */ - tmp = readl(SC_DPLLCTRL3); + tmp = readl(sc_base + SC_DPLLCTRL3); tmp &= ~0x00ff0717; tmp |= 0x00d0061b; - writel(tmp, SC_DPLLCTRL3); + writel(tmp, sc_base + SC_DPLLCTRL3); /* * Set DPLL SSC parameters for DPLLCTRL @@ -33,14 +33,14 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) */ - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp &= ~0x3ff07fff; #ifdef DPLL_SSC_RATE_1PER tmp |= 0x084018bf; #else tmp |= 0x084031a6; #endif - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); /* * Set DPLL SSC parameters for DPLLCTRL2 @@ -49,10 +49,10 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) * [26:20] SSC_M 79 (0x4f) * [19:0] SSC_K 964689 (0xeb851) */ - tmp = readl(SC_DPLLCTRL2); + tmp = readl(sc_base + SC_DPLLCTRL2); tmp &= ~0xefffffff; tmp |= 0x0cfeb851; - writel(tmp, SC_DPLLCTRL2); + writel(tmp, sc_base + SC_DPLLCTRL2); /* Wait 500 usec until dpll gets stable */ udelay(500); diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c index 7f434f66962..6ba5a367274 100644 --- a/arch/arm/mach-uniphier/clk/dpll-tail.c +++ b/arch/arm/mach-uniphier/clk/dpll-tail.c @@ -14,7 +14,7 @@ void uniphier_ld4_dpll_ssc_en(void) { u32 tmp; - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); } diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 67b8ee7c3e3..ea96d739c53 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -12,6 +12,7 @@ #include <linux/io.h> #include <linux/sizes.h> +#include "../sc64-regs.h" #include "pll.h" /* PLL type: SSC */ @@ -31,13 +32,9 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, unsigned int ssc_rate, unsigned int divn) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; @@ -60,57 +57,39 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, tmp |= SC_PLLCTRL2_NRSTDS; writel(tmp, base + 4); - iounmap(base); - return 0; } int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base); /* SSCPLLCTRL */ tmp |= SC_PLLCTRL_SSC_EN; writel(tmp, base); - iounmap(base); - return 0; } int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); - iounmap(base); - return 0; } int uniphier_ld20_vpll27_init(unsigned long reg_base) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base); /* VPLL27CTRL */ tmp |= SC_VPLL27CTRL_WP; /* write protect off */ writel(tmp, base); @@ -123,25 +102,17 @@ int uniphier_ld20_vpll27_init(unsigned long reg_base) tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */ writel(tmp, base); - iounmap(base); - return 0; } int uniphier_ld20_dspll_init(unsigned long reg_base) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base + 4); /* DSPLLCTRL2 */ tmp |= SC_DSPLLCTRL2_K_LD; writel(tmp, base + 4); - iounmap(base); - return 0; } diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index fd724f3e8c2..7f07e3e92b8 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -11,15 +11,15 @@ #include "pll.h" /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */ -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */ +#define SC_CPLLCTRL 0x1400 /* CPU/ARM */ +#define SC_SPLLCTRL 0x1410 /* misc */ +#define SC_MPLLCTRL 0x1430 /* DSP */ +#define SC_VSPLLCTRL 0x1440 /* Video codec, VPE etc. */ +#define SC_DPLLCTRL 0x1460 /* DDR memory */ /* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) +#define SC_VPLL27FCTRL 0x1500 +#define SC_VPLL27ACTRL 0x1520 void uniphier_ld11_pll_init(void) { @@ -40,6 +40,6 @@ void uniphier_ld11_pll_init(void) uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); - writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ - writel(SC_CA_GEARUPD, SC_CA53_GEARUPD); + writel(0, sc_base + SC_CA53_GEARSET); /* Gear0: CPLL/2 */ + writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD); } diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 682bd1e0c12..04b3312a2a5 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -11,23 +11,23 @@ #include "pll.h" /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ -#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ +#define SC_CPLLCTRL 0x1400 /* CPU/ARM */ +#define SC_SPLLCTRL 0x1410 /* misc */ +#define SC_SPLL2CTRL 0x1420 /* DSP */ +#define SC_MPLLCTRL 0x1430 /* Video codec */ +#define SC_VPPLLCTRL 0x1440 /* VPE etc. */ +#define SC_GPPLLCTRL 0x1450 /* GPU/Mali */ +#define SC_DPLL0CTRL 0x1460 /* DDR memory 0 */ +#define SC_DPLL1CTRL 0x1470 /* DDR memory 1 */ +#define SC_DPLL2CTRL 0x1480 /* DDR memory 2 */ /* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) +#define SC_VPLL27FCTRL 0x1500 +#define SC_VPLL27ACTRL 0x1520 /* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) -#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) +#define SC_VPLL8KCTRL 0x1540 +#define SC_A2PLLCTRL 0x15C0 void uniphier_ld20_pll_init(void) { diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 6a145a3baa1..c66031bdd05 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -16,14 +16,14 @@ static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); + tmp = readl(sc_base + SC_UPLLCTRL); tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || @@ -38,110 +38,110 @@ static void upll_init(void) } } - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); /* set 1 to K_LD(UPLLCTRL.bit[27]) */ tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); /* wait 10 usec */ udelay(10); /* set 1 to SNRT(UPLLCTRL.bit[28]) */ tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); } static void vpll_init(void) { u32 tmp, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } else { /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* wait 10 usec */ udelay(10); /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); } void uniphier_ld4_pll_init(void) diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c index 2ee2ed6bd66..b7dc3e261f8 100644 --- a/arch/arm/mach-uniphier/clk/pll-pro4.c +++ b/arch/arm/mach-uniphier/clk/pll-pro4.c @@ -17,7 +17,7 @@ static void vpll_init(void) u32 tmp, clk_mode_axosel; /* Set VPLL27A & VPLL27B */ - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ @@ -26,80 +26,80 @@ static void vpll_init(void) return; /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); /* Unset VPLA_K_LD and VPLB_K_LD bit */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* Set VPLA_M and VPLB_M to 0x20 */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { /* Set VPLA_K and VPLB_K for AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x00066666; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x00066666; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } else { /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } /* wait 1 usec */ udelay(1); /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* Unset VPLA_SNRST and VPLB_SNRST bit */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp &= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); } void uniphier_pro4_pll_init(void) diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index 5a1b1d25aca..278f530ea9a 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -10,25 +10,25 @@ #include "pll.h" /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ -#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) -#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) -#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) -#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) +#define SC_CPLLCTRL 0x1400 /* CPU/ARM */ +#define SC_SPLLCTRL 0x1410 /* misc */ +#define SC_SPLL2CTRL 0x1420 /* DSP */ +#define SC_VPPLLCTRL 0x1430 /* VPE */ +#define SC_VGPLLCTRL 0x1440 +#define SC_DECPLLCTRL 0x1450 +#define SC_ENCPLLCTRL 0x1460 +#define SC_PXFPLLCTRL 0x1470 +#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */ +#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */ +#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */ +#define SC_VSPLLCTRL 0x14c0 /* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) +#define SC_VPLL27FCTRL 0x1500 +#define SC_VPLL27ACTRL 0x1520 /* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_VPLL8KCTRL 0x1540 void uniphier_pxs3_pll_init(void) { diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c index 9f5f5051b31..6a7b203a44d 100644 --- a/arch/arm/mach-uniphier/cpu-info.c +++ b/arch/arm/mach-uniphier/cpu-info.c @@ -10,11 +10,17 @@ #include <linux/io.h> #include <linux/printk.h> +#include "base-address.h" #include "soc-info.h" int print_cpuinfo(void) { unsigned int id, model, rev, required_model = 1, required_rev = 1; + int ret; + + ret = uniphier_base_address_init(); + if (ret) + return ret; id = uniphier_get_soc_id(); model = uniphier_get_soc_model(); diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c index 22d2caa1099..f64ff39c9e6 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c @@ -22,9 +22,9 @@ unsigned int uniphier_ld6b_debug_uart_init(void) sg_set_pinsel(115, 0, 8, 4); /* TXD1 -> TXD1 */ sg_set_pinsel(113, 2, 8, 4); /* SBO0 -> TXD2 */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_LD6B_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c index 0d6629918ac..79c6c101e22 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c @@ -20,11 +20,11 @@ unsigned int uniphier_pro4_debug_uart_init(void) sg_set_iectrl(0); sg_set_pinsel(128, 0, 4, 8); /* TXD0 -> TXD0 */ - writel(1, SG_LOADPINCTRL); + writel(1, sg_base + SG_LOADPINCTRL); - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_PRO4_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c index 1a0a942f2dc..ef3b383ee43 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c @@ -23,11 +23,11 @@ unsigned int uniphier_pro5_debug_uart_init(void) sg_set_pinsel(51, 0, 4, 8); /* TXD2 -> TXD2 */ sg_set_pinsel(53, 0, 4, 8); /* TXD3 -> TXD3 */ - writel(1, SG_LOADPINCTRL); + writel(1, sg_base + SG_LOADPINCTRL); - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_PRO5_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c index 5d50c4fa244..ee8caad1d45 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c @@ -23,9 +23,9 @@ unsigned int uniphier_pxs2_debug_uart_init(void) sg_set_pinsel(113, 8, 8, 4); /* TXD2 -> TXD2 */ sg_set_pinsel(219, 8, 8, 4); /* TXD3 -> TXD3 */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_PXS2_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index bc96b2e7be1..a70ce59accd 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -32,7 +32,8 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval, unsigned int mux_bits, unsigned int reg_stride) { unsigned int shift = pin * mux_bits % 32; - unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; + void __iomem *reg = sg_base + SG_PINCTRL_BASE + + pin * mux_bits / 32 * reg_stride; u32 mask = (1U << mux_bits) - 1; u32 tmp; @@ -45,7 +46,7 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval, void sg_set_iectrl(unsigned int pin) { unsigned int bit = pin % 32; - unsigned long reg = SG_IECTRL + pin / 32 * 4; + void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4; u32 tmp; tmp = readl(reg); diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index fa4b3e386b8..13821a92883 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -13,82 +13,27 @@ #include <linux/sizes.h> #include <asm/global_data.h> +#include "init.h" #include "sg-regs.h" #include "soc-info.h" DECLARE_GLOBAL_DATA_PTR; -struct uniphier_memif_data { - unsigned int soc_id; - unsigned long sparse_ch1_base; - int have_ch2; -}; - -static const struct uniphier_memif_data uniphier_memif_data[] = { - { - .soc_id = UNIPHIER_LD4_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PRO4_ID, - .sparse_ch1_base = 0xa0000000, - }, - { - .soc_id = UNIPHIER_SLD8_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PRO5_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PXS2_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_LD6B_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_LD11_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_LD20_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_PXS3_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, -}; -UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data) - struct uniphier_dram_map { unsigned long base; unsigned long size; }; -static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) +static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map, + unsigned long sparse_ch1_base, bool have_ch2) { - const struct uniphier_memif_data *data; unsigned long size; u32 val; - data = uniphier_get_memif_data(); - if (!data) { - pr_err("unsupported SoC\n"); - return -EINVAL; - } - - val = readl(SG_MEMCONF); + val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ - dram_map[0].base = CONFIG_SYS_SDRAM_BASE; + dram_map[0].base = 0x80000000; switch (val & SG_MEMCONF_CH0_SZ_MASK) { case SG_MEMCONF_CH0_SZ_64M: @@ -120,14 +65,14 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) dram_map[1].base = dram_map[0].base + size; if (val & SG_MEMCONF_SPARSEMEM) { - if (dram_map[1].base > data->sparse_ch1_base) { + if (dram_map[1].base > sparse_ch1_base) { pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n"); pr_warn("Only ch0 is available\n"); dram_map[1].base = 0; return 0; } - dram_map[1].base = data->sparse_ch1_base; + dram_map[1].base = sparse_ch1_base; } switch (val & SG_MEMCONF_CH1_SZ_MASK) { @@ -156,7 +101,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) dram_map[1].size = size; - if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE) + if (!have_ch2 || val & SG_MEMCONF_CH2_DISABLE) return 0; /* set up ch2 */ @@ -191,14 +136,90 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) return 0; } +static int uniphier_ld4_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xc0000000, false); +} + +static int uniphier_pro4_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xa0000000, false); +} + +static int uniphier_pxs2_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xc0000000, true); +} + +struct uniphier_dram_init_data { + unsigned int soc_id; + int (*dram_map_get)(struct uniphier_dram_map dram_map[]); +}; + +static const struct uniphier_dram_init_data uniphier_dram_init_data[] = { + { + .soc_id = UNIPHIER_LD4_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PRO4_ID, + .dram_map_get = uniphier_pro4_dram_map_get, + }, + { + .soc_id = UNIPHIER_SLD8_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PRO5_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PXS2_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD6B_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD11_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD20_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_PXS3_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, +}; +UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_dram_init_data, + uniphier_dram_init_data) + +static int uniphier_dram_map_get(struct uniphier_dram_map *dram_map) +{ + const struct uniphier_dram_init_data *data; + + data = uniphier_get_dram_init_data(); + if (!data) { + pr_err("unsupported SoC\n"); + return -ENOTSUPP; + } + + return data->dram_map_get(dram_map); +} + int dram_init(void) { struct uniphier_dram_map dram_map[3] = {}; + bool valid_bank_found = false; + unsigned long prev_top; int ret, i; gd->ram_size = 0; - ret = uniphier_memconf_decode(dram_map); + ret = uniphier_dram_map_get(dram_map); if (ret) return ret; @@ -206,15 +227,14 @@ int dram_init(void) unsigned long max_size; if (!dram_map[i].size) - break; + continue; /* * U-Boot relocates itself to the tail of the memory region, * but it does not expect sparse memory. We use the first * contiguous chunk here. */ - if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size < - dram_map[i].base) + if (valid_bank_found && prev_top < dram_map[i].base) break; /* @@ -234,6 +254,12 @@ int dram_init(void) } gd->ram_size += dram_map[i].size; + + if (!valid_bank_found) + gd->ram_base = dram_map[i].base; + + prev_top = dram_map[i].base + dram_map[i].size; + valid_bank_found = true; } /* @@ -249,17 +275,34 @@ int dram_init(void) int dram_init_banksize(void) { struct uniphier_dram_map dram_map[3] = {}; - int i; + unsigned long base, top; + bool valid_bank_found = false; + int ret, i; - uniphier_memconf_decode(dram_map); + ret = uniphier_dram_map_get(dram_map); + if (ret) + return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i >= ARRAY_SIZE(gd->bd->bi_dram)) - break; + if (i < ARRAY_SIZE(gd->bd->bi_dram)) { + gd->bd->bi_dram[i].start = dram_map[i].base; + gd->bd->bi_dram[i].size = dram_map[i].size; + } + + if (!dram_map[i].size) + continue; - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (!valid_bank_found) + base = dram_map[i].base; + top = dram_map[i].base + dram_map[i].size; + valid_bank_found = true; } + if (!valid_bank_found) + return -EINVAL; + + /* map all the DRAM regions */ + uniphier_mem_map_init(base, top - base); + return 0; } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index c6b3f3656cc..b37ab2fa508 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -102,5 +102,13 @@ unsigned int uniphier_boot_device_raw(void); int uniphier_have_internal_stm(void); int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); +#ifdef CONFIG_ARM64 +void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size); +#else +static inline void uniphier_mem_map_init(unsigned long dram_base, + unsigned long dram_size) +{ +} +#endif #endif /* __MACH_INIT_H */ diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c index 8105368df14..f69b489b76e 100644 --- a/arch/arm/mach-uniphier/memconf.c +++ b/arch/arm/mach-uniphier/memconf.c @@ -140,7 +140,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd, } out: - writel(val, SG_MEMCONF); + writel(val, sg_base + SG_MEMCONF); return 0; } diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index 1be5685c6fb..46879019fda 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -18,6 +18,25 @@ #define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034) #define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0) +static bool support_card_found; + +static void support_card_detect(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const void *fdt = gd->fdt_blob; + int offset; + + offset = fdt_node_offset_by_compatible(fdt, 0, "smsc,lan9118"); + if (offset < 0) + return; + + offset = fdt_node_offset_by_compatible(fdt, 0, "ns16550a"); + if (offset < 0) + return; + + support_card_found = true; +} + /* * 0: reset deassert, 1: reset * @@ -51,6 +70,11 @@ static int support_card_show_revision(void) void support_card_init(void) { + support_card_detect(); + + if (!support_card_found) + return; + support_card_reset(); /* * After power on, we need to keep the LAN controller in reset state @@ -67,6 +91,9 @@ void support_card_init(void) int board_eth_init(bd_t *bis) { + if (!support_card_found) + return 0; + return smc911x_initialize(0, SMC911X_BASE); } #endif @@ -161,6 +188,9 @@ static void detect_num_flash_banks(void) void support_card_late_init(void) { + if (!support_card_found) + return; + detect_num_flash_banks(); } @@ -221,6 +251,9 @@ void led_puts(const char *s) int i; u32 val = 0; + if (!support_card_found) + return; + if (!s) return; diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 28c95e2ce58..31685d00094 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -22,14 +22,14 @@ void __SECURE reset_cpu(unsigned long ignored) { u32 tmp; - writel(5, SC_IRQTIMSET); /* default value */ + writel(5, sc_base + SC_IRQTIMSET); /* default value */ - tmp = readl(SC_SLFRSTSEL); + tmp = readl(sc_base + SC_SLFRSTSEL); tmp &= ~0x3; /* mask [1:0] */ tmp |= 0x0; /* XRST reboot */ - writel(tmp, SC_SLFRSTSEL); + writel(tmp, sc_base + SC_SLFRSTSEL); - tmp = readl(SC_SLFRSTCTL); + tmp = readl(sc_base + SC_SLFRSTCTL); tmp |= 0x1; - writel(tmp, SC_SLFRSTCTL); + writel(tmp, sc_base + SC_SLFRSTCTL); } diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index 912e05a725d..6c698a39225 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-y += sbc-boot.o + +ifndef CONFIG_SPL_BUILD obj-y += sbc.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o @@ -9,3 +12,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += sbc-pxs2.o +endif diff --git a/arch/arm/mach-uniphier/sbc/sbc-boot.c b/arch/arm/mach-uniphier/sbc/sbc-boot.c new file mode 100644 index 00000000000..ec22b453e0f --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-boot.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2011-2014 Panasonic Corporation +// Copyright (C) 2015-2019 Socionext Inc. + +#include <linux/io.h> + +#include "sbc-regs.h" + +int uniphier_sbc_boot_is_swapped(void) +{ + return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); +} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld11.c b/arch/arm/mach-uniphier/sbc/sbc-ld11.c index 44d8a1e3bd9..21972ac9494 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ld11.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ld11.c @@ -12,6 +12,9 @@ void uniphier_ld11_sbc_init(void) { + if (!uniphier_sbc_is_enabled()) + return; + uniphier_sbc_init_savepin(); /* necessary for ROM boot ?? */ diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ld4.c index d08b571e23c..72e9743c8f8 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ld4.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ld4.c @@ -13,6 +13,9 @@ void uniphier_ld4_sbc_init(void) { u32 tmp; + if (!uniphier_sbc_is_enabled()) + return; + uniphier_sbc_init_savepin(); /* system bus output enable */ diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c index 8c167ef0698..3275f22ce96 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c +++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c @@ -10,6 +10,9 @@ void uniphier_pxs2_sbc_init(void) { + if (!uniphier_sbc_is_enabled()) + return; + uniphier_sbc_init_savepin(); /* necessary for ROM boot ?? */ diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h index 853015acbca..1e9618653f2 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-regs.h +++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h @@ -76,12 +76,7 @@ #define PC0CTRL 0x598000c0 -#ifndef __ASSEMBLY__ -#include <linux/io.h> -static inline int boot_is_swapped(void) -{ - return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); -} -#endif +int uniphier_sbc_boot_is_swapped(void); +int uniphier_sbc_is_enabled(void); #endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/mach-uniphier/sbc/sbc.c b/arch/arm/mach-uniphier/sbc/sbc.c index df01e5c01d5..af8d6f4f9dc 100644 --- a/arch/arm/mach-uniphier/sbc/sbc.c +++ b/arch/arm/mach-uniphier/sbc/sbc.c @@ -5,7 +5,9 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ +#include <common.h> #include <linux/io.h> +#include <asm/global_data.h> #include "../init.h" #include "sbc-regs.h" @@ -31,6 +33,20 @@ #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 +int uniphier_sbc_is_enabled(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const void *fdt = gd->fdt_blob; + int offset; + + offset = fdt_node_offset_by_compatible(fdt, 0, + "socionext,uniphier-system-bus"); + if (offset < 0) + return 0; + + return fdtdec_get_is_enabled(fdt, offset); +} + static void __uniphier_sbc_init(int savepin) { /* @@ -48,7 +64,7 @@ static void __uniphier_sbc_init(int savepin) writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); } - if (boot_is_swapped()) { + if (uniphier_sbc_boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index 28de19c039c..e43116e064b 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -10,31 +10,36 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#define SC_BASE_ADDR 0x61840000 +#ifndef __ASSEMBLY__ +#include <linux/compiler.h> +#define sc_base ((void __iomem *)SC_BASE) +#endif -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) +#define SC_BASE 0x61840000 + +#define SC_DPLLCTRL 0x1200 #define SC_DPLLCTRL_SSC_EN (0x1 << 31) #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) -#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) +#define SC_DPLLCTRL2 0x1204 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) -#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) +#define SC_DPLLCTRL3 0x1208 #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) -#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) +#define SC_UPLLCTRL 0x1210 -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) -#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) -#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) +#define SC_VPLL27ACTRL 0x1270 +#define SC_VPLL27ACTRL2 0x1274 +#define SC_VPLL27ACTRL3 0x1278 -#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) -#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) -#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) +#define SC_VPLL27BCTRL 0x1290 +#define SC_VPLL27BCTRL2 0x1294 +#define SC_VPLL27BCTRL3 0x1298 -#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL 0x2000 #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) @@ -44,14 +49,14 @@ #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2) -#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL2 0x2004 #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ -#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) +#define SC_RSTCTRL3 0x2008 /* Pro5 or newer */ -#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) +#define SC_RSTCTRL4 0x200c #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */ #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ @@ -60,11 +65,11 @@ #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ -#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) +#define SC_RSTCTRL5 0x2010 -#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) +#define SC_RSTCTRL6 0x2014 -#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL 0x2104 #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) @@ -76,15 +81,15 @@ #define SC_CLKCTRL_CEN_PERI (0x1 << 0) /* Pro5 or newer */ -#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) +#define SC_CLKCTRL4 0x210c #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */ #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ /* System reset control register */ -#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) -#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) -#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) +#define SC_IRQTIMSET 0x3000 +#define SC_SLFRSTSEL 0x3010 +#define SC_SLFRSTCTL 0x3014 #endif /* ARCH_SC_REGS_H */ diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index 83f34e3faf1..fdcca232b61 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -9,28 +9,33 @@ #ifndef SC64_REGS_H #define SC64_REGS_H -#define SC_BASE_ADDR 0x61840000 +#ifndef __ASSEMBLY__ +#include <linux/compiler.h> +extern void __iomem *sc_base; +#endif -#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) -#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) -#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) -#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) -#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) -#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) +#define SC_BASE 0x61840000 -#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) -#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) -#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) -#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) -#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) -#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) +#define SC_RSTCTRL 0x2000 +#define SC_RSTCTRL3 0x2008 +#define SC_RSTCTRL4 0x200c +#define SC_RSTCTRL5 0x2010 +#define SC_RSTCTRL6 0x2014 +#define SC_RSTCTRL7 0x2018 -#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) -#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) -#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) -#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) -#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) -#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CLKCTRL 0x2100 +#define SC_CLKCTRL3 0x2108 +#define SC_CLKCTRL4 0x210c +#define SC_CLKCTRL5 0x2110 +#define SC_CLKCTRL6 0x2114 +#define SC_CLKCTRL7 0x2118 + +#define SC_CA72_GEARST 0x8000 +#define SC_CA72_GEARSET 0x8004 +#define SC_CA72_GEARUPD 0x8008 +#define SC_CA53_GEARST 0x8080 +#define SC_CA53_GEARSET 0x8084 +#define SC_CA53_GEARUPD 0x8088 #define SC_CA_GEARUPD (1 << 0) #endif /* SC64_REGS_H */ diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 39ffed5885d..f47d1019498 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -10,15 +10,23 @@ #ifndef UNIPHIER_SG_REGS_H #define UNIPHIER_SG_REGS_H +#ifndef __ASSEMBLY__ +#include <linux/compiler.h> +#ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI +extern void __iomem *sg_base; +#else +#define sg_base ((void __iomem *)SG_BASE) +#endif +#endif /* __ASSEMBLY__ */ + /* Base Address */ -#define SG_CTRL_BASE 0x5f800000 -#define SG_DBG_BASE 0x5f900000 +#define SG_BASE 0x5f800000 /* Revision */ -#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION 0x0000 /* Memory Configuration */ -#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) +#define SG_MEMCONF 0x0400 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) @@ -54,22 +62,22 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) -#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500) -#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) -#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) +#define SG_USBPHYCTRL 0x0500 +#define SG_ETPHYPSHUT 0x0554 +#define SG_ETPHYCNT 0x0550 /* Pin Control */ -#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) +#define SG_PINCTRL_BASE 0x1000 /* PH1-Pro4, PH1-Pro5 */ -#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) +#define SG_LOADPINCTRL 0x1700 /* Input Enable */ -#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) +#define SG_IECTRL 0x1d00 /* Pin Monitor */ -#define SG_PINMON0 (SG_DBG_BASE | 0x0100) -#define SG_PINMON2 (SG_DBG_BASE | 0x0108) +#define SG_PINMON0 0x00100100 +#define SG_PINMON2 0x00100108 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) diff --git a/arch/arm/mach-uniphier/soc-info.c b/arch/arm/mach-uniphier/soc-info.c index ce2d4b6dea4..f021a8cab33 100644 --- a/arch/arm/mach-uniphier/soc-info.c +++ b/arch/arm/mach-uniphier/soc-info.c @@ -13,7 +13,7 @@ static unsigned int __uniphier_get_revision_field(unsigned int mask, unsigned int shift) { - u32 revision = readl(SG_REVISION); + u32 revision = readl(sg_base + SG_REVISION); return (revision >> shift) & mask; } diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index c328258901a..a7a566c0d8b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -487,6 +487,10 @@ }; }; + pci_ep: pci_ep { + compatible = "sandbox,pci_ep"; + }; + probing { compatible = "simple-bus"; test1 { diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index e956a05262f..7ec9b610083 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -177,4 +177,12 @@ int sandbox_get_beep_frequency(struct udevice *dev); */ int sandbox_get_pch_spi_protect(struct udevice *dev); +/** + * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count + * + * @dev: Device to check + * @return irq count + */ +int sandbox_get_pci_ep_irq_count(struct udevice *dev); + #endif diff --git a/cmd/Kconfig b/cmd/Kconfig index cda7931fe36..3afb760a816 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -631,6 +631,23 @@ config CMD_ADC Shows ADC device info and permit printing one-shot analog converted data from a named Analog to Digital Converter. +config CMD_BCB + bool "bcb" + depends on MMC + depends on PARTITIONS + help + Read/modify/write the fields of Bootloader Control Block, usually + stored on the flash "misc" partition with its structure defined in: + https://android.googlesource.com/platform/bootable/recovery/+/master/ + bootloader_message/include/bootloader_message/bootloader_message.h + + Some real-life use-cases include (but are not limited to): + - Determine the "boot reason" (and act accordingly): + https://source.android.com/devices/bootloader/boot-reason + - Get/pass a list of commands from/to recovery: + https://android.googlesource.com/platform/bootable/recovery + - Inspect/dump the contents of the BCB fields + config CMD_BIND bool "bind/unbind - Bind or unbind a device to/from a driver" depends on DM diff --git a/cmd/Makefile b/cmd/Makefile index f982564ab9f..49e64cde1d0 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_CMD_ADC) += adc.o obj-$(CONFIG_CMD_ARMFLASH) += armflash.o obj-y += blk_common.o obj-$(CONFIG_CMD_SOURCE) += source.o +obj-$(CONFIG_CMD_BCB) += bcb.o obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-$(CONFIG_CMD_BEDBUG) += bedbug.o obj-$(CONFIG_CMD_BIND) += bind.o diff --git a/cmd/bcb.c b/cmd/bcb.c new file mode 100644 index 00000000000..2bd5a744deb --- /dev/null +++ b/cmd/bcb.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Eugeniu Rosca <rosca.eugeniu@gmail.com> + * + * Command to read/modify/write Android BCB fields + */ + +#include <android_bootloader_message.h> +#include <command.h> +#include <common.h> + +enum bcb_cmd { + BCB_CMD_LOAD, + BCB_CMD_FIELD_SET, + BCB_CMD_FIELD_CLEAR, + BCB_CMD_FIELD_TEST, + BCB_CMD_FIELD_DUMP, + BCB_CMD_STORE, +}; + +static int bcb_dev = -1; +static int bcb_part = -1; +static struct bootloader_message bcb = { { 0 } }; + +static int bcb_cmd_get(char *cmd) +{ + if (!strncmp(cmd, "load", sizeof("load"))) + return BCB_CMD_LOAD; + if (!strncmp(cmd, "set", sizeof("set"))) + return BCB_CMD_FIELD_SET; + if (!strncmp(cmd, "clear", sizeof("clear"))) + return BCB_CMD_FIELD_CLEAR; + if (!strncmp(cmd, "test", sizeof("test"))) + return BCB_CMD_FIELD_TEST; + if (!strncmp(cmd, "store", sizeof("store"))) + return BCB_CMD_STORE; + if (!strncmp(cmd, "dump", sizeof("dump"))) + return BCB_CMD_FIELD_DUMP; + else + return -1; +} + +static int bcb_is_misused(int argc, char *const argv[]) +{ + int cmd = bcb_cmd_get(argv[0]); + + switch (cmd) { + case BCB_CMD_LOAD: + if (argc != 3) + goto err; + break; + case BCB_CMD_FIELD_SET: + if (argc != 3) + goto err; + break; + case BCB_CMD_FIELD_TEST: + if (argc != 4) + goto err; + break; + case BCB_CMD_FIELD_CLEAR: + if (argc != 1 && argc != 2) + goto err; + break; + case BCB_CMD_STORE: + if (argc != 1) + goto err; + break; + case BCB_CMD_FIELD_DUMP: + if (argc != 2) + goto err; + break; + default: + printf("Error: 'bcb %s' not supported\n", argv[0]); + return -1; + } + + if (cmd != BCB_CMD_LOAD && (bcb_dev < 0 || bcb_part < 0)) { + printf("Error: Please, load BCB first!\n"); + return -1; + } + + return 0; +err: + printf("Error: Bad usage of 'bcb %s'\n", argv[0]); + + return -1; +} + +static int bcb_field_get(char *name, char **field, int *size) +{ + if (!strncmp(name, "command", sizeof("command"))) { + *field = bcb.command; + *size = sizeof(bcb.command); + } else if (!strncmp(name, "status", sizeof("status"))) { + *field = bcb.status; + *size = sizeof(bcb.status); + } else if (!strncmp(name, "recovery", sizeof("recovery"))) { + *field = bcb.recovery; + *size = sizeof(bcb.recovery); + } else if (!strncmp(name, "stage", sizeof("stage"))) { + *field = bcb.stage; + *size = sizeof(bcb.stage); + } else if (!strncmp(name, "reserved", sizeof("reserved"))) { + *field = bcb.reserved; + *size = sizeof(bcb.reserved); + } else { + printf("Error: Unknown bcb field '%s'\n", name); + return -1; + } + + return 0; +} + +static int +do_bcb_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct blk_desc *desc; + disk_partition_t info; + u64 cnt; + char *endp; + int part, ret; + + ret = blk_get_device_by_str("mmc", argv[1], &desc); + if (ret < 0) + goto err_1; + + part = simple_strtoul(argv[2], &endp, 0); + if (*endp == '\0') { + ret = part_get_info(desc, part, &info); + if (ret) + goto err_1; + } else { + part = part_get_info_by_name(desc, argv[2], &info); + if (part < 0) { + ret = part; + goto err_1; + } + } + + cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz); + if (cnt > info.size) + goto err_2; + + if (blk_dread(desc, info.start, cnt, &bcb) != cnt) { + ret = -EIO; + goto err_1; + } + + bcb_dev = desc->devnum; + bcb_part = part; + debug("%s: Loaded from mmc %d:%d\n", __func__, bcb_dev, bcb_part); + + return CMD_RET_SUCCESS; +err_1: + printf("Error: mmc %s:%s read failed (%d)\n", argv[1], argv[2], ret); + goto err; +err_2: + printf("Error: mmc %s:%s too small!", argv[1], argv[2]); + goto err; +err: + bcb_dev = -1; + bcb_part = -1; + + return CMD_RET_FAILURE; +} + +static int do_bcb_set(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int size, len; + char *field, *str, *found; + + if (bcb_field_get(argv[1], &field, &size)) + return CMD_RET_FAILURE; + + len = strlen(argv[2]); + if (len >= size) { + printf("Error: sizeof('%s') = %d >= %d = sizeof(bcb.%s)\n", + argv[2], len, size, argv[1]); + return CMD_RET_FAILURE; + } + str = argv[2]; + + field[0] = '\0'; + while ((found = strsep(&str, ":"))) { + if (field[0] != '\0') + strcat(field, "\n"); + strcat(field, found); + } + + return CMD_RET_SUCCESS; +} + +static int do_bcb_clear(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int size; + char *field; + + if (argc == 1) { + memset(&bcb, 0, sizeof(bcb)); + return CMD_RET_SUCCESS; + } + + if (bcb_field_get(argv[1], &field, &size)) + return CMD_RET_FAILURE; + + memset(field, 0, size); + + return CMD_RET_SUCCESS; +} + +static int do_bcb_test(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int size; + char *field; + char *op = argv[2]; + + if (bcb_field_get(argv[1], &field, &size)) + return CMD_RET_FAILURE; + + if (*op == '=' && *(op + 1) == '\0') { + if (!strncmp(argv[3], field, size)) + return CMD_RET_SUCCESS; + else + return CMD_RET_FAILURE; + } else if (*op == '~' && *(op + 1) == '\0') { + if (!strstr(field, argv[3])) + return CMD_RET_FAILURE; + else + return CMD_RET_SUCCESS; + } else { + printf("Error: Unknown operator '%s'\n", op); + } + + return CMD_RET_FAILURE; +} + +static int do_bcb_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int size; + char *field; + + if (bcb_field_get(argv[1], &field, &size)) + return CMD_RET_FAILURE; + + print_buffer((ulong)field - (ulong)&bcb, (void *)field, 1, size, 16); + + return CMD_RET_SUCCESS; +} + +static int do_bcb_store(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct blk_desc *desc; + disk_partition_t info; + u64 cnt; + int ret; + + desc = blk_get_devnum_by_type(IF_TYPE_MMC, bcb_dev); + if (!desc) { + ret = -ENODEV; + goto err; + } + + ret = part_get_info(desc, bcb_part, &info); + if (ret) + goto err; + + cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz); + + if (blk_dwrite(desc, info.start, cnt, &bcb) != cnt) { + ret = -EIO; + goto err; + } + + return CMD_RET_SUCCESS; +err: + printf("Error: mmc %d:%d write failed (%d)\n", bcb_dev, bcb_part, ret); + + return CMD_RET_FAILURE; +} + +static cmd_tbl_t cmd_bcb_sub[] = { + U_BOOT_CMD_MKENT(load, CONFIG_SYS_MAXARGS, 1, do_bcb_load, "", ""), + U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 1, do_bcb_set, "", ""), + U_BOOT_CMD_MKENT(clear, CONFIG_SYS_MAXARGS, 1, do_bcb_clear, "", ""), + U_BOOT_CMD_MKENT(test, CONFIG_SYS_MAXARGS, 1, do_bcb_test, "", ""), + U_BOOT_CMD_MKENT(dump, CONFIG_SYS_MAXARGS, 1, do_bcb_dump, "", ""), + U_BOOT_CMD_MKENT(store, CONFIG_SYS_MAXARGS, 1, do_bcb_store, "", ""), +}; + +static int do_bcb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_bcb_sub, ARRAY_SIZE(cmd_bcb_sub)); + if (!c) + return CMD_RET_USAGE; + + if (bcb_is_misused(argc, argv)) { + /* We try to improve the user experience by reporting the + * root-cause of misusage, so don't return CMD_RET_USAGE, + * since the latter prints out the full-blown help text + */ + return CMD_RET_FAILURE; + } + + return c->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + bcb, CONFIG_SYS_MAXARGS, 1, do_bcb, + "Load/set/clear/test/dump/store Android BCB fields", + "load <dev> <part> - load BCB from mmc <dev>:<part>\n" + "bcb set <field> <val> - set BCB <field> to <val>\n" + "bcb clear [<field>] - clear BCB <field> or all fields\n" + "bcb test <field> <op> <val> - test BCB <field> against <val>\n" + "bcb dump <field> - dump BCB <field>\n" + "bcb store - store BCB back to mmc\n" + "\n" + "Legend:\n" + "<dev> - MMC device index containing the BCB partition\n" + "<part> - MMC partition index or name containing the BCB\n" + "<field> - one of {command,status,recovery,stage,reserved}\n" + "<op> - the binary operator used in 'bcb test':\n" + " '=' returns true if <val> matches the string stored in <field>\n" + " '~' returns true if <val> matches a subset of <field>'s string\n" + "<val> - string/text provided as input to bcb {set,test}\n" + " NOTE: any ':' character in <val> will be replaced by line feed\n" + " during 'bcb set' and used as separator by upper layers\n" +); diff --git a/cmd/bootm.c b/cmd/bootm.c index c3a063474ac..41b341e2e53 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -249,7 +249,7 @@ static int image_info(ulong addr) printf("\n## Checking Image at %08lx ...\n", addr); switch (genimg_get_format(hdr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: puts(" Legacy image found\n"); if (!image_check_magic(hdr)) { @@ -337,7 +337,7 @@ static int do_imls_nor(void) goto next_sector; switch (genimg_get_format(hdr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: if (!image_check_hcrc(hdr)) goto next_sector; @@ -485,7 +485,7 @@ static int do_imls_nand(void) } switch (genimg_get_format(buffer)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: header = (const image_header_t *)buffer; diff --git a/cmd/disk.c b/cmd/disk.c index dcc36a6c2cb..9e635c1172d 100644 --- a/cmd/disk.c +++ b/cmd/disk.c @@ -15,7 +15,7 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, ulong addr = CONFIG_SYS_LOAD_ADDR; ulong cnt; disk_partition_t info; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) image_header_t *hdr; #endif struct blk_desc *dev_desc; @@ -62,7 +62,7 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ); switch (genimg_get_format((void *) addr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: hdr = (image_header_t *) addr; diff --git a/cmd/fdc.c b/cmd/fdc.c index 906845d4049..7bfaae0e381 100644 --- a/cmd/fdc.c +++ b/cmd/fdc.c @@ -634,7 +634,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; FDC_COMMAND_STRUCT *pCMD = &cmd; unsigned long addr,imsize; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) image_header_t *hdr; /* used for fdc boot */ #endif unsigned char boot_drive; @@ -690,7 +690,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } switch (genimg_get_format ((void *)addr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: hdr = (image_header_t *)addr; image_print_contents (hdr); diff --git a/cmd/fpga.c b/cmd/fpga.c index b1f224bc6ad..bc48abdd6d8 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -280,7 +280,7 @@ static int do_fpga_loadmk(cmd_tbl_t *cmdtp, int flag, int argc, } switch (genimg_get_format(fpga_data)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: { image_header_t *hdr = (image_header_t *)fpga_data; diff --git a/cmd/nand.c b/cmd/nand.c index a22945d144b..899d5045337 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -846,7 +846,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, struct mtd_info *mtd, int r; char *s; size_t cnt; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) image_header_t *hdr; #endif #if defined(CONFIG_FIT) @@ -874,7 +874,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, struct mtd_info *mtd, bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ); switch (genimg_get_format ((void *)addr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: hdr = (image_header_t *)addr; diff --git a/cmd/source.c b/cmd/source.c index 6d98a1cfd32..1a9a71aa374 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -44,7 +44,7 @@ int source (ulong addr, const char *fit_uname) { ulong len; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) const image_header_t *hdr; #endif u32 *data; @@ -61,7 +61,7 @@ source (ulong addr, const char *fit_uname) buf = map_sysmem(addr, 0); switch (genimg_get_format(buf)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: hdr = buf; diff --git a/cmd/ximg.c b/cmd/ximg.c index 32bfae8b22b..9e53cc45572 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -35,7 +35,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) ulong data, len; int verify; int part = 0; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) ulong count; image_header_t *hdr = NULL; #endif @@ -67,7 +67,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } switch (genimg_get_format((void *)addr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: printf("## Copying part %d from legacy image " @@ -217,7 +217,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } break; #endif -#if defined(CONFIG_BZIP2) && defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_BZIP2) && defined(CONFIG_LEGACY_IMAGE_FORMAT) case IH_COMP_BZIP2: { int i; diff --git a/common/bootm.c b/common/bootm.c index d1937516478..bea516025fd 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -98,7 +98,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, /* get image parameters */ switch (genimg_get_format(os_hdr)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: images.os.type = image_get_type(os_hdr); images.os.comp = image_get_comp(os_hdr); @@ -738,7 +738,7 @@ err: return ret; } -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) /** * image_get_kernel - verify legacy format kernel image * @img_addr: in RAM address of the legacy format image to be verified @@ -807,7 +807,7 @@ static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], bootm_headers_t *images, ulong *os_data, ulong *os_len) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) image_header_t *hdr; #endif ulong img_addr; @@ -828,7 +828,7 @@ static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, *os_data = *os_len = 0; buf = map_sysmem(img_addr, 0); switch (genimg_get_format(buf)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: printf("## Booting kernel from Legacy Image at %08lx ...\n", img_addr); diff --git a/common/image-fdt.c b/common/image-fdt.c index eb552ca207c..e70da3dcb33 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -33,7 +33,7 @@ static void fdt_error(const char *msg) puts(" - must RESET the board to recover.\n"); } -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) static const image_header_t *image_get_fdt(ulong fdt_addr) { const image_header_t *fdt_hdr = map_sysmem(fdt_addr, 0); @@ -263,7 +263,7 @@ error: int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, bootm_headers_t *images, char **of_flat_tree, ulong *of_size) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) const image_header_t *fdt_hdr; ulong load, load_end; ulong image_start, image_data, image_end; @@ -344,7 +344,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, */ buf = map_sysmem(fdt_addr, 0); switch (genimg_get_format(buf)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: /* verify fdt_addr points to a valid image header */ printf("## Flattened Device Tree from Legacy Image at %08lx\n", diff --git a/common/image.c b/common/image.c index 75b84d50091..9f9538fac2f 100644 --- a/common/image.c +++ b/common/image.c @@ -38,7 +38,7 @@ extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, int verify); #endif @@ -377,7 +377,7 @@ void image_print_contents(const void *ptr) #ifndef USE_HOSTCC -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) /** * image_get_ramdisk - get and verify ramdisk image * @rd_addr: ramdisk image start address @@ -867,7 +867,7 @@ ulong genimg_get_kernel_addr(char * const img_addr) */ int genimg_get_format(const void *img_addr) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) const image_header_t *hdr; hdr = (const image_header_t *)img_addr; @@ -933,7 +933,7 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, { ulong rd_addr, rd_load; ulong rd_data, rd_len; -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) const image_header_t *rd_hdr; #endif void *buf; @@ -1025,7 +1025,7 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, */ buf = map_sysmem(rd_addr, 0); switch (genimg_get_format(buf)) { -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: printf("## Loading init Ramdisk from Legacy " "Image at %08lx ...\n", rd_addr); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 802166131c5..a48617ddcd0 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -158,7 +158,7 @@ config SPL_RAW_IMAGE_SUPPORT config SPL_LEGACY_IMAGE_SUPPORT bool "Support SPL loading and booting of Legacy images" - default y if !TI_SECURE_DEVICE + default y if !TI_SECURE_DEVICE && !SPL_LOAD_FIT help SPL will support loading and booting Legacy images when this option is y. If this is not set, SPL will move on to other available diff --git a/common/spl/spl.c b/common/spl/spl.c index 4ddeff9b51e..d5e3f680f4c 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -535,7 +535,7 @@ static int spl_load_image(struct spl_image_info *spl_image, } /** - * boot_from_devices() - Try loading an booting U-Boot from a list of devices + * boot_from_devices() - Try loading a booting U-Boot from a list of devices * * @spl_image: Place to put the image details if successful * @spl_boot_list: List of boot devices to try diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index dfd69069c7c..5eafbaaa5a6 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index d331e4e807f..49731ee230f 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -10,7 +10,7 @@ CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig index 4edade457b6..1a1167b2a67 100644 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -9,7 +9,7 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset" diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 707d2709208..a456e3b575e 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -12,7 +12,7 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset" diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 154a0756826..31ed63c000d 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -117,7 +117,7 @@ CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=1 diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 6801ff00eb2..b86b9e8773b 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 1657298cf3d..4ea0803ab54 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index d52b18c9397..268c9098826 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -17,7 +17,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 68e371df3a9..b15c547e372 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -19,7 +19,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 1657298cf3d..4ea0803ab54 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 3d164c0685d..712c79f54e0 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -14,7 +14,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 4d3bef81a37..8a7b1ad6d55 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 68e16bb4be7..d24027cd69c 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 92f5bd031cf..584d7662624 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 8ed5ea4a835..80f7cb3e037 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig index 7d7cdf04eaa..aa76633802a 100644 --- a/configs/linkit-smart-7688-ram_defconfig +++ b/configs/linkit-smart-7688-ram_defconfig @@ -7,7 +7,7 @@ CONFIG_BOARD_LINKIT_SMART_7688=y CONFIG_MIPS_BOOT_FDT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index b3acbbc2c73..3750e59a4b6 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -10,7 +10,7 @@ CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y CONFIG_MIPS_BOOT_FDT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 075045bdc73..ac1bac877dd 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -15,7 +15,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 83f78776b7d..3908ff80d6b 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -1,7 +1,9 @@ CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARCH_UNIPHIER_V8_MULTI=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 19fac901221..012ba3ebbeb 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_COUNTER_FREQUENCY=2720000 -# CONFIG_IMAGE_FORMAT_LEGACY is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index aa9dd230b5f..93fa7d8f6bd 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set -# CONFIG_IMAGE_FORMAT_LEGACY is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index d3cc8511762..b0bc84d55ec 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -11,7 +11,7 @@ CONFIG_ZYNQMP_NO_DDR=y # CONFIG_PSCI_RESET is not set # CONFIG_CMD_ZYNQMP is not set # CONFIG_EXPERT is not set -# CONFIG_IMAGE_FORMAT_LEGACY is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_TEXT_BASE=0xfffc0000 diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 35ebd144850..4d914ea725e 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -13,7 +13,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index 944c11381b3..1e15889bda9 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -14,7 +14,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index a48f203c167..1fceccdc09d 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index d105b71c280..0908fc767c6 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -13,7 +13,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 3c4103f1f8a..2ff263034a8 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -14,7 +14,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 3124de9795f..33f26a6f2ab 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -16,7 +16,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 3b59cf2473c..55ae55edc48 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -14,7 +14,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 6d377e94fbe..7792ba29a01 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -15,7 +15,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig index fc2d3f362ca..3a3740629b2 100644 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@ -15,7 +15,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 0767e91b07b..d777ba889e1 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 9eb67cf4ec8..c5288e56e35 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index b5dbe405e05..e47cce5e070 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -13,7 +13,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 0ad92849dde..ee15d83147f 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -13,7 +13,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index d434982df3d..43b746f56cd 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -13,7 +13,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/doc/README.avb2 b/doc/android/avb2.txt index a29cee1b6f5..a29cee1b6f5 100644 --- a/doc/README.avb2 +++ b/doc/android/avb2.txt diff --git a/doc/android/bcb.txt b/doc/android/bcb.txt new file mode 100644 index 00000000000..7b7177cacf2 --- /dev/null +++ b/doc/android/bcb.txt @@ -0,0 +1,89 @@ +Android Bootloader Control Block (BCB) + +The purpose behind this file is to: + - give an overview of BCB w/o duplicating public documentation + - describe the main BCB use-cases which concern U-Boot + - reflect current support status in U-Boot + - mention any relevant U-Boot build-time tunables + - precisely exemplify one or more use-cases + +Additions and fixes are welcome! + + +1. OVERVIEW +--------------------------------- +Bootloader Control Block (BCB) is a well established term/acronym in +the Android namespace which refers to a location in a dedicated raw +(i.e. FS-unaware) flash (e.g. eMMC) partition, usually called "misc", +which is used as media for exchanging messages between Android userspace +(particularly recovery [1]) and an Android-capable bootloader. + +On higher level, BCB provides a way to implement a subset of Android +Bootloader Requirements [2], amongst which are: + - Android-specific bootloader flow [3] + - Get the "reboot reason" (and act accordingly) [4] + - Get/pass a list of commands from/to recovery [1] + - TODO + + +2. 'BCB'. SHELL COMMAND OVERVIEW +----------------------------------- +The 'bcb' command provides a CLI to facilitate the development of the +requirements enumerated above. Below is the command's help message: + +=> bcb +bcb - Load/set/clear/test/dump/store Android BCB fields + +Usage: +bcb load <dev> <part> - load BCB from mmc <dev>:<part> +bcb set <field> <val> - set BCB <field> to <val> +bcb clear [<field>] - clear BCB <field> or all fields +bcb test <field> <op> <val> - test BCB <field> against <val> +bcb dump <field> - dump BCB <field> +bcb store - store BCB back to mmc + +Legend: +<dev> - MMC device index containing the BCB partition +<part> - MMC partition index or name containing the BCB +<field> - one of {command,status,recovery,stage,reserved} +<op> - the binary operator used in 'bcb test': + '=' returns true if <val> matches the string stored in <field> + '~' returns true if <val> matches a subset of <field>'s string +<val> - string/text provided as input to bcb {set,test} + NOTE: any ':' character in <val> will be replaced by line feed + during 'bcb set' and used as separator by upper layers + + +3. 'BCB'. EXAMPLE OF GETTING REBOOT REASON +----------------------------------- +if bcb load 1 misc; then + # valid BCB found + if bcb test command = bootonce-bootloader; then + bcb clear command; bcb store; + # do the equivalent of AOSP ${fastbootcmd} + # i.e. call fastboot + else if bcb test command = boot-recovery; then + bcb clear command; bcb store; + # do the equivalent of AOSP ${recoverycmd} + # i.e. do anything required for booting into recovery + else + # boot Android OS normally + fi +else + # corrupted/non-existent BCB + # report error or boot non-Android OS (platform-specific) +fi + + +4. ENABLE ON YOUR BOARD +----------------------------------- +The following Kconfig options must be enabled: +CONFIG_PARTITIONS=y +CONFIG_MMC=y +CONFIG_BCB=y + +[1] https://android.googlesource.com/platform/bootable/recovery +[2] https://source.android.com/devices/bootloader +[3] https://patchwork.ozlabs.org/patch/746835/ + ("[U-Boot,5/6] Initial support for the Android Bootloader flow") +[4] https://source.android.com/devices/bootloader/boot-reason diff --git a/doc/README.android-fastboot b/doc/android/fastboot.txt index 431191c473f..431191c473f 100644 --- a/doc/README.android-fastboot +++ b/doc/android/fastboot.txt diff --git a/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt new file mode 100644 index 00000000000..77054305593 --- /dev/null +++ b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt @@ -0,0 +1,18 @@ +* Cadence PCIe endpoint controller + +Required properties: +- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. +- reg: Should contain the controller register base address. + +Optional properties: +- max-functions: Maximum number of functions that can be configured (default 1). +- cdns,max-outbound-regions: Set to maximum number of outbound regions (default 8) + +Example: + +pcie_ep@fc000000 { + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0 0xfc000000 0x0 0x01000000>; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <8>; +}; diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index bfff6fdc733..78b59e7203f 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -335,7 +335,7 @@ CONFIG_RSA - enable RSA algorithm for signing WARNING: When relying on signed FIT images with required signature check the legacy image format is default disabled by not defining -CONFIG_IMAGE_FORMAT_LEGACY +CONFIG_LEGACY_IMAGE_FORMAT Testing ------- diff --git a/drivers/Kconfig b/drivers/Kconfig index 96ff4f566ab..5a9d01b5088 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -66,6 +66,8 @@ source "drivers/nvme/Kconfig" source "drivers/pci/Kconfig" +source "drivers/pci_endpoint/Kconfig" + source "drivers/pch/Kconfig" source "drivers/pcmcia/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 6635dabd2ca..603aa985901 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ obj-$(CONFIG_NVME) += nvme/ +obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/ obj-y += pcmcia/ obj-y += dfu/ obj-$(CONFIG_PCH) += pch/ diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 487b43ebdab..c627a4bf851 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -18,8 +18,8 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\ defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) - UNIPHIER_LD4_SYS_CLK_NAND(2), - UNIPHIER_CLK_RATE(3, 200000000), + UNIPHIER_LD4_SYS_CLK_NAND(2), /* nand */ + UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */ UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ @@ -35,8 +35,9 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) - UNIPHIER_LD11_SYS_CLK_NAND(2), - UNIPHIER_CLK_RATE(3, 200000000), + UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */ + UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */ + UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ @@ -48,8 +49,9 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) - UNIPHIER_LD11_SYS_CLK_NAND(2), - UNIPHIER_CLK_RATE(3, 200000000), + UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */ + UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */ + UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 341527acc5e..07a3356b3c8 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -363,6 +363,7 @@ static const struct udevice_id pca953x_ids[] = { { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), }, { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, + { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), }, diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig new file mode 100644 index 00000000000..19cfa0aafb5 --- /dev/null +++ b/drivers/pci_endpoint/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# PCI Endpoint Support +# + +menu "PCI Endpoint" + +config PCI_ENDPOINT + bool "PCI Endpoint Support" + depends on DM + help + Enable this configuration option to support configurable PCI + endpoints. This should be enabled if the platform has a PCI + controllers that can operate in endpoint mode (as a device + connected to PCI host or bridge). + +config PCIE_CADENCE_EP + bool "Cadence PCIe endpoint controller" + depends on PCI_ENDPOINT + help + Say Y here if you want to support the Cadence PCIe controller in + endpoint mode. This PCIe controller may be embedded into many + different vendors SoCs. + +config PCI_SANDBOX_EP + bool "Sandbox PCIe endpoint controller" + depends on PCI_ENDPOINT + help + Say Y here if you want to support the Sandbox PCIe controller in + endpoint mode. + The sandbox driver act as a dummy driver which stores and + retrieves PCIe endpoint configuration as is. + +endmenu diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile new file mode 100644 index 00000000000..3cd987259d3 --- /dev/null +++ b/drivers/pci_endpoint/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2019 +# Ramon Fried <ramon.fried@gmail.com> + +obj-y += pci_ep-uclass.o +obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o +obj-$(CONFIG_PCI_SANDBOX_EP) += sandbox-pci_ep.o diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c new file mode 100644 index 00000000000..2f9c70398d7 --- /dev/null +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCI Endpoint uclass + * + * Based on Linux PCI-EP driver written by + * Kishon Vijay Abraham I <kishon@ti.com> + * + * Copyright (c) 2019 + * Written by Ramon Fried <ramon.fried@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <linux/log2.h> +#include <pci_ep.h> + +DECLARE_GLOBAL_DATA_PTR; + +int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->write_header) + return -ENOSYS; + + return ops->write_header(dev, fn, hdr); +} + +int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->read_header) + return -ENOSYS; + + return ops->read_header(dev, fn, hdr); +} + +int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + int flags = ep_bar->flags; + + /* Some basic bar validity checks */ + if (ep_bar->barno > BAR_5 || ep_bar < BAR_0) + return -EINVAL; + + if ((ep_bar->barno == BAR_5 && + (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) || + ((flags & PCI_BASE_ADDRESS_SPACE_IO) && + (flags & PCI_BASE_ADDRESS_IO_MASK)) || + (upper_32_bits(ep_bar->size) && + !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))) + return -EINVAL; + + if (!ops->set_bar) + return -ENOSYS; + + return ops->set_bar(dev, func_no, ep_bar); +} + +int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar, + enum pci_barno barno) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + /* Some basic bar validity checks */ + if (barno > BAR_5 || barno < BAR_0) + return -EINVAL; + + if (!ops->read_bar) + return -ENOSYS; + + return ops->read_bar(dev, func_no, ep_bar, barno); +} + +int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->clear_bar) + return -ENOSYS; + + return ops->clear_bar(dev, func_num, bar); +} + +int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr, + u64 pci_addr, size_t size) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->map_addr) + return -ENOSYS; + + return ops->map_addr(dev, func_no, addr, pci_addr, size); +} + +int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->unmap_addr) + return -ENOSYS; + + return ops->unmap_addr(dev, func_no, addr); +} + +int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + uint encode_int; + + if (interrupts > 32) + return -EINVAL; + + if (!ops->set_msi) + return -ENOSYS; + + /* MSI spec permits allocation of + * only 1, 2, 4, 8, 16, 32 interrupts + */ + encode_int = order_base_2(interrupts); + + return ops->set_msi(dev, func_no, encode_int); +} + +int pci_ep_get_msi(struct udevice *dev, uint func_no) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + int interrupt; + + if (!ops->get_msi) + return -ENOSYS; + + interrupt = ops->get_msi(dev, func_no); + + if (interrupt < 0) + return 0; + + /* Translate back from order base 2*/ + interrupt = 1 << interrupt; + + return interrupt; +} + +int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (interrupts < 1 || interrupts > 2048) + return -EINVAL; + + if (!ops->set_msix) + return -ENOSYS; + + return ops->set_msix(dev, func_no, interrupts - 1); +} + +int pci_ep_get_msix(struct udevice *dev, uint func_no) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + int interrupt; + + if (!ops->get_msix) + return -ENOSYS; + + interrupt = ops->get_msix(dev, func_no); + + if (interrupt < 0) + return 0; + + return interrupt + 1; +} + +int pci_ep_raise_irq(struct udevice *dev, uint func_no, + enum pci_ep_irq_type type, uint interrupt_num) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->raise_irq) + return -ENOSYS; + + return ops->raise_irq(dev, func_no, type, interrupt_num); +} + +int pci_ep_start(struct udevice *dev) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->start) + return -ENOSYS; + + return ops->start(dev); +} + +int pci_ep_stop(struct udevice *dev) +{ + struct pci_ep_ops *ops = pci_ep_get_ops(dev); + + if (!ops->stop) + return -ENOSYS; + + return ops->stop(dev); +} + +UCLASS_DRIVER(pci_ep) = { + .id = UCLASS_PCI_EP, + .name = "pci_ep", + .flags = DM_UC_FLAG_SEQ_ALIAS, +}; diff --git a/drivers/pci_endpoint/pcie-cadence-ep.c b/drivers/pci_endpoint/pcie-cadence-ep.c new file mode 100644 index 00000000000..59231d340a5 --- /dev/null +++ b/drivers/pci_endpoint/pcie-cadence-ep.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 + * Written by Ramon Fried <ramon.fried@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci_ep.h> +#include <linux/sizes.h> +#include <linux/log2.h> +#include "pcie-cadence.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int cdns_write_header(struct udevice *dev, uint fn, + struct pci_ep_header *hdr) +{ + struct cdns_pcie *pcie = dev_get_priv(dev); + + cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, + hdr->progif_code); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, + hdr->subclass_code | + hdr->baseclass_code << 8); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, + hdr->cache_line_size); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, + hdr->subsys_id); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, + hdr->interrupt_pin); + + /* + * Vendor ID can only be modified from function 0, all other functions + * use the same vendor ID as function 0. + */ + if (fn == 0) { + /* Update the vendor IDs. */ + u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | + CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); + + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + return 0; +} + +static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar) +{ + struct cdns_pcie *pcie = dev_get_priv(dev); + dma_addr_t bar_phys = ep_bar->phys_addr; + enum pci_barno bar = ep_bar->barno; + int flags = ep_bar->flags; + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u64 sz; + + /* BAR size is 2^(aperture + 7) */ + sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE); + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + sz = 1ULL << fls64(sz - 1); + aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ + + if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS; + } else { + bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); + bool is_64bits = (sz > SZ_2G) | + !!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (is_64bits && (bar & 1)) + return -EINVAL; + + if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) + ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; + + if (is_64bits && is_prefetch) + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; + else if (is_prefetch) + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; + else if (is_64bits) + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS; + else + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS; + } + + addr0 = lower_32_bits(bar_phys); + addr1 = upper_32_bits(bar_phys); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), + addr0); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), + addr1); + + if (bar < BAR_4) { + reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); + b = bar; + } else { + reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); + b = bar - BAR_4; + } + + cfg = cdns_pcie_readl(pcie, reg); + cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | + CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); + cdns_pcie_writel(pcie, reg, cfg); + + return 0; +} + +static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc) +{ + struct cdns_pcie *pcie = dev_get_priv(dev); + u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + + /* + * Set the Multiple Message Capable bitfield into the Message Control + * register. + */ + u16 flags; + + flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); + flags |= PCI_MSI_FLAGS_64BIT; + flags &= ~PCI_MSI_FLAGS_MASKBIT; + cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); + + return 0; +} + +static struct pci_ep_ops cdns_pci_ep_ops = { + .write_header = cdns_write_header, + .set_bar = cdns_set_bar, + .set_msi = cdns_set_msi, +}; + +static int cdns_pci_ep_probe(struct udevice *dev) +{ + struct cdns_pcie *pdata = dev_get_priv(dev); + + pdata->reg_base = (void __iomem *)devfdt_get_addr(dev); + if (!pdata->reg_base) + return -ENOMEM; + + pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "max-functions", 1); + pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "cdns,max-outbound-regions", 8); + + return 0; +} + +static int cdns_pci_ep_remove(struct udevice *dev) +{ + return 0; +} + +const struct udevice_id cadence_pci_ep_of_match[] = { + { .compatible = "cdns,cdns-pcie-ep" }, + { } +}; + +U_BOOT_DRIVER(cdns_pcie) = { + .name = "cdns,pcie-ep", + .id = UCLASS_PCI_EP, + .of_match = cadence_pci_ep_of_match, + .ops = &cdns_pci_ep_ops, + .probe = cdns_pci_ep_probe, + .remove = cdns_pci_ep_remove, + .priv_auto_alloc_size = sizeof(struct cdns_pcie), +}; diff --git a/drivers/pci_endpoint/pcie-cadence.h b/drivers/pci_endpoint/pcie-cadence.h new file mode 100644 index 00000000000..91630d35c3f --- /dev/null +++ b/drivers/pci_endpoint/pcie-cadence.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cadence PCIe controlloer definitions + * Adapted from linux kernel driver. + * Copyright (c) 2017 Cadence + * + * Copyright (c) 2019 + * Written by Ramon Fried <ramon.fried@gmail.com> + */ + +#ifndef PCIE_CADENCE_H +#define PCIE_CADENCE_H + +#include <common.h> +#include <pci_ep.h> +#include <asm/io.h> + +/* + * Local Management Registers + */ +#define CDNS_PCIE_LM_BASE 0x00100000 + +/* Vendor ID Register */ +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +#define CDNS_PCIE_LM_ID_VENDOR(vid) \ + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) + +/* Root Port Requestor ID Register */ +#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +#define CDNS_PCIE_LM_RP_RID_(rid) \ + (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) + +/* Endpoint Bus and Device Number Register */ +#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) +#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 + +/* Endpoint Function f BAR b Configuration Registers */ +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ + (GENMASK(4, 0) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ + (GENMASK(7, 5) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) + +/* Endpoint Function Configuration Register */ +#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) + +/* Root Complex BAR Configuration Register */ +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) + +/* BAR control values applicable to both Endpoint Function and Root Complex */ +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 + +/* + * Endpoint Function Registers (PCI configuration space for endpoint functions) + */ +#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) + +#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 + +/* + * Root Port Registers (PCI configuration space for the root port function) + */ +#define CDNS_PCIE_RP_BASE 0x00200000 + +/* + * Address Translation Registers + */ +#define CDNS_PCIE_AT_BASE 0x00400000 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) + +/* Region r Outbound PCIe Descriptor Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd +/* Bit 23 MUST be set in RC mode. */ +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) + +/* Region r Outbound PCIe Descriptor Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ + (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) + +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + +enum cdns_pcie_rp_bar { + RP_BAR0, + RP_BAR1, + RP_NO_BAR +}; + +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) + +/* Normal/Vendor specific message access: offset inside some outbound region */ +#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ + (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ + (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +#define CDNS_PCIE_MSG_NO_DATA BIT(16) + +#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ + +enum cdns_pcie_msg_code { + MSG_CODE_ASSERT_INTA = 0x20, + MSG_CODE_ASSERT_INTB = 0x21, + MSG_CODE_ASSERT_INTC = 0x22, + MSG_CODE_ASSERT_INTD = 0x23, + MSG_CODE_DEASSERT_INTA = 0x24, + MSG_CODE_DEASSERT_INTB = 0x25, + MSG_CODE_DEASSERT_INTC = 0x26, + MSG_CODE_DEASSERT_INTD = 0x27, +}; + +enum cdns_pcie_msg_routing { + /* Route to Root Complex */ + MSG_ROUTING_TO_RC, + + /* Use Address Routing */ + MSG_ROUTING_BY_ADDR, + + /* Use ID Routing */ + MSG_ROUTING_BY_ID, + + /* Route as Broadcast Message from Root Complex */ + MSG_ROUTING_BCAST, + + /* Local message; terminate at receiver (INTx messages) */ + MSG_ROUTING_LOCAL, + + /* Gather & route to Root Complex (PME_TO_Ack message) */ + MSG_ROUTING_GATHER, +}; + +struct cdns_pcie { + void __iomem *reg_base; + u32 max_functions; + u32 max_regions; +}; + +/* Register access */ +static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) +{ + writeb(value, pcie->reg_base + reg); +} + +static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) +{ + writew(value, pcie->reg_base + reg); +} + +static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) +{ + writel(value, pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) +{ + return readl(pcie->reg_base + reg); +} + +/* Root Port register access */ +static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) +{ + writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + +static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, + u32 reg, u16 value) +{ + writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + +static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, + u32 reg, u32 value) +{ + writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + +/* Endpoint Function register access */ +static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, + u32 reg, u8 value) +{ + writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); +} + +static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, + u32 reg, u16 value) +{ + writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); +} + +static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, + u32 reg, u32 value) +{ + writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); +} + +static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) +{ + return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); +} + +static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) +{ + return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); +} + +static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) +{ + return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); +} + +#endif /* end of include guard: PCIE_CADENCE_H */ diff --git a/drivers/pci_endpoint/sandbox-pci_ep.c b/drivers/pci_endpoint/sandbox-pci_ep.c new file mode 100644 index 00000000000..0258433d8f9 --- /dev/null +++ b/drivers/pci_endpoint/sandbox-pci_ep.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Ramon Fried <ramon.fried@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> +#include <pci_ep.h> +#include <asm/test.h> + +/** + * struct sandbox_pci_ep_priv - private data for driver + * @hdr: Stores the EP device header + * @msix: required MSIx count; + * @msi: required MSI count; + */ +struct sandbox_pci_ep_priv { + struct pci_ep_header hdr; + struct pci_bar bars[6]; + int msix; + int msi; + int irq_count; +}; + +/* Method exported for testing purposes */ +int sandbox_get_pci_ep_irq_count(struct udevice *dev) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + return priv->irq_count; +} + +static const struct udevice_id sandbox_pci_ep_ids[] = { + { .compatible = "sandbox,pci_ep" }, + { } +}; + +static int sandbox_write_header(struct udevice *dev, uint fn, + struct pci_ep_header *hdr) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + memcpy(&priv->hdr, hdr, sizeof(*hdr)); + + return 0; +} + +static int sandbox_read_header(struct udevice *dev, uint fn, + struct pci_ep_header *hdr) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + memcpy(hdr, &priv->hdr, sizeof(*hdr)); + + return 0; +} + +static int sandbox_set_bar(struct udevice *dev, uint fn, + struct pci_bar *ep_bar) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + int bar_idx; + + if (fn > 0) + return -ENODEV; + + bar_idx = ep_bar->barno; + + memcpy(&priv->bars[bar_idx], ep_bar, sizeof(*ep_bar)); + + return 0; +} + +static int sandbox_read_bar(struct udevice *dev, uint fn, + struct pci_bar *ep_bar, enum pci_barno barno) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + int bar_idx; + + if (fn > 0) + return -ENODEV; + + bar_idx = ep_bar->barno; + + memcpy(ep_bar, &priv->bars[bar_idx], sizeof(*ep_bar)); + + return 0; +} + +static int sandbox_set_msi(struct udevice *dev, uint fn, uint interrupts) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + priv->msi = interrupts; + + return 0; +} + +static int sandbox_get_msi(struct udevice *dev, uint fn) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + return priv->msi; +} + +static int sandbox_set_msix(struct udevice *dev, uint fn, uint interrupts) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + priv->msix = interrupts; + + return 0; +} + +static int sandbox_get_msix(struct udevice *dev, uint fn) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + return priv->msix; +} + +static int sandbox_raise_irq(struct udevice *dev, uint fn, + enum pci_ep_irq_type type, uint interrupt_num) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + if (fn > 0) + return -ENODEV; + + priv->irq_count++; + + return 0; +} + +static int sandbox_pci_ep_probe(struct udevice *dev) +{ + struct sandbox_pci_ep_priv *priv = dev_get_priv(dev); + + memset(priv, 0, sizeof(*priv)); + return 0; +} + +static struct pci_ep_ops sandbox_pci_ep_ops = { + .write_header = sandbox_write_header, + .read_header = sandbox_read_header, + .set_bar = sandbox_set_bar, + .read_bar = sandbox_read_bar, + .set_msi = sandbox_set_msi, + .get_msi = sandbox_get_msi, + .set_msix = sandbox_set_msix, + .get_msix = sandbox_get_msix, + .raise_irq = sandbox_raise_irq, +}; + +U_BOOT_DRIVER(pci_ep_sandbox) = { + .name = "pci_ep_sandbox", + .id = UCLASS_PCI_EP, + .of_match = sandbox_pci_ep_ids, + .probe = sandbox_pci_ep_probe, + .ops = &sandbox_pci_ep_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_pci_ep_priv), +}; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f9b282313a2..509dd0ec589 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -293,6 +293,14 @@ config TI_QSPI Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. This driver support spi flash single, quad and memory reads. +config UNIPHIER_SPI + bool "Socionext UniPhier SPI driver" + depends on ARCH_UNIPHIER + help + Enable the Socionext UniPhier SPI driver. This driver can + be used to access SPI chips on platforms embedding this + UniPhier IP core. + config XILINX_SPI bool "Xilinx SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64c407e2edd..ab84122f083 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o +obj-$(CONFIG_UNIPHIER_SPI) += uniphier_spi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c new file mode 100644 index 00000000000..ef02d07aa46 --- /dev/null +++ b/drivers/spi/uniphier_spi.c @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * uniphier_spi.c - Socionext UniPhier SPI driver + * Copyright 2019 Socionext, Inc. + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <linux/io.h> +#include <spi.h> +#include <wait_bit.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SSI_CTL 0x00 +#define SSI_CTL_EN BIT(0) + +#define SSI_CKS 0x04 +#define SSI_CKS_CKRAT_MASK GENMASK(7, 0) +#define SSI_CKS_CKPHS BIT(14) +#define SSI_CKS_CKINIT BIT(13) +#define SSI_CKS_CKDLY BIT(12) + +#define SSI_TXWDS 0x08 +#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8) +#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6) +#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0) + +#define SSI_RXWDS 0x0c +#define SSI_RXWDS_RDTF_MASK GENMASK(7, 6) +#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0) + +#define SSI_FPS 0x10 +#define SSI_FPS_FSPOL BIT(15) +#define SSI_FPS_FSTRT BIT(14) + +#define SSI_SR 0x14 +#define SSI_SR_BUSY BIT(7) +#define SSI_SR_TNF BIT(5) +#define SSI_SR_RNE BIT(0) + +#define SSI_IE 0x18 + +#define SSI_IC 0x1c +#define SSI_IC_TCIC BIT(4) +#define SSI_IC_RCIC BIT(3) +#define SSI_IC_RORIC BIT(0) + +#define SSI_FC 0x20 +#define SSI_FC_TXFFL BIT(12) +#define SSI_FC_TXFTH_MASK GENMASK(11, 8) +#define SSI_FC_RXFFL BIT(4) +#define SSI_FC_RXFTH_MASK GENMASK(3, 0) + +#define SSI_XDR 0x24 /* TXDR for write, RXDR for read */ + +#define SSI_FIFO_DEPTH 8U + +#define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */ +#define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */ + +#define SSI_CLK 50000000 /* internal I/O clock: 50MHz */ + +struct uniphier_spi_platdata { + void __iomem *base; + u32 frequency; /* input frequency */ + u32 speed_hz; + uint deactivate_delay_us; /* Delay to wait after deactivate */ + uint activate_delay_us; /* Delay to wait after activate */ +}; + +struct uniphier_spi_priv { + void __iomem *base; + u8 mode; + u8 fifo_depth; + u8 bits_per_word; + ulong last_transaction_us; /* Time of last transaction end */ +}; + +static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable) +{ + u32 val; + + val = readl(priv->base + SSI_CTL); + if (enable) + val |= SSI_CTL_EN; + else + val &= ~SSI_CTL_EN; + writel(val, priv->base + SSI_CTL); +} + +static void uniphier_spi_regdump(struct uniphier_spi_priv *priv) +{ + pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL)); + pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS)); + pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS)); + pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS)); + pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS)); + pr_debug("SR %08x\n", readl(priv->base + SSI_SR)); + pr_debug("IE %08x\n", readl(priv->base + SSI_IE)); + pr_debug("IC %08x\n", readl(priv->base + SSI_IC)); + pr_debug("FC %08x\n", readl(priv->base + SSI_FC)); + pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR)); +} + +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_platdata *plat = bus->platdata; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + ulong delay_us; /* The delay completed so far */ + u32 val; + + /* If it's too soon to do another transaction, wait */ + if (plat->deactivate_delay_us && priv->last_transaction_us) { + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < plat->deactivate_delay_us) + udelay(plat->deactivate_delay_us - delay_us); + } + + val = readl(priv->base + SSI_FPS); + if (priv->mode & SPI_CS_HIGH) + val |= SSI_FPS_FSPOL; + else + val &= ~SSI_FPS_FSPOL; + writel(val, priv->base + SSI_FPS); + + if (plat->activate_delay_us) + udelay(plat->activate_delay_us); +} + +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_platdata *plat = bus->platdata; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val; + + val = readl(priv->base + SSI_FPS); + if (priv->mode & SPI_CS_HIGH) + val &= ~SSI_FPS_FSPOL; + else + val |= SSI_FPS_FSPOL; + writel(val, priv->base + SSI_FPS); + + /* Remember time of this transaction so we can honour the bus delay */ + if (plat->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); +} + +static int uniphier_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val, size; + + uniphier_spi_enable(priv, false); + + /* disable interrupts */ + writel(0, priv->base + SSI_IE); + + /* bits_per_word */ + size = priv->bits_per_word; + val = readl(priv->base + SSI_TXWDS); + val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK); + val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size); + val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size); + writel(val, priv->base + SSI_TXWDS); + + val = readl(priv->base + SSI_RXWDS); + val &= ~SSI_RXWDS_DTLEN_MASK; + val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size); + writel(val, priv->base + SSI_RXWDS); + + /* reset FIFOs */ + val = SSI_FC_TXFFL | SSI_FC_RXFFL; + writel(val, priv->base + SSI_FC); + + /* FIFO threthold */ + val = readl(priv->base + SSI_FC); + val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK); + val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth); + val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth); + writel(val, priv->base + SSI_FC); + + /* clear interrupts */ + writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC, + priv->base + SSI_IC); + + uniphier_spi_enable(priv, true); + + return 0; +} + +static int uniphier_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + + uniphier_spi_enable(priv, false); + + return 0; +} + +static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + const u8 *tx_buf = dout; + u8 *rx_buf = din, buf; + u32 len = bitlen / 8; + u32 tx_len, rx_len; + u32 ts, status; + int ret = 0; + + if (bitlen % 8) { + dev_err(dev, "Non byte aligned SPI transfer\n"); + return -EINVAL; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + uniphier_spi_enable(priv, true); + + ts = get_timer(0); + tx_len = len; + rx_len = len; + + uniphier_spi_regdump(priv); + + while (tx_len || rx_len) { + ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false, + SSI_REG_TIMEOUT * 1000, false); + if (ret) { + if (ret == -ETIMEDOUT) + dev_err(dev, "access timeout\n"); + break; + } + + status = readl(priv->base + SSI_SR); + /* write the data into TX */ + if (tx_len && (status & SSI_SR_TNF)) { + buf = tx_buf ? *tx_buf++ : 0; + writel(buf, priv->base + SSI_XDR); + tx_len--; + } + + /* read the data from RX */ + if (rx_len && (status & SSI_SR_RNE)) { + buf = readl(priv->base + SSI_XDR); + if (rx_buf) + *rx_buf++ = buf; + rx_len--; + } + + if (get_timer(ts) >= SSI_XFER_TIMEOUT) { + dev_err(dev, "transfer timeout\n"); + ret = -ETIMEDOUT; + break; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + uniphier_spi_enable(priv, false); + + return ret; +} + +static int uniphier_spi_set_speed(struct udevice *bus, uint speed) +{ + struct uniphier_spi_platdata *plat = bus->platdata; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val, ckdiv; + + if (speed > plat->frequency) + speed = plat->frequency; + + /* baudrate */ + ckdiv = DIV_ROUND_UP(SSI_CLK, speed); + ckdiv = round_up(ckdiv, 2); + + val = readl(priv->base + SSI_CKS); + val &= ~SSI_CKS_CKRAT_MASK; + val |= ckdiv & SSI_CKS_CKRAT_MASK; + writel(val, priv->base + SSI_CKS); + + return 0; +} + +static int uniphier_spi_set_mode(struct udevice *bus, uint mode) +{ + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val1, val2; + + /* + * clock setting + * CKPHS capture timing. 0:rising edge, 1:falling edge + * CKINIT clock initial level. 0:low, 1:high + * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT + * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock) + * + * frame setting + * FSPOL frame signal porarity. 0: low, 1: high + * FSTRT start frame timing + * 0: rising edge of clock, 1: falling edge of clock + */ + val1 = readl(priv->base + SSI_CKS); + val2 = readl(priv->base + SSI_FPS); + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */ + val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY; + val1 &= ~SSI_CKS_CKINIT; + val2 &= ~SSI_FPS_FSTRT; + break; + case SPI_MODE_1: + /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */ + val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY); + val2 |= SSI_FPS_FSTRT; + break; + case SPI_MODE_2: + /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */ + val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY; + val1 &= ~SSI_CKS_CKPHS; + val2 |= SSI_FPS_FSTRT; + break; + case SPI_MODE_3: + /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */ + val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT; + val1 &= ~SSI_CKS_CKDLY; + val2 &= ~SSI_FPS_FSTRT; + break; + } + + writel(val1, priv->base + SSI_CKS); + writel(val2, priv->base + SSI_FPS); + + /* format */ + val1 = readl(priv->base + SSI_TXWDS); + val2 = readl(priv->base + SSI_RXWDS); + if (mode & SPI_LSB_FIRST) { + val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1); + val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1); + } + writel(val1, priv->base + SSI_TXWDS); + writel(val2, priv->base + SSI_RXWDS); + + priv->mode = mode; + + return 0; +} + +static int uniphier_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct uniphier_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + plat->base = devfdt_get_addr_ptr(bus); + + plat->frequency = + fdtdec_get_int(blob, node, "spi-max-frequency", 12500000); + plat->deactivate_delay_us = + fdtdec_get_int(blob, node, "spi-deactivate-delay", 0); + plat->activate_delay_us = + fdtdec_get_int(blob, node, "spi-activate-delay", 0); + plat->speed_hz = plat->frequency / 2; + + return 0; +} + +static int uniphier_spi_probe(struct udevice *bus) +{ + struct uniphier_spi_platdata *plat = dev_get_platdata(bus); + struct uniphier_spi_priv *priv = dev_get_priv(bus); + + priv->base = plat->base; + priv->fifo_depth = SSI_FIFO_DEPTH; + priv->bits_per_word = 8; + + return 0; +} + +static const struct dm_spi_ops uniphier_spi_ops = { + .claim_bus = uniphier_spi_claim_bus, + .release_bus = uniphier_spi_release_bus, + .xfer = uniphier_spi_xfer, + .set_speed = uniphier_spi_set_speed, + .set_mode = uniphier_spi_set_mode, +}; + +static const struct udevice_id uniphier_spi_ids[] = { + { .compatible = "socionext,uniphier-scssi" }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_spi) = { + .name = "uniphier_spi", + .id = UCLASS_SPI, + .of_match = uniphier_spi_ids, + .ops = &uniphier_spi_ops, + .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata), + .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv), + .probe = uniphier_spi_probe, +}; diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 8878130bd72..7186c179d11 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -295,6 +295,14 @@ static int tpm_tis_spi_wait_for_stat(struct udevice *dev, u8 mask, return -ETIMEDOUT; } +static u8 tpm_tis_spi_valid_status(struct udevice *dev, u8 *status) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + return tpm_tis_spi_wait_for_stat(dev, TPM_STS_VALID, + chip->timeout_c, status); +} + static int tpm_tis_spi_get_burstcount(struct udevice *dev) { struct tpm_chip *chip = dev_get_priv(dev); @@ -455,7 +463,7 @@ static int tpm_tis_spi_send(struct udevice *dev, const u8 *buf, size_t len) i += size; } - ret = tpm_tis_spi_status(dev, &status); + ret = tpm_tis_spi_valid_status(dev, &status); if (ret) goto out_err; @@ -469,7 +477,7 @@ static int tpm_tis_spi_send(struct udevice *dev, const u8 *buf, size_t len) if (ret) goto out_err; - ret = tpm_tis_spi_status(dev, &status); + ret = tpm_tis_spi_valid_status(dev, &status); if (ret) goto out_err; diff --git a/include/android_bootloader_message.h b/include/android_bootloader_message.h index b84789f0222..286d7ab0f31 100644 --- a/include/android_bootloader_message.h +++ b/include/android_bootloader_message.h @@ -2,7 +2,7 @@ * This is from the Android Project, * Repository: https://android.googlesource.com/platform/bootable/recovery * File: bootloader_message/include/bootloader_message/bootloader_message.h - * Commit: c784ce50e8c10eaf70e1f97e24e8324aef45faf5 + * Commit: See U-Boot commit description * * Copyright (C) 2008 The Android Open Source Project * @@ -12,18 +12,24 @@ #ifndef __ANDROID_BOOTLOADER_MESSAGE_H #define __ANDROID_BOOTLOADER_MESSAGE_H +#ifndef __UBOOT__ +#include <assert.h> +#include <stddef.h> +#include <stdint.h> +#else /* compiler.h defines the types that otherwise are included from stdint.h and * stddef.h */ #include <compiler.h> +#endif -/* Spaces used by misc partition are as below: - * 0 - 2K For bootloader_message - * 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used - * as bootloader_message_ab struct) - * 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices - * Note that these offsets are admitted by bootloader,recovery and uncrypt, so they - * are not configurable without changing all of them. */ +// Spaces used by misc partition are as below: +// 0 - 2K For bootloader_message +// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used +// as bootloader_message_ab struct) +// 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices +// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they +// are not configurable without changing all of them. static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0; static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024; @@ -61,17 +67,17 @@ struct bootloader_message { char status[32]; char recovery[768]; - /* The 'recovery' field used to be 1024 bytes. It has only ever - * been used to store the recovery command line, so 768 bytes - * should be plenty. We carve off the last 256 bytes to store the - * stage string (for multistage packages) and possible future - * expansion. */ + // The 'recovery' field used to be 1024 bytes. It has only ever + // been used to store the recovery command line, so 768 bytes + // should be plenty. We carve off the last 256 bytes to store the + // stage string (for multistage packages) and possible future + // expansion. char stage[32]; - /* The 'reserved' field used to be 224 bytes when it was initially - * carved off from the 1024-byte recovery field. Bump it up to - * 1184-byte so that the entire bootloader_message struct rounds up - * to 2048-byte. */ + // The 'reserved' field used to be 224 bytes when it was initially + // carved off from the 1024-byte recovery field. Bump it up to + // 1184-byte so that the entire bootloader_message struct rounds up + // to 2048-byte. char reserved[1184]; }; @@ -79,10 +85,12 @@ struct bootloader_message { * We must be cautious when changing the bootloader_message struct size, * because A/B-specific fields may end up with different offsets. */ +#ifndef __UBOOT__ #if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) static_assert(sizeof(struct bootloader_message) == 2048, "struct bootloader_message size changes, which may break A/B devices"); #endif +#endif /* __UBOOT__ */ /** * The A/B-specific bootloader message structure (4-KiB). @@ -108,7 +116,7 @@ struct bootloader_message_ab { char slot_suffix[32]; char update_channel[128]; - /* Round up the entire struct to 4096-byte. */ + // Round up the entire struct to 4096-byte. char reserved[1888]; }; @@ -116,26 +124,28 @@ struct bootloader_message_ab { * Be cautious about the struct size change, in case we put anything post * bootloader_message_ab struct (b/29159185). */ +#ifndef __UBOOT__ #if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) static_assert(sizeof(struct bootloader_message_ab) == 4096, "struct bootloader_message_ab size changes"); #endif +#endif /* __UBOOT__ */ #define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */ #define BOOT_CTRL_VERSION 1 struct slot_metadata { - /* Slot priority with 15 meaning highest priority, 1 lowest - * priority and 0 the slot is unbootable. */ + // Slot priority with 15 meaning highest priority, 1 lowest + // priority and 0 the slot is unbootable. uint8_t priority : 4; - /* Number of times left attempting to boot this slot. */ + // Number of times left attempting to boot this slot. uint8_t tries_remaining : 3; - /* 1 if this slot has booted successfully, 0 otherwise. */ + // 1 if this slot has booted successfully, 0 otherwise. uint8_t successful_boot : 1; - /* 1 if this slot is corrupted from a dm-verity corruption, 0 - * otherwise. */ + // 1 if this slot is corrupted from a dm-verity corruption, 0 + // otherwise. uint8_t verity_corrupted : 1; - /* Reserved for further use. */ + // Reserved for further use. uint8_t reserved : 7; } __attribute__((packed)); @@ -148,99 +158,99 @@ struct slot_metadata { * mandatory. */ struct bootloader_control { - /* NUL terminated active slot suffix. */ + // NUL terminated active slot suffix. char slot_suffix[4]; - /* Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). */ + // Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). uint32_t magic; - /* Version of struct being used (see BOOT_CTRL_VERSION). */ + // Version of struct being used (see BOOT_CTRL_VERSION). uint8_t version; - /* Number of slots being managed. */ + // Number of slots being managed. uint8_t nb_slot : 3; - /* Number of times left attempting to boot recovery. */ + // Number of times left attempting to boot recovery. uint8_t recovery_tries_remaining : 3; - /* Ensure 4-bytes alignment for slot_info field. */ + // Ensure 4-bytes alignment for slot_info field. uint8_t reserved0[2]; - /* Per-slot information. Up to 4 slots. */ + // Per-slot information. Up to 4 slots. struct slot_metadata slot_info[4]; - /* Reserved for further use. */ + // Reserved for further use. uint8_t reserved1[8]; - /* CRC32 of all 28 bytes preceding this field (little endian - * format). */ + // CRC32 of all 28 bytes preceding this field (little endian + // format). uint32_t crc32_le; } __attribute__((packed)); +#ifndef __UBOOT__ #if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) static_assert(sizeof(struct bootloader_control) == sizeof(((struct bootloader_message_ab *)0)->slot_suffix), "struct bootloader_control has wrong size"); #endif +#endif /* __UBOOT__ */ #ifndef __UBOOT__ - #ifdef __cplusplus #include <string> #include <vector> -/* Return the block device name for the bootloader message partition and waits - * for the device for up to 10 seconds. In case of error returns the empty - * string. */ +// Return the block device name for the bootloader message partition and waits +// for the device for up to 10 seconds. In case of error returns the empty +// string. std::string get_bootloader_message_blk_device(std::string* err); -/* Read bootloader message into boot. Error message will be set in err. */ +// Read bootloader message into boot. Error message will be set in err. bool read_bootloader_message(bootloader_message* boot, std::string* err); -/* Read bootloader message from the specified misc device into boot. */ +// Read bootloader message from the specified misc device into boot. bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device, std::string* err); -/* Write bootloader message to BCB. */ +// Write bootloader message to BCB. bool write_bootloader_message(const bootloader_message& boot, std::string* err); -/* Write bootloader message to the specified BCB device. */ +// Write bootloader message to the specified BCB device. bool write_bootloader_message_to(const bootloader_message& boot, const std::string& misc_blk_device, std::string* err); -/* Write bootloader message (boots into recovery with the options) to BCB. Will - * set the command and recovery fields, and reset the rest. */ +// Write bootloader message (boots into recovery with the options) to BCB. Will +// set the command and recovery fields, and reset the rest. bool write_bootloader_message(const std::vector<std::string>& options, std::string* err); -/* Write bootloader message (boots into recovery with the options) to the specific BCB device. Will - * set the command and recovery fields, and reset the rest. */ +// Write bootloader message (boots into recovery with the options) to the specific BCB device. Will +// set the command and recovery fields, and reset the rest. bool write_bootloader_message_to(const std::vector<std::string>& options, const std::string& misc_blk_device, std::string* err); -/* Update bootloader message (boots into recovery with the options) to BCB. Will - * only update the command and recovery fields. */ +// Update bootloader message (boots into recovery with the options) to BCB. Will +// only update the command and recovery fields. bool update_bootloader_message(const std::vector<std::string>& options, std::string* err); -/* Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update - * the command and recovery fields. */ +// Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update +// the command and recovery fields. bool update_bootloader_message_in_struct(bootloader_message* boot, const std::vector<std::string>& options); -/* Clear BCB. */ +// Clear BCB. bool clear_bootloader_message(std::string* err); -/* Writes the reboot-bootloader reboot reason to the bootloader_message. */ +// Writes the reboot-bootloader reboot reason to the bootloader_message. bool write_reboot_bootloader(std::string* err); -/* Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC). */ +// Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC). bool read_wipe_package(std::string* package_data, size_t size, std::string* err); -/* Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC). */ +// Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC). bool write_wipe_package(const std::string& package_data, std::string* err); #else #include <stdbool.h> -/* C Interface. */ +// C Interface. bool write_bootloader_message(const char* options); bool write_reboot_bootloader(void); -#endif /* ifdef __cplusplus */ - +#endif // ifdef __cplusplus #endif /* __UBOOT__ */ #endif /* __ANDROID_BOOTLOADER_MESSAGE_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5b42e0c1dee..68568f41224 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -90,10 +90,6 @@ #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) - /* * Network Configuration */ @@ -102,8 +98,7 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 0x85000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_LOAD_ADDR 0x85000000 #define CONFIG_SYS_BOOTM_LEN (32 << 20) #if defined(CONFIG_ARM64) @@ -126,8 +121,8 @@ #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "fitImage" +#define KERNEL_ADDR_R_OFFSET "0x05100000" #define LINUXBOOT_ENV_SETTINGS \ - "kernel_addr_r=0x85100000\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "bootm $kernel_addr_r\0" \ "__nfsboot=run tftpboot\0" @@ -135,17 +130,13 @@ #ifdef CONFIG_ARM64 #define CONFIG_BOOTFILE "Image" #define LINUXBOOT_CMD "booti" -#define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0" +#define KERNEL_ADDR_R_OFFSET "0x02080000" #else #define CONFIG_BOOTFILE "zImage" #define LINUXBOOT_CMD "bootz" -#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" +#define KERNEL_ADDR_R_OFFSET "0x00208000" #endif #define LINUXBOOT_ENV_SETTINGS \ - "fdt_addr_r=0x85100000\0" \ - KERNEL_ADDR_R \ - "ramdisk_addr_r=0x86000000\0" \ - "ramdisk_file=rootfs.cpio.gz\0" \ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile && " \ @@ -160,8 +151,13 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r_offset=0x05100000\0" \ + "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \ + "ramdisk_addr_r_offset=0x06000000\0" \ + "ramdisk_file=rootfs.cpio.gz\0" \ "netdev=eth0\0" \ "initrd_high=0xffffffffffffffff\0" \ + "loadaddr_offset=0x05000000\0" \ "script=boot.scr\0" \ "scriptaddr=0x85000000\0" \ "nor_base=0x42000000\0" \ @@ -215,15 +211,9 @@ #define CONFIG_SYS_BOOTMAPSZ 0x20000000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) /* only for SPL */ -#if defined(CONFIG_ARCH_UNIPHIER_LD4) || \ - defined(CONFIG_ARCH_UNIPHIER_SLD8) -#endif - #define CONFIG_SPL_STACK (0x00200000) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 418392875cf..5056a084d23 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -69,6 +69,7 @@ enum uclass_id { UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */ UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ + UCLASS_PCI_EP, /* PCI endpoint device */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ UCLASS_PHY, /* Physical Layer (PHY) device */ UCLASS_PINCONFIG, /* Pin configuration node device */ diff --git a/include/image.h b/include/image.h index bb7089ef5d1..5f821949513 100644 --- a/include/image.h +++ b/include/image.h @@ -561,7 +561,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start, #ifndef USE_HOSTCC /* Image format types, returned by _get_format() routine */ #define IMAGE_FORMAT_INVALID 0x00 -#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ #endif #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ diff --git a/include/pci_ep.h b/include/pci_ep.h new file mode 100644 index 00000000000..00e8c6d8ab1 --- /dev/null +++ b/include/pci_ep.h @@ -0,0 +1,414 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Adapted from Linux kernel driver + * Copyright (C) 2017 Texas Instruments + * Author: Kishon Vijay Abraham I <kishon@ti.com> + * + * (C) Copyright 2019 + * Ramon Fried <ramon.fried@gmail.com> + */ + +#ifndef _PCI_EP_H +#define _PCI_EP_H + +#include <pci.h> + +/** + * enum pci_interrupt_pin - PCI INTx interrupt values + * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt + * @PCI_INTERRUPT_INTA: PCI INTA pin + * @PCI_INTERRUPT_INTB: PCI INTB pin + * @PCI_INTERRUPT_INTC: PCI INTC pin + * @PCI_INTERRUPT_INTD: PCI INTD pin + * + * Corresponds to values for legacy PCI INTx interrupts, as can be found in the + * PCI_INTERRUPT_PIN register. + */ +enum pci_interrupt_pin { + PCI_INTERRUPT_UNKNOWN, + PCI_INTERRUPT_INTA, + PCI_INTERRUPT_INTB, + PCI_INTERRUPT_INTC, + PCI_INTERRUPT_INTD, +}; + +enum pci_barno { + BAR_0, + BAR_1, + BAR_2, + BAR_3, + BAR_4, + BAR_5, +}; + +enum pci_ep_irq_type { + PCI_EP_IRQ_UNKNOWN, + PCI_EP_IRQ_LEGACY, + PCI_EP_IRQ_MSI, + PCI_EP_IRQ_MSIX, +}; + +/** + * struct pci_bar - represents the BAR (Base Address Register) of EP device + * @phys_addr: physical address that should be mapped to the BAR + * @size: the size of the address space present in BAR + * pci_barno: number of pci BAR to set (0..5) + * @flags: BAR access flags + */ +struct pci_bar { + dma_addr_t phys_addr; + size_t size; + enum pci_barno barno; + int flags; +}; + +/** + * struct pci_ep_header - represents standard configuration header + * @vendorid: identifies device manufacturer + * @deviceid: identifies a particular device + * @revid: specifies a device-specific revision identifier + * @progif_code: identifies a specific register-level programming interface + * @subclass_code: identifies more specifically the function of the device + * @baseclass_code: broadly classifies the type of function the device performs + * @cache_line_size: specifies the system cacheline size in units of DWORDs + * @subsys_vendor_id: vendor of the add-in card or subsystem + * @subsys_id: id specific to vendor + * @interrupt_pin: interrupt pin the device (or device function) uses + */ +struct pci_ep_header { + u16 vendorid; + u16 deviceid; + u8 revid; + u8 progif_code; + u8 subclass_code; + u8 baseclass_code; + u8 cache_line_size; + u16 subsys_vendor_id; + u16 subsys_id; + enum pci_interrupt_pin interrupt_pin; +}; + +/* PCI endpoint operations */ +struct pci_ep_ops { + /** + * write_header() - Write a PCI configuration space header + * + * @dev: device to write to + * @func_num: EP function to fill + * @hdr: header to write + * @return 0 if OK, -ve on error + */ + int (*write_header)(struct udevice *dev, uint func_num, + struct pci_ep_header *hdr); + /** + * read_header() - Read a PCI configuration space header + * + * @dev: device to write to + * @func_num: EP function to fill + * @hdr: header to read to + * @return 0 if OK, -ve on error + */ + int (*read_header)(struct udevice *dev, uint func_num, + struct pci_ep_header *hdr); + /** + * set_bar() - Set BAR (Base Address Register) properties + * + * @dev: device to set + * @func_num: EP function to set + * @bar: bar data + * @return 0 if OK, -ve on error + */ + int (*set_bar)(struct udevice *dev, uint func_num, + struct pci_bar *bar); + /** + * read_bar() - Read BAR (Base Address Register) properties + * + * @dev: device to read + * @func_num: EP function to read + * @bar: struct to copy data to + * @barno: bar number to read + * @return 0 if OK, -ve on error + */ + int (*read_bar)(struct udevice *dev, uint func_num, + struct pci_bar *bar, enum pci_barno barno); + /** + * clear_bar() - clear BAR (Base Address Register) + * + * @dev: device to clear + * @func_num: EP function to clear + * @bar: bar number + * @return 0 if OK, -ve on error + */ + int (*clear_bar)(struct udevice *dev, uint func_num, + enum pci_barno bar); + /** + * map_addr() - map CPU address to PCI address + * + * outband region is used in order to generate PCI read/write + * transaction from local memory/write. + * + * @dev: device to set + * @func_num: EP function to set + * @addr: local physical address base + * @pci_addr: pci address to translate to + * @size: region size + * @return 0 if OK, -ve on error + */ + int (*map_addr)(struct udevice *dev, uint func_num, + phys_addr_t addr, u64 pci_addr, size_t size); + /** + * unmap_addr() - unmap CPU address to PCI address + * + * unmap previously mapped region. + * + * @dev: device to set + * @func_num: EP function to set + * @addr: local physical address base + * @return 0 if OK, -ve on error + */ + int (*unmap_addr)(struct udevice *dev, uint func_num, + phys_addr_t addr); + /** + * set_msi() - set msi capability property + * + * set the number of required MSI vectors the device + * needs for operation. + * + * @dev: device to set + * @func_num: EP function to set + * @interrupts: required interrupts count + * @return 0 if OK, -ve on error + */ + int (*set_msi)(struct udevice *dev, uint func_num, uint interrupts); + + /** + * get_msi() - get the number of MSI interrupts allocated by the host. + * + * Read the Multiple Message Enable bitfield from + * Message control register. + * + * @dev: device to use + * @func_num: EP function to use + * @return msi count if OK, -EINVAL if msi were not enabled at host. + */ + int (*get_msi)(struct udevice *dev, uint func_num); + + /** + * set_msix() - set msix capability property + * + * set the number of required MSIx vectors the device + * needs for operation. + * + * @dev: device to set + * @func_num: EP function to set + * @interrupts: required interrupts count + * @return 0 if OK, -ve on error + */ + int (*set_msix)(struct udevice *dev, uint func_num, + uint interrupts); + + /** + * get_msix() - get the number of MSIx interrupts allocated by the host. + * + * Read the Multiple Message Enable bitfield from + * Message control register. + * + * @dev: device to use + * @func_num: EP function to use + * @return msi count if OK, -EINVAL if msi were not enabled at host. + */ + int (*get_msix)(struct udevice *dev, uint func_num); + + /** + * raise_irq() - raise a legacy, MSI or MSI-X interrupt + * + * @dev: device to set + * @func_num: EP function to set + * @type: type of irq to send + * @interrupt_num: interrupt vector to use + * @return 0 if OK, -ve on error + */ + int (*raise_irq)(struct udevice *dev, uint func_num, + enum pci_ep_irq_type type, uint interrupt_num); + /** + * start() - start the PCI link + * + * @dev: device to set + * @return 0 if OK, -ve on error + */ + int (*start)(struct udevice *dev); + + /** + * stop() - stop the PCI link + * + * @dev: device to set + * @return 0 if OK, -ve on error + */ + int (*stop)(struct udevice *dev); +}; + +#define pci_ep_get_ops(dev) ((struct pci_ep_ops *)(dev)->driver->ops) + +/** + * pci_ep_write_header() - Write a PCI configuration space header + * + * @dev: device to write to + * @func_num: EP function to fill + * @hdr: header to write + * @return 0 if OK, -ve on error + */ +int pci_ep_write_header(struct udevice *dev, uint func_num, + struct pci_ep_header *hdr); + +/** + * dm_pci_ep_read_header() - Read a PCI configuration space header + * + * @dev: device to write to + * @func_num: EP function to fill + * @hdr: header to read to + * @return 0 if OK, -ve on error + */ +int pci_ep_read_header(struct udevice *dev, uint func_num, + struct pci_ep_header *hdr); +/** + * pci_ep_set_bar() - Set BAR (Base Address Register) properties + * + * @dev: device to set + * @func_num: EP function to set + * @bar: bar data + * @return 0 if OK, -ve on error + */ +int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar); + +/** + * pci_ep_read_bar() - Read BAR (Base Address Register) properties + * + * @dev: device to read + * @func_num: EP function to read + * @bar: struct to copy data to + * @barno: bar number to read + * @return 0 if OK, -ve on error + */ +int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar, + enum pci_barno barno); + +/** + * pci_ep_clear_bar() - Clear BAR (Base Address Register) + * mark the BAR as empty so host won't map it. + * @dev: device to clear + * @func_num: EP function to clear + * @bar: bar number + * @return 0 if OK, -ve on error + */ +int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar); +/** + * pci_ep_map_addr() - map CPU address to PCI address + * + * outband region is used in order to generate PCI read/write + * transaction from local memory/write. + * + * @dev: device to set + * @func_num: EP function to set + * @addr: local physical address base + * @pci_addr: pci address to translate to + * @size: region size + * @return 0 if OK, -ve on error + */ +int pci_ep_map_addr(struct udevice *dev, uint func_num, phys_addr_t addr, + u64 pci_addr, size_t size); +/** + * pci_ep_unmap_addr() - unmap CPU address to PCI address + * + * unmap previously mapped region. + * + * @dev: device to set + * @func_num: EP function to set + * @addr: local physical address base + * @return 0 if OK, -ve on error + */ +int pci_ep_unmap_addr(struct udevice *dev, uint func_num, phys_addr_t addr); + +/** + * pci_ep_set_msi() - set msi capability property + * + * set the number of required MSI vectors the device + * needs for operation. + * + * @dev: device to set + * @func_num: EP function to set + * @interrupts: required interrupts count + * @return 0 if OK, -ve on error + */ +int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts); + +/** + * pci_ep_get_msi() - get the number of MSI interrupts allocated by the host. + * + * Read the Multiple Message Enable bitfield from + * Message control register. + * + * @dev: device to use + * @func_num: EP function to use + * @return msi count if OK, -EINVAL if msi were not enabled at host. + */ +int pci_ep_get_msi(struct udevice *dev, uint func_num); + +/** + * pci_ep_set_msix() - set msi capability property + * + * set the number of required MSIx vectors the device + * needs for operation. + * + * @dev: device to set + * @func_num: EP function to set + * @interrupts: required interrupts count + * @return 0 if OK, -ve on error + */ +int pci_ep_set_msix(struct udevice *dev, uint func_num, uint interrupts); + +/** + * pci_ep_get_msix() - get the number of MSIx interrupts allocated by the host. + * + * Read the Multiple Message Enable bitfield from + * Message control register. + * + * @dev: device to use + * @func_num: EP function to use + * @return msi count if OK, -EINVAL if msi were not enabled at host. + */ +int pci_ep_get_msix(struct udevice *dev, uint func_num); + +/** + * pci_ep_raise_irq() - raise a legacy, MSI or MSI-X interrupt + * + * @dev: device to set + * @func_num: EP function to set + * @type: type of irq to send + * @interrupt_num: interrupt vector to use + * @return 0 if OK, -ve on error + */ +int pci_ep_raise_irq(struct udevice *dev, uint func_num, + enum pci_ep_irq_type type, uint interrupt_num); +/** + * pci_ep_start() - start the PCI link + * + * Enable PCI endpoint device and start link + * process. + * + * @dev: device to set + * @return 0 if OK, -ve on error + */ +int pci_ep_start(struct udevice *dev); + +/** + * pci_ep_stop() - stop the PCI link + * + * Disable PCI endpoint device and stop + * link. + * + * @dev: device to set + * @return 0 if OK, -ve on error + */ +int pci_ep_stop(struct udevice *dev); + +#endif diff --git a/test/dm/Makefile b/test/dm/Makefile index aeb3aa0ca7c..420bf811545 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -31,6 +31,7 @@ obj-y += ofnode.o obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_VIDEO) += panel.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o obj-$(CONFIG_PHY) += phy.o obj-$(CONFIG_POWER_DOMAIN) += power-domain.o diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c new file mode 100644 index 00000000000..101f8617513 --- /dev/null +++ b/test/dm/pci_ep.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Ramon Fried + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/test.h> +#include <dm/test.h> +#include <test/ut.h> +#include <hexdump.h> +#include <pci_ep.h> + +/* Test that sandbox PCI EP works correctly */ +static int dm_test_pci_ep_base(struct unit_test_state *uts) +{ + struct udevice *bus; + struct pci_bar tmp_bar; + struct pci_ep_header tmp_header; + int i; + + struct pci_ep_header ep_header = { + .vendorid = 0x1234, + .deviceid = 0x2020, + .revid = 1, + .interrupt_pin = PCI_INTERRUPT_INTA, + }; + + struct pci_bar bar = { + .phys_addr = 0x80000000, + .size = 0x100000, + .barno = BAR_0, + .flags = PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, + }; + + ut_assertok(uclass_get_device(UCLASS_PCI_EP, 0, &bus)); + ut_assertnonnull(bus); + + ut_assertok(pci_ep_write_header(bus, 0, &ep_header)); + ut_assertok(pci_ep_read_header(bus, 0, &tmp_header)); + ut_asserteq_mem(&tmp_header, &ep_header, sizeof(ep_header)); + + ut_assertok(pci_ep_set_msi(bus, 0, 4)); + ut_asserteq(pci_ep_get_msi(bus, 0), 4); + + ut_assertok(pci_ep_set_msix(bus, 0, 360)); + ut_asserteq(pci_ep_get_msix(bus, 0), 360); + + ut_assertok(pci_ep_set_bar(bus, 0, &bar)); + + ut_assertok(pci_ep_read_bar(bus, 0, &tmp_bar, BAR_0)); + ut_asserteq_mem(&tmp_bar, &bar, sizeof(bar)); + + for (i = 0; i < 10; i++) + ut_assertok(pci_ep_raise_irq(bus, 0, 1, PCI_EP_IRQ_LEGACY)); + + ut_asserteq(sandbox_get_pci_ep_irq_count(bus), 10); + return 0; +} + +DM_TEST(dm_test_pci_ep_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + |