diff options
714 files changed, 15057 insertions, 25272 deletions
diff --git a/.gitignore b/.gitignore index be137040a2c..37f71c275c3 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ *.a *.asn1.[ch] *.bin +*.bin[_.]* *.cfgout *.cover *.dtb @@ -17,23 +18,27 @@ *.dtb.S *.elf *.exe +*.fit *.gcda *.gcno *.i *.img +*.itb *.lex.c *.lst +*.map *.mod.c *.mbx *.o *.o.* *.order *.patch +*.pem *.s *.su *.swp *.tab.[ch] - +*.ti-* # Build tree /build* @@ -67,6 +72,7 @@ fit-dtb.blob* /Test* /capsule.*.efi-capsule /capsule*.map +/keep-syms-lto.* # # Generated include files @@ -15,6 +15,7 @@ # Proper Name <proper@email.xx> <commit@email.xx> # Proper Name <proper@email.xx> Commit Name <commit@email.xx> +AKASHI Takahiro <akashi.tkhro@gmail.com> <takahiro.akashi@linaro.org> Alexander Graf <agraf@csgraf.de> <agraf@suse.de> Allen Martin <amartin@nvidia.com> Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com> diff --git a/MAINTAINERS b/MAINTAINERS index 0462ade4ac6..921ce05755a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -603,11 +603,9 @@ ARM SNAPDRAGON M: Caleb Connolly <caleb.connolly@linaro.org> M: Neil Armstrong <neil.armstrong@linaro.org> R: Sumit Garg <sumit.garg@linaro.org> +L: u-boot-qcom@groups.io S: Maintained -F: arch/arm/dts/msm8*.dtsi -F: arch/arm/dts/pm8???.dtsi -F: arch/arm/dts/pms405.dtsi -F: arch/arm/dts/sdm845.dtsi +T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git F: drivers/*/*/pm8???-* F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c @@ -1642,9 +1640,18 @@ M: Jens Wiklander <jens.wiklander@linaro.org> M: Ilias Apalodimas <ilias.apalodimas@linaro.org> T: git https://source.denx.de/u-boot/custodians/u-boot-tpm.git S: Maintained +F: cmd/optee* +F: doc/README.tee +F: doc/device-tree-bindings/firmware/linaro,optee-tz.txt +F: drivers/firmware/scmi/optee_agent.c F: drivers/tee/ +F: include/sandboxtee.h F: include/tee.h F: include/tee/ +F: include/test/optee.h +F: test/dm/tee.c +F: test/optee/ +F: test/py/tests/test_optee_rpmb.py TEE-lib M: Bryan O'Donoghue <bryan.odonoghue@linaro.org> @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ VERSION = 2024 -PATCHLEVEL = 04 +PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* @@ -717,7 +717,7 @@ KBUILD_CFLAGS += -O2 endif ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG -KBUILD_CFLAGS += -Og -Wno-maybe-uninitialized +KBUILD_CFLAGS += -Og # Avoid false positives -Wmaybe-uninitialized # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394 KBUILD_CFLAGS += -Wno-maybe-uninitialized diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index be8ab0f559a..93e12d8d533 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -762,10 +762,8 @@ config ARCH_IPQ40XX select DM_SERIAL select DM_RESET select GPIO_EXTRA_HEADER - select MSM_SMEM select PINCTRL select CLK - select SMEM select OF_CONTROL select CLK_QCOM_IPQ4019 select PINCTRL_QCOM_IPQ4019 @@ -1022,7 +1020,7 @@ config ARCH_APPLE select USB imply CMD_DM imply CMD_GPT - imply DISTRO_DEFAULTS + imply BOOTSTD_FULL imply OF_HAS_PRIOR_STAGE config ARCH_OWL @@ -1089,7 +1087,8 @@ config ARCH_SNAPDRAGON select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR - select LINUX_KERNEL_IMAGE_HEADER + select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK + imply OF_UPSTREAM imply CMD_DM config ARCH_SOCFPGA @@ -1345,7 +1344,7 @@ config ARCH_ZYNQMP config ARCH_TEGRA bool "NVIDIA Tegra" select GPIO_EXTRA_HEADER - imply DISTRO_DEFAULTS + imply BOOTSTD_DEFAULTS imply FAT_WRITE imply SPL_TIMER if SPL diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index 1541dfb3ec4..b1bb29bcaf5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -258,7 +258,7 @@ int setup_serdes_volt(u32 svdd) /* Wait for SVDD to stabilize */ udelay(100); - /* For each PLL that’s not disabled via RCW */ + /* For each PLL that's not disabled via RCW */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index c0efc341afc..fbd5fd7d433 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -483,7 +483,7 @@ int setup_serdes_volt(u32 svdd) ret = -1; } - /* For each PLL that’s not disabled via RCW enable the SERDES */ + /* For each PLL that's not disabled via RCW enable the SERDES */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; do_serdes_enable(cfg_tmp, serdes1_base); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a7a97a9f087..c9f1b25ad64 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -166,8 +166,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ - rk3588s-coolpi-4b.dts \ - rk3588-coolpi-cm5-evb.dts \ + rk3588s-coolpi-4b.dtb \ + rk3588-coolpi-cm5-evb.dtb \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ @@ -179,6 +179,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-quartzpro64.dtb \ rk3588s-rock-5a.dtb \ rk3588-rock-5b.dtb \ + rk3588-toybrick-x0.dtb \ rk3588-turing-rk1.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ @@ -571,12 +572,6 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb -dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \ - apq8096-db820c.dtb \ - sdm845-db845c.dtb \ - sdm845-samsung-starqltechn.dtb \ - qcs404-evb-4000.dtb - dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ @@ -1046,7 +1041,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-11x11-evk.dtb \ imx93-var-som-symphony.dtb \ imx93-phyboard-segin.dtb @@ -1325,7 +1319,9 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am6548-iot2050-advanced-pg2.dtb \ k3-am6548-iot2050-advanced-m2.dtb \ k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \ - k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo + k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \ + k3-am654-icssg2.dtbo + dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-r5-common-proc-board.dtb \ k3-j7200-common-proc-board.dtb \ diff --git a/arch/arm/dts/apq8016-sbc.dts b/arch/arm/dts/apq8016-schneider-hmibsc.dts index 9ffad7d1f2b..75c6137e5a1 100644 --- a/arch/arm/dts/apq8016-sbc.dts +++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. */ /dts-v1/; @@ -14,50 +15,25 @@ #include <dt-bindings/sound/apq8016-lpass.h> / { - model = "Qualcomm Technologies, Inc. APQ 8016 SBC"; - compatible = "qcom,apq8016-sbc", "qcom,apq8016"; + model = "Schneider Electric HMIBSC Board"; + compatible = "schneider,apq8016-hmibsc", "qcom,apq8016"; aliases { - mmc0 = &sdhc_1; /* eMMC */ - mmc1 = &sdhc_2; /* SD card */ - serial0 = &blsp_uart2; - serial1 = &blsp_uart1; - usid0 = &pm8916_0; - i2c0 = &blsp_i2c2; i2c1 = &blsp_i2c6; i2c3 = &blsp_i2c4; + i2c4 = &blsp_i2c3; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; spi0 = &blsp_spi5; - spi1 = &blsp_spi3; + usid0 = &pm8916_0; }; chosen { stdout-path = "serial0"; }; - reserved-memory { - ramoops@bff00000 { - compatible = "ramoops"; - reg = <0x0 0xbff00000 0x0 0x100000>; - - record-size = <0x20000>; - console-size = <0x20000>; - ftrace-size = <0x20000>; - }; - }; - - usb2513 { - compatible = "smsc,usb3503"; - reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - }; - - usb_id: usb-id { - compatible = "linux,extcon-usb-gpio"; - id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_id_default>; - }; - hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -72,9 +48,8 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - - pinctrl-names = "default"; pinctrl-0 = <&msm_key_volp_n_default>; + pinctrl-names = "default"; button { label = "Volume Up"; @@ -84,51 +59,11 @@ }; leds { - pinctrl-names = "default"; - pinctrl-0 = <&tlmm_leds>, - <&pm8916_gpios_leds>, - <&pm8916_mpps_leds>; - compatible = "gpio-leds"; + pinctrl-0 = <&pm8916_mpps_leds>; + pinctrl-names = "default"; - led@1 { - label = "apq8016-sbc:green:user1"; - function = LED_FUNCTION_HEARTBEAT; - color = <LED_COLOR_ID_GREEN>; - gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@2 { - label = "apq8016-sbc:green:user2"; - function = LED_FUNCTION_DISK_ACTIVITY; - color = <LED_COLOR_ID_GREEN>; - gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@3 { - label = "apq8016-sbc:green:user3"; - function = LED_FUNCTION_DISK_ACTIVITY; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led@4 { - label = "apq8016-sbc:green:user4"; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - panic-indicator; - default-state = "off"; - }; - - led@5 { - label = "apq8016-sbc:yellow:wlan"; + led-1 { function = LED_FUNCTION_WLAN; color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; @@ -136,8 +71,7 @@ default-state = "off"; }; - led@6 { - label = "apq8016-sbc:blue:bt"; + led-2 { function = LED_FUNCTION_BLUETOOTH; color = <LED_COLOR_ID_BLUE>; gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; @@ -145,30 +79,56 @@ default-state = "off"; }; }; + + memory@80000000 { + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usb-hub { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; }; -&blsp_i2c2 { - /* On Low speed expansion: LS-I2C0 */ +&blsp_i2c3 { status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; &blsp_i2c4 { - /* On High speed expansion: HS-I2C2 */ status = "okay"; adv_bridge: bridge@39 { - status = "okay"; - compatible = "adi,adv7533"; reg = <0x39>; - - interrupt-parent = <&tlmm>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; clocks = <&rpmcc RPM_SMD_BB_CLK2>; clock-names = "cec"; - pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; avdd-supply = <&pm8916_l6>; @@ -178,10 +138,10 @@ v1p2-supply = <&pm8916_l6>; v3p3-supply = <&pm8916_l17>; - pinctrl-names = "default","sleep"; pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; - #sound-dai-cells = <1>; + pinctrl-names = "default","sleep"; + #sound-dai-cells = <0>; ports { #address-cells = <1>; @@ -205,35 +165,37 @@ }; &blsp_i2c6 { - /* On Low speed expansion: LS-I2C1 */ status = "okay"; -}; -&blsp_spi3 { - /* On High speed expansion: HS-SPI1 */ - status = "okay"; + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; }; &blsp_spi5 { - /* On Low speed expansion: LS-SPI0 */ + cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; }; &blsp_uart1 { + label = "UART0"; status = "okay"; - label = "LS-UART0"; }; &blsp_uart2 { - status = "okay"; - label = "LS-UART1"; -}; - -&camss { - status = "okay"; -}; - -&gpu { + label = "UART1"; status = "okay"; }; @@ -241,14 +203,6 @@ status = "okay"; }; -&lpass_codec { - status = "okay"; -}; - -&mba_mem { - status = "okay"; -}; - &mdss { status = "okay"; }; @@ -258,51 +212,70 @@ remote-endpoint = <&adv7533_in>; }; -&mpss { +&pm8916_codec { + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; status = "okay"; - - firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn"; }; -&mpss_mem { - status = "okay"; - reg = <0x0 0x86800000 0x0 0x2b00000>; +&pm8916_gpios { + gpio-line-names = + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM", + "NC", + "NC"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-low; + }; }; -&pm8916_codec { - status = "okay"; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +&pm8916_mpps { + gpio-line-names = + "NC", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "NC"; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; }; &pm8916_resin { + linux,code = <KEY_POWER>; status = "okay"; - linux,code = <KEY_VOLUMEDOWN>; }; &pm8916_rpm_regulators { - /* - * The 96Boards specification expects a 1.8V power rail on the low-speed - * expansion connector that is able to provide at least 0.18W / 100 mA. - * L15/L16 are connected in parallel to provide 55 mA each. A minimum load - * must be specified to ensure the regulators are not put in LPM where they - * would only provide 5 mA. - */ - pm8916_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <50000>; - regulator-allow-set-load; - regulator-always-on; - }; - pm8916_l16: l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <50000>; - regulator-allow-set-load; - regulator-always-on; - }; - pm8916_l17: l17 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -314,25 +287,22 @@ }; &sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_default &sdc2_cd_default>; pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - + pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + status = "okay"; }; &sound { - status = "okay"; - pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; pinctrl-names = "default", "sleep"; - model = "DB410c"; + model = "HMIBSC"; audio-routing = "AMIC2", "MIC BIAS Internal2", "AMIC3", "MIC BIAS External1"; + status = "okay"; quaternary-dai-link { link-name = "ADV7533"; @@ -365,258 +335,13 @@ }; }; -&usb { - status = "okay"; - extcon = <&usb_id>, <&usb_id>; - - pinctrl-names = "default", "device"; - pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; - pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; -}; - -&usb_hs_phy { - extcon = <&usb_id>; -}; - -&venus { - status = "okay"; -}; - -&venus_mem { - status = "okay"; -}; - -&wcnss { - status = "okay"; - firmware-name = "qcom/apq8016/wcnss.mbn"; -}; - -&wcnss_ctrl { - firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; -}; - -&wcnss_iris { - compatible = "qcom,wcn3620"; -}; - -&wcnss_mem { - status = "okay"; -}; - -/* Enable CoreSight */ -&cti0 { status = "okay"; }; -&cti1 { status = "okay"; }; -&cti12 { status = "okay"; }; -&cti13 { status = "okay"; }; -&cti14 { status = "okay"; }; -&cti15 { status = "okay"; }; -&debug0 { status = "okay"; }; -&debug1 { status = "okay"; }; -&debug2 { status = "okay"; }; -&debug3 { status = "okay"; }; -&etf { status = "okay"; }; -&etm0 { status = "okay"; }; -&etm1 { status = "okay"; }; -&etm2 { status = "okay"; }; -&etm3 { status = "okay"; }; -&etr { status = "okay"; }; -&funnel0 { status = "okay"; }; -&funnel1 { status = "okay"; }; -&replicator { status = "okay"; }; -&stm { status = "okay"; }; -&tpiu { status = "okay"; }; - -/* - * 2mA drive strength is not enough when connecting multiple - * I2C devices with different pull up resistors. - */ -&blsp_i2c2_default { - drive-strength = <16>; -}; - -&blsp_i2c4_default { - drive-strength = <16>; -}; - -&blsp_i2c6_default { - drive-strength = <16>; -}; - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "DragonBoard410c" - * dated monday, august 31, 2015. Page 5 in particular. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - &tlmm { - gpio-line-names = - "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ - "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ - "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ - "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ - "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ - "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ - "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ - "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ - "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ - "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ - "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ - "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ - "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ - "[I2C3_SDA]", /* HSEC pin 38 */ - "[I2C3_SCL]", /* HSEC pin 36 */ - "[SPI0_MOSI]", /* LSEC pin 14 */ - "[SPI0_MISO]", /* LSEC pin 10 */ - "[SPI0_CS_N]", /* LSEC pin 12 */ - "[SPI0_CLK]", /* LSEC pin 8 */ - "HDMI_HPD_N", /* GPIO 20 */ - "USR_LED_1_CTRL", - "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ - "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ - "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ - "[CSI0_MCLK]", /* HSEC pin 15 */ - "[CSI1_MCLK]", /* HSEC pin 17 */ - "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ - "[I2C2_SDA]", /* HSEC pin 34 */ - "[I2C2_SCL]", /* HSEC pin 32 */ - "DSI2HDMI_INT_N", - "DSI_SW_SEL_APQ", - "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ - "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ - "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ - "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ - "FORCED_USB_BOOT", - "SD_CARD_DET_N", - "[WCSS_BT_SSBI]", - "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ - "[WCSS_WLAN_DATA_1]", - "[WCSS_WLAN_DATA_0]", - "[WCSS_WLAN_SET]", - "[WCSS_WLAN_CLK]", - "[WCSS_FM_SSBI]", - "[WCSS_FM_SDI]", - "[WCSS_BT_DAT_CTL]", - "[WCSS_BT_DAT_STB]", - "NC", - "NC", /* GPIO 50 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 60 */ - "NC", - "NC", - "[CDC_PDM0_CLK]", - "[CDC_PDM0_SYNC]", - "[CDC_PDM0_TX0]", - "[CDC_PDM0_RX0]", - "[CDC_PDM0_RX1]", - "[CDC_PDM0_RX2]", - "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ - "NC", /* GPIO 70 */ - "NC", - "NC", - "NC", - "NC", /* GPIO 74 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "BOOT_CONFIG_0", /* GPIO 80 */ - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_3", - "NC", - "NC", - "BOOT_CONFIG_5", - "NC", - "NC", - "NC", - "NC", /* GPIO 90 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 100 */ - "NC", - "NC", - "NC", - "SSBI_GPS", - "NC", - "NC", - "KEY_VOLP_N", - "NC", - "NC", - "[LS_EXP_MI2S_WS]", /* GPIO 110 */ - "NC", - "NC", - "[LS_EXP_MI2S_SCK]", - "[LS_EXP_MI2S_DATA0]", - "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ - "NC", - "[DSI2HDMI_MI2S_WS]", - "[DSI2HDMI_MI2S_SCK]", - "[DSI2HDMI_MI2S_DATA0]", - "USR_LED_2_CTRL", /* GPIO 120 */ - "SB_HS_ID"; - - sdc2_cd_default: sdc2-cd-default-state { - pins = "gpio38"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tlmm_leds: tlmm-leds-state { - pins = "gpio21", "gpio120"; - function = "gpio"; - - output-low; - }; - - usb_id_default: usb-id-default-state { - pins = "gpio121"; - function = "gpio"; - - drive-strength = <8>; - bias-pull-up; - }; + pinctrl-0 = <&uart1_mux0_rs232_high &uart1_mux1_rs232_low>; + pinctrl-names = "default"; adv7533_int_active: adv533-int-active-state { pins = "gpio31"; function = "gpio"; - drive-strength = <16>; bias-disable; }; @@ -624,7 +349,6 @@ adv7533_int_suspend: adv7533-int-suspend-state { pins = "gpio31"; function = "gpio"; - drive-strength = <2>; bias-disable; }; @@ -632,7 +356,6 @@ adv7533_switch_active: adv7533-switch-active-state { pins = "gpio32"; function = "gpio"; - drive-strength = <16>; bias-disable; }; @@ -640,7 +363,6 @@ adv7533_switch_suspend: adv7533-switch-suspend-state { pins = "gpio32"; function = "gpio"; - drive-strength = <2>; bias-disable; }; @@ -648,82 +370,122 @@ msm_key_volp_n_default: msm-key-volp-n-default-state { pins = "gpio107"; function = "gpio"; - drive-strength = <8>; bias-pull-up; }; -}; -&pm8916_gpios { - gpio-line-names = - "USR_LED_3_CTRL", - "USR_LED_4_CTRL", - "USB_HUB_RESET_N_PM", - "USB_SW_SEL_PM"; - - usb_hub_reset_pm: usb-hub-reset-pm-state { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; - input-disable; + /* + * UART1 being the debug console supports various modes of + * operation (RS-232/485/422) controlled via GPIOs configured + * mux as follows: + * + * gpio100 gpio99 UART mode + * 0 0 loopback + * 0 1 RS-232 + * 1 0 RS-485 + * 1 1 RS-422 + * + * The default mode configured here is RS-232 mode. + */ + uart1_mux0_rs232_high: uart1-mux0-rs232-state { + bootph-all; + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + bias-disable; output-high; }; - usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - + uart1_mux1_rs232_low: uart1-mux1-rs232-state { + bootph-all; + pins = "gpio100"; + function = "gpio"; + drive-strength = <16>; + bias-disable; output-low; }; - usb_sw_sel_pm: usb-sw-sel-pm-state { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - - power-source = <PM8916_GPIO_VPH>; - input-disable; - output-high; + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; }; +}; - usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; +&usb { + extcon = <&usb_id>, <&usb_id>; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; + pinctrl-names = "default", "device"; + status = "okay"; +}; - power-source = <PM8916_GPIO_VPH>; - input-disable; - output-low; - }; +&usb_hs_phy { + extcon = <&usb_id>; +}; - pm8916_gpios_leds: pm8916-gpios-leds-state { - pins = "gpio1", "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; +&wcnss { + firmware-name = "qcom/apq8016/wcnss.mbn"; + status = "okay"; +}; - output-low; - }; +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; }; -&pm8916_mpps { - gpio-line-names = - "VDD_PX_BIAS", - "WLAN_LED_CTRL", - "BT_LED_CTRL", - "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f>; +&wcnss_mem { + status = "okay"; +}; - ls_exp_gpio_f: pm8916-mpp4-state { - pins = "mpp4"; - function = "digital"; +/* PINCTRL - additions to nodes defined in msm8916.dtsi */ - output-low; - power-source = <PM8916_MPP_L5>; /* 1.8V */ - }; +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ +&blsp_i2c4_default { + drive-strength = <16>; +}; - pm8916_mpps_leds: pm8916-mpps-state { - pins = "mpp2", "mpp3"; - function = "digital"; +&blsp_i2c6_default { + drive-strength = <16>; +}; - output-low; - }; +&blsp_uart1_default { + bootph-all; }; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; }; diff --git a/arch/arm/dts/apq8096-db820c.dts b/arch/arm/dts/apq8096-db820c.dts deleted file mode 100644 index e8148b3d6c5..00000000000 --- a/arch/arm/dts/apq8096-db820c.dts +++ /dev/null @@ -1,1137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8996.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/sound/qcom,q6afe.h> -#include <dt-bindings/sound/qcom,q6asm.h> -#include <dt-bindings/sound/qcom,wcd9335.h> - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * P HSEC = Primary High Speed External Connector - * S HSEC = Secondary High Speed External Connector - * J14 = Camera Connector - * TP = Test Points - * - * Line names are taken from the schematic "DragonBoard 820c", - * drawing no: LM25-P2751-1 - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - -/ { - model = "Qualcomm Technologies, Inc. DB820c"; - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; - - aliases { - serial0 = &blsp2_uart2; - serial1 = &blsp2_uart3; - serial2 = &blsp1_uart2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c1; - spi0 = &blsp1_spi1; - spi1 = &blsp2_spi6; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - div1_mclk: divclk1 { - compatible = "gpio-gate-clock"; - pinctrl-0 = <&audio_mclk>; - pinctrl-names = "default"; - clocks = <&rpmcc RPM_SMD_DIV_CLK1>; - #clock-cells = <0>; - enable-gpios = <&pm8994_gpios 15 0>; - }; - - divclk4: divclk4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "divclk4"; - - pinctrl-names = "default"; - pinctrl-0 = <&divclk4_pin_a>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&volume_up_gpio>; - - button { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; - }; - }; - - usb2_id: usb2-id { - compatible = "linux,extcon-usb-gpio"; - id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_det_gpio>; - }; - - usb3_id: usb3-id { - compatible = "linux,extcon-usb-gpio"; - id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_det_gpio>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - wlan_en: wlan-en-1-8v { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_gpios>; - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8994_gpios 8 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&blsp1_i2c3 { - /* On Low speed expansion: LS-I2C0 */ - status = "okay"; -}; - -&blsp1_spi1 { - /* On Low speed expansion */ - status = "okay"; -}; - -&blsp1_uart2 { - label = "BT-UART"; - status = "okay"; - - bluetooth { - compatible = "qcom,qca6174-bt"; - - /* bt_disable_n gpio */ - enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; - - clocks = <&divclk4>; - }; -}; - -&adsp_pil { - status = "okay"; - firmware-name = "qcom/apq8096/adsp.mbn"; -}; - -&blsp2_i2c1 { - /* On High speed expansion: HS-I2C2 */ - status = "okay"; -}; - -&blsp2_i2c1 { - /* On Low speed expansion: LS-I2C1 */ - status = "okay"; -}; - -&blsp2_spi6 { - /* On High speed expansion */ - status = "okay"; -}; - -&blsp2_uart2 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_2pins_default>; - pinctrl-1 = <&blsp2_uart2_2pins_sleep>; -}; - -&blsp2_uart3 { - label = "LS-UART0"; - status = "disabled"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart3_4pins_default>; - pinctrl-1 = <&blsp2_uart3_4pins_sleep>; -}; - -&camss { - vdda-supply = <&vreg_l2a_1p25>; -}; - -&gpu { - status = "okay"; -}; - -&hsusb_phy1 { - status = "okay"; - - vdd-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&hsusb_phy2 { - status = "okay"; - - vdd-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&mdp { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&mdss_hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - -&mmcc { - vdd-gfx-supply = <&vdd_gfx>; -}; - -&mss_pil { - status = "okay"; - pll-supply = <&vreg_l12a_1p8>; - firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn"; -}; - -&pm8994_resin { - status = "okay"; - linux,code = <KEY_VOLUMEDOWN>; -}; - -&tlmm { - gpio-line-names = - "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ - "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ - "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ - "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ - "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ - "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ - "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ - "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ - "TP93", /* GPIO_9 */ - "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ - "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ - "NC", /* GPIO_12 */ - "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ - "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ - "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ - "TP99", /* GPIO_16 */ - "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ - "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ - "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ - "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ - "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ - "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ - "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ - "GPIO-D", /* GPIO_24, LSEC pin 26 */ - "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ - "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ - "BLSP6_I2C_SDA", /* GPIO_27 */ - "BLSP6_I2C_SCL", /* GPIO_28 */ - "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ - "GPIO30", /* GPIO_30, S HSEC pin 4 */ - "HDMI_CEC", /* GPIO_31 */ - "HDMI_DDC_CLOCK", /* GPIO_32 */ - "HDMI_DDC_DATA", /* GPIO_33 */ - "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ - "PCIE0_RST_N", /* GPIO_35 */ - "PCIE0_CLKREQ_N", /* GPIO_36 */ - "PCIE0_WAKE", /* GPIO_37 */ - "SD_CARD_DET_N", /* GPIO_38 */ - "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ - "W_DISABLE_N", /* GPIO_40 */ - "[BLSP9_UART_TX]", /* GPIO_41 */ - "[BLSP9_UART_RX]", /* GPIO_42 */ - "[BLSP2_UART_CTS_N]", /* GPIO_43 */ - "[BLSP2_UART_RFR_N]", /* GPIO_44 */ - "[BLSP3_UART_TX]", /* GPIO_45 */ - "[BLSP3_UART_RX]", /* GPIO_46 */ - "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ - "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ - "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ - "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ - "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ - "[CODEC_INT1_N]", /* GPIO_53 */ - "[CODEC_INT2_N]", /* GPIO_54 */ - "[BLSP7_I2C_SDA]", /* GPIO_55 */ - "[BLSP7_I2C_SCL]", /* GPIO_56 */ - "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ - "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ - "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ - "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ - "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ - "GPIO-E", /* GPIO_62, LSEC pin 27 */ - "TP87", /* GPIO_63 */ - "[CODEC_RST_N]", /* GPIO_64 */ - "[PCM1_CLK]", /* GPIO_65 */ - "[PCM1_SYNC]", /* GPIO_66 */ - "[PCM1_DIN]", /* GPIO_67 */ - "[PCM1_DOUT]", /* GPIO_68 */ - "AUDIO_REF_CLK", /* GPIO_69 */ - "SLIMBUS_CLK", /* GPIO_70 */ - "SLIMBUS_DATA0", /* GPIO_71 */ - "SLIMBUS_DATA1", /* GPIO_72 */ - "NC", /* GPIO_73 */ - "NC", /* GPIO_74 */ - "NC", /* GPIO_75 */ - "NC", /* GPIO_76 */ - "TP94", /* GPIO_77 */ - "NC", /* GPIO_78 */ - "TP95", /* GPIO_79 */ - "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ - "TP88", /* GPIO_81 */ - "TP89", /* GPIO_82 */ - "TP90", /* GPIO_83 */ - "TP91", /* GPIO_84 */ - "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ - "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ - "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ - "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ - "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ - "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ - "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ - "NC", /* GPIO_92 */ - "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ - "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ - "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ - "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ - "NC", /* GPIO_97 */ - "CAM1_STANDBY_N", /* GPIO_98 */ - "NC", /* GPIO_99 */ - "NC", /* GPIO_100 */ - "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ - "BOOT_CONFIG1", /* GPIO_102 */ - "USB_HUB_RESET", /* GPIO_103 */ - "CAM1_RST_N", /* GPIO_104 */ - "NC", /* GPIO_105 */ - "NC", /* GPIO_106 */ - "NC", /* GPIO_107 */ - "NC", /* GPIO_108 */ - "NC", /* GPIO_109 */ - "NC", /* GPIO_110 */ - "NC", /* GPIO_111 */ - "NC", /* GPIO_112 */ - "PMI8994_BUA", /* GPIO_113 */ - "PCIE2_RST_N", /* GPIO_114 */ - "PCIE2_CLKREQ_N", /* GPIO_115 */ - "PCIE2_WAKE", /* GPIO_116 */ - "SSC_IRQ_0", /* GPIO_117 */ - "SSC_IRQ_1", /* GPIO_118 */ - "SSC_IRQ_2", /* GPIO_119 */ - "NC", /* GPIO_120 */ - "GPIO121", /* GPIO_121, S HSEC pin 2 */ - "NC", /* GPIO_122 */ - "SSC_IRQ_6", /* GPIO_123 */ - "SSC_IRQ_7", /* GPIO_124 */ - "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ - "BOOT_CONFIG5", /* GPIO_126 */ - "NC", /* GPIO_127 */ - "NC", /* GPIO_128 */ - "BOOT_CONFIG7", /* GPIO_129 */ - "PCIE1_RST_N", /* GPIO_130 */ - "PCIE1_CLKREQ_N", /* GPIO_131 */ - "PCIE1_WAKE", /* GPIO_132 */ - "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ - "NC", /* GPIO_134 */ - "NC", /* GPIO_135 */ - "BOOT_CONFIG8", /* GPIO_136 */ - "NC", /* GPIO_137 */ - "NC", /* GPIO_138 */ - "GPS_SSBI2", /* GPIO_139 */ - "GPS_SSBI1", /* GPIO_140 */ - "NC", /* GPIO_141 */ - "NC", /* GPIO_142 */ - "NC", /* GPIO_143 */ - "BOOT_CONFIG6", /* GPIO_144 */ - "NC", /* GPIO_145 */ - "NC", /* GPIO_146 */ - "NC", /* GPIO_147 */ - "NC", /* GPIO_148 */ - "NC"; /* GPIO_149 */ - - sdc2_cd_on: sdc2-cd-on-state { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - - sdc2_cd_off: sdc2-cd-off-state { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - - hdmi_hpd_active: hdmi-hpd-active-state { - pins = "gpio34"; - function = "hdmi_hot"; - bias-pull-down; - drive-strength = <16>; - }; - - hdmi_hpd_suspend: hdmi-hpd-suspend-state { - pins = "gpio34"; - function = "hdmi_hot"; - bias-pull-down; - drive-strength = <2>; - }; - - hdmi_ddc_active: hdmi-ddc-active-state { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - drive-strength = <2>; - bias-pull-up; - }; - - hdmi_ddc_suspend: hdmi-ddc-suspend-state { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - drive-strength = <2>; - bias-pull-down; - }; -}; - -&pcie0 { - status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&wlan_en>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie1 { - status = "okay"; - perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie2 { - status = "okay"; - perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&pm8994_gpios { - gpio-line-names = - "NC", - "KEY_VOLP_N", - "NC", - "BL1_PWM", - "GPIO-F", /* BL0_PWM, LSEC pin 28 */ - "BL1_EN", - "NC", - "WLAN_EN", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "DIVCLK1", - "DIVCLK2", - "DIVCLK3", - "DIVCLK4", - "BT_EN", - "PMIC_SLB", - "PMIC_BUA", - "USB_VBUS_DET"; - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; - - ls_exp_gpio_f: pm8994-gpio5-state { - pinconf { - pins = "gpio5"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - }; - }; - - bt_en_gpios: bt-en-pios-state { - pinconf { - pins = "gpio19"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; - bias-pull-down; - }; - }; - - wlan_en_gpios: wlan-en-gpios-state { - pinconf { - pins = "gpio8"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; - bias-pull-down; - }; - }; - - audio_mclk: clk-div1-state { - pinconf { - pins = "gpio15"; - function = "func1"; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - }; - }; - - volume_up_gpio: pm8996-gpio2-state { - pinconf { - pins = "gpio2"; - function = "normal"; - input-enable; - drive-push-pull; - bias-pull-up; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - }; - }; - - divclk4_pin_a: divclk4-state { - pinconf { - pins = "gpio18"; - function = PMIC_GPIO_FUNC_FUNC2; - - bias-disable; - power-source = <PM8994_GPIO_S4>; - }; - }; - - usb3_vbus_det_gpio: pm8996-gpio22-state { - pinconf { - pins = "gpio22"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - }; - }; -}; - -&pm8994_mpps { - gpio-line-names = - "VDDPX_BIAS", - "WIFI_LED", - "NC", - "BT_LED", - "PM_MPP05", - "PM_MPP06", - "PM_MPP07", - "NC"; -}; - -&pm8994_spmi_regulators { - qcom,saw-reg = <&saw3>; - vdd_s11-supply = <&vph_pwr>; - - s9 { - qcom,saw-slave; - }; - s10 { - qcom,saw-slave; - }; - s11 { - qcom,saw-leader; - regulator-name = "VDD_APCC"; - regulator-always-on; - regulator-min-microvolt = <980000>; - regulator-max-microvolt = <980000>; - }; -}; - -&pmi8994_gpios { - gpio-line-names = - "NC", - "SPKR_AMP_EN1", - "SPKR_AMP_EN2", - "TP61", - "NC", - "USB2_VBUS_DET", - "NC", - "NC", - "NC", - "NC"; - - usb2_vbus_det_gpio: pmi8996-gpio6-state { - pinconf { - pins = "gpio6"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; - power-source = <PM8994_GPIO_S4>; /* 1.8V */ - }; - }; -}; - -&pmi8994_lpg { - qcom,power-source = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmi8994_mpp2_userled4>; - - qcom,dtest = <0 0>, - <0 0>, - <0 0>, - <4 1>; - - status = "okay"; - - led@1 { - reg = <1>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <1>; - - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led@2 { - reg = <2>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <0>; - }; - - led@3 { - reg = <3>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <2>; - }; - - led@4 { - reg = <4>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <3>; - }; -}; - -&pmi8994_mpps { - pmi8994_mpp2_userled4: mpp2-userled4-state { - pins = "mpp2"; - function = "sink"; - - output-low; - qcom,dtest = <4>; - }; -}; - -&pmi8994_spmi_regulators { - vdd_s2-supply = <&vph_pwr>; - - vdd_gfx: s2 { - regulator-name = "VDD_GFX"; - regulator-min-microvolt = <980000>; - regulator-max-microvolt = <980000>; - }; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_l1-supply = <&vreg_s1b_1p025>; - vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s3a_1p3>; - vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; - vdd_l5_l7-supply = <&vreg_s5a_2p15>; - vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; - vdd_l8_l16_l30-supply = <&vph_pwr>; - vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; - vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; - vdd_l14_l15-supply = <&vreg_s5a_2p15>; - vdd_l17_l29-supply = <&vph_pwr_bbyp>; - vdd_l20_l21-supply = <&vph_pwr_bbyp>; - vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p3: s3 { - regulator-name = "vreg_s3a_1p3"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - vreg_s4a_1p8: s4 { - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - vreg_s5a_2p15: s5 { - regulator-name = "vreg_s5a_2p15"; - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - vreg_s7a_1p0: s7 { - regulator-name = "vreg_s7a_1p0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - vreg_l1a_1p0: l1 { - regulator-name = "vreg_l1a_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l2a_1p25: l2 { - regulator-name = "vreg_l2a_1p25"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - vreg_l3a_0p875: l3 { - regulator-name = "vreg_l3a_0p875"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - }; - vreg_l4a_1p225: l4 { - regulator-name = "vreg_l4a_1p225"; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - vreg_l6a_1p2: l6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l8a_1p8: l8 { - regulator-name = "vreg_l8a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l9a_1p8: l9 { - regulator-name = "vreg_l9a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l10a_1p8: l10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l11a_1p15: l11 { - regulator-name = "vreg_l11a_1p15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - vreg_l12a_1p8: l12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-name = "vreg_l13a_2p95"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l14a_1p8: l14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l15a_1p8: l15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vreg_l17a_2p8: l17 { - regulator-name = "vreg_l17a_2p8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - vreg_l18a_2p85: l18 { - regulator-name = "vreg_l18a_2p85"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2900000>; - }; - vreg_l19a_2p8: l19 { - regulator-name = "vreg_l19a_2p8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - vreg_l20a_2p95: l20 { - regulator-name = "vreg_l20a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-name = "vreg_l21a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - vreg_l22a_3p0: l22 { - regulator-name = "vreg_l22a_3p0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vreg_l23a_2p8: l23 { - regulator-name = "vreg_l23a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l24a_3p075: l24 { - regulator-name = "vreg_l24a_3p075"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - vreg_l25a_1p2: l25 { - regulator-name = "vreg_l25a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l26a_0p8: l27 { - regulator-name = "vreg_l26a_0p8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l28a_0p925: l28 { - regulator-name = "vreg_l28a_0p925"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <925000>; - regulator-allow-set-load; - }; - vreg_l29a_2p8: l29 { - regulator-name = "vreg_l29a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l30a_1p8: l30 { - regulator-name = "vreg_l30a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l32a_1p8: l32 { - regulator-name = "vreg_l32a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-name = "vreg_lvs1a_1p8"; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-name = "vreg_lvs2a_1p8"; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pmi8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_bst_byp-supply = <&vph_pwr>; - - vph_pwr_bbyp: boost-bypass { - regulator-name = "vph_pwr_bbyp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_s1b_1p025: s1 { - regulator-name = "vreg_s1b_1p025"; - regulator-min-microvolt = <1025000>; - regulator-max-microvolt = <1025000>; - }; - }; -}; - -&sdhc2 { - /* External SD card */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; - cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - status = "okay"; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - }; - - dai@1 { - reg = <1>; - }; - - dai@2 { - reg = <2>; - }; -}; - -&slim_msm { - status = "okay"; - - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - tasha_ifd: tas-ifd@0,0 { - compatible = "slim217,1a0"; - reg = <0 0>; - }; - - wcd9335: codec@1,0 { - compatible = "slim217,1a0"; - reg = <1 0>; - - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; - interrupt-controller; - #interrupt-cells = <1>; - - pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; - pinctrl-names = "default"; - - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - slim-ifc-dev = <&tasha_ifd>; - - #sound-dai-cells = <1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - }; - }; -}; - -&sound { - compatible = "qcom,apq8096-sndcard"; - model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MultiMedia3 Capture", "MM_UL3"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI"; - cpu { - sound-dai = <&q6afedai HDMI_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&mdss_hdmi 0>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_6_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 AIF4_PB>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 AIF1_CAP>; - }; - }; -}; - -&ufsphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&ufshc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l25a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - vdd-hba-supply = <&vreg_l25a_1p2>; - - vcc-max-microamp = <600000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <450000>; -}; - -&usb2 { - status = "okay"; - extcon = <&usb2_id>; -}; - -&usb2_dwc3 { - extcon = <&usb2_id>; - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&usb3 { - status = "okay"; - extcon = <&usb3_id>; -}; - -&usb3_dwc3 { - extcon = <&usb3_id>; - dr_mode = "otg"; -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&venus { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts deleted file mode 100644 index 7cd29ab970d..00000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 1 which has one ethernet port. It is - * different than the base variant, which also has one port, but here the - * port is connected via RGMII. This port is not TSN aware. - * None of the four SerDes lanes are used by the module, instead they are - * all led out to the carrier for customer use. - * - * Copyright (C) 2021 Michael Walle <michael@walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" -#include <dt-bindings/net/qca-ar803x.h> - -/ { - model = "Kontron SMARC-sAL28 (4 Lanes)"; - compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - /* Delete unused phy node */ - /delete-node/ ethernet-phy@5; - - phy0: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = <AR803X_STRENGTH_FULL>; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; - }; -}; - -&enetc_port0 { - status = "disabled"; - /* Delete the phy-handle to the old phy0 label */ - /delete-property/ phy-handle; -}; - -&enetc_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts deleted file mode 100644 index 330e34f933a..00000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 2 which has two ethernet ports. These - * ports are connected to the internal switch. - * - * Copyright (C) 2021 Michael Walle <michael@walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" - -/ { - model = "Kontron SMARC-sAL28 (TSN-on-module)"; - compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&enetc_port0 { - status = "disabled"; - /* - * In the base device tree the PHY at address 5 was assigned for - * this port. On this module this PHY is connected to a switch - * port instead. Therefore, delete the phy-handle property here. - */ - /delete-property/ phy-handle; -}; - -&enetc_port2 { - status = "okay"; -}; - -&mscc_felix { - status = "okay"; -}; - -&mscc_felix_port0 { - label = "swp0"; - managed = "in-band-status"; - phy-handle = <&phy0>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&mscc_felix_port1 { - label = "swp1"; - managed = "in-band-status"; - phy-handle = <&phy1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&mscc_felix_port4 { - ethernet = <&enetc_port2>; - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts deleted file mode 100644 index 0c8b2af41a6..00000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * Copyright (C) 2019 Michael Walle <michael@walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" - -/ { - model = "Kontron SMARC-sAL28 (Single PHY)"; - compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts deleted file mode 100644 index 9b5e92fb753..00000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 4 which has two ethernet ports. It - * extends the base and provides one more port connected via RGMII. - * - * Copyright (C) 2021 Michael Walle <michael@walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" -#include <dt-bindings/net/qca-ar803x.h> - -/ { - model = "Kontron SMARC-sAL28 (Dual PHY)"; - compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = <AR803X_STRENGTH_FULL>; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; - }; -}; - -&enetc_port1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts deleted file mode 100644 index ab713b4949b..00000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * Copyright (C) 2021 Michael Walle <michael@walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Kontron SMARC-sAL28"; - compatible = "kontron,sl28", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &lpuart1; - spi0 = &fspi; - spi1 = &dspi2; - mmc0 = &esdhc1; - mmc1 = &esdhc; - rtc0 = &rtc; - rtc1 = &ftm_alarm0; - }; - - buttons0 { - compatible = "gpio-keys"; - - power-button { - interrupts-extended = <&sl28cpld_intc - 4 IRQ_TYPE_EDGE_BOTH>; - linux,code = <KEY_POWER>; - label = "Power"; - }; - - sleep-button { - interrupts-extended = <&sl28cpld_intc - 5 IRQ_TYPE_EDGE_BOTH>; - linux,code = <KEY_SLEEP>; - label = "Sleep"; - }; - }; - - buttons1 { - compatible = "gpio-keys-polled"; - poll-interval = <200>; - - lid-switch { - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; - label = "Lid"; - }; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&can0 { - status = "okay"; -}; - -&dspi2 { - status = "okay"; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_mdio_pf3 { - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&enetc_port0 { - phy-handle = <&phy0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&esdhc { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <133000000>; - reg = <0>; - /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x000000 0x010000>; - label = "rcw"; - read-only; - }; - - partition@10000 { - reg = <0x010000 0x1d0000>; - label = "failsafe bootloader"; - read-only; - }; - - partition@200000 { - reg = <0x200000 0x010000>; - label = "configuration store"; - }; - - partition@210000 { - reg = <0x210000 0x1d0000>; - label = "bootloader"; - }; - - partition@3e0000 { - reg = <0x3e0000 0x020000>; - label = "bootloader environment"; - }; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "TDO", "TCK", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "TMS", "TDI", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c0 { - status = "okay"; - - rtc: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - sl28cpld@4a { - compatible = "kontron,sl28cpld"; - reg = <0x4a>; - #address-cells = <1>; - #size-cells = <0>; - - watchdog@4 { - compatible = "kontron,sl28cpld-wdt"; - reg = <0x4>; - kontron,assert-wdt-timeout-pin; - }; - - hwmon@b { - compatible = "kontron,sl28cpld-fan"; - reg = <0xb>; - }; - - sl28cpld_pwm0: pwm@c { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xc>; - #pwm-cells = <2>; - }; - - sl28cpld_pwm1: pwm@e { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xe>; - #pwm-cells = <2>; - }; - - sl28cpld_gpio0: gpio@10 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x10>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", - "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", - "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", - "GPIO6_TACHIN", "GPIO7"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sl28cpld_gpio1: gpio@15 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x15>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GPIO8", "GPIO9", "GPIO10", "GPIO11", - "", "", "", ""; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sl28cpld_gpio2: gpio@1a { - compatible = "kontron,sl28cpld-gpo"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "LCD0 voltage enable", - "LCD0 backlight enable", - "eMMC reset", "LVDS bridge reset", - "LVDS bridge power-down", - "SDIO power enable", - "", ""; - }; - - sl28cpld_gpio3: gpio@1b { - compatible = "kontron,sl28cpld-gpi"; - reg = <0x1b>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "Power button", "Force recovery", "Sleep", - "Battery low", "Lid state", "Charging", - "Charger present", ""; - }; - - sl28cpld_intc: interrupt-controller@1c { - compatible = "kontron,sl28cpld-intc"; - reg = <0x1c>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&lpuart1 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx6dl-brppt2.dts b/arch/arm/dts/imx6dl-brppt2.dts index 575bfac7bb7..05c843c3d0f 100644 --- a/arch/arm/dts/imx6dl-brppt2.dts +++ b/arch/arm/dts/imx6dl-brppt2.dts @@ -17,7 +17,7 @@ #include "imx6dl.dtsi" #include "imx6qdl-u-boot.dtsi" #include <dt-bindings/pwm/pwm.h> -#include <include/dt-bindings/gpio/gpio.h> +#include <dt-bindings/gpio/gpio.h> / { model = "PPT50"; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 06f2f73a03f..6ab8f66256e 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -5,7 +5,6 @@ / { binman: binman { - multiple-images; }; #ifdef CONFIG_OPTEE @@ -43,56 +42,61 @@ }; &binman { - u-boot-spl-ddr { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + filename = "flash.bin"; + section { + pad-byte = <0x00>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; +#ifdef CONFIG_FSPI_CONF_HEADER + fspi_conf_block { + filename = CONFIG_FSPI_CONF_FILE; type = "blob-ext"; + size = <0x1000>; }; +#endif - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; - }; + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - spl { - filename = "spl.bin"; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - mkimage { - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - blob { - filename = "u-boot-spl-ddr.bin"; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; }; }; - }; - - itb { - filename = "u-boot.itb"; fit { description = "Configuration to load ATF before U-Boot"; @@ -101,6 +105,11 @@ #endif fit,fdt-list = "of-list"; #address-cells = <1>; +#ifdef CONFIG_FSPI_CONF_HEADER + offset = <0x58C00>; +#else + offset = <0x57c00>; +#endif images { uboot { @@ -166,43 +175,6 @@ }; }; }; - - imx-boot { - filename = "flash.bin"; - pad-byte = <0x00>; - -#ifdef CONFIG_FSPI_CONF_HEADER - fspi_conf_block { - filename = CONFIG_FSPI_CONF_FILE; - type = "blob-ext"; - size = <0x1000>; - }; - - spl { - filename = "spl.bin"; - offset = <0x1000>; - type = "blob-ext"; - }; - - binman_uboot: uboot { - filename = "u-boot.itb"; - offset = <0x58C00>; - type = "blob-ext"; - }; -#else - spl { - filename = "spl.bin"; - offset = <0x0>; - type = "blob-ext"; - }; - - binman_uboot: uboot { - filename = "u-boot.itb"; - offset = <0x57c00>; - type = "blob-ext"; - }; -#endif - }; }; &clk { diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 38db56059d6..90183aff8bc 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -35,8 +35,12 @@ bootph-pre-ram; }; -&binman_uboot { - offset = <0x5fc00>; +&binman { + section { + fit { + offset = <0x5fc00>; + }; + }; }; &gpio1 { @@ -60,6 +64,11 @@ ctrl-sleep-moci-hog { bootph-pre-ram; + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + }; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 96b1a1bc802..ba9967dbe4a 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -5,7 +5,6 @@ / { binman: binman { - multiple-images; }; #ifdef CONFIG_OPTEE @@ -92,78 +91,83 @@ }; &binman { - u-boot-spl-ddr { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; + filename = "flash.bin"; + section { + pad-byte = <0x00>; + +#ifdef CONFIG_FSPI_CONF_HEADER + fspi_conf_block { + filename = CONFIG_FSPI_CONF_FILE; + type = "blob-ext"; + offset = <0x400>; }; +#endif - ddr-1d-imem-fw { + nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <2>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ + + section { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + + ddr-1d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_imem_1d_201810.bin"; + filename = "ddr4_imem_1d_201810.bin"; #else - filename = "ddr3_imem_1d.bin"; + filename = "ddr3_imem_1d.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; - ddr-1d-dmem-fw { + ddr-1d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_dmem_1d_201810.bin"; + filename = "ddr4_dmem_1d_201810.bin"; #else - filename = "ddr3_dmem_1d.bin"; + filename = "ddr3_dmem_1d.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; #if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) - ddr-2d-imem-fw { + ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem.bin"; #else - filename = "ddr4_imem_2d_201810.bin"; + filename = "ddr4_imem_2d_201810.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-dmem-fw { + ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem.bin"; #else - filename = "ddr4_dmem_2d_201810.bin"; + filename = "ddr4_dmem_2d_201810.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; #endif - }; - - spl { - filename = "spl.bin"; - - mkimage { - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; - - blob { - filename = "u-boot-spl-ddr.bin"; }; }; - }; - - itb { - filename = "u-boot.itb"; fit { description = "Configuration to load ATF before U-Boot"; @@ -172,6 +176,11 @@ #endif fit,fdt-list = "of-list"; #address-cells = <1>; +#ifdef CONFIG_FSPI_CONF_HEADER + offset = <0x59000>; +#else + offset = <0x58000>; +#endif images { uboot { @@ -237,42 +246,4 @@ }; }; }; - - imx-boot { - filename = "flash.bin"; - pad-byte = <0x00>; - -#ifdef CONFIG_FSPI_CONF_HEADER - fspi_conf_block { - filename = CONFIG_FSPI_CONF_FILE; - type = "blob-ext"; - offset = <0x400>; - }; - - spl { - filename = "spl.bin"; - offset = <0x1000>; - type = "blob-ext"; - }; - - binman_uboot: uboot { - filename = "u-boot.itb"; - offset = <0x59000>; - type = "blob-ext"; - }; -#else - - spl { - offset = <0x0>; - filename = "spl.bin"; - type = "blob-ext"; - }; - - binman_uboot: uboot { - offset = <0x58000>; - filename = "u-boot.itb"; - type = "blob-ext"; - }; -#endif - }; }; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi index 040f333c52d..b0b99d51856 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi @@ -4,3 +4,15 @@ */ #include "imx8mp-dhcom-u-boot.dtsi" + +/ { + clk_pcie100: clk-pcie100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; + +&pcie_phy { + clocks = <&clk_pcie100>; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index b05be57e71b..cb37e28f28f 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -136,7 +136,7 @@ }; &binman { - itb { + section { fit { images { fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index 22171bd344e..aff5dcf615d 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -136,7 +136,7 @@ }; &binman { - itb { + section { fit { images { fip { diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 4fadcaea509..c4c1a177102 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -6,7 +6,6 @@ / { binman: binman { - multiple-images; }; #ifdef CONFIG_OPTEE @@ -83,55 +82,52 @@ #endif &binman { - u-boot-spl-ddr { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; - - u-boot-spl { - align-end = <4>; - }; + filename = "flash.bin"; + section { + pad-byte = <0x00>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <2>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + section { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + u-boot-spl { + align-end = <4>; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - spl { - filename = "spl.bin"; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - mkimage { - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000"; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - blob { - filename = "u-boot-spl-ddr.bin"; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; }; }; - }; - - itb { - filename = "u-boot.itb"; fit { description = "Configuration to load ATF before U-Boot"; @@ -140,6 +136,7 @@ #endif fit,fdt-list = "of-list"; #address-cells = <1>; + offset = <0x58000>; images { uboot { @@ -195,21 +192,4 @@ }; }; }; - - imx-boot { - filename = "flash.bin"; - pad-byte = <0x00>; - - spl { - filename = "spl.bin"; - offset = <0x0>; - type = "blob-ext"; - }; - - binman_uboot: uboot { - filename = "u-boot.itb"; - offset = <0x58000>; - type = "blob-ext"; - }; - }; }; diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 03f211d5f7d..7b45a87450b 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -58,6 +58,10 @@ ctrl-sleep-moci-hog { bootph-pre-ram; + gpio-hog; + output-high; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; }; }; diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi b/arch/arm/dts/imx8mq-cm-u-boot.dtsi index e23998f5aba..819501337e9 100644 --- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi @@ -3,11 +3,7 @@ * Copyright 2019 NXP */ -/ { - binman: binman { - multiple-images; - }; -}; +#include "imx8mq-u-boot.dtsi" &pinctrl_uart1 { bootph-pre-ram; @@ -16,108 +12,3 @@ &uart1 { bootph-pre-ram; }; - -&binman { - u-boot-spl-ddr { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; - - u-boot-spl { - align-end = <4>; - }; - - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - type = "blob-ext"; - align-end = <4>; - }; - - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - type = "blob-ext"; - align-end = <4>; - }; - - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - type = "blob-ext"; - align-end = <4>; - }; - - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - type = "blob-ext"; - align-end = <4>; - }; - }; - - flash { - mkimage { - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; - - blob { - filename = "u-boot-spl-ddr.bin"; - }; - }; - }; - - itb { - filename = "u-boot.itb"; - - fit { - description = "Configuration to load ATF before U-Boot"; - #address-cells = <1>; - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; - - images { - uboot { - description = "U-Boot (64-bit)"; - type = "standalone"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - - uboot_blob: blob-ext { - filename = "u-boot-nodtb.bin"; - }; - }; - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x910000>; - entry = <0x910000>; - - atf_blob: blob-ext { - filename = "bl31.bin"; - }; - }; - - fdt { - description = "NAME"; - type = "flat_dt"; - compression = "none"; - - uboot_fdt_blob: blob-ext { - filename = "u-boot.dtb"; - }; - }; - }; - - configurations { - default = "conf"; - - conf { - description = "NAME"; - firmware = "uboot"; - loadables = "atf"; - fdt = "fdt"; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi index e3341a46d63..1a4568dac65 100644 --- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi @@ -11,14 +11,13 @@ }; &binman { - /delete-node/ signed-hdmi; - - signed-hdmi { - filename = "signed_hdmi.bin"; - - signed-dp-imx8m { - filename = "signed_dp_imx8m.bin"; - type = "blob-ext"; + section { + nxp-imx8mimage { + section { + signed-hdmi-imx8m { + filename = "signed_dp_imx8m.bin"; + }; + }; }; }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 90b2274754b..48dbe94f0c4 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -5,7 +5,6 @@ / { binman: binman { - multiple-images; }; }; @@ -35,65 +34,58 @@ }; &binman { - u-boot-spl-ddr { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + filename = "flash.bin"; + section { + pad-byte = <0x00>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; - - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; - }; + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - signed-hdmi { - filename = "signed_hdmi.bin"; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - signed-hdmi-imx8m { - filename = "signed_hdmi_imx8m.bin"; - type = "blob-ext"; - }; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - spl { - filename = "spl.bin"; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - mkimage { - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - blob { - filename = "u-boot-spl-ddr.bin"; + signed-hdmi-imx8m { + filename = "signed_hdmi_imx8m.bin"; + type = "blob-ext"; + }; }; }; - }; - - itb { - filename = "u-boot.itb"; fit { description = "Configuration to load ATF before U-Boot"; @@ -158,21 +150,4 @@ }; }; }; - - imx-boot { - filename = "flash.bin"; - pad-byte = <0x00>; - - spl { - filename = "spl.bin"; - offset = <0x0>; - type = "blob-ext"; - }; - - binman_uboot: uboot { - filename = "u-boot.itb"; - offset = <0x57c00>; - type = "blob-ext"; - }; - }; }; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index a99ba99bfb4..408e601bc90 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -26,6 +26,111 @@ bootph-pre-ram; }; +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585gpio: gpio@34 { + compatible = "adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &aips1 { bootph-pre-ram; bootph-all; @@ -44,6 +149,19 @@ &iomuxc { bootph-pre-ram; bootph-some-ram; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; }; ®_usdhc2_vmmc { diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts deleted file mode 100644 index 4322cc3e11b..00000000000 --- a/arch/arm/dts/imx93-11x11-evk.dts +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 NXP - */ - -/dts-v1/; - -#include "imx93.dtsi" - -/ { - model = "NXP i.MX93 11X11 EVK board"; - compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; - - chosen { - stdout-path = &lpuart1; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&mu1 { - status = "okay"; -}; - -&mu2 { - status = "okay"; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - eee-broken-1000t; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - eee-broken-1000t; - }; - }; -}; - -&lpi2c2 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-1 = <&pinctrl_lpi2c2>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupt-parent = <&pcal6524>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2237500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6524>; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - adp5585gpio: gpio@34 { - compatible = "adp5585"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&lpuart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; - no-sdio; - no-mmc; -}; - -&iomuxc { - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e - >; - }; - - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; -}; diff --git a/arch/arm/dts/imx93-u-boot.dtsi b/arch/arm/dts/imx93-u-boot.dtsi index 40e17bbc5ae..289aba17584 100644 --- a/arch/arm/dts/imx93-u-boot.dtsi +++ b/arch/arm/dts/imx93-u-boot.dtsi @@ -86,3 +86,18 @@ }; }; }; + +&tmu { + compatible = "fsl,imx93-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; + #thermal-sensor-cells = <1>; +}; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 6f5845024f2..a9b86b61e53 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -150,12 +150,107 @@ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; + + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x40000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl { insert-template = <&ti_spl_template>; fit { images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-secure { content = <&dm>; @@ -187,7 +282,8 @@ conf-0 { description = "k3-am625-verdin-wifi-dev"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -243,6 +339,45 @@ fit { images { + tifsstub-hs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-dm { filename = "ti-dm.bin"; @@ -266,7 +401,8 @@ conf-0 { description = "k3-am625-verdin-wifi-dev"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index 7fe7ae41543..9ecb3052740 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -91,6 +91,14 @@ &main_gpio0 { bootph-all; + + ctrl-sleep-moci-hog { + bootph-all; + gpio-hog; + gpios = <31 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; }; /* On-module I2C - PMIC_I2C */ @@ -165,10 +173,6 @@ status = "disabled"; }; -&verdin_ctrl_sleep_moci { - bootph-all; -}; - /* Verdin UART_2 */ &wkup_uart0 { bootph-all; diff --git a/arch/arm/dts/k3-am654-icssg2.dtso b/arch/arm/dts/k3-am654-icssg2.dtso new file mode 100644 index 00000000000..faefa2febcf --- /dev/null +++ b/arch/arm/dts/k3-am654-icssg2.dtso @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for enabling ICSSG2 on AM654 EVM + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/net/ti-dp83867.h> +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg2-eth/ethernet-ports/port@0"; + ethernet2 = "/icssg2-eth/ethernet-ports/port@1"; + }; + + /* Ethernet node on PRU-ICSSG2 */ + icssg2_eth: icssg2-eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_rgmii_pins_default>; + sram = <&msmc_ram>; + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg2_mii_g_rt>; + ti,mii-rt = <&icssg2_mii_rt>; + ti,iep = <&icssg2_iep0>, <&icssg2_iep1>; + + interrupt-parent = <&icssg2_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_udmap 0xc300>, /* egress slice 0 */ + <&main_udmap 0xc301>, /* egress slice 0 */ + <&main_udmap 0xc302>, /* egress slice 0 */ + <&main_udmap 0xc303>, /* egress slice 0 */ + <&main_udmap 0xc304>, /* egress slice 1 */ + <&main_udmap 0xc305>, /* egress slice 1 */ + <&main_udmap 0xc306>, /* egress slice 1 */ + <&main_udmap 0xc307>, /* egress slice 1 */ + <&main_udmap 0x4300>, /* ingress slice 0 */ + <&main_udmap 0x4301>; /* ingress slice 1 */ + + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg2_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg2_phy0>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4120>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg2_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg2_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4124>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&main_pmx0 { + + icssg2_mdio_pins_default: icssg2-mdio-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */ + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */ + >; + }; + + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */ + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */ + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */ + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */ + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */ + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */ + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */ + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */ + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */ + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */ + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */ + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */ + + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */ + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */ + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */ + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */ + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */ + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */ + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */ + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */ + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */ + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */ + >; + }; +}; + +&icssg2_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + icssg2_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + + icssg2_phy1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi index 8cc24da1f3f..d0cd4889cde 100644 --- a/arch/arm/dts/k3-am65x-binman.dtsi +++ b/arch/arm/dts/k3-am65x-binman.dtsi @@ -98,6 +98,8 @@ #define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb" #define AM654_EVM_DTB "u-boot.dtb" +#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo" + &binman { ti-spl { insert-template = <&ti_spl_template>; @@ -124,6 +126,20 @@ filename = SPL_AM654_EVM_DTB; }; }; + + fdt-1 { + description = "k3-am654-icssg2 overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am65x_evm_icssg2_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am65x_evm_icssg2_dtb: blob-ext { + filename = AM654_EVM_ICSSG2_DTBO; + }; + }; }; configurations { @@ -133,7 +149,7 @@ description = "k3-am654-base-board"; firmware = "atf"; loadables = "tee", "dm", "spl"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; @@ -168,6 +184,24 @@ }; }; + fdt-1 { + description = "k3-am654-icssg2 overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am65x_evm_icssg2_dtb>; + keyfile = "custMpk.pem"; + + }; + am65x_evm_icssg2_dtb: blob-ext { + filename = AM654_EVM_ICSSG2_DTBO; + }; + hash { + algo = "crc32"; + }; + }; + }; configurations { @@ -177,7 +211,7 @@ description = "k3-am654-base-board"; firmware = "uboot"; loadables = "uboot"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; @@ -205,6 +239,16 @@ filename = SPL_AM654_EVM_DTB; }; }; + + fdt-1 { + description = "k3-am654-icssg2 overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM654_EVM_ICSSG2_DTBO; + }; + }; }; configurations { @@ -214,7 +258,7 @@ description = "k3-am654-base-board"; firmware = "atf"; loadables = "tee", "dm", "spl"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; @@ -243,6 +287,19 @@ algo = "crc32"; }; }; + + fdt-1 { + description = "k3-am654-icssg2"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM654_EVM_ICSSG2_DTBO; + }; + hash { + algo = "crc32"; + }; + }; }; configurations { @@ -252,7 +309,7 @@ description = "k3-am654-base-board"; firmware = "uboot"; loadables = "uboot"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; diff --git a/arch/arm/dts/msm8916-pm8916.dtsi b/arch/arm/dts/msm8916-pm8916.dtsi deleted file mode 100644 index b1a7eafbee3..00000000000 --- a/arch/arm/dts/msm8916-pm8916.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections) - * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC. - * Many regulators have a fixed purpose in the original reference design and - * were rarely re-used for different purposes. Devices that deviate from the - * typical reference design should not make use of this include and instead add - * the necessary properties in the board-specific device tree. - */ - -#include "msm8916.dtsi" -#include "pm8916.dtsi" - -&camss { - vdda-supply = <&pm8916_l2>; -}; - -&mdss_dsi0 { - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; -}; - -&mdss_dsi0_phy { - vddio-supply = <&pm8916_l6>; -}; - -&mpss { - pll-supply = <&pm8916_l7>; -}; - -&pm8916_codec { - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; -}; - -&sdhc_1 { - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; -}; - -&sdhc_2 { - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; -}; - -&usb_hs_phy { - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; -}; - -&wcnss { - vddpx-supply = <&pm8916_l7>; -}; - -&wcnss_iris { - vddxo-supply = <&pm8916_l7>; - vddrfa-supply = <&pm8916_s3>; - vddpa-supply = <&pm8916_l9>; - vdddig-supply = <&pm8916_l5>; -}; - -&rpm_requests { - pm8916_rpm_regulators: regulators { - compatible = "qcom,rpm-pm8916-regulators"; - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ - - pm8916_s3: s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; /* Needed for L2 */ - }; - - pm8916_s4: s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - regulator-always-on; /* Needed for L5/L7 */ - }; - - /* - * Some of the regulators are unused or managed by another - * processor (e.g. the modem). We should still define nodes for - * them to ensure the vote from the application processor can be - * dropped in case the regulators are already on during boot. - * - * The labels for these nodes are omitted on purpose because - * boards should configure a proper voltage before using them. - */ - l1 {}; - - pm8916_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; /* Needed for LPDDR RAM */ - }; - - /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ - - l4 {}; - - pm8916_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; /* Needed for most digital I/O */ - }; - - pm8916_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; /* Needed for CPU PLL */ - }; - - pm8916_l8: l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - pm8916_l9: l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 {}; - - pm8916_l11: l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - pm8916_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8916_l13: l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 {}; - l15 {}; - l16 {}; - l17 {}; - l18 {}; - }; -}; diff --git a/arch/arm/dts/msm8916.dtsi b/arch/arm/dts/msm8916.dtsi deleted file mode 100644 index 4f799b536a9..00000000000 --- a/arch/arm/dts/msm8916.dtsi +++ /dev/null @@ -1,2702 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -#include <dt-bindings/arm/coresight-cti-dt.h> -#include <dt-bindings/clock/qcom,gcc-msm8916.h> -#include <dt-bindings/clock/qcom,rpmcc.h> -#include <dt-bindings/interconnect/qcom,msm8916.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/qcom-rpmpd.h> -#include <dt-bindings/reset/qcom,gcc-msm8916.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0x80000000 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz-apps@86000000 { - reg = <0x0 0x86000000 0x0 0x300000>; - no-map; - }; - - smem@86300000 { - compatible = "qcom,smem"; - reg = <0x0 0x86300000 0x0 0x100000>; - no-map; - - hwlocks = <&tcsr_mutex 3>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - }; - - hypervisor@86400000 { - reg = <0x0 0x86400000 0x0 0x100000>; - no-map; - }; - - tz@86500000 { - reg = <0x0 0x86500000 0x0 0x180000>; - no-map; - }; - - reserved@86680000 { - reg = <0x0 0x86680000 0x0 0x80000>; - no-map; - }; - - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x86700000 0x0 0xe0000>; - no-map; - - qcom,client-id = <1>; - }; - - rfsa@867e0000 { - reg = <0x0 0x867e0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: mpss@86800000 { - /* - * The memory region for the mpss firmware is generally - * relocatable and could be allocated dynamically. - * However, many firmware versions tend to fail when - * loaded to some special addresses, so it is hard to - * define reliable alloc-ranges. - * - * alignment = <0x0 0x400000>; - * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; - */ - reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ - no-map; - status = "disabled"; - }; - - wcnss_mem: wcnss { - size = <0x0 0x600000>; - alignment = <0x0 0x100000>; - alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; - no-map; - status = "disabled"; - }; - - venus_mem: venus { - size = <0x0 0x500000>; - alignment = <0x0 0x100000>; - alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; - no-map; - status = "disabled"; - }; - - mba_mem: mba { - size = <0x0 0x100000>; - alignment = <0x0 0x100000>; - alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; - no-map; - status = "disabled"; - }; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - qcom,acc = <&cpu0_acc>; - qcom,saw = <&cpu0_saw>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - qcom,acc = <&cpu1_acc>; - qcom,saw = <&cpu1_saw>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - qcom,acc = <&cpu2_acc>; - qcom,saw = <&cpu2_saw>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - qcom,acc = <&cpu3_acc>; - qcom,saw = <&cpu3_saw>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x40000002>; - entry-latency-us = <130>; - exit-latency-us = <150>; - min-residency-us = <2000>; - local-timer-stop; - }; - }; - - domain-idle-states { - - CLUSTER_RET: cluster-retention { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x41000012>; - entry-latency-us = <500>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - - CLUSTER_PWRDN: cluster-gdhs { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x41000032>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - }; - - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - }; - opp-998400000 { - opp-hz = /bits/ 64 <998400000>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-msm8916", "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "core", "bus", "iface"; - #reset-cells = <1>; - - qcom,dload-mode = <&tcsr 0x6100>; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: power-domain-cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD1: power-domain-cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD2: power-domain-cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD3: power-domain-cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CLUSTER_PD: power-domain-cluster { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; - }; - }; - - rpm: remoteproc { - compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; - - smd-edge { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8916-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - - smp2p-hexagon { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - hexagon_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - hexagon_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - hexagon_smsm: hexagon@1 { - reg = <1>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@6 { - reg = <6>; - interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - rng@22000 { - compatible = "qcom,prng"; - reg = <0x00022000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x004ab000 0x4>; - }; - - qfprom: qfprom@5c000 { - compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; - reg = <0x0005c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_base1: base1@d0 { - reg = <0xd0 0x1>; - bits = <0 7>; - }; - - tsens_s0_p1: s0-p1@d0 { - reg = <0xd0 0x2>; - bits = <7 5>; - }; - - tsens_s0_p2: s0-p2@d1 { - reg = <0xd1 0x2>; - bits = <4 5>; - }; - - tsens_s1_p1: s1-p1@d2 { - reg = <0xd2 0x1>; - bits = <1 5>; - }; - tsens_s1_p2: s1-p2@d2 { - reg = <0xd2 0x2>; - bits = <6 5>; - }; - tsens_s2_p1: s2-p1@d3 { - reg = <0xd3 0x1>; - bits = <3 5>; - }; - - tsens_s2_p2: s2-p2@d4 { - reg = <0xd4 0x1>; - bits = <0 5>; - }; - - // no tsens with hw_id 3 - - tsens_s4_p1: s4-p1@d4 { - reg = <0xd4 0x2>; - bits = <5 5>; - }; - - tsens_s4_p2: s4-p2@d5 { - reg = <0xd5 0x1>; - bits = <2 5>; - }; - - tsens_s5_p1: s5-p1@d5 { - reg = <0xd5 0x2>; - bits = <7 5>; - }; - - tsens_s5_p2: s5-p2@d6 { - reg = <0xd6 0x2>; - bits = <4 5>; - }; - - tsens_base2: base2@d7 { - reg = <0xd7 0x1>; - bits = <1 7>; - }; - - tsens_mode: mode@ef { - reg = <0xef 0x1>; - bits = <5 3>; - }; - }; - - rpm_msg_ram: sram@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00060000 0x8000>; - }; - - sram@290000 { - compatible = "qcom,msm8916-rpm-stats"; - reg = <0x00290000 0x10000>; - }; - - bimc: interconnect@400000 { - compatible = "qcom,msm8916-bimc"; - reg = <0x00400000 0x62000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - tsens: thermal-sensor@4a9000 { - compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - - // no hw_id 3 - nvmem-cells = <&tsens_mode>, - <&tsens_base1>, <&tsens_base2>, - <&tsens_s0_p1>, <&tsens_s0_p2>, - <&tsens_s1_p1>, <&tsens_s1_p2>, - <&tsens_s2_p1>, <&tsens_s2_p2>, - <&tsens_s4_p1>, <&tsens_s4_p2>, - <&tsens_s5_p1>, <&tsens_s5_p2>; - nvmem-cell-names = "mode", - "base1", "base2", - "s0_p1", "s0_p2", - "s1_p1", "s1_p2", - "s2_p1", "s2_p2", - "s4_p1", "s4_p2", - "s5_p1", "s5_p2"; - #qcom,sensors = <5>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - pcnoc: interconnect@500000 { - compatible = "qcom,msm8916-pcnoc"; - reg = <0x00500000 0x11000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, - <&rpmcc RPM_SMD_PCNOC_A_CLK>; - }; - - snoc: interconnect@580000 { - compatible = "qcom,msm8916-snoc"; - reg = <0x00580000 0x14000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - stm: stm@802000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x00802000 0x1000>, - <0x09280000 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - /* System CTIs */ - /* CTI 0 - TMC connections */ - cti0: cti@810000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x00810000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - status = "disabled"; - }; - - /* CTI 1 - TPIU connections */ - cti1: cti@811000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x00811000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - status = "disabled"; - }; - - /* CTIs 2-11 - no information - not instantiated */ - - tpiu: tpiu@820000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x00820000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel0: funnel@821000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x00821000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected to Resource and Power Manger CPU ETM - * 1 - not-connected - * 2 - connected to Modem CPU ETM - * 3 - not-connected - * 5 - not-connected - * 6 - connected trought funnel to Wireless CPU ETM - * 7 - connected to STM component - */ - - port@4 { - reg = <4>; - funnel0_in4: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - }; - - replicator: replicator@824000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x00824000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf: etf@825000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x00825000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - }; - - etr: etr@826000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x00826000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x00841000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel1_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - funnel1_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - funnel1_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - funnel1_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&funnel0_in4>; - }; - }; - }; - }; - - debug0: debug@850000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00850000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; - status = "disabled"; - }; - - debug1: debug@852000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00852000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; - status = "disabled"; - }; - - debug2: debug@854000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00854000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; - status = "disabled"; - }; - - debug3: debug@856000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00856000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; - status = "disabled"; - }; - - /* Core CTIs; CTIs 12-15 */ - /* CTI - CPU-0 */ - cti12: cti@858000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x00858000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - arm,cs-dev-assoc = <&etm0>; - - status = "disabled"; - }; - - /* CTI - CPU-1 */ - cti13: cti@859000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x00859000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - arm,cs-dev-assoc = <&etm1>; - - status = "disabled"; - }; - - /* CTI - CPU-2 */ - cti14: cti@85a000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x0085a000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - arm,cs-dev-assoc = <&etm2>; - - status = "disabled"; - }; - - /* CTI - CPU-3 */ - cti15: cti@85b000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x0085b000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - arm,cs-dev-assoc = <&etm3>; - - status = "disabled"; - }; - - etm0: etm@85c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085c000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU0>; - - status = "disabled"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel1_in0>; - }; - }; - }; - }; - - etm1: etm@85d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085d000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU1>; - - status = "disabled"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel1_in1>; - }; - }; - }; - }; - - etm2: etm@85e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085e000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU2>; - - status = "disabled"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel1_in2>; - }; - }; - }; - }; - - etm3: etm@85f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085f000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU3>; - - status = "disabled"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel1_in3>; - }; - }; - }; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,msm8916-pinctrl"; - reg = <0x01000000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 122>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp_i2c1_default: blsp-i2c1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c1_sleep: blsp-i2c1-sleep-state { - pins = "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c2_default: blsp-i2c2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c2_sleep: blsp-i2c2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c3_default: blsp-i2c3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c3_sleep: blsp-i2c3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c4_default: blsp-i2c4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c4_sleep: blsp-i2c4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c5_default: blsp-i2c5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c5_sleep: blsp-i2c5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c6_default: blsp-i2c6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c6_sleep: blsp-i2c6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp_spi1_default: blsp-spi1-default-state { - spi-pins { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio2"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi1_sleep: blsp-spi1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi2_default: blsp-spi2-default-state { - spi-pins { - pins = "gpio4", "gpio5", "gpio7"; - function = "blsp_spi2"; - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio6"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi2_sleep: blsp-spi2-sleep-state { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi3_default: blsp-spi3-default-state { - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio10"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi3_sleep: blsp-spi3-sleep-state { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi4_default: blsp-spi4-default-state { - spi-pins { - pins = "gpio12", "gpio13", "gpio15"; - function = "blsp_spi4"; - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio14"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi4_sleep: blsp-spi4-sleep-state { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi5_default: blsp-spi5-default-state { - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio18"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi5_sleep: blsp-spi5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi6_default: blsp-spi6-default-state { - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio22"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi6_sleep: blsp-spi6-sleep-state { - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_uart1_default: blsp-uart1-default-state { - /* TX, RX, CTS_N, RTS_N */ - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - drive-strength = <16>; - bias-disable; - }; - - blsp_uart1_sleep: blsp-uart1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp_uart2_default: blsp-uart2-default-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - drive-strength = <16>; - bias-disable; - }; - - blsp_uart2_sleep: blsp-uart2-sleep-state { - pins = "gpio4", "gpio5"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - camera_front_default: camera-front-default-state { - pwdn-pins { - pins = "gpio33"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - rst-pins { - pins = "gpio28"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - mclk1-pins { - pins = "gpio27"; - function = "cam_mclk1"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera-rear-default-state { - pwdn-pins { - pins = "gpio34"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - rst-pins { - pins = "gpio35"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - mclk0-pins { - pins = "gpio26"; - function = "cam_mclk0"; - drive-strength = <16>; - bias-disable; - }; - }; - - cci0_default: cci0-default-state { - pins = "gpio29", "gpio30"; - function = "cci_i2c"; - drive-strength = <16>; - bias-disable; - }; - - cdc_dmic_default: cdc-dmic-default-state { - clk-pins { - pins = "gpio0"; - function = "dmic0_clk"; - drive-strength = <8>; - }; - data-pins { - pins = "gpio1"; - function = "dmic0_data"; - drive-strength = <8>; - }; - }; - - cdc_dmic_sleep: cdc-dmic-sleep-state { - clk-pins { - pins = "gpio0"; - function = "dmic0_clk"; - drive-strength = <2>; - bias-disable; - }; - data-pins { - pins = "gpio1"; - function = "dmic0_data"; - drive-strength = <2>; - bias-disable; - }; - }; - - cdc_pdm_default: cdc-pdm-default-state { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - drive-strength = <8>; - bias-disable; - }; - - cdc_pdm_sleep: cdc-pdm-sleep-state { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - drive-strength = <2>; - bias-pull-down; - }; - - pri_mi2s_default: mi2s-pri-default-state { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - drive-strength = <8>; - bias-disable; - }; - - pri_mi2s_sleep: mi2s-pri-sleep-state { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - drive-strength = <2>; - bias-disable; - }; - - pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { - pins = "gpio116"; - function = "pri_mi2s"; - drive-strength = <8>; - bias-disable; - }; - - pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { - pins = "gpio116"; - function = "pri_mi2s"; - drive-strength = <2>; - bias-disable; - }; - - pri_mi2s_ws_default: mi2s-pri-ws-default-state { - pins = "gpio110"; - function = "pri_mi2s_ws"; - drive-strength = <8>; - bias-disable; - }; - - pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { - pins = "gpio110"; - function = "pri_mi2s_ws"; - drive-strength = <2>; - bias-disable; - }; - - sec_mi2s_default: mi2s-sec-default-state { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - drive-strength = <8>; - bias-disable; - }; - - sec_mi2s_sleep: mi2s-sec-sleep-state { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - drive-strength = <2>; - bias-disable; - }; - - sdc1_default: sdc1-default-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc1_sleep: sdc1-sleep-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_default: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_sleep: sdc2-sleep-state { - clk-pins { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - wcss_wlan_default: wcss-wlan-default-state { - pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; - function = "wcss_wlan"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-msm8916"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x01800000 0x80000>; - clocks = <&xo_board>, - <&sleep_clk>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <0>, - <0>, - <0>; - clock-names = "xo", - "sleep_clk", - "dsi0pll", - "dsi0pllbyte", - "ext_mclk", - "ext_pri_i2s", - "ext_sec_i2s"; - }; - - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01905000 0x20000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@1937000 { - compatible = "qcom,tcsr-msm8916", "syscon"; - reg = <0x01937000 0x30000>; - }; - - mdss: display-subsystem@1a00000 { - status = "disabled"; - compatible = "qcom,mdss"; - reg = <0x01a00000 0x1000>, - <0x01ac8000 0x3000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&gcc MDSS_GDSC>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync"; - - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdss_mdp: display-controller@1a01000 { - compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; - reg = <0x01a01000 0x89000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - iommus = <&apps_iommu 4>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_mdp_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; - }; - }; - }; - }; - - mdss_dsi0: dsi@1a98000 { - compatible = "qcom,msm8916-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0x01a98000 0x25c>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - assigned-clocks = <&gcc BYTE0_CLK_SRC>, - <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; - - clocks = <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_BYTE0_CLK>, - <&gcc GCC_MDSS_PCLK0_CLK>, - <&gcc GCC_MDSS_ESC0_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core"; - phys = <&mdss_dsi0_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi0_in: endpoint { - remote-endpoint = <&mdss_mdp_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi0_out: endpoint { - }; - }; - }; - }; - - mdss_dsi0_phy: phy@1a98300 { - compatible = "qcom,dsi-phy-28nm-lp"; - reg = <0x01a98300 0xd4>, - <0x01a98500 0x280>, - <0x01a98780 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "ref"; - }; - }; - - camss: camss@1b0ac00 { - compatible = "qcom,msm8916-camss"; - reg = <0x01b0ac00 0x200>, - <0x01b00030 0x4>, - <0x01b0b000 0x200>, - <0x01b00038 0x4>, - <0x01b08000 0x100>, - <0x01b08400 0x100>, - <0x01b0a000 0x500>, - <0x01b00020 0x10>, - <0x01b10000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csid0", - "csid1", - "ispif", - "csi_clk_mux", - "vfe0"; - interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "csiphy0", - "csiphy1", - "csid0", - "csid1", - "ispif", - "vfe0"; - power-domains = <&gcc VFE_GDSC>; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI0_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0_CLK>, - <&gcc GCC_CAMSS_CSI0PHY_CLK>, - <&gcc GCC_CAMSS_CSI0PIX_CLK>, - <&gcc GCC_CAMSS_CSI0RDI_CLK>, - <&gcc GCC_CAMSS_CSI1_AHB_CLK>, - <&gcc GCC_CAMSS_CSI1_CLK>, - <&gcc GCC_CAMSS_CSI1PHY_CLK>, - <&gcc GCC_CAMSS_CSI1PIX_CLK>, - <&gcc GCC_CAMSS_CSI1RDI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>, - <&gcc GCC_CAMSS_VFE0_CLK>, - <&gcc GCC_CAMSS_CSI_VFE0_CLK>, - <&gcc GCC_CAMSS_VFE_AHB_CLK>, - <&gcc GCC_CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe_ahb", - "vfe_axi"; - iommus = <&apps_iommu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - cci: cci@1b0c000 { - compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01b0c000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>; - clock-names = "camss_top_ahb", "cci_ahb", - "cci", "camss_ahb"; - assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_CLK>; - assigned-clock-rates = <80000000>, <19200000>; - pinctrl-names = "default"; - pinctrl-0 = <&cci0_default>; - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gpu: gpu@1c00000 { - compatible = "qcom,adreno-306.0", "qcom,adreno"; - reg = <0x01c00000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core", - "iface", - "mem", - "mem_iface", - "alt_mem_iface", - "gfx3d"; - clocks = - <&gcc GCC_OXILI_GFX3D_CLK>, - <&gcc GCC_OXILI_AHB_CLK>, - <&gcc GCC_OXILI_GMEM_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_BIMC_GPU_CLK>, - <&gcc GFX3D_CLK_SRC>; - power-domains = <&gcc OXILI_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - }; - }; - }; - - venus: video-codec@1d00000 { - compatible = "qcom,msm8916-venus"; - reg = <0x01d00000 0xff000>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&gcc VENUS_GDSC>; - clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, - <&gcc GCC_VENUS0_AHB_CLK>, - <&gcc GCC_VENUS0_AXI_CLK>; - clock-names = "core", "iface", "bus"; - iommus = <&apps_iommu 5>; - memory-region = <&venus_mem>; - status = "disabled"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - }; - - apps_iommu: iommu@1ef0000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x01e20000 0x20000>; - reg = <0x01ef0000 0x3000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_APSS_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <17>; - - /* VFE */ - iommu-ctx@3000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x3000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* MDP_0 */ - iommu-ctx@4000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x4000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* VENUS_NS */ - iommu-ctx@5000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x5000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpu_iommu: iommu@1f08000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x01f08000 0x10000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_GFX_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <18>; - - /* GFX3D_USER */ - iommu-ctx@1000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x1000 0x1000>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* GFX3D_PRIV */ - iommu-ctx@2000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x2000 0x1000>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x400000>, - <0x02c00000 0x400000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - bam_dmux_dma: dma-controller@4044000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x04044000 0x19000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - qcom,ee = <0>; - - num-channels = <6>; - qcom,num-ees = <1>; - qcom,powered-remotely; - - status = "disabled"; - }; - - mpss: remoteproc@4080000 { - compatible = "qcom,msm8916-mss-pil"; - reg = <0x04080000 0x100>, - <0x04020000 0x040>; - - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; - power-domain-names = "cx", "mx"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - qcom,smem-states = <&hexagon_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&scm 0>; - reset-names = "mss_restart"; - - qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; - - status = "disabled"; - - mba { - memory-region = <&mba_mem>; - }; - - mpss { - memory-region = <&mpss_mem>; - }; - - bam_dmux: bam-dmux { - compatible = "qcom,bam-dmux"; - - interrupt-parent = <&hexagon_smsm>; - interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pc", "pc-ack"; - - qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; - qcom,smem-state-names = "pc", "pc-ack"; - - dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; - dma-names = "tx", "rx"; - - status = "disabled"; - }; - - smd-edge { - interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - - qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; - qcom,remote-pid = <1>; - - label = "hexagon"; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,smd-channels = "fastrpcsmd-apps-dsp"; - label = "adsp"; - qcom,non-secure-domain; - - #address-cells = <1>; - #size-cells = <0>; - - cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - }; - }; - }; - }; - - sound: sound@7702000 { - status = "disabled"; - compatible = "qcom,apq8016-sbc-sndcard"; - reg = <0x07702000 0x4>, <0x07702004 0x4>; - reg-names = "mic-iomux", "spkr-iomux"; - }; - - lpass: audio-controller@7708000 { - status = "disabled"; - compatible = "qcom,apq8016-lpass-cpu"; - - /* - * Note: Unlike the name would suggest, the SEC_I2S_CLK - * is actually only used by Tertiary MI2S while - * Primary/Secondary MI2S both use the PRI_I2S_CLK. - */ - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; - - clock-names = "ahbix-clk", - "mi2s-bit-clk0", - "mi2s-bit-clk1", - "mi2s-bit-clk2", - "mi2s-bit-clk3", - "pcnoc-mport-clk", - "pcnoc-sway-clk"; - #sound-dai-cells = <1>; - - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x07708000 0x10000>; - reg-names = "lpass-lpaif"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - lpass_codec: audio-codec@771c000 { - compatible = "qcom,msm8916-wcd-digital-codec"; - reg = <0x0771c000 0x400>; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "ahbix-clk", "mclk"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - sdhc_1: mmc@7824900 { - compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc", "core"; - - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - pinctrl-0 = <&sdc1_default>; - pinctrl-1 = <&sdc1_sleep>; - pinctrl-names = "default", "sleep"; - mmc-ddr-1_8v; - bus-width = <8>; - non-removable; - status = "disabled"; - }; - - sdhc_2: mmc@7864900 { - compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc", "core"; - - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - pinctrl-0 = <&sdc2_default>; - pinctrl-1 = <&sdc2_sleep>; - pinctrl-names = "default", "sleep"; - bus-width = <4>; - status = "disabled"; - }; - - blsp_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 0>, <&blsp_dma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_uart1_default>; - pinctrl-1 = <&blsp_uart1_sleep>; - status = "disabled"; - }; - - blsp_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b0000 0x200>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 2>, <&blsp_dma 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c1: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, <&blsp_dma 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_i2c1_default>; - pinctrl-1 = <&blsp_i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, <&blsp_dma 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_spi1_default>; - pinctrl-1 = <&blsp_spi1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c2: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 6>, <&blsp_dma 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_i2c2_default>; - pinctrl-1 = <&blsp_i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi2: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 6>, <&blsp_dma 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_spi2_default>; - pinctrl-1 = <&blsp_spi2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c3: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b7000 0x500>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 8>, <&blsp_dma 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_i2c3_default>; - pinctrl-1 = <&blsp_i2c3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi3: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x500>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 8>, <&blsp_dma 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_spi3_default>; - pinctrl-1 = <&blsp_spi3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c4: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 10>, <&blsp_dma 11>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_i2c4_default>; - pinctrl-1 = <&blsp_i2c4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi4: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 10>, <&blsp_dma 11>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_spi4_default>; - pinctrl-1 = <&blsp_spi4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c5: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 12>, <&blsp_dma 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_i2c5_default>; - pinctrl-1 = <&blsp_i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi5: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 12>, <&blsp_dma 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_spi5_default>; - pinctrl-1 = <&blsp_spi5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c6: i2c@78ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 14>, <&blsp_dma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_i2c6_default>; - pinctrl-1 = <&blsp_i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi6: spi@78ba000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 14>, <&blsp_dma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_spi6_default>; - pinctrl-1 = <&blsp_spi6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb: usb@78d9000 { - compatible = "qcom,ci-hdrc"; - reg = <0x078d9000 0x200>, - <0x078d9200 0x200>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <80000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - phys = <&usb_hs_phy>; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs_phy: phy { - compatible = "qcom,usb-hs-phy-msm8916", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; - reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44>, - <0x1 0x6b>, - <0x2 0x24>, - <0x3 0x13>; - }; - }; - }; - - wcnss: remoteproc@a204000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_mem>; - - interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; - power-domain-names = "cx", "mx"; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcss_wlan_default>; - - status = "disabled"; - - wcnss_iris: iris { - /* Separate chip, compatible is board-specific */ - clocks = <&rpmcc RPM_SMD_RF_CLK2>; - clock-names = "xo"; - }; - - smd-edge { - interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss_ctrl: wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&wcnss>; - - wcnss_bt: bluetooth { - compatible = "qcom,wcnss-bt"; - }; - - wcnss_wifi: wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, - <0x0b001000 0x1000>, <0x0b004000 0x2000>; - interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - apcs: mailbox@b011000 { - compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&a53pll>, <&gcc GPLL0_VOTE>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; - - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0x0b016000 0x40>; - #clock-cells = <0>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - timer@b020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b020000 0x1000>; - clock-frequency = <19200000>; - - frame@b021000 { - frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b021000 0x1000>, - <0x0b022000 0x1000>; - }; - - frame@b023000 { - frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b023000 0x1000>; - status = "disabled"; - }; - - frame@b024000 { - frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b024000 0x1000>; - status = "disabled"; - }; - - frame@b025000 { - frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b025000 0x1000>; - status = "disabled"; - }; - - frame@b026000 { - frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b026000 0x1000>; - status = "disabled"; - }; - - frame@b027000 { - frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b027000 0x1000>; - status = "disabled"; - }; - - frame@b028000 { - frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b028000 0x1000>; - status = "disabled"; - }; - }; - - cpu0_acc: power-manager@b088000 { - compatible = "qcom,msm8916-acc"; - reg = <0x0b088000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu0_saw: power-manager@b089000 { - compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; - reg = <0x0b089000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu1_acc: power-manager@b098000 { - compatible = "qcom,msm8916-acc"; - reg = <0x0b098000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu1_saw: power-manager@b099000 { - compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; - reg = <0x0b099000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu2_acc: power-manager@b0a8000 { - compatible = "qcom,msm8916-acc"; - reg = <0x0b0a8000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu2_saw: power-manager@b0a9000 { - compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; - reg = <0x0b0a9000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu3_acc: power-manager@b0b8000 { - compatible = "qcom,msm8916-acc"; - reg = <0x0b0b8000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - - cpu3_saw: power-manager@b0b9000 { - compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; - reg = <0x0b0b9000 0x1000>; - status = "reserved"; /* Controlled by PSCI firmware */ - }; - }; - - thermal-zones { - cpu0-1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu0_1_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_1_crit: cpu-crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - cpu2_3_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_3_crit: cpu-crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - gpu_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - cam_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; - - trips { - modem_alert0: trip-point0 { - temperature = <85000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/dts/msm8996.dtsi b/arch/arm/dts/msm8996.dtsi deleted file mode 100644 index 6ba9da9e6a8..00000000000 --- a/arch/arm/dts/msm8996.dtsi +++ /dev/null @@ -1,3884 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/qcom,gcc-msm8996.h> -#include <dt-bindings/clock/qcom,mmcc-msm8996.h> -#include <dt-bindings/clock/qcom,rpmcc.h> -#include <dt-bindings/interconnect/qcom,msm8996.h> -#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> -#include <dt-bindings/firmware/qcom,scm.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/power/qcom-rpmpd.h> -#include <dt-bindings/soc/qcom,apr.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - clocks = <&kryocc 0>; - interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - clocks = <&kryocc 0>; - interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - clocks = <&kryocc 1>; - interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - clocks = <&kryocc 1>; - interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU2>; - }; - - core1 { - cpu = <&CPU3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x00000004>; - entry-latency-us = <130>; - exit-latency-us = <80>; - min-residency-us = <300>; - }; - }; - }; - - cluster0_opp: opp-table-cluster0 { - compatible = "operating-points-v2-kryo-cpu"; - nvmem-cells = <&speedbin_efuse>; - opp-shared; - - /* Nominal fmax for now */ - opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-422400000 { - opp-hz = /bits/ 64 <422400000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-556800000 { - opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <384000>; - }; - opp-729600000 { - opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <460800>; - }; - opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <537600>; - }; - opp-960000000 { - opp-hz = /bits/ 64 <960000000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <672000>; - }; - opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <672000>; - }; - opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <825600>; - }; - opp-1190400000 { - opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <825600>; - }; - opp-1228800000 { - opp-hz = /bits/ 64 <1228800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <902400>; - }; - opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0xd>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1056000>; - }; - opp-1363200000 { - opp-hz = /bits/ 64 <1363200000>; - opp-supported-hw = <0x2>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1132800>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0xd>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1132800>; - }; - opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x9>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1190400>; - }; - opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-supported-hw = <0x04>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1305600>; - }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; - opp-supported-hw = <0x9>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1382400>; - }; - }; - - cluster1_opp: opp-table-cluster1 { - compatible = "operating-points-v2-kryo-cpu"; - nvmem-cells = <&speedbin_efuse>; - opp-shared; - - /* Nominal fmax for now */ - opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-556800000 { - opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-729600000 { - opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <307200>; - }; - opp-806400000 { - opp-hz = /bits/ 64 <806400000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <384000>; - }; - opp-883200000 { - opp-hz = /bits/ 64 <883200000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <460800>; - }; - opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <537600>; - }; - opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <595200>; - }; - opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <672000>; - }; - opp-1190400000 { - opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <672000>; - }; - opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <748800>; - }; - opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <825600>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <902400>; - }; - opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <979200>; - }; - opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1056000>; - }; - opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1190400>; - }; - opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1228800>; - }; - opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1305600>; - }; - opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-supported-hw = <0xe>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1305600>; - }; - opp-1824000000 { - opp-hz = /bits/ 64 <1824000000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1382400>; - }; - opp-1900800000 { - opp-hz = /bits/ 64 <1900800000>; - opp-supported-hw = <0x4>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1305600>; - }; - opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1459200>; - }; - opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1593600>; - }; - opp-2073600000 { - opp-hz = /bits/ 64 <2073600000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1593600>; - }; - opp-2150400000 { - opp-hz = /bits/ 64 <2150400000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - opp-peak-kBps = <1593600>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8996", "qcom,scm"; - qcom,dload-mode = <&tcsr_2 0x13000>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - rpm: remoteproc { - compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; - - glink-edge { - compatible = "qcom,glink-rpm"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8996-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp1: opp1 { - opp-level = <1>; - }; - - rpmpd_opp2: opp2 { - opp-level = <2>; - }; - - rpmpd_opp3: opp3 { - opp-level = <3>; - }; - - rpmpd_opp4: opp4 { - opp-level = <4>; - }; - - rpmpd_opp5: opp5 { - opp-level = <5>; - }; - - rpmpd_opp6: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85800000 { - reg = <0x0 0x85800000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x200000>; - no-map; - }; - - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x2600000>; - no-map; - }; - - rmtfs_mem: rmtfs { - compatible = "qcom,rmtfs-mem"; - - size = <0x0 0x200000>; - alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; - }; - - mpss_mem: mpss@88800000 { - reg = <0x0 0x88800000 0x0 0x6200000>; - no-map; - }; - - adsp_mem: adsp@8ea00000 { - reg = <0x0 0x8ea00000 0x0 0x1b00000>; - no-map; - }; - - slpi_mem: slpi@90500000 { - reg = <0x0 0x90500000 0x0 0xa00000>; - no-map; - }; - - gpu_mem: gpu@90f00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x90f00000 0x0 0x100000>; - no-map; - }; - - venus_mem: venus@91000000 { - reg = <0x0 0x91000000 0x0 0x500000>; - no-map; - }; - - mba_mem: mba@91500000 { - reg = <0x0 0x91500000 0x0 0x200000>; - no-map; - }; - - mdata_mem: mpss-metadata { - alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; - size = <0x0 0x4000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apcs_glb 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apcs_glb 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - mpss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - mpss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apcs_glb 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - pcie_phy: phy-wrapper@34000 { - compatible = "qcom,msm8996-qmp-pcie-phy"; - reg = <0x00034000 0x488>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00034000 0x4000>; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_PCIE_PHY_BCR>, - <&gcc GCC_PCIE_PHY_COM_BCR>, - <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; - reset-names = "phy", "common", "cfg"; - - status = "disabled"; - - pciephy_0: phy@1000 { - reg = <0x1000 0x130>, - <0x1200 0x200>, - <0x1400 0x1dc>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "lane0"; - - #clock-cells = <0>; - clock-output-names = "pcie_0_pipe_clk_src"; - - #phy-cells = <0>; - }; - - pciephy_1: phy@2000 { - reg = <0x2000 0x130>, - <0x2200 0x200>, - <0x2400 0x1dc>; - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe1"; - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "lane1"; - - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk_src"; - - #phy-cells = <0>; - }; - - pciephy_2: phy@3000 { - reg = <0x3000 0x130>, - <0x3200 0x200>, - <0x3400 0x1dc>; - - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; - clock-names = "pipe2"; - resets = <&gcc GCC_PCIE_2_PHY_BCR>; - reset-names = "lane2"; - - #clock-cells = <0>; - clock-output-names = "pcie_2_pipe_clk_src"; - - #phy-cells = <0>; - }; - }; - - rpm_msg_ram: sram@68000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00068000 0x6000>; - }; - - qfprom@74000 { - compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; - reg = <0x00074000 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx_trim@24e { - reg = <0x24e 0x2>; - bits = <5 4>; - }; - - qusb2s_hstx_trim: hstx_trim@24f { - reg = <0x24f 0x1>; - bits = <1 4>; - }; - - speedbin_efuse: speedbin@133 { - reg = <0x133 0x1>; - bits = <5 3>; - }; - }; - - rng: rng@83000 { - compatible = "qcom,prng-ee"; - reg = <0x00083000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - gcc: clock-controller@300000 { - compatible = "qcom,gcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00300000 0x90000>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&rpmcc RPM_SMD_LN_BB_CLK>, - <&sleep_clk>, - <&pciephy_0>, - <&pciephy_1>, - <&pciephy_2>, - <&ssusb_phy_0>, - <&ufsphy_lane 0>, - <&ufsphy_lane 1>, - <&ufsphy_lane 2>; - clock-names = "cxo", - "cxo2", - "sleep_clk", - "pcie_0_pipe_clk_src", - "pcie_1_pipe_clk_src", - "pcie_2_pipe_clk_src", - "usb3_phy_pipe_clk_src", - "ufs_rx_symbol_0_clk_src", - "ufs_rx_symbol_1_clk_src", - "ufs_tx_symbol_0_clk_src"; - }; - - bimc: interconnect@408000 { - compatible = "qcom,msm8996-bimc"; - reg = <0x00408000 0x5a000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - tsens0: thermal-sensor@4a9000 { - compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - #qcom,sensors = <13>; - interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@4ad000 { - compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; - reg = <0x004ad000 0x1000>, /* TM */ - <0x004ac000 0x1000>; /* SROT */ - #qcom,sensors = <8>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - cryptobam: dma-controller@644000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x00644000 0x24000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_CE1_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - }; - - crypto: crypto@67a000 { - compatible = "qcom,crypto-v5.4"; - reg = <0x0067a000 0x6000>; - clocks = <&gcc GCC_CE1_AHB_CLK>, - <&gcc GCC_CE1_AXI_CLK>, - <&gcc GCC_CE1_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 6>, <&cryptobam 7>; - dma-names = "rx", "tx"; - }; - - cnoc: interconnect@500000 { - compatible = "qcom,msm8996-cnoc"; - reg = <0x00500000 0x1000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; - }; - - snoc: interconnect@524000 { - compatible = "qcom,msm8996-snoc"; - reg = <0x00524000 0x1c000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - a0noc: interconnect@543000 { - compatible = "qcom,msm8996-a0noc"; - reg = <0x00543000 0x6000>; - #interconnect-cells = <1>; - clock-names = "aggre0_snoc_axi", - "aggre0_cnoc_ahb", - "aggre0_noc_mpu_cfg"; - clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, - <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, - <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; - power-domains = <&gcc AGGRE0_NOC_GDSC>; - }; - - a1noc: interconnect@562000 { - compatible = "qcom,msm8996-a1noc"; - reg = <0x00562000 0x5000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, - <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; - }; - - a2noc: interconnect@583000 { - compatible = "qcom,msm8996-a2noc"; - reg = <0x00583000 0x7000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; - clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, - <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, - <&gcc GCC_AGGRE2_UFS_AXI_CLK>, - <&gcc GCC_UFS_AXI_CLK>; - }; - - mnoc: interconnect@5a4000 { - compatible = "qcom,msm8996-mnoc"; - reg = <0x005a4000 0x1c000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a", "iface"; - clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, - <&rpmcc RPM_SMD_MMAXI_A_CLK>, - <&mmcc AHB_CLK_SRC>; - }; - - pnoc: interconnect@5c0000 { - compatible = "qcom,msm8996-pnoc"; - reg = <0x005c0000 0x3000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, - <&rpmcc RPM_SMD_PCNOC_A_CLK>; - }; - - tcsr_mutex: hwlock@740000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x00740000 0x20000>; - #hwlock-cells = <1>; - }; - - tcsr_1: syscon@760000 { - compatible = "qcom,tcsr-msm8996", "syscon"; - reg = <0x00760000 0x20000>; - }; - - tcsr_2: syscon@7a0000 { - compatible = "qcom,tcsr-msm8996", "syscon"; - reg = <0x007a0000 0x18000>; - }; - - mmcc: clock-controller@8c0000 { - compatible = "qcom,mmcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x008c0000 0x40000>; - clocks = <&xo_board>, - <&gcc GPLL0>, - <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_hdmi_phy>; - clock-names = "xo", - "gpll0", - "gcc_mmss_noc_cfg_ahb_clk", - "dsi0pll", - "dsi0pllbyte", - "dsi1pll", - "dsi1pllbyte", - "hdmipll"; - assigned-clocks = <&mmcc MMPLL9_PLL>, - <&mmcc MMPLL1_PLL>, - <&mmcc MMPLL3_PLL>, - <&mmcc MMPLL4_PLL>, - <&mmcc MMPLL5_PLL>; - assigned-clock-rates = <624000000>, - <810000000>, - <980000000>, - <960000000>, - <825000000>; - }; - - mdss: display-subsystem@900000 { - compatible = "qcom,mdss"; - - reg = <0x00900000 0x1000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>; - reg-names = "mdss_phys", - "vbif_phys", - "vbif_nrt_phys"; - - power-domains = <&mmcc MDSS_GDSC>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-controller; - #interrupt-cells = <1>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>; - clock-names = "iface", "core"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - status = "disabled"; - - mdp: display-controller@901000 { - compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; - reg = <0x00901000 0x90000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "iommu", - "vsync"; - - iommus = <&mdp_smmu 0>; - - assigned-clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; - - interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, - <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, - <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; - interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf3_out: endpoint { - remote-endpoint = <&mdss_hdmi_in>; - }; - }; - - port@1 { - reg = <1>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; - }; - }; - - port@2 { - reg = <2>; - mdp5_intf2_out: endpoint { - remote-endpoint = <&mdss_dsi1_in>; - }; - }; - }; - }; - - mdss_dsi0: dsi@994000 { - compatible = "qcom,msm8996-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0x00994000 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_PCLK0_CLK>, - <&mmcc MDSS_ESC0_CLK>; - clock-names = "mdp_core", - "byte", - "iface", - "bus", - "core_mmss", - "pixel", - "core"; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; - - phys = <&mdss_dsi0_phy>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi0_out: endpoint { - }; - }; - }; - }; - - mdss_dsi0_phy: phy@994400 { - compatible = "qcom,dsi-phy-14nm"; - reg = <0x00994400 0x100>, - <0x00994500 0x300>, - <0x00994800 0x188>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "ref"; - status = "disabled"; - }; - - mdss_dsi1: dsi@996000 { - compatible = "qcom,msm8996-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0x00996000 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <5>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_BYTE1_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_PCLK1_CLK>, - <&mmcc MDSS_ESC1_CLK>; - clock-names = "mdp_core", - "byte", - "iface", - "bus", - "core_mmss", - "pixel", - "core"; - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; - - phys = <&mdss_dsi1_phy>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi1_in: endpoint { - remote-endpoint = <&mdp5_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi1_out: endpoint { - }; - }; - }; - }; - - mdss_dsi1_phy: phy@996400 { - compatible = "qcom,dsi-phy-14nm"; - reg = <0x00996400 0x100>, - <0x00996500 0x300>, - <0x00996800 0x188>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "ref"; - status = "disabled"; - }; - - mdss_hdmi: hdmi-tx@9a0000 { - compatible = "qcom,hdmi-tx-8996"; - reg = <0x009a0000 0x50c>, - <0x00070000 0x6158>, - <0x009e0000 0xfff>; - reg-names = "core_physical", - "qfprom_physical", - "hdcp_physical"; - - interrupt-parent = <&mdss>; - interrupts = <8>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_HDMI_CLK>, - <&mmcc MDSS_HDMI_AHB_CLK>, - <&mmcc MDSS_EXTPCLK_CLK>; - clock-names = - "mdp_core", - "iface", - "core", - "alt_iface", - "extp"; - - phys = <&mdss_hdmi_phy>; - #sound-dai-cells = <1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_hdmi_in: endpoint { - remote-endpoint = <&mdp5_intf3_out>; - }; - }; - }; - }; - - mdss_hdmi_phy: phy@9a0600 { - #phy-cells = <0>; - compatible = "qcom,hdmi-phy-8996"; - reg = <0x009a0600 0x1c4>, - <0x009a0a00 0x124>, - <0x009a0c00 0x124>, - <0x009a0e00 0x124>, - <0x009a1000 0x124>, - <0x009a1200 0x0c8>; - reg-names = "hdmi_pll", - "hdmi_tx_l0", - "hdmi_tx_l1", - "hdmi_tx_l2", - "hdmi_tx_l3", - "hdmi_phy"; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&gcc GCC_HDMI_CLKREF_CLK>, - <&xo_board>; - clock-names = "iface", - "ref", - "xo"; - - #clock-cells = <0>; - - status = "disabled"; - }; - }; - - gpu: gpu@b00000 { - compatible = "qcom,adreno-530.2", "qcom,adreno"; - - reg = <0x00b00000 0x3f000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc GPU_GX_GFX3D_CLK>, - <&mmcc GPU_AHB_CLK>, - <&mmcc GPU_GX_RBBMTIMER_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - - clock-names = "core", - "iface", - "rbbmtimer", - "mem", - "mem_iface"; - - interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; - interconnect-names = "gfx-mem"; - - power-domains = <&mmcc GPU_GX_GDSC>; - iommus = <&adreno_smmu 0>; - - nvmem-cells = <&speedbin_efuse>; - nvmem-cell-names = "speed_bin"; - - operating-points-v2 = <&gpu_opp_table>; - - status = "disabled"; - - #cooling-cells = <2>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* - * 624Mhz is only available on speed bins 0 and 3. - * 560Mhz is only available on speed bins 0, 2 and 3. - * All the rest are available on all bins of the hardware. - */ - opp-624000000 { - opp-hz = /bits/ 64 <624000000>; - opp-supported-hw = <0x09>; - }; - opp-560000000 { - opp-hz = /bits/ 64 <560000000>; - opp-supported-hw = <0x0d>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-supported-hw = <0xff>; - }; - opp-401800000 { - opp-hz = /bits/ 64 <401800000>; - opp-supported-hw = <0xff>; - }; - opp-315000000 { - opp-hz = /bits/ 64 <315000000>; - opp-supported-hw = <0xff>; - }; - opp-214000000 { - opp-hz = /bits/ 64 <214000000>; - opp-supported-hw = <0xff>; - }; - opp-133000000 { - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0xff>; - }; - }; - - zap-shader { - memory-region = <&gpu_mem>; - }; - }; - - tlmm: pinctrl@1010000 { - compatible = "qcom,msm8996-pinctrl"; - reg = <0x01010000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 150>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_spi1_default: blsp1-spi1-default-state { - spi-pins { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio2"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp1_spi1_sleep: blsp1-spi1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart8"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { - pins = "gpio4", "gpio5"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_i2c2_default: blsp2-i2c2-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c8"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c6_default: blsp1-i2c6-state { - pins = "gpio27", "gpio28"; - function = "blsp_i2c6"; - drive-strength = <16>; - bias-disable; - }; - - blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { - pins = "gpio27", "gpio28"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - cci0_default: cci0-default-state { - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - drive-strength = <16>; - bias-disable; - }; - - camera0_state_on: - camera_rear_default: camera-rear-default-state { - camera0_mclk: mclk0-pins { - pins = "gpio13"; - function = "cam_mclk"; - drive-strength = <16>; - bias-disable; - }; - - camera0_rst: rst-pins { - pins = "gpio25"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - camera0_pwdn: pwdn-pins { - pins = "gpio26"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - }; - - cci1_default: cci1-default-state { - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - drive-strength = <16>; - bias-disable; - }; - - camera1_state_on: - camera_board_default: camera-board-default-state { - mclk1-pins { - pins = "gpio14"; - function = "cam_mclk"; - drive-strength = <16>; - bias-disable; - }; - - pwdn-pins { - pins = "gpio98"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - rst-pins { - pins = "gpio104"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera2_state_on: - camera_front_default: camera-front-default-state { - camera2_mclk: mclk2-pins { - pins = "gpio15"; - function = "cam_mclk"; - drive-strength = <16>; - bias-disable; - }; - - camera2_rst: rst-pins { - pins = "gpio23"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - pwdn-pins { - pins = "gpio133"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - }; - - pcie0_state_on: pcie0-state-on-state { - perst-pins { - pins = "gpio35"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio36"; - function = "pci_e0"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio37"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_state_off: pcie0-state-off-state { - perst-pins { - pins = "gpio35"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio36"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-pins { - pins = "gpio37"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp1_uart2_default: blsp1-uart2-default-state { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "blsp_uart2"; - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart2_sleep: blsp1-uart2-sleep-state { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c3_default: blsp1-i2c3-default-state { - pins = "gpio47", "gpio48"; - function = "blsp_i2c3"; - drive-strength = <16>; - bias-disable; - }; - - blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { - pins = "gpio47", "gpio48"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - function = "blsp_uart9"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - function = "blsp_uart9"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_i2c3_default: blsp2-i2c3-state-state { - pins = "gpio51", "gpio52"; - function = "blsp_i2c9"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { - pins = "gpio51", "gpio52"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_i2c1_default: blsp2-i2c1-state { - pins = "gpio55", "gpio56"; - function = "blsp_i2c7"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { - pins = "gpio55", "gpio56"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_i2c5_default: blsp2-i2c5-state { - pins = "gpio60", "gpio61"; - function = "blsp_i2c11"; - drive-strength = <2>; - bias-disable; - }; - - /* Sleep state for BLSP2_I2C5 is missing.. */ - - cdc_reset_active: cdc-reset-active-state { - pins = "gpio64"; - function = "gpio"; - drive-strength = <16>; - bias-pull-down; - output-high; - }; - - cdc_reset_sleep: cdc-reset-sleep-state { - pins = "gpio64"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; - - blsp2_spi6_default: blsp2-spi6-default-state { - spi-pins { - pins = "gpio85", "gpio86", "gpio88"; - function = "blsp_spi12"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio87"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp2_spi6_sleep: blsp2-spi6-sleep-state { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_i2c6_default: blsp2-i2c6-state { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { - pins = "gpio87", "gpio88"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - pcie1_state_on: pcie1-on-state { - perst-pins { - pins = "gpio130"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio131"; - function = "pci_e1"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio132"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_state_off: pcie1-off-state { - /* Perst is missing? */ - clkreq-pins { - pins = "gpio131"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-pins { - pins = "gpio132"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_state_on: pcie2-on-state { - perst-pins { - pins = "gpio114"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio115"; - function = "pci_e2"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio116"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_state_off: pcie2-off-state { - /* Perst is missing? */ - clkreq-pins { - pins = "gpio115"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-pins { - pins = "gpio116"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; - - sdc1_state_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - rclk-pins { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_state_off: sdc1-off-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - rclk-pins { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc2_state_on: sdc2-on-state { - clk-pins { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_state_off: sdc2-off-state { - clk-pins { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - }; - - sram@290000 { - compatible = "qcom,rpm-stats"; - reg = <0x00290000 0x10000>; - }; - - spmi_bus: spmi@400f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0400f000 0x1000>, - <0x04400000 0x800000>, - <0x04c00000 0x800000>, - <0x05800000 0x200000>, - <0x0400a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - bus@0 { - power-domains = <&gcc AGGRE0_NOC_GDSC>; - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xffffffff>; - - pcie0: pcie@600000 { - compatible = "qcom,pcie-msm8996"; - status = "disabled"; - power-domains = <&gcc PCIE0_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - reg = <0x00600000 0x2000>, - <0x0c000000 0xf1d>, - <0x0c000f20 0xa8>, - <0x0c100000 0x100000>; - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_0>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, - <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; - - device_type = "pci"; - - interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie0_state_on>; - pinctrl-1 = <&pcie0_state_off>; - - linux,pci-domain = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - - pcie1: pcie@608000 { - compatible = "qcom,pcie-msm8996"; - power-domains = <&gcc PCIE1_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - status = "disabled"; - - reg = <0x00608000 0x2000>, - <0x0d000000 0xf1d>, - <0x0d000f20 0xa8>, - <0x0d100000 0x100000>; - - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_1>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, - <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; - - device_type = "pci"; - - interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie1_state_on>; - pinctrl-1 = <&pcie1_state_off>; - - linux,pci-domain = <1>; - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - - pcie2: pcie@610000 { - compatible = "qcom,pcie-msm8996"; - power-domains = <&gcc PCIE2_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - status = "disabled"; - reg = <0x00610000 0x2000>, - <0x0e000000 0xf1d>, - <0x0e000f20 0xa8>, - <0x0e100000 0x100000>; - - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_2>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, - <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; - - device_type = "pci"; - - interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie2_state_on>; - pinctrl-1 = <&pcie2_state_off>; - - linux,pci-domain = <2>; - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, - <&gcc GCC_PCIE_2_AUX_CLK>, - <&gcc GCC_PCIE_2_CFG_AHB_CLK>, - <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_2_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - }; - - ufshc: ufshc@624000 { - compatible = "qcom,msm8996-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0x00624000 0x2500>; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - - phys = <&ufsphy_lane>; - phy-names = "ufsphy"; - - power-domains = <&gcc UFS_GDSC>; - - clock-names = - "core_clk_src", - "core_clk", - "bus_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro_src", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; - clocks = - <&gcc UFS_AXI_CLK_SRC>, - <&gcc GCC_UFS_AXI_CLK>, - <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, - <&gcc GCC_AGGRE2_UFS_AXI_CLK>, - <&gcc GCC_UFS_AHB_CLK>, - <&gcc UFS_ICE_CORE_CLK_SRC>, - <&gcc GCC_UFS_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_ICE_CORE_CLK>, - <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; - freq-table-hz = - <100000000 200000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <150000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, - <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - - lanes-per-direction = <1>; - #reset-cells = <1>; - status = "disabled"; - }; - - ufsphy: phy@627000 { - compatible = "qcom,msm8996-qmp-ufs-phy"; - reg = <0x00627000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_UFS_CLKREF_CLK>; - clock-names = "ref"; - - resets = <&ufshc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufsphy_lane: phy@627400 { - reg = <0x627400 0x12c>, - <0x627600 0x200>, - <0x627c00 0x1b4>; - #clock-cells = <1>; - #phy-cells = <0>; - }; - }; - - camss: camss@a34000 { - compatible = "qcom,msm8996-camss"; - reg = <0x00a34000 0x1000>, - <0x00a00030 0x4>, - <0x00a35000 0x1000>, - <0x00a00038 0x4>, - <0x00a36000 0x1000>, - <0x00a00040 0x4>, - <0x00a30000 0x100>, - <0x00a30400 0x100>, - <0x00a30800 0x100>, - <0x00a30c00 0x100>, - <0x00a31000 0x500>, - <0x00a00020 0x10>, - <0x00a10000 0x1000>, - <0x00a14000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csiphy2", - "csiphy2_clk_mux", - "csid0", - "csid1", - "csid2", - "csid3", - "ispif", - "csi_clk_mux", - "vfe0", - "vfe1"; - interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "csiphy0", - "csiphy1", - "csiphy2", - "csid0", - "csid1", - "csid2", - "csid3", - "ispif", - "vfe0", - "vfe1"; - power-domains = <&mmcc VFE0_GDSC>, - <&mmcc VFE1_GDSC>; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_ISPIF_AHB_CLK>, - <&mmcc CAMSS_CSI0PHYTIMER_CLK>, - <&mmcc CAMSS_CSI1PHYTIMER_CLK>, - <&mmcc CAMSS_CSI2PHYTIMER_CLK>, - <&mmcc CAMSS_CSI0_AHB_CLK>, - <&mmcc CAMSS_CSI0_CLK>, - <&mmcc CAMSS_CSI0PHY_CLK>, - <&mmcc CAMSS_CSI0PIX_CLK>, - <&mmcc CAMSS_CSI0RDI_CLK>, - <&mmcc CAMSS_CSI1_AHB_CLK>, - <&mmcc CAMSS_CSI1_CLK>, - <&mmcc CAMSS_CSI1PHY_CLK>, - <&mmcc CAMSS_CSI1PIX_CLK>, - <&mmcc CAMSS_CSI1RDI_CLK>, - <&mmcc CAMSS_CSI2_AHB_CLK>, - <&mmcc CAMSS_CSI2_CLK>, - <&mmcc CAMSS_CSI2PHY_CLK>, - <&mmcc CAMSS_CSI2PIX_CLK>, - <&mmcc CAMSS_CSI2RDI_CLK>, - <&mmcc CAMSS_CSI3_AHB_CLK>, - <&mmcc CAMSS_CSI3_CLK>, - <&mmcc CAMSS_CSI3PHY_CLK>, - <&mmcc CAMSS_CSI3PIX_CLK>, - <&mmcc CAMSS_CSI3RDI_CLK>, - <&mmcc CAMSS_AHB_CLK>, - <&mmcc CAMSS_VFE0_CLK>, - <&mmcc CAMSS_CSI_VFE0_CLK>, - <&mmcc CAMSS_VFE0_AHB_CLK>, - <&mmcc CAMSS_VFE0_STREAM_CLK>, - <&mmcc CAMSS_VFE1_CLK>, - <&mmcc CAMSS_CSI_VFE1_CLK>, - <&mmcc CAMSS_VFE1_AHB_CLK>, - <&mmcc CAMSS_VFE1_STREAM_CLK>, - <&mmcc CAMSS_VFE_AHB_CLK>, - <&mmcc CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csiphy2_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "csi2_ahb", - "csi2", - "csi2_phy", - "csi2_pix", - "csi2_rdi", - "csi3_ahb", - "csi3", - "csi3_phy", - "csi3_pix", - "csi3_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe0_ahb", - "vfe0_stream", - "vfe1", - "csi_vfe1", - "vfe1_ahb", - "vfe1_stream", - "vfe_ahb", - "vfe_axi"; - iommus = <&vfe_smmu 0>, - <&vfe_smmu 1>, - <&vfe_smmu 2>, - <&vfe_smmu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci: cci@a0c000 { - compatible = "qcom,msm8996-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa0c000 0x1000>; - interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; - power-domains = <&mmcc CAMSS_GDSC>; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CLK>, - <&mmcc CAMSS_AHB_CLK>; - clock-names = "camss_top_ahb", - "cci_ahb", - "cci", - "camss_ahb"; - assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CLK>; - assigned-clock-rates = <80000000>, <37500000>; - pinctrl-names = "default"; - pinctrl-0 = <&cci0_default &cci1_default>; - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - adreno_smmu: iommu@b40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; - reg = <0x00b40000 0x10000>; - - #global-interrupts = <1>; - interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - - clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, - <&mmcc GPU_AHB_CLK>; - clock-names = "bus", "iface"; - - power-domains = <&mmcc GPU_GDSC>; - }; - - venus: video-codec@c00000 { - compatible = "qcom,msm8996-venus"; - reg = <0x00c00000 0xff000>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&mmcc VENUS_GDSC>; - clocks = <&mmcc VIDEO_CORE_CLK>, - <&mmcc VIDEO_AHB_CLK>, - <&mmcc VIDEO_AXI_CLK>, - <&mmcc VIDEO_MAXI_CLK>; - clock-names = "core", "iface", "bus", "mbus"; - interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, - <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; - interconnect-names = "video-mem", "cpu-cfg"; - iommus = <&venus_smmu 0x00>, - <&venus_smmu 0x01>, - <&venus_smmu 0x0a>, - <&venus_smmu 0x07>, - <&venus_smmu 0x0e>, - <&venus_smmu 0x0f>, - <&venus_smmu 0x08>, - <&venus_smmu 0x09>, - <&venus_smmu 0x0b>, - <&venus_smmu 0x0c>, - <&venus_smmu 0x0d>, - <&venus_smmu 0x10>, - <&venus_smmu 0x11>, - <&venus_smmu 0x21>, - <&venus_smmu 0x28>, - <&venus_smmu 0x29>, - <&venus_smmu 0x2b>, - <&venus_smmu 0x2c>, - <&venus_smmu 0x2d>, - <&venus_smmu 0x31>; - memory-region = <&venus_mem>; - status = "disabled"; - - video-decoder { - compatible = "venus-decoder"; - clocks = <&mmcc VIDEO_SUBCORE0_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE0_GDSC>; - }; - - video-encoder { - compatible = "venus-encoder"; - clocks = <&mmcc VIDEO_SUBCORE1_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE1_GDSC>; - }; - }; - - mdp_smmu: iommu@d00000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00d00000 0x10000>; - - #global-interrupts = <1>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - clocks = <&mmcc SMMU_MDP_AXI_CLK>, - <&mmcc SMMU_MDP_AHB_CLK>; - clock-names = "bus", "iface"; - - power-domains = <&mmcc MDSS_GDSC>; - }; - - venus_smmu: iommu@d40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00d40000 0x20000>; - #global-interrupts = <1>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; - clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, - <&mmcc SMMU_VIDEO_AHB_CLK>; - clock-names = "bus", "iface"; - #iommu-cells = <1>; - status = "okay"; - }; - - vfe_smmu: iommu@da0000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00da0000 0x10000>; - - #global-interrupts = <1>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; - clocks = <&mmcc SMMU_VFE_AXI_CLK>, - <&mmcc SMMU_VFE_AHB_CLK>; - clock-names = "bus", "iface"; - #iommu-cells = <1>; - }; - - lpass_q6_smmu: iommu@1600000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x01600000 0x20000>; - #iommu-cells = <1>; - power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; - - #global-interrupts = <1>; - interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, - <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; - clock-names = "bus", "iface"; - }; - - slpi_pil: remoteproc@1c00000 { - compatible = "qcom,msm8996-slpi-pil"; - reg = <0x01c00000 0x4000>; - - interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - clocks = <&xo_board>, - <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; - clock-names = "xo", "aggre2"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - power-domains = <&rpmpd MSM8996_VDDSSCX>; - power-domain-names = "ssc_cx"; - - status = "disabled"; - - smd-edge { - interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; - - label = "dsps"; - mboxes = <&apcs_glb 25>; - qcom,smd-edge = <3>; - qcom,remote-pid = <3>; - }; - }; - - mss_pil: remoteproc@2080000 { - compatible = "qcom,msm8996-mss-pil"; - reg = <0x2080000 0x100>, - <0x2180000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, - <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack", - "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>, - <&gcc GCC_MSS_GPLL0_DIV_CLK>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, - <&rpmcc RPM_SMD_PCNOC_CLK>, - <&rpmcc RPM_SMD_QDSS_CLK>; - clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "pnoc", "qdss"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - power-domains = <&rpmpd MSM8996_VDDCX>, - <&rpmpd MSM8996_VDDMX>; - power-domain-names = "cx", "mx"; - - qcom,smem-states = <&mpss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; - - status = "disabled"; - - mba { - memory-region = <&mba_mem>; - }; - - mpss { - memory-region = <&mpss_mem>; - }; - - metadata { - memory-region = <&mdata_mem>; - }; - - smd-edge { - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; - - label = "mpss"; - mboxes = <&apcs_glb 12>; - qcom,smd-edge = <0>; - qcom,remote-pid = <1>; - }; - }; - - stm@3002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x3002000 0x1000>, - <0x8280000 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = - <&funnel0_in>; - }; - }; - }; - }; - - tpiu@3020000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x3020000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator_out1>; - }; - }; - }; - }; - - funnel@3021000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3021000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in: endpoint { - remote-endpoint = - <&stm_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - }; - - funnel@3022000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3022000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - funnel1_in: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = - <&merge_funnel_in1>; - }; - }; - }; - }; - - funnel@3023000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3023000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = - <&merge_funnel_in2>; - }; - }; - }; - }; - - funnel@3025000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3025000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = - <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = - <&funnel2_out>; - }; - }; - }; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - }; - - replicator@3026000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x3026000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = - <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = - <&tpiu_in>; - }; - }; - }; - }; - - etf@3027000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x3027000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - etr@3028000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x3028000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out0>; - }; - }; - }; - }; - - debug@3810000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3810000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - }; - - etm@3840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3840000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel0_in0>; - }; - }; - }; - }; - - debug@3910000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3910000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - }; - - etm@3940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3940000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel0_in1>; - }; - }; - }; - }; - - funnel@39b0000 { /* APSS Funnel 0 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x39b0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel0_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel0_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - }; - - out-ports { - port { - apss_funnel0_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in0>; - }; - }; - }; - }; - - debug@3a10000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3a10000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - }; - - etm@3a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3a40000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel1_in0>; - }; - }; - }; - }; - - debug@3b10000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3b10000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - }; - - etm@3b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3b40000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel1_in1>; - }; - }; - }; - }; - - funnel@3bb0000 { /* APSS Funnel 1 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3bb0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel1_in0: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel1_in1: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - apss_funnel1_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in1>; - }; - }; - }; - }; - - funnel@3bc0000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3bc0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_merge_funnel_in0: endpoint { - remote-endpoint = - <&apss_funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_merge_funnel_in1: endpoint { - remote-endpoint = - <&apss_funnel1_out>; - }; - }; - }; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel1_in>; - }; - }; - }; - }; - - kryocc: clock-controller@6400000 { - compatible = "qcom,msm8996-apcc"; - reg = <0x06400000 0x90000>; - - clock-names = "xo", "sys_apcs_aux"; - clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; - - #clock-cells = <1>; - }; - - usb3: usb@6af8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0x06af8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; - - clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_AGGRE2_USB3_AXI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <120000000>; - - interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, - <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; - interconnect-names = "usb-ddr", "apps-usb"; - - power-domains = <&gcc USB30_GDSC>; - status = "disabled"; - - usb3_dwc3: usb@6a00000 { - compatible = "snps,dwc3"; - reg = <0x06a00000 0xcc00>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hsusb_phy1>, <&ssusb_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - snps,hird-threshold = /bits/ 8 <0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,is-utmi-l1-suspend; - tx-fifo-resize; - }; - }; - - usb3phy: phy@7410000 { - compatible = "qcom,msm8996-qmp-usb3-phy"; - reg = <0x07410000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy", "common"; - status = "disabled"; - - ssusb_phy_0: phy@7410200 { - reg = <0x07410200 0x200>, - <0x07410400 0x130>, - <0x07410600 0x1a8>; - #phy-cells = <0>; - - #clock-cells = <0>; - clock-output-names = "usb3_phy_pipe_clk_src"; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - }; - }; - - hsusb_phy1: phy@7411000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x07411000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - nvmem-cells = <&qusb2p_hstx_trim>; - status = "disabled"; - }; - - hsusb_phy2: phy@7412000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x07412000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX2_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - nvmem-cells = <&qusb2s_hstx_trim>; - status = "disabled"; - }; - - sdhc1: mmc@7464900 { - compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x07464900 0x11c>, <0x07464000 0x800>; - reg-names = "hc", "core"; - - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - resets = <&gcc GCC_SDCC1_BCR>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_state_on>; - pinctrl-1 = <&sdc1_state_off>; - - bus-width = <8>; - non-removable; - status = "disabled"; - }; - - sdhc2: mmc@74a4900 { - compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc", "core"; - - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - resets = <&gcc GCC_SDCC2_BCR>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_state_on>; - pinctrl-1 = <&sdc2_state_off>; - - bus-width = <4>; - status = "disabled"; - }; - - blsp1_dma: dma-controller@7544000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07544000 0x2b000>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - qcom,controlled-remotely; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp1_uart2: serial@7570000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x07570000 0x1000>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - blsp1_spi1: spi@7575000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x07575000 0x600>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi1_default>; - pinctrl-1 = <&blsp1_spi1_sleep>; - dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c3: i2c@7577000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x07577000 0x1000>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c3_default>; - pinctrl-1 = <&blsp1_i2c3_sleep>; - dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c6: i2c@757a000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x757a000 0x1000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c6_default>; - pinctrl-1 = <&blsp1_i2c6_sleep>; - dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_dma: dma-controller@7584000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07584000 0x2b000>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - qcom,controlled-remotely; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp2_uart2: serial@75b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x075b0000 0x1000>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart3: serial@75b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x075b1000 0x1000>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_i2c1: i2c@75b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b5000 0x1000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c1_default>; - pinctrl-1 = <&blsp2_i2c1_sleep>; - dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_i2c2: i2c@75b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b6000 0x1000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c2_default>; - pinctrl-1 = <&blsp2_i2c2_sleep>; - dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_i2c3: i2c@75b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b7000 0x1000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c3_default>; - pinctrl-1 = <&blsp2_i2c3_sleep>; - dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_i2c5: i2c@75b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x75b9000 0x1000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_i2c5_default>; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_i2c6: i2c@75ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x75ba000 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c6_default>; - pinctrl-1 = <&blsp2_i2c6_sleep>; - dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_spi6: spi@75ba000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x075ba000 0x600>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_spi6_default>; - pinctrl-1 = <&blsp2_spi6_sleep>; - dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb2: usb@76f8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0x076f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq"; - - clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, - <&gcc GCC_USB20_MASTER_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_SLEEP_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>; - assigned-clock-rates = <19200000>, <60000000>; - - power-domains = <&gcc USB30_GDSC>; - qcom,select-utmi-as-pipe-clk; - status = "disabled"; - - usb2_dwc3: usb@7600000 { - compatible = "snps,dwc3"; - reg = <0x07600000 0xcc00>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hsusb_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - }; - }; - - slimbam: dma-controller@9184000 { - compatible = "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0x09184000 0x32000>; - num-channels = <31>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - }; - - slim_msm: slim-ngd@91c0000 { - compatible = "qcom,slim-ngd-v1.5.0"; - reg = <0x091c0000 0x2c000>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&slimbam 3>, <&slimbam 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - adsp_pil: remoteproc@9300000 { - compatible = "qcom,msm8996-adsp-pil"; - reg = <0x09300000 0x80000>; - - interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - power-domains = <&rpmpd MSM8996_VDDCX>; - power-domain-names = "cx"; - - status = "disabled"; - - smd-edge { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - - label = "lpass"; - mboxes = <&apcs_glb 8>; - qcom,smd-edge = <1>; - qcom,remote-pid = <2>; - - apr { - power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; - compatible = "qcom,apr-v2"; - qcom,smd-channels = "apr_audio_svc"; - qcom,domain = <APR_DOMAIN_ADSP>; - #address-cells = <1>; - #size-cells = <0>; - - service@3 { - reg = <APR_SVC_ADSP_CORE>; - compatible = "qcom,q6core"; - }; - - q6afe: service@4 { - compatible = "qcom,q6afe"; - reg = <APR_SVC_AFE>; - q6afedai: dais { - compatible = "qcom,q6afe-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - dai@1 { - reg = <1>; - }; - }; - }; - - q6asm: service@7 { - compatible = "qcom,q6asm"; - reg = <APR_SVC_ASM>; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - iommus = <&lpass_q6_smmu 1>; - }; - }; - - q6adm: service@8 { - compatible = "qcom,q6adm"; - reg = <APR_SVC_ADM>; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; - }; - }; - }; - }; - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x09820000 0x1000>; - - #mbox-cells = <1>; - #clock-cells = <0>; - }; - - timer@9840000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x09840000 0x1000>; - clock-frequency = <19200000>; - - frame@9850000 { - frame-number = <0>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x09850000 0x1000>, - <0x09860000 0x1000>; - }; - - frame@9870000 { - frame-number = <1>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x09870000 0x1000>; - status = "disabled"; - }; - - frame@9880000 { - frame-number = <2>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x09880000 0x1000>; - status = "disabled"; - }; - - frame@9890000 { - frame-number = <3>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x09890000 0x1000>; - status = "disabled"; - }; - - frame@98a0000 { - frame-number = <4>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x098a0000 0x1000>; - status = "disabled"; - }; - - frame@98b0000 { - frame-number = <5>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x098b0000 0x1000>; - status = "disabled"; - }; - - frame@98c0000 { - frame-number = <6>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x098c0000 0x1000>; - status = "disabled"; - }; - }; - - saw3: syscon@9a10000 { - compatible = "syscon"; - reg = <0x09a10000 0x1000>; - }; - - cbf: clock-controller@9a11000 { - compatible = "qcom,msm8996-cbf"; - reg = <0x09a11000 0x10000>; - clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; - #clock-cells = <0>; - #interconnect-cells = <1>; - }; - - intc: interrupt-controller@9bc0000 { - compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x09bc0000 0x10000>, - <0x09c00000 0x100000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - sound: sound { - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu-crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu-crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu-crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu-crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu1_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu2_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - m4m-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - m4m_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - l3-or-venus-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - l3_or_venus_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cluster0_l2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster1-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cluster1_l2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - q6_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modemtx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - modemtx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm/dts/pm8916.dtsi b/arch/arm/dts/pm8916.dtsi deleted file mode 100644 index f4de8678774..00000000000 --- a/arch/arm/dts/pm8916.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <dt-bindings/iio/qcom,spmi-vadc.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/spmi/spmi.h> - -&spmi_bus { - - pm8916_0: pmic@0 { - compatible = "qcom,pm8916", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_POWER>; - }; - - pm8916_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - status = "disabled"; - }; - - watchdog { - compatible = "qcom,pm8916-wdt"; - interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; - timeout-sec = <60>; - }; - }; - - pm8916_usbin: usb-detect@1300 { - compatible = "qcom,pm8941-misc"; - reg = <0x1300>; - interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "usb_vbus"; - status = "disabled"; - }; - - pm8916_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8916_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8916_vadc: adc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - channel@0 { - reg = <VADC_USBIN>; - qcom,pre-scaling = <1 10>; - }; - channel@7 { - reg = <VADC_VSYS>; - qcom,pre-scaling = <1 3>; - }; - channel@8 { - reg = <VADC_DIE_TEMP>; - }; - channel@9 { - reg = <VADC_REF_625MV>; - }; - channel@a { - reg = <VADC_REF_1250MV>; - }; - channel@e { - reg = <VADC_GND_REF>; - }; - channel@f { - reg = <VADC_VDD_VADC>; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8916_mpps: mpps@a000 { - compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8916_mpps 0 0 4>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm8916_gpios: gpio@c000 { - compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8916_gpios 0 0 4>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8916_1: pmic@1 { - compatible = "qcom,pm8916", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8916_pwm: pwm { - compatible = "qcom,pm8916-pwm"; - - #pwm-cells = <2>; - - status = "disabled"; - }; - - pm8916_vib: vibrator@c000 { - compatible = "qcom,pm8916-vib"; - reg = <0xc000>; - status = "disabled"; - }; - - pm8916_codec: audio-codec@f000 { - compatible = "qcom,pm8916-wcd-analog-codec"; - reg = <0xf000>; - interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, - <0x1 0xf0 0x1 IRQ_TYPE_NONE>, - <0x1 0xf0 0x2 IRQ_TYPE_NONE>, - <0x1 0xf0 0x3 IRQ_TYPE_NONE>, - <0x1 0xf0 0x4 IRQ_TYPE_NONE>, - <0x1 0xf0 0x5 IRQ_TYPE_NONE>, - <0x1 0xf0 0x6 IRQ_TYPE_NONE>, - <0x1 0xf0 0x7 IRQ_TYPE_NONE>, - <0x1 0xf1 0x0 IRQ_TYPE_NONE>, - <0x1 0xf1 0x1 IRQ_TYPE_NONE>, - <0x1 0xf1 0x2 IRQ_TYPE_NONE>, - <0x1 0xf1 0x3 IRQ_TYPE_NONE>, - <0x1 0xf1 0x4 IRQ_TYPE_NONE>, - <0x1 0xf1 0x5 IRQ_TYPE_NONE>; - interrupt-names = "cdc_spk_cnp_int", - "cdc_spk_clip_int", - "cdc_spk_ocp_int", - "mbhc_ins_rem_det1", - "mbhc_but_rel_det", - "mbhc_but_press_det", - "mbhc_ins_rem_det", - "mbhc_switch_int", - "cdc_ear_ocp_int", - "cdc_hphr_ocp_int", - "cdc_hphl_ocp_det", - "cdc_ear_cnp_int", - "cdc_hphr_cnp_int", - "cdc_hphl_cnp_int"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi deleted file mode 100644 index d44a95caf04..00000000000 --- a/arch/arm/dts/pm8994.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <dt-bindings/iio/qcom,spmi-vadc.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/spmi/spmi.h> - -/ { - thermal-zones { - pm8994-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pm8994_temp>; - - trips { - pm8994_alert0: pm8994-alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - pm8994_crit: pm8994-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - - pmic@0 { - compatible = "qcom,pm8994", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8994_pon: pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_POWER>; - }; - - pm8994_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - status = "disabled"; - }; - }; - - pm8994_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8994_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8994_vadc: adc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - channel@7 { - reg = <VADC_VSYS>; - qcom,pre-scaling = <1 3>; - label = "vph_pwr"; - }; - channel@8 { - reg = <VADC_DIE_TEMP>; - label = "die_temp"; - }; - channel@9 { - reg = <VADC_REF_625MV>; - label = "ref_625mv"; - }; - channel@a { - reg = <VADC_REF_1250MV>; - label = "ref_1250mv"; - }; - channel@e { - reg = <VADC_GND_REF>; - }; - channel@f { - reg = <VADC_VDD_VADC>; - }; - }; - - pm8994_gpios: gpio@c000 { - compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8994_gpios 0 0 22>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm8994_mpps: mpps@a000 { - compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8994_mpps 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@1 { - compatible = "qcom,pm8994", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8994_lpg: pwm { - compatible = "qcom,pm8994-lpg"; - - #address-cells = <1>; - #size-cells = <0>; - #pwm-cells = <2>; - - status = "disabled"; - }; - - pm8994_spmi_regulators: regulators { - compatible = "qcom,pm8994-regulators"; - }; - }; -}; diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi deleted file mode 100644 index 3f82715392c..00000000000 --- a/arch/arm/dts/pm8998.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright 2018 Google LLC. */ - -#include <dt-bindings/iio/qcom,spmi-vadc.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/spmi/spmi.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - thermal-zones { - pm8998-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pm8998_temp>; - - trips { - pm8998_alert0: pm8998-alert0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - pm8998_crit: pm8998-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pm8998_lsid0: pmic@0 { - compatible = "qcom,pm8998", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8998_pon: pon@800 { - compatible = "qcom,pm8998-pon"; - - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pm8998_pwrkey: pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_POWER>; - }; - - pm8998_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - status = "disabled"; - }; - }; - - pm8998_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8998_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8998_coincell: charger@2800 { - compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell"; - reg = <0x2800>; - - status = "disabled"; - }; - - pm8998_adc: adc@3100 { - compatible = "qcom,spmi-adc-rev2"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - channel@6 { - reg = <ADC5_DIE_TEMP>; - label = "die_temp"; - }; - }; - - pm8998_adc_tm: adc-tm@3400 { - compatible = "qcom,spmi-adc-tm-hc"; - reg = <0x3400>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; - #thermal-sensor-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8998_gpios: gpio@c000 { - compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8998_gpios 0 0 26>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - }; - - pm8998_lsid1: pmic@1 { - compatible = "qcom,pm8998", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm/dts/pmi8994.dtsi b/arch/arm/dts/pmi8994.dtsi deleted file mode 100644 index 36d6a1fb553..00000000000 --- a/arch/arm/dts/pmi8994.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/spmi/spmi.h> - -&spmi_bus { - - pmic@2 { - compatible = "qcom,pmi8994", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8994_gpios: gpio@c000 { - compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmi8994_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pmi8994_mpps: mpps@a000 { - compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - gpio-ranges = <&pmi8994_mpps 0 0 4>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@3 { - compatible = "qcom,pmi8994", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8994_lpg: pwm { - compatible = "qcom,pmi8994-lpg"; - - #address-cells = <1>; - #size-cells = <0>; - #pwm-cells = <2>; - - status = "disabled"; - }; - - pmi8994_spmi_regulators: regulators { - compatible = "qcom,pmi8994-regulators"; - }; - - pmi8994_wled: wled@d800 { - compatible = "qcom,pmi8994-wled"; - reg = <0xd800>, <0xd900>; - interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, - <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp", "short"; - qcom,cabc; - qcom,external-pfet; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/pmi8998.dtsi b/arch/arm/dts/pmi8998.dtsi deleted file mode 100644 index cd3f0790fd4..00000000000 --- a/arch/arm/dts/pmi8998.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/spmi/spmi.h> - -&spmi_bus { - pmi8998_lsid0: pmic@2 { - compatible = "qcom,pmi8998", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8998_charger: charger@1000 { - compatible = "qcom,pmi8998-charger"; - reg = <0x1000>; - - interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, - <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "usb-plugin", - "bat-ov", - "wdog-bark", - "usbin-icl-change"; - - io-channels = <&pmi8998_rradc 3>, - <&pmi8998_rradc 4>; - io-channel-names = "usbin_i", "usbin_v"; - - status = "disabled"; - }; - - pmi8998_gpios: gpio@c000 { - compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmi8998_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pmi8998_rradc: adc@4500 { - compatible = "qcom,pmi8998-rradc"; - reg = <0x4500>; - #io-channel-cells = <1>; - }; - }; - - pmi8998_lsid1: pmic@3 { - compatible = "qcom,pmi8998", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - labibb { - compatible = "qcom,pmi8998-lab-ibb"; - - ibb: ibb { - interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>, - <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "sc-err", "ocp"; - }; - - lab: lab { - interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>, - <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "sc-err", "ocp"; - }; - }; - - pmi8998_lpg: pwm { - compatible = "qcom,pmi8998-lpg"; - - #address-cells = <1>; - #size-cells = <0>; - #pwm-cells = <2>; - - status = "disabled"; - }; - - pmi8998_flash: led-controller@d300 { - compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led"; - reg = <0xd300>; - status = "disabled"; - }; - - pmi8998_wled: leds@d800 { - compatible = "qcom,pmi8998-wled"; - reg = <0xd800>, <0xd900>; - interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, - <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp", "short"; - label = "backlight"; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi deleted file mode 100644 index 461ad97032f..00000000000 --- a/arch/arm/dts/pms405.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, Linaro Limited - */ - -#include <dt-bindings/spmi/spmi.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/iio/qcom,spmi-vadc.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - thermal-zones { - pms405-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pms405_temp>; - - trips { - pms405_alert0: pms405-alert0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - pms405_crit: pms405-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pms405_0: pms405@0 { - compatible = "qcom,pms405", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pms405_gpios: gpio@c000 { - compatible = "qcom,pms405-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pms405_gpios 0 0 12>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pon@800 { - compatible = "qcom,pms405-pon"; - reg = <0x0800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_POWER>; - }; - }; - - pms405_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pms405_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pms405_adc: adc@3100 { - compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - channel@0 { - reg = <ADC5_REF_GND>; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - channel@1 { - reg = <ADC5_1P25VREF>; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - channel@131 { - reg = <ADC5_VPH_PWR>; - qcom,pre-scaling = <1 3>; - label = "vph_pwr"; - }; - - channel@6 { - reg = <ADC5_DIE_TEMP>; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - - channel@77 { - reg = <ADC5_AMUX_THM1_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - label = "pa_therm1"; - }; - - channel@79 { - reg = <ADC5_AMUX_THM3_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - label = "pa_therm3"; - }; - - channel@76 { - reg = <ADC5_XO_THERM_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - label = "xo_therm"; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - }; - }; - - pms405_1: pms405@1 { - compatible = "qcom,pms405", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - - pms405_spmi_regulators: regulators { - compatible = "qcom,pms405-regulators"; - }; - }; -}; diff --git a/arch/arm/dts/qcs404-evb-4000.dts b/arch/arm/dts/qcs404-evb-4000.dts deleted file mode 100644 index 358827c2fbd..00000000000 --- a/arch/arm/dts/qcs404-evb-4000.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, Linaro Limited - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include "qcs404-evb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; - compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", - "qcom,qcs404"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&phy1>; - phy-mode = "rgmii"; - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x4>; - }; - }; -}; - -&tlmm { - ethernet_defaults: ethernet-defaults-state { - int-pins { - pins = "gpio61"; - function = "rgmii_int"; - bias-disable; - drive-strength = <2>; - }; - mdc-pins { - pins = "gpio76"; - function = "rgmii_mdc"; - bias-pull-up; - }; - mdio-pins { - pins = "gpio75"; - function = "rgmii_mdio"; - bias-pull-up; - }; - tx-pins { - pins = "gpio67", "gpio66", "gpio65", "gpio64"; - function = "rgmii_tx"; - bias-pull-up; - drive-strength = <16>; - }; - rx-pins { - pins = "gpio73", "gpio72", "gpio71", "gpio70"; - function = "rgmii_rx"; - bias-disable; - drive-strength = <2>; - }; - tx-ctl-pins { - pins = "gpio68"; - function = "rgmii_ctl"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ctl-pins { - pins = "gpio74"; - function = "rgmii_ctl"; - bias-disable; - drive-strength = <2>; - }; - tx-ck-pins { - pins = "gpio63"; - function = "rgmii_ck"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ck-pins { - pins = "gpio69"; - function = "rgmii_ck"; - bias-disable; - drive-strength = <2>; - }; - }; -}; diff --git a/arch/arm/dts/qcs404-evb.dtsi b/arch/arm/dts/qcs404-evb.dtsi deleted file mode 100644 index 10655401528..00000000000 --- a/arch/arm/dts/qcs404-evb.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, Linaro Limited - */ - -#include <dt-bindings/gpio/gpio.h> -#include "qcs404.dtsi" -#include "pms405.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> - -/ { - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ch0_3p3: - vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "eSMPS3_3P3"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - usb3_vbus_reg: regulator-usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_BOOST_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_vbus_boost_pin>; - vin-supply = <&vph_pwr>; - enable-active-high; - - /* TODO: Drop this when introducing role switching */ - regulator-always-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_l6_1p8>; - vddxo-supply = <&vreg_l5_1p8>; - vddrf-supply = <&vreg_l1_1p3>; - vddch0-supply = <&vdd_ch0_3p3>; - - local-bd-address = [ 02 00 00 00 5a ad ]; - - max-speed = <3200000>; - }; -}; - -&blsp1_dma { - qcom,controlled-remotely; -}; - -&blsp2_dma { - qcom,controlled-remotely; -}; - -&gcc { - protected-clocks = <GCC_BIMC_CDSP_CLK>, - <GCC_CDSP_CFG_AHB_CLK>, - <GCC_CDSP_BIMC_CLK_SRC>, - <GCC_CDSP_TBU_CLK>, - <141>, /* GCC_WCSS_Q6_AHB_CLK */ - <142>; /* GCC_WCSS_Q6_AXIM_CLK */ -}; - -&pms405_spmi_regulators { - vdd_s3-supply = <&vph_pwr>; - - pms405_s3: s3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd_apc"; - regulator-initial-mode = <1>; - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1384000>; - }; -}; - -&pcie { - status = "okay"; - - perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&perst_state>; -}; - -&pcie_phy { - status = "okay"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_cdsp { - status = "okay"; -}; - -&remoteproc_wcss { - status = "okay"; -}; - -&rpm_requests { - regulators { - compatible = "qcom,rpm-pms405-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_l1_l2-supply = <&vreg_s5_1p35>; - vdd_l3_l8-supply = <&vreg_s5_1p35>; - vdd_l4-supply = <&vreg_s5_1p35>; - vdd_l5_l6-supply = <&vreg_s4_1p8>; - vdd_l7-supply = <&vph_pwr>; - vdd_l9-supply = <&vreg_s5_1p35>; - vdd_l10_l11_l12_l13-supply = <&vph_pwr>; - - vreg_s4_1p8: s4 { - regulator-min-microvolt = <1728000>; - regulator-max-microvolt = <1920000>; - }; - - vreg_s5_1p35: s5 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l1_1p3: l1 { - regulator-min-microvolt = <1240000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l2_1p275: l2 { - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1280000>; - }; - - vreg_l3_1p05: l3 { - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1160000>; - }; - - vreg_l4_1p2: l4 { - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1256000>; - }; - - vreg_l5_1p8: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_l6_1p8: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vreg_l7_1p8: l7 { - regulator-min-microvolt = <1616000>; - regulator-max-microvolt = <3000000>; - }; - - vreg_l8_1p2: l8 { - regulator-min-microvolt = <1136000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l10_3p3: l10 { - regulator-min-microvolt = <2936000>; - regulator-max-microvolt = <3088000>; - }; - - vreg_l11_sdc2: l11 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <3304000>; - }; - - vreg_l12_3p3: l12 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_l13_3p3: l13 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - }; -}; - -&sdcc1 { - status = "okay"; - - supports-cqe; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - non-removable; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&tlmm { - perst_state: perst-state { - pins = "gpio43"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-low; - }; - - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - rclk-pins { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_off: sdc1-off-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - rclk-pins { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - usb3_id_pin: usb3-id-state { - pins = "gpio116"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; -}; - -&pms405_gpios { - usb_vbus_boost_pin: usb-vbus-boost-state { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = <1>; - }; - }; - usb3_vbus_pin: usb3-vbus-state { - pinconf { - pins = "gpio12"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - power-source = <1>; - }; - }; -}; - -&usb2 { - status = "okay"; -}; - -&usb2_phy_sec { - vdd-supply = <&vreg_l4_1p2>; - vdda1p8-supply = <&vreg_l5_1p8>; - vdda3p3-supply = <&vreg_l12_3p3>; - status = "okay"; -}; - -&usb3 { - status = "okay"; - -}; - -&usb3_dwc3 { - dr_mode = "host"; -}; - -&usb2_phy_prim { - vdd-supply = <&vreg_l4_1p2>; - vdda1p8-supply = <&vreg_l5_1p8>; - vdda3p3-supply = <&vreg_l12_3p3>; - status = "okay"; -}; - -&usb3_phy { - vdd-supply = <&vreg_l3_1p05>; - vdda1p8-supply = <&vreg_l5_1p8>; - status = "okay"; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; - vdd-1.8-xo-supply = <&vreg_l5_1p8>; - vdd-1.3-rfa-supply = <&vreg_l1_1p3>; -}; - -/* PINCTRL - additions to nodes defined in qcs404.dtsi */ - -&blsp1_uart2_default { - rx-pins { - drive-strength = <2>; - bias-disable; - }; - - tx-pins { - drive-strength = <2>; - bias-disable; - }; -}; - -&blsp1_uart3_default { - cts-pins { - bias-disable; - }; - - rts-tx-pins { - drive-strength = <2>; - bias-disable; - }; - - rx-pins { - bias-pull-up; - }; -}; diff --git a/arch/arm/dts/qcs404.dtsi b/arch/arm/dts/qcs404.dtsi deleted file mode 100644 index 2721f32dfb7..00000000000 --- a/arch/arm/dts/qcs404.dtsi +++ /dev/null @@ -1,1829 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, Linaro Limited - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/qcom,gcc-qcs404.h> -#include <dt-bindings/clock/qcom,turingcc-qcs404.h> -#include <dt-bindings/clock/qcom,rpmcc.h> -#include <dt-bindings/power/qcom-rpmpd.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x102>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x103>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <125>; - exit-latency-us = <180>; - min-residency-us = <595>; - local-timer-stop; - }; - }; - }; - - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2-kryo-cpu"; - opp-shared; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - required-opps = <&cpr_opp1>; - }; - opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - required-opps = <&cpr_opp2>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - required-opps = <&cpr_opp3>; - }; - }; - - cpr_opp_table: opp-table-cpr { - compatible = "operating-points-v2-qcom-level"; - - cpr_opp1: opp1 { - opp-level = <1>; - qcom,opp-fuse-level = <1>; - }; - cpr_opp2: opp2 { - opp-level = <2>; - qcom,opp-fuse-level = <2>; - }; - cpr_opp3: opp3 { - opp-level = <3>; - qcom,opp-fuse-level = <3>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-qcs404", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - rpm: remoteproc { - compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; - - glink-edge { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-qcs404"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,qcs404-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <416>; - }; - - rpmpd_opp_turbo_plus: opp11 { - opp-level = <512>; - }; - }; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz_apps_mem: memory@85900000 { - reg = <0 0x85900000 0 0x500000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - smem_region: memory@85f00000 { - reg = <0 0x85f00000 0 0x200000>; - no-map; - }; - - tz_mem: memory@86100000 { - reg = <0 0x86100000 0 0x300000>; - no-map; - }; - - wlan_fw_mem: memory@86400000 { - reg = <0 0x86400000 0 0x1100000>; - no-map; - }; - - adsp_fw_mem: memory@87500000 { - reg = <0 0x87500000 0 0x1a00000>; - no-map; - }; - - cdsp_fw_mem: memory@88f00000 { - reg = <0 0x88f00000 0 0x600000>; - no-map; - }; - - wlan_msa_mem: memory@89500000 { - reg = <0 0x89500000 0 0x100000>; - no-map; - }; - - uefi_mem: memory@9f800000 { - reg = <0 0x9f800000 0 0x800000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - soc: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - turingcc: clock-controller@800000 { - compatible = "qcom,qcs404-turingcc"; - reg = <0x00800000 0x30000>; - clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; - - #clock-cells = <1>; - #reset-cells = <1>; - - status = "disabled"; - }; - - rpm_msg_ram: sram@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00060000 0x6000>; - }; - - usb3_phy: phy@78000 { - compatible = "qcom,usb-ss-28nm-phy"; - reg = <0x00078000 0x400>; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "ref", "ahb", "pipe"; - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "com", "phy"; - status = "disabled"; - }; - - usb2_phy_prim: phy@7a000 { - compatible = "qcom,usb-hs-28nm-femtophy"; - reg = <0x0007a000 0x200>; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "ahb", "sleep"; - resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, - <&gcc GCC_USB2A_PHY_BCR>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - usb2_phy_sec: phy@7c000 { - compatible = "qcom,usb-hs-28nm-femtophy"; - reg = <0x0007c000 0x200>; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "ahb", "sleep"; - resets = <&gcc GCC_QUSB2_PHY_BCR>, - <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - qfprom: qfprom@a4000 { - compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; - reg = <0x000a4000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - cpr_efuse_speedbin: speedbin@13c { - reg = <0x13c 0x4>; - bits = <2 3>; - }; - - tsens_s0_p1: s0-p1@1f8 { - reg = <0x1f8 0x1>; - bits = <0 6>; - }; - - tsens_s0_p2: s0-p2@1f8 { - reg = <0x1f8 0x2>; - bits = <6 6>; - }; - - tsens_s1_p1: s1-p1@1f9 { - reg = <0x1f9 0x2>; - bits = <4 6>; - }; - - tsens_s1_p2: s1-p2@1fa { - reg = <0x1fa 0x1>; - bits = <2 6>; - }; - - tsens_s2_p1: s2-p1@1fb { - reg = <0x1fb 0x1>; - bits = <0 6>; - }; - - tsens_s2_p2: s2-p2@1fb { - reg = <0x1fb 0x2>; - bits = <6 6>; - }; - - tsens_s3_p1: s3-p1@1fc { - reg = <0x1fc 0x2>; - bits = <4 6>; - }; - - tsens_s3_p2: s3-p2@1fd { - reg = <0x1fd 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1: s4-p1@1fe { - reg = <0x1fe 0x1>; - bits = <0 6>; - }; - - tsens_s4_p2: s4-p2@1fe { - reg = <0x1fe 0x2>; - bits = <6 6>; - }; - - tsens_s5_p1: s5-p1@200 { - reg = <0x200 0x1>; - bits = <0 6>; - }; - - tsens_s5_p2: s5-p2@200 { - reg = <0x200 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1: s6-p1@201 { - reg = <0x201 0x2>; - bits = <4 6>; - }; - - tsens_s6_p2: s6-p2@202 { - reg = <0x202 0x1>; - bits = <2 6>; - }; - - tsens_s7_p1: s7-p1@203 { - reg = <0x203 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2: s7-p2@203 { - reg = <0x203 0x2>; - bits = <6 6>; - }; - - tsens_s8_p1: s8-p1@204 { - reg = <0x204 0x2>; - bits = <4 6>; - }; - - tsens_s8_p2: s8-p2@205 { - reg = <0x205 0x1>; - bits = <2 6>; - }; - - tsens_s9_p1: s9-p1@206 { - reg = <0x206 0x1>; - bits = <0 6>; - }; - - tsens_s9_p2: s9-p2@206 { - reg = <0x206 0x2>; - bits = <6 6>; - }; - - tsens_mode: mode@208 { - reg = <0x208 1>; - bits = <0 3>; - }; - - tsens_base1: base1@208 { - reg = <0x208 2>; - bits = <3 8>; - }; - - tsens_base2: base2@208 { - reg = <0x209 2>; - bits = <3 8>; - }; - - cpr_efuse_quot_offset1: qoffset1@231 { - reg = <0x231 0x4>; - bits = <4 7>; - }; - cpr_efuse_quot_offset2: qoffset2@232 { - reg = <0x232 0x4>; - bits = <3 7>; - }; - cpr_efuse_quot_offset3: qoffset3@233 { - reg = <0x233 0x4>; - bits = <2 7>; - }; - cpr_efuse_init_voltage1: ivoltage1@229 { - reg = <0x229 0x4>; - bits = <4 6>; - }; - cpr_efuse_init_voltage2: ivoltage2@22a { - reg = <0x22a 0x4>; - bits = <2 6>; - }; - cpr_efuse_init_voltage3: ivoltage3@22b { - reg = <0x22b 0x4>; - bits = <0 6>; - }; - cpr_efuse_quot1: quot1@22b { - reg = <0x22b 0x4>; - bits = <6 12>; - }; - cpr_efuse_quot2: quot2@22d { - reg = <0x22d 0x4>; - bits = <2 12>; - }; - cpr_efuse_quot3: quot3@230 { - reg = <0x230 0x4>; - bits = <0 12>; - }; - cpr_efuse_ring1: ring1@228 { - reg = <0x228 0x4>; - bits = <0 3>; - }; - cpr_efuse_ring2: ring2@228 { - reg = <0x228 0x4>; - bits = <4 3>; - }; - cpr_efuse_ring3: ring3@229 { - reg = <0x229 0x4>; - bits = <0 3>; - }; - cpr_efuse_revision: revision@218 { - reg = <0x218 0x4>; - bits = <3 3>; - }; - }; - - rng: rng@e3000 { - compatible = "qcom,prng-ee"; - reg = <0x000e3000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - bimc: interconnect@400000 { - reg = <0x00400000 0x80000>; - compatible = "qcom,qcs404-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - tsens: thermal-sensor@4a9000 { - compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_mode>, - <&tsens_base1>, <&tsens_base2>, - <&tsens_s0_p1>, <&tsens_s0_p2>, - <&tsens_s1_p1>, <&tsens_s1_p2>, - <&tsens_s2_p1>, <&tsens_s2_p2>, - <&tsens_s3_p1>, <&tsens_s3_p2>, - <&tsens_s4_p1>, <&tsens_s4_p2>, - <&tsens_s5_p1>, <&tsens_s5_p2>, - <&tsens_s6_p1>, <&tsens_s6_p2>, - <&tsens_s7_p1>, <&tsens_s7_p2>, - <&tsens_s8_p1>, <&tsens_s8_p2>, - <&tsens_s9_p1>, <&tsens_s9_p2>; - nvmem-cell-names = "mode", - "base1", "base2", - "s0_p1", "s0_p2", - "s1_p1", "s1_p2", - "s2_p1", "s2_p2", - "s3_p1", "s3_p2", - "s4_p1", "s4_p2", - "s5_p1", "s5_p2", - "s6_p1", "s6_p2", - "s7_p1", "s7_p2", - "s8_p1", "s8_p2", - "s9_p1", "s9_p2"; - #qcom,sensors = <10>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - pcnoc: interconnect@500000 { - reg = <0x00500000 0x15080>; - compatible = "qcom,qcs404-pcnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; - }; - - snoc: interconnect@580000 { - reg = <0x00580000 0x23080>; - compatible = "qcom,qcs404-snoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - remoteproc_cdsp: remoteproc@b00000 { - compatible = "qcom,qcs404-cdsp-pas"; - reg = <0x00b00000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - /* - * If the node was using the PIL binding, then include properties: - * clocks = <&xo_board>, - * <&gcc GCC_CDSP_CFG_AHB_CLK>, - * <&gcc GCC_CDSP_TBU_CLK>, - * <&gcc GCC_BIMC_CDSP_CLK>, - * <&turingcc TURING_WRAPPER_AON_CLK>, - * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, - * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, - * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; - * clock-names = "xo", - * "sway", - * "tbu", - * "bimc", - * "ahb_aon", - * "q6ss_slave", - * "q6ss_master", - * "q6_axim"; - * resets = <&gcc GCC_CDSP_RESTART>; - * reset-names = "restart"; - * qcom,halt-regs = <&tcsr 0x19004>; - */ - - memory-region = <&cdsp_fw_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; - - qcom,remote-pid = <5>; - mboxes = <&apcs_glb 12>; - - label = "cdsp"; - }; - }; - - usb3: usb@7678800 { - compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; - reg = <0x07678800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi"; - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - status = "disabled"; - - usb3_dwc3: usb@7580000 { - compatible = "snps,dwc3"; - reg = <0x07580000 0xcd00>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb2_phy_prim>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - dr_mode = "otg"; - }; - }; - - usb2: usb@79b8800 { - compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; - reg = <0x079b8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, - <&gcc GCC_PCNOC_USB2_CLK>, - <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi"; - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <19200000>, <133333333>; - status = "disabled"; - - usb@78c0000 { - compatible = "snps,dwc3"; - reg = <0x078c0000 0xcc00>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb2_phy_sec>; - phy-names = "usb2-phy"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - dr_mode = "peripheral"; - }; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,qcs404-pinctrl"; - reg = <0x01000000 0x200000>, - <0x01300000 0x200000>, - <0x07b00000 0x200000>; - reg-names = "south", "north", "east"; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&tlmm 0 0 120>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_i2c0_default: blsp1-i2c0-default-state { - pins = "gpio32", "gpio33"; - function = "blsp_i2c0"; - }; - - blsp1_i2c1_default: blsp1-i2c1-default-state { - pins = "gpio24", "gpio25"; - function = "blsp_i2c1"; - }; - - blsp1_i2c2_default: blsp1-i2c2-default-state { - sda-pins { - pins = "gpio19"; - function = "blsp_i2c_sda_a2"; - }; - - scl-pins { - pins = "gpio20"; - function = "blsp_i2c_scl_a2"; - }; - }; - - blsp1_i2c3_default: blsp1-i2c3-default-state { - pins = "gpio84", "gpio85"; - function = "blsp_i2c3"; - }; - - blsp1_i2c4_default: blsp1-i2c4-default-state { - pins = "gpio117", "gpio118"; - function = "blsp_i2c4"; - }; - - blsp1_uart0_default: blsp1-uart0-default-state { - pins = "gpio30", "gpio31", "gpio32", "gpio33"; - function = "blsp_uart0"; - }; - - blsp1_uart1_default: blsp1-uart1-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_uart1"; - }; - - blsp1_uart2_default: blsp1-uart2-default-state { - rx-pins { - pins = "gpio18"; - function = "blsp_uart_rx_a2"; - }; - - tx-pins { - pins = "gpio17"; - function = "blsp_uart_tx_a2"; - }; - }; - - blsp1_uart3_default: blsp1-uart3-default-state { - cts-pins { - pins = "gpio84"; - function = "blsp_uart3"; - }; - - rts-tx-pins { - pins = "gpio85", "gpio82"; - function = "blsp_uart3"; - }; - - rx-pins { - pins = "gpio83"; - function = "blsp_uart3"; - }; - }; - - blsp2_i2c0_default: blsp2-i2c0-default-state { - pins = "gpio28", "gpio29"; - function = "blsp_i2c5"; - }; - - blsp1_spi0_default: blsp1-spi0-default-state { - pins = "gpio30", "gpio31", "gpio32", "gpio33"; - function = "blsp_spi0"; - }; - - blsp1_spi1_default: blsp1-spi1-default-state { - mosi-pins { - pins = "gpio22"; - function = "blsp_spi_mosi_a1"; - }; - - miso-pins { - pins = "gpio23"; - function = "blsp_spi_miso_a1"; - }; - - cs-n-pins { - pins = "gpio24"; - function = "blsp_spi_cs_n_a1"; - }; - - clk-pins { - pins = "gpio25"; - function = "blsp_spi_clk_a1"; - }; - }; - - blsp1_spi2_default: blsp1-spi2-default-state { - pins = "gpio17", "gpio18", "gpio19", "gpio20"; - function = "blsp_spi2"; - }; - - blsp1_spi3_default: blsp1-spi3-default-state { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "blsp_spi3"; - }; - - blsp1_spi4_default: blsp1-spi4-default-state { - pins = "gpio37", "gpio38", "gpio117", "gpio118"; - function = "blsp_spi4"; - }; - - blsp2_spi0_default: blsp2-spi0-default-state { - pins = "gpio26", "gpio27", "gpio28", "gpio29"; - function = "blsp_spi5"; - }; - - blsp2_uart0_default: blsp2-uart0-default-state { - pins = "gpio26", "gpio27", "gpio28", "gpio29"; - function = "blsp_uart5"; - }; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-qcs404"; - reg = <0x01800000 0x80000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - clocks = <&xo_board>, - <&sleep_clk>, - <&pcie_phy>, - <0>, - <0>, - <0>; - - assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; - assigned-clock-rates = <19200000>; - }; - - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01905000 0x20000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@1937000 { - compatible = "qcom,qcs404-tcsr", "syscon"; - reg = <0x01937000 0x25000>; - }; - - sram@290000 { - compatible = "qcom,rpm-stats"; - reg = <0x00290000 0x10000>; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x800000>, - <0x02c00000 0x800000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - remoteproc_wcss: remoteproc@7400000 { - compatible = "qcom,qcs404-wcss-pas"; - reg = <0x07400000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&wlan_fw_mem>; - - qcom,smem-states = <&wcss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 16>; - - label = "wcss"; - }; - }; - - pcie_phy: phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - - status = "disabled"; - }; - - sdcc1: mmc@7804000 { - compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x7805000 0x1000>; - reg-names = "hc", "cqhci"; - - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - - status = "disabled"; - }; - - blsp1_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x25000>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "okay"; - }; - - blsp1_uart0: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart0_default>; - status = "disabled"; - }; - - blsp1_uart1: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b0000 0x200>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart1_default>; - status = "disabled"; - }; - - blsp1_uart2: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b1000 0x200>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_default>; - status = "okay"; - }; - - ethernet: ethernet@7a80000 { - compatible = "qcom,qcs404-ethqos"; - reg = <0x07a80000 0x10000>, - <0x07a96000 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_ETH_AXI_CLK>, - <&gcc GCC_ETH_SLAVE_AHB_CLK>, - <&gcc GCC_ETH_PTP_CLK>, - <&gcc GCC_ETH_RGMII_CLK>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_lpi"; - - snps,tso; - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; - - status = "disabled"; - }; - - wifi: wifi@a000000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0xa000000 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - blsp1_uart3: serial@78b2000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b2000 0x200>; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart3_default>; - status = "disabled"; - }; - - blsp1_i2c0: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi0: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c1: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi1: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi1_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c2: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi2: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi2_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi3: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi3_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c4: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi4: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi4_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_dma: dma-controller@7ac4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07ac4000 0x17000>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp2_uart0: serial@7aef000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x07aef000 0x200>; - interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart0_default>; - status = "disabled"; - }; - - blsp2_i2c0: i2c@7af5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x07af5000 0x600>; - interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_spi0: spi@7af5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x07af5000 0x600>; - interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_spi0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sram@8600000 { - compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; - reg = <0x08600000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0x08600000 0x1000>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0xc8>; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, - <0x0b002000 0x1000>; - }; - - apcs_glb: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global", - "qcom,msm8916-apcs-kpss-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; - - apcs_hfpll: clock-controller@b016000 { - compatible = "qcom,hfpll"; - reg = <0x0b016000 0x30>; - #clock-cells = <0>; - clock-output-names = "apcs_hfpll"; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - watchdog@b017000 { - compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; - reg = <0x0b017000 0x1000>; - clocks = <&sleep_clk>; - }; - - cpr: power-controller@b018000 { - compatible = "qcom,qcs404-cpr", "qcom,cpr"; - reg = <0x0b018000 0x1000>; - interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; - clocks = <&xo_board>; - clock-names = "ref"; - vdd-apc-supply = <&pms405_s3>; - #power-domain-cells = <0>; - operating-points-v2 = <&cpr_opp_table>; - acc-syscon = <&tcsr>; - - nvmem-cells = <&cpr_efuse_quot_offset1>, - <&cpr_efuse_quot_offset2>, - <&cpr_efuse_quot_offset3>, - <&cpr_efuse_init_voltage1>, - <&cpr_efuse_init_voltage2>, - <&cpr_efuse_init_voltage3>, - <&cpr_efuse_quot1>, - <&cpr_efuse_quot2>, - <&cpr_efuse_quot3>, - <&cpr_efuse_ring1>, - <&cpr_efuse_ring2>, - <&cpr_efuse_ring3>, - <&cpr_efuse_revision>; - nvmem-cell-names = "cpr_quotient_offset1", - "cpr_quotient_offset2", - "cpr_quotient_offset3", - "cpr_init_voltage1", - "cpr_init_voltage2", - "cpr_init_voltage3", - "cpr_quotient1", - "cpr_quotient2", - "cpr_quotient3", - "cpr_ring_osc1", - "cpr_ring_osc2", - "cpr_ring_osc3", - "cpr_fuse_revision"; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; - clock-frequency = <19200000>; - - frame@b121000 { - frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0b128000 0x1000>; - status = "disabled"; - }; - }; - - remoteproc_adsp: remoteproc@c700000 { - compatible = "qcom,qcs404-adsp-pas"; - reg = <0x0c700000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_fw_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; - - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 8>; - - label = "adsp"; - }; - }; - - pcie: pci@10000000 { - compatible = "qcom,pcie-qcs404"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x07780000 0x2000>, - <0x10001000 0x2000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ - <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ - - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - clock-names = "iface", "aux", "master_bus", "slave_bus"; - - resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_AHB_ARES>; - reset-names = "axi_m", - "axi_s", - "axi_m_sticky", - "pipe_sticky", - "pwr", - "ahb"; - - phys = <&pcie_phy>; - phy-names = "pciephy"; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 0xff08>, - <GIC_PPI 3 0xff08>, - <GIC_PPI 4 0xff08>, - <GIC_PPI 1 0xff08>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apcs_glb 10>; - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apcs_glb 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apcs_glb 18>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - wcss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - wcss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - thermal-zones { - aoss-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; - - trips { - aoss_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - lpass-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - lpass_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - cluster_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cluster_crit: cluster-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cluster_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu0_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_crit: cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu1_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1_crit: cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu2_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_crit: cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu3_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3_crit: cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - - trips { - gpu_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/qrb4210-rb2-u-boot.dtsi b/arch/arm/dts/qrb4210-rb2-u-boot.dtsi new file mode 100644 index 00000000000..7d1375f38c4 --- /dev/null +++ b/arch/arm/dts/qrb4210-rb2-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This is usually OTG but U-Boot doesn't support that properly */ +&usb_dwc3 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi b/arch/arm/dts/rk3308-evb-u-boot.dtsi index d15ba94d37b..007a69f9a60 100644 --- a/arch/arm/dts/rk3308-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi @@ -4,14 +4,11 @@ */ #include "rk3308-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc; - }; -}; - &uart4 { bootph-all; clock-frequency = <24000000>; - status = "okay"; +}; + +&uart4_xfer { + bootph-all; }; diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts index 124a2408668..184b84fdde0 100644 --- a/arch/arm/dts/rk3308-evb.dts +++ b/arch/arm/dts/rk3308-evb.dts @@ -23,7 +23,7 @@ poll-interval = <100>; keyup-threshold-microvolt = <1800000>; - func-key { + button-func { linux,code = <KEY_FN>; label = "function"; press-threshold-microvolt = <18000>; @@ -37,31 +37,31 @@ poll-interval = <100>; keyup-threshold-microvolt = <1800000>; - esc-key { + button-esc { linux,code = <KEY_MICMUTE>; label = "micmute"; press-threshold-microvolt = <1130000>; }; - home-key { + button-home { linux,code = <KEY_MODE>; label = "mode"; press-threshold-microvolt = <901000>; }; - menu-key { + button-menu { linux,code = <KEY_PLAY>; label = "play"; press-threshold-microvolt = <624000>; }; - vol-down-key { + button-down { linux,code = <KEY_VOLUMEDOWN>; label = "volume down"; press-threshold-microvolt = <300000>; }; - vol-up-key { + button-up { linux,code = <KEY_VOLUMEUP>; label = "volume up"; press-threshold-microvolt = <18000>; @@ -75,115 +75,115 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; - wakeup-source; debounce-interval = <100>; + wakeup-source; }; }; vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; }; vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; regulator-always-on; regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_1v0: vdd-1v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc12v_dcin>; }; vccio_sdio: vcc_1v8: vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc_io>; }; vcc_ddr: vcc-ddr { compatible = "regulator-fixed"; regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc5v0_sys>; }; vcc_io: vcc-io { compatible = "regulator-fixed"; regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc5v0_sys>; }; vccio_flash: vccio-flash { compatible = "regulator-fixed"; regulator-name = "vccio_flash"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc_io>; }; vcc5v0_host: vcc5v0-host { compatible = "regulator-fixed"; - enable-active-high; gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&usb_drv>; regulator-name = "vbus_host"; vin-supply = <&vcc5v0_sys>; }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu0 { diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi index 97d922c435d..3e01e7af611 100644 --- a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi @@ -5,13 +5,37 @@ #include "rk3308-u-boot.dtsi" / { - chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc; + aliases { + ethernet0 = &gmac; }; }; +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&mac_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmiim1_pins &macm1_refclk>; + status = "okay"; +}; + +&gpio4 { + bootph-pre-ram; +}; + &uart2 { bootph-all; clock-frequency = <24000000>; - status = "okay"; +}; + +&uart2m0_xfer { + bootph-all; +}; + +&vcc_sd { + bootph-pre-ram; +}; + +&vdd_core { + regulator-init-microvolt = <1015000>; }; diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts index b4a54a852ce..9232357f4fe 100644 --- a/arch/arm/dts/rk3308-roc-cc.dts +++ b/arch/arm/dts/rk3308-roc-cc.dts @@ -9,11 +9,17 @@ / { model = "Firefly ROC-RK3308-CC board"; compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; - ir_rx { + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -27,14 +33,15 @@ leds { compatible = "gpio-leds"; - power { + + power_led: led-0 { label = "firefly:red:power"; linux,default-trigger = "ir-power-click"; default-state = "on"; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; }; - user { + user_led: led-1 { label = "firefly:blue:user"; linux,default-trigger = "ir-user-click"; default-state = "off"; @@ -45,10 +52,10 @@ typec_vcc5v: typec-vcc5v { compatible = "regulator-fixed"; regulator-name = "typec_vcc5v"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; }; vcc5v0_sys: vcc5v0-sys { @@ -61,29 +68,6 @@ vin-supply = <&typec_vcc5v>; }; - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-init-microvolt = <1015000>; - regulator-always-on; - regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; - vcc_io: vcc-io { compatible = "regulator-fixed"; regulator-name = "vcc_io"; @@ -100,8 +84,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; vin-supply = <&vcc5v0_sys>; }; @@ -113,9 +97,30 @@ regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; - vim-supply = <&vcc_io>; + vin-supply = <&vcc_io>; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + pwm-supply = <&vcc5v0_sys>; }; + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu0 { @@ -123,12 +128,9 @@ }; &emmc { - bus-width = <8>; cap-mmc-highspeed; - supports-emmc; - disable-wp; + mmc-hs200-1_8v; non-removable; - num-slots = <1>; status = "okay"; }; @@ -143,15 +145,6 @@ }; }; -&mac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&mac_clkin>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rmiim1_pins &macm1_refclk>; - status = "okay"; -}; - &pwm5 { status = "okay"; pinctrl-names = "active"; @@ -181,10 +174,8 @@ }; &sdmmc { - bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - supports-sd; card-detect-delay = <300>; sd-uhs-sdr25; sd-uhs-sdr50; diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index d88dee80573..a6fb8b12da3 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -4,39 +4,42 @@ */ #include "rk3308-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc; - }; +&emmc { + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>; }; -&uart0 { - bootph-all; -}; - -&pinctrl { +&emmc_bus4 { + bootph-pre-ram; bootph-some-ram; +}; - uart0 { - bootph-some-ram; - }; - rtc { - bootph-some-ram; - }; +&u2phy_otg { + /delete-property/ phy-supply; }; -&uart0_xfer { - bootph-some-ram; +&uart0 { + bootph-all; + clock-frequency = <24000000>; }; &uart0_cts { - bootph-some-ram; + bootph-all; }; &uart0_rts { - bootph-some-ram; + bootph-all; }; -&rtc_32k { - bootph-some-ram; +&uart0_xfer { + bootph-all; +}; + +&vcc5v0_otg { + /delete-property/ regulator-always-on; +}; + +&vdd_core { + regulator-init-microvolt = <1015000>; }; diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts b/arch/arm/dts/rk3308-rock-pi-s.dts index b5a8691b3fe..b47fe02c33f 100644 --- a/arch/arm/dts/rk3308-rock-pi-s.dts +++ b/arch/arm/dts/rk3308-rock-pi-s.dts @@ -1,12 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (C) 2023 Akash Gajjar <gajjar04akash@gmail.com> - * Copyright (c) 2023 Jagan Teki <jagan@openedev.com> + * Copyright (c) 2019 Akash Gajjar <akash@openedev.com> + * Copyright (c) 2019 Jagan Teki <jagan@openedev.com> */ /dts-v1/; -#include <dt-bindings/input/input.h> #include "rk3308.dtsi" / { @@ -14,7 +12,7 @@ compatible = "radxa,rockpis", "rockchip,rk3308"; aliases { - ethernet0 = &mac; + ethernet0 = &gmac; mmc0 = &emmc; mmc1 = &sdmmc; }; @@ -107,7 +105,6 @@ regulator-name = "vdd_core"; regulator-min-microvolt = <827000>; regulator-max-microvolt = <1340000>; - regulator-init-microvolt = <1015000>; regulator-settling-time-up-us = <250>; regulator-always-on; regulator-boot-on; @@ -137,7 +134,7 @@ status = "okay"; }; -&mac { +&gmac { clock_in_out = "output"; phy-supply = <&vcc_io>; snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; @@ -146,6 +143,68 @@ status = "okay"; }; +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "header1-pin3 [GPIO0_B3]", + "header1-pin5 [GPIO0_B4]", "", "", + "header1-pin11 [GPIO0_B7]", + /* GPIO0_C0 - C7 */ + "header1-pin13 [GPIO0_C0]", + "header1-pin15 [GPIO0_C1]", "", "", "", + "", "", "", + /* GPIO0_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", + "header1-pin19 [GPIO1_C7]", + /* GPIO1_D0 - D7 */ + "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", + "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", + "", "", + "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", + "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", + /* GPIO2_B0 - B7 */ + "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", + "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", + "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", + "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", + /* GPIO2_C0 - C7 */ + "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_B0 - B7 */ + "", "", "header2-pin42 [GPIO3_B2]", + "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", + "header2-pin39 [GPIO3_B5]", "", "", + /* GPIO3_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + &i2c1 { status = "okay"; }; @@ -209,6 +268,20 @@ status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; + + u2phy_otg: otg-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; +}; + &uart0 { status = "okay"; }; @@ -223,6 +296,19 @@ }; }; +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index db2c20a7055..684fa7abddb 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -10,32 +10,134 @@ mmc0 = &emmc; mmc1 = &sdmmc; }; -}; -&cru { - bootph-all; + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; + + dmc: dmc@ff010000 { + compatible = "rockchip,rk3308-dmc"; + reg = <0x0 0xff010000 0x0 0x10000>; + bootph-all; + }; + + otp: nvmem@ff210000 { + compatible = "rockchip,rk3308-otp"; + reg = <0x0 0xff210000 0x0 0x4000>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "phy"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + }; + + rng: rng@ff2f0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff2f0000 0x0 0x4000>; + }; }; -&dmc { +&cru { bootph-all; }; &emmc { + bootph-pre-ram; + bootph-some-ram; + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&grf { bootph-all; }; -&sdmmc { +&pcfg_pull_none { bootph-all; - u-boot,spl-fifo-mode; }; -&grf { +&pcfg_pull_none_4ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_none_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up { bootph-all; }; -&saradc { +&pcfg_pull_up_4ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&rtc_32k { + bootph-all; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&sdmmc_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&xin24m { bootph-all; - status = "okay"; }; diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi index 9a152a8a907..cfc0a87b519 100644 --- a/arch/arm/dts/rk3308.dtsi +++ b/arch/arm/dts/rk3308.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd * @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> #include <dt-bindings/thermal/thermal.h> / { @@ -19,6 +20,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -39,7 +45,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; clocks = <&cru ARMCLK>; @@ -52,7 +58,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; @@ -62,7 +68,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; @@ -72,7 +78,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; @@ -95,10 +101,12 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -126,7 +134,7 @@ }; arm-pmu { - compatible = "arm,cortex-a53-pmu"; + compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, @@ -163,12 +171,53 @@ grf: grf@ff000000 { compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x10000>; + reg = <0x0 0xff000000 0x0 0x08000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x500>; + mode-bootloader = <BOOT_BL_DOWNLOAD>; + mode-loader = <BOOT_BL_DOWNLOAD>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-fastboot = <BOOT_FASTBOOT>; + }; }; - dmc: dmc@0xff010000 { - compatible = "rockchip,rk3308-dmc"; - reg = <0x0 0xff010000 0x0 0x10000>; + usb2phy_grf: syscon@ff008000 { + compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff008000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2phy@100 { + compatible = "rockchip,rk3308-usb2phy"; + reg = <0x100 0x10>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; detect_grf: syscon@ff00b000 { @@ -183,7 +232,6 @@ reg = <0x0 0xff00c000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; - }; i2c0: i2c@ff040000 { @@ -239,7 +287,7 @@ }; wdt: watchdog@ff080000 { - compatible = "snps,dw-wdt"; + compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; reg = <0x0 0xff080000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -321,9 +369,8 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 0>, <&dmac0 1>; dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; + pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; - pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; status = "disabled"; }; @@ -337,9 +384,8 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 2>, <&dmac0 3>; dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; + pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; - pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>; status = "disabled"; }; @@ -353,141 +399,140 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&dmac1 16>, <&dmac1 17>; dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; + pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; - pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; status = "disabled"; }; pwm8: pwm@ff160000 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm8_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm8_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm9: pwm@ff160010 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm9_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm9_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm10: pwm@ff160020 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm10_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm10_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm11: pwm@ff160030 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm11_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm11_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm4: pwm@ff170000 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm5: pwm@ff170010 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm6: pwm@ff170020 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm6_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm7: pwm@ff170030 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm0: pwm@ff180000 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm1: pwm@ff180010 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm2: pwm@ff180020 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm3: pwm@ff180030 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; status = "disabled"; }; @@ -503,41 +548,34 @@ compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff1e0000 0x0 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + #io-channel-cells = <1>; resets = <&cru SRST_SARADC_P>; reset-names = "saradc-apb"; status = "disabled"; }; - amba { - compatible = "arm,amba-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + dmac0: dma-controller@ff2c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - peripherals-req-type-burst; - }; - - dmac1: dma-controller@ff2d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2d0000 0x0 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - peripherals-req-type-burst; - }; + dmac1: dma-controller@ff2d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2d0000 0x0 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; }; i2s_2ch_0: i2s@ff350000 { @@ -572,7 +610,7 @@ }; spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif"; + compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; reg = <0x0 0xff3a0000 0x0 0x1000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; @@ -584,16 +622,52 @@ status = "disabled"; }; + usb20_otg: usb@ff400000 { + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ehci: usb@ff440000 { + compatible = "generic-ehci"; + reg = <0x0 0xff440000 0x0 0x10000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@ff450000 { + compatible = "generic-ohci"; + reg = <0x0 0xff450000 0x0 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + sdmmc: mmc@ff480000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff480000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; bus-width = <4>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; status = "disabled"; @@ -602,35 +676,49 @@ emmc: mmc@ff490000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff490000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; bus-width = <8>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; status = "disabled"; }; sdio: mmc@ff4a0000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff4a0000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; bus-width = <4>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; status = "disabled"; }; - mac: ethernet@ff4e0000 { - compatible = "rockchip,rk3308-mac"; + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,rk3308-nfc", + "rockchip,rv1108-nfc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 + &flash_rdn &flash_rdy &flash_wrn>; + pinctrl-names = "default"; + status = "disabled"; + }; + + gmac: ethernet@ff4e0000 { + compatible = "rockchip,rk3308-gmac"; reg = <0x0 0xff4e0000 0x0 0x10000>; - rockchip,grf = <&grf>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, @@ -646,40 +734,57 @@ pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; resets = <&cru SRST_MAC_A>; reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + sfc: spi@ff4c0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff4c0000 0x0 0x4000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; status = "disabled"; }; cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru SCLK_RTC32K>; + assigned-clock-rates = <32768>; }; gic: interrupt-controller@ff580000 { compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff581000 0x0 0x1000>, <0x0 0xff582000 0x0 0x2000>, <0x0 0xff584000 0x0 0x2000>, <0x0 0xff586000 0x0 0x2000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <0>; }; sram: sram@fff80000 { compatible = "mmio-sram"; reg = <0x0 0xfff80000 0x0 0x40000>; + ranges = <0 0x0 0xfff80000 0x40000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0xfff80000 0x40000>; + /* reserved for ddr dvfs and system suspend/resume */ ddr-sram@0 { reg = <0x0 0x8000>; }; + /* reserved for vad audio buffer */ vad_sram: vad-sram@8000 { reg = <0x8000 0x38000>; @@ -692,62 +797,58 @@ #address-cells = <2>; #size-cells = <2>; ranges; - gpio0: gpio0@ff220000 { + + gpio0: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio1: gpio1@ff230000 { + gpio1: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio2: gpio2@ff240000 { + gpio2: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio3: gpio3@ff250000 { + gpio3: gpio@ff250000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff250000 0x0 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio4: gpio4@ff260000 { + gpio4: gpio@ff260000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; @@ -831,6 +932,191 @@ input-enable; }; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + <3 RK_PB1 2 &pcfg_pull_none_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <3 RK_PB0 2 &pcfg_pull_up_8ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + emmc_rstn: emmc-rstn { + rockchip,pins = + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up_8ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up_8ma>, + <3 RK_PA1 2 &pcfg_pull_up_8ma>, + <3 RK_PA2 2 &pcfg_pull_up_8ma>, + <3 RK_PA3 2 &pcfg_pull_up_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up_8ma>, + <3 RK_PA1 2 &pcfg_pull_up_8ma>, + <3 RK_PA2 2 &pcfg_pull_up_8ma>, + <3 RK_PA3 2 &pcfg_pull_up_8ma>, + <3 RK_PA4 2 &pcfg_pull_up_8ma>, + <3 RK_PA5 2 &pcfg_pull_up_8ma>, + <3 RK_PA6 2 &pcfg_pull_up_8ma>, + <3 RK_PA7 2 &pcfg_pull_up_8ma>; + }; + }; + + flash { + flash_csn0: flash-csn0 { + rockchip,pins = + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = + <3 RK_PB4 1 &pcfg_pull_none>; + }; + + flash_ale: flash-ale { + rockchip,pins = + <3 RK_PB3 1 &pcfg_pull_none>; + }; + + flash_cle: flash-cle { + rockchip,pins = + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = + <3 RK_PB2 1 &pcfg_pull_none>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_up_12ma>, + <3 RK_PA1 1 &pcfg_pull_up_12ma>, + <3 RK_PA2 1 &pcfg_pull_up_12ma>, + <3 RK_PA3 1 &pcfg_pull_up_12ma>, + <3 RK_PA4 1 &pcfg_pull_up_12ma>, + <3 RK_PA5 1 &pcfg_pull_up_12ma>, + <3 RK_PA6 1 &pcfg_pull_up_12ma>, + <3 RK_PA7 1 &pcfg_pull_up_12ma>; + }; + }; + + sfc { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>, + <3 RK_PA2 3 &pcfg_pull_none>, + <3 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <3 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + gmac { + rmii_pins: rmii-pins { + rockchip,pins = + /* mac_txen */ + <1 RK_PC1 3 &pcfg_pull_none_12ma>, + /* mac_txd1 */ + <1 RK_PC3 3 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 RK_PC2 3 &pcfg_pull_none_12ma>, + /* mac_rxd0 */ + <1 RK_PC4 3 &pcfg_pull_none>, + /* mac_rxd1 */ + <1 RK_PC5 3 &pcfg_pull_none>, + /* mac_rxer */ + <1 RK_PB7 3 &pcfg_pull_none>, + /* mac_rxdv */ + <1 RK_PC0 3 &pcfg_pull_none>, + /* mac_mdio */ + <1 RK_PB6 3 &pcfg_pull_none>, + /* mac_mdc */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + + mac_refclk_12ma: mac-refclk-12ma { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none_12ma>; + }; + + mac_refclk: mac-refclk { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + gmac-m1 { + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_txen */ + <4 RK_PB7 2 &pcfg_pull_none_12ma>, + /* mac_txd1 */ + <4 RK_PA5 2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <4 RK_PA4 2 &pcfg_pull_none_12ma>, + /* mac_rxd0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* mac_rxd1 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* mac_rxer */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* mac_rxdv */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* mac_mdio */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* mac_mdc */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + macm1_refclk_12ma: macm1-refclk-12ma { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none_12ma>; + }; + + macm1_refclk: macm1-refclk { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = @@ -1163,281 +1449,154 @@ }; }; - spdif_in { - spdif_in: spdif-in { + pwm0 { + pwm0_pin: pwm0-pin { rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; + <0 RK_PB5 1 &pcfg_pull_none>; }; - }; - spdif_out { - spdif_out: spdif-out { + pwm0_pin_pull_down: pwm0-pin-pull-down { rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; + <0 RK_PB5 1 &pcfg_pull_down>; }; }; - tsadc { - tsadc_otp_gpio: tsadc-otp-gpio { + pwm1 { + pwm1_pin: pwm1-pin { rockchip,pins = - <0 RK_PB2 0 &pcfg_pull_none>; + <0 RK_PB6 1 &pcfg_pull_none>; }; - tsadc_otp_out: tsadc-otp-out { + pwm1_pin_pull_down: pwm1-pin-pull-down { rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_none>; + <0 RK_PB6 1 &pcfg_pull_down>; }; }; - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <2 RK_PA1 1 &pcfg_pull_up>, - <2 RK_PA0 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <2 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { + pwm2 { + pwm2_pin: pwm2-pin { rockchip,pins = - <2 RK_PA3 1 &pcfg_pull_none>; + <0 RK_PB7 1 &pcfg_pull_none>; }; - uart0_rts_gpio: uart0-rts-gpio { + pwm2_pin_pull_down: pwm2-pin-pull-down { rockchip,pins = - <2 RK_PA3 0 &pcfg_pull_none>; + <0 RK_PB7 1 &pcfg_pull_down>; }; }; - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <1 RK_PD1 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { + pwm3 { + pwm3_pin: pwm3-pin { rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_none>; + <0 RK_PC0 1 &pcfg_pull_none>; }; - uart1_rts: uart1-rts { + pwm3_pin_pull_down: pwm3-pin-pull-down { rockchip,pins = - <1 RK_PC7 1 &pcfg_pull_none>; + <0 RK_PC0 1 &pcfg_pull_down>; }; }; - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { + pwm4 { + pwm4_pin: pwm4-pin { rockchip,pins = - <1 RK_PC7 2 &pcfg_pull_up>, - <1 RK_PC6 2 &pcfg_pull_up>; + <0 RK_PA1 2 &pcfg_pull_none>; }; - }; - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { + pwm4_pin_pull_down: pwm4-pin-pull-down { rockchip,pins = - <4 RK_PD3 2 &pcfg_pull_up>, - <4 RK_PD2 2 &pcfg_pull_up>; + <0 RK_PA1 2 &pcfg_pull_down>; }; }; - uart3 { - uart3_xfer: uart3-xfer { + pwm5 { + pwm5_pin: pwm5-pin { rockchip,pins = - <3 RK_PB5 4 &pcfg_pull_up>, - <3 RK_PB4 4 &pcfg_pull_up>; + <0 RK_PC1 2 &pcfg_pull_none>; }; - }; - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { + pwm5_pin_pull_down: pwm5-pin-pull-down { rockchip,pins = - <0 RK_PC2 3 &pcfg_pull_up>, - <0 RK_PC1 3 &pcfg_pull_up>; + <0 RK_PC1 2 &pcfg_pull_down>; }; }; - uart4 { - - uart4_xfer: uart4-xfer { - rockchip,pins = - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <4 RK_PA6 1 &pcfg_pull_none>; - - }; - - uart4_rts: uart4-rts { + pwm6 { + pwm6_pin: pwm6-pin { rockchip,pins = - <4 RK_PA7 1 &pcfg_pull_none>; + <0 RK_PC2 2 &pcfg_pull_none>; }; - uart4_rts_gpio: uart4-rts-gpio { + pwm6_pin_pull_down: pwm6-pin-pull-down { rockchip,pins = - <4 RK_PA7 0 &pcfg_pull_none>; + <0 RK_PC2 2 &pcfg_pull_down>; }; }; - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_4ma>; - }; - - spi0_csn0: spi0-csn0 { - rockchip,pins = - <2 RK_PA3 2 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_4ma>; - }; - - spi0_clk_hs: spi0-clk-hs { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_8ma>; - }; - - spi0_miso_hs: spi0-miso-hs { + pwm7 { + pwm7_pin: pwm7-pin { rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_8ma>; + <2 RK_PB0 2 &pcfg_pull_none>; }; - spi0_mosi_hs: spi0-mosi-hs { + pwm7_pin_pull_down: pwm7-pin-pull-down { rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_8ma>; + <2 RK_PB0 2 &pcfg_pull_down>; }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - - spi1_clk_hs: spi1-clk-hs { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_8ma>; - }; - - spi1_miso_hs: spi1-miso-hs { + pwm8 { + pwm8_pin: pwm8-pin { rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_8ma>; + <2 RK_PB2 2 &pcfg_pull_none>; }; - spi1_mosi_hs: spi1-mosi-hs { + pwm8_pin_pull_down: pwm8-pin-pull-down { rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_8ma>; + <2 RK_PB2 2 &pcfg_pull_down>; }; }; - spi1-m1 { - spi1m1_miso: spi1m1-miso { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_mosi: spi1m1-mosi { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_clk: spi1m1-clk { - rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_csn0: spi1m1-csn0 { - rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_miso_hs: spi1m1-miso-hs { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_8ma>; - }; - - spi1m1_mosi_hs: spi1m1-mosi-hs { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_8ma>; - }; - - spi1m1_clk_hs: spi1m1-clk-hs { + pwm9 { + pwm9_pin: pwm9-pin { rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_8ma>; + <2 RK_PB3 2 &pcfg_pull_none>; }; - spi1m1_csn0_hs: spi1m1-csn0-hs { + pwm9_pin_pull_down: pwm9-pin-pull-down { rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_8ma>; + <2 RK_PB3 2 &pcfg_pull_down>; }; }; - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_4ma>; - }; - - spi2_csn0: spi2-csn0 { - rockchip,pins = - <1 RK_PD1 3 &pcfg_pull_up_4ma>; - }; - - spi2_miso: spi2-miso { + pwm10 { + pwm10_pin: pwm10-pin { rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_4ma>; + <2 RK_PB4 2 &pcfg_pull_none>; }; - spi2_mosi: spi2-mosi { + pwm10_pin_pull_down: pwm10-pin-pull-down { rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_4ma>; + <2 RK_PB4 2 &pcfg_pull_down>; }; + }; - spi2_clk_hs: spi2-clk-hs { + pwm11 { + pwm11_pin: pwm11-pin { rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_8ma>; + <2 RK_PC0 4 &pcfg_pull_none>; }; - spi2_miso_hs: spi2-miso-hs { + pwm11_pin_pull_down: pwm11-pin-pull-down { rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_8ma>; + <2 RK_PC0 4 &pcfg_pull_down>; }; + }; - spi2_mosi_hs: spi2-mosi-hs { + rtc { + rtc_32k: rtc-32k { rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_8ma>; + <0 RK_PC3 1 &pcfg_pull_none>; }; }; @@ -1474,17 +1633,6 @@ <4 RK_PD2 1 &pcfg_pull_up_4ma>, <4 RK_PD3 1 &pcfg_pull_up_4ma>; }; - - sdmmc_gpio: sdmmc-gpio { - rockchip,pins = - <4 RK_PD0 0 &pcfg_pull_up_4ma>, - <4 RK_PD1 0 &pcfg_pull_up_4ma>, - <4 RK_PD2 0 &pcfg_pull_up_4ma>, - <4 RK_PD3 0 &pcfg_pull_up_4ma>, - <4 RK_PD4 0 &pcfg_pull_up_4ma>, - <4 RK_PD5 0 &pcfg_pull_up_4ma>, - <4 RK_PD6 0 &pcfg_pull_up_4ma>; - }; }; sdio { @@ -1525,327 +1673,216 @@ <4 RK_PA2 1 &pcfg_pull_up_8ma>, <4 RK_PA3 1 &pcfg_pull_up_8ma>; }; - - sdio_gpio: sdio-gpio { - rockchip,pins = - <4 RK_PA0 0 &pcfg_pull_up_4ma>, - <4 RK_PA1 0 &pcfg_pull_up_4ma>, - <4 RK_PA2 0 &pcfg_pull_up_4ma>, - <4 RK_PA3 0 &pcfg_pull_up_4ma>, - <4 RK_PA4 0 &pcfg_pull_up_4ma>, - <4 RK_PA5 0 &pcfg_pull_up_4ma>; - }; }; - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { + spdif_in { + spdif_in: spdif-in { rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up_8ma>; + <0 RK_PC2 1 &pcfg_pull_none>; }; + }; - emmc_pwren: emmc-pwren { + spdif_out { + spdif_out: spdif-out { rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; + <0 RK_PC1 1 &pcfg_pull_none>; }; + }; - emmc_rstn: emmc-rstn { + spi0 { + spi0_clk: spi0-clk { rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_none>; + <2 RK_PA2 2 &pcfg_pull_up_4ma>; }; - emmc_bus1: emmc-bus1 { + spi0_csn0: spi0-csn0 { rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>; + <2 RK_PA3 2 &pcfg_pull_up_4ma>; }; - emmc_bus4: emmc-bus4 { + spi0_miso: spi0-miso { rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>; + <2 RK_PA0 2 &pcfg_pull_up_4ma>; }; - emmc_bus8: emmc-bus8 { + spi0_mosi: spi0-mosi { rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>, - <3 RK_PA4 2 &pcfg_pull_up_8ma>, - <3 RK_PA5 2 &pcfg_pull_up_8ma>, - <3 RK_PA6 2 &pcfg_pull_up_8ma>, - <3 RK_PA7 2 &pcfg_pull_up_8ma>; + <2 RK_PA1 2 &pcfg_pull_up_4ma>; }; }; - flash { - flash_csn0: flash-csn0 { - rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <3 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <3 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { + spi1 { + spi1_clk: spi1-clk { rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none>; + <3 RK_PB3 3 &pcfg_pull_up_4ma>; }; - flash_wrn: flash-wrn { + spi1_csn0: spi1-csn0 { rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none>; + <3 RK_PB5 3 &pcfg_pull_up_4ma>; }; - flash_rdn: flash-rdn { + spi1_miso: spi1-miso { rockchip,pins = - <3 RK_PB2 1 &pcfg_pull_none>; + <3 RK_PB2 3 &pcfg_pull_up_4ma>; }; - flash_bus8: flash-bus8 { + spi1_mosi: spi1-mosi { rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_up_12ma>, - <3 RK_PA1 1 &pcfg_pull_up_12ma>, - <3 RK_PA2 1 &pcfg_pull_up_12ma>, - <3 RK_PA3 1 &pcfg_pull_up_12ma>, - <3 RK_PA4 1 &pcfg_pull_up_12ma>, - <3 RK_PA5 1 &pcfg_pull_up_12ma>, - <3 RK_PA6 1 &pcfg_pull_up_12ma>, - <3 RK_PA7 1 &pcfg_pull_up_12ma>; + <3 RK_PB4 3 &pcfg_pull_up_4ma>; }; }; - pwm0 { - pwm0_pin: pwm0-pin { + spi1-m1 { + spi1m1_miso: spi1m1-miso { rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; + <2 RK_PA4 2 &pcfg_pull_up_4ma>; }; - pwm0_pin_pull_down: pwm0-pin-pull-down { + spi1m1_mosi: spi1m1-mosi { rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_down>; + <2 RK_PA5 2 &pcfg_pull_up_4ma>; }; - }; - pwm1 { - pwm1_pin: pwm1-pin { + spi1m1_clk: spi1m1-clk { rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_none>; + <2 RK_PA7 2 &pcfg_pull_up_4ma>; }; - pwm1_pin_pull_down: pwm1-pin-pull-down { + spi1m1_csn0: spi1m1-csn0 { rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_down>; + <2 RK_PB1 2 &pcfg_pull_up_4ma>; }; }; - pwm2 { - pwm2_pin: pwm2-pin { + spi2 { + spi2_clk: spi2-clk { rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; + <1 RK_PD0 3 &pcfg_pull_up_4ma>; }; - pwm2_pin_pull_down: pwm2-pin-pull-down { + spi2_csn0: spi2-csn0 { rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_down>; + <1 RK_PD1 3 &pcfg_pull_up_4ma>; }; - }; - pwm3 { - pwm3_pin: pwm3-pin { + spi2_miso: spi2-miso { rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; + <1 RK_PC6 3 &pcfg_pull_up_4ma>; }; - pwm3_pin_pull_down: pwm3-pin-pull-down { + spi2_mosi: spi2-mosi { rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_down>; + <1 RK_PC7 3 &pcfg_pull_up_4ma>; }; }; - pwm4 { - pwm4_pin: pwm4-pin { + tsadc { + tsadc_otp_pin: tsadc-otp-pin { rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_none>; + <0 RK_PB2 0 &pcfg_pull_none>; }; - pwm4_pin_pull_down: pwm4-pin-pull-down { + tsadc_otp_out: tsadc-otp-out { rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_down>; + <0 RK_PB2 1 &pcfg_pull_none>; }; }; - pwm5 { - pwm5_pin: pwm5-pin { + uart0 { + uart0_xfer: uart0-xfer { rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_none>; + <2 RK_PA1 1 &pcfg_pull_up>, + <2 RK_PA0 1 &pcfg_pull_up>; }; - pwm5_pin_pull_down: pwm5-pin-pull-down { + uart0_cts: uart0-cts { rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_down>; + <2 RK_PA2 1 &pcfg_pull_none>; }; - }; - pwm6 { - pwm6_pin: pwm6-pin { + uart0_rts: uart0-rts { rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; + <2 RK_PA3 1 &pcfg_pull_none>; }; - pwm6_pin_pull_down: pwm6-pin-pull-down { + uart0_rts_pin: uart0-rts-pin { rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_down>; + <2 RK_PA3 0 &pcfg_pull_none>; }; }; - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>; - }; - - pwm7_pin_pull_down: pwm7-pin-pull-down { + uart1 { + uart1_xfer: uart1-xfer { rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_down>; + <1 RK_PD1 1 &pcfg_pull_up>, + <1 RK_PD0 1 &pcfg_pull_up>; }; - }; - pwm8 { - pwm8_pin: pwm8-pin { + uart1_cts: uart1-cts { rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; + <1 RK_PC6 1 &pcfg_pull_none>; }; - pwm8_pin_pull_down: pwm8-pin-pull-down { + uart1_rts: uart1-rts { rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_down>; + <1 RK_PC7 1 &pcfg_pull_none>; }; }; - pwm9 { - pwm9_pin: pwm9-pin { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_none>; - }; - - pwm9_pin_pull_down: pwm9-pin-pull-down { + uart2-m0 { + uart2m0_xfer: uart2m0-xfer { rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_down>; + <1 RK_PC7 2 &pcfg_pull_up>, + <1 RK_PC6 2 &pcfg_pull_up>; }; }; - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_none>; - }; - - pwm10_pin_pull_down: pwm10-pin-pull-down { + uart2-m1 { + uart2m1_xfer: uart2m1-xfer { rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_down>; + <4 RK_PD3 2 &pcfg_pull_up>, + <4 RK_PD2 2 &pcfg_pull_up>; }; }; - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - pwm11_pin_pull_down: pwm11-pin-pull-down { + uart3 { + uart3_xfer: uart3-xfer { rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_down>; + <3 RK_PB5 4 &pcfg_pull_up>, + <3 RK_PB4 4 &pcfg_pull_up>; }; }; - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_txen */ - <1 RK_PC1 3 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <1 RK_PC3 3 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PC2 3 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <1 RK_PC4 3 &pcfg_pull_none>, - /* mac_rxd1 */ - <1 RK_PC5 3 &pcfg_pull_none>, - /* mac_rxer */ - <1 RK_PB7 3 &pcfg_pull_none>, - /* mac_rxdv */ - <1 RK_PC0 3 &pcfg_pull_none>, - /* mac_mdio */ - <1 RK_PB6 3 &pcfg_pull_none>, - /* mac_mdc */ - <1 RK_PB5 3 &pcfg_pull_none>; - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { + uart3-m1 { + uart3m1_xfer: uart3m1-xfer { rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none>; + <0 RK_PC2 3 &pcfg_pull_up>, + <0 RK_PC1 3 &pcfg_pull_up>; }; }; - gmac-m1 { - rmiim1_pins: rmiim1-pins { + uart4 { + uart4_xfer: uart4-xfer { rockchip,pins = - /* mac_txen */ - <4 RK_PB7 2 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <4 RK_PA5 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <4 RK_PA4 2 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* mac_rxd1 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* mac_rxer */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* mac_rxdv */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* mac_mdio */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* mac_mdc */ - <4 RK_PB5 2 &pcfg_pull_none>; + <4 RK_PB1 1 &pcfg_pull_up>, + <4 RK_PB0 1 &pcfg_pull_up>; }; - macm1_refclk_12ma: macm1-refclk-12ma { + uart4_cts: uart4-cts { rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none_12ma>; + <4 RK_PA6 1 &pcfg_pull_none>; }; - macm1_refclk: macm1-refclk { + uart4_rts: uart4-rts { rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none>; + <4 RK_PA7 1 &pcfg_pull_none>; }; - }; - rtc { - rtc_32k: rtc-32k { + uart4_rts_pin: uart4-rts-pin { rockchip,pins = - <0 RK_PC3 1 &pcfg_pull_none>; + <4 RK_PA7 0 &pcfg_pull_none>; }; }; - }; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index e0c6aee58ab..d3608bd0e2b 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -130,6 +130,10 @@ bootph-all; }; +&vop { + bootph-some-ram; +}; + #ifdef CONFIG_ROCKCHIP_SPI_IMAGE &binman { simple-bin-spi { diff --git a/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi index 85ee5770add..38385621deb 100644 --- a/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi @@ -4,3 +4,10 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +&spi1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts index 931334aa3d6..d5df8939a65 100644 --- a/arch/arm/dts/rk3399-rock-pi-4a.dts +++ b/arch/arm/dts/rk3399-rock-pi-4a.dts @@ -12,3 +12,13 @@ model = "Radxa ROCK Pi 4A"; compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; }; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index 791f16b206f..793ed4ae8ae 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -6,12 +6,6 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0; }; - - rng: rng@fe388000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xfe388000 0x0 0x2000>; - status = "okay"; - }; }; &dsi_dphy0 { diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi index 4aa6ab1c848..eb18008f2fe 100644 --- a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi +++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi @@ -3,20 +3,31 @@ #include "rk356x-u-boot.dtsi" &fspi_dual_io_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &gpio0 { - bootph-all; + bootph-pre-ram; }; &i2c0 { bootph-pre-ram; }; -&rk817 { +&i2c0_xfer { + bootph-pre-ram; +}; + +&i2s1m0_mclk { + bootph-pre-ram; +}; + +&pmic_int_l { bootph-pre-ram; +}; +&rk817 { regulators { bootph-pre-ram; }; @@ -27,15 +38,13 @@ }; &sdmmc_pwren_l { - bootph-all; + bootph-pre-ram; }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; - flash@0 { bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi index 930d660868b..0e25b7e108f 100644 --- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -3,7 +3,7 @@ #include "rk356x-u-boot.dtsi" &gpio0 { - bootph-all; + bootph-pre-ram; }; &sdhci { @@ -13,11 +13,9 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; - flash@0 { bootph-pre-ram; + bootph-some-ram; }; }; @@ -34,5 +32,5 @@ }; &vcc_sd_h { - bootph-all; + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi index c235b4357f7..f2c9d8e167d 100644 --- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -9,11 +9,9 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; - flash@0 { bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3568-generic-u-boot.dtsi b/arch/arm/dts/rk3568-generic-u-boot.dtsi index 6e8307e3bdf..fd7f5367b75 100644 --- a/arch/arm/dts/rk3568-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3568-generic-u-boot.dtsi @@ -1,3 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk356x-u-boot.dtsi" + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3568-generic.dts b/arch/arm/dts/rk3568-generic.dts index 88eb1bfd2aa..085a09268e8 100644 --- a/arch/arm/dts/rk3568-generic.dts +++ b/arch/arm/dts/rk3568-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3566/RK3568 with eMMC and SD-card enabled + * Minimal generic DT for RK3566/RK3568 with eMMC, SD-card, SPI flash and USB OTG enabled */ /dts-v1/; @@ -12,7 +12,7 @@ aliases { mmc0 = &sdhci; - mmc1 = &sdmmc; + mmc1 = &sdmmc0; }; chosen { @@ -28,7 +28,7 @@ no-sdio; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; status = "okay"; }; @@ -39,10 +39,39 @@ no-mmc; no-sdio; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; status = "okay"; }; +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + &uart2 { status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "peripheral"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi index 1fc71faa9e0..d8a6dd87510 100644 --- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi @@ -3,7 +3,8 @@ #include "rk356x-u-boot.dtsi" &fspi_dual_io_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdhci { @@ -15,10 +16,8 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; - flash@0 { bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 5b823fcca5f..9d18f5d0b36 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -26,16 +26,15 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; #address-cells = <1>; #size-cells = <0>; status = "okay"; flash@0 { - bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0>; + bootph-pre-ram; + bootph-some-ram; spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index d347080577d..0a0943b462a 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -21,6 +21,11 @@ bootph-all; }; + rng: rng@fe388000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xfe388000 0x0 0x2000>; + }; + otp: nvmem@fe38c000 { compatible = "rockchip,rk3568-otp"; reg = <0x0 0xfe38c000 0x0 0x4000>; @@ -33,119 +38,134 @@ }; }; -&xin24m { - bootph-all; +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; }; +#endif &cru { bootph-all; }; -&pmucru { - bootph-all; +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; }; -&grf { - bootph-all; +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; }; -&pmugrf { - bootph-all; +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; }; -&pinctrl { - bootph-all; +&emmc_datastrobe { + bootph-pre-ram; + bootph-some-ram; }; -&pcfg_pull_none_smt { - bootph-all; +&emmc_rstnout { + bootph-pre-ram; + bootph-some-ram; }; -&pcfg_pull_none { - bootph-all; +&fspi_pins { + bootph-pre-ram; + bootph-some-ram; }; -&pcfg_pull_up_drv_level_2 { +&grf { bootph-all; }; -&pcfg_pull_up { +&pcfg_pull_none { bootph-all; }; -&emmc_bus8 { - bootph-all; +&pcfg_pull_none_smt { + bootph-pre-ram; + bootph-some-ram; }; -&emmc_clk { +&pcfg_pull_up { bootph-all; }; -&emmc_cmd { - bootph-all; +&pcfg_pull_up_drv_level_2 { + bootph-pre-ram; + bootph-some-ram; }; -&emmc_datastrobe { +&pinctrl { bootph-all; }; -&emmc_rstnout { +&pmucru { bootph-all; }; -&fspi_pins { +&pmugrf { bootph-all; }; -&i2c0_xfer { - bootph-all; +&sdhci { + bootph-pre-ram; + bootph-some-ram; + max-frequency = <200000000>; +}; + +&sdmmc0 { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_bus4 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_clk { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_cmd { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_det { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_pwren { - bootph-all; -}; - -&uart2m0_xfer { - bootph-all; -}; - -&sdhci { bootph-pre-ram; - max-frequency = <200000000>; + bootph-some-ram; }; -&sdmmc0 { - bootph-pre-ram; +&sfc { + u-boot,spl-sfc-no-dma; }; &uart2 { - bootph-pre-ram; + bootph-all; clock-frequency = <24000000>; }; -#ifdef CONFIG_ROCKCHIP_SPI_IMAGE -&binman { - simple-bin-spi { - mkimage { - args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; - offset = <0x8000>; - }; - }; +&uart2m0_xfer { + bootph-all; +}; + +&xin24m { + bootph-all; }; -#endif diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi index ed15b14ea0e..f0ef0164664 100644 --- a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi @@ -3,7 +3,8 @@ #include "rk3588-u-boot.dtsi" &fspim2_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdhci { @@ -12,16 +13,15 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim2_pins>; status = "okay"; flash@0 { - bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0>; + bootph-pre-ram; + bootph-some-ram; spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index 853ed58cfe5..225dfa0b682 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -1,3 +1,25 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3588s-u-boot.dtsi" + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index e4721d97a87..95d757676f1 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled + * Minimal generic DT for RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled */ /dts-v1/; @@ -40,5 +40,6 @@ }; &uart2 { + pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi index 60494bb8485..968385622fa 100644 --- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi +++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi @@ -7,12 +7,11 @@ #include "rk3588-u-boot.dtsi" &fspim1_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim1_pins>; #address-cells = <1>; @@ -20,9 +19,10 @@ status = "okay"; flash@0 { - bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0>; + bootph-pre-ram; + bootph-some-ram; spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi index 5d5fa6ffb21..1ab31a4ec5a 100644 --- a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi @@ -3,7 +3,8 @@ #include "rk3588-u-boot.dtsi" &fspim1_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdhci { @@ -12,10 +13,8 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; - flash@0 { bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 9ee9dd051e3..d6020ca790f 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -18,7 +18,8 @@ }; &fspim2_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &pinctrl { @@ -35,16 +36,15 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim2_pins>; status = "okay"; flash@0 { - bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0>; + bootph-pre-ram; + bootph-some-ram; spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi index ca2a684f354..a50bcc45f21 100644 --- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi @@ -12,6 +12,10 @@ }; &uart9 { - bootph-pre-ram; + bootph-all; clock-frequency = <24000000>; }; + +&uart9m0_xfer { + bootph-all; +}; diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi index 6e4b97028d7..f51d7f30d78 100644 --- a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi @@ -3,7 +3,8 @@ #include "rk3588s-u-boot.dtsi" &fspim2_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdhci { @@ -12,16 +13,15 @@ }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim2_pins>; status = "okay"; flash@0 { - bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0>; + bootph-pre-ram; + bootph-some-ram; spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi index 888d1b9c12d..12a92c0cba1 100644 --- a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi @@ -9,14 +9,13 @@ }; &fspim0_pins { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sfc { - bootph-pre-ram; - u-boot,spl-sfc-no-dma; - flash@0 { bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index ac67c777ade..d3c257983ec 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -41,6 +41,17 @@ status = "disabled"; }; + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + usbdpphy0_grf: syscon@fd5c8000 { compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; reg = <0x0 0xfd5c8000 0x0 0x4000>; @@ -72,26 +83,9 @@ }; }; - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; - status = "disabled"; }; usbdp_phy0: phy@fed80000 { @@ -126,35 +120,55 @@ }; }; -&emmc_bus8 { +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; +}; +#endif + +&cru { bootph-all; }; +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + &emmc_clk { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &emmc_cmd { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &emmc_data_strobe { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &emmc_rstnout { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; -&pinctrl { +&ioc { bootph-all; }; -&pcfg_pull_none { +&pcfg_pull_down { bootph-all; }; -&pcfg_pull_up_drv_level_2 { +&pcfg_pull_none { bootph-all; }; @@ -162,16 +176,17 @@ bootph-all; }; -&xin24m { - bootph-all; +&pcfg_pull_up_drv_level_2 { + bootph-pre-ram; + bootph-some-ram; }; -&cru { - bootph-pre-ram; +&php_grf { + bootph-all; }; -&sys_grf { - bootph-pre-ram; +&pinctrl { + bootph-all; }; &pmu1grf { @@ -180,42 +195,56 @@ &scmi { bootph-pre-ram; + bootph-some-ram; }; &scmi_clk { bootph-pre-ram; + bootph-some-ram; }; -&sdmmc { +&sdhci { bootph-pre-ram; bootph-some-ram; u-boot,spl-fifo-mode; }; -&sdhci { +&sdmmc { bootph-pre-ram; bootph-some-ram; u-boot,spl-fifo-mode; }; &sdmmc_bus4 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + u-boot,spl-sfc-no-dma; +}; + +&sys_grf { bootph-all; }; &uart2 { - bootph-pre-ram; + bootph-all; clock-frequency = <24000000>; }; @@ -223,17 +252,6 @@ bootph-all; }; -&ioc { - bootph-pre-ram; -}; - -#ifdef CONFIG_ROCKCHIP_SPI_IMAGE -&binman { - simple-bin-spi { - mkimage { - args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; - offset = <0x8000>; - }; - }; +&xin24m { + bootph-all; }; -#endif diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi index 906f9faa545..9e4533e603c 100644 --- a/arch/arm/dts/sdm845-db845c-u-boot.dtsi +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi @@ -7,3 +7,10 @@ &pcie0_3p3v_dual { regulator-always-on; }; + +&sdhc_2 { + /* Remove the unsupported rpmhcc xo clock reference */ + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; +}; diff --git a/arch/arm/dts/sdm845-db845c.dts b/arch/arm/dts/sdm845-db845c.dts deleted file mode 100644 index c7eba6c491b..00000000000 --- a/arch/arm/dts/sdm845-db845c.dts +++ /dev/null @@ -1,1190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019, Linaro Ltd. - */ - -/dts-v1/; - -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/regulator/qcom,rpmh-regulator.h> -#include <dt-bindings/sound/qcom,q6afe.h> -#include <dt-bindings/sound/qcom,q6asm.h> -#include "sdm845.dtsi" -#include "sdm845-wcd9340.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" - -/ { - model = "Thundercomm Dragonboard 845c"; - compatible = "thundercomm,db845c", "qcom,sdm845"; - qcom,msm-id = <341 0x20001>; - qcom,board-id = <8 0>; - - aliases { - serial0 = &uart9; - serial1 = &uart6; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* Fixed crystal oscillator dedicated to MCP2517FD */ - clk40M: can-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - }; - - dc12v: dc12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "DC12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&vol_up_pin_a>; - - key-vol-up { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "green:user4"; - function = LED_FUNCTION_INDICATOR; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "panic-indicator"; - default-state = "off"; - }; - - led-1 { - label = "yellow:wlan"; - function = LED_FUNCTION_WLAN; - color = <LED_COLOR_ID_YELLOW>; - gpios = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led-2 { - label = "blue:bt"; - function = LED_FUNCTION_BLUETOOTH; - color = <LED_COLOR_ID_BLUE>; - gpios = <&pm8998_gpios 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <<9611_out>; - }; - }; - }; - - reserved-memory { - /* Cont splash region set up by the bootloader */ - cont_splash_mem: framebuffer@9d400000 { - reg = <0x0 0x9d400000 0x0 0x2400000>; - no-map; - }; - }; - - lt9611_1v8: lt9611-vdd18-regulator { - compatible = "regulator-fixed"; - regulator-name = "LT9611_1V8"; - - vin-supply = <&vdc_5v>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lt9611_3v3: lt9611-3v3 { - compatible = "regulator-fixed"; - regulator-name = "LT9611_3V3"; - - vin-supply = <&vdc_3v3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* - * TODO: make it possible to drive same GPIO from two clients - * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - }; - - pcie0_1p05v: pcie-0-1p05v-regulator { - compatible = "regulator-fixed"; - regulator-name = "PCIE0_1.05V"; - - vin-supply = <&vbat>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - /* - * TODO: make it possible to drive same GPIO from two clients - * gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - }; - - cam0_dvdd_1v2: cam0-dvdd-1v2-regulator { - compatible = "regulator-fixed"; - regulator-name = "CAM0_DVDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - enable-active-high; - gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cam0_dvdd_1v2_en_default>; - vin-supply = <&vbat>; - }; - - cam0_avdd_2v8: cam0-avdd-2v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "CAM0_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&pm8998_gpios 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cam0_avdd_2v8_en_default>; - vin-supply = <&vbat>; - }; - - /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ - cam3_avdd_2v8: cam3-avdd-2v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "CAM3_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vbat>; - }; - - pcie0_3p3v_dual: vldo-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VLDO_3V3"; - - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pwren_state>; - }; - - v5p0_hdmiout: v5p0-hdmiout-regulator { - compatible = "regulator-fixed"; - regulator-name = "V5P0_HDMIOUT"; - - vin-supply = <&vdc_5v>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <500000>; - - /* - * TODO: make it possible to drive same GPIO from two clients - * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - }; - - vbat: vbat-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vbat_som: vbat-som-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vdc_3v3: vdc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdc_5v: vdc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_5V"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <500000>; - regulator-always-on; - }; - - vreg_s4a_1p8: vreg-s4a-1p8 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - - vin-supply = <&vbat_som>; - }; -}; - -&adsp_pas { - status = "okay"; - - firmware-name = "qcom/sdm845/adsp.mbn"; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - vdd-s13-supply = <&vph_pwr>; - vdd-l1-l27-supply = <&vreg_s7a_1p025>; - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l3-l11-supply = <&vreg_s7a_1p025>; - vdd-l4-l5-supply = <&vreg_s7a_1p025>; - vdd-l6-supply = <&vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l9-supply = <&vreg_bob>; - vdd-l10-l23-l25-supply = <&vreg_bob>; - vdd-l13-l19-l21-supply = <&vreg_bob>; - vdd-l16-l28-supply = <&vreg_bob>; - vdd-l18-l22-supply = <&vreg_bob>; - vdd-l20-l24-supply = <&vreg_bob>; - vdd-l26-supply = <&vreg_s3a_1p35>; - vin-lvs-1-2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7a_1p025: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - - regulators-1 { - compatible = "qcom,pmi8998-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; - regulator-allow-bypass; - }; - }; -}; - -&camss { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&cdsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mbn"; -}; - -&gcc { - protected-clocks = <GCC_QSPI_CORE_CLK>, - <GCC_QSPI_CORE_CLK_SRC>, - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <GCC_LPASS_Q6_AXI_CLK>, - <GCC_LPASS_SWAY_CLK>; -}; - -&gmu { - status = "okay"; -}; - -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpu { - status = "okay"; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&i2c10 { - status = "okay"; - clock-frequency = <400000>; - - lt9611_codec: hdmi-bridge@3b { - compatible = "lontium,lt9611"; - reg = <0x3b>; - #sound-dai-cells = <1>; - - interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>; - - reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; - - vdd-supply = <<9611_1v8>; - vcc-supply = <<9611_3v3>; - - pinctrl-names = "default"; - pinctrl-0 = <<9611_irq_pin>, <&dsi_sw_sel>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lt9611_a: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - - lt9611_b: endpoint { - remote-endpoint = <&mdss_dsi1_out>; - }; - }; - - port@2 { - reg = <2>; - - lt9611_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&i2c11 { - /* On Low speed expansion */ - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c14 { - /* On Low speed expansion */ - clock-frequency = <100000>; - status = "okay"; -}; - -&mdss { - memory-region = <&cont_splash_mem>; - status = "okay"; -}; - -&mdss_dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - qcom,dual-dsi-mode; - qcom,master-dsi; - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&mdss_dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - -&mdss_dsi1 { - vdda-supply = <&vreg_l26a_1p2>; - - qcom,dual-dsi-mode; - - /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; - - status = "okay"; - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_b>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&mdss_dsi1_phy { - vdds-supply = <&vreg_l1a_0p875>; - status = "okay"; -}; - -&mss_pil { - status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; -}; - -&pcie0 { - status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; - - vddpe-3v3-supply = <&pcie0_3p3v_dual>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; -}; - -&pcie0_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&pcie1 { - status = "okay"; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; -}; - -&pcie1_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&pm8998_gpios { - gpio-line-names = - "NC", - "NC", - "WLAN_SW_CTRL", - "NC", - "PM_GPIO5_BLUE_BT_LED", - "VOL_UP_N", - "NC", - "ADC_IN1", - "PM_GPIO9_YEL_WIFI_LED", - "CAM0_AVDD_EN", - "NC", - "CAM0_DVDD_EN", - "PM_GPIO13_GREEN_U4_LED", - "DIV_CLK2", - "NC", - "NC", - "NC", - "SMB_STAT", - "NC", - "NC", - "ADC_IN2", - "OPTION1", - "WCSS_PWR_REQ", - "PM845_GPIO24", - "OPTION2", - "PM845_SLB"; - - cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state { - pins = "gpio12"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; - }; - - cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { - pins = "gpio10"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; - }; - - vol_up_pin_a: vol-up-active-state { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; - }; -}; - -&pm8998_resin { - linux,code = <KEY_VOLUMEDOWN>; - status = "okay"; -}; - -&pmi8998_lpg { - status = "okay"; - - qcom,power-source = <1>; - - led@3 { - reg = <3>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <3>; - - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led@4 { - reg = <4>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led@5 { - reg = <5>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; -}; - -/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ -&q6afedai { - dai@22 { - reg = <QUATERNARY_MI2S_RX>; - qcom,sd-lines = <0 1 2 3>; - }; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - }; - - dai@1 { - reg = <1>; - }; - - dai@2 { - reg = <2>; - }; - - dai@3 { - reg = <3>; - direction = <2>; - is-compress-dai; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - bus-width = <4>; - cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; -}; - -&sound { - compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; - pinctrl-0 = <&quat_mi2s_active - &quat_mi2s_sd0_active - &quat_mi2s_sd1_active - &quat_mi2s_sd2_active - &quat_mi2s_sd3_active>; - pinctrl-names = "default"; - model = "DB845c"; - audio-routing = - "RX_BIAS", "MCLK", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "DMIC0", "MIC BIAS1", - "DMIC1", "MIC BIAS1", - "DMIC2", "MIC BIAS3", - "DMIC3", "MIC BIAS3", - "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MM_DL4", "MultiMedia4 Playback", - "MultiMedia3 Capture", "MM_UL3"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - mm4-dai-link { - link-name = "MultiMedia4"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI Playback"; - cpu { - sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <<9611_codec 0>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9340 1>; - }; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - - can@0 { - compatible = "microchip,mcp2517fd"; - reg = <0>; - clocks = <&clk40M>; - interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <10000000>; - vdd-supply = <&vdc_5v>; - xceiver-supply = <&vdc_5v>; - }; -}; - -&spi2 { - /* On Low speed expansion */ - status = "okay"; -}; - -&tlmm { - cam0_default: cam0-default-state { - rst-pins { - pins = "gpio9"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - - mclk0-pins { - pins = "gpio13"; - function = "cam_mclk"; - - drive-strength = <16>; - bias-disable; - }; - }; - - cam3_default: cam3-default-state { - rst-pins { - function = "gpio"; - pins = "gpio21"; - - drive-strength = <16>; - bias-disable; - }; - - mclk3-pins { - function = "cam_mclk"; - pins = "gpio16"; - - drive-strength = <16>; - bias-disable; - }; - }; - - dsi_sw_sel: dsi-sw-sel-state { - pins = "gpio120"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-high; - }; - - lt9611_irq_pin: lt9611-irq-state { - pins = "gpio84"; - function = "gpio"; - bias-disable; - }; - - pcie0_default_state: pcie0-default-state { - clkreq-pins { - pins = "gpio36"; - function = "pci_e0"; - bias-pull-up; - }; - - reset-n-pins { - pins = "gpio35"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n-pins { - pins = "gpio37"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_pwren_state: pcie0-pwren-state { - pins = "gpio90"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - pcie1_default_state: pcie1-default-state { - perst-n-pins { - pins = "gpio102"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - - clkreq-pins { - pins = "gpio103"; - function = "pci_e1"; - bias-pull-up; - }; - - wake-n-pins { - pins = "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - - reset-n-pins { - pins = "gpio75"; - function = "gpio"; - - drive-strength = <16>; - bias-pull-up; - output-high; - }; - }; - - sdc2_default_state: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; - - cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_card_det_n: sd-card-det-n-state { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; -}; - -&uart3 { - label = "LS-UART0"; - pinctrl-0 = <&qup_uart3_4pin>; - - status = "disabled"; -}; - -&uart6 { - status = "okay"; - - pinctrl-0 = <&qup_uart6_4pin>; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&uart9 { - label = "LS-UART1"; - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; - qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; - qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <800000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&venus { - status = "okay"; -}; - -&wcd9340 { - reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - - swm: swm@c85 { - left_spkr: speaker@0,1 { - compatible = "sdw10217201000"; - reg = <0 1>; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; - - right_spkr: speaker@0,2 { - compatible = "sdw10217201000"; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; - reg = <0 2>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; - }; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - - qcom,snoc-host-cap-8bit-quirk; - qcom,ath10k-calibration-variant = "Thundercomm_DB845C"; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ -&qup_spi2_default { - drive-strength = <16>; -}; - -&qup_i2c10_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart9_rx { - drive-strength = <2>; - bias-pull-up; -}; - -&qup_uart9_tx { - drive-strength = <2>; - bias-disable; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ -&qup_spi0_default { - drive-strength = <6>; - bias-disable; -}; diff --git a/arch/arm/dts/sdm845-samsung-starqltechn.dts b/arch/arm/dts/sdm845-samsung-starqltechn.dts deleted file mode 100644 index d37a433130b..00000000000 --- a/arch/arm/dts/sdm845-samsung-starqltechn.dts +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/regulator/qcom,rpmh-regulator.h> -#include "sdm845.dtsi" - -/ { - chassis-type = "handset"; - model = "Samsung Galaxy S9 SM-G9600"; - compatible = "samsung,starqltechn", "qcom,sdm845"; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - framebuffer: framebuffer@9d400000 { - compatible = "simple-framebuffer"; - reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000 - width = <1440>; - height = <2960>; - stride = <(1440 * 4)>; - format = "a8r8g8b8"; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - vreg_s4a_1p8: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - reserved-memory { - memory@9d400000 { - reg = <0x0 0x9d400000 0x0 0x02400000>; - no-map; - }; - - memory@a1300000 { - compatible = "ramoops"; - reg = <0x0 0xa1300000 0x0 0x100000>; - record-size = <0x40000>; - console-size = <0x40000>; - ftrace-size = <0x40000>; - pmsg-size = <0x40000>; - }; - }; -}; - - -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - vdd-s13-supply = <&vph_pwr>; - vdd-l1-l27-supply = <&vreg_s7a_1p025>; - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l3-l11-supply = <&vreg_s7a_1p025>; - vdd-l4-l5-supply = <&vreg_s7a_1p025>; - vdd-l6-supply = <&vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l26-supply = <&vreg_s3a_1p35>; - vin-lvs-1-2-supply = <&vreg_s4a_1p8>; - - vreg_s2a_1p125: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7a_1p025: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vddpx_10: - vreg_l2a_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-always-on; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vddpx_13: - vreg_l6a_1p8: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l8a_1p2: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l9a_1p8: ldo9 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l11a_1p0: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vddpx_2: - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l14a_1p88: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l18a_2p7: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l19a_3p0: ldo19 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l22a_2p85: ldo22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l23a_3p3: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdda_qusb_hs0_3p1: - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l28a_3p0: ldo28 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - regulators-1 { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - - vreg_s3c_0p6: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -&gcc { - protected-clocks = <GCC_QSPI_CORE_CLK>, - <GCC_QSPI_CORE_CLK_SRC>, - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <GCC_LPASS_Q6_AXI_CLK>, - <GCC_LPASS_SWAY_CLK>; -}; - -&i2c10 { - clock-frequency = <400000>; - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <600000>; - status = "okay"; -}; - -&ufs_mem_phy { - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; - status = "okay"; -}; - -&sdhc_2 { - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>; - cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vddpx_2>; - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - /* Until we have Type C hooked up we'll force this as peripheral. */ - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; - qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; - qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; - status = "okay"; -}; - -&usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; - status = "okay"; -}; - -&wifi { - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>; - - sdc2_clk_state: sdc2-clk-state { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; - - sdc2_cmd_state: sdc2-cmd-state { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - - sdc2_data_state: sdc2-data-state { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - - sd_card_det_n_state: sd-card-det-n-state { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; -}; diff --git a/arch/arm/dts/sdm845-wcd9340.dtsi b/arch/arm/dts/sdm845-wcd9340.dtsi deleted file mode 100644 index c15d4886064..00000000000 --- a/arch/arm/dts/sdm845-wcd9340.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 SoC device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -&slim { - status = "okay"; - - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - wcd9340_ifd: ifd@0,0 { - compatible = "slim217,250"; - reg = <0 0>; - }; - - wcd9340: codec@1,0 { - compatible = "slim217,250"; - reg = <1 0>; - slim-ifc-dev = <&wcd9340_ifd>; - - #sound-dai-cells = <1>; - - interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - - #address-cells = <1>; - #size-cells = <1>; - - wcdgpio: gpio-controller@42 { - compatible = "qcom,wcd9340-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42 0x2>; - }; - - swm: swm@c85 { - compatible = "qcom,soundwire-v1.3.0"; - reg = <0xc85 0x40>; - interrupts-extended = <&wcd9340 20>; - - qcom,dout-ports = <6>; - qcom,din-ports = <2>; - qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>; - - #sound-dai-cells = <1>; - clocks = <&wcd9340>; - clock-names = "iface"; - #address-cells = <2>; - #size-cells = <0>; - }; - }; - }; -}; - -&tlmm { - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - bias-pull-down; - drive-strength = <2>; - }; -}; diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi deleted file mode 100644 index bf5e6eb9d31..00000000000 --- a/arch/arm/dts/sdm845.dtsi +++ /dev/null @@ -1,5752 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 SoC device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#include <dt-bindings/clock/qcom,camcc-sdm845.h> -#include <dt-bindings/clock/qcom,dispcc-sdm845.h> -#include <dt-bindings/clock/qcom,gcc-sdm845.h> -#include <dt-bindings/clock/qcom,gpucc-sdm845.h> -#include <dt-bindings/clock/qcom,lpass-sdm845.h> -#include <dt-bindings/clock/qcom,rpmh.h> -#include <dt-bindings/clock/qcom,videocc-sdm845.h> -#include <dt-bindings/dma/qcom-gpi.h> -#include <dt-bindings/firmware/qcom,scm.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interconnect/qcom,osm-l3.h> -#include <dt-bindings/interconnect/qcom,sdm845.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/phy/phy-qcom-qmp.h> -#include <dt-bindings/phy/phy-qcom-qusb2.h> -#include <dt-bindings/power/qcom-rpmpd.h> -#include <dt-bindings/reset/qcom,sdm845-aoss.h> -#include <dt-bindings/reset/qcom,sdm845-pdc.h> -#include <dt-bindings/soc/qcom,apr.h> -#include <dt-bindings/soc/qcom,rpmh-rsc.h> -#include <dt-bindings/clock/qcom,gcc-sdm845.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - spi5 = &spi5; - spi6 = &spi6; - spi7 = &spi7; - spi8 = &spi8; - spi9 = &spi9; - spi10 = &spi10; - spi11 = &spi11; - spi12 = &spi12; - spi13 = &spi13; - spi14 = &spi14; - spi15 = &spi15; - }; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - }; - - cpus: cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - clocks = <&cpufreq_hw 0>; - enable-method = "psci"; - capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <154>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - clocks = <&cpufreq_hw 0>; - enable-method = "psci"; - capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <154>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_100>; - L2_100: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - clocks = <&cpufreq_hw 0>; - enable-method = "psci"; - capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <154>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_200>; - L2_200: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - clocks = <&cpufreq_hw 0>; - enable-method = "psci"; - capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <154>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - next-level-cache = <&L2_300>; - L2_300: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - clocks = <&cpufreq_hw 1>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <442>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_400>; - L2_400: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - clocks = <&cpufreq_hw 1>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <442>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_500>; - L2_500: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - clocks = <&cpufreq_hw 1>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <442>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_600>; - L2_600: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - clocks = <&cpufreq_hw 1>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <442>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - #cooling-cells = <2>; - next-level-cache = <&L2_700>; - L2_700: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - cpu_idle_states: idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <350>; - exit-latency-us = <461>; - min-residency-us = <1890>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <264>; - exit-latency-us = <621>; - min-residency-us = <952>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x4100c244>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-sdm845", "qcom,scm"; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - cpu0_opp_table: opp-table-cpu0 { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu0_opp3: opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-peak-kBps = <800000 6451200>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 6451200>; - }; - - cpu0_opp5: opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <800000 7680000>; - }; - - cpu0_opp6: opp-748800000 { - opp-hz = /bits/ 64 <748800000>; - opp-peak-kBps = <1804000 9216000>; - }; - - cpu0_opp7: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <1804000 9216000>; - }; - - cpu0_opp8: opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-peak-kBps = <1804000 10444800>; - }; - - cpu0_opp9: opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <1804000 11980800>; - }; - - cpu0_opp10: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <1804000 11980800>; - }; - - cpu0_opp11: opp-1132800000 { - opp-hz = /bits/ 64 <1132800000>; - opp-peak-kBps = <2188000 13516800>; - }; - - cpu0_opp12: opp-1228800000 { - opp-hz = /bits/ 64 <1228800000>; - opp-peak-kBps = <2188000 15052800>; - }; - - cpu0_opp13: opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <2188000 16588800>; - }; - - cpu0_opp14: opp-1420800000 { - opp-hz = /bits/ 64 <1420800000>; - opp-peak-kBps = <3072000 18124800>; - }; - - cpu0_opp15: opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <3072000 19353600>; - }; - - cpu0_opp16: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 19353600>; - }; - - cpu0_opp17: opp-1689600000 { - opp-hz = /bits/ 64 <1689600000>; - opp-peak-kBps = <4068000 20889600>; - }; - - cpu0_opp18: opp-1766400000 { - opp-hz = /bits/ 64 <1766400000>; - opp-peak-kBps = <4068000 22425600>; - }; - }; - - cpu4_opp_table: opp-table-cpu4 { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu4_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu4_opp3: opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp5: opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp6: opp-748800000 { - opp-hz = /bits/ 64 <748800000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp7: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 9216000>; - }; - - cpu4_opp8: opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-peak-kBps = <2188000 9216000>; - }; - - cpu4_opp9: opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <2188000 9216000>; - }; - - cpu4_opp10: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 9216000>; - }; - - cpu4_opp11: opp-1132800000 { - opp-hz = /bits/ 64 <1132800000>; - opp-peak-kBps = <3072000 11980800>; - }; - - cpu4_opp12: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <4068000 11980800>; - }; - - cpu4_opp13: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 11980800>; - }; - - cpu4_opp14: opp-1363200000 { - opp-hz = /bits/ 64 <1363200000>; - opp-peak-kBps = <4068000 15052800>; - }; - - cpu4_opp15: opp-1459200000 { - opp-hz = /bits/ 64 <1459200000>; - opp-peak-kBps = <4068000 15052800>; - }; - - cpu4_opp16: opp-1536000000 { - opp-hz = /bits/ 64 <1536000000>; - opp-peak-kBps = <5412000 15052800>; - }; - - cpu4_opp17: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <5412000 15052800>; - }; - - cpu4_opp18: opp-1689600000 { - opp-hz = /bits/ 64 <1689600000>; - opp-peak-kBps = <5412000 19353600>; - }; - - cpu4_opp19: opp-1766400000 { - opp-hz = /bits/ 64 <1766400000>; - opp-peak-kBps = <6220000 19353600>; - }; - - cpu4_opp20: opp-1843200000 { - opp-hz = /bits/ 64 <1843200000>; - opp-peak-kBps = <6220000 19353600>; - }; - - cpu4_opp21: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <7216000 19353600>; - }; - - cpu4_opp22: opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp23: opp-2092800000 { - opp-hz = /bits/ 64 <2092800000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp24: opp-2169600000 { - opp-hz = /bits/ 64 <2169600000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp25: opp-2246400000 { - opp-hz = /bits/ 64 <2246400000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp26: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp27: opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp28: opp-2476800000 { - opp-hz = /bits/ 64 <2476800000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp29: opp-2553600000 { - opp-hz = /bits/ 64 <2553600000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp30: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp31: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <7216000 25497600>; - }; - - cpu4_opp32: opp-2803200000 { - opp-hz = /bits/ 64 <2803200000>; - opp-peak-kBps = <7216000 25497600>; - }; - }; - - dsi_opp_table: opp-table-dsi { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-328580000 { - opp-hz = /bits/ 64 <328580000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - qspi_opp_table: opp-table-qspi { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - qup_opp_table: opp-table-qup { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: power-domain-cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: power-domain-cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: power-domain-cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: power-domain-cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: power-domain-cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: power-domain-cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: power-domain-cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: power-domain-cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: power-domain-cluster { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp-mem@85700000 { - reg = <0 0x85700000 0 0x600000>; - no-map; - }; - - xbl_mem: xbl-mem@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - aop_mem: aop-mem@85fc0000 { - reg = <0 0x85fc0000 0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85fe0000 0 0x20000>; - no-map; - }; - - smem@86000000 { - compatible = "qcom,smem"; - reg = <0x0 0x86000000 0 0x200000>; - no-map; - hwlocks = <&tcsr_mutex 3>; - }; - - tz_mem: tz@86200000 { - reg = <0 0x86200000 0 0x2d00000>; - no-map; - }; - - rmtfs_mem: rmtfs@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0 0x88f00000 0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; - }; - - qseecom_mem: qseecom@8ab00000 { - reg = <0 0x8ab00000 0 0x1400000>; - no-map; - }; - - camera_mem: camera-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x500000>; - no-map; - }; - - ipa_fw_mem: ipa-fw@8c400000 { - reg = <0 0x8c400000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: ipa-gsi@8c410000 { - reg = <0 0x8c410000 0 0x5000>; - no-map; - }; - - gpu_mem: gpu@8c415000 { - reg = <0 0x8c415000 0 0x2000>; - no-map; - }; - - adsp_mem: adsp@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - - wlan_msa_mem: wlan-msa@8df00000 { - reg = <0 0x8df00000 0 0x100000>; - no-map; - }; - - mpss_region: mpss@8e000000 { - reg = <0 0x8e000000 0 0x7800000>; - no-map; - }; - - venus_mem: venus@95800000 { - reg = <0 0x95800000 0 0x500000>; - no-map; - }; - - cdsp_mem: cdsp@95d00000 { - reg = <0 0x95d00000 0 0x800000>; - no-map; - }; - - mba_region: mba@96500000 { - reg = <0 0x96500000 0 0x200000>; - no-map; - }; - - slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0x1400000>; - no-map; - }; - - spss_mem: spss@97b00000 { - reg = <0 0x97b00000 0 0x100000>; - no-map; - }; - - mdata_mem: mpss-metadata { - alloc-ranges = <0 0xa0000000 0 0x20000000>; - size = <0 0x4000>; - no-map; - }; - - fastrpc_mem: fastrpc { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - reusable; - }; - }; - - adsp_pas: remoteproc-adsp { - compatible = "qcom,sdm845-adsp-pas"; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - apr { - compatible = "qcom,apr-v2"; - qcom,glink-channels = "apr_audio_svc"; - qcom,domain = <APR_DOMAIN_ADSP>; - #address-cells = <1>; - #size-cells = <0>; - qcom,intents = <512 20>; - - service@3 { - reg = <APR_SVC_ADSP_CORE>; - compatible = "qcom,q6core"; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - }; - - q6afe: service@4 { - compatible = "qcom,q6afe"; - reg = <APR_SVC_AFE>; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6afedai: dais { - compatible = "qcom,q6afe-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - }; - }; - - q6asm: service@7 { - compatible = "qcom,q6asm"; - reg = <APR_SVC_ASM>; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - iommus = <&apps_smmu 0x1821 0x0>; - }; - }; - - q6adm: service@8 { - compatible = "qcom,q6adm"; - reg = <APR_SVC_ADM>; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; - }; - }; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1823 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1824 0x0>; - }; - }; - }; - }; - - cdsp_pas: remoteproc-cdsp { - compatible = "qcom,sdm845-cdsp-pas"; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; - label = "turing"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x30>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x1402 0x30>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1403 0x30>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1404 0x30>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1405 0x30>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x1406 0x30>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x1407 0x30>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x1408 0x30>; - }; - }; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apss_shared 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apss_shared 26>; - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0 0x00100000 0 0x1f0000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>, - <&pcie0_phy>, - <&pcie1_phy>; - clock-names = "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - power-domains = <&rpmhpd SDM845_CX>; - }; - - qfprom@784000 { - compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx-trim-primary@1eb { - reg = <0x1eb 0x1>; - bits = <1 4>; - }; - - qusb2s_hstx_trim: hstx-trim-secondary@1eb { - reg = <0x1eb 0x2>; - bits = <6 4>; - }; - }; - - rng: rng@793000 { - compatible = "qcom,prng-ee"; - reg = <0 0x00793000 0 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - gpi_dma0: dma-controller@800000 { - #dma-cells = <3>; - compatible = "qcom,sdm845-gpi-dma"; - reg = <0 0x00800000 0 0x60000>; - interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x0016 0x0>; - status = "disabled"; - }; - - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x008c0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - iommus = <&apps_smmu 0x3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core"; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart0: serial@880000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart0_default>; - interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@884000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart1_default>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart2: serial@888000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default>; - interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart4: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart4_default>; - interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart5: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; - interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart6: serial@898000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, - <&gpi_dma0 1 7 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart7: serial@89c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_default>; - interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - #dma-cells = <3>; - compatible = "qcom,sdm845-gpi-dma"; - reg = <0 0x00a00000 0 0x60000>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x06d6 0x0>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x00ac0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x6c3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core"; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart8: serial@a80000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart8_default>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart9: serial@a84000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9_default>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart10: serial@a88000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart10_default>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart11: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart11_default>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart12: serial@a90000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart12_default>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi13: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart13: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart13_default>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi14: spi@a98000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart14: serial@a98000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart14_default>; - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c15: i2c@a9c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, - <&gpi_dma1 1 7 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - }; - - spi15: spi@a9c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, - <&gpi_dma1 1 7 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart15: serial@a9c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart15_default>; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - }; - - llcc: system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, - <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, - <0 0x01300000 0 0x50000>; - reg-names = "llcc0_base", "llcc1_base", "llcc2_base", - "llcc3_base", "llcc_broadcast_base"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma@10a2000 { - compatible = "qcom,sdm845-dcc", "qcom,dcc"; - reg = <0x0 0x010a2000 0x0 0x1000>, - <0x0 0x010ae000 0x0 0x2000>; - }; - - pmu@114a000 { - compatible = "qcom,sdm845-llcc-bwmon"; - reg = <0 0x0114a000 0 0x1000>; - interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; - - operating-points-v2 = <&llcc_bwmon_opp_table>; - - llcc_bwmon_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* - * The interconnect path bandwidth taken from - * cpu4_opp_table bandwidth for gladiator_noc-mem_noc - * interconnect. This also matches the - * bandwidth table of qcom,llccbw (qcom,bw-tbl, - * bus width: 4 bytes) from msm-4.9 downstream - * kernel. - */ - opp-0 { - opp-peak-kBps = <800000>; - }; - opp-1 { - opp-peak-kBps = <1804000>; - }; - opp-2 { - opp-peak-kBps = <3072000>; - }; - opp-3 { - opp-peak-kBps = <5412000>; - }; - opp-4 { - opp-peak-kBps = <7216000>; - }; - }; - }; - - pmu@1436400 { - compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; - reg = <0 0x01436400 0 0x600>; - interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; - - operating-points-v2 = <&cpu_bwmon_opp_table>; - - cpu_bwmon_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* - * The interconnect path bandwidth taken from - * cpu4_opp_table bandwidth for OSM L3 - * interconnect. This also matches the OSM L3 - * from bandwidth table of qcom,cpu4-l3lat-mon - * (qcom,core-dev-table, bus width: 16 bytes) - * from msm-4.9 downstream kernel. - */ - opp-0 { - opp-peak-kBps = <4800000>; - }; - opp-1 { - opp-peak-kBps = <9216000>; - }; - opp-2 { - opp-peak-kBps = <15052800>; - }; - opp-3 { - opp-peak-kBps = <20889600>; - }; - opp-4 { - opp-peak-kBps = <25497600>; - }; - }; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sdm845"; - reg = <0 0x01c00000 0 0x2000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60100000 0 0x100000>, - <0 0x01c07000 0 0x1000>; - reg-names = "parf", "dbi", "elbi", "config", "mhi"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; - - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "tbu"; - - iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, - <0x100 &apps_smmu 0x1c11 0x1>, - <0x200 &apps_smmu 0x1c12 0x1>, - <0x300 &apps_smmu 0x1c13 0x1>, - <0x400 &apps_smmu 0x1c14 0x1>, - <0x500 &apps_smmu 0x1c15 0x1>, - <0x600 &apps_smmu 0x1c16 0x1>, - <0x700 &apps_smmu 0x1c17 0x1>, - <0x800 &apps_smmu 0x1c18 0x1>, - <0x900 &apps_smmu 0x1c19 0x1>, - <0xa00 &apps_smmu 0x1c1a 0x1>, - <0xb00 &apps_smmu 0x1c1b 0x1>, - <0xc00 &apps_smmu 0x1c1c 0x1>, - <0xd00 &apps_smmu 0x1c1d 0x1>, - <0xe00 &apps_smmu 0x1c1e 0x1>, - <0xf00 &apps_smmu 0x1c1f 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sdm845-qmp-pcie-phy"; - reg = <0 0x01c06000 0 0x1000>; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "refgen", - "pipe"; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - - #phy-cells = <0>; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sdm845"; - reg = <0 0x01c08000 0 0x2000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40100000 0 0x100000>, - <0 0x01c0c000 0 0x1000>; - reg-names = "parf", "dbi", "elbi", "config", "mhi"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - - interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ref", - "tbu"; - - assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates = <19200000>; - - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>, - <0x200 &apps_smmu 0x1c02 0x1>, - <0x300 &apps_smmu 0x1c03 0x1>, - <0x400 &apps_smmu 0x1c04 0x1>, - <0x500 &apps_smmu 0x1c05 0x1>, - <0x600 &apps_smmu 0x1c06 0x1>, - <0x700 &apps_smmu 0x1c07 0x1>, - <0x800 &apps_smmu 0x1c08 0x1>, - <0x900 &apps_smmu 0x1c09 0x1>, - <0xa00 &apps_smmu 0x1c0a 0x1>, - <0xb00 &apps_smmu 0x1c0b 0x1>, - <0xc00 &apps_smmu 0x1c0c 0x1>, - <0xd00 &apps_smmu 0x1c0d 0x1>, - <0xe00 &apps_smmu 0x1c0e 0x1>, - <0xf00 &apps_smmu 0x1c0f 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0a000 { - compatible = "qcom,sdm845-qhp-pcie-phy"; - reg = <0 0x01c0a000 0 0x2000>; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "refgen", - "pipe"; - - clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; - - #phy-cells = <0>; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - }; - - mem_noc: interconnect@1380000 { - compatible = "qcom,sdm845-mem-noc"; - reg = <0 0x01380000 0 0x27200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - dc_noc: interconnect@14e0000 { - compatible = "qcom,sdm845-dc-noc"; - reg = <0 0x014e0000 0 0x400>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sdm845-config-noc"; - reg = <0 0x01500000 0 0x5080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sdm845-system-noc"; - reg = <0 0x01620000 0 0x18080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sdm845-aggre1-noc"; - reg = <0 0x016e0000 0 0x15080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sdm845-aggre2-noc"; - reg = <0 0x01700000 0 0x1f300>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sdm845-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sdm845-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - power-domains = <&gcc UFS_PHY_GDSC>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - iommus = <&apps_smmu 0x100 0xf>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <75000000 300000000>; - - interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sdm845-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x18c>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rpmhcc RPMH_CE_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x704 0x1>, - <&apps_smmu 0x706 0x1>, - <&apps_smmu 0x714 0x1>, - <&apps_smmu 0x716 0x1>; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,crypto-v5.4"; - reg = <0 0x01dfa000 0 0x6000>; - clocks = <&gcc GCC_CE1_AHB_CLK>, - <&gcc GCC_CE1_AXI_CLK>, - <&rpmhcc RPMH_CE_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 6>, <&cryptobam 7>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x704 0x1>, - <&apps_smmu 0x706 0x1>, - <&apps_smmu 0x714 0x1>, - <&apps_smmu 0x716 0x1>; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sdm845-ipa"; - - iommus = <&apps_smmu 0x720 0x0>, - <&apps_smmu 0x722 0x0>; - reg = <0 0x01e40000 0 0x7000>, - <0 0x01e47000 0 0x2000>, - <0 0x01e04000 0 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, - <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0 0x01f40000 0 0x20000>; - #hwlock-cells = <1>; - }; - - tcsr_regs_1: syscon@1f60000 { - compatible = "qcom,sdm845-tcsr", "syscon"; - reg = <0 0x01f60000 0 0x20000>; - }; - - tlmm: pinctrl@3400000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0 0x03400000 0 0xc00000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 151>; - wakeup-parent = <&pdc_intc>; - - cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - - bias-pull-up; - drive-strength = <2>; /* 2 mA */ - }; - - cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - }; - - cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - - bias-pull-up; - drive-strength = <2>; /* 2 mA */ - }; - - cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - }; - - qspi_clk: qspi-clk-state { - pins = "gpio95"; - function = "qspi_clk"; - }; - - qspi_cs0: qspi-cs0-state { - pins = "gpio90"; - function = "qspi_cs"; - }; - - qspi_cs1: qspi-cs1-state { - pins = "gpio89"; - function = "qspi_cs"; - }; - - qspi_data0: qspi-data0-state { - pins = "gpio91"; - function = "qspi_data"; - }; - - qspi_data1: qspi-data1-state { - pins = "gpio92"; - function = "qspi_data"; - }; - - qspi_data23: qspi-data23-state { - pins = "gpio93", "gpio94"; - function = "qspi_data"; - }; - - qup_i2c0_default: qup-i2c0-default-state { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - qup_i2c1_default: qup-i2c1-default-state { - pins = "gpio17", "gpio18"; - function = "qup1"; - }; - - qup_i2c2_default: qup-i2c2-default-state { - pins = "gpio27", "gpio28"; - function = "qup2"; - }; - - qup_i2c3_default: qup-i2c3-default-state { - pins = "gpio41", "gpio42"; - function = "qup3"; - }; - - qup_i2c4_default: qup-i2c4-default-state { - pins = "gpio89", "gpio90"; - function = "qup4"; - }; - - qup_i2c5_default: qup-i2c5-default-state { - pins = "gpio85", "gpio86"; - function = "qup5"; - }; - - qup_i2c6_default: qup-i2c6-default-state { - pins = "gpio45", "gpio46"; - function = "qup6"; - }; - - qup_i2c7_default: qup-i2c7-default-state { - pins = "gpio93", "gpio94"; - function = "qup7"; - }; - - qup_i2c8_default: qup-i2c8-default-state { - pins = "gpio65", "gpio66"; - function = "qup8"; - }; - - qup_i2c9_default: qup-i2c9-default-state { - pins = "gpio6", "gpio7"; - function = "qup9"; - }; - - qup_i2c10_default: qup-i2c10-default-state { - pins = "gpio55", "gpio56"; - function = "qup10"; - }; - - qup_i2c11_default: qup-i2c11-default-state { - pins = "gpio31", "gpio32"; - function = "qup11"; - }; - - qup_i2c12_default: qup-i2c12-default-state { - pins = "gpio49", "gpio50"; - function = "qup12"; - }; - - qup_i2c13_default: qup-i2c13-default-state { - pins = "gpio105", "gpio106"; - function = "qup13"; - }; - - qup_i2c14_default: qup-i2c14-default-state { - pins = "gpio33", "gpio34"; - function = "qup14"; - }; - - qup_i2c15_default: qup-i2c15-default-state { - pins = "gpio81", "gpio82"; - function = "qup15"; - }; - - qup_spi0_default: qup-spi0-default-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "qup0"; - }; - - qup_spi1_default: qup-spi1-default-state { - pins = "gpio17", "gpio18", "gpio19", "gpio20"; - function = "qup1"; - }; - - qup_spi2_default: qup-spi2-default-state { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - function = "qup2"; - }; - - qup_spi3_default: qup-spi3-default-state { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "qup3"; - }; - - qup_spi4_default: qup-spi4-default-state { - pins = "gpio89", "gpio90", "gpio91", "gpio92"; - function = "qup4"; - }; - - qup_spi5_default: qup-spi5-default-state { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - function = "qup5"; - }; - - qup_spi6_default: qup-spi6-default-state { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - qup_spi7_default: qup-spi7-default-state { - pins = "gpio93", "gpio94", "gpio95", "gpio96"; - function = "qup7"; - }; - - qup_spi8_default: qup-spi8-default-state { - pins = "gpio65", "gpio66", "gpio67", "gpio68"; - function = "qup8"; - }; - - qup_spi9_default: qup-spi9-default-state { - pins = "gpio6", "gpio7", "gpio4", "gpio5"; - function = "qup9"; - }; - - qup_spi10_default: qup-spi10-default-state { - pins = "gpio55", "gpio56", "gpio53", "gpio54"; - function = "qup10"; - }; - - qup_spi11_default: qup-spi11-default-state { - pins = "gpio31", "gpio32", "gpio33", "gpio34"; - function = "qup11"; - }; - - qup_spi12_default: qup-spi12-default-state { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - function = "qup12"; - }; - - qup_spi13_default: qup-spi13-default-state { - pins = "gpio105", "gpio106", "gpio107", "gpio108"; - function = "qup13"; - }; - - qup_spi14_default: qup-spi14-default-state { - pins = "gpio33", "gpio34", "gpio31", "gpio32"; - function = "qup14"; - }; - - qup_spi15_default: qup-spi15-default-state { - pins = "gpio81", "gpio82", "gpio83", "gpio84"; - function = "qup15"; - }; - - qup_uart0_default: qup-uart0-default-state { - qup_uart0_tx: tx-pins { - pins = "gpio2"; - function = "qup0"; - }; - - qup_uart0_rx: rx-pins { - pins = "gpio3"; - function = "qup0"; - }; - }; - - qup_uart1_default: qup-uart1-default-state { - qup_uart1_tx: tx-pins { - pins = "gpio19"; - function = "qup1"; - }; - - qup_uart1_rx: rx-pins { - pins = "gpio20"; - function = "qup1"; - }; - }; - - qup_uart2_default: qup-uart2-default-state { - qup_uart2_tx: tx-pins { - pins = "gpio29"; - function = "qup2"; - }; - - qup_uart2_rx: rx-pins { - pins = "gpio30"; - function = "qup2"; - }; - }; - - qup_uart3_default: qup-uart3-default-state { - qup_uart3_tx: tx-pins { - pins = "gpio43"; - function = "qup3"; - }; - - qup_uart3_rx: rx-pins { - pins = "gpio44"; - function = "qup3"; - }; - }; - - qup_uart3_4pin: qup-uart3-4pin-state { - qup_uart3_4pin_cts: cts-pins { - pins = "gpio41"; - function = "qup3"; - }; - - qup_uart3_4pin_rts_tx: rts-tx-pins { - pins = "gpio42", "gpio43"; - function = "qup3"; - }; - - qup_uart3_4pin_rx: rx-pins { - pins = "gpio44"; - function = "qup3"; - }; - }; - - qup_uart4_default: qup-uart4-default-state { - qup_uart4_tx: tx-pins { - pins = "gpio91"; - function = "qup4"; - }; - - qup_uart4_rx: rx-pins { - pins = "gpio92"; - function = "qup4"; - }; - }; - - qup_uart5_default: qup-uart5-default-state { - qup_uart5_tx: tx-pins { - pins = "gpio87"; - function = "qup5"; - }; - - qup_uart5_rx: rx-pins { - pins = "gpio88"; - function = "qup5"; - }; - }; - - qup_uart6_default: qup-uart6-default-state { - qup_uart6_tx: tx-pins { - pins = "gpio47"; - function = "qup6"; - }; - - qup_uart6_rx: rx-pins { - pins = "gpio48"; - function = "qup6"; - }; - }; - - qup_uart6_4pin: qup-uart6-4pin-state { - qup_uart6_4pin_cts: cts-pins { - pins = "gpio45"; - function = "qup6"; - bias-pull-down; - }; - - qup_uart6_4pin_rts_tx: rts-tx-pins { - pins = "gpio46", "gpio47"; - function = "qup6"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart6_4pin_rx: rx-pins { - pins = "gpio48"; - function = "qup6"; - bias-pull-up; - }; - }; - - qup_uart7_default: qup-uart7-default-state { - qup_uart7_tx: tx-pins { - pins = "gpio95"; - function = "qup7"; - }; - - qup_uart7_rx: rx-pins { - pins = "gpio96"; - function = "qup7"; - }; - }; - - qup_uart8_default: qup-uart8-default-state { - qup_uart8_tx: tx-pins { - pins = "gpio67"; - function = "qup8"; - }; - - qup_uart8_rx: rx-pins { - pins = "gpio68"; - function = "qup8"; - }; - }; - - qup_uart9_default: qup-uart9-default-state { - qup_uart9_tx: tx-pins { - pins = "gpio4"; - function = "qup9"; - }; - - qup_uart9_rx: rx-pins { - pins = "gpio5"; - function = "qup9"; - }; - }; - - qup_uart10_default: qup-uart10-default-state { - qup_uart10_tx: tx-pins { - pins = "gpio53"; - function = "qup10"; - }; - - qup_uart10_rx: rx-pins { - pins = "gpio54"; - function = "qup10"; - }; - }; - - qup_uart11_default: qup-uart11-default-state { - qup_uart11_tx: tx-pins { - pins = "gpio33"; - function = "qup11"; - }; - - qup_uart11_rx: rx-pins { - pins = "gpio34"; - function = "qup11"; - }; - }; - - qup_uart12_default: qup-uart12-default-state { - qup_uart12_tx: tx-pins { - pins = "gpio51"; - function = "qup0"; - }; - - qup_uart12_rx: rx-pins { - pins = "gpio52"; - function = "qup0"; - }; - }; - - qup_uart13_default: qup-uart13-default-state { - qup_uart13_tx: tx-pins { - pins = "gpio107"; - function = "qup13"; - }; - - qup_uart13_rx: rx-pins { - pins = "gpio108"; - function = "qup13"; - }; - }; - - qup_uart14_default: qup-uart14-default-state { - qup_uart14_tx: tx-pins { - pins = "gpio31"; - function = "qup14"; - }; - - qup_uart14_rx: rx-pins { - pins = "gpio32"; - function = "qup14"; - }; - }; - - qup_uart15_default: qup-uart15-default-state { - qup_uart15_tx: tx-pins { - pins = "gpio83"; - function = "qup15"; - }; - - qup_uart15_rx: rx-pins { - pins = "gpio84"; - function = "qup15"; - }; - }; - - quat_mi2s_sleep: quat-mi2s-sleep-state { - pins = "gpio58", "gpio59"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - quat_mi2s_active: quat-mi2s-active-state { - pins = "gpio58", "gpio59"; - function = "qua_mi2s"; - drive-strength = <8>; - bias-disable; - output-high; - }; - - quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { - pins = "gpio60"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { - pins = "gpio60"; - function = "qua_mi2s"; - drive-strength = <8>; - bias-disable; - }; - - quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { - pins = "gpio61"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { - pins = "gpio61"; - function = "qua_mi2s"; - drive-strength = <8>; - bias-disable; - }; - - quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { - pins = "gpio62"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { - pins = "gpio62"; - function = "qua_mi2s"; - drive-strength = <8>; - bias-disable; - }; - - quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { - pins = "gpio63"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { - pins = "gpio63"; - function = "qua_mi2s"; - drive-strength = <8>; - bias-disable; - }; - }; - - mss_pil: remoteproc@4080000 { - compatible = "qcom,sdm845-mss-pil"; - reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = - <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack", - "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&gcc GCC_PRNG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bus", "mem", "gpll0_mss", - "snoc_axi", "mnoc_axi", "prng", "xo"; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - - power-domains = <&rpmhpd SDM845_CX>, - <&rpmhpd SDM845_MX>, - <&rpmhpd SDM845_MSS>; - power-domain-names = "cx", "mx", "mss"; - - status = "disabled"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - metadata { - memory-region = <&mdata_mem>; - }; - - glink-edge { - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0 0x05090000 0 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - }; - - slpi_pas: remoteproc@5c00000 { - compatible = "qcom,sdm845-slpi-pas"; - reg = <0 0x5c00000 0 0x4000>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - qcom,qmp = <&aoss_qmp>; - - power-domains = <&rpmhpd SDM845_CX>, - <&rpmhpd SDM845_MX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - qcom,non-secure-domain; - qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA - QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; - memory-region = <&fastrpc_mem>; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@0 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <0>; - }; - }; - }; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = - <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = - <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@5 { - reg = <5>; - funnel2_in5: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = - <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - replicator_out: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel2_in5>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = - <&apss_funnel_out>; - }; - }; - }; - }; - - sdhc_2: mmc@8804000 { - compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "core", "xo"; - iommus = <&apps_smmu 0xa0 0xf>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - - status = "disabled"; - - sdhc2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-9600000 { - opp-hz = /bits/ 64 <9600000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-201500000 { - opp-hz = /bits/ 64 <201500000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - qspi: spi@88df000 { - compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0 0x088df000 0 0x600>; - iommus = <&apps_smmu 0x160 0x0>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - clock-names = "iface", "core"; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qspi_opp_table>; - status = "disabled"; - }; - - slim: slim-ngd@171c0000 { - compatible = "qcom,slim-ngd-v2.1.0"; - reg = <0 0x171c0000 0 0x2c000>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - - dmas = <&slimbam 3>, <&slimbam 4>; - dma-names = "rx", "tx"; - - iommus = <&apps_smmu 0x1806 0x0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - lmh_cluster1: lmh@17d70800 { - compatible = "qcom,sdm845-lmh"; - reg = <0 0x17d70800 0 0x400>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - cpus = <&CPU4>; - qcom,lmh-temp-arm-millicelsius = <65000>; - qcom,lmh-temp-low-millicelsius = <94500>; - qcom,lmh-temp-high-millicelsius = <95000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - lmh_cluster0: lmh@17d78800 { - compatible = "qcom,sdm845-lmh"; - reg = <0 0x17d78800 0 0x400>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - cpus = <&CPU0>; - qcom,lmh-temp-arm-millicelsius = <65000>; - qcom,lmh-temp-low-millicelsius = <94500>; - qcom,lmh-temp-high-millicelsius = <95000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2p_hstx_trim>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - - nvmem-cells = <&qusb2s_hstx_trim>; - }; - - usb_1_qmpphy: phy@88e8000 { - compatible = "qcom,sdm845-qmp-usb3-dp-phy"; - reg = <0 0x088e8000 0 0x3000>; - status = "disabled"; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe", - "cfg_ahb"; - - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - #clock-cells = <1>; - #phy-cells = <1>; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x18c>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x128>, - <0 0x088eb400 0 0x1fc>, - <0 0x088eb800 0 0x218>, - <0 0x088eb600 0 0x70>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; - interconnect-names = "usb-ddr", "apps-usb"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x740 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; - interconnect-names = "usb-ddr", "apps-usb"; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x760 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - venus: video-codec@aa00000 { - compatible = "qcom,sdm845-venus-v2"; - reg = <0 0x0aa00000 0 0xff000>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&videocc VENUS_GDSC>, - <&videocc VCODEC0_GDSC>, - <&videocc VCODEC1_GDSC>, - <&rpmhpd SDM845_CX>; - power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; - operating-points-v2 = <&venus_opp_table>; - clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, - <&videocc VIDEO_CC_VENUS_AHB_CLK>, - <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, - <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, - <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; - clock-names = "core", "iface", "bus", - "vcodec0_core", "vcodec0_bus", - "vcodec1_core", "vcodec1_bus"; - iommus = <&apps_smmu 0x10a0 0x8>, - <&apps_smmu 0x10b0 0x0>; - memory-region = <&venus_mem>; - interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; - interconnect-names = "video-mem", "cpu-cfg"; - - status = "disabled"; - - video-core0 { - compatible = "venus-decoder"; - }; - - video-core1 { - compatible = "venus-encoder"; - }; - - venus_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-320000000 { - opp-hz = /bits/ 64 <320000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-380000000 { - opp-hz = /bits/ 64 <380000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-444000000 { - opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-533000097 { - opp-hz = /bits/ 64 <533000097>; - required-opps = <&rpmhpd_opp_turbo>; - }; - }; - }; - - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0 0x0ab00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - }; - - camss: camss@acb3000 { - compatible = "qcom,sdm845-camss"; - - reg = <0 0x0acb3000 0 0x1000>, - <0 0x0acba000 0 0x1000>, - <0 0x0acc8000 0 0x1000>, - <0 0x0ac65000 0 0x1000>, - <0 0x0ac66000 0 0x1000>, - <0 0x0ac67000 0 0x1000>, - <0 0x0ac68000 0 0x1000>, - <0 0x0acaf000 0 0x4000>, - <0 0x0acb6000 0 0x4000>, - <0 0x0acc4000 0 0x4000>; - reg-names = "csid0", - "csid1", - "csid2", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy3", - "vfe0", - "vfe1", - "vfe_lite"; - - interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "csid0", - "csid1", - "csid2", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy3", - "vfe0", - "vfe1", - "vfe_lite"; - - power-domains = <&clock_camcc IFE_0_GDSC>, - <&clock_camcc IFE_1_GDSC>, - <&clock_camcc TITAN_TOP_GDSC>; - - clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, - <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, - <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, - <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, - <&clock_camcc CAM_CC_CSIPHY0_CLK>, - <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&clock_camcc CAM_CC_CSIPHY1_CLK>, - <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, - <&clock_camcc CAM_CC_CSIPHY2_CLK>, - <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, - <&clock_camcc CAM_CC_CSIPHY3_CLK>, - <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, - <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, - <&gcc GCC_CAMERA_AHB_CLK>, - <&gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, - <&clock_camcc CAM_CC_IFE_0_CLK>, - <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, - <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, - <&clock_camcc CAM_CC_IFE_1_CLK>, - <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, - <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_LITE_CLK>, - <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, - <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; - clock-names = "camnoc_axi", - "cpas_ahb", - "cphy_rx_src", - "csi0", - "csi0_src", - "csi1", - "csi1_src", - "csi2", - "csi2_src", - "csiphy0", - "csiphy0_timer", - "csiphy0_timer_src", - "csiphy1", - "csiphy1_timer", - "csiphy1_timer_src", - "csiphy2", - "csiphy2_timer", - "csiphy2_timer_src", - "csiphy3", - "csiphy3_timer", - "csiphy3_timer_src", - "gcc_camera_ahb", - "gcc_camera_axi", - "slow_ahb_src", - "soc_ahb", - "vfe0_axi", - "vfe0", - "vfe0_cphy_rx", - "vfe0_src", - "vfe1_axi", - "vfe1", - "vfe1_cphy_rx", - "vfe1_src", - "vfe_lite", - "vfe_lite_cphy_rx", - "vfe_lite_src"; - - iommus = <&apps_smmu 0x0808 0x0>, - <&apps_smmu 0x0810 0x8>, - <&apps_smmu 0x0c08 0x0>, - <&apps_smmu 0x0c10 0x8>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - }; - }; - - cci: cci@ac4a000 { - compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0 0x0ac4a000 0 0x4000>; - interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; - power-domains = <&clock_camcc TITAN_TOP_GDSC>; - - clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CCI_CLK>, - <&clock_camcc CAM_CC_CCI_CLK_SRC>; - clock-names = "camnoc_axi", - "soc_ahb", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - - assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_CCI_CLK>; - assigned-clock-rates = <80000000>, <37500000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - clock_camcc: clock-controller@ad00000 { - compatible = "qcom,sdm845-camcc"; - reg = <0 0x0ad00000 0 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - }; - - mdss: display-subsystem@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0 0x0ae00000 0 0x1000>; - reg-names = "mdss"; - - power-domains = <&dispcc MDSS_GDSC>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "core"; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, - <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_smmu 0x880 0x8>, - <&apps_smmu 0xc80 0x8>; - - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mdss_mdp: display-controller@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf0_out: endpoint { - remote-endpoint = <&dp_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; - }; - }; - - port@2 { - reg = <2>; - dpu_intf2_out: endpoint { - remote-endpoint = <&mdss_dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-171428571 { - opp-hz = /bits/ 64 <171428571>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-344000000 { - opp-hz = /bits/ 64 <344000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-430000000 { - opp-hz = /bits/ 64 <430000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - mdss_dp: displayport-controller@ae90000 { - status = "disabled"; - compatible = "qcom,sdm845-dp"; - - reg = <0 0x0ae90000 0 0x200>, - <0 0x0ae90200 0 0x200>, - <0 0x0ae90400 0 0x600>, - <0 0x0ae90a00 0 0x600>, - <0 0x0ae91000 0 0x600>; - - interrupt-parent = <&mdss>; - interrupts = <12>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; - assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, - <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; - phy-names = "dp"; - - operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dp_in: endpoint { - remote-endpoint = <&dpu_intf0_out>; - }; - }; - - port@1 { - reg = <1>; - dp_out: endpoint { }; - }; - }; - - dp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - mdss_dsi0: dsi@ae94000 { - compatible = "qcom,sdm845-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae94000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; - - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - phys = <&mdss_dsi0_phy>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi0_in: endpoint { - remote-endpoint = <&dpu_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi0_out: endpoint { - }; - }; - }; - }; - - mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - - mdss_dsi1: dsi@ae96000 { - compatible = "qcom,sdm845-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <5>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; - - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - phys = <&mdss_dsi1_phy>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi1_out: endpoint { - }; - }; - }; - }; - - mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96a00 0 0x10e>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - }; - - gpu: gpu@5000000 { - compatible = "qcom,adreno-630.2", "qcom,adreno"; - - reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; - reg-names = "kgsl_3d0_reg_memory", "cx_mem"; - - /* - * Look ma, no clocks! The GPU clocks and power are - * controlled entirely by the GMU - */ - - interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; - - iommus = <&adreno_smmu 0>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "gfx-mem"; - - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-710000000 { - opp-hz = /bits/ 64 <710000000>; - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; - opp-peak-kBps = <7216000>; - }; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; - opp-peak-kBps = <7216000>; - }; - - opp-596000000 { - opp-hz = /bits/ 64 <596000000>; - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - opp-peak-kBps = <6220000>; - }; - - opp-520000000 { - opp-hz = /bits/ 64 <520000000>; - opp-level = <RPMH_REGULATOR_LEVEL_NOM>; - opp-peak-kBps = <6220000>; - }; - - opp-414000000 { - opp-hz = /bits/ 64 <414000000>; - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - opp-peak-kBps = <4068000>; - }; - - opp-342000000 { - opp-hz = /bits/ 64 <342000000>; - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - opp-peak-kBps = <2724000>; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - opp-peak-kBps = <1648000>; - }; - }; - }; - - adreno_smmu: iommu@5040000 { - compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; - reg = <0 0x05040000 0 0x10000>; - #iommu-cells = <1>; - #global-interrupts = <2>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; - clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_CFG_AHB_CLK>; - clock-names = "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - gmu: gmu@506a000 { - compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; - - reg = <0 0x0506a000 0 0x30000>, - <0 0x0b280000 0 0x10000>, - <0 0x0b480000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - }; - }; - }; - - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, - <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, - <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - clock-names = "bi_tcxo", - "gcc_disp_gpll0_clk_src", - "gcc_disp_gpll0_div_clk_src", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_link_clk_divsel_ten", - "dp_vco_divided_clk_src_mux"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc_intc: interrupt-controller@b220000 { - compatible = "qcom,sdm845-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - pdc_reset: reset-controller@b2e0000 { - compatible = "qcom,sdm845-pdc-global"; - reg = <0 0x0b2e0000 0 0x20000>; - #reset-cells = <1>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <13>; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_reset: reset-controller@c2a0000 { - compatible = "qcom,sdm845-aoss-cc"; - reg = <0 0x0c2a0000 0 0x31000>; - #reset-cells = <1>; - }; - - aoss_qmp: power-management@c300000 { - compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - - cx_cdev: cx { - #cooling-cells = <2>; - }; - - ebi_cdev: ebi { - #cooling-cells = <2>; - }; - }; - - sram@c3f0000 { - compatible = "qcom,sdm845-rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c440000 0 0x1100>, - <0 0x0c600000 0 0x2000000>, - <0 0x0e600000 0 0x100000>, - <0 0x0e700000 0 0xa0000>, - <0 0x0c40a000 0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - sram@146bf000 { - compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; - reg = <0 0x146bf000 0 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0 0x146bf000 0x1000>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0xc8>; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x80000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; - }; - - lpasscc: clock-controller@17014000 { - compatible = "qcom,sdm845-lpasscc"; - reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; - reg-names = "cc", "qdsp6ss"; - #clock-cells = <1>; - status = "disabled"; - }; - - gladiator_noc: interconnect@17900000 { - compatible = "qcom,sdm845-gladiator-noc"; - reg = <0 0x17900000 0 0xd080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - watchdog@17980000 { - compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; - reg = <0 0x17980000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - }; - - apss_shared: mailbox@17990000 { - compatible = "qcom,sdm845-apss-shared"; - reg = <0 0x17990000 0 0x1000>; - #mbox-cells = <1>; - }; - - apps_rsc: rsc@179c0000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0 0x179c0000 0 0x10000>, - <0 0x179d0000 0 0x10000>, - <0 0x179e0000 0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = <ACTIVE_TCS 2>, - <SLEEP_TCS 3>, - <WAKE_TCS 3>, - <CONTROL_TCS 1>; - power-domains = <&CLUSTER_PD>; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sdm845-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdm845-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM>; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0x17a00000 0 0x10000>, /* GICD */ - <0 0x17a60000 0 0x100000>; /* GICR * 8 */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - msi-controller@17a40000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; - status = "disabled"; - }; - }; - - slimbam: dma-controller@17184000 { - compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0 0x17184000 0 0x2a000>; - num-channels = <31>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - iommus = <&apps_smmu 0x1806 0x0>; - }; - - timer@17c90000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - compatible = "arm,armv7-timer-mem"; - reg = <0 0x17c90000 0 0x1000>; - - frame@17ca0000 { - frame-number = <0>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17ca0000 0x1000>, - <0x17cb0000 0x1000>; - }; - - frame@17cc0000 { - frame-number = <1>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17cc0000 0x1000>; - status = "disabled"; - }; - - frame@17cd0000 { - frame-number = <2>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17cd0000 0x1000>; - status = "disabled"; - }; - - frame@17ce0000 { - frame-number = <3>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17ce0000 0x1000>; - status = "disabled"; - }; - - frame@17cf0000 { - frame-number = <4>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17cf0000 0x1000>; - status = "disabled"; - }; - - frame@17d00000 { - frame-number = <5>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17d00000 0x1000>; - status = "disabled"; - }; - - frame@17d10000 { - frame-number = <6>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17d10000 0x1000>; - status = "disabled"; - }; - }; - - osm_l3: interconnect@17d41000 { - compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; - reg = <0 0x17d41000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; - reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - #clock-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - status = "disabled"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - clock-names = "cxo_ref_clk_pin"; - clocks = <&rpmhcc RPMH_RF_CLK2>; - interrupts = - <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x0040 0x1>; - }; - }; - - sound: sound { - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu-crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - q6_modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi index ba0c02489d1..f004e9840a2 100644 --- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -16,11 +16,26 @@ u-boot,mmc-env-partition = "u-boot-env"; }; + gpio-keys { + button-user-1 { + label = "User-1"; + linux,code = <BTN_2>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user { + /* update label to match the label requested in board_key_check() */ + label = "User-2"; + }; + }; + leds { + led-blue { + /delete-property/default-state; + }; + led-red { - color = <LED_COLOR_ID_RED>; gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 20728f27ee1..a5158fec7ef 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright : STMicroelectronics 2022 */ +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-scmi-u-boot.dtsi" / { @@ -12,20 +13,35 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; }; led { - red { - label = "error"; + led-blue { + /delete-property/label; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index a16358266a2..f97debaa0e4 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" @@ -14,12 +15,10 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "fip"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL) @@ -48,12 +47,29 @@ }; #endif + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + led { - red { - label = "error"; + led-blue { + /delete-property/label; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 4d763bd3a2c..7c0d1bab11a 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright : STMicroelectronics 2022 */ +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-scmi-u-boot.dtsi" / { @@ -11,19 +12,36 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; }; led { - red { - label = "error"; + compatible = "gpio-leds"; + + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index ef91088aa37..d93359f967c 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" @@ -13,11 +14,9 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "fip"; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL) @@ -43,12 +42,31 @@ }; #endif + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + led { - red { - label = "error"; + compatible = "gpio-leds"; + + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 139940bd5d4..3515347e91d 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -33,11 +33,11 @@ label = "fsbl1"; reg = <0x00000000 0x00040000>; }; - partition@80000 { + partition@40000 { label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "ssbl"; reg = <0x00080000 0x00200000>; }; @@ -58,7 +58,7 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "fip"; reg = <0x00080000 0x00400000>; }; @@ -112,7 +112,7 @@ label = "fip2"; reg = <0x00600000 0x00400000>; }; - partition@1200000 { + partition@a00000 { label = "UBI"; reg = <0x00a00000 0x3f600000>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 2f70b0690d2..1b445619325 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -106,15 +106,15 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@500000 { + partition@80000 { label = "uboot"; reg = <0x00080000 0x00160000>; }; - partition@900000 { + partition@1e0000 { label = "env1"; reg = <0x001E0000 0x00010000>; }; - partition@980000 { + partition@1f0000 { label = "env2"; reg = <0x001F0000 0x00010000>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 552b35db3c7..ba84db679e1 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -42,15 +42,15 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@500000 { + partition@80000 { label = "uboot"; reg = <0x00080000 0x00160000>; }; - partition@900000 { + partition@1e0000 { label = "env1"; reg = <0x001E0000 0x00010000>; }; - partition@980000 { + partition@1f0000 { label = "env2"; reg = <0x001F0000 0x00010000>; }; diff --git a/arch/arm/dts/tegra114-u-boot.dtsi b/arch/arm/dts/tegra114-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra114-u-boot.dtsi +++ b/arch/arm/dts/tegra114-u-boot.dtsi @@ -1,3 +1,16 @@ #include <config.h> #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 68ee7f31656..250d692f6bf 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -42,7 +42,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP1>, @@ -61,7 +61,7 @@ }; dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP2>, diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5cf604e8659..f851767a55f 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -35,22 +35,6 @@ status = "okay"; nvidia,panel = <&panel>; - - display-timings { - timing@0 { - /* PAZ00 has 1024x600 */ - clock-frequency = <54030000>; - hactive = <1024>; - vactive = <600>; - hback-porch = <160>; - hfront-porch = <24>; - hsync-len = <136>; - vback-porch = <3>; - vfront-porch = <61>; - vsync-len = <6>; - hsync-active = <1>; - }; - }; }; }; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index e8a3511a9f7..d437ddc4dce 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -829,6 +829,12 @@ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; }; + + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; }; panel: panel { diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 350443d55eb..243ff2bda26 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -118,8 +118,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -203,7 +203,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; gen2_i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -213,7 +213,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; cam_i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -223,7 +223,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; ddc_i2c { nvidia,pins = "ddc_scl_pv4", @@ -232,7 +232,7 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; pwr_i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -242,7 +242,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hotplug_i2c { nvidia,pins = "pu4"; @@ -260,7 +260,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hdmi_hpd { nvidia,pins = "hdmi_int_pn7"; @@ -632,8 +632,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -718,8 +718,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_d10_pt2 { nvidia,pins = "vi_d10_pt2", @@ -838,8 +838,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index f49e7341fe0..3ddd78b3df6 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -90,6 +90,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC2 pinmux */ @@ -98,21 +100,15 @@ "vi_d2_pl0", "vi_d3_pl1", "vi_d5_pl3", - "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6", + "vi_d7_pl5", + "vi_d8_pl6", "vi_d9_pl7"; nvidia,function = "sdmmc2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -146,6 +142,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; sdmmc4_cmd { nvidia,pins = "sdmmc4_cmd_pt7", @@ -161,6 +159,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; sdmmc4_rst_n { nvidia,pins = "sdmmc4_rst_n_pcc3"; @@ -469,6 +469,42 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; + /* SPI pinmux */ + spi1_ctrl { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_sck { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs1_n { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi4_ctrl { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + /* Display A pinmux */ lcd_pwr0_pb2 { nvidia,pins = "lcd_pwr0_pb2", @@ -577,8 +613,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -657,18 +693,19 @@ nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6", + nvidia,pins = "vi_d0_pt4", + "vi_d10_pt2", + "vi_vsync_pd6", "vi_hsync_pd7"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2", - "vi_d0_pt4", "pbb0"; + pbb0 { + nvidia,pins = "pbb0"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -783,21 +820,15 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; + vi_d4 { + nvidia,pins = "vi_d4_pl2", + "vi_d6_pl4"; nvidia,function = "vi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; @@ -805,6 +836,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; jtag { @@ -1089,6 +1122,16 @@ clock-output-names = "pmic-oscillator"; }; + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts index cc03f5a7ec2..6dc760b90d6 100644 --- a/arch/arm/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -7,7 +7,18 @@ model = "ASUS Transformer Infinity TF700T"; compatible = "asus,tf700t", "nvidia,tegra30"; - /delete-node/ host1x@50000000; + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&tc358768>; + }; + }; + }; pinmux@70000868 { state_default: pinmux { @@ -62,5 +73,92 @@ }; }; - /delete-node/ panel; + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&gen1_i2c>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tc358768: dsi@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + panel = <&panel>; + }; + }; + }; + + panel: panel { + compatible = "panasonic,vvx10f004b00"; + + power-supply = <&vdd_pnl_reg>; + backlight = <&backlight>; + + /delete-property/ enable-gpios; + + display-timings { + timing@0 { + /* 1920x1200@60Hz */ + clock-frequency = <154000000>; + + hactive = <1920>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + hsync-active = <1>; + + vactive = <1200>; + vfront-porch = <3>; + vback-porch = <26>; + vsync-len = <6>; + vsync-active = <1>; + }; + }; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index e6cc6e7105f..03ba8fb9604 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -99,8 +99,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -189,7 +189,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; gen2_i2c { @@ -200,7 +200,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; cam_i2c { @@ -211,7 +211,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; ddc_i2c { @@ -221,7 +221,7 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; pwr_i2c { @@ -232,7 +232,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hotplug_i2c { @@ -647,8 +647,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -741,8 +741,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_d10_pt2 { @@ -879,8 +879,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { @@ -1150,6 +1150,16 @@ clock-output-names = "pmic-oscillator"; }; + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi index 3038227dbed..6a02714a258 100644 --- a/arch/arm/dts/tegra30-u-boot.dtsi +++ b/arch/arm/dts/tegra30-u-boot.dtsi @@ -8,5 +8,9 @@ dc@54200000 { bootph-all; }; + + dc@54240000 { + bootph-all; + }; }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index f198bc0edbe..1177e2ab1f4 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -158,7 +158,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 4276a0f6811..ecf3b4e7428 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -43,11 +43,14 @@ void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd); * Boot-device identifiers as used by the BROM */ enum { + BROM_BOOTSOURCE_UNKNOWN = 0, BROM_BOOTSOURCE_NAND = 1, BROM_BOOTSOURCE_EMMC = 2, BROM_BOOTSOURCE_SPINOR = 3, BROM_BOOTSOURCE_SPINAND = 4, BROM_BOOTSOURCE_SD = 5, + BROM_BOOTSOURCE_I2C = 8, + BROM_BOOTSOURCE_SPI = 9, BROM_BOOTSOURCE_USB = 10, BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB }; diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h index 84b63e4d568..091ae82d7cc 100644 --- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h @@ -147,6 +147,20 @@ enum { CORE_DIV_CON_SHIFT = 0, CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, + /* CRU_CLK_SEL2_CON */ + CLK_RTC32K_SEL_SHIFT = 8, + CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT, + CLK_RTC32K_IO = 0, + CLK_RTC32K_PVTM, + CLK_RTC32K_FRAC_DIV, + CLK_RTC32K_DIV, + + /* CRU_CLK_SEL3_CON */ + CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, + CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, + CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, + /* CRU_CLK_SEL5_CON */ BUS_PLL_SEL_SHIFT = 6, BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 226744d67d9..4ad1d33e056 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); enum apll_frequencies { APLL_816_MHZ, APLL_600_MHZ, + + /* CRU_CLK_SEL37_CON */ + ACLK_VIO_PLL_SEL_CPLL = 0, + ACLK_VIO_PLL_SEL_GPLL = 1, + ACLK_VIO_PLL_SEL_HDMIPHY = 2, + ACLK_VIO_PLL_SEL_USB480M = 3, + ACLK_VIO_PLL_SEL_SHIFT = 6, + ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, + ACLK_VIO_DIV_CON_SHIFT = 0, + ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, + HCLK_VIO_DIV_CON_SHIFT = 8, + HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, + + /* CRU_CLK_SEL39_CON */ + ACLK_VOP_PLL_SEL_CPLL = 0, + ACLK_VOP_PLL_SEL_GPLL = 1, + ACLK_VOP_PLL_SEL_HDMIPHY = 2, + ACLK_VOP_PLL_SEL_USB480M = 3, + ACLK_VOP_PLL_SEL_SHIFT = 6, + ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, + ACLK_VOP_DIV_CON_SHIFT = 0, + ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, + + /* CRU_CLK_SEL40_CON */ + DCLK_LCDC_PLL_SEL_GPLL = 0, + DCLK_LCDC_PLL_SEL_CPLL = 1, + DCLK_LCDC_PLL_SEL_SHIFT = 0, + DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, + DCLK_LCDC_SEL_HDMIPHY = 0, + DCLK_LCDC_SEL_PLL = 1, + DCLK_LCDC_SEL_SHIFT = 1, + DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, + DCLK_LCDC_DIV_CON_SHIFT = 8, + DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, }; void rk3328_configure_cpu(struct rk3328_cru *cru, diff --git a/arch/arm/include/asm/arch-rk3308/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h index a995bb950d9..a995bb950d9 100644 --- a/arch/arm/include/asm/arch-rk3308/grf_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index fe6b8ba2732..0264bfe1c50 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -220,10 +220,7 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); -void clock_set_pll2(unsigned int clk); -void clock_set_pll4(unsigned int clk); void clock_set_pll6(unsigned int clk); -void clock_set_pll12(unsigned int clk); unsigned int clock_get_pll4_periph0(void); #endif diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h index 7a6fcaebdb5..92696088a39 100644 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h @@ -28,6 +28,12 @@ struct sunxi_tzpc { #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 void tzpc_init(void); +#else +static inline void tzpc_init(void) +{ +} +#endif #endif /* _SUNXI_TZPC_H */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 7613d84f221..ca3718411ab 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -443,6 +443,11 @@ enum win_color_depth_id { #define WINDOW_D_SELECT BIT(7) #define WINDOW_H_SELECT BIT(8) +/* DC_COM_PIN_OUTPUT_POLARITY1 0x307 */ +#define LHS_OUTPUT_POLARITY_LOW BIT(30) +#define LVS_OUTPUT_POLARITY_LOW BIT(28) +#define LSC0_OUTPUT_POLARITY_LOW BIT(24) + /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ #define CURSOR_ENABLE BIT(16) #define SOR_ENABLE BIT(25) @@ -569,12 +574,4 @@ enum { #define DC_N_WINDOWS 5 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) -#define TEGRA_DSI_A "dsi@54300000" -#define TEGRA_DSI_B "dsi@54400000" - -struct tegra_dc_plat { - struct udevice *dev; /* Display controller device */ - struct dc_ctlr *dc; /* Display controller regmap */ -}; - #endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/arch/arm/include/asm/arch-tegra114/pwm.h b/arch/arm/include/asm/arch-tegra114/pwm.h new file mode 100644 index 00000000000..af391518035 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA114_PWM_H +#define __ASM_ARCH_TEGRA114_PWM_H + +#include <asm/arch-tegra/pwm.h> + +#endif /* __ASM_ARCH_TEGRA114_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h deleted file mode 100644 index e7b3cffd466..00000000000 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned x; /* Horizontal address offset (bytes) */ - unsigned y; /* Veritical address offset (bytes) */ - unsigned w; /* Width of source window */ - unsigned h; /* Height of source window */ - unsigned stride; /* Number of bytes per line */ - unsigned out_x; /* Left edge of output window (col) */ - unsigned out_y; /* Top edge of output window (row) */ - unsigned out_w; /* Width of output window in pixels */ - unsigned out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra30/display.h b/arch/arm/include/asm/arch-tegra30/display.h deleted file mode 100644 index 9411525799d..00000000000 --- a/arch/arm/include/asm/arch-tegra30/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned int bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned int x; /* Horizontal address offset (bytes) */ - unsigned int y; /* Veritical address offset (bytes) */ - unsigned int w; /* Width of source window */ - unsigned int h; /* Height of source window */ - unsigned int stride; /* Number of bytes per line */ - unsigned int out_x; /* Left edge of output window (col) */ - unsigned int out_y; /* Top edge of output window (row) */ - unsigned int out_w; /* Width of output window in pixels */ - unsigned int out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c index cd7e95e61d0..7d787d04598 100644 --- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c +++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c @@ -45,7 +45,7 @@ * based on trace length differences from their * layout. * Mismatches up to 25% or tCK (clock period) are - * allowed, so the value in the filed doesn’t have + * allowed, so the value in the filed doesn't have * to be very accurate. * * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation @@ -184,14 +184,14 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n", (tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0 - /* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */ + /* Program Leveling mode - CR93[SW_LVL_MODE] to 'b10 */ clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3), DDRMC_CR93_SW_LVL_MODE(0x2)); tmp = readl(&ddrmr->cr[93]); debug("RDLVL: SW_LVL_MODE:\t 0x%x\n", (tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3); - /* Start procedure - CR93[SWLVL_START] to ’b1 */ + /* Start procedure - CR93[SWLVL_START] to 'b1 */ sw_leveling_start; /* Poll CR94[SWLVL_OP_DONE] */ @@ -211,7 +211,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) 0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF, i << DDRMC_CR105_RDLVL_DL_0_OFF); - /* Load values CR93[SWLVL_LOAD] to ’b1 */ + /* Load values CR93[SWLVL_LOAD] to 'b1 */ sw_leveling_load_value; /* Poll CR94[SWLVL_OP_DONE] */ @@ -263,7 +263,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) 0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF, i << DDRMC_CR110_RDLVL_DL_1_OFF); - /* Load values CR93[SWLVL_LOAD] to ’b1 */ + /* Load values CR93[SWLVL_LOAD] to 'b1 */ sw_leveling_load_value; /* Poll CR94[SWLVL_OP_DONE] */ @@ -317,7 +317,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) sw_leveling_load_value; sw_leveling_op_done; - /* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */ + /* Exit procedure - CR94[SWLVL_EXIT] to 'b1 */ sw_leveling_exit; /* Poll CR94[SWLVL_OP_DONE] */ diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index b79485f1f75..e892da80fe8 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -31,6 +31,7 @@ choice config TARGET_IMX93_11X11_EVK bool "imx93_11x11_evk" select IMX93 + imply OF_UPSTREAM config TARGET_IMX93_VAR_SOM bool "imx93_var_som" diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 1bdc568f9b1..e0da9c23958 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -714,10 +714,10 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) /* * Register: PLL_VIDEO * Bit Field: POST_DIV_SELECT - * 00 — Divide by 4. - * 01 — Divide by 2. - * 10 — Divide by 1. - * 11 — Reserved + * 00 - Divide by 4. + * 01 - Divide by 2. + * 10 - Divide by 1. + * 11 - Reserved * No need to check post_div(1) */ for (post_div = 2; post_div <= 4; post_div <<= 1) { diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 699a2569cb7..0b71fa40344 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -631,9 +631,9 @@ __secure void psci_system_suspend(u32 __always_unused function_id, * Workaround: * If both CPU0/CPU1 are IDLE, the last IDLE CPU should * disable GIC first, then REG_BYPASS_COUNTER is used - * to mask wakeup INT, and then execute “wfi” is used to + * to mask wakeup INT, and then execute "wfi" is used to * bring the system into power down processing safely. - * The counter must be enabled as close to the “wfi” state + * The counter must be enabled as close to the "wfi" state * as possible. The following equation can be used to * determine the RBC counter value: * RBC_COUNT * (1/32K RTC frequency) >= diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h b/arch/arm/mach-ipq40xx/include/mach/gpio.h index a45747c0fe5..53c6ae06490 100644 --- a/arch/arm/mach-ipq40xx/include/mach/gpio.h +++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h @@ -1,10 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Empty gpio.h + * Qualcomm common pin control data. * - * This file must stay as arch/arm/include/asm/gpio.h requires it. - * - * Copyright (c) 2019 Sartura Ltd. - * - * Author: Robert Marko <robert.marko@sartura.hr> + * Copyright (C) 2023 Linaro Ltd. */ +#ifndef _QCOM_GPIO_H_ +#define _QCOM_GPIO_H_ + +#include <asm/types.h> +#include <stdbool.h> + +struct msm_pin_data { + int pin_count; + const unsigned int *pin_offsets; + /* Index of first special pin, these are ignored for now */ + unsigned int special_pins_start; +}; + +static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector) +{ + u32 out = (selector * 0x1000); + + if (offs) + return out + offs[selector]; + + return out; +} + +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin) +{ + return pindata->special_pins_start && pin >= pindata->special_pins_start; +} + +#endif /* _QCOM_GPIO_H_ */ diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index 2a0221a3718..658828cf75f 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -31,7 +31,7 @@ static void store_boot_info_from_rom(void) bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); if (IS_ENABLED(CONFIG_CPU_V7R)) { - memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, sizeof(struct rom_extended_boot_data)); } } diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index ddf47ef0a9b..80c3cb3479f 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -226,7 +226,7 @@ void board_init_f(ulong dummy) * The warm reset realigns internal clocks and prevents the lockup from * happening. */ - ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); + ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, DM_DRIVER_GET(ti_sci), &dev); if (ret) printf("\n%s:uclass device error [%d]\n",__func__,ret); diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h index 11080801c4c..cd61abe0185 100644 --- a/arch/arm/mach-k3/include/mach/am62a_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -66,7 +66,7 @@ #define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) #define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) -#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0 +#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 #define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f68a0a48949..67d3b28d058 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -160,14 +160,25 @@ config ROCKCHIP_RK3308 select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM select SPL_LOAD_FIT + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply DM_RNG + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD - imply SPL_ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_OTP imply SPL_CLK - imply SPL_REGMAP - imply SPL_SYSCON + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_PINCTRL imply SPL_RAM - imply SPL_SERIAL + imply SPL_REGMAP + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS + imply SPL_SERIAL + imply SPL_SYSCON help The Rockchip RK3308 is a ARM-based Soc which embedded with quad Cortex-A35 and highly integrated audio interfaces. @@ -180,18 +191,19 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply MISC + imply MISC_INIT_R + imply OF_LIVE + imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SEPARATE_BSS imply SPL_SERIAL imply TPL_SERIAL - imply SPL_SEPARATE_BSS - select ENABLE_ARM_SOC_BOOT0_HOOK - select DEBUG_UART_BOARD_INIT - select SYS_NS16550 - imply MISC - imply ROCKCHIP_EFUSE - imply MISC_INIT_R help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -294,12 +306,16 @@ config ROCKCHIP_RK3568 select BOARD_LATE_INIT select DM_REGULATOR_FIXED select DM_RESET - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply OF_LIBFDT_OVERLAY - imply ROCKCHIP_OTP + imply BOOTSTD_FULL + imply DM_RNG imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_OTP + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, @@ -321,16 +337,19 @@ config ROCKCHIP_RK3588 select BOARD_LATE_INIT select DM_REGULATOR_FIXED select DM_RESET - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply OF_LIBFDT_OVERLAY - imply ROCKCHIP_OTP + imply BOOTSTD_FULL + imply CLK_SCMI + imply DM_RNG imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP - imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT - imply CLK_SCMI + imply OF_LIBFDT_OVERLAY + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_OTP imply SCMI_FIRMWARE - imply BOOTSTD_FULL + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, @@ -573,6 +592,9 @@ config ROCKCHIP_COMMON_STACK_ADDR imply TPL_SYS_MALLOC_F if TPL imply TPL_SYS_MALLOC_SIMPLE if TPL +config NR_DRAM_BANKS + default 10 if ROCKCHIP_EXTERNAL_TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index 637a5e1b18b..db368a7b8c2 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -36,7 +36,7 @@ void board_init_f(ulong dummy) { int ret; -#ifdef CONFIG_DEBUG_UART +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL) debug_uart_init(); /* * Debug UART can be used from here if required: @@ -46,8 +46,10 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ +#if CONFIG_TPL_BANNER_PRINT printascii("U-Boot TPL board init\n"); #endif +#endif secure_timer_init(); ret = sdram_init(); diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 41893920cb4..23f8f430c4a 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -36,9 +36,9 @@ config TARGET_PX30_CORE 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. config TARGET_RINGNECK_PX30 - bool "Theobroma Systems PX30-µQ7 (Ringneck)" + bool "Theobroma Systems PX30-uQ7 (Ringneck)" help - The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, + The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm, MXM-230 connector) system-on-module from Theobroma Systems[1], featuring the Rockchip PX30. diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index b4f655fa4b3..2ec3289d75b 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -19,6 +19,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff3a0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff370000", }; diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index c77c56c1dab..70cf5002912 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -28,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff130000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 749e9995d91..fac966207a9 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -23,9 +23,6 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00600000 -config SPL_SERIAL - default y - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c index ccda53380c6..201bf661f9b 100644 --- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c @@ -7,7 +7,7 @@ #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch/cru_rk3308.h> +#include <asm/arch-rockchip/cru_rk3308.h> #include <linux/err.h> int rockchip_get_clk(struct udevice **devp) diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 27a748327e3..a0915c72bfa 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -5,8 +5,8 @@ #include <common.h> #include <init.h> #include <malloc.h> -#include <asm/arch/grf_rk3308.h> #include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/grf_rk3308.h> #include <asm/arch-rockchip/hardware.h> #include <asm/gpio.h> #include <debug_uart.h> @@ -141,6 +141,7 @@ enum { const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff4c0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff480000", }; diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index daf74a0e2d3..d2f267e6353 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -17,4 +17,7 @@ U_BOOT_DRIVER(rockchip_rk3328_grf) = { .name = "rockchip_rk3328_grf", .id = UCLASS_SYSCON, .of_match = rk3328_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif }; diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 651ba109020..8f5ca1dfa7c 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -55,6 +55,7 @@ struct mm_region *mem_map = rk3368_mem_map; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff120000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index d7e4af31f24..39049ab35a9 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -66,7 +66,7 @@ config TARGET_NANOPCT6_RK3588 HDMI2.0, and HDMI1.4 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1 USB-A: USB 3.0, Type A - USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0 + USB-C: Full function USB Type-C port, DP display up to 4Kp60, USB 3.0 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs, 8x PWMs, 2x I2Ss, 28x GPIOs Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps @@ -117,7 +117,7 @@ config TARGET_ROCK5A_RK3588 Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector 4-lane MIPI DSI connector - Audio – 3.5mm earphone jack + Audio - 3.5mm earphone jack eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 @@ -197,7 +197,7 @@ config TARGET_TOYBRICK_RK3588 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB Memory LPDDR4x Mali G610MC4 GPU - 2× MIPI-CSI0 Connector + 2x MIPI-CSI0 Connector 1x 2Lanes PCIe3.0 Connector 1x SATA3.0 Connector 32GB eMMC Module @@ -221,14 +221,14 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00a00000 -source board/edgeble/neural-compute-module-6/Kconfig -source board/friendlyelec/nanopc-t6-rk3588/Kconfig -source board/pine64/quartzpro64-rk3588/Kconfig -source board/turing/turing-rk1-rk3588/Kconfig -source board/radxa/rock5a-rk3588s/Kconfig -source board/radxa/rock5b-rk3588/Kconfig -source board/rockchip/evb_rk3588/Kconfig -source board/rockchip/toybrick_rk3588/Kconfig -source board/theobroma-systems/jaguar_rk3588/Kconfig +source "board/edgeble/neural-compute-module-6/Kconfig" +source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" +source "board/pine64/quartzpro64-rk3588/Kconfig" +source "board/turing/turing-rk1-rk3588/Kconfig" +source "board/radxa/rock5a-rk3588s/Kconfig" +source "board/radxa/rock5b-rk3588/Kconfig" +source "board/rockchip/evb_rk3588/Kconfig" +source "board/rockchip/toybrick_rk3588/Kconfig" +source "board/theobroma-systems/jaguar_rk3588/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index a12216dccf6..28ed0b24581 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -36,7 +36,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -source board/rockchip/evb_rv1108/Kconfig -source board/elgin/elgin_rv1108/Kconfig +source "board/rockchip/evb_rv1108/Kconfig" +source "board/elgin/elgin_rv1108/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index 55b11121203..330b7df2312 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -6,8 +6,8 @@ config TARGET_RV1126_NEU2 Neu2: Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. - Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC. - Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC. + Neu2 powered with Consumer grade (0 to +80 deg C) RV1126 SoC. + Neu2k powered with Industrial grade (-40 C to +85 deg C) RV1126K SoC. Neu2-IO: Neural Compute Module 2(Neu2) IO board is an industrial form factor @@ -64,7 +64,7 @@ config SYS_MALLOC_F_LEN config TEXT_BASE default 0x600000 -source board/edgeble/neural-compute-module-2/Kconfig -source board/itead/sonoff-ihost/Kconfig +source "board/edgeble/neural-compute-module-2/Kconfig" +source "board/itead/sonoff-ihost/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 8589c46f10a..40eb9eb7b19 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -15,6 +15,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ffc90000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ffc60000", }; diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 0d9a0aef6f5..f2a3d6b1400 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -8,6 +8,7 @@ #include <init.h> #include <log.h> #include <ram.h> +#include <asm/armv8/mmu.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch-rockchip/sdram.h> @@ -35,12 +36,271 @@ struct tos_parameter_t { s64 reserve[8]; }; +#ifdef CONFIG_ARM64 +/* Tag size and offset */ +#define ATAGS_SIZE SZ_8K +#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE) +#define ATAGS_PHYS_BASE (CFG_SYS_SDRAM_BASE + ATAGS_OFFSET) +#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE) + +/* ATAGS memory structures */ + +enum tag_magic { + ATAG_NONE, + ATAG_CORE = 0x54410001, + ATAG_SERIAL = 0x54410050, + ATAG_DDR_MEM = 0x54410052, + ATAG_MAX = 0x544100ff, +}; + +/* + * An ATAG contains the following data: + * - header + * u32 size // sizeof(header + tag data) / sizeof(u32) + * u32 magic + * - tag data + */ + +struct tag_header { + u32 size; + u32 magic; +} __packed; + +/* + * DDR_MEM tag bank is storing data this way: + * - address0 + * - address1 + * - [...] + * - addressX + * - size0 + * - size1 + * - [...] + * - sizeX + * + * with X being tag_ddr_mem.count - 1. + */ +struct tag_ddr_mem { + u32 count; + u32 version; + u64 bank[20]; + u32 flags; + u32 data[2]; + u32 hash; +} __packed; + +static u32 js_hash(const void *buf, u32 len) +{ + u32 i, hash = 0x47C6A7E6; + + if (!buf || !len) + return hash; + + for (i = 0; i < len; i++) + hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2)); + + return hash; +} + +static int rockchip_dram_init_banksize(void) +{ + const struct tag_header *tag_h = NULL; + u32 *addr = (void *)ATAGS_PHYS_BASE; + struct tag_ddr_mem *ddr_info; + u32 calc_hash; + u8 i, j; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && + !IS_ENABLED(CONFIG_ROCKCHIP_RK3568)) + return -ENOTSUPP; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL)) + return -ENOTSUPP; + + /* Find DDR_MEM tag */ + while (addr < (u32 *)ATAGS_PHYS_END) { + tag_h = (const struct tag_header *)addr; + + if (!tag_h->size) { + debug("End of ATAGS (0-size tag), no DDR_MEM found\n"); + return -ENODATA; + } + + if (tag_h->magic == ATAG_DDR_MEM) + break; + + switch (tag_h->magic) { + case ATAG_NONE: + case ATAG_CORE: + case ATAG_SERIAL ... ATAG_MAX: + addr += tag_h->size; + continue; + default: + debug("Invalid magic (0x%08x) for ATAG at 0x%p\n", + tag_h->magic, addr); + return -EINVAL; + } + } + + if (addr >= (u32 *)ATAGS_PHYS_END || + (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) { + debug("End of ATAGS, no DDR_MEM found\n"); + return -ENODATA; + } + + /* Data is right after the magic member of the tag_header struct */ + ddr_info = (struct tag_ddr_mem *)(&tag_h->magic + 1); + if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) { + debug("Too many ATAG banks, got (%d) but max allowed (%d)\n", + ddr_info->count, CONFIG_NR_DRAM_BANKS); + return -ENOMEM; + } + + if (!ddr_info->hash) { + debug("No hash for tag (0x%08x)\n", tag_h->magic); + } else { + calc_hash = js_hash(addr, sizeof(u32) * (tag_h->size - 1)); + + if (calc_hash != ddr_info->hash) { + debug("Incorrect hash for tag (0x%08x), got (0x%08x) expected (0x%08x)\n", + tag_h->magic, ddr_info->hash, calc_hash); + return -EINVAL; + } + } + + /* + * Rockchip guaranteed DDR_MEM is ordered so no need to worry about + * bi_dram order. + */ + for (i = 0, j = 0; i < ddr_info->count; i++, j++) { + phys_size_t size = ddr_info->bank[(i + ddr_info->count)]; + phys_addr_t start_addr = ddr_info->bank[i]; + struct mm_region *tmp_mem_map = mem_map; + phys_addr_t end_addr; + + /* + * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not + * have it, so force this space as reserved. + */ + if (start_addr < SZ_2M) { + size -= SZ_2M - start_addr; + start_addr = SZ_2M; + } + + /* + * Put holes for reserved memory areas from mem_map. + * + * Only check for at most one overlap with one reserved memory + * area. + */ + while (tmp_mem_map->size) { + const phys_addr_t rsrv_start = tmp_mem_map->phys; + const phys_size_t rsrv_size = tmp_mem_map->size; + const phys_addr_t rsrv_end = rsrv_start + rsrv_size; + + /* + * DRAM memories are expected by Arm to be marked as + * Normal Write-back cacheable, Inner shareable[1], so + * let's filter on that to put holes in non-DRAM areas. + * + * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes + */ + const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + /* + * (AttrIndx | SH) in Lower Attributes of Block + * Descriptor[2]. + * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64 + */ + const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8); + + if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) { + tmp_mem_map++; + continue; + } + + /* + * If the start of the DDR_MEM tag is in a reserved + * memory area, move start address and resize. + */ + if (start_addr >= rsrv_start && start_addr < rsrv_end) { + if (rsrv_end - start_addr > size) { + debug("Would be negative memory size\n"); + return -EINVAL; + } + + size -= rsrv_end - start_addr; + start_addr = rsrv_end; + break; + } + + if (start_addr < rsrv_start) { + end_addr = start_addr + size; + + if (end_addr <= rsrv_start) { + tmp_mem_map++; + continue; + } + + /* + * If the memory area overlaps a reserved memory + * area with start address outside of reserved + * memory area and... + * + * ... ends in the middle of reserved memory + * area, resize. + */ + if (end_addr <= rsrv_end) { + size = rsrv_start - start_addr; + break; + } + + /* + * ... ends after the reserved memory area, + * split the region in two, one for before the + * reserved memory area and one for after. + */ + gd->bd->bi_dram[j].start = start_addr; + gd->bd->bi_dram[j].size = rsrv_start - start_addr; + + j++; + + size = end_addr - rsrv_end; + start_addr = rsrv_end; + + break; + } + + tmp_mem_map++; + } + + if (j > CONFIG_NR_DRAM_BANKS) { + debug("Too many banks, max allowed (%d)\n", + CONFIG_NR_DRAM_BANKS); + return -ENOMEM; + } + + gd->bd->bi_dram[j].start = start_addr; + gd->bd->bi_dram[j].size = size; + } + + return 0; +} +#endif + int dram_init_banksize(void) { size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE); size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top)); #ifdef CONFIG_ARM64 + int ret = rockchip_dram_init_banksize(); + + if (!ret) + return ret; + + debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n", + ret); + /* Reserve 0x200000 for ATF bl31 */ gd->bd->bi_dram[0].start = 0x200000; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 79c856d2a0a..3543267aa57 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -29,7 +29,7 @@ * -ENOSYS, if the device matching the node can not be mapped onto a * SPL boot device (e.g. the third MMC device) * -1, for unspecified failures - * a positive integer (from the BOOT_DEVICE_... family) on succes. + * a positive integer (from the BOOT_DEVICE_... family) on success. */ static int spl_node_to_boot_device(int node) @@ -148,8 +148,8 @@ void board_boot_order(u32 *spl_boot_list) /* Try to map this back onto SPL boot devices */ boot_device = spl_node_to_boot_device(node); if (boot_device < 0) { - debug("%s: could not map node @%x to a boot-device\n", - __func__, node); + debug("%s: could not map node %s to a boot-device\n", + __func__, conf); continue; } diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 1586a093fc3..3ce7e792b5a 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -32,18 +32,26 @@ __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { const char *board_spl_was_booted_from(void) { - u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN; + u32 bootdevice_brom_id; const char *bootdevice_ofpath = NULL; + if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN) + bootdevice_brom_id = brom_bootsource_id_cache; + else + bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) bootdevice_ofpath = boot_devices[bootdevice_brom_id]; - if (bootdevice_ofpath) + if (bootdevice_ofpath) { + brom_bootsource_id_cache = bootdevice_brom_id; debug("%s: brom_bootdevice_id %x maps to '%s'\n", __func__, bootdevice_brom_id, bootdevice_ofpath); - else + } else { debug("%s: failed to resolve brom_bootdevice_id %x\n", __func__, bootdevice_brom_id); + } return bootdevice_ofpath; } diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 96e44e2c549..536960b83c3 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -4,7 +4,12 @@ config SYS_SOC default "snapdragon" config SYS_VENDOR + string "Snapdragon board vendor" default "qualcomm" + help + Allows to specify vendor for the Snapdragon SoCs based boards. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> + will be used as the custom board directory. config SYS_MALLOC_F_LEN default 0x2000 @@ -19,12 +24,11 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 config SYS_BOARD - string "Qualcomm custom board" + string "Snapdragon SoCs based board" help - The Dragonboard 410c and 820c have additional board init - code that isn't shared with other Qualcomm boards. - Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will - be used. + Allows to specify the Snapdragon SoCs based board name. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> + will be used as the custom board directory. config SYS_CONFIG_NAME string "Board configuration name" diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 3f7ac227bd0..55368dd43b6 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -17,6 +17,8 @@ * Author: Caleb Connolly <caleb.connolly@linaro.org> */ +#define pr_fmt(fmt) "of_fixup: " fmt + #include <dt-bindings/input/linux-event-codes.h> #include <dm/of_access.h> #include <dm/of.h> @@ -153,3 +155,21 @@ void qcom_of_fixup_nodes(void) time_call(fixup_usb_nodes); time_call(fixup_power_domains); } + +int ft_board_setup(void *blob, struct bd_info __maybe_unused *bd) +{ + struct fdt_header *fdt = blob; + int node; + + /* We only want to do this fix-up for the RB1 board, quick return for all others */ + if (!fdt_node_check_compatible(fdt, 0, "qcom,qrb4210-rb2")) + return 0; + + fdt_for_each_node_by_compatible(node, blob, 0, "snps,dwc3") { + log_debug("%s: Setting 'dr_mode' to OTG\n", fdt_get_name(blob, node, NULL)); + fdt_setprop_string(fdt, node, "dr_mode", "otg"); + break; + } + + return 0; +} diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 8f91db4b46b..589276282e4 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -17,6 +17,7 @@ config CMD_STM32PROG config CMD_STM32PROG_USB bool "support stm32prog over USB" depends on CMD_STM32PROG + depends on USB_GADGET_DOWNLOAD default y help activate the command "stm32prog usb" for STM32MP soc family diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index 857148747ef..ebae50f66c9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,7 +8,6 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..4f2379df45f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); bool iwdg1_wake = false; bool iwdg2_wake = false; bool other_wake = false; @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); } diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index afc56b02eea..d75ec99d6a1 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <linux/bitfield.h> /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* + * TAMP: Configure non-zero secure protection settings. This is + * checked by BootROM function 35ac on OTP-CLOSED device during + * CPU core 1 release from endless loop. If secure protection + * fields are zero, the core 1 is not released from endless + * loop on second SGI0. + */ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); @@ -322,8 +338,23 @@ void get_soc_name(char name[SOC_NAME_SIZE]) get_cpu_string_offsets(&type, &pkg, &rev); - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); + if (bsec_dbgswenable()) { + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); + } else { + /* + * SoC revision is only accessible via DBUMCU IDC register, + * which requires BSEC.DENABLE DBGSWENABLE bit to be set to + * make the register accessible, otherwise an access to the + * register triggers bus fault. As BSEC.DBGSWENABLE is zero + * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE + * bit as this might open a brief window for timing attacks. + * Instead, report that this system is OTP-CLOSED and do not + * report any SoC revision to avoid confusing users. + */ + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C", + soc_type[type], soc_pkg[pkg]); + } } static void setup_soc_type_pkg_rev(void) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index fe89aec6b9a..ddf9414b08e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1078,7 +1078,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 1d4c70ec352..3f83c0280ef 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -7,7 +7,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += board.o -obj-y += clock.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o @@ -31,6 +30,7 @@ obj-y += timer.o endif ifdef CONFIG_SPL_BUILD +obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index f4dbb2a740b..0140b07d32a 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -458,10 +458,8 @@ void board_init_f(ulong dummy) { sunxi_sram_init(); -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ tzpc_init(); -#endif clock_init(); timer_init(); diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index b6c68c94f67..5e9fa0d0748 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -23,10 +23,8 @@ __weak void gtbus_init(void) int clock_init(void) { -#ifdef CONFIG_SPL_BUILD clock_init_safe(); gtbus_init(); -#endif clock_init_uart(); clock_init_sec(); diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index ac3b7a801f4..6458d066f7e 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -43,7 +43,6 @@ void clock_init_safe(void) setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); #endif } -#endif void clock_init_uart(void) { @@ -77,7 +76,6 @@ int clock_twi_onoff(int port, int state) return 0; } -#ifdef CONFIG_SPL_BUILD #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ @@ -177,8 +175,9 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index dac3663e1be..cc2ee336416 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -51,7 +51,6 @@ void clock_init_safe(void) */ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); } -#endif void clock_init_uart(void) { @@ -73,7 +72,6 @@ void clock_init_uart(void) 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -105,33 +103,6 @@ void clock_set_pll1(unsigned int clk) val |= CCM_CPU_AXI_MUX_PLL_CPUX; writel(val, &ccm->cpu_axi_cfg); } -#endif - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; - int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> - CCM_PLL6_CTRL_DIV2_SHIFT) + 1; - int div1, m; - - if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { - div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> - CCM_PLL6_CTRL_P0_SHIFT) + 1; - m = 1; - } else { - div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> - CCM_PLL6_CTRL_DIV1_SHIFT) + 1; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) - m = 4; - else - m = 2; - } - - return 24000000U * n / m / div1 / div2; -} int clock_twi_onoff(int port, int state) { @@ -160,3 +131,31 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ + +/* PLL_PERIPH0 clock, used by the MMC driver */ +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + int div1, m; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> + CCM_PLL6_CTRL_P0_SHIFT) + 1; + m = 1; + } else { + div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + m = 4; + else + m = 2; + } + + return 24000000U * n / m / div1 / div2; +} diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index aad9df282ec..59f7e15ffe8 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -62,7 +62,6 @@ void clock_init_safe(void) setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); #endif } -#endif /* CONFIG_SPL_BUILD */ void clock_init_sec(void) { @@ -124,7 +123,6 @@ void clock_init_uart(void) #endif } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -173,6 +171,7 @@ void clock_set_pll1(unsigned int clk) } #endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 198fe9dbd73..9eeba084f95 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -46,7 +46,6 @@ void clock_init_safe(void) /* timestamp */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -70,7 +69,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -102,8 +100,9 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index edaff9a28ce..5913e40cb65 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -17,6 +17,52 @@ #ifdef CONFIG_SPL_BUILD +static void clock_set_pll2(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch cluster 1 to 24MHz clock while changing PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_OSC24M); + + writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | + CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), + &ccm->pll2_c1_cfg); + + sdelay(2000); + + /* Switch cluster 1 back to PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_PLL2); +} + +static void clock_set_pll4(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), + &ccm->pll4_periph0_cfg); + + sdelay(2000); +} + +static void clock_set_pll12(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) + return; + + writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), + &ccm->pll12_periph1_cfg); + + sdelay(2000); +} + void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -63,7 +109,6 @@ void clock_init_safe(void) /* set enable-bit in TSTAMP_CTRL_REG */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -80,7 +125,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -108,27 +152,6 @@ void clock_set_pll1(unsigned int clk) C0_CPUX_CLK_SRC_PLL1); } -void clock_set_pll2(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int p = 0; - - /* Switch cluster 1 to 24MHz clock while changing PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_OSC24M); - - writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | - CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), - &ccm->pll2_c1_cfg); - - sdelay(2000); - - /* Switch cluster 1 back to PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_PLL2); -} - void clock_set_pll6(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -143,32 +166,6 @@ void clock_set_pll6(unsigned int clk) sdelay(2000); } -void clock_set_pll12(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) - return; - - writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), - &ccm->pll12_periph1_cfg); - - sdelay(2000); -} - - -void clock_set_pll4(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), - &ccm->pll4_periph0_cfg); - - sdelay(2000); -} -#endif int clock_twi_onoff(int port, int state) { @@ -193,7 +190,9 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ +/* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 72faa7171c1..7acb44f52ae 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -72,18 +72,27 @@ #define SUN6I_CTL_ENABLE BIT(0) #define SUN6I_CTL_MASTER BIT(1) #define SUN6I_CTL_SRST BIT(31) +#define SUN6I_TCR_SDM BIT(13) #define SUN6I_TCR_XCH BIT(31) /*****************************************************************************/ -#define CCM_AHB_GATING0 (0x01C20000 + 0x60) -#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) -#ifdef CONFIG_SUN50I_GEN_H6 -#define CCM_SPI0_CLK (0x03001000 + 0x940) +#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) +#define CCM_BASE 0x03001000 +#elif IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) +#define CCM_BASE 0x02001000 #else -#define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#define CCM_BASE 0x01C20000 #endif -#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) + +#define CCM_AHB_GATING0 (CCM_BASE + 0x60) +#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c) +#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) +#define CCM_SPI0_CLK (CCM_BASE + 0x940) +#else +#define CCM_SPI0_CLK (CCM_BASE + 0xA0) +#endif +#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0) #define AHB_RESET_SPI0_SHIFT 20 #define AHB_GATE_OFFSET_SPI0 20 @@ -101,17 +110,22 @@ */ static void spi0_pinmux_setup(unsigned int pin_function) { - /* All chips use PC0 and PC2. */ - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + /* All chips use PC2. And all chips use PC0, except R528/T113 */ + if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - /* All chips except H6 and H616 use PC1. */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + /* All chips except H6/H616/R528/T113 use PC1. */ + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); /* Older generations use PC23 for CS, newer ones use PC3. */ @@ -125,7 +139,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6); + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2); } static uintptr_t spi0_base_address(void) @@ -136,6 +151,9 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) return 0x05010000; + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + return 0x04025000; + if (!is_sun6i_gen_spi() || IS_ENABLED(CONFIG_MACH_SUNIV)) return 0x01C05000; @@ -151,23 +169,30 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); if (IS_ENABLED(CONFIG_MACH_SUNIV)) { /* Divide by 32, clock source is AHB clock 200MHz */ writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL); } else { - /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + /* New SoCs do not have a clock divider inside */ + if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + /* Divide by 4 */ + writel(SPI0_CLK_DIV_BY_4, + base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : + SUN4I_SPI0_CCTL)); + } + /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); } @@ -179,6 +204,14 @@ static void spi0_enable_clock(void) /* Wait for completion */ while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; + + /* + * For new SoCs we should configure sample mode depending on + * input clock. As 24MHz from OSC24M is used, we could use + * normal sample mode by setting SDM bit in the TCR register + */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM); } else { /* Enable SPI in the master mode and reset FIFO */ setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | @@ -205,11 +238,13 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -223,7 +258,8 @@ static void spi0_init(void) if (IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6)) pin_function = SUN50I_GPC_SPI0; - else if (IS_ENABLED(CONFIG_MACH_SUNIV)) + else if (IS_ENABLED(CONFIG_MACH_SUNIV) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) pin_function = SUNIV_GPC_SPI0; spi0_pinmux_setup(pin_function); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 05e194de082..04612895576 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -219,6 +219,10 @@ config TEGRA_ENABLE_UARTC config TEGRA_ENABLE_UARTD bool "Use UARTD" +config TEGRA_ENABLE_UARTE + bool "Use UARTE" + depends on TEGRA20 || TEGRA30 + endchoice config TEGRA_GPU diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index 3ba33d27c17..58c89d5e645 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -225,7 +225,7 @@ #define VC3_MPAR_FAW VC3_MPAR_tFAW #define VC3_MPAR_BL 4 #define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9) -/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */ +/* ODT_RTT: "0x0040" for 120ohm, and "0x0004" for 60ohm. */ #define MSCC_MEMPARM_MR1 0x0040 #define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3) #define MSCC_MEMPARM_MR3 0 diff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h index ff32dab67b5..25e2877469a 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h @@ -267,7 +267,7 @@ void cvmx_helper_pki_set_fcs_op(int node, int interface, int nports, int has_fcs * buffer separate from the work queue entry. Words following the * WQE in the same cache line will be zeroed, other lines in the * buffer will not be modified and will retain stale data (from the - * buffer’s previous use). This setting may decrease the peak PKI + * buffer's previous use). This setting may decrease the peak PKI * performance by up to half on small packets. */ void cvmx_helper_pki_set_wqe_mode(int node, bool pkt_outside_wqe); diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pki.h b/arch/mips/mach-octeon/include/mach/cvmx-pki.h index c1feb55a1f0..d918f792eee 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-pki.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-pki.h @@ -110,8 +110,8 @@ enum cvmx_pki_wqe_vlan { CVMX_PKI_USE_FIRST_VLAN = 0, CVMX_PKI_USE_SECOND_VLAN } * Controls how the PKI statistics counters are handled * The PKI_STAT*_X registers can be indexed either by port kind (pkind), or * final style. (Does not apply to the PKI_STAT_INB* registers.) - * 0 = X represents the packet’s pkind - * 1 = X represents the low 6-bits of packet’s final style + * 0 = X represents the packet's pkind + * 1 = X represents the low 6-bits of packet's final style */ enum cvmx_pki_stats_mode { CVMX_PKI_STAT_MODE_PKIND, CVMX_PKI_STAT_MODE_STYLE }; @@ -880,7 +880,7 @@ int cvmx_pki_get_pkind_style(int node, int pkind); * buffer separate from the work queue entry. Words following the * WQE in the same cache line will be zeroed, other lines in the * buffer will not be modified and will retain stale data (from the - * buffer’s previous use). This setting may decrease the peak PKI + * buffer's previous use). This setting may decrease the peak PKI * performance by up to half on small packets. */ void cvmx_pki_set_wqe_mode(int node, u64 style, bool pkt_outside_wqe); diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pko3.h b/arch/mips/mach-octeon/include/mach/cvmx-pko3.h index 86f89be855f..bda607203f3 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-pko3.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-pko3.h @@ -366,7 +366,7 @@ enum cvmx_pko_memalg_e { */ MEMALG_SETRSLT = 2, /* [DSZ] = B64; mem = PKO_MEM_RESULT_S. */ MEMALG_ADD = 8, /* mem = mem + PKO_SEND_MEM_S[OFFSET] */ - MEMALG_SUB = 9, /* mem = mem – PKO_SEND_MEM_S[OFFSET] */ + MEMALG_SUB = 9, /* mem = mem - PKO_SEND_MEM_S[OFFSET] */ MEMALG_ADDLEN = 0xA, /* mem += [OFFSET] + PKO_SEND_HDR_S[TOTAL] */ MEMALG_SUBLEN = 0xB, /* mem -= [OFFSET] + PKO_SEND_HDR_S[TOTAL] */ MEMALG_ADDMBUF = 0xC, /* mem += [OFFSET] + mbufs_freed */ diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 12eae17c396..1095dc92c5a 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -98,6 +98,8 @@ int write_tables(void) int size = table->size ? : CONFIG_ROM_TABLE_SIZE; u32 rom_table_end; + rom_addr = ALIGN(rom_addr, 16); + if (!strcmp("smbios", table->name)) gd->arch.smbios_start = rom_addr; diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 1a2f60e3d19..00114e6d915 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -395,7 +395,7 @@ static void load_spi_dtb(void) return; /* - * SPI NOR "dtb" partition offset & size hardcoded for now because the + * SPI NOR "dtb" partition offset & size hardcoded for now because the * mtd subsystem does not offer finding the partition yet and we do not * want to reimplement OF partition parser here. */ diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c index 43d7a8e84f6..a4850364f41 100644 --- a/board/amlogic/vim3/vim3.c +++ b/board/amlogic/vim3/vim3.c @@ -89,7 +89,7 @@ int meson_ft_board_setup(void *blob, struct bd_info *bd) /* * If in PCIe mode, alter DT - * 0：Enable USB3.0，Disable PCIE, 1：Disable USB3.0, Enable PCIE + * 0: Enable USB3.0, Disable PCIE, 1: Disable USB3.0, Enable PCIE */ if (ret > 0) { static char data[32] __aligned(4); diff --git a/board/asus/transformer-t30/configs/p1801-t.config b/board/asus/transformer-t30/configs/p1801-t.config index fab2912132c..f378f54570d 100644 --- a/board/asus/transformer-t30/configs/p1801-t.config +++ b/board/asus/transformer-t30/configs/p1801-t.config @@ -1,2 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-p1801-t" +# CONFIG_I2C_MUX is not set CONFIG_USB_GADGET_PRODUCT_NUM=0x4cb0 diff --git a/board/asus/transformer-t30/configs/tf201.config b/board/asus/transformer-t30/configs/tf201.config index 296743b7748..e4fd30378a1 100644 --- a/board/asus/transformer-t30/configs/tf201.config +++ b/board/asus/transformer-t30/configs/tf201.config @@ -1,2 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201" +# CONFIG_I2C_MUX is not set CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf300t.config b/board/asus/transformer-t30/configs/tf300t.config index 32a92fe76fa..9ad2ebd98e8 100644 --- a/board/asus/transformer-t30/configs/tf300t.config +++ b/board/asus/transformer-t30/configs/tf300t.config @@ -1,2 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300t" +# CONFIG_I2C_MUX is not set CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf300tg.config b/board/asus/transformer-t30/configs/tf300tg.config index 1396294f6de..7b44a91acc4 100644 --- a/board/asus/transformer-t30/configs/tf300tg.config +++ b/board/asus/transformer-t30/configs/tf300tg.config @@ -1,2 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tg" +# CONFIG_I2C_MUX is not set CONFIG_USB_GADGET_PRODUCT_NUM=0x4c80 diff --git a/board/asus/transformer-t30/configs/tf300tl.config b/board/asus/transformer-t30/configs/tf300tl.config index 3db033c8df4..81e96d5df6f 100644 --- a/board/asus/transformer-t30/configs/tf300tl.config +++ b/board/asus/transformer-t30/configs/tf300tl.config @@ -1,2 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tl" +# CONFIG_I2C_MUX is not set CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config index e40d0fdd479..b3734869f59 100644 --- a/board/asus/transformer-t30/configs/tf600t.config +++ b/board/asus/transformer-t30/configs/tf600t.config @@ -1,4 +1,6 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t" CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +# CONFIG_I2C_MUX is not set +CONFIG_TEGRA20_SLINK=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf700t.config b/board/asus/transformer-t30/configs/tf700t.config index 066c884d082..887c25fbf22 100644 --- a/board/asus/transformer-t30/configs/tf700t.config +++ b/board/asus/transformer-t30/configs/tf700t.config @@ -1,2 +1,4 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf700t" +CONFIG_CLK_GPIO=y CONFIG_USB_GADGET_PRODUCT_NUM=0x4c90 +CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index 34088adee47..65c2f356713 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -437,7 +437,7 @@ static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = { .trcd = 1313, // 13.125ns .trcmin = 5063, // 50.625ns .trasmin = 3750, // 37.5ns - .SRT = 0, // Set to 1 for temperatures above 85°C + .SRT = 0, // Set to 1 for temperatures above 85 deg C }; static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = { diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index 962a485acd2..aebdfd4dfec 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -115,7 +115,7 @@ static void __maybe_unused force_modules_running(void) gpio_direction_output(WIFI_REGEN_GPIO, 1); /* * Wait for Wi-Fi power regulator to reach a stable voltage - * (soft-start time, max. 350 µs) + * (soft-start time, max. 350 us) */ __udelay(350); diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h index 4cc02f93c64..a5e58186c9c 100644 --- a/board/bosch/shc/board.h +++ b/board/bosch/shc/board.h @@ -154,7 +154,7 @@ static inline int board_is_series(void) #define HDR_FATC_LEN 12 /* -* SHC parameters held in On-Board I²C EEPROM device. +* SHC parameters held in On-Board I2C EEPROM device. * * Header Format * diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index 3b01354bb6b..d8e5b1d6963 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -171,7 +171,7 @@ int board_mmc_init(struct bd_info *bis) * (U-Boot device node) (Physical Port) * mmc0 (onboard eMMC) USDHC1 * mmc1 (external SD card) USDHC2 - * mmc2 (onboard µSD) USDHC3 + * mmc2 (onboard uSD) USDHC3 */ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { @@ -196,7 +196,7 @@ int board_mmc_init(struct bd_info *bis) gpio_direction_input(USDHC1_CD_GPIO); break; case 2: - /* onboard µSD */ + /* onboard uSD */ if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd)) power_domain_on(&pd); diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 079dfff0389..22af423536d 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -48,12 +48,10 @@ /* SYSCFG registers */ #define SYSCFG_BOOTR 0x00 -#define SYSCFG_PMCSETR 0x04 #define SYSCFG_IOCTRLSETR 0x18 #define SYSCFG_ICNR 0x1C #define SYSCFG_CMPCR 0x20 #define SYSCFG_CMPENSETR 0x24 -#define SYSCFG_PMCCLRR 0x44 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 @@ -69,16 +67,6 @@ #define SYSCFG_CMPENSETR_MPU_EN BIT(0) -#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) -#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) - -#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) - -#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) - #define KS_CCR 0x08 #define KS_CCR_EEPROM BIT(9) #define KS_BE0 BIT(12) @@ -685,76 +673,6 @@ void board_quiesce_devices(void) #endif } -/* eth init function : weak called in eqos driver */ -int board_interface_eth_init(struct udevice *dev, - phy_interface_t interface_type) -{ - u8 *syscfg; - u32 value; - bool eth_clk_sel_reg = false; - bool eth_ref_clk_sel_reg = false; - - /* Gigabit Ethernet 125MHz clock selection. */ - eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); - - /* Ethernet 50Mhz RMII clock selection */ - eth_ref_clk_sel_reg = - dev_read_bool(dev, "st,eth-ref-clk-sel"); - - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); - - if (!syscfg) - return -ENODEV; - - switch (interface_type) { - case PHY_INTERFACE_MODE_MII: - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; - debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); - break; - case PHY_INTERFACE_MODE_GMII: - if (eth_clk_sel_reg) - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | - SYSCFG_PMCSETR_ETH_CLK_SEL; - else - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; - debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); - break; - case PHY_INTERFACE_MODE_RMII: - if (eth_ref_clk_sel_reg) - value = SYSCFG_PMCSETR_ETH_SEL_RMII | - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; - else - value = SYSCFG_PMCSETR_ETH_SEL_RMII; - debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - if (eth_clk_sel_reg) - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | - SYSCFG_PMCSETR_ETH_CLK_SEL; - else - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; - debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); - break; - default: - debug("%s: Do not manage %d interface\n", - __func__, interface_type); - /* Do not manage others interfaces */ - return -EINVAL; - } - - /* clear and set ETH configuration bits */ - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, - syscfg + SYSCFG_PMCCLRR); - writel(value, syscfg + SYSCFG_PMCSETR); - - return 0; -} - #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/firefly/firefly-rk3308/MAINTAINERS b/board/firefly/firefly-rk3308/MAINTAINERS index e584038a203..b70ff52ea74 100644 --- a/board/firefly/firefly-rk3308/MAINTAINERS +++ b/board/firefly/firefly-rk3308/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/firefly/firefly-rk3308/ F: configs/roc-cc-rk3308_defconfig F: include/configs/firefly_rk3308.h +F: arch/arm/dts/rk3308-roc-cc* diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index 99a52a77116..af00250e118 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -5,7 +5,7 @@ #include <common.h> #include <adc.h> -#include <asm/arch/grf_rk3308.h> +#include <asm/arch-rockchip/grf_rk3308.h> #include <asm/arch-rockchip/hardware.h> #include <linux/bitops.h> diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c index 54f89e25760..d40b34f1039 100644 --- a/board/freescale/common/i2c_mux.c +++ b/board/freescale/common/i2c_mux.c @@ -12,7 +12,7 @@ /* * A new Kconfig option for something that used to always be built should be - * “default y”. + * "default y". */ #ifdef CONFIG_FSL_USE_PCA9547_MUX diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 7331a20f94c..6d5e110b277 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -120,8 +120,8 @@ void board_init_f(ulong dummy) if (ret) { printf("Fail to init Sentinel API\n"); } else { - printf("SOC: 0x%x\n", gd->arch.soc_rev); - printf("LC: 0x%x\n", gd->arch.lifecycle); + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); } power_init_board(); diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile deleted file mode 100644 index c1c49b19708..00000000000 --- a/board/friendlyelec/nanopc-t6-rk3588/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. -# - -obj-y += nanopc-t6-rk3588.o diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c deleted file mode 100644 index 99bbef964e0..00000000000 --- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - unsigned int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return nanopc_t6_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index f54f1186b68..5b105d7659e 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -230,6 +230,7 @@ uint mmc_get_env_part(struct mmc *mmc) int ft_board_setup(void *fdt, struct bd_info *bd) { const char *base_model = eeprom_get_baseboard_model(); + const char *path; char pcbrev; int off; @@ -238,10 +239,10 @@ int ft_board_setup(void *fdt, struct bd_info *bd) if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); + path = fdt_get_alias(fdt, "ethernet1"); - if (pcbrev > 'B' && pcbrev < 'E') { - printf("adjusting dt for %s\n", base_model); - + if (pcbrev > 'B' && pcbrev < 'E' && path && !strncmp(path, "/soc@0/pcie@", 12)) { + printf("adjusting %s pcie\n", base_model); /* * revC/D/E has PCIe 4-port switch which changes * ethernet1 PCIe GbE: diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index ffaf517a8bb..80acde74956 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -47,15 +47,14 @@ int board_fit_config_name_match(const char *name) switch (variant) { case 1: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var1"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var1"); case 2: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var2"); - case 3: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var2"); case 4: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var4"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var4"); + case 3: default: - return strcmp(name, "fsl-ls1028a-kontron-sl28"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28"); } } diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index f03bfee9ffa..5efa38a1442 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -126,8 +126,8 @@ void board_init_f(ulong dummy) if (ret) { printf("Fail to init ELE API\n"); } else { - printf("SOC: 0x%x\n", gd->arch.soc_rev); - printf("LC: 0x%x\n", gd->arch.lifecycle); + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); } clock_init(); diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile deleted file mode 100644 index 47819d9be93..00000000000 --- a/board/pine64/quartzpro64-rk3588/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y += quartzpro64-rk3588.o diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c deleted file mode 100644 index bda804a89e2..00000000000 --- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2023 Google, Inc - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - unsigned int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return quartzpro64_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/radxa/rock2/MAINTAINERS b/board/radxa/rock2/MAINTAINERS index 5328fd76014..af974c98304 100644 --- a/board/radxa/rock2/MAINTAINERS +++ b/board/radxa/rock2/MAINTAINERS @@ -1,9 +1,7 @@ FIREFLY M: Simon Glass <sjg@chromium.org> S: Maintained -F: arch/arm/dts/rk3288-rock2-som.dtsi -F: arch/arm/dts/rk3288-rock2-square.dts -F: arch/arm/dts/rk3288-rock2-square-u-boot.dtsi +F: arch/arm/dts/rk3288-rock2* F: board/radxa/rock2 F: include/configs/rock2.h F: configs/rock2_defconfig diff --git a/board/radxa/rock5a-rk3588s/Makefile b/board/radxa/rock5a-rk3588s/Makefile deleted file mode 100644 index 48dd5124550..00000000000 --- a/board/radxa/rock5a-rk3588s/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2023 Collabora Ltd. -# - -obj-y += rock5a-rk3588s.o diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c deleted file mode 100644 index 2d7a8c07dc5..00000000000 --- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2023 Collabora Ltd. - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -int rock5a_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - unsigned int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return rock5a_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/radxa/rock5b-rk3588/Makefile b/board/radxa/rock5b-rk3588/Makefile deleted file mode 100644 index 95d813596da..00000000000 --- a/board/radxa/rock5b-rk3588/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2022 Collabora Ltd. -# - -obj-y += rock5b-rk3588.o diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c deleted file mode 100644 index 5c3b52b9489..00000000000 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2023 Collabora Ltd. - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -int rock5b_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - unsigned int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return rock5b_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/rockchip/evb_rk3308/MAINTAINERS b/board/rockchip/evb_rk3308/MAINTAINERS index fe2c5f004c3..abffbb1eb0a 100644 --- a/board/rockchip/evb_rk3308/MAINTAINERS +++ b/board/rockchip/evb_rk3308/MAINTAINERS @@ -4,10 +4,11 @@ S: Maintained F: board/rockchip/evb_rk3308 F: include/configs/evb_rk3308.h F: configs/evb-rk3308_defconfig +F: arch/arm/dts/rk3308-evb* ROCK-PI-S M: Akash Gajjar <gajjar04akash@gmail.com> +R: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: configs/rock-pi-s-rk3308_defconfig -F: arch/arm/dts/rk3308-rock-pi-s.dts -F: arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +F: arch/arm/dts/rk3308-rock-pi-s* diff --git a/board/rockchip/evb_rk3588/Makefile b/board/rockchip/evb_rk3588/Makefile deleted file mode 100644 index 240d2ec597e..00000000000 --- a/board/rockchip/evb_rk3588/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. -# - -obj-y += evb-rk3588.o diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c b/board/rockchip/evb_rk3588/evb-rk3588.c deleted file mode 100644 index caf94d8d29c..00000000000 --- a/board/rockchip/evb_rk3588/evb-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - unsigned int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return rk3588_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/rockchip/toybrick_rk3588/Makefile b/board/rockchip/toybrick_rk3588/Makefile deleted file mode 100644 index 75d4d9438f7..00000000000 --- a/board/rockchip/toybrick_rk3588/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2024 Rockchip Electronics Co,. Ltd. -# - -obj-y += toybrick-rk3588.o diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c deleted file mode 100644 index e3217f70b50..00000000000 --- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2024 Rockchip Electronics Co,. Ltd. - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return rk3588_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/schneider/hmibsc/MAINTAINERS b/board/schneider/hmibsc/MAINTAINERS new file mode 100644 index 00000000000..0f31bbda966 --- /dev/null +++ b/board/schneider/hmibsc/MAINTAINERS @@ -0,0 +1,6 @@ +HMIBSC BOARD +M: Sumit Garg <sumit.garg@linaro.org> +S: Maintained +F: board/schneider/hmibsc/ +F: include/configs/hmibsc.h +F: configs/hmibsc_defconfig diff --git a/board/schneider/hmibsc/hmibsc.env b/board/schneider/hmibsc/hmibsc.env new file mode 100644 index 00000000000..da3d892f91d --- /dev/null +++ b/board/schneider/hmibsc/hmibsc.env @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +loadaddr=0x90000000 +bootcmd= + echo "Booting RAUC A/B system"; + setenv devtype mmc; setenv devnum 0; + test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"; + test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3; + test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3; + setenv raucslot; + for BOOT_SLOT in "${BOOT_ORDER}"; do + if test "x${raucslot}" != "x"; then + echo "skip remaining slots..."; + elif test "x${BOOT_SLOT}" = "xA"; then + if test ${BOOT_A_LEFT} -gt 0; then + setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1; + echo "Found valid RAUC slot A"; + setenv raucslot "rauc.slot=A"; + setenv raucpart A; setenv distro_bootpart 6; + fi; + elif test "x${BOOT_SLOT}" = "xB"; then + if test ${BOOT_B_LEFT} -gt 0; then + setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1; + echo "Found valid RAUC slot B"; + setenv raucslot "rauc.slot=B"; + setenv raucpart B; setenv distro_bootpart 7; + fi; + fi; + done; + if test -n "${raucslot}"; then + setenv bootargs console=ttyMSM1 root=PARTLABEL=rootfs_${raucpart} rw rootwait ${raucslot}; + saveenv; + else + echo "No valid RAUC slot found. Resetting tries to 3"; + setenv BOOT_A_LEFT 3; + setenv BOOT_B_LEFT 3; + saveenv; + reset; + fi; + load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} /boot/fitImage && bootm; diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 0d66a75bbfa..b1d7e3b1c05 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -156,14 +156,14 @@ int setup_gpr_fec(void) * 0: internal clock * 1: external clock ---> your choice for RMII * - * CLKDIV_SEL: it controls a div by 2 on the internal clock path à - * it should be don’t care when using external clock + * CLKDIV_SEL: it controls a div by 2 on the internal clock path a + * it should be don't care when using external clock * 0: non-divided clock * 1: clock divided by 2 * 50_DISABLE or 125_DISABLE: - * it’s used to disable the clock tree going outside the chip + * it's used to disable the clock tree going outside the chip * when reference clock is generated internally. - * It should be don’t care when reference clock is provided + * It should be don't care when reference clock is provided * externally. * 0: clock is enabled * 1: clock is disabled diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index cb103e69b36..c8c0bad5da1 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -9,7 +9,7 @@ * - "Commercial Product Name" (CPN): type of product board (DKX, EVX) * associated to the board ID "MBxxxx" * - "Finished Good" or "Finish Good" (FG): - * effective content of the product without chip STM32MP1xx (LCD, Wifi,…) + * effective content of the product without chip STM32MP1xx (LCD, Wifi,...) * - BOM: cost variant for same FG (for example, several provider of the same * component) * diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index a17c314daeb..db15d78237e 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -8,6 +8,7 @@ #include <common.h> #include <adc.h> #include <bootm.h> +#include <button.h> #include <clk.h> #include <config.h> #include <dm.h> @@ -38,6 +39,7 @@ #include <asm/gpio.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> +#include <dm/device-internal.h> #include <dm/ofnode.h> #include <jffs2/load_kernel.h> #include <linux/bitops.h> @@ -52,12 +54,10 @@ /* SYSCFG registers */ #define SYSCFG_BOOTR 0x00 -#define SYSCFG_PMCSETR 0x04 #define SYSCFG_IOCTRLSETR 0x18 #define SYSCFG_ICNR 0x1C #define SYSCFG_CMPCR 0x20 #define SYSCFG_CMPENSETR 0x24 -#define SYSCFG_PMCCLRR 0x44 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 @@ -73,16 +73,6 @@ #define SYSCFG_CMPENSETR_MPU_EN BIT(0) -#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) -#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) - -#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) - -#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) - #define USB_LOW_THRESHOLD_UV 200000 #define USB_WARNING_LOW_THRESHOLD_UV 660000 #define USB_START_LOW_THRESHOLD_UV 1230000 @@ -150,45 +140,55 @@ int checkboard(void) static void board_key_check(void) { - ofnode node; - struct gpio_desc gpio; + struct udevice *button1 = NULL, *button2 = NULL; enum forced_boot_mode boot_mode = BOOT_NORMAL; + int ret; + + if (!IS_ENABLED(CONFIG_BUTTON)) + return; if (!IS_ENABLED(CONFIG_FASTBOOT) && !IS_ENABLED(CONFIG_CMD_STM32PROG)) return; - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - log_debug("no /config node?\n"); + if (IS_ENABLED(CONFIG_CMD_STM32PROG)) + button_get_by_label("User-1", &button1); + + if (IS_ENABLED(CONFIG_FASTBOOT)) + button_get_by_label("User-2", &button2); + + if (!button1 && !button2) return; - } - if (IS_ENABLED(CONFIG_FASTBOOT)) { - if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, - &gpio, GPIOD_IS_IN)) { - log_debug("could not find a /config/st,fastboot-gpios\n"); - } else { - udelay(20); - if (dm_gpio_get_value(&gpio)) { - log_notice("Fastboot key pressed, "); - boot_mode = BOOT_FASTBOOT; - } - dm_gpio_free(NULL, &gpio); + if (button2) { + if (button_get_state(button2) == BUTTON_ON) { + log_notice("Fastboot key pressed, "); + boot_mode = BOOT_FASTBOOT; } + /* + * On some boards, same gpio is shared betwwen gpio-keys and + * leds, remove the button device to free the gpio for led + * usage + */ + ret = device_remove(button2, DM_REMOVE_NORMAL); + if (ret) + log_err("Can't remove button2 (%d)\n", ret); } - if (IS_ENABLED(CONFIG_CMD_STM32PROG)) { - if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, - &gpio, GPIOD_IS_IN)) { - log_debug("could not find a /config/st,stm32prog-gpios\n"); - } else { - udelay(20); - if (dm_gpio_get_value(&gpio)) { - log_notice("STM32Programmer key pressed, "); - boot_mode = BOOT_STM32PROG; - } - dm_gpio_free(NULL, &gpio); + + if (button1) { + if (button_get_state(button1) == BUTTON_ON) { + log_notice("STM32Programmer key pressed, "); + boot_mode = BOOT_STM32PROG; } + /* + * On some boards, same gpio is shared betwwen gpio-keys and + * leds, remove the button device to free the gpio for led + * usage + */ + ret = device_remove(button1, DM_REMOVE_NORMAL); + if (ret) + log_err("Can't remove button1 (%d)\n", ret); } + if (boot_mode != BOOT_NORMAL) { log_notice("entering download mode...\n"); clrsetbits_le32(TAMP_BOOT_CONTEXT, @@ -742,76 +742,6 @@ void board_quiesce_devices(void) setup_led(LEDST_OFF); } -/* eth init function : weak called in eqos driver */ -int board_interface_eth_init(struct udevice *dev, - phy_interface_t interface_type) -{ - u8 *syscfg; - u32 value; - bool eth_clk_sel_reg = false; - bool eth_ref_clk_sel_reg = false; - - /* Gigabit Ethernet 125MHz clock selection. */ - eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); - - /* Ethernet 50Mhz RMII clock selection */ - eth_ref_clk_sel_reg = - dev_read_bool(dev, "st,eth-ref-clk-sel"); - - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); - - if (!syscfg) - return -ENODEV; - - switch (interface_type) { - case PHY_INTERFACE_MODE_MII: - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; - log_debug("PHY_INTERFACE_MODE_MII\n"); - break; - case PHY_INTERFACE_MODE_GMII: - if (eth_clk_sel_reg) - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | - SYSCFG_PMCSETR_ETH_CLK_SEL; - else - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; - log_debug("PHY_INTERFACE_MODE_GMII\n"); - break; - case PHY_INTERFACE_MODE_RMII: - if (eth_ref_clk_sel_reg) - value = SYSCFG_PMCSETR_ETH_SEL_RMII | - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; - else - value = SYSCFG_PMCSETR_ETH_SEL_RMII; - log_debug("PHY_INTERFACE_MODE_RMII\n"); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - if (eth_clk_sel_reg) - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | - SYSCFG_PMCSETR_ETH_CLK_SEL; - else - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; - log_debug("PHY_INTERFACE_MODE_RGMII\n"); - break; - default: - log_debug("Do not manage %d interface\n", - interface_type); - /* Do not manage others interfaces */ - return -EINVAL; - } - - /* clear and set ETH configuration bits */ - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, - syscfg + SYSCFG_PMCCLRR); - writel(value, syscfg + SYSCFG_PMCSETR); - - return 0; -} - enum env_location env_get_location(enum env_operation op, int prio) { u32 bootmode = get_bootmode(); diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index ddef7d61235..5095a0e9fdb 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -503,7 +503,7 @@ int mac_read_from_eeprom(void) * "<product>-<date>-<DDR&eMMC>-<serial_number>" * <date>: 4Byte, should be the output of `date +%y%W` * <DDR&eMMC>: 8Byte, "D008" means 8GB, "D01T" means 1TB; - * "E000" means no eMMC，"E032" means 32GB, "E01T" means 1TB. + * "E000" means no eMMC, "E032" means 32GB, "E01T" means 1TB. * <serial_number>: 8Byte, the Unique Identifier of board in hex. */ if (!env_get("serial#")) @@ -533,7 +533,7 @@ u8 get_pcb_revision_from_eeprom(void) * get_ddr_size_from_eeprom - get the DDR size * pstr: VF7110A1-2228-D008E000-00000001 * VF7110A1/VF7110B1 : VisionFive JH7110A /VisionFive JH7110B - * D008: 8GB LPDDR4 + * D008: 8GB LPDDR4 * E000: No emmc device, ECxx: include emmc device, xx: Capacity size[GB] * return: the field of 'D008E000' */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 8c12c8deade..1313b01dcea 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -186,7 +186,7 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_UNKNOWN; } -/* add board specific code here */ +/* called only from U-Boot proper */ int board_init(void) { __maybe_unused int id_pfr1, ret; @@ -226,13 +226,6 @@ int board_init(void) if (ret) return ret; -#if CONFIG_IS_ENABLED(DM_I2C) - /* - * Temporary workaround for enabling I2C clocks until proper sunxi DM - * clk, reset and pinctrl drivers land. - */ - i2c_init_board(); -#endif eth_init_board(); return 0; diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c index bfebfe5136d..c48de7345f7 100644 --- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c @@ -58,9 +58,9 @@ void spl_board_init(void) mdelay(1); - ret = gpio_direction_output(STM32_RST, 1); + ret = gpio_direction_input(STM32_RST); if (ret) { - debug("Failed to configure STM32_RST as output high\n"); + debug("Failed to configure STM32_RST as input\n"); return; } } diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index 814374d68cf..631997e4c97 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -27,3 +27,7 @@ get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt} args_ubi=setenv bootargs console=${console} ${optargs} rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs +#if CONFIG_TI_ICSSG_PRUETH +storage_interface=mmc +fw_dev_part=1:2 +#endif diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 3109c9a2aca..07073a5940b 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -91,10 +91,13 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { -#ifdef CONFIG_TARGET_AM654_A53_EVM - if (!strcmp(name, "k3-am654-base-board")) + if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH) && + strcmp(name, "k3-am654-icssg2") == 0) + return 0; + + if (IS_ENABLED(CONFIG_TARGET_AM654_A53_EVM) && + strcmp(name, "k3-am654-base-board") == 0) return 0; -#endif return -1; } diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 9dc3ed6dfff..539eaf47186 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -465,10 +465,13 @@ void spl_board_init(void) } if (IS_ENABLED(CONFIG_ESM_K3)) { - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(k3_esm), &dev); + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@700000", &dev); + if (ret) + printf("MISC init for esm@700000 failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@40800000", &dev); if (ret) - printf("ESM init failed: %d\n", ret); + printf("MISC init for esm@40800000 failed: %d\n", ret); } if (IS_ENABLED(CONFIG_ESM_PMIC)) { diff --git a/board/turing/turing-rk1-rk3588/Makefile b/board/turing/turing-rk1-rk3588/Makefile deleted file mode 100644 index a979d8023aa..00000000000 --- a/board/turing/turing-rk1-rk3588/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. -# - -obj-y += turing-rk1-rk3588.o diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c deleted file mode 100644 index e2338a2a35a..00000000000 --- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. - */ - -#include <fdtdec.h> -#include <fdt_support.h> - -#ifdef CONFIG_OF_BOARD_SETUP -int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob) -{ - struct fdt_memory gap1 = { - .start = 0x3fc000000, - .end = 0x3fc4fffff, - }; - struct fdt_memory gap2 = { - .start = 0x3fff00000, - .end = 0x3ffffffff, - }; - unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - unsigned int ret; - - /* - * Inject the reserved-memory nodes into the DTS - */ - ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, - NULL, flags); - if (ret) - return ret; - - return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, - NULL, flags); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return turing_rk1_add_reserved_memory_fdt_nodes(blob); -} -#endif diff --git a/board/variscite/imx93_var_som/spl.c b/board/variscite/imx93_var_som/spl.c index 71f346cf77b..8852aea156b 100644 --- a/board/variscite/imx93_var_som/spl.c +++ b/board/variscite/imx93_var_som/spl.c @@ -125,8 +125,8 @@ void board_init_f(ulong dummy) if (ret) { printf("Fail to init ELE API\n"); } else { - printf("SOC: 0x%x\n", gd->arch.soc_rev); - printf("LC: 0x%x\n", gd->arch.lifecycle); + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); } power_init_board(); diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c index 069ced75a7f..837920bd3a3 100644 --- a/boot/fdt_simplefb.c +++ b/boot/fdt_simplefb.c @@ -12,6 +12,8 @@ #include <asm/global_data.h> #include <linux/libfdt.h> #include <video.h> +#include <spl.h> +#include <bloblist.h> DECLARE_GLOBAL_DATA_PTR; @@ -26,15 +28,29 @@ static int fdt_simplefb_configure_node(void *blob, int off) struct udevice *dev; int ret; - ret = uclass_first_device_err(UCLASS_VIDEO, &dev); - if (ret) - return ret; - uc_priv = dev_get_uclass_priv(dev); - plat = dev_get_uclass_plat(dev); - xsize = uc_priv->xsize; - ysize = uc_priv->ysize; - bpix = uc_priv->bpix; - fb_base = plat->base; + if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) { + struct video_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing video bloblist", -ENOENT); + + xsize = ho->xsize; + ysize = ho->ysize; + bpix = ho->bpix; + fb_base = ho->fb; + } else { + ret = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (ret) + return ret; + uc_priv = dev_get_uclass_priv(dev); + plat = dev_get_uclass_plat(dev); + xsize = uc_priv->xsize; + ysize = uc_priv->ysize; + bpix = uc_priv->bpix; + fb_base = plat->base; + } + switch (bpix) { case 4: /* VIDEO_BPP16 */ name = "r5g6b5"; @@ -91,7 +107,6 @@ static int fdt_simplefb_enable_existing_node(void *blob) #if IS_ENABLED(CONFIG_VIDEO) int fdt_simplefb_enable_and_mem_rsv(void *blob) { - struct fdt_memory mem; int ret; /* nothing to do when video is not active */ @@ -102,15 +117,6 @@ int fdt_simplefb_enable_and_mem_rsv(void *blob) if (ret) return ret; - /* nothing to do when the frame buffer is not defined */ - if (gd->video_bottom == gd->video_top) - return 0; - - /* reserved with no-map tag the video buffer */ - mem.start = gd->video_bottom; - mem.end = gd->video_top - 1; - - return fdtdec_add_reserved_memory(blob, "framebuffer", &mem, NULL, 0, NULL, - FDTDEC_RESERVED_MEMORY_NO_MAP); + return fdt_add_fb_mem_rsv(blob); } #endif diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 9844c70be80..2bd80a9dfb1 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -23,6 +23,9 @@ #include <exports.h> #include <fdtdec.h> #include <version.h> +#include <video.h> + +DECLARE_GLOBAL_DATA_PTR; /** * fdt_getprop_u32_default_node - Return a node's property or a default @@ -2043,6 +2046,24 @@ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, return 0; } +#if CONFIG_IS_ENABLED(VIDEO) +int fdt_add_fb_mem_rsv(void *blob) +{ + struct fdt_memory mem; + + /* nothing to do when the frame buffer is not defined */ + if (gd->video_bottom == gd->video_top) + return 0; + + /* reserved with no-map tag the video buffer */ + mem.start = gd->video_bottom; + mem.end = gd->video_top - 1; + + return fdtdec_add_reserved_memory(blob, "framebuffer", &mem, NULL, 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); +} +#endif + /* * Update native-mode in display-timings from display environment variable. * The node to update are specified by path. diff --git a/cmd/Kconfig b/cmd/Kconfig index 42757e0cdf1..b026439c773 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -446,7 +446,7 @@ config CMD_BOOTEFI_HELLO for testing that EFI is working at a basic level, and for bringing up EFI support on a new architecture. -source lib/efi_selftest/Kconfig +source "lib/efi_selftest/Kconfig" endif config CMD_BOOTMENU @@ -741,7 +741,8 @@ config CMD_BINOP config CMD_BLOBLIST bool "bloblist" - default y if BLOBLIST + depends on BLOBLIST + default y help Show information about the bloblist, a collection of binary blobs held in memory that persist between SPL and U-Boot. In the case of diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 8234e602b8f..0ba92c60e03 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -1419,7 +1419,7 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo } bo->initrd_info.current_path = calloc(1, EFICONFIG_FILE_PATH_BUF_SIZE); - if (!bo->file_info.current_path) { + if (!bo->initrd_info.current_path) { ret = EFI_OUT_OF_RESOURCES; goto out; } diff --git a/common/Kconfig b/common/Kconfig index 0283701f1d0..5e3070e9253 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -231,7 +231,7 @@ config PRE_CON_BUF_ADDR default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I default 0x0f000000 if ROCKCHIP_RK3288 - default 0x0f200000 if ROCKCHIP_RK3399 + default 0x0f200000 if ROCKCHIP_RK3399 || ROCKCHIP_RK3328 help This sets the start address of the pre-console buffer. This must be in available memory and is accessed before relocation and diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 977daf9f090..c4625bf132d 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -6,7 +6,6 @@ CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFKW/kwbimage.cfg" CONFIG_TEXT_BASE=0x00600000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -# CONFIG_OF_UPSTREAM is not set CONFIG_TARGET_SBx81LIFKW=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 @@ -36,6 +35,7 @@ CONFIG_CMD_SNTP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y +# CONFIG_OF_UPSTREAM is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=20000000 diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 9bc86140302..01e50af94d6 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -6,7 +6,6 @@ CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg" CONFIG_TEXT_BASE=0x00600000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -# CONFIG_OF_UPSTREAM is not set CONFIG_TARGET_SBx81LIFXCAT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 @@ -37,6 +36,7 @@ CONFIG_CMD_SNTP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y +# CONFIG_OF_UPSTREAM is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=20000000 diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig index 9050e325e6c..a8f3c00066e 100644 --- a/configs/ae350_rv32_falcon_defconfig +++ b/configs/ae350_rv32_falcon_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -25,7 +26,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000 diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig index bebdef57c9b..0f9a7b0f4c9 100644 --- a/configs/ae350_rv32_falcon_xip_defconfig +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -26,7 +27,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000 diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 321025b7452..76711b96400 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -25,7 +26,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 0ca40a520f3..39db36c3f6c 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -26,7 +27,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig index 423fa7ba6e8..1cd978e4229 100644 --- a/configs/ae350_rv64_falcon_defconfig +++ b/configs/ae350_rv64_falcon_defconfig @@ -7,6 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -25,7 +26,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000 diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig index 6ddb81b5648..7a1f880e059 100644 --- a/configs/ae350_rv64_falcon_xip_defconfig +++ b/configs/ae350_rv64_falcon_xip_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -26,7 +27,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index e274f8975c2..c70413c8ba7 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -7,6 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -25,7 +26,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 0f7fb71f22b..279923cb832 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -26,7 +27,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index abbbb03d33d..75138542431 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -16,7 +16,6 @@ CONFIG_AM335X_USB1=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x44E3E000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x540000 CONFIG_SPL_LIBDISK_SUPPORT=y diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 41ffcfdcd5e..c4556f5dd2e 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -15,6 +15,10 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -25,11 +29,7 @@ CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 8dd8f0823eb..44ccb6baa90 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -17,6 +17,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y @@ -28,12 +32,8 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c3b000 -CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 638d2e90a6b..9f40c9a0b3c 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -114,6 +114,8 @@ CONFIG_FS_LOADER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 25505167f01..b365c7ea902 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -20,6 +19,11 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3C000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 CONFIG_SPL_FS_FAT=y @@ -33,24 +37,14 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c4b000 -CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 147967d3c11..4f1be1df593 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -17,6 +17,10 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80c80000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 CONFIG_SPL_FS_FAT=y @@ -34,12 +38,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80c80000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" @@ -91,9 +91,9 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y +CONFIG_DM_ETH_PHY=y CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PHY=y -CONFIG_DM_ETH_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 9413c859870..d0cc4f5b405 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -20,6 +20,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y @@ -32,13 +36,9 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c3b000 -CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 6b37f8b4791..6c708dcb052 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -52,8 +52,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MMC=y -CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_EFIDEBUG=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 3e4d3a76628..4b2e57b13a0 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -22,6 +22,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y @@ -35,12 +39,8 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c3b000 -CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 4a3780ce660..96475d4c1b8 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -22,6 +22,11 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x7019b800 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x400000 CONFIG_SPL_SIZE_LIMIT=0x190000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -36,14 +41,9 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x180000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x7019b800 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x400000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 3afa80f45a8..ee79adef699 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -22,6 +22,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_ENV_OFFSET_REDUND=0x6A0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -37,11 +41,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y @@ -68,6 +68,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" @@ -129,6 +130,7 @@ CONFIG_PHY_FIXED=y CONFIG_E1000=y CONFIG_CMD_E1000=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PCI_KEYSTONE=y CONFIG_PHY=y CONFIG_SPL_PHY=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index d6e85db0869..4fc9c39711c 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -21,6 +21,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y @@ -35,11 +39,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c7effc -CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 09f0c6af8c3..953487ccfbf 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -19,6 +19,10 @@ CONFIG_DM_RESET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_LIBDISK_SUPPORT=y @@ -31,11 +35,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c7effc -CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 4d95ab6f83d..01517619272 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -19,6 +19,10 @@ CONFIG_DM_RESET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y @@ -31,11 +35,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c7effc -CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index c8c9238f96f..fcade9172b7 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -3,12 +3,9 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -70,8 +67,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y # CONFIG_RNG_SMCCC_TRNG is not set CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index e00d72e8beb..20d2cff93f7 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -3,13 +3,16 @@ CONFIG_ARCH_APPLE=y CONFIG_DEFAULT_DEVICE_TREE="t8103-j274" CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_SYS_BOOTM_LEN=0x800000 +CONFIG_BOOTCOMMAND="bootflow scan -b" CONFIG_USE_PREBOOT=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y +CONFIG_CMD_SELECT_FONT=y # CONFIG_NET is not set +CONFIG_SYS_64BIT_LBA=y CONFIG_APPLE_SPI_KEYB=y # CONFIG_MMC is not set CONFIG_NVME_APPLE=y @@ -18,6 +21,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO_FONT_16X32=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 1a892a9bc18..8588f8c5adf 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" CONFIG_SPL_STACK=0x304000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3e00 +CONFIG_SPL_BSS_MAX_SIZE=0x600 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=18432000 @@ -39,9 +42,6 @@ CONFIG_SYS_PBSIZE=281 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x3e00 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3e00 -CONFIG_SPL_BSS_MAX_SIZE=0x600 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 494c018a0e5..4bade848e6f 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -12,6 +12,10 @@ CONFIG_DEFAULT_DEVICE_TREE="bitmain-antminer-s9" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_SYS_LOAD_ADDR=0x0 @@ -30,11 +34,7 @@ CONFIG_SYS_PBSIZE=2075 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_HUSH_PARSER=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index 5cc95241ba4..a0caa367f9d 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y @@ -15,7 +14,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_BOOTSTD_FULL=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 47f51e0e6b1..24dfdae11e3 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -17,6 +17,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -33,9 +36,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index c4136477c26..e5d805d7da7 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -17,6 +17,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_CHROMEBIT_MICKEY=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,8 +38,6 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index d0321948697..55d44700d6e 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,6 +17,11 @@ CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_SPL_STACK=0xff8effff +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -32,14 +37,9 @@ CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 4b80d6a8051..9bc59539dc8 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -16,6 +16,8 @@ CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC is not set CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -35,8 +37,6 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 120c11c0497..48ee8b9fd25 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -18,6 +18,11 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_KEVIN=y CONFIG_SPL_STACK=0xff8effff +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -33,14 +38,9 @@ CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 126b8ce41ce..26fa05e543b 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -17,6 +17,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_CHROMEBOOK_MINNIE=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,8 +38,6 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 2346c83aab4..5deb09b28ec 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -17,6 +17,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_CHROMEBOOK_SPEEDY=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,8 +38,6 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 07c5a26221a..39f33844e46 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL_TEXT_BASE=0xf4000a00 CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0xf4008000 +CONFIG_SPL_BSS_START_ADDR=0xf4004000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ARCH_JZ47XX=y @@ -28,8 +30,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x2e00 -CONFIG_SPL_BSS_START_ADDR=0xf4004000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set # CONFIG_SPL_BANNER_PRINT is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 38177a7648a..217617ee868 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -16,6 +16,8 @@ CONFIG_TARGET_CL_SOM_IMX7=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -29,8 +31,6 @@ CONFIG_BOOTCOMMAND="echo SD boot attempt ...; run sdbootscript; run sdboot; echo CONFIG_SYS_PBSIZE=543 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index db2f2664c8d..9bbc723f9c7 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -28,9 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig index c7e74912612..9ddd5d295fe 100644 --- a/configs/clearfog_sata_defconfig +++ b/configs/clearfog_sata_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -28,9 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig index 8d3dd0195ed..4175fdb17a1 100644 --- a/configs/clearfog_spi_defconfig +++ b/configs/clearfog_spi_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -28,9 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index fc10d7f66a6..4a0ff029ac7 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 +CONFIG_OF_ENV_SETUP=y CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb" diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 16f923b07c2..47c2ffcc84e 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -19,6 +19,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 +CONFIG_OF_ENV_SETUP=y CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run distro_bootcmd;" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb " @@ -99,12 +100,12 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y -CONFIG_IMX_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 -CONFIG_WDT=y CONFIG_CI_UDC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 7c6a725ea9a..001f2f92229 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -85,12 +85,12 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y -CONFIG_IMX_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 -CONFIG_WDT=y CONFIG_CI_UDC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 351d3920608..cf7499bb16f 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -17,6 +17,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x40031000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40028000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -36,9 +39,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_LAST_STAGE_INIT=y CONFIG_SPL_MAX_SIZE=0x27fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40028000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig index a0fe3708344..2608bb67679 100644 --- a/configs/coolpi-4b-rk3588s_defconfig +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" @@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig index fc17660da2a..c5bb7a42957 100644 --- a/configs/coolpi-cm5-evb-rk3588_defconfig +++ b/configs/coolpi-cm5-evb-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb" @@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 3f057302dd1..65e24b72bec 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -21,6 +21,9 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus" CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3000 +CONFIG_SPL_BSS_MAX_SIZE=0x800 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SYS_LOAD_ADDR=0x70000000 @@ -36,9 +39,6 @@ CONFIG_SYS_PBSIZE=281 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x3000 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3000 -CONFIG_SPL_BSS_MAX_SIZE=0x800 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_NAND_SUPPORT=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 81305759267..1095a761ab8 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -22,6 +22,8 @@ CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0000000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -40,8 +42,6 @@ CONFIG_CLOCKS=y CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc0000000 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 330f88183c7..1f22b65302d 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -19,6 +19,8 @@ CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0000000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -36,8 +38,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_HWCONFIG=y CONFIG_SPL_PAD_TO=0x8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc0000000 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index f30d878a531..33b8b806652 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -27,9 +30,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1ffd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40020000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index f67737a95d6..540a348fdcf 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=200000000 @@ -29,9 +32,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig index b6b772ea707..4d4cf36749a 100644 --- a/configs/db-88f6820-amc_nand_defconfig +++ b/configs/db-88f6820-amc_nand_defconfig @@ -17,6 +17,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=200000000 @@ -31,9 +34,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index cc98e35e5cb..4f98ee4f382 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -28,9 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 5d78b140f8d..d776693b600 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -28,9 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1bfd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40020000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index c27f061e5b7..4b9b0734c5a 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING=" ##v01.06" @@ -41,9 +44,6 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index db357e12ede..7653fbbe7e5 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -11,13 +11,13 @@ CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_DEVKIT8000=y CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_SPL_BSS_START_ADDR=0x80000500 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_MAX_SIZE=0xec00 -CONFIG_SPL_BSS_START_ADDR=0x80000500 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index 7424e2bfbc0..ba3f381f69f 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -16,6 +16,7 @@ CONFIG_TARGET_ETAMIN=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xB80000 CONFIG_SPL_FS_FAT=y @@ -33,7 +34,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 6fdf12a92d1..43d29f5b11a 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_RASTABAN=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y @@ -31,7 +32,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index e22d03a9387..b457b22fc64 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_THUBAN=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y @@ -31,7 +32,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 260a8349d3b..9ef04fd4554 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="apq8016-sbc" +CONFIG_DEFAULT_DEVICE_TREE="qcom/apq8016-sbc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_SYS_LOAD_ADDR=0x80080000 diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index ebc80eb2a46..f6b2cb09ba3 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x804000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x4000 -CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c" +CONFIG_DEFAULT_DEVICE_TREE="qcom/apq8096-db820c" CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig index df641c959ec..1fc73802160 100644 --- a/configs/ds116_defconfig +++ b/configs/ds116_defconfig @@ -20,6 +20,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-synology-ds116" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -35,9 +38,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 7b367e1872b..ecf9501ba5a 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -19,6 +19,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -34,9 +37,6 @@ CONFIG_BOOTCOMMAND="sf probe; sf read ${loadaddr} 0xd0000 0x2d0000; sf read ${ra CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x1bfd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40020000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 446c9c9b7ac..59b88a851e4 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -56,7 +56,6 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x110a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_RANDOM_UUID=y CONFIG_ERRNO_STR=y diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index 26622508f01..3230d360eda 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SUPPORT_PASSING_ATAGS=y CONFIG_CMDLINE_TAG=y @@ -15,12 +14,13 @@ CONFIG_TEGRA30=y CONFIG_TARGET_ENDEAVORU=y CONFIG_CMD_EBTUPDATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_BUTTON_CMD=y CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;" +CONFIG_BOOTCOMMAND="bootflow scan; poweroff" CONFIG_SYS_PBSIZE=2084 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index 314d5d3e5b2..e6a4e4d1b7c 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -20,6 +20,11 @@ CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" CONFIG_DM_RESET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x83000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x83000000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 CONFIG_SPL_SIZE_LIMIT=0x10000 CONFIG_SPL=y # CONFIG_ARMV7_NONSEC is not set @@ -40,12 +45,7 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x83000000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DM_RESET=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index d75329d3851..07c56a45ec0 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -16,9 +16,13 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -34,13 +38,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_BANNER_PRINT is not set diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 5f32c926745..ccd38831533 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -17,6 +17,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_PX5=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x188000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x20000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF1c0000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -37,13 +41,9 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x20000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index e21bea9d499..94ee21e344e 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_TEXT_BASE=0x10081000 CONFIG_ROCKCHIP_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0x10081fff +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 @@ -28,7 +29,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_SPL_STACK_R=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index d632fd7b5ef..69dd880b38f 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x60000000 CONFIG_ROCKCHIP_RK322X=y CONFIG_TARGET_EVB_RK3229=y CONFIG_SPL_STACK_R_ADDR=0x60600000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x61800800 @@ -30,7 +31,6 @@ CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_STACK_R=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 31dad12f49d..6407f22470e 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -16,6 +16,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x04000000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -34,8 +36,6 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_OPTEE_IMAGE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index d57b2f6b8e5..04a94e13a68 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -3,43 +3,35 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y -CONFIG_DEBUG_UART_BASE=0xFF0C0000 +CONFIG_DEBUG_UART_BASE=0xFF0E0000 CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -50,9 +42,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -61,15 +55,15 @@ CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 75a0e0f286b..53ad6777ec5 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -57,6 +57,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +# CONFIG_ROCKCHIP_IODOMAIN is not set CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index 6e8061f5f48..e71d6705568 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y @@ -32,7 +31,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -49,6 +48,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index c8db04c076e..a8c32c4fcf4 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -33,7 +31,8 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -52,7 +51,7 @@ CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_PINCTRL=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 1c62149a9b5..25453fba0dc 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -49,7 +49,6 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x110a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_RANDOM_UUID=y CONFIG_ERRNO_STR=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b5..618f6baf91a 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,6 +13,11 @@ CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y CONFIG_SPL_STACK=0xff8effff +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -20,13 +25,8 @@ CONFIG_DEBUG_UART=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 11a3baa7a37..e5377dcdf3d 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -17,9 +17,13 @@ CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -35,13 +39,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_BANNER_PRINT is not set diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 4860298003c..03ee04e5bf2 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -16,6 +16,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -30,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index ceb48dfc63d..3b9466c830f 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x308000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 @@ -39,9 +42,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_MAX_SIZE=0x7000 CONFIG_SPL_PAD_TO=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index d72e8269a22..f4642e3fcff 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" CONFIG_SPL_SERIAL=y CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xB0000 @@ -41,8 +43,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_BSS_START_ADDR=0x80010000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index e7d5e55bbfd..033702fd149 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -2,18 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 +CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -21,19 +25,27 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +# CONFIG_ADC is not set CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_MISC=y # CONFIG_ROCKCHIP_IODOMAIN is not set @@ -43,10 +55,27 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index b50f4f8b800..87a171701e4 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -15,8 +14,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -27,15 +26,21 @@ CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +# CONFIG_ADC is not set CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y @@ -44,10 +49,19 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index 1c20af51bfb..c7390d1d323 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING=" ##v01.07" @@ -41,9 +44,6 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig index 2346cd6b522..001f5b88040 100644 --- a/configs/grouper_common_defconfig +++ b/configs/grouper_common_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SUPPORT_PASSING_ATAGS=y CONFIG_CMDLINE_TAG=y @@ -15,12 +14,13 @@ CONFIG_TEGRA30=y CONFIG_TARGET_GROUPER=y CONFIG_CMD_EBTUPDATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_BUTTON_CMD=y CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;" +CONFIG_BOOTCOMMAND="bootflow scan; poweroff" CONFIG_SYS_PBSIZE=2084 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index f6db7de8eba..ad994744c82 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y @@ -45,7 +46,6 @@ CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 0c86cfd4806..96c64c8b767 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1080000 CONFIG_CMD_HDMIDETECT=y @@ -45,7 +46,6 @@ CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 72d1d771a78..c4c5d48f4eb 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -28,9 +31,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig new file mode 100644 index 00000000000..a07689894ef --- /dev/null +++ b/configs/hmibsc_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="schneider" +CONFIG_SYS_BOARD="hmibsc" +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_TEXT_BASE=0x8f600000 +CONFIG_SYS_MALLOC_LEN=0x802000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DEFAULT_DEVICE_TREE="apq8016-schneider-hmibsc" +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC" +CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=2048 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="hmibsc => " +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_ENV_EXISTS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON_QCOM_PMIC=y +CONFIG_CLK=y +CONFIG_CLK_QCOM_APQ8016=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MSM_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_APQ8016=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_MSM_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_PHYLIB=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d +CONFIG_CI_UDC=y diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index ce957d926a4..064758c48c8 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_MX6ULZ_SMM_M2=y CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-bsh-smm-m2" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_SERIAL=y +CONFIG_SPL_BSS_START_ADDR=0x84100000 CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y @@ -22,7 +23,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_BSS_START_ADDR=0x84100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_MTD=y diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig index 62dda1a533b..a04008c57d8 100644 --- a/configs/imx7_cm_defconfig +++ b/configs/imx7_cm_defconfig @@ -17,6 +17,8 @@ CONFIG_TARGET_IMX7_CM=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y @@ -27,8 +29,6 @@ CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SYS_PBSIZE=532 # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index c011f4f4906..f5bb50c5f39 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -28,9 +31,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 6afdb399b14..b36ad7c867c 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -17,6 +17,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -30,9 +33,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 0f81a69d623..d4e9d9f342d 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -27,9 +30,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index c2321e15b27..c85a14119e7 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -27,9 +30,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 1ed7f0a2259..e9b18ac1be7 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00 @@ -39,9 +42,6 @@ CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 252eeb9d261..cb292dde4cb 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -29,9 +32,6 @@ CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 0b601bb8624..e3dcbfe0452 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -18,6 +18,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -30,9 +33,6 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index eaf8dce3b5f..0aca853afd9 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -32,9 +35,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index bb183381c3e..53249f44a4e 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -23,6 +23,9 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 @@ -48,9 +51,6 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index e41facd8513..ff33d1532a0 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -26,9 +29,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 3aaf7a4d0d5..a57dc47f26f 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y @@ -30,9 +33,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index fb7cc33f0bf..e14dcdf9a3d 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -27,9 +30,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index cb6b97d097c..f4d999bfcef 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -12,14 +12,19 @@ CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_VENICE=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SYS_LOAD_ADDR=0x48200000 +CONFIG_PCI=y CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_FIT=y @@ -34,9 +39,6 @@ CONFIG_PREBOOT="gsc wd-disable" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y @@ -60,14 +62,19 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -83,6 +90,8 @@ CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y @@ -114,6 +123,9 @@ CONFIG_PHY_GIGE=y CONFIG_FEC_MXC=y CONFIG_KSZ9477=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -124,17 +136,22 @@ CONFIG_DM_PMIC_BD71837=y CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_PMIC_MP5416=y CONFIG_SPL_DM_PMIC_MP5416=y -CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y @@ -152,4 +169,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y +CONFIG_TPM=y +# CONFIG_SPL_SHA512 is not set +# CONFIG_SPL_SHA384 is not set CONFIG_HEXDUMP=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index e8009c410ab..1129d8070cc 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -21,6 +21,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -38,9 +41,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index ed671cf4a77..f4af99847d1 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -37,9 +40,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 11c257a756e..cecde443367 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -37,9 +40,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 8c28b92f752..0e0a548a57f 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -17,6 +17,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -32,9 +35,6 @@ CONFIG_SYS_PBSIZE=2067 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 3b55f6ff418..f739569dde9 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -18,6 +18,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -33,9 +36,6 @@ CONFIG_SYS_PBSIZE=2067 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 56b88808ebd..82e3ce19480 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -31,9 +34,6 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 91b7586a657..2402e9e8bfb 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -31,9 +34,6 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 6057d13a73d..218415fad57 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -36,9 +39,6 @@ CONFIG_SYS_PBSIZE=2067 CONFIG_BOARD_TYPES=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 0a4fba5f1ca..b65fef0a806 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -17,6 +17,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -36,9 +39,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x950000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -65,18 +65,21 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="freescale/imx8mn-venice-gw7902" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 @@ -86,6 +89,8 @@ CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y @@ -128,14 +133,20 @@ CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y @@ -153,4 +164,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y +CONFIG_TPM=y +# CONFIG_SPL_SHA512 is not set +# CONFIG_SPL_SHA384 is not set CONFIG_HEXDUMP=y diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 83d7d18f316..3a622727232 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -33,9 +36,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index fe1678d8ae9..b0dcbc723ba 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y CONFIG_ARMV8_SET_SMPEN=y @@ -42,9 +45,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -135,7 +135,6 @@ CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PCA9450=y CONFIG_SPL_DM_PMIC_PCA9450=y -CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index 51cfca016a7..209d896b00c 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -24,6 +24,9 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_DEBUG_UART_BASE=0x30880000 @@ -55,9 +58,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x96fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig index 5092ac22744..70126c961f3 100644 --- a/configs/imx8mp_debix_model_a_defconfig +++ b/configs/imx8mp_debix_model_a_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -30,9 +33,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 50a7d193688..76f2fe8fcc9 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -24,6 +24,9 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_DEBUG_UART_BASE=0x30860000 @@ -53,9 +56,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x96fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index f9444ec9deb..5b338f22195 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -23,6 +23,9 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_DEBUG_UART_BASE=0x30860000 @@ -31,6 +34,7 @@ CONFIG_ENV_OFFSET_REDUND=0xFF0000 CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y @@ -54,9 +58,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x96fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -104,6 +105,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_BKOPS_ENABLE=y CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -216,7 +218,10 @@ CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 7e5dfce2ab6..d907aedb05a 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -30,9 +33,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 14e6a3f3d05..393a1316cd9 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -22,6 +22,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -42,9 +45,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index fecdaed4979..6dd51a3f1fc 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -22,6 +22,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -42,9 +45,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 6e4addc7728..df93774b307 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -18,6 +18,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -38,9 +41,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -67,12 +67,16 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -86,9 +90,9 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y @@ -132,17 +136,22 @@ CONFIG_DM_PMIC_BD71837=y CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_PMIC_MP5416=y CONFIG_SPL_DM_PMIC_MP5416=y -CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y @@ -160,4 +169,7 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_IMX_WATCHDOG=y +CONFIG_TPM=y +# CONFIG_SPL_SHA512 is not set +# CONFIG_SPL_SHA384 is not set CONFIG_HEXDUMP=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index a5f8f0b9510..5eb96d3826a 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -31,9 +34,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1050 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 3a2d88aec45..3c1701a3768 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -33,9 +36,6 @@ CONFIG_SYS_PBSIZE=1050 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 3ac4b213ad1..3a3fb754fa4 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -34,9 +37,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x2b000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 283d6d9ce7c..1844e3c8b84 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -36,9 +39,6 @@ CONFIG_CONSOLE_MUX=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig index 333115de2d3..43d8205760f 100644 --- a/configs/imx8qm_dmsse20a1_defconfig +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -36,9 +39,6 @@ CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index f353c167d40..bf02d3e4f67 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -34,9 +37,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index f0b109b4f89..bee69645876 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -16,6 +16,9 @@ CONFIG_TARGET_IMX8QM_ROM7720_A1=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -30,9 +33,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index da7cb05becf..d6b79f53893 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -35,9 +38,6 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index a7085ceb4a3..721c4cb9d11 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -17,6 +17,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x22050000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x22048000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SYS_LOAD_ADDR=0x80480000 @@ -32,9 +35,6 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x22048000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig index 54215c51c08..e3eb0029fa4 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phyboard-segin_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x720000 CONFIG_CMD_DEKBLOB=y @@ -36,9 +39,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051a000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 63613477c7f..5ad770f91e1 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -10,13 +10,16 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-evk" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_TARGET_IMX93_11X11_EVK=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SYS_LOAD_ADDR=0x80400000 @@ -30,9 +33,6 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051a000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index 4e3bbdd0cf5..abda6d12662 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-evk" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_IMX9_LOW_DRIVE_MODE=y CONFIG_TARGET_IMX93_11X11_EVK=y @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SYS_LOAD_ADDR=0x80400000 @@ -31,9 +34,6 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051a000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index 996cad4854a..e39d7dc5e88 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -18,6 +18,9 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_CMD_DEKBLOB=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 @@ -37,9 +40,6 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051a000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 484f8e46e3e..e0c2b140441 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -23,6 +23,10 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_ENV_OFFSET_REDUND=0x6a0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -44,12 +48,8 @@ CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd" CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 0f2e83dfeec..fe8e84c9214 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -23,6 +23,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -37,12 +41,8 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index d5b44e37f01..e023af24674 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -22,6 +22,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc +CONFIG_SPL_BSS_MAX_SIZE=0xa000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -33,11 +37,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc -CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index 3d234bc1a8f..a354876f8c2 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -21,6 +21,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_PSCI_RESET is not set @@ -37,11 +41,7 @@ CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb CONFIG_LOGLEVEL=7 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y @@ -57,19 +57,19 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y CONFIG_CMD_BOOTEFI_SELFTEST=y +CONFIG_CMD_ASKENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO_READ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MMC_SPEED_MODE_SET=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig index eab7a603f09..314161b8a62 100644 --- a/configs/j721e_beagleboneai64_r5_defconfig +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -19,6 +19,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 +CONFIG_SPL_BSS_MAX_SIZE=0xa000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0xf59f0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -32,10 +36,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xf59f0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 -CONFIG_SPL_BSS_MAX_SIZE=0xa000 -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 077bf508328..3d8e9391987 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -22,6 +22,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,12 +40,8 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 4d4b96dec6b..cea48b26136 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -21,6 +21,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 +CONFIG_SPL_BSS_MAX_SIZE=0xa000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0xf59f0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -37,11 +41,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xf59f0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 -CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 92f69413fa4..19cd44b068c 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -21,6 +21,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -34,12 +38,8 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index cb6b4a44864..5ef5247a3e0 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -20,6 +20,11 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c76000 +CONFIG_SPL_BSS_MAX_SIZE=0xa000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -35,14 +40,9 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c76000 -CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 6c62403613a..bb9603bef0f 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -14,7 +13,6 @@ CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_OF_UPSTREAM=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j784s4-evm" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y @@ -23,6 +21,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -30,19 +32,11 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y -CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" -CONFIG_BOARD_LATE_INIT=y CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y @@ -50,18 +44,15 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -72,8 +63,8 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_OF_LIST="ti/k3-j784s4-evm" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -145,7 +136,6 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_RESET_TI_SCI=y CONFIG_SCSI=y -CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 50a52b9228e..f5fe7432206 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -21,6 +20,11 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c76000 +CONFIG_SPL_BSS_MAX_SIZE=0xa000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -29,23 +33,15 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_USE_BOOTCOMMAND=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xc0000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c76000 -CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -54,21 +50,17 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_TIME=y @@ -76,7 +68,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-j784s4-r5-evm" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 3233b75cee9..f29505ea150 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 8dbdf1f4240..8d6cb240446 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -22,6 +22,9 @@ CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_SPL_TEXT_BASE=0xC100000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc1223f4 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc10fff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -32,9 +35,6 @@ CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0xfff8 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc10fff8 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x8000 diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index eed18844106..88965e273e2 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -21,6 +21,9 @@ CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" CONFIG_SPL_TEXT_BASE=0xC0A0000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc0c23f4 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0afff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -31,9 +34,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_mon_${bo CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0xfff8 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc0afff8 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x8000 diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 6ed17721ced..4da75d1ca76 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -22,6 +22,9 @@ CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_SPL_TEXT_BASE=0xC200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc2223f4 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc20fff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -32,9 +35,6 @@ CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0xfff8 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc20fff8 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x8000 diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index d642a68e135..c4534f033ac 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -22,6 +22,9 @@ CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" CONFIG_SPL_TEXT_BASE=0xC100000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc1223f4 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc10fff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -32,9 +35,6 @@ CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0xfff8 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc10fff8 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x8000 diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 50c55902637..f2570289298 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL_STACK=0x91fff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1F0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -35,9 +38,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=276 CONFIG_BOARD_TYPES=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 02fc696b76f..e2a87c4a81d 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -36,9 +39,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 639c5c6ce10..a1d5f89b1ec 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -11,7 +11,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x3e0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" +CONFIG_DEFAULT_DEVICE_TREE="freescale/fsl-ls1028a-kontron-sl28" CONFIG_SPL_TEXT_BASE=0x18010000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_OF_LIBFDT_OVERLAY=y @@ -19,6 +19,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f0000 @@ -45,9 +48,6 @@ CONFIG_BOARD_LATE_INIT=y # CONFIG_HWCONFIG is not set CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y @@ -73,7 +73,8 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RNG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="fsl-ls1028a-kontron-sl28 fsl-ls1028a-kontron-sl28-var1 fsl-ls1028a-kontron-sl28-var2 fsl-ls1028a-kontron-sl28-var3 fsl-ls1028a-kontron-sl28-var4" +CONFIG_OF_UPSTREAM=y +CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var4" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index ed4f2ba5558..b9b50e8c23a 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -18,6 +18,7 @@ CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0x10081fff +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 @@ -30,7 +31,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_SPL_STACK_R=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index 1dd08360485..6999a689e29 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -37,9 +40,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index 784a269fd5b..6859dfd517c 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index f2182927c91..69494f5e405 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_ARCH_MTMIPS=y @@ -33,8 +35,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_BSS_START_ADDR=0x80010000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 32d34bc20a1..a4a7f1a5cbd 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -14,6 +14,11 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x188000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x20000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -33,14 +38,9 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-lion-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x20000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y CONFIG_TPL=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 7ea28bbaf40..2354f4113ae 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -41,9 +44,6 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index a45b4d90360..136ca9a2670 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -52,9 +55,6 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 9ab19f17ad1..befb4ae442c 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -51,9 +54,6 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 31496ee000b..db06a03fe6b 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -50,9 +53,6 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index e4b72d3cf29..e5d8eeb8a2f 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -44,9 +47,6 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 148d0306334..dc0e507263f 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -52,9 +55,6 @@ CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index b5a6ca51c83..9980d6106ec 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -53,9 +56,6 @@ CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 41f7a0dc317..ed92e34dccf 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -20,6 +20,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x1001d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_PCI=y @@ -54,9 +57,6 @@ CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 3093f7023d5..06e41546d67 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_PCI=y CONFIG_AHCI=y @@ -39,9 +42,6 @@ CONFIG_SYS_PBSIZE=532 CONFIG_RESET_PHY_R=y CONFIG_SPL_MAX_SIZE=0x16000 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index d335b33bc05..f1009e1738b 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_PCI=y CONFIG_AHCI=y @@ -45,9 +48,6 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_SPL_MAX_SIZE=0x16000 CONFIG_SPL_PAD_TO=0x80000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 1c50a0ccbe6..ea67b6a7286 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 40be03ca77c..9906099e8c5 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -26,9 +29,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1bfd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40020000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 374d21e3655..9e653c73eec 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_MIQI_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -30,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index cc3906f07da..9a342d3a33a 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -24,6 +24,8 @@ CONFIG_TPL_STACK=0x1008FFFF CONFIG_TARGET_MK808=y CONFIG_SPL_STACK_R_ADDR=0x70000000 CONFIG_SPL_STACK=0x1008ffff +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_FS_FAT=y @@ -43,8 +45,6 @@ CONFIG_SPL_MAX_SIZE=0x32000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FS_EXT4=y CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2 diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig index 88b97ad57d8..dc5a45fb0d8 100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -16,6 +16,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0098FC00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -32,9 +35,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s-ep1.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x0098FC00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig index 6dc7c22b994..20f62fa86d0 100644 --- a/configs/mt7620_mt7530_rfb_defconfig +++ b/configs/mt7620_mt7530_rfb_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb" CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xb0000c00 CONFIG_DEBUG_UART_CLOCK=40000000 @@ -27,8 +29,6 @@ CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_BSS_START_ADDR=0x80010000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y # CONFIG_CMD_ELF is not set diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig index b17b2cd9343..bf9d7115863 100644 --- a/configs/mt7620_rfb_defconfig +++ b/configs/mt7620_rfb_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb" CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xb0000c00 CONFIG_DEBUG_UART_CLOCK=40000000 @@ -26,8 +28,6 @@ CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_BSS_START_ADDR=0x80010000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y # CONFIG_CMD_ELF is not set diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig index 7f0a24b36c4..7e12c040ffb 100644 --- a/configs/mt7621_nand_rfb_defconfig +++ b/configs/mt7621_nand_rfb_defconfig @@ -8,6 +8,8 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-nand-rfb" CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x80140000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xbe000c00 CONFIG_DEBUG_UART_CLOCK=50000000 @@ -27,8 +29,6 @@ CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_BSS_START_ADDR=0x80140000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig index 43d00d34133..ec5996a2e0b 100644 --- a/configs/mt7621_rfb_defconfig +++ b/configs/mt7621_rfb_defconfig @@ -10,6 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb" CONFIG_SPL_SERIAL=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x80140000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xbe000c00 CONFIG_DEBUG_UART_CLOCK=50000000 @@ -27,8 +29,6 @@ CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_BSS_START_ADDR=0x80140000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_TPL=y diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig index 85b32a7d39f..351e6a160e8 100644 --- a/configs/mt7628_rfb_defconfig +++ b/configs/mt7628_rfb_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb" CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80010000 CONFIG_ARCH_MTMIPS=y @@ -26,8 +28,6 @@ CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_BSS_START_ADDR=0x80010000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y # CONFIG_CMD_ELF is not set diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 7868b02eb3c..bccbbccc601 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x40800000 CONFIG_SPL_STACK=0x106000 +CONFIG_SPL_STACK_R=y CONFIG_SYS_LOAD_ADDR=0x42007f1c CONFIG_SPL_PAYLOAD="u-boot-lzma.img" CONFIG_BUILD_TARGET="u-boot-mtk.bin" @@ -33,7 +34,6 @@ CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig index fde14f09b9f..5e13d2cb768 100644 --- a/configs/n2350_defconfig +++ b/configs/n2350_defconfig @@ -20,6 +20,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-thecus-n2350" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -36,9 +39,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig index 5c7bc0b7196..738dda026b0 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6" @@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 0f1a9461a0c..00743b7f926 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 4ebf0cc9ee8..91e3a19dea6 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 307a540f424..56198556aff 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -13,11 +12,13 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y @@ -28,6 +29,7 @@ CONFIG_CMD_MMC=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -40,10 +42,11 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_PINCTRL=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 9ef2bb21fff..40baec319c9 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -13,11 +12,13 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y @@ -28,6 +29,7 @@ CONFIG_CMD_MMC=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -40,10 +42,11 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_PINCTRL=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index eb759e00738..99d7149a44c 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -19,9 +19,13 @@ CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -39,13 +43,9 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index b5ed9e4bc98..e749f9af9d2 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index c7483b8433e..947a6c6b3bc 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_DYNAMIC_SYS_CLK_FREQ=y @@ -35,8 +37,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xc0000000 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index 12b423f52e7..a08040d878d 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK=0x83fffe80 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x82000000 CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x87000000 @@ -28,7 +29,6 @@ CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x82000000 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig index d6e23c154f1..ba8005363ad 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus" @@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig index e6b3da1dc59..d61f85aaa8c 100644 --- a/configs/orangepi-5-rk3588s_defconfig +++ b/configs/orangepi-5-rk3588s_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5" @@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 5c1c47ecc43..4f0725f3425 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -35,6 +35,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_SYS_I2C_TEGRA=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 19d6aa8cd30..22d419024f6 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -17,6 +17,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -30,9 +33,6 @@ CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 6c67f14b555..e9a287cb441 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -18,6 +18,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3e0000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -31,9 +34,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 792e122f3f6..fd36edc29dd 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -19,6 +19,10 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80c80000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 CONFIG_SPL_FS_FAT=y @@ -35,12 +39,8 @@ CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80c80000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index bd28e145e60..389672d5227 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -22,6 +22,11 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y @@ -35,13 +40,8 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c3b000 -CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 09f1e2621d5..1a9359773b4 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -24,6 +24,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -35,12 +39,8 @@ CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SPL_MAX_SIZE=0x180000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 74e6e8331a9..61d784fa17f 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -22,6 +22,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x7019b800 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x190000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -36,13 +40,9 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x180000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x7019b800 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 2e32a7e28d9..9d5241a50d0 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -13,6 +13,8 @@ CONFIG_TARGET_PICO_IMX7D=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y @@ -25,8 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BOOTD is not set diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 42abda08177..690139c09ca 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -13,6 +13,8 @@ CONFIG_TARGET_PICO_IMX7D=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y @@ -25,8 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BOOTD is not set diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 154c2dbaa35..1327523e289 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -13,6 +13,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_SYS_MEMTEST_START=0x80000000 @@ -27,8 +29,6 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 3202894226c..6009b1c65c1 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -13,6 +13,8 @@ CONFIG_TARGET_PICO_IMX7D=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y @@ -25,8 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BOOTD is not set diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index ebd43b5c36a..cf91eb563b9 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -34,9 +37,6 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x180000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 2e32a7e28d9..9d5241a50d0 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -13,6 +13,8 @@ CONFIG_TARGET_PICO_IMX7D=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y @@ -25,8 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BOOTD is not set diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 1c2ba2651b1..28c46abed78 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -13,6 +13,8 @@ CONFIG_TARGET_PICO_IMX7D=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y @@ -25,8 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BOOTD is not set diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig index bc7a77aa52f..ad237edf8d9 100644 --- a/configs/pinetab2-rk3566_defconfig +++ b/configs/pinetab2-rk3566_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 +CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0" CONFIG_ROCKCHIP_RK3568=y @@ -99,7 +99,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x350a CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 09af09ea6ee..92f93f6503b 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_POPMETAL_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -30,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2759e1a952..14a7bc8b1e0 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -17,6 +17,11 @@ CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_PUMA_RK3399=y CONFIG_SPL_STACK=0xff8effff +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -27,13 +32,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index d96fd14b36d..a2801ec7796 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -17,9 +17,13 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -35,13 +39,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_BANNER_PRINT is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index ac2af6d8cbb..cc33e275742 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -17,9 +17,13 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -35,13 +39,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_BANNER_PRINT is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index a49bb4072d2..99e1b2fc7ae 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -17,9 +17,13 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -35,13 +39,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_BANNER_PRINT is not set diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 64fed8b33eb..366d8fc3aea 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_PXM2=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -37,7 +38,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..80ad3b32e13 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -2,8 +2,9 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SNAPDRAGON=y -CONFIG_DEFAULT_DEVICE_TREE="sdm845-db845c" -CONFIG_SYS_LOAD_ADDR=0x0 +CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" +CONFIG_SYS_LOAD_ADDR=0xA0000000 +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -33,14 +34,21 @@ CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y +CONFIG_OF_BOARD_SETUP=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y +CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y +CONFIG_CLK_QCOM_SM6115=y +CONFIG_CLK_QCOM_SM8250=y +CONFIG_CLK_QCOM_SM8550=y +CONFIG_CLK_QCOM_SM8650=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_QUP=y +CONFIG_SYS_I2C_GENI=y CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y @@ -63,9 +71,15 @@ CONFIG_RGMII=y CONFIG_PHY=y CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_PHY_QCOM_SNPS_EUSB2=y CONFIG_PINCTRL=y +CONFIG_PINCTRL_QCOM_QCM2290=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y +CONFIG_PINCTRL_QCOM_SM6115=y +CONFIG_PINCTRL_QCOM_SM8250=y +CONFIG_PINCTRL_QCOM_SM8550=y +CONFIG_PINCTRL_QCOM_SM8650=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_DM_REGULATOR=y @@ -92,5 +106,5 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_HEXDUMP=y -# CONFIG_GENERATE_SMBIOS_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLE=y CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 4ff8ec8a5cf..dd774a0259a 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -6,6 +6,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y @@ -18,7 +19,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index f663a13770a..220b5fed6ae 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -5,6 +5,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" +CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y @@ -17,7 +18,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig index fef80439d89..535e34fb990 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig index bb541ed1af6..e197defd3af 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b" diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index b2a66d3f2db..33cbda88285 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -19,7 +18,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -64,7 +62,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_SCSI=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index fc39412f65c..09ea1c54f13 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -15,6 +15,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_EAGLE=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y @@ -25,9 +28,6 @@ CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77970-eagle. CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig index bcd70b768ee..089c7544e5e 100644 --- a/configs/r8a77970_v3msk_defconfig +++ b/configs/r8a77970_v3msk_defconfig @@ -16,6 +16,9 @@ CONFIG_R8A77970=y CONFIG_TARGET_V3MSK=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y @@ -25,9 +28,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 65eb563a712..9f5212f93d8 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -14,6 +14,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_CONDOR=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y @@ -25,9 +28,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb" CONFIG_SYS_PBSIZE=2068 # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig index 38f9da445dd..8c85f42ed42 100644 --- a/configs/r8a77980_v3hsk_defconfig +++ b/configs/r8a77980_v3hsk_defconfig @@ -15,6 +15,9 @@ CONFIG_R8A77980=y CONFIG_TARGET_V3HSK=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y @@ -24,9 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb" CONFIG_SYS_PBSIZE=2068 # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index f3cf2f8835d..3960a250d9e 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -14,6 +14,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_EBISU=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_SYS_MONITOR_BASE=0x00000000 @@ -26,9 +29,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" CONFIG_SYS_PBSIZE=2068 # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index ae722724e27..01f5b135959 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -14,6 +14,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_DRAAK=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_SYS_MONITOR_BASE=0x00000000 @@ -25,9 +28,6 @@ CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77995-draak. CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index ff317e7c4bc..6bd872f063f 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +# CONFIG_OF_UPSTREAM is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 @@ -72,4 +73,3 @@ CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_RENESAS_RPC_SPI=y -# CONFIG_OF_UPSTREAM is not set diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index bf61db44d3a..d23ab57ada5 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index 43aa8ec20e4..dbb77b85f5d 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 3200e3933b0..45d2446b8a1 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -12,6 +12,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe633f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_PCI=y CONFIG_REMAKE_ELF=y @@ -25,9 +28,6 @@ CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77951-salvat CONFIG_DEFAULT_FDT_FILE="r8a77951-salvator-x.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe633f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index c5cce826efd..b5d81219246 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -13,6 +13,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe633f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_SYS_MONITOR_BASE=0x00000000 @@ -24,9 +27,6 @@ CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77951-ulcb.d CONFIG_DEFAULT_FDT_FILE="r8a77951-ulcb.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe633f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index b314636b4d9..67a44eda684 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -17,9 +17,13 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_RINGNECK_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -35,14 +39,10 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 5e8f51ec01e..ef58bd65753 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -2,10 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_ROC_RK3308_CC=y CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -14,32 +15,23 @@ CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -50,26 +42,30 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 6526d2606e7..1dbd39e6b5e 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y @@ -94,6 +95,10 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index c161bc974fb..b06b57fe0bf 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index bca44beca12..315b8b853fc 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -3,25 +3,30 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -40,14 +45,20 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -61,6 +72,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -81,7 +93,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 695effcb0c5..4c09b9137ef 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -17,6 +17,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -29,8 +31,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_CMD_SPL=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 1e9cd2c0fc7..37a124eae18 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y CONFIG_DEBUG_UART_BASE=0xFF0A0000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -17,30 +16,22 @@ CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -51,9 +42,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -62,15 +55,15 @@ CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 3ebfb4ed436..2f6799c7b6a 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_ROCK2=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -30,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index ebe2d4a2d81..01df911d9dc 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 58c7c44fb4f..9e14b14af7c 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b" @@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -75,7 +73,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_SCSI=y @@ -102,7 +99,6 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x350b CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index b3fa76feb6b..2b5334c3c25 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -18,6 +18,8 @@ CONFIG_ROCKCHIP_RK3188=y CONFIG_TARGET_ROCK=y CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_SPL_STACK=0x10087fff +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 @@ -30,8 +32,6 @@ CONFIG_SPL_MAX_SIZE=0x7800 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index be0080804b9..7e78f1d6491 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_RUT=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -37,7 +38,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig index 1c313d2d4da..c7f3e2749a0 100644 --- a/configs/rzn1_snarc_defconfig +++ b/configs/rzn1_snarc_defconfig @@ -16,9 +16,9 @@ CONFIG_SYS_ALT_MEMTEST=y # CONFIG_SYS_ALT_MEMTEST_BITFLIP is not set CONFIG_CMD_CLK=y CONFIG_OF_CONTROL=y +# CONFIG_OF_UPSTREAM is not set CONFIG_RAM=y CONFIG_CADENCE_DDR_CTRL=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y # CONFIG_EFI_LOADER is not set -# CONFIG_OF_UPSTREAM is not set diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig index 6637d158248..283c9300c56 100644 --- a/configs/sama5d27_giantboard_defconfig +++ b/configs/sama5d27_giantboard_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 @@ -44,9 +47,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index b8c794c0985..89622c0e2a2 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 @@ -41,9 +44,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 03448ecbb0a..ef6f9fb7946 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 @@ -42,9 +45,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 349f3a7dd87..0693a5b5053 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 @@ -40,9 +43,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 25e95d596b0..89a5bcdfac8 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 @@ -41,9 +44,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 9c319d2ac7d..a07044578a8 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -19,6 +19,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 @@ -41,9 +44,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index faf1f4315bb..6b9fa27de63 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=83000000 @@ -41,9 +44,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index 90e64bf3ff6..e2423475cbf 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 @@ -41,9 +44,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index c9b8681ed8b..40d98584098 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 @@ -43,9 +46,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index d1cdb90e8e7..36aaa83fcb8 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 @@ -44,9 +47,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 4807f4f99be..9fd254e911e 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -23,6 +23,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 @@ -45,9 +48,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 7d0ed1befa3..5fb7aa6c84a 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x318000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 @@ -40,9 +43,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 756ffd1419b..054e52ef73d 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x318000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 @@ -37,9 +40,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 82541c23c4a..0072ce4c91f 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x318000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 @@ -42,9 +45,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index a8866648364..0c0029387ce 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x318000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 @@ -39,9 +42,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 25a330acd38..95624a1f884 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -22,6 +22,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x318000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 @@ -42,9 +45,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 280f7ee4405..40440c56b28 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 @@ -42,9 +45,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index f956104e946..abdde54f417 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -19,6 +19,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 @@ -39,9 +42,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 754cde68992..f814a94fbd0 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -23,6 +23,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 @@ -44,9 +47,6 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 780b2956253..3d3cc2d9f9e 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -20,6 +20,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 @@ -42,9 +45,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 8f66d8eebd6..551c87ee3cc 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -18,6 +18,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 @@ -39,9 +42,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index d132f8512d7..5b4628a32b1 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -22,6 +22,9 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x218000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 @@ -42,9 +45,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_MAX_SIZE=0x18000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 diff --git a/configs/sama7g54_curiosity_mmc_defconfig b/configs/sama7g54_curiosity_mmc_defconfig index fa3636828eb..00a091df0e5 100644 --- a/configs/sama7g54_curiosity_mmc_defconfig +++ b/configs/sama7g54_curiosity_mmc_defconfig @@ -117,7 +117,6 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_AT91=y CONFIG_TIMER=y CONFIG_MCHP_PIT64B_TIMER=y -CONFIG_FAT_WRITE=y CONFIG_CMD_DHRYSTONE=y # CONFIG_EFI_LOADER is not set CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama7g54_curiosity_nandflash_defconfig b/configs/sama7g54_curiosity_nandflash_defconfig index 331bb8d0fec..0b2116d0419 100644 --- a/configs/sama7g54_curiosity_nandflash_defconfig +++ b/configs/sama7g54_curiosity_nandflash_defconfig @@ -8,7 +8,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000 CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity" CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index f68171c9920..2365cc7d3bf 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe70 +CONFIG_SPL_BSS_START_ADDR=0x85000000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -30,7 +31,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x85000000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 7c6c5b4d5d1..47dbf1294d5 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe60 +CONFIG_SPL_BSS_START_ADDR=0x85000000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -36,7 +37,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ID_EEPROM=y CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x85000000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 4c94d016454..4c6009dbe45 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -15,6 +15,9 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_SILINUX_EK874=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_STACK=0xe6304000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y @@ -27,9 +30,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb" CONFIG_SYS_PBSIZE=2068 # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xe631f000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 66685230982..af08354e601 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -19,6 +19,9 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb" CONFIG_SPL_STACK=0x301000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SYS_LOAD_ADDR=0x22000000 @@ -37,9 +40,6 @@ CONFIG_SYS_PBSIZE=537 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1000 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x460000 diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 1afc6daf9e6..0243b15f31c 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_SNIPER=y CONFIG_SPL_STACK=0x4020fffc +CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};" @@ -17,7 +18,6 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=538 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_MAX_SIZE=0xec00 -CONFIG_SPL_BSS_START_ADDR=0x80000000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index f39954aea88..dc1cef3754e 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -1,55 +1,55 @@ CONFIG_ARM=y -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 +CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x04100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" +CONFIG_DM_RESET=y +CONFIG_SPL_STACK=0x7f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xbff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex5" CONFIG_SPL_FS_FAT=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000 -# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" -CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # " +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_DOS_PARTITION=y -CONFIG_SPL_DOS_PARTITION=y -CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y CONFIG_CMD_MTD=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y -CONFIG_SPL_SPI_FLASH_MTD=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_CMD_TIMER=y CONFIG_CMD_UBI=y -CONFIG_CMD_UBIFS=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_LIST="" @@ -57,60 +57,34 @@ CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_UBI_PART="root" CONFIG_ENV_UBI_VOLUME="env" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_BOOTFILE=y +CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_MISC=y -CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_UBI_SILENCE_MSG=y -CONFIG_DM_ETH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_RGMII=y -CONFIG_DM_RESET=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USB=y -CONFIG_USB_DWC2=y CONFIG_USB_XHCI_HCD=y -CONFIG_UBIFS_SILENCE_MSG=y +CONFIG_USB_DWC2=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_WDT=y -CONFIG_CMD_WDT=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_SPL_WDT=y -CONFIG_WATCHDOG_AUTOSTART=n -CONFIG_TIMER=y -CONFIG_DESIGNWARE_APB_TIMER=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 -CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xbff00000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x7f000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa00000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_CRC32=y # CONFIG_EFI_LOADER is not set -CONFIG_I3C=y -CONFIG_DW_I3C_MASTER=y -CONFIG_CMD_I3C=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_TIMER=y -# CONFIG_BOOTFILE="Image" is not set for CONFIG_SPL_ATF=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index ad4cb231345..4fc5c7918b9 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y @@ -32,9 +35,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" CONFIG_SYS_PBSIZE=2082 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 25fac3126b1..03d15efb52c 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y @@ -30,9 +33,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" CONFIG_SYS_PBSIZE=2082 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index c15cc5b3de4..83a808fe927 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" @@ -33,9 +36,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" CONFIG_SYS_PBSIZE=2082 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 7506aa8d329..029833675b4 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -6,8 +6,8 @@ CONFIG_ENV_OFFSET=0x4400 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y +CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y CONFIG_SPL_FS_FAT=y CONFIG_FIT=y CONFIG_SPL_FIT=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 923c202e0b3..2cf67167e9b 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" CONFIG_SPL_FS_FAT=y @@ -31,9 +34,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" CONFIG_SYS_PBSIZE=2079 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index e856b04679b..967f7562b17 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" CONFIG_SPL_FS_FAT=y @@ -27,9 +30,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" CONFIG_SYS_PBSIZE=2079 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 0f103334b99..53bdb4cbbf9 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" @@ -32,9 +35,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" CONFIG_SYS_PBSIZE=2079 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 92a8b2ef7f7..6d126a62a9b 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y @@ -32,9 +35,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" CONFIG_SYS_PBSIZE=2085 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index de4c8fe31b8..be7f747a7ed 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -14,6 +14,9 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y @@ -32,9 +35,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" CONFIG_SYS_PBSIZE=2085 CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig index b9ac6b9f33d..9d565c162ef 100644 --- a/configs/soquartz-blade-rk3566_defconfig +++ b/configs/soquartz-blade-rk3566_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig index e87a6392c52..fe2c771db71 100644 --- a/configs/soquartz-cm4-rk3566_defconfig +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig index b2c1684515e..db9eee21751 100644 --- a/configs/soquartz-model-a-rk3566_defconfig +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index fa80d489f5e..3bbd1dbd67c 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -16,6 +16,8 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x8180000 +CONFIG_SPL_BSS_START_ADDR=0x8040000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -49,8 +51,6 @@ CONFIG_SYS_EEPROM_BUS_NUM=5 CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_BSS_START_ADDR=0x8040000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index c893e272db9..caaabf39ef3 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_STM32PROG=y CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_DISTRO_DEFAULTS=y @@ -51,8 +52,17 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_ENV_MMC_USE_DT=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xc0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x02000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y @@ -92,7 +102,6 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_ERRNO_STR=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 005f1d55f80..2e22bf86000 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -97,6 +97,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 3302b306996..ffe7512650e 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -69,6 +69,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index eb6e367b901..8442f0bfe94 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -164,6 +164,8 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index ab92924a9b4..91b64f7537a 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -164,6 +164,8 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 84b0854b557..74deaaba2e4 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -70,6 +70,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 0d547d1a323..f96ab04e91f 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -9,6 +9,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_DEBUG_UART=y @@ -25,11 +29,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2071 CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 8679b905415..52d90f53dfd 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -23,6 +23,9 @@ CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" CONFIG_SPL_STACK=0x304000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3e00 +CONFIG_SPL_BSS_MAX_SIZE=0x600 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=18432000 @@ -43,9 +46,6 @@ CONFIG_SYS_PBSIZE=281 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x3e00 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3e00 -CONFIG_SPL_BSS_MAX_SIZE=0x600 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index e3444fcbc23..ed468b8fe9a 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -16,6 +16,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -33,9 +36,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1bfd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40020000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index edb62945a9e..855cf414a6b 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -17,6 +17,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -31,8 +33,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_CMD_GPIO=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 499094b3e17..2a2e1226eb5 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -17,6 +17,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x800000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -31,8 +33,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_CMD_GPIO=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 79e107f01bf..638d7306146 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -11,6 +11,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" @@ -29,11 +33,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2077 CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 0168cf8657e..af47fab83c0 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -11,6 +11,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" @@ -29,11 +33,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2077 CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 303096325c9..ad321749694 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -11,6 +11,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" @@ -29,11 +33,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2077 CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig index 6ee92e94313..76bfa50c306 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y @@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -33,8 +31,9 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -53,7 +52,7 @@ CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_PINCTRL=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 61fe3d34c99..11a552d9b0d 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SUPPORT_PASSING_ATAGS=y CONFIG_CMDLINE_TAG=y @@ -15,12 +14,13 @@ CONFIG_TEGRA30=y CONFIG_TARGET_TRANSFORMER_T30=y CONFIG_CMD_EBTUPDATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_BUTTON_CMD=y CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="setenv skip_boot 0; setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; if test ${skip_boot} -eq 1; then; else run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff; fi" +CONFIG_BOOTCOMMAND="setenv boot_targets usb mmc1 mmc0; bootflow scan; poweroff" CONFIG_SYS_PBSIZE=2084 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 @@ -71,7 +71,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_TPS65911=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y -CONFIG_TEGRA20_SLINK=y CONFIG_SYSRESET_TPS65910=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 07f7b848529..038b14769e5 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1" @@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -81,7 +79,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_SCSI=y @@ -91,7 +88,6 @@ CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y @@ -109,7 +105,6 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x350b CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index f2b39115fef..9753e270951 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -21,6 +21,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -46,9 +49,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 1e74d83b962..56ab20d787c 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 @@ -24,7 +25,6 @@ CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 CONFIG_SPL_MAX_SIZE=0x10000 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 0c838246953..7e1e2a9d802 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 @@ -24,7 +25,6 @@ CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 CONFIG_SPL_MAX_SIZE=0x10000 CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 633e9c7398e..03730b498fd 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -22,6 +22,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80c80000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 CONFIG_SPL_FS_FAT=y @@ -44,13 +48,9 @@ CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80c80000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 5b4b81c925a..06c63fa6488 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -19,6 +19,11 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_LIBDISK_SUPPORT=y @@ -29,13 +34,8 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 CONFIG_SPL_PAD_TO=0x0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c3b000 -CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 4f1480c610c..ef7f3b1bc10 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -17,6 +17,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x48200000 @@ -38,9 +41,6 @@ CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 4490a4a19a3..fca91f7b1ee 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -23,6 +23,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -49,9 +52,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x98fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -105,8 +105,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_COMPOSITE_CCF=y @@ -161,7 +159,6 @@ CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_POWER_PCA9450=y -CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index 17634ffdf3c..04b093ded82 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_LOAD_ADDR=0x80100000 @@ -35,8 +37,6 @@ CONFIG_LOGLEVEL=8 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x10000 -CONFIG_SPL_BSS_START_ADDR=0x80010000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 02f2d74141f..42c06d1e985 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -18,6 +18,8 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_VYASA_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0xff718000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -30,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_OS_BOOT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0xffe5000 CONFIG_SPL_FALCON_BOOT_MMCSD=y diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig index 7af68bd9afc..c489d59ef0e 100644 --- a/configs/x3_t30_defconfig +++ b/configs/x3_t30_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SUPPORT_PASSING_ATAGS=y CONFIG_CMDLINE_TAG=y @@ -16,12 +15,13 @@ CONFIG_TARGET_X3_T30=y CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_CMD_EBTUPDATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_BUTTON_CMD=y CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_BOOTCOMMAND="bootflow scan; poweroff" CONFIG_SYS_PBSIZE=2084 CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 diff --git a/configs/x530_defconfig b/configs/x530_defconfig index a55379a7ccb..3cd8ef5f9f3 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -16,6 +16,9 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -33,9 +36,6 @@ CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x22fd0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x40023000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 4113409efbb..9364dcebb6f 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -6,6 +6,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 @@ -24,8 +26,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_START_ADDR=0x24000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index 99381478ac5..6b57cc1b9f8 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -6,6 +6,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 @@ -25,8 +27,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_START_ADDR=0x24000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 708cfe96b63..f30fbdf3f64 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -10,6 +10,10 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xE40000 CONFIG_CMD_FRU=y @@ -34,11 +38,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2071 CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x100000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 7af8b27be93..ba42f0c7848 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -15,6 +15,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL_STACK=0xfffffffc +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x2a000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2220000 @@ -40,9 +42,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_FS_LOAD_KERNEL_NAME="" CONFIG_SPL_FS_LOAD_ARGS_NAME="" CONFIG_SPL_FPGA=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index bf34832d22c..49c7235fb8c 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0" CONFIG_SPL_STACK=0xfffffffc CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_REMAKE_ELF=y @@ -26,7 +27,6 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index af70ccfae12..1ef89f50444 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1" CONFIG_SPL_STACK=0xfffffffc CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_REMAKE_ELF=y @@ -26,7 +27,6 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 096feeb83cd..957ae07b80e 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" CONFIG_SPL_STACK=0xfffffffc +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set @@ -29,7 +30,6 @@ CONFIG_LOGLEVEL=0 # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 18931cffbbd..ee87beb19c6 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -10,6 +10,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL_STACK=0xfffffffc +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y CONFIG_SPL_SIZE_LIMIT=0x2a000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1E80000 @@ -34,9 +36,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000 diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 0dbc80442bb..48473d78443 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -12,6 +12,10 @@ CONFIG_ENV_SIZE=0x190 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set @@ -27,11 +31,7 @@ CONFIG_SYS_PBSIZE=1047 # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000 diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index d95f7602d68..9f2b738d9d1 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -12,6 +12,10 @@ CONFIG_ENV_SIZE=0x190 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set @@ -27,11 +31,7 @@ CONFIG_SYS_PBSIZE=1047 # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000 diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index dd7f978c494..5b861bdde18 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -13,6 +13,10 @@ CONFIG_ENV_SIZE=0x190 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +CONFIG_SPL_STACK_R=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x0 CONFIG_DEBUG_UART_CLOCK=0 @@ -34,11 +38,7 @@ CONFIG_SYS_PBSIZE=1047 # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000 diff --git a/doc/board/index.rst b/doc/board/index.rst index f0a11f84ccc..428faa810be 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + schneider/index sielaff/index siemens/index sifive/index diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 5dd5ea7f1e2..9a726e9cde6 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -131,6 +131,8 @@ List of mainline supported Rockchip boards: - Turing Machines RK1 (turing-rk1-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) + - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) + - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) * rv1108 - Rockchip Evb-rv1108 (evb-rv1108) diff --git a/doc/board/schneider/hmibsc.rst b/doc/board/schneider/hmibsc.rst new file mode 100644 index 00000000000..f09fb5af1b3 --- /dev/null +++ b/doc/board/schneider/hmibsc.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org> + +HMIBSC +====== + +The HMIBSC is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. +More information can be found on the `SE product page`_. + +U-Boot can be used as a replacement for Qualcomm's original Android bootloader +(a fork of Little Kernel/LK). Like LK, it is installed directly into the ``aboot`` +partition. Note that the U-Boot port used to be loaded as an Android boot image +through LK. This is no longer the case, now U-Boot can replace LK entirely. + +.. _SE product page: https://www.se.com/us/en/product/HMIBSCEA53D1L0T/iiot-edge-box-core-harmony-ipc-emmc-dc-linux-tpm/ + +Build steps +----------- + +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``hmibsc``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make hmibsc_defconfig + $ make + +This will build ``u-boot.elf`` in the configured output directory. + +Installation +------------ + +Although the HMIBSC does not have secure boot set up by default, the firmware +still expects firmware ELF images to be "signed". The signature does not provide +any security in this case, but it provides the firmware with some required +metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ ./qtestsign.py aboot u-boot.elf + +Then install the resulting ``u-boot-test-signed.mbn`` to the ``aboot`` partition +on your device, e.g. with ``fastboot flash aboot u-boot-test-signed.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign diff --git a/doc/board/schneider/index.rst b/doc/board/schneider/index.rst new file mode 100644 index 00000000000..55792ed3100 --- /dev/null +++ b/doc/board/schneider/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Schneider Electric +================== + +.. toctree:: + :maxdepth: 2 + + hmibsc diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 8d4c112f149..e44252f0fb6 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -19,6 +19,9 @@ Cycle as follows: * After the merge window closes, no new features may be added to allow for a release candidate phase which is intended to fix bugs and regressions. +* To help with late pull requests, the **next** branch will open when the + second release candidate is published. + *Note:* While we try to adhere to the release schedule, we will not hesitate and take the liberty to delay a release if there are good reasons, for example if there are known bugs or other technical @@ -50,8 +53,7 @@ Current Status * U-Boot v2024.04 was released on Tue 02 April 2024. -* The Merge Window for the next release (v2024.07) is **open** until the -rc1 - release on Mon 22 April 2024. +* The Merge Window for the next release (v2024.07) is **closed**. * The next branch is now **closed**. @@ -63,9 +65,9 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -.. For the next scheduled release, release candidates were made on:: +For the next scheduled release, release candidates were made on:: -.. * U-Boot v2024.07-rc1 was released on Mon 22 April 2024. +* U-Boot v2024.07-rc1 was released on Mon 22 April 2024. .. * U-Boot v2024.07-rc2 was released on Tue 06 May 2024. diff --git a/doc/device-tree-bindings/serial/msm-serial.txt b/doc/device-tree-bindings/serial/msm-serial.txt deleted file mode 100644 index dca995798a9..00000000000 --- a/doc/device-tree-bindings/serial/msm-serial.txt +++ /dev/null @@ -1,10 +0,0 @@ -Qualcomm UART (Data Mover mode) - -Required properties: -- compatible: must be "qcom,msm-uartdm-v1.4" -- reg: start address and size of the registers -- clock: interface clock (must accept baudrate as a frequency) - -Optional properties: -- bit-rate: Data Mover bit rate register value - (If not defined then 0xCC is used as default) diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst index a7e21693a67..040076bcc03 100644 --- a/doc/usage/cmd/env.rst +++ b/doc/usage/cmd/env.rst @@ -16,18 +16,18 @@ Synopsis env default [-f] (-a | var [...]) env delete [-f] var [...] env edit name + env erase env exists name env export [-t | -b | -c] [-s size] addr [var ...] env flags env grep [-e] [-n | -v | -b] string [...] env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] env info [-d] [-p] [-q] + env load env print [-a | name ...] env print -e [-guid guid] [-n] [name ...] env run var [...] env save - env erase - env load env select [target] env set [-f] name [value] env set -e [-nv][-bs][-rt][-at][-a][-i addr:size][-v] name [value] @@ -40,11 +40,12 @@ the UEFI variables. The next commands are kept as alias and for compatibility: ++ :doc:`askenv <askenv>` = *env ask* + *editenv* = *env edit* + *grepenv* = *env grep* -+ *setenv* = *env set* -+ *askenv* = *env ask* ++ :doc:`printenv <printenv>` = *env print* + *run* = *env run* ++ *setenv* = *env set* Ask ~~~ @@ -103,6 +104,11 @@ The *env edit* command edits an environment variable. name name of the variable. +Erase +~~~~~ + +The *env erase* command erases the U-Boot environment. + Exists ~~~~~~ @@ -204,6 +210,11 @@ environment information. quiet output, use only for command result, by example with 'test' command. +Load +~~~~ + +The *env load* command loads the U-Boot environment from persistent storage. + Print ~~~~~ @@ -235,16 +246,6 @@ Save The *env save* command saves the U-Boot environment in persistent storage. -Erase -~~~~~ - -The *env erase* command erases the U-Boot environment. - -Load -~~~~ - -The *env load* command loads the U-Boot environment from persistent storage. - Select ~~~~~~ @@ -350,15 +351,15 @@ edit exists CONFIG_CMD_ENV_EXISTS -flags - CONFIG_CMD_ENV_FLAGS - erase CONFIG_CMD_ERASEENV export CONFIG_CMD_EXPORTENV +flags + CONFIG_CMD_ENV_FLAGS + grep CONFIG_CMD_GREPENV, CONFIG_REGEX for '-e' option diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index bad445efa86..ad7fed3ddaa 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -19,6 +19,13 @@ #define REG_TYPE 0x4 #define REG_SUBTYPE 0x5 +struct qcom_pmic_btn_data { + char *compatible; + unsigned int status_bit; + int code; + char *label; +}; + struct qcom_pmic_btn_priv { u32 base; u32 status_bit; @@ -27,11 +34,10 @@ struct qcom_pmic_btn_priv { }; #define PON_INT_RT_STS 0x10 -#define KPDPWR_ON_INT_BIT 0 -#define RESIN_ON_INT_BIT 1 - -#define NODE_IS_PWRKEY(node) (!strncmp(ofnode_get_name(node), "pwrkey", strlen("pwrkey"))) -#define NODE_IS_RESIN(node) (!strncmp(ofnode_get_name(node), "resin", strlen("resin"))) +#define PON_KPDPWR_N_SET 0 +#define PON_RESIN_N_SET 1 +#define PON_GEN3_RESIN_N_SET 6 +#define PON_GEN3_KPDPWR_N_SET 7 static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev) { @@ -52,10 +58,51 @@ static int qcom_pwrkey_get_code(struct udevice *dev) return priv->code; } +static const struct qcom_pmic_btn_data qcom_pmic_btn_data_table[] = { + { + .compatible = "qcom,pm8941-pwrkey", + .status_bit = PON_KPDPWR_N_SET, + .code = KEY_ENTER, + .label = "pwrkey", + }, + { + .compatible = "qcom,pm8941-resin", + .status_bit = PON_RESIN_N_SET, + .code = KEY_DOWN, + .label = "vol_down", + }, + { + .compatible = "qcom,pmk8350-pwrkey", + .status_bit = PON_GEN3_KPDPWR_N_SET, + .code = KEY_ENTER, + .label = "pwrkey", + }, + { + .compatible = "qcom,pmk8350-resin", + .status_bit = PON_GEN3_RESIN_N_SET, + .code = KEY_DOWN, + .label = "vol_down", + }, +}; + +static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qcom_pmic_btn_data_table); ++i) { + if (ofnode_device_is_compatible(node, + qcom_pmic_btn_data_table[i].compatible)) + return &qcom_pmic_btn_data_table[i]; + } + + return NULL; +} + static int qcom_pwrkey_probe(struct udevice *dev) { struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev); struct qcom_pmic_btn_priv *priv = dev_get_priv(dev); + const struct qcom_pmic_btn_data *btn_data; ofnode node = dev_ofnode(dev); int ret; u64 base; @@ -64,6 +111,14 @@ static int qcom_pwrkey_probe(struct udevice *dev) if (!uc_plat->label) return 0; + /* Get the data for the node compatible */ + btn_data = button_qcom_pmic_match(node); + if (!btn_data) + return -EINVAL; + + priv->status_bit = btn_data->status_bit; + priv->code = btn_data->code; + /* the pwrkey and resin nodes are children of the "pon" node, get the * PMIC device to use in pmic_reg_* calls. */ @@ -87,23 +142,10 @@ static int qcom_pwrkey_probe(struct udevice *dev) ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE); if (ret < 0 || (ret & 0x7) == 0) { - printf("%s: unexpected PMCI function subtype %d\n", dev->name, ret); + printf("%s: unexpected PMIC function subtype %d\n", dev->name, ret); return -ENXIO; } - if (NODE_IS_PWRKEY(node)) { - priv->status_bit = 0; - priv->code = KEY_ENTER; - } else if (NODE_IS_RESIN(node)) { - priv->status_bit = 1; - priv->code = KEY_DOWN; - } else { - /* Should not get here! */ - printf("Invalid pon node '%s' should be 'pwrkey' or 'resin'\n", - ofnode_get_name(node)); - return -EINVAL; - } - return 0; } @@ -114,12 +156,20 @@ static int button_qcom_pmic_bind(struct udevice *parent) int ret; dev_for_each_subnode(node, parent) { + const struct qcom_pmic_btn_data *btn_data; struct button_uc_plat *uc_plat; const char *label; if (!ofnode_is_enabled(node)) continue; + /* Get the data for the node compatible */ + btn_data = button_qcom_pmic_match(node); + if (!btn_data) { + debug("Unknown button node '%s'\n", ofnode_get_name(node)); + continue; + } + ret = device_bind_driver_to_node(parent, "qcom_pwrkey", ofnode_get_name(node), node, &dev); @@ -128,15 +178,7 @@ static int button_qcom_pmic_bind(struct udevice *parent) return ret; } uc_plat = dev_get_uclass_plat(dev); - if (NODE_IS_PWRKEY(node)) { - uc_plat->label = "pwrkey"; - } else if (NODE_IS_RESIN(node)) { - uc_plat->label = "vol_down"; - } else { - debug("Unknown button node '%s' should be 'pwrkey' or 'resin'\n", - ofnode_get_name(node)); - device_unbind(dev); - } + uc_plat->label = btn_data->label; } return 0; @@ -151,6 +193,7 @@ static const struct udevice_id qcom_pwrkey_ids[] = { { .compatible = "qcom,pm8916-pon" }, { .compatible = "qcom,pm8941-pon" }, { .compatible = "qcom,pm8998-pon" }, + { .compatible = "qcom,pmk8350-pon" }, { } }; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 017dd260a54..bda6873be33 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -57,27 +57,27 @@ config CLK_BOSTON Enable this to support the clocks config SPL_CLK_CCF - bool "SPL Common Clock Framework [CCF] support " + bool "SPL Common Clock Framework [CCF] support" depends on SPL help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's SPL. config SPL_CLK_COMPOSITE_CCF - bool "SPL Common Clock Framework [CCF] composite clk support " + bool "SPL Common Clock Framework [CCF] composite clk support" depends on SPL_CLK_CCF help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] composite code in U-Boot's SPL. config CLK_CCF - bool "Common Clock Framework [CCF] support " + bool "Common Clock Framework [CCF] support" help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's clock driver. config CLK_COMPOSITE_CCF - bool "Common Clock Framework [CCF] composite clk support " + bool "Common Clock Framework [CCF] composite clk support" depends on CLK_CCF help Enable this option if you want to (re-)use the Linux kernel's Common @@ -164,7 +164,7 @@ config CLK_OCTEON Enable this to support the clocks on Octeon MIPS platforms. config SANDBOX_CLK_CCF - bool "Sandbox Common Clock Framework [CCF] support " + bool "Sandbox Common Clock Framework [CCF] support" depends on SANDBOX select CLK_CCF help diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b5c253e4966..1a00dd1d287 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -66,6 +66,17 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_ static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +#if CONFIG_IS_ENABLED(PCIE_DW_IMX) +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", + "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; + +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4", "sys_pll1_400m", }; + +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", + "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; +#endif + #ifndef CONFIG_SPL_BUILD static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; @@ -256,6 +267,17 @@ static int imx8mm_clk_probe(struct udevice *dev) imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); /* IP */ +#if CONFIG_IS_ENABLED(PCIE_DW_IMX) + clk_dm(IMX8MM_CLK_PCIE1_CTRL, + imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, + base + 0xa300)); + clk_dm(IMX8MM_CLK_PCIE1_PHY, + imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, + base + 0xa380)); + clk_dm(IMX8MM_CLK_PCIE1_AUX, + imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, + base + 0xa400)); +#endif clk_dm(IMX8MM_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, base + 0xac00)); @@ -339,6 +361,11 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif +#if CONFIG_IS_ENABLED(PCIE_DW_IMX) + clk_dm(IMX8MM_CLK_PCIE1_ROOT, + imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); +#endif + #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MM_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 8dae635ac2c..45d63c6d6db 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019 on the Snapdragon IPQ4019 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_QCM2290 + bool "Qualcomm QCM2290 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon QCM2290 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select CLK_QCOM @@ -47,6 +55,37 @@ config CLK_QCOM_SDM845 on the Snapdragon 845 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SM6115 + bool "Qualcomm SM6115 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM6115 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +config CLK_QCOM_SM8250 + bool "Qualcomm SM8250 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM8250 SoC. This driver supports the clocks + +config CLK_QCOM_SM8550 + bool "Qualcomm SM8550 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM8550 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +config CLK_QCOM_SM8650 + bool "Qualcomm SM8650 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM8650 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index cb179fdac58..dec20e4b594 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -7,4 +7,9 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o +obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o +obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o +obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o +obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c8..d3b63b9c1ac 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -31,7 +31,8 @@ #define BLSP1_AHB_CBCR 0x1008 /* Uart clock control registers */ -#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART1_APPS_CBCR (0x203C) +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) @@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { }; /* SDHCI */ -static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) +static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { int div = 15; /* 100MHz default */ @@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) } /* UART: 115200 */ -int apq8016_clk_init_uart(phys_addr_t base) +int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) { + u32 cmd_rcgr, apps_cbcr; + + switch (id) { + case GCC_BLSP1_UART1_APPS_CLK: + cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART1_APPS_CBCR; + break; + case GCC_BLSP1_UART2_APPS_CLK: + cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART2_APPS_CBCR; + break; + default: + return 0; + } + /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, - CFG_CLK_SRC_GPLL0, 16); + clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0, + 16); /* Vote for gpll0 clock */ clk_enable_gpll0(base, &gpll0_vote_clk); /* Enable core clk */ - clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR); + clk_enable_cbc(base + apps_cbcr); return 0; } @@ -94,14 +110,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_SDCC1_APPS_CLK: /* SDC1 */ - return clk_init_sdc(priv, 0, rate); - break; + return apq8016_clk_init_sdc(priv, 0, rate); case GCC_SDCC2_APPS_CLK: /* SDC2 */ - return clk_init_sdc(priv, 1, rate); - break; + return apq8016_clk_init_sdc(priv, 1, rate); + case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */ case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + apq8016_clk_init_uart(priv->base, clk->id); + return 7372800; default: return 0; } diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index d693776d339..72f235eab21 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -21,7 +21,7 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ - return 0; + return 1843200; default: return -EINVAL; } diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c new file mode 100644 index 00000000000..c78705cb8cf --- /dev/null +++ b/drivers/clk/qcom/clock-qcm2290.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm qcm2290 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-qcm2290.h> + +#include "clock-qcom.h" + +#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 +#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), + {} +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + F(202000000, CFG_CLK_SRC_GPLL7, 4, 0, 0), // 6.5, 1, 4 + {} +}; + +static const struct pll_vote_clk gpll7_clk = { + .status = 0x7000, + .status_bit = BIT(31), + .ena_vote = 0x79000, + .vote_bit = BIT(7), +}; + +static const struct gate_clk qcm2290_clks[] = { + GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, 0x00000001), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, 0x00000200), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, 0x00000100), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, 0x00000400), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, 0x00000800), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, 0x00001000), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, 0x00002000), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, 0x00004000), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, 0x00008000), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, 0x00000040), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, 0x00000080), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, 0x00000001), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, 0x00000001), + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, 0x00000001), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, 0x00000001), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, 0x00000001), + GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, 0x00000001), + GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x9f000, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, 0x00000001), +}; + +static ulong qcm2290_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + debug("%s: clk %s rate %lu\n", __func__, clk->dev->name, rate); + + switch (clk->id) { + case GCC_QUPV3_WRAP0_S4_CLK: /*UART2*/ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 16); + return 0; + case GCC_SDCC2_APPS_CLK: + /* Enable GPLL7 so we can point SDCC2_APPS_CLK_SRC RCG at it */ + clk_enable_gpll0(priv->base, &gpll7_clk); + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + WARN(freq->src != CFG_CLK_SRC_GPLL7, + "SDCC2_APPS_CLK_SRC not set to GPLL7, requested rate %lu\n", + rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 8); + return freq->freq; + case GCC_SDCC1_APPS_CLK: + /* The firmware turns this on for us and always sets it to this rate */ + return 384000000; + default: + return 0; + } +} + +static int qcm2290_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, qcm2290_clks[clk->id].name); + + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map qcm2290_gcc_resets[] = { + [GCC_CAMSS_OPE_BCR] = { 0x55000 }, + [GCC_CAMSS_TFE_BCR] = { 0x52000 }, + [GCC_CAMSS_TOP_BCR] = { 0x58000 }, + [GCC_GPU_BCR] = { 0x36000 }, + [GCC_MMSS_BCR] = { 0x17000 }, + [GCC_PDM_BCR] = { 0x20000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_SDCC1_BCR] = { 0x38000 }, + [GCC_SDCC2_BCR] = { 0x1e000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_VCODEC0_BCR] = { 0x58094 }, + [GCC_VENUS_BCR] = { 0x58078 }, + [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, +}; + +static const struct qcom_power_map qcm2290_gdscs[] = { + [GCC_USB30_PRIM_GDSC] = { 0x1a004 }, +}; + +static struct msm_clk_data qcm2290_gcc_data = { + .resets = qcm2290_gcc_resets, + .num_resets = ARRAY_SIZE(qcm2290_gcc_resets), + .clks = qcm2290_clks, + .num_clks = ARRAY_SIZE(qcm2290_clks), + .power_domains = qcm2290_gdscs, + .num_power_domains = ARRAY_SIZE(qcm2290_gdscs), + + .enable = qcm2290_enable, + .set_rate = qcm2290_set_rate, +}; + +static const struct udevice_id gcc_qcm2290_of_match[] = { + { + .compatible = "qcom,gcc-qcm2290", + .data = (ulong)&qcm2290_gcc_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_qcm2290) = { + .name = "gcc_qcm2290", + .id = UCLASS_NOP, + .of_match = gcc_qcm2290_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index a7f833a4b6d..f6445c8f566 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -9,6 +9,11 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) +#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) +#define CFG_CLK_SRC_GPLL9 (2 << 8) +#define CFG_CLK_SRC_GPLL6 (4 << 8) +#define CFG_CLK_SRC_GPLL7 (3 << 8) +#define CFG_CLK_SRC_GPLL4 (5 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index e9c61eb480d..782df7da844 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -24,6 +24,7 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c +#define SDCC2_APPS_CLK_CMD_RCGR 0x1400c static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), @@ -44,6 +45,17 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(9600000, CFG_CLK_SRC_CXO, 2, 0, 0), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(201500000, CFG_CLK_SRC_GPLL4, 4, 0, 0), + { } +}; + static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -55,6 +67,11 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; default: return 0; } diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c new file mode 100644 index 00000000000..8314a0deb34 --- /dev/null +++ b/drivers/clk/qcom/clock-sm6115.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm6115 (and sm4250/qrb4210) + * + * Copyright (c) 2024 Linaro Ltd. + * + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <dt-bindings/clock/qcom,gcc-sm6115.h> + +#include "clock-qcom.h" + +#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 +#define SDCC1_APPS_CLK_CMD_RCGR 0x38028 +#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), + {} +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + {} +}; + +static const struct pll_vote_clk gpll0_clk = { + .status = 0, + .status_bit = BIT(31), + .ena_vote = 0x79000, + .vote_bit = BIT(0), +}; + +static const struct gate_clk sm6115_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, 0x00000001), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, 0x00000200), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, 0x00000100), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, 0x00000400), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, 0x00000800), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, 0x00001000), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, 0x00002000), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, 0x00004000), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, 0x00008000), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, 0x00000040), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, 0x00000080), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, 0x00000001), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, 0x00000001), + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, 0x00000001), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, 0x00000001), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, 0x00000001), + GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, 0x00000001), + GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, 0x00000001), + GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, 0x00000001), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, 0x00000001), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, 0x00000001), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x9f000, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, 0x00000001), + GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001), + GATE_CLK(GCC_UFS_CLKREF_CLK, 0x8c000, 0x00000001), +}; + +static ulong sm6115_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + debug("%s: clk %s rate %lu\n", __func__, sm6115_clks[clk->id].name, + rate); + + switch (clk->id) { + case GCC_QUPV3_WRAP0_S4_CLK: /*UART2*/ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 16); + return 0; + case GCC_SDCC2_APPS_CLK: + /* Enable GPLL7 so we can point SDCC2_APPS_CLK_SRC RCG at it */ + clk_enable_gpll0(priv->base, &gpll0_clk); + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + WARN(freq->src != CFG_CLK_SRC_GPLL0, + "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n", + rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 8); + return freq->freq; + case GCC_SDCC1_APPS_CLK: + /* The firmware turns this on for us and always sets it to this rate */ + return 384000000; + default: + return rate; + } +} + +static int sm6115_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, sm6115_clks[clk->id].name); + + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sm6115_gcc_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_SDCC1_BCR] = { 0x38000 }, + [GCC_SDCC2_BCR] = { 0x1e000 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_VCODEC0_BCR] = { 0x58094 }, + [GCC_VENUS_BCR] = { 0x58078 }, + [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, +}; + +static const struct qcom_power_map sm6115_gdscs[] = { + [GCC_USB30_PRIM_GDSC] = { 0x1a004 }, +}; + +static struct msm_clk_data sm6115_gcc_data = { + .resets = sm6115_gcc_resets, + .num_resets = ARRAY_SIZE(sm6115_gcc_resets), + .clks = sm6115_clks, + .num_clks = ARRAY_SIZE(sm6115_clks), + .power_domains = sm6115_gdscs, + .num_power_domains = ARRAY_SIZE(sm6115_gdscs), + + .enable = sm6115_enable, + .set_rate = sm6115_set_rate, +}; + +static const struct udevice_id gcc_sm6115_of_match[] = { + { + .compatible = "qcom,gcc-sm6115", + .data = (ulong)&sm6115_gcc_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_sm6115) = { + .name = "gcc_sm6115", + .id = UCLASS_NOP, + .of_match = gcc_sm6115_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c new file mode 100644 index 00000000000..af10fc11621 --- /dev/null +++ b/drivers/clk/qcom/clock-sm8250.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm8250 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-sm8250.h> + +#include "clock-qcom.h" + +#define GCC_SE12_UART_RCG_REG 0x184D0 +#define GCC_SDCC2_APPS_CLK_SRC_REG 0x1400c + +#define APCS_GPLL0_ENA_VOTE 0x79000 +#define APCS_GPLL9_STATUS 0x1c000 +#define APCS_GPLLX_ENA_REG 0x52018 + +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf064 + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + {} +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), + {} +}; + +static struct pll_vote_clk gpll9_vote_clk = { + .status = APCS_GPLL9_STATUS, + .status_bit = BIT(31), + .ena_vote = APCS_GPLLX_ENA_REG, + .vote_bit = BIT(9), +}; + +static ulong sm8250_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, + priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_QUPV3_WRAP1_S4_CLK: /*UART2*/ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s4_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, GCC_SE12_UART_RCG_REG, + freq->pre_div, freq->m, freq->n, freq->src, + 16); + + return freq->freq; + case GCC_SDCC2_APPS_CLK: + /* Enable GPLL9 so that we can point SDCC2_APPS_CLK_SRC at it */ + clk_enable_gpll0(priv->base, &gpll9_vote_clk); + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + printf("%s: got freq %u\n", __func__, freq->freq); + WARN(freq->src != CFG_CLK_SRC_GPLL9, + "SDCC2_APPS_CLK_SRC not set to GPLL9, requested rate %lu\n", + rate); + clk_rcg_set_rate_mnd(priv->base, GCC_SDCC2_APPS_CLK_SRC_REG, + freq->pre_div, freq->m, freq->n, + CFG_CLK_SRC_GPLL9, 8); + + return rate; + default: + return 0; + } +} + +static const struct gate_clk sm8250_clks[] = { + GATE_CLK(GCC_AGGRE_UFS_CARD_AXI_CLK, 0x750cc, 0x00000001), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, 0x00000001), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x0f080, 0x00000001), + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x10080, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x0f07c, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x1007c, 0x00000001), + GATE_CLK(GCC_QMIP_CAMERA_NRT_AHB_CLK, 0x0b018, 0x00000001), + GATE_CLK(GCC_QMIP_CAMERA_RT_AHB_CLK, 0x0b01c, 0x00000001), + GATE_CLK(GCC_QMIP_DISP_AHB_CLK, 0x0b020, 0x00000001), + GATE_CLK(GCC_QMIP_VIDEO_CVP_AHB_CLK, 0x0b010, 0x00000001), + GATE_CLK(GCC_QMIP_VIDEO_VCODEC_AHB_CLK, 0x0b014, 0x00000001), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x52008, 0x00000200), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x52008, 0x00000100), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, 0x00000400), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, 0x00000800), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x52008, 0x00001000), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, 0x00002000), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x52008, 0x00004000), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, 0x00008000), + GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, 0x00010000), + GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, 0x00020000), + GATE_CLK(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x52008, 0x00040000), + GATE_CLK(GCC_QUPV3_WRAP1_CORE_CLK, 0x52008, 0x00080000), + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x52008, 0x00400000), + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, 0x00800000), + GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x52008, 0x01000000), + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x52008, 0x02000000), + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x52008, 0x04000000), + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x52008, 0x08000000), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, 0x00000008), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, 0x00000001), + GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, 0x00000010), + GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, 0x00000020), + GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, 0x00000040), + GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, 0x00000080), + GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, 0x00000100), + GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, 0x00000200), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x52008, 0x00000040), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x52008, 0x00000080), + GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x52008, 0x00100000), + GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x52008, 0x00200000), + GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, 0x00000004), + GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, 0x00000002), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001), + GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001), + GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001), + GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75018, 0x00000001), + GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x75010, 0x00000001), + GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75064, 0x00000001), + GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7509c, 0x00000001), + GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75020, 0x00000001), + GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750b8, 0x00000001), + GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x7501c, 0x00000001), + GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x7505c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, 0x00000001), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, 0x00000001), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, 0x00000001), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f010, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f01c, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f018, 0x00000001), + GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x10010, 0x00000001), + GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x1001c, 0x00000001), + GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10018, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f054, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f058, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f05c, 0x00000001), + GATE_CLK(GCC_USB3_SEC_CLKREF_EN, 0x8c010, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x10054, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10058, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x1005c, 0x00000001), +}; + +static int sm8250_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, sm8250_clks[clk->id].name); + + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sm8250_gcc_resets[] = { + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_MMSS_BCR] = { 0xb000 }, + [GCC_NPU_BWMON_BCR] = { 0x73000 }, + [GCC_NPU_BCR] = { 0x4d000 }, + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 }, + [GCC_PCIE_2_BCR] = { 0x6000 }, + [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 }, + [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 }, + [GCC_PCIE_2_PHY_BCR] = { 0x1f01c }, + [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_PRNG_BCR] = { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_TSIF_BCR] = { 0x36000 }, + [GCC_UFS_CARD_BCR] = { 0x75000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB30_SEC_BCR] = { 0x10000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct qcom_power_map sm8250_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, [PCIE_1_GDSC] = { 0x8d004 }, + [PCIE_2_GDSC] = { 0x6004 }, [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, +}; + +static struct msm_clk_data qcs404_gcc_data = { + .resets = sm8250_gcc_resets, + .num_resets = ARRAY_SIZE(sm8250_gcc_resets), + .clks = sm8250_clks, + .num_clks = ARRAY_SIZE(sm8250_clks), + .power_domains = sm8250_gdscs, + .num_power_domains = ARRAY_SIZE(sm8250_gdscs), + + .enable = sm8250_enable, + .set_rate = sm8250_set_rate, +}; + +static const struct udevice_id gcc_sm8250_of_match[] = { + { + .compatible = "qcom,gcc-sm8250", + .data = (ulong)&qcs404_gcc_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_sm8250) = { + .name = "gcc_sm8250", + .id = UCLASS_NOP, + .of_match = gcc_sm8250_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c new file mode 100644 index 00000000000..c0249925cc7 --- /dev/null +++ b/drivers/clk/qcom/clock-sm8550.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm8550 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,sm8550-gcc.h> +#include <dt-bindings/clock/qcom,sm8550-tcsr.h> + +#include "clock-qcom.h" + +/* On-board TCXO, TOFIX get from DT */ +#define TCXO_RATE 38400000 + +/* bi_tcxo_div2 divided after RPMh output */ +#define TCXO_DIV2_RATE (TCXO_RATE / 2) + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(51200000, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */ + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +static ulong sm8550_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_QUPV3_WRAP1_S7_CLK: /* UART7 */ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s2_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x18898, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x14018, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3902c, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + clk_rcg_set_rate(priv->base, 0x39044, 0, 0); + return TCXO_DIV2_RATE; + case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: + clk_rcg_set_rate(priv->base, 0x39070, 0, 0); + return TCXO_DIV2_RATE; + default: + return 0; + } +} + +static const struct gate_clk sm8550_clks[] = { + GATE_CLK(GCC_AGGRE_NOC_PCIE_AXI_CLK, 0x52000, BIT(12)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK, 0x770e4, BIT(1)), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_CNOC_PCIE_SF_AXI_CLK, 0x52008, BIT(6)), + GATE_CLK(GCC_DDRSS_GPU_AXI_CLK, 0x71154, BIT(0)), + GATE_CLK(GCC_DDRSS_PCIE_SF_QTB_CLK, 0x52000, BIT(19)), + GATE_CLK(GCC_PCIE_0_AUX_CLK, 0x52008, BIT(3)), + GATE_CLK(GCC_PCIE_0_CFG_AHB_CLK, 0x52008, BIT(2)), + GATE_CLK(GCC_PCIE_0_MSTR_AXI_CLK, 0x52008, BIT(1)), + GATE_CLK(GCC_PCIE_0_PHY_RCHNG_CLK, 0x52000, BIT(22)), + GATE_CLK(GCC_PCIE_0_PIPE_CLK, 0x52008, BIT(4)), + GATE_CLK(GCC_PCIE_0_SLV_AXI_CLK, 0x52008, BIT(0)), + GATE_CLK(GCC_PCIE_0_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), + GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)), + GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)), + GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)), + GATE_CLK(GCC_PCIE_1_PHY_AUX_CLK, 0x52000, BIT(24)), + GATE_CLK(GCC_PCIE_1_PHY_RCHNG_CLK, 0x52000, BIT(23)), + GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)), + GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)), + GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)), + GATE_CLK(GCC_QUPV3_I2C_CORE_CLK, 0x52008, BIT(8)), + GATE_CLK(GCC_QUPV3_I2C_S0_CLK, 0x52008, BIT(10)), + GATE_CLK(GCC_QUPV3_I2C_S1_CLK, 0x52008, BIT(11)), + GATE_CLK(GCC_QUPV3_I2C_S2_CLK, 0x52008, BIT(12)), + GATE_CLK(GCC_QUPV3_I2C_S3_CLK, 0x52008, BIT(13)), + GATE_CLK(GCC_QUPV3_I2C_S4_CLK, 0x52008, BIT(14)), + GATE_CLK(GCC_QUPV3_I2C_S5_CLK, 0x52008, BIT(15)), + GATE_CLK(GCC_QUPV3_I2C_S6_CLK, 0x52008, BIT(16)), + GATE_CLK(GCC_QUPV3_I2C_S7_CLK, 0x52008, BIT(17)), + GATE_CLK(GCC_QUPV3_I2C_S8_CLK, 0x52010, BIT(14)), + GATE_CLK(GCC_QUPV3_I2C_S9_CLK, 0x52010, BIT(15)), + GATE_CLK(GCC_QUPV3_I2C_S_AHB_CLK, 0x52008, BIT(7)), + GATE_CLK(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x52008, BIT(18)), + GATE_CLK(GCC_QUPV3_WRAP1_CORE_CLK, 0x52008, BIT(19)), + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x52008, BIT(22)), + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)), + GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x52008, BIT(24)), + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x52008, BIT(25)), + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x52008, BIT(26)), + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x52008, BIT(27)), + GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x52008, BIT(28)), + GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x52010, BIT(16)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), + GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)), + GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)), + GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)), + GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x52008, BIT(20)), + GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x52008, BIT(21)), + GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)), + GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14010, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77024, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_HW_CTL_CLK, 0x77018, BIT(1)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77074, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK, 0x77074, BIT(1)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x770b0, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK, 0x770b0, BIT(1)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7702c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770cc, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77028, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77068, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK, 0x77068, BIT(1)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), +}; + +static int sm8550_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sm8550_gcc_resets[] = { + [GCC_CAMERA_BCR] = { 0x26000 }, + [GCC_DISPLAY_BCR] = { 0x27000 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, + [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0x39000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, + [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, + [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, + [GCC_VIDEO_BCR] = { 0x32000 }, +}; + +static const struct qcom_power_map sm8550_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_0_PHY_GDSC] = { 0x6c000 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [PCIE_1_PHY_GDSC] = { 0x8e000 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [UFS_MEM_PHY_GDSC] = { 0x9e000 }, + [USB30_PRIM_GDSC] = { 0x39004 }, + [USB3_PHY_GDSC] = { 0x50018 }, +}; + +static struct msm_clk_data sm8550_gcc_data = { + .resets = sm8550_gcc_resets, + .num_resets = ARRAY_SIZE(sm8550_gcc_resets), + .clks = sm8550_clks, + .num_clks = ARRAY_SIZE(sm8550_clks), + .power_domains = sm8550_gdscs, + .num_power_domains = ARRAY_SIZE(sm8550_gdscs), + + .enable = sm8550_enable, + .set_rate = sm8550_set_rate, +}; + +static const struct udevice_id gcc_sm8550_of_match[] = { + { + .compatible = "qcom,sm8550-gcc", + .data = (ulong)&sm8550_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sm8550) = { + .name = "gcc_sm8550", + .id = UCLASS_NOP, + .of_match = gcc_sm8550_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + +/* TCSRCC */ + +static const struct gate_clk sm8550_tcsr_clks[] = { + GATE_CLK(TCSR_PCIE_0_CLKREF_EN, 0x15100, BIT(0)), + GATE_CLK(TCSR_PCIE_1_CLKREF_EN, 0x15114, BIT(0)), + GATE_CLK(TCSR_UFS_CLKREF_EN, 0x15110, BIT(0)), + GATE_CLK(TCSR_UFS_PAD_CLKREF_EN, 0x15104, BIT(0)), + GATE_CLK(TCSR_USB2_CLKREF_EN, 0x15118, BIT(0)), + GATE_CLK(TCSR_USB3_CLKREF_EN, 0x15108, BIT(0)), +}; + +static struct msm_clk_data sm8550_tcsrcc_data = { + .clks = sm8550_tcsr_clks, + .num_clks = ARRAY_SIZE(sm8550_tcsr_clks), +}; + +static int tcsrcc_sm8550_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static ulong tcsrcc_sm8550_clk_get_rate(struct clk *clk) +{ + return TCXO_RATE; +} + +static int tcsrcc_sm8550_clk_probe(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->data = data; + + return 0; +} + +static struct clk_ops tcsrcc_sm8550_clk_ops = { + .enable = tcsrcc_sm8550_clk_enable, + .get_rate = tcsrcc_sm8550_clk_get_rate, +}; + +static const struct udevice_id tcsrcc_sm8550_of_match[] = { + { + .compatible = "qcom,sm8550-tcsr", + .data = (ulong)&sm8550_tcsrcc_data, + }, + { } +}; + +U_BOOT_DRIVER(tcsrcc_sm8550) = { + .name = "tcsrcc_sm8550", + .id = UCLASS_CLK, + .of_match = tcsrcc_sm8550_of_match, + .ops = &tcsrcc_sm8550_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = tcsrcc_sm8550_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c new file mode 100644 index 00000000000..0ce83e9b243 --- /dev/null +++ b/drivers/clk/qcom/clock-sm8650.c @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm8650 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,sm8650-gcc.h> +#include <dt-bindings/clock/qcom,sm8650-tcsr.h> + +#include "clock-qcom.h" + +/* On-board TCXO, TOFIX get from DT */ +#define TCXO_RATE 38400000 + +/* bi_tcxo_div2 divided after RPMh output */ +#define TCXO_DIV2_RATE (TCXO_RATE / 2) + +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */ + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +static ulong sm8650_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_QUPV3_WRAP2_S7_CLK: /* UART15 */ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s3_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x1e898, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x14018, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3902c, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + clk_rcg_set_rate(priv->base, 0x39044, 0, 0); + return TCXO_DIV2_RATE; + case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: + clk_rcg_set_rate(priv->base, 0x39070, 0, 0); + return TCXO_DIV2_RATE; + default: + return 0; + } +} + +static const struct gate_clk sm8650_clks[] = { + GATE_CLK(GCC_AGGRE_NOC_PCIE_AXI_CLK, 0x52000, BIT(12)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK, 0x770e4, BIT(1)), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_CNOC_PCIE_SF_AXI_CLK, 0x52008, BIT(6)), + GATE_CLK(GCC_DDRSS_GPU_AXI_CLK, 0x71154, BIT(0)), + GATE_CLK(GCC_DDRSS_PCIE_SF_QTB_CLK, 0x52000, BIT(19)), + GATE_CLK(GCC_PCIE_0_AUX_CLK, 0x52008, BIT(3)), + GATE_CLK(GCC_PCIE_0_CFG_AHB_CLK, 0x52008, BIT(2)), + GATE_CLK(GCC_PCIE_0_MSTR_AXI_CLK, 0x52008, BIT(1)), + GATE_CLK(GCC_PCIE_0_PHY_RCHNG_CLK, 0x52000, BIT(22)), + GATE_CLK(GCC_PCIE_0_PIPE_CLK, 0x52008, BIT(4)), + GATE_CLK(GCC_PCIE_0_SLV_AXI_CLK, 0x52008, BIT(0)), + GATE_CLK(GCC_PCIE_0_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), + GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)), + GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)), + GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)), + GATE_CLK(GCC_PCIE_1_PHY_AUX_CLK, 0x52000, BIT(24)), + GATE_CLK(GCC_PCIE_1_PHY_RCHNG_CLK, 0x52000, BIT(23)), + GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)), + GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)), + GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)), + GATE_CLK(GCC_QUPV3_I2C_CORE_CLK, 0x52008, BIT(8)), + GATE_CLK(GCC_QUPV3_I2C_S0_CLK, 0x52008, BIT(10)), + GATE_CLK(GCC_QUPV3_I2C_S1_CLK, 0x52008, BIT(11)), + GATE_CLK(GCC_QUPV3_I2C_S2_CLK, 0x52008, BIT(12)), + GATE_CLK(GCC_QUPV3_I2C_S3_CLK, 0x52008, BIT(13)), + GATE_CLK(GCC_QUPV3_I2C_S4_CLK, 0x52008, BIT(14)), + GATE_CLK(GCC_QUPV3_I2C_S5_CLK, 0x52008, BIT(15)), + GATE_CLK(GCC_QUPV3_I2C_S6_CLK, 0x52008, BIT(16)), + GATE_CLK(GCC_QUPV3_I2C_S7_CLK, 0x52008, BIT(17)), + GATE_CLK(GCC_QUPV3_I2C_S8_CLK, 0x52010, BIT(14)), + GATE_CLK(GCC_QUPV3_I2C_S9_CLK, 0x52010, BIT(15)), + GATE_CLK(GCC_QUPV3_I2C_S_AHB_CLK, 0x52008, BIT(7)), + GATE_CLK(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x52008, BIT(18)), + GATE_CLK(GCC_QUPV3_WRAP1_CORE_CLK, 0x52008, BIT(19)), + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x52008, BIT(22)), + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)), + GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x52008, BIT(24)), + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x52008, BIT(25)), + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x52008, BIT(26)), + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x52008, BIT(27)), + GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x52008, BIT(28)), + GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x52010, BIT(16)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), + GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)), + GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)), + GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)), + GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x52008, BIT(20)), + GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x52008, BIT(21)), + GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)), + GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14010, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77024, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_HW_CTL_CLK, 0x77018, BIT(1)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77074, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK, 0x77074, BIT(1)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x770b0, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK, 0x770b0, BIT(1)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7702c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770cc, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77028, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77068, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK, 0x77068, BIT(1)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), +}; + +static int sm8650_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sm8650_gcc_resets[] = { + [GCC_CAMERA_BCR] = { 0x26000 }, + [GCC_DISPLAY_BCR] = { 0x27000 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, + [GCC_QUPV3_WRAPPER_3_BCR] = { 0x19000 }, + [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0x39000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, + [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, + [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, + [GCC_VIDEO_BCR] = { 0x32000 }, +}; + +static const struct qcom_power_map sm8650_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_0_PHY_GDSC] = { 0x6c000 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [PCIE_1_PHY_GDSC] = { 0x8e000 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [UFS_MEM_PHY_GDSC] = { 0x9e000 }, + [USB30_PRIM_GDSC] = { 0x39004 }, + [USB3_PHY_GDSC] = { 0x50018 }, +}; + +static struct msm_clk_data sm8650_gcc_data = { + .resets = sm8650_gcc_resets, + .num_resets = ARRAY_SIZE(sm8650_gcc_resets), + .clks = sm8650_clks, + .num_clks = ARRAY_SIZE(sm8650_clks), + .power_domains = sm8650_gdscs, + .num_power_domains = ARRAY_SIZE(sm8650_gdscs), + + .enable = sm8650_enable, + .set_rate = sm8650_set_rate, +}; + +static const struct udevice_id gcc_sm8650_of_match[] = { + { + .compatible = "qcom,sm8650-gcc", + .data = (ulong)&sm8650_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sm8650) = { + .name = "gcc_sm8650", + .id = UCLASS_NOP, + .of_match = gcc_sm8650_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + +/* TCSRCC */ + +static const struct gate_clk sm8650_tcsr_clks[] = { + GATE_CLK(TCSR_PCIE_0_CLKREF_EN, 0x31100, BIT(0)), + GATE_CLK(TCSR_PCIE_1_CLKREF_EN, 0x31114, BIT(0)), + GATE_CLK(TCSR_UFS_CLKREF_EN, 0x31110, BIT(0)), + GATE_CLK(TCSR_UFS_PAD_CLKREF_EN, 0x31104, BIT(0)), + GATE_CLK(TCSR_USB2_CLKREF_EN, 0x31118, BIT(0)), + GATE_CLK(TCSR_USB3_CLKREF_EN, 0x31108, BIT(0)), +}; + +static struct msm_clk_data sm8650_tcsrcc_data = { + .clks = sm8650_tcsr_clks, + .num_clks = ARRAY_SIZE(sm8650_tcsr_clks), +}; + +static int tcsrcc_sm8650_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static ulong tcsrcc_sm8650_clk_get_rate(struct clk *clk) +{ + return TCXO_RATE; +} + +static int tcsrcc_sm8650_clk_probe(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->data = data; + + return 0; +} + +static struct clk_ops tcsrcc_sm8650_clk_ops = { + .enable = tcsrcc_sm8650_clk_enable, + .get_rate = tcsrcc_sm8650_clk_get_rate, +}; + +static const struct udevice_id tcsrcc_sm8650_of_match[] = { + { + .compatible = "qcom,sm8650-tcsr", + .data = (ulong)&sm8650_tcsrcc_data, + }, + { } +}; + +U_BOOT_DRIVER(tcsrcc_sm8650) = { + .name = "tcsrcc_sm8650", + .id = UCLASS_CLK, + .of_match = tcsrcc_sm8650_of_match, + .ops = &tcsrcc_sm8650_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = tcsrcc_sm8650_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index dba009997a8..c8735d869cf 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -313,9 +313,9 @@ static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_ /* * As per the HW manual, we should not directly switch from 533 MHz to - * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) - * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, - * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 + * 400 MHz and vice versa. To change the setting from 2'b01 (533 MHz) + * to 2'b10 (400 MHz) or vice versa, Switch to 2'b11 (266 MHz) first, + * and then switch to the target setting (2'b01 (533 MHz) or 2'b10 * (400 MHz)). */ if (new_sel != SEL_SDHI_266MHz && prev_sel != SEL_SDHI_266MHz) { diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 7755b016111..861648321d4 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -12,8 +12,8 @@ #include <malloc.h> #include <syscon.h> #include <asm/global_data.h> -#include <asm/arch/cru_rk3308.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3308.h> #include <asm/arch-rockchip/hardware.h> #include <dm/device-internal.h> #include <dm/lists.h> @@ -65,6 +65,57 @@ static struct rockchip_pll_clock rk3308_pll_clks[] = { RK3308_MODE_CON, 6, 10, 0, NULL), }; +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz) { struct rk3308_cru *cru = priv->cru; @@ -832,6 +883,44 @@ static ulong rk3308_crypto_set_clk(struct rk3308_clk_priv *priv, ulong clk_id, return rk3308_crypto_get_clk(priv, clk_id); } +static ulong rk3308_rtc32k_get_clk(struct rk3308_clk_priv *priv, ulong clk_id) +{ + struct rk3308_cru *cru = priv->cru; + unsigned long m, n; + u32 con, fracdiv; + + con = readl(&cru->clksel_con[2]); + if ((con & CLK_RTC32K_SEL_MASK) >> CLK_RTC32K_SEL_SHIFT != + CLK_RTC32K_FRAC_DIV) + return -EINVAL; + + fracdiv = readl(&cru->clksel_con[3]); + m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK; + m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT; + n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK; + n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT; + + return OSC_HZ * m / n; +} + +static ulong rk3308_rtc32k_set_clk(struct rk3308_clk_priv *priv, ulong clk_id, + ulong hz) +{ + struct rk3308_cru *cru = priv->cru; + unsigned long m, n, val; + + rational_best_approximation(hz, OSC_HZ, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n; + writel(val, &cru->clksel_con[3]); + rk_clrsetreg(&cru->clksel_con[2], CLK_RTC32K_SEL_MASK, + CLK_RTC32K_FRAC_DIV << CLK_RTC32K_SEL_SHIFT); + + return rk3308_rtc32k_get_clk(priv, clk_id); +} + static ulong rk3308_clk_get_rate(struct clk *clk) { struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); @@ -912,6 +1001,9 @@ static ulong rk3308_clk_get_rate(struct clk *clk) case SCLK_CRYPTO_APK: rate = rk3308_crypto_get_clk(priv, clk->id); break; + case SCLK_RTC32K: + rate = rk3308_rtc32k_get_clk(priv, clk->id); + break; default: return -ENOENT; } @@ -990,6 +1082,11 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) case SCLK_CRYPTO_APK: ret = rk3308_crypto_set_clk(priv, clk->id, rate); break; + case SCLK_RTC32K: + ret = rk3308_rtc32k_set_clk(priv, clk->id, rate); + break; + case USB480M: + return 0; default: return -ENOENT; } @@ -1022,6 +1119,8 @@ static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *par switch (clk->id) { case SCLK_MAC: return rk3308_mac_set_parent(clk, parent); + case USB480M: + return 0; default: break; } diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index cfec1d974ac..87075ec7134 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -178,6 +178,10 @@ enum { CLK_I2C3_DIV_CON_SHIFT = 8, CLK_I2C2_PLL_SEL_SHIFT = 7, CLK_I2C2_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON40 */ + CLK_HDMIPHY_DIV_CON_SHIFT = 3, + CLK_HDMIPHY_DIV_CON_MASK = 0x7 << CLK_HDMIPHY_DIV_CON_SHIFT, }; #define VCO_MAX_KHZ (3200 * (MHz / KHz)) @@ -580,6 +584,96 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) return rk3328_spi_get_clk(cru); } +#ifndef CONFIG_SPL_BUILD +static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id) +{ + struct rk3328_cru *cru = priv->cru; + u32 div, con, parent; + + switch (clk_id) { + case ACLK_VOP_PRE: + con = readl(&cru->clksel_con[39]); + div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT; + parent = GPLL_HZ; + break; + case ACLK_VIO_PRE: + con = readl(&cru->clksel_con[37]); + div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT; + parent = GPLL_HZ; + break; + case DCLK_LCDC: + con = readl(&cru->clksel_con[40]); + div = (con & DCLK_LCDC_DIV_CON_MASK) >> DCLK_LCDC_DIV_CON_SHIFT; + parent = GPLL_HZ; + break; + default: + printf("%s: Unsupported vop get clk#%ld\n", __func__, clk_id); + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3328_vop_set_clk(struct rk3328_clk_priv *priv, + ulong clk_id, uint hz) +{ + struct rk3328_cru *cru = priv->cru; + int src_clk_div; + u32 con, parent; + + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); + assert(src_clk_div - 1 < 31); + + switch (clk_id) { + case ACLK_VOP_PRE: + rk_clrsetreg(&cru->clksel_con[39], + ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, + ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | + (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); + break; + case ACLK_VIO_PRE: + rk_clrsetreg(&cru->clksel_con[37], + ACLK_VIO_PLL_SEL_MASK | ACLK_VIO_DIV_CON_MASK, + ACLK_VIO_PLL_SEL_CPLL << ACLK_VIO_PLL_SEL_SHIFT | + (src_clk_div - 1) << ACLK_VIO_DIV_CON_SHIFT); + break; + case DCLK_LCDC: + con = readl(&cru->clksel_con[40]); + con = (con & DCLK_LCDC_SEL_MASK) >> DCLK_LCDC_SEL_SHIFT; + if (con) { + parent = readl(&cru->clksel_con[40]); + parent = (parent & DCLK_LCDC_PLL_SEL_MASK) >> + DCLK_LCDC_PLL_SEL_SHIFT; + if (parent) + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); + else + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); + + rk_clrsetreg(&cru->clksel_con[40], + DCLK_LCDC_DIV_CON_MASK, + (src_clk_div - 1) << + DCLK_LCDC_DIV_CON_SHIFT); + } + break; + default: + printf("%s: Unable to set vop clk#%ld\n", __func__, clk_id); + return -EINVAL; + } + + return rk3328_vop_get_clk(priv, clk_id); +} +#endif + +static ulong rk3328_hdmiphy_get_clk(struct rk3328_cru *cru) +{ + u32 div, con; + + con = readl(&cru->clksel_con[40]); + div = (con & CLK_HDMIPHY_DIV_CON_MASK) >> CLK_HDMIPHY_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -609,6 +703,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case SCLK_SPI: rate = rk3328_spi_get_clk(priv->cru); break; + case PCLK_HDMIPHY: + rate = rk3328_hdmiphy_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -648,7 +745,13 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI: ret = rk3328_spi_set_clk(priv->cru, rate); break; +#ifndef CONFIG_SPL_BUILD case DCLK_LCDC: + case ACLK_VOP_PRE: + case ACLK_VIO_PRE: + rate = rk3328_vop_set_clk(priv, clk->id, rate); + break; +#endif case SCLK_PDM: case SCLK_RTC32K: case SCLK_UART0: @@ -663,11 +766,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case ACLK_PERI_PRE: case HCLK_PERI: case PCLK_PERI: - case ACLK_VIO_PRE: case HCLK_VIO_PRE: case ACLK_RGA_PRE: case SCLK_RGA: - case ACLK_VOP_PRE: case ACLK_RKVDEC_PRE: case ACLK_RKVENC: case ACLK_VPU_PRE: diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 57ef27dda89..24eeca8bf26 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1527,28 +1527,20 @@ static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) struct rk3568_cru *cru = priv->cru; int src_clk; - switch (rate) { - case OSC_HZ: - src_clk = SCLK_SFC_SEL_24M; - break; - case 50 * MHz: - src_clk = SCLK_SFC_SEL_50M; - break; - case 75 * MHz: - src_clk = SCLK_SFC_SEL_75M; - break; - case 100 * MHz: - src_clk = SCLK_SFC_SEL_100M; - break; - case 125 * MHz: - src_clk = SCLK_SFC_SEL_125M; - break; - case 150 * MHz: + if (rate >= 150 * MHz) src_clk = SCLK_SFC_SEL_150M; - break; - default: + else if (rate >= 125 * MHz) + src_clk = SCLK_SFC_SEL_125M; + else if (rate >= 100 * MHz) + src_clk = SCLK_SFC_SEL_100M; + else if (rate >= 75 * MHz) + src_clk = SCLK_SFC_SEL_75M; + else if (rate >= 50 * MHz) + src_clk = SCLK_SFC_SEL_50M; + else if (rate >= OSC_HZ) + src_clk = SCLK_SFC_SEL_24M; + else return -ENOENT; - } rk_clrsetreg(&cru->clksel_con[28], SCLK_SFC_SEL_MASK, @@ -2417,6 +2409,8 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case BCLK_EMMC: rate = rk3568_emmc_get_bclk(priv); break; + case CLK_USB3OTG0_REF: + case CLK_USB3OTG1_REF: case TCLK_EMMC: rate = OSC_HZ; break; @@ -2596,6 +2590,8 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case BCLK_EMMC: ret = rk3568_emmc_set_bclk(priv, rate); break; + case CLK_USB3OTG0_REF: + case CLK_USB3OTG1_REF: case TCLK_EMMC: ret = OSC_HZ; break; diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 8f33843179b..4c611a39049 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1569,6 +1569,9 @@ static ulong rk3588_clk_get_rate(struct clk *clk) case DCLK_DECOM: rate = rk3588_mmc_get_clk(priv, clk->id); break; + case REF_CLK_USB3OTG0: + case REF_CLK_USB3OTG1: + case REF_CLK_USB3OTG2: case TMCLK_EMMC: case TCLK_WDT0: rate = OSC_HZ; @@ -1734,6 +1737,9 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) case DCLK_DECOM: ret = rk3588_mmc_set_clk(priv, clk->id, rate); break; + case REF_CLK_USB3OTG0: + case REF_CLK_USB3OTG1: + case REF_CLK_USB3OTG2: case TMCLK_EMMC: case TCLK_WDT0: ret = OSC_HZ; diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h index 53c2b467ab8..f9ef0702005 100644 --- a/drivers/clk/stm32/clk-stm32-core.h +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -178,7 +178,7 @@ int stm32_rcc_init(struct udevice *dev, * ------------------------------ ---------- * Each peripheral requires a bus interface clock, named ckg_bus_perx - * (for peripheral ‘x’). + * (for peripheral `x'). * Some peripherals (SAI, UART...) need also a dedicated clock for their * communication interface, this clock is generally asynchronous with respect to * the bus interface clock, and is named kernel clock (ckg_ker_perx). @@ -188,16 +188,16 @@ int stm32_rcc_init(struct udevice *dev, * the bus or the Kernel was enable. * * Example: - * 1) enable the bus clock - * --> bus_clk ref_counting = 1, gate_ref_count = 1 - * 2) enable the kernel clock - * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2 - * 3) disable kernel clock - * ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1 - * ==> then i will not gate because gate_ref_count > 0 - * 4) disable bus clock - * --> bus_clk ref_counting = 0, gate_ref_count = 0 - * ==> then i can gate (write in the register) because + * 1) enable the bus clock + * --> bus_clk ref_counting = 1, gate_ref_count = 1 + * 2) enable the kernel clock + * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2 + * 3) disable kernel clock + * ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1 + * ==> then i will not gate because gate_ref_count > 0 + * 4) disable bus clock + * --> bus_clk ref_counting = 0, gate_ref_count = 0 + * ==> then i can gate (write in the register) because * gate_ref_count = 0 */ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 12ef84ca05c..8b49997030b 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -1,11 +1,11 @@ menu "Hardware crypto devices" -source drivers/crypto/hash/Kconfig +source "drivers/crypto/hash/Kconfig" -source drivers/crypto/fsl/Kconfig +source "drivers/crypto/fsl/Kconfig" -source drivers/crypto/aspeed/Kconfig +source "drivers/crypto/aspeed/Kconfig" -source drivers/crypto/nuvoton/Kconfig +source "drivers/crypto/nuvoton/Kconfig" endmenu diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index 5448c33838c..005f581f4ba 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -5,7 +5,7 @@ config IMX8ULP_DRAM bool "imx8m dram" config IMX8ULP_DRAM_PHY_PLL_BYPASS - bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK " + bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK" depends on IMX8ULP_DRAM config SAVED_DRAM_TIMING_BASE diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 14a8210522b..0dd3434e9e0 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -35,6 +35,8 @@ #define REG_SUBTYPE_GPIOC_8CH 0xd #define REG_SUBTYPE_GPIO_LV 0x10 #define REG_SUBTYPE_GPIO_MV 0x11 +#define REG_SUBTYPE_GPIO_LV_VIN2 0x12 +#define REG_SUBTYPE_GPIO_MV_VIN3 0x13 #define REG_STATUS 0x08 #define REG_STATUS_VAL_MASK 0x1 @@ -322,9 +324,20 @@ static int qcom_gpio_probe(struct udevice *dev) return log_msg_ret("bad type", -ENXIO); val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE); - if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH && - val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV) + switch (val) { + case REG_SUBTYPE_GPIO_4CH: + case REG_SUBTYPE_GPIOC_4CH: + plat->lv_mv_type = false; + break; + case REG_SUBTYPE_GPIO_LV: + case REG_SUBTYPE_GPIO_MV: + case REG_SUBTYPE_GPIO_LV_VIN2: + case REG_SUBTYPE_GPIO_MV_VIN3: + plat->lv_mv_type = true; + break; + default: return log_msg_ret("bad subtype", -ENXIO); + } plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV || val == REG_SUBTYPE_GPIO_MV; @@ -351,6 +364,9 @@ static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, { .compatible = "qcom,pms405-gpio" }, + { .compatible = "qcom,pm6125-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm8150-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, { } }; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 59c635af80b..34b02114dc6 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -638,6 +638,16 @@ config SYS_I2C_QUP Technical Reference Manual, chapter "6.1 Qualcomm Universal Peripherals Engine (QUP)". +config SYS_I2C_GENI + bool "Qualcomm Generic Interface (GENI) I2C controller" + depends on ARCH_SNAPDRAGON + help + Support for the Qualcomm Generic Interface (GENI) I2C interface. + The Generic Interface (GENI) is a firmware based Qualcomm Universal + Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple + bus protocols depending on the firmware type loaded at early boot time + based on system configuration. + config SYS_I2C_S3C24X0 bool "Samsung I2C driver" depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 692f63bafd0..00b90523c62 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o +obj-$(CONFIG_SYS_I2C_GENI) += geni_i2c.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o diff --git a/drivers/i2c/geni_i2c.c b/drivers/i2c/geni_i2c.c new file mode 100644 index 00000000000..eabf5c76c21 --- /dev/null +++ b/drivers/i2c/geni_i2c.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Author: Neil Armstrong <neil.armstrong@linaro.org> + * + * Based on Linux driver: drivers/i2c/busses/i2c-qcom-geni.c + */ + +#include <log.h> +#include <dm/device.h> +#include <dm/read.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <i2c.h> +#include <fdtdec.h> +#include <clk.h> +#include <reset.h> +#include <time.h> +#include <soc/qcom/geni-se.h> + +#define SE_I2C_TX_TRANS_LEN 0x26c +#define SE_I2C_RX_TRANS_LEN 0x270 +#define SE_I2C_SCL_COUNTERS 0x278 + +#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ + M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) +#define SE_I2C_ABORT BIT(1) + +/* M_CMD OP codes for I2C */ +#define I2C_WRITE 0x1 +#define I2C_READ 0x2 +#define I2C_WRITE_READ 0x3 +#define I2C_ADDR_ONLY 0x4 +#define I2C_BUS_CLEAR 0x6 +#define I2C_STOP_ON_BUS 0x7 +/* M_CMD params for I2C */ +#define PRE_CMD_DELAY BIT(0) +#define TIMESTAMP_BEFORE BIT(1) +#define STOP_STRETCH BIT(2) +#define TIMESTAMP_AFTER BIT(3) +#define POST_COMMAND_DELAY BIT(4) +#define IGNORE_ADD_NACK BIT(6) +#define READ_FINISHED_WITH_ACK BIT(7) +#define BYPASS_ADDR_PHASE BIT(8) +#define SLV_ADDR_MSK GENMASK(15, 9) +#define SLV_ADDR_SHFT 9 +/* I2C SCL COUNTER fields */ +#define HIGH_COUNTER_MSK GENMASK(29, 20) +#define HIGH_COUNTER_SHFT 20 +#define LOW_COUNTER_MSK GENMASK(19, 10) +#define LOW_COUNTER_SHFT 10 +#define CYCLE_COUNTER_MSK GENMASK(9, 0) + +#define I2C_PACK_TX BIT(0) +#define I2C_PACK_RX BIT(1) + +#define PACKING_BYTES_PW 4 + +#define GENI_I2C_IS_MASTER_HUB BIT(0) + +#define I2C_TIMEOUT_MS 100 + +struct geni_i2c_clk_fld { + u32 clk_freq_out; + u8 clk_div; + u8 t_high_cnt; + u8 t_low_cnt; + u8 t_cycle_cnt; +}; + +struct geni_i2c_priv { + fdt_addr_t wrapper; + phys_addr_t base; + struct clk core; + struct clk se; + u32 tx_wm; + bool is_master_hub; + const struct geni_i2c_clk_fld *clk_fld; +}; + +/* + * Hardware uses the underlying formula to calculate time periods of + * SCL clock cycle. Firmware uses some additional cycles excluded from the + * below formula and it is confirmed that the time periods are within + * specification limits. + * + * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock + * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock + * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock + * clk_freq_out = t / t_cycle + * source_clock = 19.2 MHz + */ +static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { + {I2C_SPEED_STANDARD_RATE, 7, 10, 11, 26}, + {I2C_SPEED_FAST_RATE, 2, 5, 12, 24}, + {I2C_SPEED_FAST_PLUS_RATE, 1, 3, 9, 18}, +}; + +static int geni_i2c_clk_map_idx(struct geni_i2c_priv *geni, unsigned int clk_freq) +{ + const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; + int i; + + for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { + if (itr->clk_freq_out == clk_freq) { + geni->clk_fld = itr; + return 0; + } + } + + return -EINVAL; +} + +static void geni_i2c_setup_m_cmd(struct geni_i2c_priv *geni, u32 cmd, u32 params) +{ + u32 m_cmd; + + m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); + writel(m_cmd, geni->base + SE_GENI_M_CMD0); +} + +static void qcom_geni_i2c_conf(struct geni_i2c_priv *geni) +{ + const struct geni_i2c_clk_fld *itr = geni->clk_fld; + u32 val; + + writel(0, geni->base + SE_GENI_CLK_SEL); + + val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; + writel(val, geni->base + GENI_SER_M_CLK_CFG); + + val = itr->t_high_cnt << HIGH_COUNTER_SHFT; + val |= itr->t_low_cnt << LOW_COUNTER_SHFT; + val |= itr->t_cycle_cnt; + writel(val, geni->base + SE_I2C_SCL_COUNTERS); + + writel(0xffffffff, geni->base + SE_GENI_M_IRQ_CLEAR); +} + +static int geni_i2c_fifo_tx_fill(struct geni_i2c_priv *geni, struct i2c_msg *msg) +{ + ulong start = get_timer(0); + ulong cur_xfer = 0; + int i; + + while (get_timer(start) < I2C_TIMEOUT_MS) { + u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS); + + if (status & (M_CMD_ABORT_EN | + M_CMD_OVERRUN_EN | + M_ILLEGAL_CMD_EN | + M_CMD_FAILURE_EN | + M_GP_IRQ_1_EN | + M_GP_IRQ_3_EN | + M_GP_IRQ_4_EN)) { + writel(status, geni->base + SE_GENI_M_IRQ_CLEAR); + writel(0, geni->base + SE_GENI_TX_WATERMARK_REG); + return -EREMOTEIO; + } + + if ((status & M_TX_FIFO_WATERMARK_EN) == 0) { + udelay(1); + goto skip_fill; + } + + for (i = 0; i < geni->tx_wm; i++) { + u32 temp, tx = 0; + unsigned int p = 0; + + while (cur_xfer < msg->len && p < sizeof(tx)) { + temp = msg->buf[cur_xfer++]; + tx |= temp << (p * 8); + p++; + } + + writel(tx, geni->base + SE_GENI_TX_FIFOn); + + if (cur_xfer == msg->len) { + writel(0, geni->base + SE_GENI_TX_WATERMARK_REG); + break; + } + } + +skip_fill: + writel(status, geni->base + SE_GENI_M_IRQ_CLEAR); + + if (status & M_CMD_DONE_EN) + return 0; + } + + return -ETIMEDOUT; +} + +static int geni_i2c_fifo_rx_drain(struct geni_i2c_priv *geni, struct i2c_msg *msg) +{ + ulong start = get_timer(0); + ulong cur_xfer = 0; + int i; + + while (get_timer(start) < I2C_TIMEOUT_MS) { + u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS); + u32 rxstatus = readl(geni->base + SE_GENI_RX_FIFO_STATUS); + u32 rxcnt = rxstatus & RX_FIFO_WC_MSK; + + if (status & (M_CMD_ABORT_EN | + M_CMD_FAILURE_EN | + M_CMD_OVERRUN_EN | + M_ILLEGAL_CMD_EN | + M_GP_IRQ_1_EN | + M_GP_IRQ_3_EN | + M_GP_IRQ_4_EN)) { + writel(status, geni->base + SE_GENI_M_IRQ_CLEAR); + return -EREMOTEIO; + } + + if ((status & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) == 0) { + udelay(1); + goto skip_drain; + } + + for (i = 0; cur_xfer < msg->len && i < rxcnt; i++) { + u32 rx = readl(geni->base + SE_GENI_RX_FIFOn); + unsigned int p = 0; + + while (cur_xfer < msg->len && p < sizeof(rx)) { + msg->buf[cur_xfer++] = rx & 0xff; + rx >>= 8; + p++; + } + } + +skip_drain: + writel(status, geni->base + SE_GENI_M_IRQ_CLEAR); + + if (status & M_CMD_DONE_EN) + return 0; + } + + return -ETIMEDOUT; +} + +static int geni_i2c_xfer_tx(struct geni_i2c_priv *geni, struct i2c_msg *msg, u32 params) +{ + writel(msg->len, geni->base + SE_I2C_TX_TRANS_LEN); + geni_i2c_setup_m_cmd(geni, I2C_WRITE, params); + writel(1, geni->base + SE_GENI_TX_WATERMARK_REG); + + return geni_i2c_fifo_tx_fill(geni, msg); +} + +static int geni_i2c_xfer_rx(struct geni_i2c_priv *geni, struct i2c_msg *msg, u32 params) +{ + writel(msg->len, geni->base + SE_I2C_RX_TRANS_LEN); + geni_i2c_setup_m_cmd(geni, I2C_READ, params); + + return geni_i2c_fifo_rx_drain(geni, msg); +} + +static int geni_i2c_xfer(struct udevice *bus, struct i2c_msg msgs[], int num) +{ + struct geni_i2c_priv *geni = dev_get_priv(bus); + int i, ret = 0; + + qcom_geni_i2c_conf(geni); + + for (i = 0; i < num; i++) { + struct i2c_msg *msg = &msgs[i]; + u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; + + m_param |= ((msg->addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); + + if (msg->flags & I2C_M_RD) + ret = geni_i2c_xfer_rx(geni, msg, m_param); + else + ret = geni_i2c_xfer_tx(geni, msg, m_param); + + if (ret) + break; + } + + if (ret) { + if (ret == -ETIMEDOUT) { + u32 status; + + writel(M_GENI_CMD_ABORT, geni->base + SE_GENI_M_CMD_CTRL_REG); + + /* Wait until Abort has finished */ + do { + status = readl(geni->base + SE_GENI_M_IRQ_STATUS); + } while ((status & M_CMD_ABORT_EN) == 0); + + writel(status, geni->base + SE_GENI_M_IRQ_STATUS); + } + + return ret; + } + + return 0; +} + +static int geni_i2c_enable_clocks(struct udevice *dev, struct geni_i2c_priv *geni) +{ + int ret; + + if (geni->is_master_hub) { + ret = clk_enable(&geni->core); + if (ret) { + dev_err(dev, "clk_enable core failed %d\n", ret); + return ret; + } + } + + ret = clk_enable(&geni->se); + if (ret) { + dev_err(dev, "clk_enable se failed %d\n", ret); + return ret; + } + + return 0; +} + +static int geni_i2c_disable_clocks(struct udevice *dev, struct geni_i2c_priv *geni) +{ + int ret; + + if (geni->is_master_hub) { + ret = clk_disable(&geni->core); + if (ret) { + dev_err(dev, "clk_enable core failed %d\n", ret); + return ret; + } + } + + ret = clk_disable(&geni->se); + if (ret) { + dev_err(dev, "clk_enable se failed %d\n", ret); + return ret; + } + + return 0; +} + +#define NUM_PACKING_VECTORS 4 +#define PACKING_START_SHIFT 5 +#define PACKING_DIR_SHIFT 4 +#define PACKING_LEN_SHIFT 1 +#define PACKING_STOP_BIT BIT(0) +#define PACKING_VECTOR_SHIFT 10 +static void geni_i2c_config_packing(struct geni_i2c_priv *geni, int bpw, + int pack_words, bool msb_to_lsb, + bool tx_cfg, bool rx_cfg) +{ + u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; + int len; + int temp_bpw = bpw; + int idx_start = msb_to_lsb ? bpw - 1 : 0; + int idx = idx_start; + int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; + int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); + int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; + int i; + + if (iter <= 0 || iter > NUM_PACKING_VECTORS) + return; + + for (i = 0; i < iter; i++) { + len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; + cfg[i] = idx << PACKING_START_SHIFT; + cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; + cfg[i] |= len << PACKING_LEN_SHIFT; + + if (temp_bpw <= BITS_PER_BYTE) { + idx = ((i + 1) * BITS_PER_BYTE) + idx_start; + temp_bpw = bpw; + } else { + idx = idx + idx_delta; + temp_bpw = temp_bpw - BITS_PER_BYTE; + } + } + cfg[iter - 1] |= PACKING_STOP_BIT; + cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); + cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); + + if (tx_cfg) { + writel(cfg0, geni->base + SE_GENI_TX_PACKING_CFG0); + writel(cfg1, geni->base + SE_GENI_TX_PACKING_CFG1); + } + if (rx_cfg) { + writel(cfg0, geni->base + SE_GENI_RX_PACKING_CFG0); + writel(cfg1, geni->base + SE_GENI_RX_PACKING_CFG1); + } + + /* + * Number of protocol words in each FIFO entry + * 0 - 4x8, four words in each entry, max word size of 8 bits + * 1 - 2x16, two words in each entry, max word size of 16 bits + * 2 - 1x32, one word in each entry, max word size of 32 bits + * 3 - undefined + */ + if (pack_words || bpw == 32) + writel(bpw / 16, geni->base + SE_GENI_BYTE_GRAN); +} + +static void geni_i2c_init(struct geni_i2c_priv *geni, unsigned int tx_depth) +{ + u32 val; + + writel(0, geni->base + SE_GSI_EVENT_EN); + writel(0xffffffff, geni->base + SE_GENI_M_IRQ_CLEAR); + writel(0xffffffff, geni->base + SE_GENI_S_IRQ_CLEAR); + writel(0xffffffff, geni->base + SE_IRQ_EN); + + val = readl(geni->base + GENI_CGC_CTRL); + val |= DEFAULT_CGC_EN; + writel(val, geni->base + GENI_CGC_CTRL); + + writel(DEFAULT_IO_OUTPUT_CTRL_MSK, geni->base + GENI_OUTPUT_CTRL); + writel(FORCE_DEFAULT, geni->base + GENI_FORCE_DEFAULT_REG); + + val = readl(geni->base + SE_IRQ_EN); + val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; + writel(val, geni->base + SE_IRQ_EN); + + val = readl(geni->base + SE_GENI_DMA_MODE_EN); + val &= ~GENI_DMA_MODE_EN; + writel(val, geni->base + SE_GENI_DMA_MODE_EN); + + writel(0, geni->base + SE_GSI_EVENT_EN); + + writel(tx_depth - 1, geni->base + SE_GENI_RX_WATERMARK_REG); + writel(tx_depth, geni->base + SE_GENI_RX_RFR_WATERMARK_REG); + + val = readl(geni->base + SE_GENI_M_IRQ_EN); + val |= M_COMMON_GENI_M_IRQ_EN; + val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; + val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; + writel(val, geni->base + SE_GENI_M_IRQ_EN); + + val = readl(geni->base + SE_GENI_S_IRQ_EN); + val |= S_COMMON_GENI_S_IRQ_EN; + writel(val, geni->base + SE_GENI_S_IRQ_EN); +} + +static u32 geni_i2c_get_tx_fifo_depth(struct geni_i2c_priv *geni) +{ + u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; + + hw_version = readl(geni->wrapper + QUP_HW_VER_REG); + hw_major = GENI_SE_VERSION_MAJOR(hw_version); + hw_minor = GENI_SE_VERSION_MINOR(hw_version); + + if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) + tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; + else + tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; + + val = readl(geni->base + SE_HW_PARAM_0); + + return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; +} + +static int geni_i2c_probe(struct udevice *dev) +{ + ofnode parent_node = ofnode_get_parent(dev_ofnode(dev)); + struct geni_i2c_priv *geni = dev_get_priv(dev); + u32 proto, tx_depth, fifo_disable; + int ret; + + geni->is_master_hub = dev_get_driver_data(dev) & GENI_I2C_IS_MASTER_HUB; + + geni->wrapper = ofnode_get_addr(parent_node); + if (geni->wrapper == FDT_ADDR_T_NONE) + return -EINVAL; + + geni->base = (phys_addr_t)dev_read_addr_ptr(dev); + if (!geni->base) + return -EINVAL; + + if (geni->is_master_hub) { + ret = clk_get_by_name(dev, "core", &geni->core); + if (ret) { + dev_err(dev, "clk_get_by_name(core) failed: %d\n", ret); + return ret; + } + } + + ret = clk_get_by_name(dev, "se", &geni->se); + if (ret) { + dev_err(dev, "clk_get_by_name(se) failed: %d\n", ret); + return ret; + } + + geni_i2c_enable_clocks(dev, geni); + + proto = readl(geni->base + GENI_FW_REVISION_RO); + proto &= FW_REV_PROTOCOL_MSK; + proto >>= FW_REV_PROTOCOL_SHFT; + + if (proto != GENI_SE_I2C) { + dev_err(dev, "Invalid proto %d\n", proto); + geni_i2c_disable_clocks(dev, geni); + return -ENXIO; + } + + fifo_disable = readl(geni->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; + if (fifo_disable) { + geni_i2c_disable_clocks(dev, geni); + dev_err(dev, "FIFO mode disabled, DMA mode unsupported\n"); + return -ENXIO; + } + + if (!geni->is_master_hub) { + tx_depth = geni_i2c_get_tx_fifo_depth(geni); + if (!tx_depth) { + geni_i2c_disable_clocks(dev, geni); + dev_err(dev, "Invalid TX FIFO depth\n"); + return -ENXIO; + } + } else { + tx_depth = 16; + } + geni->tx_wm = tx_depth - 1; + + geni_i2c_init(geni, tx_depth); + geni_i2c_config_packing(geni, BITS_PER_BYTE, + PACKING_BYTES_PW, true, true, true); + + /* Setup for standard rate */ + return geni_i2c_clk_map_idx(geni, I2C_SPEED_STANDARD_RATE); +} + +static int geni_i2c_set_bus_speed(struct udevice *dev, unsigned int clk_freq) +{ + struct geni_i2c_priv *geni = dev_get_priv(dev); + + return geni_i2c_clk_map_idx(geni, clk_freq); +} + +static const struct dm_i2c_ops geni_i2c_ops = { + .xfer = geni_i2c_xfer, + .set_bus_speed = geni_i2c_set_bus_speed, +}; + +static const struct udevice_id geni_i2c_ids[] = { + { .compatible = "qcom,geni-i2c" }, + { .compatible = "qcom,geni-i2c-master-hub", .data = GENI_I2C_IS_MASTER_HUB}, + {} +}; + +U_BOOT_DRIVER(i2c_geni) = { + .name = "i2c_geni", + .id = UCLASS_I2C, + .of_match = geni_i2c_ids, + .probe = geni_i2c_probe, + .priv_auto = sizeof(struct geni_i2c_priv), + .ops = &geni_i2c_ops, +}; + +static const struct udevice_id geni_i2c_master_hub_ids[] = { + { .compatible = "qcom,geni-se-i2c-master-hub" }, + { } +}; + +U_BOOT_DRIVER(geni_i2c_master_hub) = { + .name = "geni-se-master-hub", + .id = UCLASS_NOP, + .of_match = geni_i2c_master_hub_ids, + .bind = dm_scan_fdt_dev, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c index f2b39de56f4..7b646d840dd 100644 --- a/drivers/iommu/qcom-hyp-smmu.c +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -381,6 +381,7 @@ static struct iommu_ops qcom_smmu_ops = { static const struct udevice_id qcom_smmu500_ids[] = { { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,smmu-500", }, { /* sentinel */ } }; diff --git a/drivers/led/led_lp5562.c b/drivers/led/led_lp5562.c index 431d7e10ab7..0c5f9bc4300 100644 --- a/drivers/led/led_lp5562.c +++ b/drivers/led/led_lp5562.c @@ -125,9 +125,9 @@ static int lp5562_led_reg_update(struct udevice *dev, int regnum, /* * Data sheet says "Delay between consecutive I2C writes to - * ENABLE register (00h) need to be longer than 488 μs + * ENABLE register (00h) need to be longer than 488 us * (typical)." and "Delay between consecutive I2C writes to - * OP_MODE register need to be longer than 153 μs (typ)." + * OP_MODE register need to be longer than 153 us (typ)." * * The linux driver does usleep_range(500, 600) and * usleep_range(200, 300), respectively. diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index a722a3836f7..1ce96077858 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -22,8 +22,15 @@ #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) #define FMC2_PCSCNTR 0x20 +#define FMC2_CFGR 0x20 +#define FMC2_SR 0x84 #define FMC2_BWTR1 0x104 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) +#define FMC2_SECCFGR 0x300 +#define FMC2_CIDCFGR0 0x30c +#define FMC2_CIDCFGR(x) ((x) * 0x8 + FMC2_CIDCFGR0) +#define FMC2_SEMCR0 0x310 +#define FMC2_SEMCR(x) ((x) * 0x8 + FMC2_SEMCR0) /* Register: FMC2_BCR1 */ #define FMC2_BCR1_CCLKEN BIT(20) @@ -44,6 +51,7 @@ #define FMC2_BCR_ASYNCWAIT BIT(15) #define FMC2_BCR_CPSIZE GENMASK(18, 16) #define FMC2_BCR_CBURSTRW BIT(19) +#define FMC2_BCR_CSCOUNT GENMASK(21, 20) #define FMC2_BCR_NBLSET GENMASK(23, 22) /* Register: FMC2_BTRx/FMC2_BWTRx */ @@ -60,8 +68,28 @@ #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) +/* Register: FMC2_CFGR */ +#define FMC2_CFGR_CLKDIV GENMASK(19, 16) +#define FMC2_CFGR_CCLKEN BIT(20) +#define FMC2_CFGR_FMC2EN BIT(31) + +/* Register: FMC2_SR */ +#define FMC2_SR_ISOST GENMASK(1, 0) + +/* Register: FMC2_CIDCFGR */ +#define FMC2_CIDCFGR_CFEN BIT(0) +#define FMC2_CIDCFGR_SEMEN BIT(1) +#define FMC2_CIDCFGR_SCID GENMASK(6, 4) +#define FMC2_CIDCFGR_SEMWLC1 BIT(17) + +/* Register: FMC2_SEMCR */ +#define FMC2_SEMCR_SEM_MUTEX BIT(0) +#define FMC2_SEMCR_SEMCID GENMASK(6, 4) + #define FMC2_MAX_EBI_CE 4 #define FMC2_MAX_BANKS 5 +#define FMC2_MAX_RESOURCES 6 +#define FMC2_CID1 1 #define FMC2_BCR_CPSIZE_0 0x0 #define FMC2_BCR_CPSIZE_128 0x1 @@ -76,6 +104,11 @@ #define FMC2_BCR_MTYP_PSRAM 0x1 #define FMC2_BCR_MTYP_NOR 0x2 +#define FMC2_BCR_CSCOUNT_0 0x0 +#define FMC2_BCR_CSCOUNT_1 0x1 +#define FMC2_BCR_CSCOUNT_64 0x2 +#define FMC2_BCR_CSCOUNT_256 0x3 + #define FMC2_BXTR_EXTMOD_A 0x0 #define FMC2_BXTR_EXTMOD_B 0x1 #define FMC2_BXTR_EXTMOD_C 0x2 @@ -90,6 +123,7 @@ #define FMC2_BTR_CLKDIV_MAX 0xf #define FMC2_BTR_DATLAT_MAX 0xf #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff +#define FMC2_CFGR_CLKDIV_MAX 0xf enum stm32_fmc2_ebi_bank { FMC2_EBI1 = 0, @@ -103,7 +137,8 @@ enum stm32_fmc2_ebi_register_type { FMC2_REG_BCR = 1, FMC2_REG_BTR, FMC2_REG_BWTR, - FMC2_REG_PCSCNTR + FMC2_REG_PCSCNTR, + FMC2_REG_CFGR }; enum stm32_fmc2_ebi_transaction_type { @@ -134,10 +169,30 @@ enum stm32_fmc2_ebi_cpsize { FMC2_CPSIZE_1024 = 1024 }; +enum stm32_fmc2_ebi_cscount { + FMC2_CSCOUNT_0 = 0, + FMC2_CSCOUNT_1 = 1, + FMC2_CSCOUNT_64 = 64, + FMC2_CSCOUNT_256 = 256 +}; + +struct stm32_fmc2_ebi; + +struct stm32_fmc2_ebi_data { + const struct stm32_fmc2_prop *child_props; + unsigned int nb_child_props; + u32 fmc2_enable_reg; + u32 fmc2_enable_bit; + int (*nwait_used_by_ctrls)(struct stm32_fmc2_ebi *ebi); + int (*check_rif)(struct stm32_fmc2_ebi *ebi, u32 resource); +}; + struct stm32_fmc2_ebi { struct clk clk; fdt_addr_t io_base; + const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; + bool access_granted; }; /* @@ -209,6 +264,28 @@ static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi, return -EINVAL; } +static int stm32_fmc2_ebi_mp25_check_cclk(struct stm32_fmc2_ebi *ebi, + const struct stm32_fmc2_prop *prop, + int cs) +{ + if (!ebi->access_granted) + return -EACCES; + + return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); +} + +static int stm32_fmc2_ebi_mp25_check_clk_period(struct stm32_fmc2_ebi *ebi, + const struct stm32_fmc2_prop *prop, + int cs) +{ + u32 cfgr = readl(ebi->io_base + FMC2_CFGR); + + if (cfgr & FMC2_CFGR_CCLKEN && !ebi->access_granted) + return -EACCES; + + return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); +} + static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi, const struct stm32_fmc2_prop *prop, int cs) @@ -296,6 +373,24 @@ static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, return DIV_ROUND_UP(nb_clk_cycles, clk_period); } +static u32 stm32_fmc2_ebi_mp25_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, + int cs, u32 setup) +{ + u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); + u32 cfgr = readl(ebi->io_base + FMC2_CFGR); + u32 clk_period; + + if (cfgr & FMC2_CFGR_CCLKEN) { + clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; + } else { + u32 btr = readl(ebi->io_base + FMC2_BTR(cs)); + + clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + } + + return DIV_ROUND_UP(nb_clk_cycles, clk_period); +} + static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) { switch (reg_type) { @@ -311,6 +406,9 @@ static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) case FMC2_REG_PCSCNTR: *reg = FMC2_PCSCNTR; break; + case FMC2_REG_CFGR: + *reg = FMC2_CFGR; + break; default: return -EINVAL; } @@ -649,6 +747,26 @@ static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, return 0; } +static int stm32_fmc2_ebi_mp25_set_clk_period(struct stm32_fmc2_ebi *ebi, + const struct stm32_fmc2_prop *prop, + int cs, u32 setup) +{ + u32 cfgr = readl(ebi->io_base + FMC2_CFGR); + u32 val; + + if (cfgr & FMC2_CFGR_CCLKEN) { + val = setup ? clamp_val(setup - 1, 1, FMC2_CFGR_CLKDIV_MAX) : 1; + val = FIELD_PREP(FMC2_CFGR_CLKDIV, val); + clrsetbits_le32(ebi->io_base + FMC2_CFGR, FMC2_CFGR_CLKDIV, val); + } else { + val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; + val = FIELD_PREP(FMC2_BTR_CLKDIV, val); + clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); + } + + return 0; +} + static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi, const struct stm32_fmc2_prop *prop, int cs, u32 setup) @@ -689,6 +807,27 @@ static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, return 0; } +static int stm32_fmc2_ebi_mp25_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, + const struct stm32_fmc2_prop *prop, + int cs, u32 setup) +{ + u32 val; + + if (setup == FMC2_CSCOUNT_0) + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_0); + else if (setup == FMC2_CSCOUNT_1) + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_1); + else if (setup <= FMC2_CSCOUNT_64) + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_64); + else + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_256); + + clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), + FMC2_BCR_CSCOUNT, val); + + return 0; +} + static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { /* st,fmc2-ebi-cs-trans-type must be the first property */ { @@ -854,6 +993,235 @@ static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { }, }; +static const struct stm32_fmc2_prop stm32_fmc2_mp25_child_props[] = { + /* st,fmc2-ebi-cs-trans-type must be the first property */ + { + .name = "st,fmc2-ebi-cs-transaction-type", + .mprop = true, + .set = stm32_fmc2_ebi_set_trans_type, + }, + { + .name = "st,fmc2-ebi-cs-cclk-enable", + .bprop = true, + .reg_type = FMC2_REG_CFGR, + .reg_mask = FMC2_CFGR_CCLKEN, + .check = stm32_fmc2_ebi_mp25_check_cclk, + .set = stm32_fmc2_ebi_set_bit_field, + }, + { + .name = "st,fmc2-ebi-cs-mux-enable", + .bprop = true, + .reg_type = FMC2_REG_BCR, + .reg_mask = FMC2_BCR_MUXEN, + .check = stm32_fmc2_ebi_check_mux, + .set = stm32_fmc2_ebi_set_bit_field, + }, + { + .name = "st,fmc2-ebi-cs-buswidth", + .reset_val = FMC2_BUSWIDTH_16, + .set = stm32_fmc2_ebi_set_buswidth, + }, + { + .name = "st,fmc2-ebi-cs-waitpol-high", + .bprop = true, + .reg_type = FMC2_REG_BCR, + .reg_mask = FMC2_BCR_WAITPOL, + .set = stm32_fmc2_ebi_set_bit_field, + }, + { + .name = "st,fmc2-ebi-cs-waitcfg-enable", + .bprop = true, + .reg_type = FMC2_REG_BCR, + .reg_mask = FMC2_BCR_WAITCFG, + .check = stm32_fmc2_ebi_check_waitcfg, + .set = stm32_fmc2_ebi_set_bit_field, + }, + { + .name = "st,fmc2-ebi-cs-wait-enable", + .bprop = true, + .reg_type = FMC2_REG_BCR, + .reg_mask = FMC2_BCR_WAITEN, + .check = stm32_fmc2_ebi_check_sync_trans, + .set = stm32_fmc2_ebi_set_bit_field, + }, + { + .name = "st,fmc2-ebi-cs-asyncwait-enable", + .bprop = true, + .reg_type = FMC2_REG_BCR, + .reg_mask = FMC2_BCR_ASYNCWAIT, + .check = stm32_fmc2_ebi_check_async_trans, + .set = stm32_fmc2_ebi_set_bit_field, + }, + { + .name = "st,fmc2-ebi-cs-cpsize", + .check = stm32_fmc2_ebi_check_cpsize, + .set = stm32_fmc2_ebi_set_cpsize, + }, + { + .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_bl_setup, + }, + { + .name = "st,fmc2-ebi-cs-address-setup-ns", + .reg_type = FMC2_REG_BTR, + .reset_val = FMC2_BXTR_ADDSET_MAX, + .check = stm32_fmc2_ebi_check_async_trans, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_address_setup, + }, + { + .name = "st,fmc2-ebi-cs-address-hold-ns", + .reg_type = FMC2_REG_BTR, + .reset_val = FMC2_BXTR_ADDHLD_MAX, + .check = stm32_fmc2_ebi_check_address_hold, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_address_hold, + }, + { + .name = "st,fmc2-ebi-cs-data-setup-ns", + .reg_type = FMC2_REG_BTR, + .reset_val = FMC2_BXTR_DATAST_MAX, + .check = stm32_fmc2_ebi_check_async_trans, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_data_setup, + }, + { + .name = "st,fmc2-ebi-cs-bus-turnaround-ns", + .reg_type = FMC2_REG_BTR, + .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_bus_turnaround, + }, + { + .name = "st,fmc2-ebi-cs-data-hold-ns", + .reg_type = FMC2_REG_BTR, + .check = stm32_fmc2_ebi_check_async_trans, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_data_hold, + }, + { + .name = "st,fmc2-ebi-cs-clk-period-ns", + .reset_val = FMC2_CFGR_CLKDIV_MAX + 1, + .check = stm32_fmc2_ebi_mp25_check_clk_period, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_mp25_set_clk_period, + }, + { + .name = "st,fmc2-ebi-cs-data-latency-ns", + .check = stm32_fmc2_ebi_check_sync_trans, + .calculate = stm32_fmc2_ebi_mp25_ns_to_clk_period, + .set = stm32_fmc2_ebi_set_data_latency, + }, + { + .name = "st,fmc2-ebi-cs-write-address-setup-ns", + .reg_type = FMC2_REG_BWTR, + .reset_val = FMC2_BXTR_ADDSET_MAX, + .check = stm32_fmc2_ebi_check_async_trans, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_address_setup, + }, + { + .name = "st,fmc2-ebi-cs-write-address-hold-ns", + .reg_type = FMC2_REG_BWTR, + .reset_val = FMC2_BXTR_ADDHLD_MAX, + .check = stm32_fmc2_ebi_check_address_hold, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_address_hold, + }, + { + .name = "st,fmc2-ebi-cs-write-data-setup-ns", + .reg_type = FMC2_REG_BWTR, + .reset_val = FMC2_BXTR_DATAST_MAX, + .check = stm32_fmc2_ebi_check_async_trans, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_data_setup, + }, + { + .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", + .reg_type = FMC2_REG_BWTR, + .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_bus_turnaround, + }, + { + .name = "st,fmc2-ebi-cs-write-data-hold-ns", + .reg_type = FMC2_REG_BWTR, + .check = stm32_fmc2_ebi_check_async_trans, + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_set_data_hold, + }, + { + .name = "st,fmc2-ebi-cs-max-low-pulse-ns", + .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, + .set = stm32_fmc2_ebi_mp25_set_max_low_pulse, + }, +}; + +static int stm32_fmc2_ebi_mp25_check_rif(struct stm32_fmc2_ebi *ebi, u32 resource) +{ + u32 seccfgr, cidcfgr, semcr; + int cid; + + if (resource >= FMC2_MAX_RESOURCES) + return -EINVAL; + + seccfgr = readl(ebi->io_base + FMC2_SECCFGR); + if (seccfgr & BIT(resource)) { + if (resource) + log_err("resource %d is configured as secure\n", + resource); + + return -EACCES; + } + + cidcfgr = readl(ebi->io_base + FMC2_CIDCFGR(resource)); + if (!(cidcfgr & FMC2_CIDCFGR_CFEN)) + /* CID filtering is turned off: access granted */ + return 0; + + if (!(cidcfgr & FMC2_CIDCFGR_SEMEN)) { + /* Static CID mode */ + cid = FIELD_GET(FMC2_CIDCFGR_SCID, cidcfgr); + if (cid != FMC2_CID1) { + if (resource) + log_err("static CID%d set for resource %d\n", + cid, resource); + + return -EACCES; + } + + return 0; + } + + /* Pass-list with semaphore mode */ + if (!(cidcfgr & FMC2_CIDCFGR_SEMWLC1)) { + if (resource) + log_err("CID1 is block-listed for resource %d\n", + resource); + + return -EACCES; + } + + semcr = readl(ebi->io_base + FMC2_SEMCR(resource)); + if (!(semcr & FMC2_SEMCR_SEM_MUTEX)) { + setbits_le32(ebi->io_base + FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX); + semcr = readl(ebi->io_base + FMC2_SEMCR(resource)); + } + + cid = FIELD_GET(FMC2_SEMCR_SEMCID, semcr); + if (cid != FMC2_CID1) { + if (resource) + log_err("resource %d is already used by CID%d\n", + resource, cid); + + return -EACCES; + } + + return 0; +} + static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, ofnode node, const struct stm32_fmc2_prop *prop, @@ -915,7 +1283,7 @@ static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs) } /* NWAIT signal can not be connected to EBI controller and NAND controller */ -static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) +static int stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) { unsigned int cs; u32 bcr; @@ -926,16 +1294,22 @@ static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) bcr = readl(ebi->io_base + FMC2_BCR(cs)); if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) && - ebi->bank_assigned & BIT(FMC2_NAND)) - return true; + ebi->bank_assigned & BIT(FMC2_NAND)) { + log_err("NWAIT signal connected to EBI and NAND controllers\n"); + return -EINVAL; + } } - return false; + return 0; } static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) { - setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN); + if (!ebi->access_granted) + return; + + setbits_le32(ebi->io_base + ebi->data->fmc2_enable_reg, + ebi->data->fmc2_enable_bit); } static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, @@ -946,8 +1320,8 @@ static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, stm32_fmc2_ebi_disable_bank(ebi, cs); - for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) { - const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i]; + for (i = 0; i < ebi->data->nb_child_props; i++) { + const struct stm32_fmc2_prop *p = &ebi->data->child_props[i]; ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs); if (ret) { @@ -987,6 +1361,14 @@ static int stm32_fmc2_ebi_parse_dt(struct udevice *dev, return -EINVAL; } + if (ebi->data->check_rif) { + ret = ebi->data->check_rif(ebi, bank + 1); + if (ret) { + dev_err(dev, "bank access failed: %d\n", bank); + return ret; + } + } + if (bank < FMC2_MAX_EBI_CE) { ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); if (ret) { @@ -1004,9 +1386,10 @@ static int stm32_fmc2_ebi_parse_dt(struct udevice *dev, return -ENODEV; } - if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) { - dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); - return -EINVAL; + if (ebi->data->nwait_used_by_ctrls) { + ret = ebi->data->nwait_used_by_ctrls(ebi); + if (ret) + return ret; } stm32_fmc2_ebi_enable(ebi); @@ -1020,6 +1403,10 @@ static int stm32_fmc2_ebi_probe(struct udevice *dev) struct reset_ctl reset; int ret; + ebi->data = (void *)dev_get_driver_data(dev); + if (!ebi->data) + return -EINVAL; + ebi->io_base = dev_read_addr(dev); if (ebi->io_base == FDT_ADDR_T_NONE) return -EINVAL; @@ -1039,11 +1426,49 @@ static int stm32_fmc2_ebi_probe(struct udevice *dev) reset_deassert(&reset); } + /* Check if CFGR register can be modified */ + ebi->access_granted = true; + if (ebi->data->check_rif) { + ret = ebi->data->check_rif(ebi, 0); + if (ret) { + ebi->access_granted = false; + + /* In case of CFGR is secure, just check that the FMC2 is enabled */ + if (readl(ebi->io_base + FMC2_SR) & FMC2_SR_ISOST) { + dev_err(dev, "FMC2 is not ready to be used.\n"); + return -EACCES; + } + } + } + return stm32_fmc2_ebi_parse_dt(dev, ebi); } +static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp1_data = { + .child_props = stm32_fmc2_child_props, + .nb_child_props = ARRAY_SIZE(stm32_fmc2_child_props), + .fmc2_enable_reg = FMC2_BCR1, + .fmc2_enable_bit = FMC2_BCR1_FMC2EN, + .nwait_used_by_ctrls = stm32_fmc2_ebi_nwait_used_by_ctrls, +}; + +static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp25_data = { + .child_props = stm32_fmc2_mp25_child_props, + .nb_child_props = ARRAY_SIZE(stm32_fmc2_mp25_child_props), + .fmc2_enable_reg = FMC2_CFGR, + .fmc2_enable_bit = FMC2_CFGR_FMC2EN, + .check_rif = stm32_fmc2_ebi_mp25_check_rif, +}; + static const struct udevice_id stm32_fmc2_ebi_match[] = { - {.compatible = "st,stm32mp1-fmc2-ebi"}, + { + .compatible = "st,stm32mp1-fmc2-ebi", + .data = (ulong)&stm32_fmc2_ebi_mp1_data, + }, + { + .compatible = "st,stm32mp25-fmc2-ebi", + .data = (ulong)&stm32_fmc2_ebi_mp25_data, + }, { /* Sentinel */ } }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6b06888454f..6009d55f400 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -104,7 +104,7 @@ config ROCKCHIP_OTP config ROCKCHIP_IODOMAIN bool "Rockchip IO-domain driver support" depends on DM_REGULATOR && ARCH_ROCKCHIP - default y if ROCKCHIP_RK3568 + default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568 help Enable support for IO-domains in Rockchip SoCs. It is necessary for the IO-domain setting of the SoC to match the voltage supplied diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c index 0ffea32ef07..04d4d07c412 100644 --- a/drivers/misc/rockchip-io-domain.c +++ b/drivers/misc/rockchip-io-domain.c @@ -27,6 +27,10 @@ #define MAX_VOLTAGE_1_8 1980000 #define MAX_VOLTAGE_3_3 3600000 +#define RK3328_SOC_CON4 0x410 +#define RK3328_SOC_CON4_VCCIO2 BIT(7) +#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 + #define RK3399_PMUGRF_CON0 0x180 #define RK3399_PMUGRF_CON0_VSEL BIT(8) #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9 @@ -95,6 +99,22 @@ static int rockchip_iodomain_write(struct regmap *grf, uint offset, int idx, int return regmap_write(grf, offset, val); } +static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) +{ + int ret = rockchip_iodomain_write(grf, offset, idx, uV); + + if (!ret && idx == RK3328_SOC_VCCIO2_SUPPLY_NUM) { + /* + * set vccio2 iodomain to also use this framework + * instead of a special gpio. + */ + u32 val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16); + ret = regmap_write(grf, RK3328_SOC_CON4, val); + } + + return ret; +} + static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) { int ret = rockchip_iodomain_write(grf, offset, idx, uV); @@ -111,6 +131,20 @@ static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx, i return ret; } +static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { + .grf_offset = 0x410, + .supply_names = { + "vccio1-supply", + "vccio2-supply", + "vccio3-supply", + "vccio4-supply", + "vccio5-supply", + "vccio6-supply", + "pmuio-supply", + }, + .write = rk3328_iodomain_write, +}; + static const struct rockchip_iodomain_soc_data soc_data_rk3399 = { .grf_offset = 0xe640, .supply_names = { @@ -157,6 +191,10 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { static const struct udevice_id rockchip_iodomain_ids[] = { { + .compatible = "rockchip,rk3328-io-voltage-domain", + .data = (ulong)&soc_data_rk3328, + }, + { .compatible = "rockchip,rk3399-io-voltage-domain", .data = (ulong)&soc_data_rk3399, }, diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 06e32e75696..549634891a3 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -504,6 +504,24 @@ config SPL_MMC_SDHCI_ADMA This enables support for the ADMA (Advanced DMA) defined in the SD Host Controller Standard Specification Version 3.00 in SPL. +config MMC_SDHCI_ADMA_FORCE_32BIT + bool "Force 32 bit mode for ADMA on 64 bit platforms" + help + This forces SDHCI ADMA to be built for 32 bit descriptors, even + on a 64 bit platform where they would otherwise be assumed to + be 64 bits. This is necessary for certain hardware platforms + that are 64-bit but include only 32-bit support within the selected + SD host controller IP. + +config MMC_SDHCI_ADMA_64BIT + bool "Use SHDCI ADMA with 64 bit descriptors" + depends on !MMC_SDHCI_ADMA_FORCE_32BIT + default y if DMA_ADDR_T_64BIT + help + This selects 64 bit descriptors for SDHCI ADMA. It is enabled by + default on 64 bit systems, but can be disabled if one of these + systems includes 32-bit ADMA. + config FIXED_SDHCI_ALIGNED_BUFFER hex "SDRAM address for fixed buffer" depends on SPL && MVEBU_SPL_BOOT_DEVICE_MMC diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 2139fea04d5..fadab7d40bb 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -85,6 +85,8 @@ #define AM654_SDHCI_MIN_FREQ 400000 #define CLOCK_TOO_SLOW_HZ 50000000 +#define ENABLE 0x1 + struct am654_sdhci_plat { struct mmc_config cfg; struct mmc mmc; @@ -92,11 +94,13 @@ struct am654_sdhci_plat { bool non_removable; u32 otap_del_sel[MMC_MODES_END]; u32 itap_del_sel[MMC_MODES_END]; + u32 itap_del_ena[MMC_MODES_END]; u32 trm_icp; u32 drv_strength; u32 strb_sel; u32 clkbuf_sel; u32 flags; + bool dll_enable; #define DLL_PRESENT BIT(0) #define IOMUX_PRESENT BIT(1) #define FREQSEL_2_BIT BIT(2) @@ -110,6 +114,12 @@ struct timing_data { u32 capability; }; +struct window { + u8 start; + u8 end; + u8 length; +}; + static const struct timing_data td[] = { [MMC_LEGACY] = {"ti,otap-del-sel-legacy", "ti,itap-del-sel-legacy", @@ -216,8 +226,10 @@ static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat, } static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat, - u32 itapdly) + u32 itapdly, u32 enable) { + regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK, + enable << ITAPDLYENA_SHIFT); /* Set ITAPCHGWIN before writing to ITAPDLY */ regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 1 << ITAPCHGWIN_SHIFT); @@ -235,7 +247,8 @@ static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat, mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; regmap_update_bits(plat->base, PHY_CTRL5, mask, val); - am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]); + am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode], + plat->itap_del_ena[mode]); } static int am654_sdhci_set_ios_post(struct sdhci_host *host) @@ -276,12 +289,22 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) regmap_update_bits(plat->base, PHY_CTRL4, mask, val); - if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) { + if ((mode > UHS_SDR25 || mode == MMC_DDR_52) && speed >= CLOCK_TOO_SLOW_HZ) { ret = am654_sdhci_setup_dll(plat, speed); if (ret) return ret; + + plat->dll_enable = true; + if (mode == MMC_HS_400) { + plat->itap_del_ena[mode] = ENABLE; + plat->itap_del_sel[mode] = plat->itap_del_sel[mode - 1]; + } + + am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode], + plat->itap_del_ena[mode]); } else { am654_sdhci_setup_delay_chain(plat, mode); + plat->dll_enable = false; } regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK, @@ -375,39 +398,103 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg) writeb(val, host->ioaddr + reg); } #ifdef MMC_SUPPORTS_TUNING -#define ITAP_MAX 32 +#define ITAPDLY_LENGTH 32 +#define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) + +static u32 am654_sdhci_calculate_itap(struct udevice *dev, struct window + *fail_window, u8 num_fails, bool circular_buffer) +{ + u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; + u8 first_fail_start = 0, last_fail_end = 0; + struct window pass_window = {0, 0, 0}; + int prev_fail_end = -1; + u8 i; + + if (!num_fails) + return ITAPDLY_LAST_INDEX >> 1; + + if (fail_window->length == ITAPDLY_LENGTH) { + dev_err(dev, "No passing ITAPDLY, return 0\n"); + return 0; + } + + first_fail_start = fail_window->start; + last_fail_end = fail_window[num_fails - 1].end; + + for (i = 0; i < num_fails; i++) { + start_fail = fail_window[i].start; + end_fail = fail_window[i].end; + pass_length = start_fail - (prev_fail_end + 1); + + if (pass_length > pass_window.length) { + pass_window.start = prev_fail_end + 1; + pass_window.length = pass_length; + } + prev_fail_end = end_fail; + } + + if (!circular_buffer) + pass_length = ITAPDLY_LAST_INDEX - last_fail_end; + else + pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; + + if (pass_length > pass_window.length) { + pass_window.start = last_fail_end + 1; + pass_window.length = pass_length; + } + + if (!circular_buffer) + itap = pass_window.start + (pass_window.length >> 1); + else + itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; + + return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; +} + static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) { struct udevice *dev = mmc->dev; struct am654_sdhci_plat *plat = dev_get_plat(dev); - int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; - u32 itap; + struct window fail_window[ITAPDLY_LENGTH]; + int mode = mmc->selected_mode; + u8 curr_pass, itap; + u8 fail_index = 0; + u8 prev_pass = 1; + + memset(fail_window, 0, sizeof(fail_window)); /* Enable ITAPDLY */ - regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK, - 1 << ITAPDLYENA_SHIFT); + plat->itap_del_ena[mode] = ENABLE; - for (itap = 0; itap < ITAP_MAX; itap++) { - am654_sdhci_write_itapdly(plat, itap); + for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { + am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]); - cur_val = !mmc_send_tuning(mmc, opcode); - if (cur_val && !prev_val) - pass_window = itap; + curr_pass = !mmc_send_tuning(mmc, opcode); - if (!cur_val) - fail_len++; + if (!curr_pass && prev_pass) + fail_window[fail_index].start = itap; - prev_val = cur_val; + if (!curr_pass) { + fail_window[fail_index].end = itap; + fail_window[fail_index].length++; + } + + if (curr_pass && !prev_pass) + fail_index++; + + prev_pass = curr_pass; } - /* - * Having determined the length of the failing window and start of - * the passing window calculate the length of the passing window and - * set the final value halfway through it considering the range as a - * circular buffer - */ - pass_len = ITAP_MAX - fail_len; - itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; - am654_sdhci_write_itapdly(plat, itap); + + if (fail_window[fail_index].length != 0) + fail_index++; + + itap = am654_sdhci_calculate_itap(dev, fail_window, fail_index, + plat->dll_enable); + + /* Save ITAPDLY */ + plat->itap_del_sel[mode] = itap; + + am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]); return 0; } @@ -442,12 +529,29 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) { struct udevice *dev = host->mmc->dev; struct am654_sdhci_plat *plat = dev_get_plat(dev); - u32 otap_del_sel, mask, val; + int mode = host->mmc->selected_mode; + u32 otap_del_sel; + u32 itap_del_ena; + u32 itap_del_sel; + u32 mask, val; + + otap_del_sel = plat->otap_del_sel[mode]; - otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode]; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (1 << OTAPDLYENA_SHIFT) | + (otap_del_sel << OTAPDLYSEL_SHIFT); + + itap_del_ena = plat->itap_del_ena[mode]; + itap_del_sel = plat->itap_del_sel[mode]; + + mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK; + val |= (itap_del_ena << ITAPDLYENA_SHIFT) | + (itap_del_sel << ITAPDLYSEL_SHIFT); + + regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 1 << ITAPCHGWIN_SHIFT); regmap_update_bits(plat->base, PHY_CTRL4, mask, val); + regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK, plat->clkbuf_sel); @@ -501,7 +605,7 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev, * Remove the corresponding capability if an otap-del-sel * value is not found */ - for (i = MMC_HS; i <= MMC_HS_400; i++) { + for (i = MMC_LEGACY; i <= MMC_HS_400; i++) { ret = dev_read_u32(dev, td[i].otap_binding, &plat->otap_del_sel[i]); if (ret) { @@ -513,9 +617,13 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev, cfg->host_caps &= ~td[i].capability; } - if (td[i].itap_binding) - dev_read_u32(dev, td[i].itap_binding, - &plat->itap_del_sel[i]); + if (td[i].itap_binding) { + ret = dev_read_u32(dev, td[i].itap_binding, + &plat->itap_del_sel[i]); + + if (!ret) + plat->itap_del_ena[i] = ENABLE; + } } return 0; diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 2666b65362b..cecc7ad783d 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -229,6 +229,7 @@ static int do_data_transfer(struct mmc *dev, u32 blksz = 0; u32 data_ctrl = 0; u32 data_len = (u32) (data->blocks * data->blocksize); + assert(data_len < U16_MAX); /* should be ensured by arm_pl180_get_b_max */ if (!host->version2) { blksz = (ffs(data->blocksize) - 1); @@ -356,6 +357,14 @@ static int host_set_ios(struct mmc *dev) return 0; } +static int arm_pl180_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; + + return U16_MAX / mmc->read_bl_len; +} + static void arm_pl180_mmc_init(struct pl180_mmc_host *host) { u32 sdi_u32; @@ -470,6 +479,7 @@ static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = { .send_cmd = dm_host_request, .set_ios = dm_host_set_ios, .get_cd = dm_mmc_getcd, + .get_b_max = arm_pl180_get_b_max, }; static int arm_pl180_mmc_of_to_plat(struct udevice *dev) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index d44dfa5d06f..595d88bd562 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -252,7 +252,7 @@ static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data) priv->adma_desc_table) { debug("Using ADMA2\n"); /* prefer ADMA2 if it is available */ - sdhci_prepare_adma_table(priv->adma_desc_table, data, + sdhci_prepare_adma_table(NULL, priv->adma_desc_table, data, priv->dma_addr); adma_addr = virt_to_phys(priv->adma_desc_table); diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 1e03901e9dc..24170c59ecc 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -257,11 +257,14 @@ int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg) if (dev_read_bool(dev, "mmc-hs200-1_2v")) cfg->host_caps |= MMC_CAP(MMC_HS_200); if (dev_read_bool(dev, "mmc-hs400-1_8v")) - cfg->host_caps |= MMC_CAP(MMC_HS_400); + cfg->host_caps |= MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_200); if (dev_read_bool(dev, "mmc-hs400-1_2v")) - cfg->host_caps |= MMC_CAP(MMC_HS_400); + cfg->host_caps |= MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_200); if (dev_read_bool(dev, "mmc-hs400-enhanced-strobe")) cfg->host_caps |= MMC_CAP(MMC_HS_400_ES); + if (dev_read_bool(dev, "no-mmc-hs400")) + cfg->host_caps &= ~(MMC_CAP(MMC_HS_400) | + MMC_CAP(MMC_HS_400_ES)); if (dev_read_bool(dev, "non-removable")) { cfg->host_caps |= MMC_CAP_NONREMOVABLE; diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 059cb3da77c..5e9d66526a8 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -33,9 +33,6 @@ #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 -/* Non standard (?) SDHCI register */ -#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c - struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; @@ -49,6 +46,8 @@ struct msm_sdhc { struct msm_sdhc_variant_info { bool mci_removed; + + u32 core_vendor_spec_capabilities0; }; DECLARE_GLOBAL_DATA_PTR; @@ -63,7 +62,7 @@ static int msm_sdc_clk_init(struct udevice *dev) ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) - clk_rate = 400000; + clk_rate = 201500000; ret = clk_get_bulk(dev, &prv->clks); if (ret) { @@ -174,6 +173,8 @@ static int msm_sdc_probe(struct udevice *dev) core_minor = core_version & SDCC_VERSION_MINOR_MASK; + log_debug("SDCC version %d.%d\n", core_major, core_minor); + /* * Support for some capabilities is not advertised by newer * controller versions and must be explicitly enabled. @@ -181,7 +182,7 @@ static int msm_sdc_probe(struct udevice *dev) if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { caps = readl(host->ioaddr + SDHCI_CAPABILITIES); caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; - writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); + writel(caps, host->ioaddr + var_info->core_vendor_spec_capabilities0); } ret = mmc_of_parse(dev, &plat->cfg); @@ -207,7 +208,7 @@ static int msm_sdc_remove(struct udevice *dev) var_info = (void *)dev_get_driver_data(dev); /* Disable host-controller mode */ - if (!var_info->mci_removed) + if (!var_info->mci_removed && priv->base) writel(0, priv->base + SDCC_MCI_HC_MODE); clk_release_bulk(&priv->clks); @@ -217,21 +218,31 @@ static int msm_sdc_remove(struct udevice *dev) static int msm_of_to_plat(struct udevice *dev) { - struct udevice *parent = dev->parent; struct msm_sdhc *priv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; struct sdhci_host *host = &priv->host; - int node = dev_of_offset(dev); + int ret; + + var_info = (void*)dev_get_driver_data(dev); host->name = strdup(dev->name); host->ioaddr = dev_read_addr_ptr(dev); - host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4); - host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0); - priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, - dev_of_offset(parent), node, "reg", 1, NULL, false); - if (priv->base == (void *)FDT_ADDR_T_NONE || - host->ioaddr == (void *)FDT_ADDR_T_NONE) + ret = dev_read_u32(dev, "bus-width", &host->bus_width); + if (ret) + host->bus_width = 4; + ret = dev_read_u32(dev, "index", &host->index); + if (ret) + host->index = 0; + priv->base = dev_read_addr_index_ptr(dev, 1); + + if (!host->ioaddr) return -EINVAL; + if (!var_info->mci_removed && !priv->base) { + printf("msm_sdhci: MCI base address not found\n"); + return -EINVAL; + } + return 0; } @@ -244,10 +255,14 @@ static int msm_sdc_bind(struct udevice *dev) static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + + .core_vendor_spec_capabilities0 = 0x11c, }; static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + + .core_vendor_spec_capabilities0 = 0x21c, }; static const struct udevice_id msm_mmc_ids[] = { diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 706fb123579..c889c7bc985 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -391,6 +391,8 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) { struct mmc *mmc = host->mmc; + struct rockchip_sdhc_plat *plat = dev_get_plat(mmc->dev); + struct mmc_config *cfg = &plat->cfg; u32 reg; reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); @@ -437,6 +439,20 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL); + /* + * Reading more than 4 blocks with a single CMD18 command in PIO mode + * triggers Data End Bit Error using a slower mode than HS200. Limit to + * reading max 4 blocks in one command when using PIO mode. + */ + if (!(host->flags & USE_DMA)) { + if (mmc->selected_mode == MMC_HS_200 || + mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == MMC_HS_400_ES) + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + else + cfg->b_max = 4; + } + return 0; } @@ -598,16 +614,6 @@ static int rockchip_sdhci_probe(struct udevice *dev) dev_read_bool(dev, "u-boot,spl-fifo-mode")) host->flags &= ~USE_DMA; - /* - * Reading more than 4 blocks with a single CMD18 command in PIO mode - * triggers Data End Bit Error on RK3568 and RK3588. Limit to reading - * max 4 blocks in one command when using PIO mode. - */ - if (!(host->flags & USE_DMA) && - (device_is_compatible(dev, "rockchip,rk3568-dwcmshc") || - device_is_compatible(dev, "rockchip,rk3588-dwcmshc"))) - cfg->b_max = 4; - return sdhci_probe(dev); } diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c index 8213223d3f9..283ba956deb 100644 --- a/drivers/mmc/sdhci-adma.c +++ b/drivers/mmc/sdhci-adma.c @@ -9,9 +9,10 @@ #include <malloc.h> #include <asm/cache.h> -static void sdhci_adma_desc(struct sdhci_adma_desc *desc, - dma_addr_t addr, u16 len, bool end) +void sdhci_adma_write_desc(struct sdhci_host *host, void **next_desc, + dma_addr_t addr, int len, bool end) { + struct sdhci_adma_desc *desc = *next_desc; u8 attr; attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; @@ -19,17 +20,30 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc, attr |= ADMA_DESC_ATTR_END; desc->attr = attr; - desc->len = len; + desc->len = len & 0xffff; desc->reserved = 0; desc->addr_lo = lower_32_bits(addr); -#ifdef CONFIG_DMA_ADDR_T_64BIT +#ifdef CONFIG_MMC_SDHCI_ADMA_64BIT desc->addr_hi = upper_32_bits(addr); #endif + + *next_desc += ADMA_DESC_LEN; +} + +static inline void __sdhci_adma_write_desc(struct sdhci_host *host, + void **desc, dma_addr_t addr, + int len, bool end) +{ + if (host && host->ops && host->ops->adma_write_desc) + host->ops->adma_write_desc(host, desc, addr, len, end); + else + sdhci_adma_write_desc(host, desc, addr, len, end); } /** * sdhci_prepare_adma_table() - Populate the ADMA table * + * @host: Pointer to the sdhci_host * @table: Pointer to the ADMA table * @data: Pointer to MMC data * @addr: DMA address to write to or read from @@ -39,25 +53,26 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc, * Please note, that the table size depends on CONFIG_SYS_MMC_MAX_BLK_COUNT and * we don't have to check for overflow. */ -void sdhci_prepare_adma_table(struct sdhci_adma_desc *table, - struct mmc_data *data, dma_addr_t addr) +void sdhci_prepare_adma_table(struct sdhci_host *host, + struct sdhci_adma_desc *table, + struct mmc_data *data, dma_addr_t start_addr) { + dma_addr_t addr = start_addr; uint trans_bytes = data->blocksize * data->blocks; - uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN); - struct sdhci_adma_desc *desc = table; - int i = desc_count; + void *next_desc = table; + int i = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN); while (--i) { - sdhci_adma_desc(desc, addr, ADMA_MAX_LEN, false); + __sdhci_adma_write_desc(host, &next_desc, addr, + ADMA_MAX_LEN, false); addr += ADMA_MAX_LEN; trans_bytes -= ADMA_MAX_LEN; - desc++; } - sdhci_adma_desc(desc, addr, trans_bytes, true); + __sdhci_adma_write_desc(host, &next_desc, addr, trans_bytes, true); - flush_cache((dma_addr_t)table, - ROUND(desc_count * sizeof(struct sdhci_adma_desc), + flush_cache((phys_addr_t)table, + ROUND(next_desc - (void *)table, ARCH_DMA_MINALIGN)); } diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 0178ed8a11e..af654ea8d13 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -111,7 +111,7 @@ static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, } #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) else if (host->flags & (USE_ADMA | USE_ADMA64)) { - sdhci_prepare_adma_table(host->adma_desc_table, data, + sdhci_prepare_adma_table(host, host->adma_desc_table, data, host->start_addr); sdhci_writel(host, lower_32_bits(host->adma_addr), @@ -897,14 +897,15 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, __func__); return -EINVAL; } - host->adma_desc_table = sdhci_adma_init(); - host->adma_addr = (dma_addr_t)host->adma_desc_table; + if (!host->adma_desc_table) { + host->adma_desc_table = sdhci_adma_init(); + host->adma_addr = virt_to_phys(host->adma_desc_table); + } -#ifdef CONFIG_DMA_ADDR_T_64BIT - host->flags |= USE_ADMA64; -#else - host->flags |= USE_ADMA; -#endif + if (IS_ENABLED(CONFIG_MMC_SDHCI_ADMA_64BIT)) + host->flags |= USE_ADMA64; + else + host->flags |= USE_ADMA; #endif if (host->quirks & SDHCI_QUIRK_REG32_RW) host->version = @@ -929,6 +930,15 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, debug("%s, caps_1: 0x%x\n", __func__, caps_1); host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; + + /* + * In case the value in Clock Multiplier is 0, then programmable + * clock mode is not supported, otherwise the actual clock + * multiplier is one more than the value of Clock Multiplier + * in the Capabilities Register. + */ + if (host->clk_mul) + host->clk_mul += 1; } if (host->max_clk == 0) { diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index a2b111a8435..39ae79ba129 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -220,9 +220,9 @@ static void stm32_sdmmc2_start_data(struct udevice *dev, if (data->flags & MMC_DATA_READ) { data_ctrl |= SDMMC_DCTRL_DTDIR; - idmabase0 = (u32)data->dest; + idmabase0 = (u32)(long)data->dest; } else { - idmabase0 = (u32)data->src; + idmabase0 = (u32)(long)data->src; } /* Set the SDMMC DataLength value */ @@ -463,8 +463,8 @@ retry_cmd: stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx); - dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n", - cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data); + dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%p\n", + cmd->cmdidx, data ? ctx.data_length : 0, data); ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx); @@ -789,6 +789,7 @@ static int stm32_sdmmc2_bind(struct udevice *dev) static const struct udevice_id stm32_sdmmc2_ids[] = { { .compatible = "st,stm32-sdmmc2" }, + { .compatible = "st,stm32mp25-sdmmc2" }, { } }; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 22ea5e2f907..be60d6d9d99 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -62,7 +62,7 @@ struct nand_flash_dev nand_flash_ids[] = { { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, NAND_ECC_INFO(40, SZ_1K), 4 }, - {"H27QCG8T2E5R‐BCF 64G 3.3V 8-bit", + {"H27QCG8T2E5R-BCF 64G 3.3V 8-bit", { .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} }, SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664, NAND_ECC_INFO(56, SZ_1K), 1 }, diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 3528824575b..d284b8cbb12 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -34,7 +34,7 @@ #define FMC2_RB_DELAY_US 30 /* Max chip enable */ -#define FMC2_MAX_CE 2 +#define FMC2_MAX_CE 4 /* Timings */ #define FMC2_THIZ 1 @@ -160,6 +160,11 @@ static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) return container_of(chip, struct stm32_fmc2_nand, chip); } +struct stm32_fmc2_nfc_data { + int max_ncs; + struct udevice *(*get_cdev)(struct udevice *dev); +}; + struct stm32_fmc2_nfc { struct nand_hw_control base; struct stm32_fmc2_nand nand; @@ -169,6 +174,7 @@ struct stm32_fmc2_nfc { fdt_addr_t cmd_base[FMC2_MAX_CE]; fdt_addr_t addr_base[FMC2_MAX_CE]; struct clk clk; + const struct stm32_fmc2_nfc_data *data; u8 cs_assigned; int cs_sel; @@ -815,7 +821,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) } for (i = 0; i < nand->ncs; i++) { - if (cs[i] >= FMC2_MAX_CE) { + if (cs[i] >= nfc->data->max_ncs) { log_err("Invalid reg value: %d\n", nand->cs_used[i]); return -EINVAL; } @@ -906,10 +912,18 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) spin_lock_init(&nfc->controller.lock); init_waitqueue_head(&nfc->controller.wq); - cdev = stm32_fmc2_nfc_get_cdev(dev); - if (!cdev) + nfc->data = (void *)dev_get_driver_data(dev); + if (!nfc->data) return -EINVAL; + if (nfc->data->get_cdev) { + cdev = nfc->data->get_cdev(dev); + if (!cdev) + return -EINVAL; + } else { + cdev = dev->parent; + } + ret = stm32_fmc2_nfc_parse_dt(dev, nfc); if (ret) return ret; @@ -921,7 +935,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) if (dev == cdev) start_region = 1; - for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE; + for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs; chip_cs++, mem_region += 3) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -1033,9 +1047,28 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) return nand_register(0, mtd); } +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { + .max_ncs = 2, + .get_cdev = stm32_fmc2_nfc_get_cdev, +}; + +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = { + .max_ncs = 4, +}; + static const struct udevice_id stm32_fmc2_nfc_match[] = { - { .compatible = "st,stm32mp15-fmc2" }, - { .compatible = "st,stm32mp1-fmc2-nfc" }, + { + .compatible = "st,stm32mp15-fmc2", + .data = (ulong)&stm32_fmc2_nfc_mp1_data, + }, + { + .compatible = "st,stm32mp1-fmc2-nfc", + .data = (ulong)&stm32_fmc2_nfc_mp1_data, + }, + { + .compatible = "st,stm32mp25-fmc2-nfc", + .data = (ulong)&stm32_fmc2_nfc_mp25_data, + }, { /* Sentinel */ } }; diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d068b7860e1..bedc4e970e4 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -246,7 +246,7 @@ config SPI_FLASH_USE_4K_SECTORS to erasing whole blocks (32/64 KiB). Changing a small part of the flash's contents is usually faster with small sectors. On the other hand erasing should be faster when using - 64 KiB block instead of 16 × 4 KiB sectors. + 64 KiB block instead of 16 x 4 KiB sectors. Please note that some tools/drivers/filesystems may not work with 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6677366ebd6..dc3404519d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o +obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 67d80d987ff..32a5d52165a 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -295,58 +295,6 @@ err: #endif } -static int eqos_start_clks_stm32(struct udevice *dev) -{ -#ifdef CONFIG_CLK - struct eqos_priv *eqos = dev_get_priv(dev); - int ret; - - debug("%s(dev=%p):\n", __func__, dev); - - ret = clk_enable(&eqos->clk_master_bus); - if (ret < 0) { - pr_err("clk_enable(clk_master_bus) failed: %d\n", ret); - goto err; - } - - ret = clk_enable(&eqos->clk_rx); - if (ret < 0) { - pr_err("clk_enable(clk_rx) failed: %d\n", ret); - goto err_disable_clk_master_bus; - } - - ret = clk_enable(&eqos->clk_tx); - if (ret < 0) { - pr_err("clk_enable(clk_tx) failed: %d\n", ret); - goto err_disable_clk_rx; - } - - if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { - ret = clk_enable(&eqos->clk_ck); - if (ret < 0) { - pr_err("clk_enable(clk_ck) failed: %d\n", ret); - goto err_disable_clk_tx; - } - eqos->clk_ck_enabled = true; - } -#endif - - debug("%s: OK\n", __func__); - return 0; - -#ifdef CONFIG_CLK -err_disable_clk_tx: - clk_disable(&eqos->clk_tx); -err_disable_clk_rx: - clk_disable(&eqos->clk_rx); -err_disable_clk_master_bus: - clk_disable(&eqos->clk_master_bus); -err: - debug("%s: FAILED: %d\n", __func__, ret); - return ret; -#endif -} - static int eqos_stop_clks_tegra186(struct udevice *dev) { #ifdef CONFIG_CLK @@ -365,22 +313,6 @@ static int eqos_stop_clks_tegra186(struct udevice *dev) return 0; } -static int eqos_stop_clks_stm32(struct udevice *dev) -{ -#ifdef CONFIG_CLK - struct eqos_priv *eqos = dev_get_priv(dev); - - debug("%s(dev=%p):\n", __func__, dev); - - clk_disable(&eqos->clk_tx); - clk_disable(&eqos->clk_rx); - clk_disable(&eqos->clk_master_bus); -#endif - - debug("%s: OK\n", __func__); - return 0; -} - static int eqos_start_resets_tegra186(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -493,17 +425,6 @@ static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) #endif } -static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) -{ -#ifdef CONFIG_CLK - struct eqos_priv *eqos = dev_get_priv(dev); - - return clk_get_rate(&eqos->clk_master_bus); -#else - return 0; -#endif -} - static int eqos_set_full_duplex(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1415,57 +1336,6 @@ err_free_reset_eqos: return ret; } -static int eqos_probe_resources_stm32(struct udevice *dev) -{ - struct eqos_priv *eqos = dev_get_priv(dev); - int ret; - phy_interface_t interface; - - debug("%s(dev=%p):\n", __func__, dev); - - interface = eqos->config->interface(dev); - - if (interface == PHY_INTERFACE_MODE_NA) { - pr_err("Invalid PHY interface\n"); - return -EINVAL; - } - - ret = board_interface_eth_init(dev, interface); - if (ret) - return -EINVAL; - - ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); - if (ret) { - pr_err("clk_get_by_name(master_bus) failed: %d\n", ret); - goto err_probe; - } - - ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); - if (ret) { - pr_err("clk_get_by_name(rx) failed: %d\n", ret); - goto err_probe; - } - - ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); - if (ret) { - pr_err("clk_get_by_name(tx) failed: %d\n", ret); - goto err_probe; - } - - /* Get ETH_CLK clocks (optional) */ - ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); - if (ret) - pr_warn("No phy clock provided %d", ret); - - debug("%s: OK\n", __func__); - return 0; - -err_probe: - - debug("%s: returns %d\n", __func__, ret); - return ret; -} - static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev) { return PHY_INTERFACE_MODE_MII; @@ -1484,12 +1354,6 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) return 0; } -static int eqos_remove_resources_stm32(struct udevice *dev) -{ - debug("%s(dev=%p):\n", __func__, dev); - return 0; -} - static int eqos_probe(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1633,35 +1497,6 @@ static const struct eqos_config __maybe_unused eqos_tegra186_config = { .ops = &eqos_tegra186_ops }; -static struct eqos_ops eqos_stm32_ops = { - .eqos_inval_desc = eqos_inval_desc_generic, - .eqos_flush_desc = eqos_flush_desc_generic, - .eqos_inval_buffer = eqos_inval_buffer_generic, - .eqos_flush_buffer = eqos_flush_buffer_generic, - .eqos_probe_resources = eqos_probe_resources_stm32, - .eqos_remove_resources = eqos_remove_resources_stm32, - .eqos_stop_resets = eqos_null_ops, - .eqos_start_resets = eqos_null_ops, - .eqos_stop_clks = eqos_stop_clks_stm32, - .eqos_start_clks = eqos_start_clks_stm32, - .eqos_calibrate_pads = eqos_null_ops, - .eqos_disable_calibration = eqos_null_ops, - .eqos_set_tx_clk_speed = eqos_null_ops, - .eqos_get_enetaddr = eqos_null_ops, - .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 -}; - -static const struct eqos_config __maybe_unused eqos_stm32_config = { - .reg_access_always_ok = false, - .mdio_wait = 10000, - .swr_wait = 50, - .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, - .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, - .axi_bus_width = EQOS_AXI_WIDTH_64, - .interface = dev_read_phy_mode, - .ops = &eqos_stm32_ops -}; - static const struct udevice_id eqos_ids[] = { #if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186) { @@ -1671,8 +1506,12 @@ static const struct udevice_id eqos_ids[] = { #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32) { + .compatible = "st,stm32mp13-dwmac", + .data = (ulong)&eqos_stm32mp13_config + }, + { .compatible = "st,stm32mp1-dwmac", - .data = (ulong)&eqos_stm32_config + .data = (ulong)&eqos_stm32mp15_config }, #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX) diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index e3222e1e17e..8b3d0d464d3 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -290,4 +290,6 @@ int eqos_null_ops(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; extern struct eqos_config eqos_qcom_config; +extern struct eqos_config eqos_stm32mp13_config; +extern struct eqos_config eqos_stm32mp15_config; extern struct eqos_config eqos_jh7110_config; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c new file mode 100644 index 00000000000..fbc08bba1d6 --- /dev/null +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Marek Vasut <marex@denx.de> + * + * This is code moved from drivers/net/dwc_eth_qos.c , which is: + * Copyright (c) 2016, NVIDIA CORPORATION. + */ + +#include <asm/cache.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <eth_phy.h> +#include <log.h> +#include <malloc.h> +#include <memalign.h> +#include <miiphy.h> +#include <net.h> +#include <netdev.h> +#include <phy.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <wait_bit.h> +#include <linux/bitfield.h> +#include <linux/delay.h> + +#include "dwc_eth_qos.h" + +/* SYSCFG registers */ +#define SYSCFG_PMCSETR 0x04 +#define SYSCFG_PMCCLRR_MP13 0x08 +#define SYSCFG_PMCCLRR_MP15 0x44 + +#define SYSCFG_PMCSETR_ETH1_MASK GENMASK(23, 16) +#define SYSCFG_PMCSETR_ETH2_MASK GENMASK(31, 24) + +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) + +/* STM32MP15xx specific bit */ +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) + +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0x0 +#define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1 +#define SYSCFG_PMCSETR_ETH_SEL_RMII 0x4 + +static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) +{ + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); + + if (!CONFIG_IS_ENABLED(CLK)) + return 0; + + return clk_get_rate(&eqos->clk_master_bus); +} + +static int eqos_start_clks_stm32(struct udevice *dev) +{ + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); + int ret; + + if (!CONFIG_IS_ENABLED(CLK)) + return 0; + + dev_dbg(dev, "%s:\n", __func__); + + ret = clk_enable(&eqos->clk_master_bus); + if (ret < 0) { + dev_err(dev, "clk_enable(clk_master_bus) failed: %d\n", ret); + goto err; + } + + ret = clk_enable(&eqos->clk_rx); + if (ret < 0) { + dev_err(dev, "clk_enable(clk_rx) failed: %d\n", ret); + goto err_disable_clk_master_bus; + } + + ret = clk_enable(&eqos->clk_tx); + if (ret < 0) { + dev_err(dev, "clk_enable(clk_tx) failed: %d\n", ret); + goto err_disable_clk_rx; + } + + if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { + ret = clk_enable(&eqos->clk_ck); + if (ret < 0) { + dev_err(dev, "clk_enable(clk_ck) failed: %d\n", ret); + goto err_disable_clk_tx; + } + eqos->clk_ck_enabled = true; + } + + dev_dbg(dev, "%s: OK\n", __func__); + return 0; + +err_disable_clk_tx: + clk_disable(&eqos->clk_tx); +err_disable_clk_rx: + clk_disable(&eqos->clk_rx); +err_disable_clk_master_bus: + clk_disable(&eqos->clk_master_bus); +err: + dev_dbg(dev, "%s: FAILED: %d\n", __func__, ret); + + return ret; +} + +static int eqos_stop_clks_stm32(struct udevice *dev) +{ + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); + + if (!CONFIG_IS_ENABLED(CLK)) + return 0; + + dev_dbg(dev, "%s:\n", __func__); + + clk_disable(&eqos->clk_tx); + clk_disable(&eqos->clk_rx); + clk_disable(&eqos->clk_master_bus); + + dev_dbg(dev, "%s: OK\n", __func__); + + return 0; +} + +static int eqos_probe_syscfg_stm32(struct udevice *dev, + phy_interface_t interface_type) +{ + /* Ethernet 50MHz RMII clock selection. */ + const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel"); + /* SoC is STM32MP13xx with two ethernet MACs */ + const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac"); + /* Gigabit Ethernet 125MHz clock selection. */ + const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel"); + /* Ethernet clock source is RCC. */ + const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk"); + struct regmap *regmap; + u32 regmap_mask; + u32 value; + + regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon"); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2, + SYSCFG_PMCSETR_ETH1_MASK); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n"); + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, + SYSCFG_PMCSETR_ETH_SEL_GMII_MII); + /* + * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. + * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and + * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx + * supports only MII, ETH_SELMII is not present. + */ + if (!is_mp13) /* Select MII mode on STM32MP15xx */ + value |= SYSCFG_PMCSETR_ETH_SELMII; + break; + case PHY_INTERFACE_MODE_GMII: /* STM32MP15xx only */ + dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n"); + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, + SYSCFG_PMCSETR_ETH_SEL_GMII_MII); + /* + * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC, + * otherwise use external clock from IO pin (requires matching + * GPIO block AF setting of that pin). + */ + if (eth_clk_sel || ext_phyclk) + value |= SYSCFG_PMCSETR_ETH_CLK_SEL; + break; + case PHY_INTERFACE_MODE_RMII: + dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n"); + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, + SYSCFG_PMCSETR_ETH_SEL_RMII); + /* + * If eth_ref_clk_sel is set, use internal clock from RCC, + * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK + * IO pin (requires matching GPIO block AF setting of that + * pin). + */ + if (eth_ref_clk_sel || ext_phyclk) + value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n"); + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, + SYSCFG_PMCSETR_ETH_SEL_RGMII); + /* + * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC, + * otherwise use external clock from ETHx_CLK125 pin (requires + * matching GPIO block AF setting of that pin). + */ + if (eth_clk_sel || ext_phyclk) + value |= SYSCFG_PMCSETR_ETH_CLK_SEL; + break; + default: + dev_dbg(dev, "Do not manage %d interface\n", + interface_type); + /* Do not manage others interfaces */ + return -EINVAL; + } + + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ + value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK); + + /* Update PMCCLRR (clear register) */ + regmap_write(regmap, is_mp13 ? + SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15, + regmap_mask); + + return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value); +} + +static int eqos_probe_resources_stm32(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + phy_interface_t interface; + int ret; + + dev_dbg(dev, "%s:\n", __func__); + + interface = eqos->config->interface(dev); + + if (interface == PHY_INTERFACE_MODE_NA) { + dev_err(dev, "Invalid PHY interface\n"); + return -EINVAL; + } + + ret = eqos_probe_syscfg_stm32(dev, interface); + if (ret) + return -EINVAL; + + ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); + if (ret) { + dev_err(dev, "clk_get_by_name(master_bus) failed: %d\n", ret); + goto err_probe; + } + + ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); + if (ret) { + dev_err(dev, "clk_get_by_name(rx) failed: %d\n", ret); + goto err_probe; + } + + ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); + if (ret) { + dev_err(dev, "clk_get_by_name(tx) failed: %d\n", ret); + goto err_probe; + } + + /* Get ETH_CLK clocks (optional) */ + ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); + if (ret) + dev_warn(dev, "No phy clock provided %d\n", ret); + + dev_dbg(dev, "%s: OK\n", __func__); + + return 0; + +err_probe: + + dev_dbg(dev, "%s: returns %d\n", __func__, ret); + + return ret; +} + +static int eqos_remove_resources_stm32(struct udevice *dev) +{ + dev_dbg(dev, "%s:\n", __func__); + + return 0; +} + +static struct eqos_ops eqos_stm32_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_resources_stm32, + .eqos_remove_resources = eqos_remove_resources_stm32, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_null_ops, + .eqos_stop_clks = eqos_stop_clks_stm32, + .eqos_start_clks = eqos_start_clks_stm32, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_null_ops, + .eqos_get_enetaddr = eqos_null_ops, + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 +}; + +struct eqos_config __maybe_unused eqos_stm32mp13_config = { + .reg_access_always_ok = false, + .mdio_wait = 10000, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_32, + .interface = dev_read_phy_mode, + .ops = &eqos_stm32_ops +}; + +struct eqos_config __maybe_unused eqos_stm32mp15_config = { + .reg_access_always_ok = false, + .mdio_wait = 10000, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &eqos_stm32_ops +}; diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c1bae3f68bd..51f835adabc 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -19,7 +19,7 @@ #include <asm/arch-rockchip/grf_px30.h> #include <asm/arch-rockchip/grf_rk322x.h> #include <asm/arch-rockchip/grf_rk3288.h> -#include <asm/arch-rk3308/grf_rk3308.h> +#include <asm/arch-rockchip/grf_rk3308.h> #include <asm/arch-rockchip/grf_rk3328.h> #include <asm/arch-rockchip/grf_rk3368.h> #include <asm/arch-rockchip/grf_rk3399.h> @@ -739,7 +739,7 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3228_gmac_ops }, { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, - { .compatible = "rockchip,rk3308-mac", + { .compatible = "rockchip,rk3308-gmac", .data = (ulong)&rk3308_gmac_ops }, { .compatible = "rockchip,rk3328-gmac", .data = (ulong)&rk3328_gmac_ops }, diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c index a2ee228224b..fdb463710ba 100644 --- a/drivers/pci/pcie_dw_imx.c +++ b/drivers/pci/pcie_dw_imx.c @@ -56,6 +56,18 @@ struct pcie_dw_imx { struct udevice *vpcie; }; +struct pcie_chip_info { + const char *gpr; +}; + +static const struct pcie_chip_info imx8mm_chip_info = { + .gpr = "fsl,imx8mm-iomuxc-gpr", +}; + +static const struct pcie_chip_info imx8mp_chip_info = { + .gpr = "fsl,imx8mp-iomuxc-gpr", +}; + static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed) { dw_pcie_dbi_write_enable(&priv->dw, true); @@ -242,6 +254,7 @@ static int pcie_dw_imx_remove(struct udevice *dev) static int pcie_dw_imx_of_to_plat(struct udevice *dev) { + struct pcie_chip_info *info = (void *)dev_get_driver_data(dev); struct pcie_dw_imx *priv = dev_get_priv(dev); ofnode gpr; int ret; @@ -287,7 +300,7 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev) goto err_phy; } - gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr"); + gpr = ofnode_by_compatible(ofnode_null(), info->gpr); if (ofnode_equal(gpr, ofnode_null())) { dev_err(dev, "unable to find GPR node\n"); ret = -ENODEV; @@ -322,7 +335,8 @@ static const struct dm_pci_ops pcie_dw_imx_ops = { }; static const struct udevice_id pcie_dw_imx_ids[] = { - { .compatible = "fsl,imx8mp-pcie" }, + { .compatible = "fsl,imx8mm-pcie", .data = (ulong)&imx8mm_chip_info, }, + { .compatible = "fsl,imx8mp-pcie", .data = (ulong)&imx8mp_chip_info, }, { } }; diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index b9fe608c279..3aae1813352 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -27,6 +27,14 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2 High-Speed PHY driver. This driver supports the Hi-Speed PHY which is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. +config PHY_QCOM_SNPS_EUSB2 + tristate "Qualcomm Synopsys eUSB2 High-Speed PHY" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare eUSB2 + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 5f4db4a5378..a5153061dfb 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o +obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c b/drivers/phy/qcom/phy-qcom-snps-eusb2.c new file mode 100644 index 00000000000..b2655ac007c --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2024, Linaro Limited + * + * Based on the Linux phy-qcom-snps-eusb2.c driver + */ + +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <generic-phy.h> +#include <malloc.h> +#include <reset.h> + +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) +#define PLL_REF_DIV_VAL (0x0) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0 BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define USB_PHY_CFG_CTRL_7 (0x74) + +#define USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASS BIT(7) + +#define USB_PHY_CFG_CTRL_10 (0x80) + +#define USB_PHY_CFG0 (0x94) +#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define CMN_CTRL_OVERRIDE_EN BIT(1) + +#define UTMI_PHY_CMN_CTRL0 (0x98) +#define TESTBURNIN BIT(6) + +#define USB_PHY_FSEL_SEL (0xb8) +#define FSEL_SEL BIT(0) + +#define USB_PHY_APB_ACCESS_CMD (0x130) +#define RW_ACCESS BIT(0) +#define APB_START_CMD BIT(1) +#define APB_LOGIC_RESET BIT(2) + +#define USB_PHY_APB_ACCESS_STATUS (0x134) +#define ACCESS_DONE BIT(0) +#define TIMED_OUT BIT(1) +#define ACCESS_ERROR BIT(2) +#define ACCESS_IN_PROGRESS BIT(3) + +#define USB_PHY_APB_ADDRESS (0x138) +#define APB_REG_ADDR_MASK GENMASK(7, 0) + +#define USB_PHY_APB_WRDATA_LSB (0x13c) +#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) + +#define USB_PHY_APB_WRDATA_MSB (0x140) +#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) + +#define USB_PHY_APB_RDDATA_LSB (0x144) +#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) + +#define USB_PHY_APB_RDDATA_MSB (0x148) +#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) + +struct qcom_snps_eusb2_phy_priv { + void __iomem *base; + struct clk *ref_clk; + struct reset_ctl_bulk resets; +}; + +static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2) +{ + /* default parameters: tx pre-emphasis */ + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_PREEMP_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); + + /* tx rise/fall time */ + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RISE_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); + + /* source impedance adjustment */ + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RES_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); + + /* dc voltage level adjustement */ + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); + + /* transmitter HS crossover adjustement */ + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_XV_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); +} + +static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2) +{ + unsigned long ref_clk_freq = clk_get_rate(qcom_snps_eusb2->ref_clk); + + switch (ref_clk_freq) { + case 19200000: + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_19_2_MHZ_VAL); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_19_2_MHZ_VAL); + break; + + case 38400000: + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_38_4_MHZ_VAL); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_38_4_MHZ_VAL); + break; + + default: + printf("%s: unsupported ref_clk_freq:%lu\n", __func__, ref_clk_freq); + return -EINVAL; + } + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); + + return 0; +} + +static int qcom_snps_eusb2_usb_init(struct phy *phy) +{ + struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(phy->dev); + int ret; + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG0, + CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_UTMI_CTRL5, POR, POR); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0, + PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_APB_ACCESS_CMD, + APB_LOGIC_RESET, APB_LOGIC_RESET); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_FSEL_SEL, + FSEL_SEL, FSEL_SEL); + + /* update ref_clk related registers */ + ret = qcom_eusb2_ref_clk_init(qcom_snps_eusb2); + if (ret) + return ret; + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_1, + PHY_CFG_PLL_CPBIAS_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_INT_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_GMP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_PROP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_6, + PHY_CFG_PLL_VCO_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL2, + VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); + + /* set default parameters */ + qcom_eusb2_default_parameters(qcom_snps_eusb2); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ_SEL, SIDDQ_SEL); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ, 0); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_UTMI_CTRL5, POR, 0); + + qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + return 0; +} + +static int qcom_snps_eusb2_phy_power_on(struct phy *phy) +{ + struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(phy->dev); + int ret; + + /* TODO Repeater */ + + clk_prepare_enable(qcom_snps_eusb2->ref_clk); + + ret = reset_deassert_bulk(&qcom_snps_eusb2->resets); + if (ret) + return ret; + + ret = qcom_snps_eusb2_usb_init(phy); + if (ret) + return ret; + + return 0; +} + +static int qcom_snps_eusb2_phy_power_off(struct phy *phy) +{ + struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(phy->dev); + + reset_assert_bulk(&qcom_snps_eusb2->resets); + clk_disable_unprepare(qcom_snps_eusb2->ref_clk); + + return 0; +} + +static int qcom_snps_eusb2_phy_probe(struct udevice *dev) +{ + struct qcom_snps_eusb2_phy_priv *qcom_snps_eusb2 = dev_get_priv(dev); + int ret; + + qcom_snps_eusb2->base = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qcom_snps_eusb2->base)) + return PTR_ERR(qcom_snps_eusb2->base); + + qcom_snps_eusb2->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(qcom_snps_eusb2->ref_clk)) { + printf("%s: failed to get ref clk %d\n", __func__, ret); + return PTR_ERR(qcom_snps_eusb2->ref_clk); + } + + ret = reset_get_bulk(dev, &qcom_snps_eusb2->resets); + if (ret < 0) { + printf("failed to get resets, ret = %d\n", ret); + return ret; + } + + return 0; +} + +static struct phy_ops qcom_snps_eusb2_phy_ops = { + .power_on = qcom_snps_eusb2_phy_power_on, + .power_off = qcom_snps_eusb2_phy_power_off, +}; + +static const struct udevice_id qcom_snps_eusb2_phy_ids[] = { + { + .compatible = "qcom,sm8550-snps-eusb2-phy", + }, + {} +}; + +U_BOOT_DRIVER(qcom_usb_qcom_snps_eusb2) = { + .name = "qcom-snps-eusb2-hsphy", + .id = UCLASS_PHY, + .of_match = qcom_snps_eusb2_phy_ids, + .ops = &qcom_snps_eusb2_phy_ops, + .probe = qcom_snps_eusb2_phy_probe, + .priv_auto = sizeof(struct qcom_snps_eusb2_phy_priv), +}; diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c index a1675b664e4..04f0f0e7817 100644 --- a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c @@ -6,8 +6,6 @@ * Based on Linux driver */ -#include <clk.h> -#include <clk-uclass.h> #include <dm.h> #include <dm/device_compat.h> #include <dm/devres.h> @@ -17,7 +15,6 @@ #include <asm/io.h> #include <linux/bitops.h> -#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/iopoll.h> @@ -62,7 +59,6 @@ struct qcom_snps_hsphy { void __iomem *base; - struct clk_bulk clks; struct reset_ctl_bulk resets; }; @@ -143,8 +139,6 @@ static int qcom_snps_hsphy_power_on(struct phy *phy) struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); int ret; - clk_enable_bulk(&priv->clks); - ret = reset_deassert_bulk(&priv->resets); if (ret) return ret; @@ -161,7 +155,6 @@ static int qcom_snps_hsphy_power_off(struct phy *phy) struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); reset_assert_bulk(&priv->resets); - clk_disable_bulk(&priv->clks); return 0; } @@ -175,19 +168,12 @@ static int qcom_snps_hsphy_phy_probe(struct udevice *dev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - ret = clk_get_bulk(dev, &priv->clks); - if (ret < 0 && ret != -ENOENT) { - printf("%s: Failed to get clocks %d\n", __func__, ret); - return ret; - } - ret = reset_get_bulk(dev, &priv->resets); if (ret < 0) { printf("failed to get resets, ret = %d\n", ret); return ret; } - clk_enable_bulk(&priv->clks); reset_deassert_bulk(&priv->resets); return 0; diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 0247d93ab40..80128335d52 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -12,6 +12,13 @@ config PHY_ROCKCHIP_INNO_DSIDPHY help Support for Rockchip MIPI DPHY with Innosilicon IP block. +config PHY_ROCKCHIP_INNO_HDMI + bool "Rockchip INNO HDMI PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip Innosilicon HDMI PHY. + config PHY_ROCKCHIP_INNO_USB2 bool "Rockchip INNO USB2PHY Driver" depends on ARCH_ROCKCHIP diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 7fdbd107976..04200174254 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -3,6 +3,7 @@ # Copyright (C) 2020 Amarula Solutions(India) # +obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c new file mode 100644 index 00000000000..3bb1a254ffb --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -0,0 +1,885 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip Innosilicon HDMI PHY + * + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <div64.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <generic-phy.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/iopoll.h> + +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) + +/* REG: 0x01 */ +#define RK3328_BYPASS_RXSENSE_EN BIT(2) +#define RK3328_BYPASS_POWERON_EN BIT(1) +#define RK3328_BYPASS_PLLPD_EN BIT(0) +/* REG: 0x02 */ +#define RK3328_INT_POL_HIGH BIT(7) +#define RK3328_BYPASS_PDATA_EN BIT(4) +#define RK3328_PDATA_EN BIT(0) +/* REG:0x05 */ +#define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4) +#define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0) +/* REG:0x07 */ +#define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4) +#define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0) +/* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */ +#define RK3328_INT_AGND_LOW_PULSE_LOCKED BIT(3) +#define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED BIT(2) +#define RK3328_INT_VSS_AGND_ESD_DET BIT(1) +#define RK3328_INT_AGND_VSS_ESD_DET BIT(0) +/* REG: 0xa0 */ +#define RK3328_PCLK_VCO_DIV_5_MASK BIT(1) +#define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1) +#define RK3328_PRE_PLL_POWER_DOWN BIT(0) +/* REG: 0xa1 */ +#define RK3328_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0) +#define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0) +/* REG: 0xa2 */ +/* unset means center spread */ +#define RK3328_SPREAD_SPECTRUM_MOD_DOWN BIT(7) +#define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) +#define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4) +#define RK3328_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0) +/* REG: 0xa3 */ +#define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) +/* REG: 0xa4*/ +#define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0) +#define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0) +#define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2) +#define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2) +#define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4) +#define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4) +/* REG: 0xa5 */ +#define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT 5 +#define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) +#define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) +/* REG: 0xa6 */ +#define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT 5 +#define RK3328_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) +#define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) +/* REG: 0xa9 */ +#define RK3328_PRE_PLL_LOCK_STATUS BIT(0) +/* REG: 0xaa */ +#define RK3328_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) +#define RK3328_POST_PLL_REFCLK_SEL_TMDS BIT(1) +#define RK3328_POST_PLL_POWER_DOWN BIT(0) +/* REG:0xab */ +#define RK3328_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) +#define RK3328_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0) +/* REG: 0xac */ +#define RK3328_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) +/* REG: 0xad */ +#define RK3328_POST_PLL_POST_DIV_MASK GENMASK(1, 0) +#define RK3328_POST_PLL_POST_DIV_2 0x0 +#define RK3328_POST_PLL_POST_DIV_4 0x1 +#define RK3328_POST_PLL_POST_DIV_8 0x3 +/* REG: 0xaf */ +#define RK3328_POST_PLL_LOCK_STATUS BIT(0) +/* REG: 0xb0 */ +#define RK3328_BANDGAP_ENABLE BIT(2) +/* REG: 0xb2 */ +#define RK3328_TMDS_CLK_DRIVER_EN BIT(3) +#define RK3328_TMDS_D2_DRIVER_EN BIT(2) +#define RK3328_TMDS_D1_DRIVER_EN BIT(1) +#define RK3328_TMDS_D0_DRIVER_EN BIT(0) +#define RK3328_TMDS_DRIVER_ENABLE (RK3328_TMDS_CLK_DRIVER_EN | \ + RK3328_TMDS_D2_DRIVER_EN | \ + RK3328_TMDS_D1_DRIVER_EN | \ + RK3328_TMDS_D0_DRIVER_EN) +/* REG:0xc5 */ +#define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7) +#define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0) +/* REG:0xc6 */ +#define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0) +/* REG:0xc7 */ +#define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1) +#define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1) +#define RK3328_TERM_RESISTOR_75 UPDATE(2, 2, 1) +#define RK3328_TERM_RESISTOR_100 UPDATE(3, 2, 1) +/* REG 0xc8 - 0xcb */ +#define RK3328_ESD_DETECT_MASK GENMASK(7, 6) +#define RK3328_ESD_DETECT_340MV (0x0 << 6) +#define RK3328_ESD_DETECT_280MV (0x1 << 6) +#define RK3328_ESD_DETECT_260MV (0x2 << 6) +#define RK3328_ESD_DETECT_240MV (0x3 << 6) +/* resistors can be used in parallel */ +#define RK3328_TMDS_TERM_RESIST_MASK GENMASK(5, 0) +#define RK3328_TMDS_TERM_RESIST_75 BIT(5) +#define RK3328_TMDS_TERM_RESIST_150 BIT(4) +#define RK3328_TMDS_TERM_RESIST_300 BIT(3) +#define RK3328_TMDS_TERM_RESIST_600 BIT(2) +#define RK3328_TMDS_TERM_RESIST_1000 BIT(1) +#define RK3328_TMDS_TERM_RESIST_2000 BIT(0) +/* REG: 0xd1 */ +#define RK3328_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0) +/* REG: 0xd2 */ +#define RK3328_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0) +/* REG: 0xd3 */ +#define RK3328_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0) + +struct phy_config { + unsigned long tmdsclock; + u8 regs[14]; +}; + +struct pre_pll_config { + unsigned long pixclock; + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 tmds_div_a; + u8 tmds_div_b; + u8 tmds_div_c; + u8 pclk_div_a; + u8 pclk_div_b; + u8 pclk_div_c; + u8 pclk_div_d; + u8 vco_div_5_en; + u32 fracdiv; +}; + +struct post_pll_config { + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 postdiv; + u8 version; +}; + +struct inno_hdmi_phy_plat_ops { + void (*init)(struct phy *phy); + int (*power_on)(struct phy *phy, const struct post_pll_config *cfg, + const struct phy_config *phy_cfg); + void (*power_off)(struct phy *phy); + void (*clk_enable)(struct phy *phy); + void (*clk_disable)(struct phy *phy); + unsigned long (*clk_recalc_rate)(struct phy *phy, + unsigned long parent_rate); + long (*clk_round_rate)(struct phy *phy, unsigned long rate); + int (*clk_set_rate)(struct phy *phy, unsigned long rate, + unsigned long parent_rate); +}; + +enum inno_hdmi_phy_type { + INNO_HDMI_PHY_RK3328, +}; + +struct inno_hdmi_phy_data { + enum inno_hdmi_phy_type phy_type; + const struct inno_hdmi_phy_plat_ops *plat_ops; + const struct phy_config *phy_cfg_table; +}; + +struct inno_hdmi_phy { + struct udevice *dev; + ofnode node; + void *regs; + + struct clk refoclk; + struct clk sysclk; + unsigned long tmdsclock; + unsigned long pixclock; + u32 bus_width; + struct phy_config *phy_cfg; + const struct inno_hdmi_phy_data *data; +}; + +static const struct pre_pll_config pre_pll_cfg_table[] = { + { 25175000, 25175000, 3, 125, 3, 1, 1, 1, 3, 3, 4, 0, 0xe00000}, + { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f}, + { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 27000000, 33750000, 1, 45, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 31500000, 39375000, 1, 105, 1, 3, 3, 10, 0, 3, 4, 0, 0x0}, + { 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 33750000, 42187500, 1, 169, 2, 3, 3, 15, 0, 3, 4, 0, 0x0}, + { 35500000, 35500000, 1, 71, 2, 2, 2, 6, 0, 3, 4, 0, 0x0}, + { 35500000, 44375000, 1, 74, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, + { 36000000, 36000000, 1, 36, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + { 36000000, 45000000, 1, 45, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + { 40000000, 40000000, 1, 40, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + { 40000000, 50000000, 1, 50, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + { 49500000, 49500000, 1, 66, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 49500000, 61875000, 1, 165, 1, 3, 3, 10, 0, 3, 4, 0, 0x0}, + { 50000000, 50000000, 1, 50, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + { 50000000, 62500000, 1, 125, 2, 2, 2, 15, 0, 2, 2, 0, 0x0}, + { 54000000, 54000000, 1, 36, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + { 54000000, 67500000, 1, 45, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + { 56250000, 56250000, 1, 75, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 56250000, 70312500, 1, 117, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, + { 59341000, 59341000, 1, 118, 2, 2, 2, 6, 0, 3, 4, 0, 0xae978d}, + { 59341000, 74176250, 2, 148, 2, 1, 1, 15, 0, 1, 1, 0, 0x5a3d70}, + { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0x0}, + { 59400000, 74250000, 1, 99, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 65000000, 65000000, 1, 65, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 68250000, 68250000, 1, 91, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 68250000, 85312500, 1, 142, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, + { 71000000, 71000000, 1, 71, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 72000000, 72000000, 1, 36, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, + { 72000000, 90000000, 1, 60, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + { 73250000, 73250000, 3, 293, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 73250000, 91562500, 1, 61, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + { 74176000, 74176000, 1, 37, 2, 0, 0, 1, 1, 2, 2, 0, 0x16872b}, + { 74176000, 92720000, 2, 185, 2, 1, 1, 15, 0, 1, 1, 0, 0x70a3d7}, + { 74250000, 74250000, 1, 99, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 74250000, 92812500, 4, 495, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 75000000, 75000000, 1, 50, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + { 75000000, 93750000, 1, 125, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 78750000, 78750000, 1, 105, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 78750000, 98437500, 1, 164, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, + { 79500000, 79500000, 1, 53, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + { 79500000, 99375000, 1, 199, 2, 2, 2, 15, 0, 2, 2, 0, 0x0}, + { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + { 83500000, 104375000, 1, 104, 2, 1, 1, 15, 0, 1, 1, 0, 0x600000}, + { 85500000, 85500000, 1, 57, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + { 85500000, 106875000, 1, 178, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, + { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 85750000, 107187500, 1, 143, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 88750000, 110937500, 1, 110, 2, 1, 1, 15, 0, 1, 1, 0, 0xf00000}, + { 94500000, 94500000, 1, 63, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + { 94500000, 118125000, 1, 197, 3, 1, 1, 25, 0, 1, 1, 0, 0x0}, + {101000000, 101000000, 1, 101, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + {101000000, 126250000, 1, 42, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {102250000, 102250000, 4, 409, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + {102250000, 127812500, 1, 128, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + {106500000, 106500000, 1, 71, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {106500000, 133125000, 1, 133, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {108000000, 135000000, 1, 45, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {115500000, 115500000, 1, 77, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {115500000, 144375000, 1, 48, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {117500000, 117500000, 2, 235, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + {117500000, 146875000, 1, 49, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {119000000, 119000000, 1, 119, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + {119000000, 148750000, 3, 148, 0, 1, 1, 1, 3, 1, 1, 0, 0xc00000}, + {121750000, 121750000, 4, 487, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + {121750000, 152187500, 1, 203, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, + {122500000, 122500000, 2, 245, 2, 1, 1, 1, 1, 3, 4, 0, 0x0}, + {122500000, 153125000, 1, 51, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {135000000, 168750000, 1, 169, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + {136750000, 136750000, 1, 68, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, + {136750000, 170937500, 1, 113, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f}, + {140250000, 140250000, 2, 187, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {140250000, 175312500, 1, 117, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {146250000, 146250000, 2, 195, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {146250000, 182812500, 1, 61, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {148250000, 148250000, 3, 222, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, + {148250000, 185312500, 1, 123, 0, 2, 2, 1, 3, 2, 2, 0, 0x8aaab0}, + {148352000, 148352000, 2, 148, 2, 0, 0, 1, 1, 2, 2, 0, 0x5a1cac}, + {148352000, 185440000, 3, 185, 0, 1, 1, 1, 3, 1, 1, 0, 0x70a3d7}, + {148500000, 148500000, 1, 99, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {154000000, 154000000, 1, 77, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, + {154000000, 192500000, 1, 64, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {156000000, 195000000, 1, 65, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {156750000, 156750000, 2, 209, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {156750000, 195937500, 1, 196, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + {157000000, 157000000, 2, 157, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, + {157000000, 196250000, 1, 131, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {157500000, 157500000, 1, 105, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {157500000, 196875000, 1, 197, 2, 1, 1, 15, 0, 1, 1, 0, 0x0}, + {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {162000000, 202500000, 2, 135, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {175500000, 175500000, 1, 117, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {175500000, 219375000, 1, 73, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {179500000, 179500000, 3, 359, 0, 2, 2, 1, 0, 3, 4, 0, 0x0}, + {179500000, 224375000, 1, 75, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {182750000, 182750000, 1, 91, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, + {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0}, + {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0}, + {187000000, 187000000, 2, 187, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, + {187000000, 233750000, 1, 39, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, + {187250000, 187250000, 3, 280, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000}, + {187250000, 234062500, 1, 156, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0}, + {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {189000000, 236250000, 1, 79, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {193250000, 193250000, 3, 289, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000}, + {193250000, 241562500, 1, 161, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0}, + {202500000, 202500000, 2, 135, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {202500000, 253125000, 1, 169, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {204750000, 204750000, 4, 273, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {204750000, 255937500, 1, 171, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {208000000, 208000000, 1, 104, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, + {208000000, 260000000, 1, 173, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {214750000, 214750000, 1, 107, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000}, + {214750000, 268437500, 1, 178, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f}, + {218250000, 218250000, 4, 291, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {218250000, 272812500, 1, 91, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {229500000, 229500000, 2, 153, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {229500000, 286875000, 1, 191, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {234000000, 234000000, 1, 39, 0, 0, 0, 1, 0, 1, 1, 0, 0x0}, + {234000000, 292500000, 1, 195, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {241500000, 241500000, 2, 161, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {241500000, 301875000, 1, 201, 0, 2, 2, 1, 3, 2, 2, 0, 0x0}, + {245250000, 245250000, 4, 327, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {245250000, 306562500, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, + {245500000, 245500000, 4, 491, 2, 0, 0, 1, 1, 2, 2, 0, 0x0}, + {245500000, 306875000, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, + {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {261000000, 326250000, 1, 109, 0, 1, 1, 1, 3, 1, 1, 0, 0x0}, + {268250000, 268250000, 9, 402, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000}, + {268250000, 335312500, 1, 111, 0, 1, 1, 1, 3, 1, 1, 0, 0xc5554f}, + {268500000, 268500000, 2, 179, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {268500000, 335625000, 1, 56, 0, 0, 0, 1, 3, 0, 0, 1, 0x0}, + {281250000, 281250000, 4, 375, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {281250000, 351562500, 1, 117, 0, 3, 1, 1, 3, 1, 1, 0, 0x0}, + {288000000, 288000000, 1, 48, 0, 0, 0, 1, 0, 1, 1, 0, 0x0}, + {288000000, 360000000, 1, 60, 0, 2, 0, 1, 3, 0, 0, 1, 0x0}, + {296703000, 296703000, 1, 49, 0, 0, 0, 1, 0, 1, 1, 0, 0x7353f7}, + {296703000, 370878750, 1, 123, 0, 3, 1, 1, 3, 1, 1, 0, 0xa051eb}, + {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {297000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 1, 1, 0, 0x0}, + {312250000, 312250000, 9, 468, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000}, + {312250000, 390312500, 1, 130, 0, 3, 1, 1, 3, 1, 1, 0, 0x1aaab0}, + {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0x0}, + {317000000, 396250000, 1, 66, 0, 2, 0, 1, 3, 0, 0, 1, 0x0}, + {319750000, 319750000, 3, 159, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000}, + {319750000, 399687500, 3, 199, 0, 2, 0, 1, 3, 0, 0, 1, 0xd80000}, + {333250000, 333250000, 9, 499, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000}, + {333250000, 416562500, 1, 138, 0, 3, 1, 1, 3, 1, 1, 0, 0xdaaab0}, + {348500000, 348500000, 9, 522, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000}, + {348500000, 435625000, 1, 145, 0, 3, 1, 1, 3, 1, 1, 0, 0x35554f}, + {356500000, 356500000, 9, 534, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000}, + {356500000, 445625000, 1, 148, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0}, + {380500000, 380500000, 9, 570, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000}, + {380500000, 475625000, 1, 158, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0}, + {443250000, 443250000, 1, 73, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000}, + {443250000, 554062500, 1, 92, 0, 2, 0, 1, 3, 0, 0, 1, 0x580000}, + {505250000, 505250000, 9, 757, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000}, + {552750000, 552750000, 3, 276, 0, 2, 0, 1, 0, 1, 1, 0, 0x600000}, + {593407000, 296703500, 3, 296, 0, 1, 1, 1, 0, 1, 1, 0, 0xb41893}, + {593407000, 370879375, 4, 494, 0, 3, 1, 1, 3, 0, 0, 1, 0x817e4a}, + {593407000, 593407000, 3, 296, 0, 2, 0, 1, 0, 1, 1, 0, 0xb41893}, + {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 1, 1, 0, 0x0}, + {594000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 0, 0, 1, 0x0}, + {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0}, + { /* sentinel */ } +}; + +static const struct post_pll_config post_pll_cfg_table[] = { + {33750000, 1, 40, 8, 1}, + {33750000, 1, 80, 8, 2}, + {74250000, 1, 40, 8, 1}, + {74250000, 18, 80, 8, 2}, + {148500000, 2, 40, 4, 3}, + {297000000, 4, 40, 2, 3}, + {594000000, 8, 40, 1, 3}, + { /* sentinel */ } +}; + +/* phy tuning values for an undocumented set of registers */ +static const struct phy_config rk3328_phy_cfg[] = { + { 165000000, { + 0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08, + 0x00, 0xac, 0xcc, 0xcc, 0xcc, + }, + }, { + 340000000, { + 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08, + 0x3f, 0xac, 0xcc, 0xcd, 0xdd, + }, + }, { + 594000000, { + 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08, + 0x00, 0xac, 0xcc, 0xcc, 0xcc, + }, + }, { /* sentinel */ }, +}; + +static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) +{ + writel(val, inno->regs + (reg * 4)); +} + +static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) +{ + u32 val; + + val = readl(inno->regs + (reg * 4)); + + return val; +} + +static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, + u8 mask, u8 val) +{ + u32 tmp, orig; + + orig = inno_read(inno, reg); + tmp = orig & ~mask; + tmp |= val & mask; + inno_write(inno, reg, tmp); +} + +#define inno_poll(reg, val, cond, sleep_us, timeout_us) \ + readl_poll_sleep_timeout((reg) * 4, val, cond, sleep_us, timeout_us) + +static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, + unsigned long rate) +{ + int bus_width = inno->bus_width; + + switch (bus_width) { + case 4: + case 5: + case 6: + case 10: + case 12: + case 16: + return (u64)rate * bus_width / 8; + default: + return rate; + } +} + +static +unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct phy *phy, + unsigned long parent_rate) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + unsigned long frac; + u8 nd, no_a, no_b, no_d; + u64 vco; + u16 nf; + + nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK; + nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8); + nf |= inno_read(inno, 0xa3); + vco = parent_rate * nf; + + if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) { + frac = inno_read(inno, 0xd3) | + (inno_read(inno, 0xd2) << 8) | + (inno_read(inno, 0xd1) << 16); + vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); + } + + if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) { + do_div(vco, nd * 5); + } else { + no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK; + no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; + no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; + no_b += 2; + no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; + + do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); + } + + inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; + + dev_info(phy->dev, "rate %lu vco %llu\n", inno->pixclock, vco); + + return inno->pixclock; +} + +static long inno_hdmi_phy_rk3328_clk_round_rate(struct phy *phy, + unsigned long rate) +{ + const struct pre_pll_config *cfg = pre_pll_cfg_table; + + rate = (rate / 1000) * 1000; + + for (; cfg->pixclock != 0; cfg++) + if (cfg->pixclock == rate) + break; + + if (cfg->pixclock == 0) + return -EINVAL; + + return cfg->pixclock; +} + +static const +struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno, + unsigned long rate) +{ + const struct pre_pll_config *cfg = pre_pll_cfg_table; + unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); + + for (; cfg->pixclock != 0; cfg++) + if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) + break; + + if (cfg->pixclock == 0) + return ERR_PTR(-EINVAL); + + return cfg; +} + +static int +inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy, + unsigned long rate, + unsigned long parent_rate) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); + const struct pre_pll_config *cfg; + u32 val; + int ret; + + dev_info(phy->dev, "rate %lu tmdsclk %lu\n", rate, tmdsclock); + + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); + + inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, + RK3328_PRE_PLL_POWER_DOWN); + + /* Configure pre-pll */ + inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, + RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); + inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); + + val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE; + if (!cfg->fracdiv) + val |= RK3328_PRE_PLL_FRAC_DIV_DISABLE; + inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); + inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); + inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | + RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b)); + inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | + RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); + inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | + RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | + RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); + inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); + inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); + inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); + + inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); + + /* Wait for Pre-PLL lock */ + ret = inno_poll(0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, + 1000, 10000); + if (ret) { + dev_err(phy->dev, "Pre-PLL locking failed\n"); + return ret; + } + + inno->pixclock = rate; + inno->tmdsclock = tmdsclock; + + return 0; +} + +static void inno_hdmi_phy_rk3328_clk_enable(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + + inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); +} + +static void inno_hdmi_phy_rk3328_clk_disable(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + + inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, + RK3328_PRE_PLL_POWER_DOWN); +} + +static int +inno_hdmi_phy_rk3328_power_on(struct phy *phy, + const struct post_pll_config *cfg, + const struct phy_config *phy_cfg) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + int ret; + u32 v; + + inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0); + inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, + RK3328_POST_PLL_POWER_DOWN); + + inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); + if (cfg->postdiv == 1) { + inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | + RK3328_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | + RK3328_POST_PLL_POWER_DOWN); + } else { + v = (cfg->postdiv / 2) - 1; + v &= RK3328_POST_PLL_POST_DIV_MASK; + inno_write(inno, 0xad, v); + inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | + RK3328_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | + RK3328_POST_PLL_REFCLK_SEL_TMDS | + RK3328_POST_PLL_POWER_DOWN); + } + + for (v = 0; v < 14; v++) + inno_write(inno, 0xb5 + v, phy_cfg->regs[v]); + + /* set ESD detection threshold for TMDS CLK, D2, D1 and D0 */ + for (v = 0; v < 4; v++) + inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK, + RK3328_ESD_DETECT_340MV); + + if (phy_cfg->tmdsclock > 340000000) { + /* Set termination resistor to 100ohm */ + v = clk_get_rate(&inno->sysclk) / 100000; + inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v) + | RK3328_BYPASS_TERM_RESISTOR_CALIB); + inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v)); + inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100); + inno_update_bits(inno, 0xc5, + RK3328_BYPASS_TERM_RESISTOR_CALIB, 0); + } else { + inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB); + + /* clk termination resistor is 50ohm (parallel resistors) */ + if (phy_cfg->tmdsclock > 165000000) + inno_update_bits(inno, 0xc8, + RK3328_TMDS_TERM_RESIST_MASK, + RK3328_TMDS_TERM_RESIST_75 | + RK3328_TMDS_TERM_RESIST_150); + + /* data termination resistor for D2, D1 and D0 is 150ohm */ + for (v = 0; v < 3; v++) + inno_update_bits(inno, 0xc9 + v, + RK3328_TMDS_TERM_RESIST_MASK, + RK3328_TMDS_TERM_RESIST_150); + } + + inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0); + inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, + RK3328_BANDGAP_ENABLE); + inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, + RK3328_TMDS_DRIVER_ENABLE); + + /* Wait for post PLL lock */ + ret = inno_poll(0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS, + 1000, 10000); + if (ret) { + dev_err(phy->dev, "Post-PLL locking failed\n"); + return ret; + } + + if (phy_cfg->tmdsclock > 340000000) + mdelay(100); + + inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN); + + /* Enable PHY IRQ */ + inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET) + | RK3328_INT_TMDS_D2(RK3328_INT_VSS_AGND_ESD_DET)); + inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET) + | RK3328_INT_TMDS_D0(RK3328_INT_VSS_AGND_ESD_DET)); + + return 0; +} + +static void inno_hdmi_phy_rk3328_power_off(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + + inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0); + inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0); + inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, + RK3328_POST_PLL_POWER_DOWN); + + /* Disable PHY IRQ */ + inno_write(inno, 0x05, 0); + inno_write(inno, 0x07, 0); +} + +static void inno_hdmi_phy_rk3328_init(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + const struct inno_hdmi_phy_plat_ops *plat_ops = inno->data->plat_ops; + + /* + * Use phy internal register control + * rxsense/poweron/pllpd/pdataen signal. + */ + inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN | + RK3328_BYPASS_POWERON_EN | + RK3328_BYPASS_PLLPD_EN); + inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN | + RK3328_PDATA_EN); + + /* Disable phy irq */ + inno_write(inno, 0x05, 0); + inno_write(inno, 0x07, 0); + + if (plat_ops->clk_recalc_rate) + plat_ops->clk_recalc_rate(phy, clk_get_rate(&inno->refoclk)); + + if (plat_ops->clk_round_rate) + plat_ops->clk_round_rate(phy, inno->pixclock); +} + +static const struct inno_hdmi_phy_plat_ops rk3328_hdmi_phy_plat_ops = { + .init = inno_hdmi_phy_rk3328_init, + .power_on = inno_hdmi_phy_rk3328_power_on, + .power_off = inno_hdmi_phy_rk3328_power_off, + .clk_enable = inno_hdmi_phy_rk3328_clk_enable, + .clk_disable = inno_hdmi_phy_rk3328_clk_disable, + .clk_recalc_rate = inno_hdmi_phy_rk3328_clk_recalc_rate, + .clk_round_rate = inno_hdmi_phy_rk3328_clk_round_rate, + .clk_set_rate = inno_hdmi_phy_rk3328_clk_set_rate, +}; + +static int inno_hdmi_phy_power_on(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + const struct post_pll_config *cfg = post_pll_cfg_table; + const struct phy_config *phy_cfg = inno->data->phy_cfg_table; + u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); + const struct inno_hdmi_phy_plat_ops *plat_ops = inno->data->plat_ops; + int ret; + + if (!tmdsclock) { + dev_err(phy->dev, "TMDS clock is zero!\n"); + return -EINVAL; + } + + if (!plat_ops->power_on) + return -EINVAL; + + dev_info(phy->dev, "TMDS clock = %d\n", tmdsclock); + + for (; cfg->tmdsclock != ~0UL; cfg++) + if (tmdsclock <= cfg->tmdsclock) + break; + + for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) + if (tmdsclock <= phy_cfg->tmdsclock) + break; + + if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0) + return -EINVAL; + + if (plat_ops->clk_set_rate) { + ret = plat_ops->clk_set_rate(phy, inno->pixclock, 24000000); + if (ret) + return ret; + } + + if (plat_ops->clk_enable) + plat_ops->clk_enable(phy); + + if (plat_ops->power_on) { + ret = plat_ops->power_on(phy, cfg, phy_cfg); + if (ret) { + if (plat_ops->clk_disable) + plat_ops->clk_disable(phy); + return ret; + } + } + + return 0; +} + +static int inno_hdmi_phy_power_off(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + const struct inno_hdmi_phy_plat_ops *plat_ops = inno->data->plat_ops; + + if (!plat_ops->power_off) + return -EINVAL; + + plat_ops->power_off(phy); + + if (plat_ops->clk_disable) + plat_ops->clk_disable(phy); + + inno->tmdsclock = 0; + + return 0; +} + +static int inno_hdmi_phy_init(struct phy *phy) +{ + struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); + + if (inno->data->plat_ops->init) + inno->data->plat_ops->init(phy); + + return 0; +} + +static struct phy_ops inno_hdmi_phy_ops = { + .init = inno_hdmi_phy_init, + .power_on = inno_hdmi_phy_power_on, + .power_off = inno_hdmi_phy_power_off, +}; + +static int inno_hdmi_phy_probe(struct udevice *dev) +{ + struct inno_hdmi_phy *inno = dev_get_priv(dev); + int ret; + + inno->regs = dev_read_addr_ptr(dev); + if (!inno->regs) + return -ENOMEM; + + inno->data = (const struct inno_hdmi_phy_data *)dev_get_driver_data(dev); + if (!inno->data) + return -EINVAL; + + inno->bus_width = 8; + + ret = clk_get_by_name(dev, "refoclk", &inno->refoclk); + if (ret) { + dev_err(dev, "failed to get the refoclk (ret=%d)\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "sysclk", &inno->sysclk); + if (ret) { + dev_err(dev, "failed to get the sysclk (ret=%d)\n", ret); + return ret; + } + + return 0; +} + +static const struct inno_hdmi_phy_data rk3328_inno_hdmi_phy_drv_data = { + .phy_type = INNO_HDMI_PHY_RK3328, + .plat_ops = &rk3328_hdmi_phy_plat_ops, + .phy_cfg_table = rk3328_phy_cfg, +}; + +static const struct udevice_id inno_hdmi_phy_ids[] = { + { + .compatible = "rockchip,rk3328-hdmi-phy", + .data = (ulong)&rk3328_inno_hdmi_phy_drv_data, + }, + { /* sentile */ } +}; + +U_BOOT_DRIVER(inno_hdmi_phy) = { + .name = "inno_hdmi_phy", + .id = UCLASS_PHY, + .of_match = inno_hdmi_phy_ids, + .ops = &inno_hdmi_phy_ops, + .probe = inno_hdmi_phy_probe, + .priv_auto = sizeof(struct inno_hdmi_phy), +}; diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index d392aed2d4d..43f6e020a6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -329,6 +329,22 @@ bind_fail: return ret; } +static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { + { + .reg = 0x100, + .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 1, 0, 2, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0104, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = { { .reg = 0x100, @@ -443,6 +459,10 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { static const struct udevice_id rockchip_usb2phy_ids[] = { { + .compatible = "rockchip,rk3308-usb2phy", + .data = (ulong)&rk3308_phy_cfgs, + }, + { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_usb2phy_cfgs, }, diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2fe63981478..b326fa85140 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -1,4 +1,4 @@ -if ARCH_SNAPDRAGON +if ARCH_SNAPDRAGON || ARCH_IPQ40XX config PINCTRL_QCOM depends on PINCTRL_GENERIC @@ -27,6 +27,13 @@ config PINCTRL_QCOM_IPQ4019 Say Y here to enable support for pinctrl on the IPQ4019 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_QCM2290 + bool "Qualcomm QCM2290 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select PINCTRL_QCOM @@ -41,6 +48,33 @@ config PINCTRL_QCOM_SDM845 Say Y here to enable support for pinctrl on the Snapdragon 845 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_SM6115 + bool "Qualcomm SM6115 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, + as well as the associated GPIO driver. + +config PINCTRL_QCOM_SM8250 + bool "Qualcomm SM8250 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC, + as well as the associated GPIO driver. + +config PINCTRL_QCOM_SM8550 + bool "Qualcomm SM8550 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, + as well as the associated GPIO driver. + +config PINCTRL_QCOM_SM8650 + bool "Qualcomm SM8650 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, + endmenu endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6d9aca6d7b7..4f1d96787be 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -6,5 +6,10 @@ obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o +obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o +obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index a9a00f4b081..b14a8921af4 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,8 @@ static const char * const msm_pinctrl_pins[] = { }; static const struct pinctrl_function msm_pinctrl_functions[] = { + {"gpio", 0}, + {"blsp_uart1", 2}, {"blsp_uart2", 2}, }; diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 44792303133..26ab487857f 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -14,19 +14,291 @@ #define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +enum ipq4019_functions { + qca_mux_gpio, + qca_mux_aud_pin, + qca_mux_audio_pwm, + qca_mux_blsp_i2c0, + qca_mux_blsp_i2c1, + qca_mux_blsp_spi0, + qca_mux_blsp_spi1, + qca_mux_blsp_uart0, + qca_mux_blsp_uart1, + qca_mux_chip_rst, + qca_mux_i2s_rx, + qca_mux_i2s_spdif_in, + qca_mux_i2s_spdif_out, + qca_mux_i2s_td, + qca_mux_i2s_tx, + qca_mux_jtag, + qca_mux_led0, + qca_mux_led1, + qca_mux_led2, + qca_mux_led3, + qca_mux_led4, + qca_mux_led5, + qca_mux_led6, + qca_mux_led7, + qca_mux_led8, + qca_mux_led9, + qca_mux_led10, + qca_mux_led11, + qca_mux_mdc, + qca_mux_mdio, + qca_mux_pcie, + qca_mux_pmu, + qca_mux_prng_rosc, + qca_mux_qpic, + qca_mux_rgmii, + qca_mux_rmii, + qca_mux_sdio, + qca_mux_smart0, + qca_mux_smart1, + qca_mux_smart2, + qca_mux_smart3, + qca_mux_tm, + qca_mux_wifi0, + qca_mux_wifi1, + qca_mux_NA, +}; + +#define QCA_PIN_FUNCTION(fname) \ + [qca_mux_##fname] = {#fname, qca_mux_##fname} + static const struct pinctrl_function msm_pinctrl_functions[] = { - {"gpio", 0}, - {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ - {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */ - {"blsp_uart1", 1}, - {"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */ - {"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */ - {"blsp_spi1", 2}, - {"mdio_0", 1}, /* Only for GPIO6 */ - {"mdio_1", 2}, /* Only for GPIO53 */ - {"mdc_0", 1}, /* Only for GPIO7 */ - {"mdc_1", 2}, /* Only for GPIO52 */ + QCA_PIN_FUNCTION(aud_pin), + QCA_PIN_FUNCTION(audio_pwm), + QCA_PIN_FUNCTION(blsp_i2c0), + QCA_PIN_FUNCTION(blsp_i2c1), + QCA_PIN_FUNCTION(blsp_spi0), + QCA_PIN_FUNCTION(blsp_spi1), + QCA_PIN_FUNCTION(blsp_uart0), + QCA_PIN_FUNCTION(blsp_uart1), + QCA_PIN_FUNCTION(chip_rst), + QCA_PIN_FUNCTION(gpio), + QCA_PIN_FUNCTION(i2s_rx), + QCA_PIN_FUNCTION(i2s_spdif_in), + QCA_PIN_FUNCTION(i2s_spdif_out), + QCA_PIN_FUNCTION(i2s_td), + QCA_PIN_FUNCTION(i2s_tx), + QCA_PIN_FUNCTION(jtag), + QCA_PIN_FUNCTION(led0), + QCA_PIN_FUNCTION(led1), + QCA_PIN_FUNCTION(led2), + QCA_PIN_FUNCTION(led3), + QCA_PIN_FUNCTION(led4), + QCA_PIN_FUNCTION(led5), + QCA_PIN_FUNCTION(led6), + QCA_PIN_FUNCTION(led7), + QCA_PIN_FUNCTION(led8), + QCA_PIN_FUNCTION(led9), + QCA_PIN_FUNCTION(led10), + QCA_PIN_FUNCTION(led11), + QCA_PIN_FUNCTION(mdc), + QCA_PIN_FUNCTION(mdio), + QCA_PIN_FUNCTION(pcie), + QCA_PIN_FUNCTION(pmu), + QCA_PIN_FUNCTION(prng_rosc), + QCA_PIN_FUNCTION(qpic), + QCA_PIN_FUNCTION(rgmii), + QCA_PIN_FUNCTION(rmii), + QCA_PIN_FUNCTION(sdio), + QCA_PIN_FUNCTION(smart0), + QCA_PIN_FUNCTION(smart1), + QCA_PIN_FUNCTION(smart2), + QCA_PIN_FUNCTION(smart3), + QCA_PIN_FUNCTION(tm), + QCA_PIN_FUNCTION(wifi0), + QCA_PIN_FUNCTION(wifi1), }; + +typedef unsigned int msm_pin_function[15]; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ + [id] = { qca_mux_gpio, /* gpio mode */ \ + qca_mux_##f1, \ + qca_mux_##f2, \ + qca_mux_##f3, \ + qca_mux_##f4, \ + qca_mux_##f5, \ + qca_mux_##f6, \ + qca_mux_##f7, \ + qca_mux_##f8, \ + qca_mux_##f9, \ + qca_mux_##f10, \ + qca_mux_##f11, \ + qca_mux_##f12, \ + qca_mux_##f13, \ + qca_mux_##f14 \ + } + +static const msm_pin_function ipq4019_pin_functions[] = { + PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA, + NA, NA, NA), + PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA, + NA, NA, NA, NA, NA), + PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, + NA, NA, NA), + PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, + NA, NA, NA), + PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA, + NA, NA, NA, NA), + PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA, + NA, NA, NA, NA), + PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm, + wifi0, wifi1, NA, NA, NA), + PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA, + NA, NA, tm, NA, NA, NA), + PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx, + NA, NA, NA, NA, NA, tm, NA), + PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx, + NA, NA, NA, NA, NA, tm, NA), + PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA, + tm, NA, NA, NA), + PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out, + i2s_spdif_in, NA, NA, NA, NA, tm, NA), + PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), +}; + static const char *ipq4019_get_function_name(struct udevice *dev, unsigned int selector) { @@ -36,14 +308,22 @@ static const char *ipq4019_get_function_name(struct udevice *dev, static const char *ipq4019_get_pin_name(struct udevice *dev, unsigned int selector) { - snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); return pin_name; } -static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin, +static unsigned int ipq4019_get_function_mux(unsigned int pin, unsigned int selector) { - return msm_pinctrl_functions[selector].val; + unsigned int i; + const msm_pin_function *func = ipq4019_pin_functions + pin; + + for (i = 0; i < 15; i++) + if ((*func)[i] == selector) + return i; + + pr_err("Can't find requested function for pin %u pin\n", pin); + return -EINVAL; } static const struct msm_pinctrl_data ipq4019_data = { @@ -68,4 +348,5 @@ U_BOOT_DRIVER(pinctrl_ipq4019) = { .of_match = msm_pinctrl_ids, .ops = &msm_pinctrl_ops, .bind = msm_pinctrl_bind, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c new file mode 100644 index 00000000000..af969e177d7 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm qcm2290 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup4", 1 }, + { "gpio", 0 }, +}; + +static const char *qcm2290_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *qcm2290_get_pin_name(struct udevice *dev, unsigned int selector) +{ + static const char *const special_pins_names[] = { + "sdc1_rclk", "sdc1_clk", "sdc1_cmd", "sdc1_data", + "sdc2_clk", "sdc2_cmd", "sdc2_data", + }; + + if (selector >= 127 && selector <= 133) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 127]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data qcm2290_data = { + .pin_data = { + .pin_count = 133, + .special_pins_start = 127, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = qcm2290_get_function_name, + .get_function_mux = qcm2290_get_function_mux, + .get_pin_name = qcm2290_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,qcm2290-tlmm", + .data = (ulong)&qcm2290_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_qcm2290) = { + .name = "pinctrl_qcm2290", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 909e566acf5..e68971b37ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -29,15 +29,24 @@ struct msm_pinctrl_priv { #define GPIO_CONFIG_REG(priv, x) \ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x)) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) +#define GPIO_IN_OUT_REG(priv, x) \ + (GPIO_CONFIG_REG(priv, x) + 0x4) + +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_OUTPUT_MASK BIT(1) +#define TLMM_GPIO_OE_MASK BIT(9) + +/* GPIO register shifts. */ +#define GPIO_OUT_SHIFT 1 static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, }; static int msm_get_functions_count(struct udevice *dev) @@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2); + TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2); return 0; } @@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break; + case PIN_CONFIG_OUTPUT: + writel(argument << GPIO_OUT_SHIFT, + priv->base + GPIO_IN_OUT_REG(priv, pin_selector)); + setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), + TLMM_GPIO_OE_MASK); + break; default: return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 459a4329ec8..c1e5cc01fde 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -66,7 +66,18 @@ static const char *sdm845_get_function_name(struct udevice *dev, static const char *sdm845_get_pin_name(struct udevice *dev, unsigned int selector) { - snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 150 && selector <= 154) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 150]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; } diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c new file mode 100644 index 00000000000..f07f39f4ac3 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm6115 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define WEST 0x00000000 +#define SOUTH 0x00400000 +#define EAST 0x00800000 + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup4", 1 }, + { "gpio", 0 }, +}; + +static const unsigned int sm6115_pin_offsets[] = { + [0] = WEST, + [1] = WEST, + [2] = WEST, + [3] = WEST, + [4] = WEST, + [5] = WEST, + [6] = WEST, + [7] = WEST, + [8] = EAST, + [9] = EAST, + [10] = EAST, + [11] = EAST, + [12] = WEST, + [13] = WEST, + [14] = WEST, + [15] = WEST, + [16] = WEST, + [17] = WEST, + [18] = EAST, + [19] = EAST, + [20] = EAST, + [21] = EAST, + [22] = EAST, + [23] = EAST, + [24] = EAST, + [25] = EAST, + [26] = EAST, + [27] = EAST, + [28] = EAST, + [29] = EAST, + [30] = EAST, + [31] = EAST, + [32] = EAST, + [33] = EAST, + [34] = EAST, + [35] = EAST, + [36] = EAST, + [37] = EAST, + [38] = EAST, + [39] = EAST, + [40] = EAST, + [41] = EAST, + [42] = EAST, + [43] = EAST, + [44] = EAST, + [45] = EAST, + [46] = EAST, + [47] = EAST, + [48] = EAST, + [49] = EAST, + [50] = EAST, + [51] = EAST, + [52] = EAST, + [53] = EAST, + [54] = EAST, + [55] = EAST, + [56] = EAST, + [57] = EAST, + [58] = EAST, + [59] = EAST, + [60] = EAST, + [61] = EAST, + [62] = EAST, + [63] = EAST, + [64] = EAST, + [65] = WEST, + [66] = WEST, + [67] = WEST, + [68] = WEST, + [69] = WEST, + [70] = WEST, + [71] = WEST, + [72] = SOUTH, + [73] = SOUTH, + [74] = SOUTH, + [75] = SOUTH, + [76] = SOUTH, + [77] = SOUTH, + [78] = SOUTH, + [79] = SOUTH, + [80] = WEST, + [81] = WEST, + [82] = WEST, + [83] = WEST, + [84] = WEST, + [85] = WEST, + [86] = WEST, + [87] = EAST, + [88] = EAST, + [89] = WEST, + [90] = EAST, + [91] = EAST, + [92] = WEST, + [93] = WEST, + [94] = WEST, + [95] = WEST, + [96] = WEST, + [97] = WEST, + [98] = SOUTH, + [99] = SOUTH, + [100] = SOUTH, + [101] = SOUTH, + [102] = SOUTH, + [103] = SOUTH, + [104] = SOUTH, + [105] = SOUTH, + [106] = SOUTH, + [107] = SOUTH, + [108] = SOUTH, + [109] = SOUTH, + [110] = SOUTH, + [111] = SOUTH, + [112] = SOUTH, + /* Special pins */ + [113] = 0, + [114] = 0, + [115] = 0, + [116] = 0, + [117] = 0, + [118] = 0, + [119] = 0, + [120] = 0, +}; + +static const char *sm6115_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm6115_get_pin_name(struct udevice *dev, unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", "sdc1_rclk", "sdc1_clk", "sdc1_cmd", + "sdc1_data", "sdc2_clk", "sdc2_cmd", "sdc2_data", + }; + + if (selector >= 113 && selector <= 120) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 113]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data sm6115_data = { + .pin_data = { + .pin_offsets = sm6115_pin_offsets, + .pin_count = ARRAY_SIZE(sm6115_pin_offsets), + .special_pins_start = 113, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm6115_get_function_name, + .get_function_mux = sm6115_get_function_mux, + .get_pin_name = sm6115_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,sm6115-tlmm", + .data = (ulong)&sm6115_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_sm6115) = { + .name = "pinctrl_sm6115", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c new file mode 100644 index 00000000000..dac24f11bc2 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8250 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define WEST 0x00000000 +#define SOUTH 0x00400000 +#define NORTH 0x00800000 + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup12", 1 }, + { "gpio", 0 }, + { "sdc2_clk", 0 } }; + +static const unsigned int sm8250_pin_offsets[] = { + [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] = NORTH, [5] = NORTH, + [6] = NORTH, [7] = NORTH, [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH, + [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH, [16] = NORTH, [17] = NORTH, + [18] = NORTH, [19] = NORTH, [20] = NORTH, [21] = NORTH, [22] = NORTH, [23] = NORTH, + [24] = SOUTH, [25] = SOUTH, [26] = SOUTH, [27] = SOUTH, [28] = NORTH, [29] = NORTH, + [30] = NORTH, [31] = NORTH, [32] = SOUTH, [33] = SOUTH, [34] = SOUTH, [35] = SOUTH, + [36] = SOUTH, [37] = SOUTH, [38] = SOUTH, [39] = SOUTH, [40] = SOUTH, [41] = SOUTH, + [42] = SOUTH, [43] = SOUTH, [44] = SOUTH, [45] = SOUTH, [46] = SOUTH, [47] = SOUTH, + [48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH, [52] = SOUTH, [53] = SOUTH, + [54] = SOUTH, [55] = SOUTH, [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, [64] = SOUTH, [65] = SOUTH, + [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, [76] = SOUTH, [77] = NORTH, + [78] = NORTH, [79] = NORTH, [80] = NORTH, [81] = NORTH, [82] = NORTH, [83] = NORTH, + [84] = NORTH, [85] = SOUTH, [86] = SOUTH, [87] = SOUTH, [88] = SOUTH, [89] = SOUTH, + [90] = SOUTH, [91] = SOUTH, [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH, + [96] = NORTH, [97] = NORTH, [98] = NORTH, [99] = NORTH, [100] = NORTH, [101] = NORTH, + [102] = NORTH, [103] = NORTH, [104] = NORTH, [105] = NORTH, [106] = NORTH, [107] = NORTH, + [108] = NORTH, [109] = NORTH, [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, + [114] = NORTH, [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] = NORTH, [119] = NORTH, + [120] = NORTH, [121] = NORTH, [122] = NORTH, [123] = NORTH, [124] = NORTH, [125] = SOUTH, + [126] = SOUTH, [127] = SOUTH, [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, [133] = WEST, [134] = WEST, [135] = WEST, [136] = WEST, [137] = WEST, + [138] = WEST, [139] = WEST, [140] = WEST, [141] = WEST, [142] = WEST, [143] = WEST, + [144] = WEST, [145] = WEST, [146] = WEST, [147] = WEST, [148] = WEST, [149] = WEST, + [150] = WEST, [151] = WEST, [152] = WEST, [153] = WEST, [154] = WEST, [155] = WEST, + [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST, [160] = WEST, [161] = WEST, + [162] = WEST, [163] = WEST, [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST, + [168] = WEST, [169] = WEST, [170] = WEST, [171] = WEST, [172] = WEST, [173] = WEST, + [174] = WEST, [175] = WEST, [176] = WEST, [177] = WEST, [178] = WEST, [179] = WEST, + [180] = 0, [181] = 0, [182] = 0, [183] = 0, +}; + +static const char *sm8250_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8250_get_pin_name(struct udevice *dev, unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; +} + +static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8250_data = { + .pin_data = { + .pin_offsets = sm8250_pin_offsets, + .pin_count = ARRAY_SIZE(sm8250_pin_offsets), + .special_pins_start = 180, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8250_get_function_name, + .get_function_mux = sm8250_get_function_mux, + .get_pin_name = sm8250_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,sm8250-pinctrl", + .data = (ulong)&sm8250_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_sm8250) = { + .name = "pinctrl_sm8250", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c new file mode 100644 index 00000000000..7265cb73404 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8550 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup1_se7", 1}, + {"gpio", 0}, +}; + +static const char *sm8550_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8550_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 210 && selector <= 213) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8550_data = { + .pin_data = { + .pin_count = 214, + .special_pins_start = 210, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8550_get_function_name, + .get_function_mux = sm8550_get_function_mux, + .get_pin_name = sm8550_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8550-tlmm", .data = (ulong)&sm8550_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm8550) = { + .name = "pinctrl_sm8550", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; + diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c new file mode 100644 index 00000000000..d6cc1bbdda8 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8650 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup2_se7", 1}, + {"gpio", 0}, +}; + +static const char *sm8650_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8650_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 210 && selector <= 213) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8650_data = { + .pin_data = { + .pin_count = 214, + .special_pins_start = 210, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8650_get_function_name, + .get_function_mux = sm8650_get_function_mux, + .get_pin_name = sm8650_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm8650) = { + .name = "pinctrl_sm8650", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; + diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index 727b42747ab..943d845086c 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -75,6 +75,10 @@ static const struct udevice_id tps65941_ids[] = { { .compatible = "ti,tps659412", .data = TPS659411 }, { .compatible = "ti,tps659413", .data = TPS659413 }, { .compatible = "ti,lp876441", .data = LP876441 }, + { .compatible = "ti,tps65224", .data = TPS65224 }, + { .compatible = "ti,tps6594-q1", .data = TPS659411 }, + { .compatible = "ti,tps6593-q1", .data = TPS659413 }, + { .compatible = "ti,lp8764-q1", .data = LP876441 }, { } }; diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index b0411267750..5809a53fa21 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -16,6 +16,38 @@ #include <power/regulator.h> #include <power/tps65941.h> +/* Single Phase Buck IDs */ +#define TPS65941_BUCK_ID_1 1 +#define TPS65941_BUCK_ID_2 2 +#define TPS65941_BUCK_ID_3 3 +#define TPS65941_BUCK_ID_4 4 +#define TPS65941_BUCK_ID_5 5 + +/* Multi Phase Buck IDs */ +#define TPS65941_BUCK_ID_12 12 +#define TPS65941_BUCK_ID_34 34 +#define TPS65941_BUCK_ID_123 123 +#define TPS65941_BUCK_ID_1234 1234 + +/* LDO IDs */ +#define TPS65941_LDO_ID_1 1 +#define TPS65941_LDO_ID_2 2 +#define TPS65941_LDO_ID_3 3 +#define TPS65941_LDO_ID_4 4 + +#define TPS65941_BUCK_CONV_OPS_IDX 0 +#define TPS65941_LDO_CONV_OPS_IDX 0 +#define TPS65224_LDO_CONV_OPS_IDX 1 +#define TPS65224_BUCK_CONV_OPS_IDX 1 + +struct tps65941_reg_conv_ops { + int volt_mask; + int (*volt2val)(int idx, int uV); + int (*val2volt)(int idx, int volt); + int slew_mask; + int (*lookup_slew)(int id); +}; + static const char tps65941_buck_ctrl[TPS65941_BUCK_NUM] = {0x4, 0x6, 0x8, 0xA, 0xC}; static const char tps65941_buck_vout[TPS65941_BUCK_NUM] = {0xE, 0x10, 0x12, @@ -25,6 +57,11 @@ static const char tps65941_ldo_ctrl[TPS65941_BUCK_NUM] = {0x1D, 0x1E, 0x1F, static const char tps65941_ldo_vout[TPS65941_BUCK_NUM] = {0x23, 0x24, 0x25, 0x26}; +static inline int tps65941_get_chip_id(struct udevice *dev) +{ + return dev->parent->driver_data; +} + static int tps65941_buck_enable(struct udevice *dev, int op, bool *enable) { int ret; @@ -60,7 +97,7 @@ static int tps65941_buck_enable(struct udevice *dev, int op, bool *enable) return 0; } -static int tps65941_buck_volt2val(int uV) +static int tps65941_buck_volt2val(__maybe_unused int idx, int uV) { if (uV > TPS65941_BUCK_VOLT_MAX) return -EINVAL; @@ -76,7 +113,7 @@ static int tps65941_buck_volt2val(int uV) return -EINVAL; } -static int tps65941_buck_val2volt(int val) +static int tps65941_buck_val2volt(__maybe_unused int idx, int val) { if (val > TPS65941_BUCK_VOLT_MAX_HEX) return -EINVAL; @@ -116,11 +153,151 @@ int tps65941_lookup_slew(int id) } } +static int tps65224_buck_volt2val(int idx, int uV) +{ + /* This functions maps a value which is in micro Volts to the VSET value. + * The mapping is as per the datasheet of TPS65224. + */ + + if (uV > TPS65224_BUCK_VOLT_MAX) + return -EINVAL; + + if (idx > 0) { + /* Buck2, Buck3 and Buck4 of TPS65224 has a different schema in + * converting b/w micro_volt and VSET hex values + * + * VSET value starts from 0x00 for 0.5V, and for every increment + * in VSET value the output voltage increases by 25mV. This is upto + * 1.15V where VSET is 0x1A. + * + * For 0x1B the output voltage is 1.2V, and for every increment of + * VSET the output voltage increases by 50mV upto the max voltage of + * 3.3V + * + * | Voltage Ranges | VSET Ranges | Voltage Step | + * +-----------------+--------------+--------------+ + * | 0.5V to 1.50V | 0x00 to 0x1A | 25mV | + * | 1.2V to 3.3V | 0x1B to 0x45 | 50mV | + */ + if (uV >= 1200000) + return (uV - 1200000) / 50000 + 0x1B; + else if (uV >= 500000) + return (uV - 500000) / 25000; + else + return -EINVAL; + } + + /* Buck1 and Buck12(dual phase) has a different mapping b/w output + * voltage and VSET value. + * + * | Voltage Ranges | VSET Ranges | Voltage Step | + * +-----------------+--------------+--------------+ + * | 0.5V to 0.58V | 0xA to 0xE | 20mV | + * | 0.6V to 1.095V | 0xF to 0x72 | 5mV | + * | 1.1V to 1.65V | 0x73 to 0xAA | 10mV | + * | 1.6V to 3.3V | 0xAB to 0xFD | 20mV | + * + */ + if (uV >= 1660000) + return (uV - 1660000) / 20000 + 0xAB; + else if (uV >= 1100000) + return (uV - 1100000) / 10000 + 0x73; + else if (uV >= 600000) + return (uV - 600000) / 5000 + 0x0F; + else if (uV >= 500000) + return (uV - 500000) / 20000 + 0x0A; + else + return -EINVAL; +} + +static int tps65224_buck_val2volt(int idx, int val) +{ + /* This function does the opposite to the tps65224_buck_volt2val function + * described above. + * This maps the VSET value to micro volts. Please refer to the ranges + * mentioned the comments of tps65224_buck_volt2val. + */ + + if (idx > 0) { + if (val > TPS65224_BUCK234_VOLT_MAX_HEX) + return -EINVAL; + else if (val >= 0x1B) + return 1200000 + (val - 0x1B) * 50000; + else if (val >= 0x00) + return 500000 + (val - 0x00) * 25000; + else + return -EINVAL; + } + + if (val > TPS65224_BUCK1_VOLT_MAX_HEX) + return -EINVAL; + else if (val >= 0xAB) + return 1660000 + (val - 0xAB) * 20000; + else if (val >= 0x73) + return 1100000 + (val - 0x73) * 10000; + else if (val >= 0xF) + return 600000 + (val - 0xF) * 5000; + else if (val >= 0xA) + return 500000 + (val - 0xA) * 20000; + else + return -EINVAL; +} + +int tps65224_lookup_slew(int id) +{ + switch (id) { + case 0: + return 10000; + case 1: + return 5000; + case 2: + return 2500; + case 3: + return 1250; + default: + return -1; + } +} + +static const struct tps65941_reg_conv_ops buck_conv_ops[] = { + [TPS65941_BUCK_CONV_OPS_IDX] = { + .volt_mask = TPS65941_BUCK_VOLT_MASK, + .volt2val = tps65941_buck_volt2val, + .val2volt = tps65941_buck_val2volt, + .slew_mask = TP65941_BUCK_CONF_SLEW_MASK, + .lookup_slew = tps65941_lookup_slew, + }, + [TPS65224_BUCK_CONV_OPS_IDX] = { + .volt_mask = TPS65941_BUCK_VOLT_MASK, + .volt2val = tps65224_buck_volt2val, + .val2volt = tps65224_buck_val2volt, + .slew_mask = TPS65224_BUCK_CONF_SLEW_MASK, + .lookup_slew = tps65224_lookup_slew, + }, +}; + static int tps65941_buck_val(struct udevice *dev, int op, int *uV) { unsigned int hex, adr; - int ret, delta, uwait, slew; + int ret, delta, uwait, slew, idx; struct dm_regulator_uclass_plat *uc_pdata; + const struct tps65941_reg_conv_ops *conv_ops; + ulong chip_id; + + idx = dev->driver_data; + chip_id = tps65941_get_chip_id(dev); + if (chip_id == TPS65224) { + /* idx is the buck id number as per devicetree node which will be same + * as the regulator name in the datasheet. + * The idx for buck1. buck2, buck3, buck4, buck12 will be 1, 2, 3, 4 + * and 12 respectively. + * In the driver the numbering is from 0. Hence the -1. + */ + idx = (idx == TPS65941_BUCK_ID_12) ? 0 : (idx - 1); + conv_ops = &buck_conv_ops[TPS65224_BUCK_CONV_OPS_IDX]; + } else { + conv_ops = &buck_conv_ops[TPS65941_BUCK_CONV_OPS_IDX]; + } uc_pdata = dev_get_uclass_plat(dev); @@ -133,8 +310,8 @@ static int tps65941_buck_val(struct udevice *dev, int op, int *uV) if (ret < 0) return ret; - ret &= TPS65941_BUCK_VOLT_MASK; - ret = tps65941_buck_val2volt(ret); + ret &= conv_ops->volt_mask; + ret = conv_ops->val2volt(idx, ret); if (ret < 0) return ret; @@ -156,14 +333,14 @@ static int tps65941_buck_val(struct udevice *dev, int op, int *uV) if (slew < 0) return ret; - slew &= TP65941_BUCK_CONF_SLEW_MASK; - slew = tps65941_lookup_slew(slew); + slew &= conv_ops->slew_mask; + slew = conv_ops->lookup_slew(slew); if (slew <= 0) return ret; uwait = delta / slew; - hex = tps65941_buck_volt2val(*uV); + hex = conv_ops->volt2val(idx, *uV); if (hex < 0) return hex; @@ -212,7 +389,7 @@ static int tps65941_ldo_enable(struct udevice *dev, int op, bool *enable) return 0; } -static int tps65941_ldo_val2volt(int val) +static int tps65941_ldo_val2volt(__maybe_unused int idx, int val) { if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX) return -EINVAL; @@ -222,11 +399,98 @@ static int tps65941_ldo_val2volt(int val) return -EINVAL; } +static int tps65224_ldo_volt2val(int idx, int uV) +{ + int base = TPS65224_LDO1_VOLT_MIN; + int max = TPS65224_LDO1_VOLT_MAX; + int offset = TPS65224_LDO1_VOLT_MIN_HEX; + int step = TPS65224_LDO_STEP; + + if (idx > 0) { + base = TPS65224_LDO23_VOLT_MIN; + max = TPS65224_LDO23_VOLT_MAX; + offset = TPS65224_LDO23_VOLT_MIN_HEX; + } + + if (uV > max) + return -EINVAL; + else if (uV >= base) + return (uV - base) / step + offset; + else + return -EINVAL; +} + +static int tps65224_ldo_val2volt(int idx, int val) +{ + int reg_base = TPS65224_LDO1_VOLT_MIN_HEX; + int reg_max = TPS65224_LDO1_VOLT_MAX_HEX; + int base = TPS65224_LDO1_VOLT_MIN; + int max = TPS65224_LDO1_VOLT_MAX; + int step = TPS65224_LDO_STEP; + /* In LDOx_VOUT reg the BIT0 is reserved and the + * vout value is stored from BIT1 to BIT7. + * Hence the below bit shit is done. + */ + int mask = TPS65224_LDO_VOLT_MASK >> 1; + + if (idx > 0) { + base = TPS65224_LDO23_VOLT_MIN; + max = TPS65224_LDO23_VOLT_MAX; + reg_base = TPS65224_LDO23_VOLT_MIN_HEX; + reg_max = TPS65224_LDO23_VOLT_MAX_HEX; + } + + /* The VSET register of LDO has its 0th bit as reserved + * hence shifting the value to right by 1 bit. + */ + val = val >> 1; + + if (val < 0 || val > mask) + return -EINVAL; + + if (val <= reg_base) + return base; + + if (val >= reg_max) + return max; + + return base + (step * (val - reg_base)); +} + +static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { + [TPS65941_LDO_CONV_OPS_IDX] = { + .volt_mask = TPS65941_LDO_VOLT_MASK, + .volt2val = tps65941_buck_volt2val, + .val2volt = tps65941_ldo_val2volt, + }, + [TPS65224_LDO_CONV_OPS_IDX] = { + .volt_mask = TPS65224_LDO_VOLT_MASK, + .volt2val = tps65224_ldo_volt2val, + .val2volt = tps65224_ldo_val2volt, + }, +}; + static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) { unsigned int hex, adr; - int ret; + int ret, ret_volt, idx; struct dm_regulator_uclass_plat *uc_pdata; + const struct tps65941_reg_conv_ops *conv_ops; + ulong chip_id; + + chip_id = tps65941_get_chip_id(dev); + idx = dev->driver_data; + if (chip_id == TPS65224) { + /* idx is the ldo id number as per devicetree node which will be same + * as the regulator name in the datasheet. + * The idx for ldo1, ldo2, ldo3 will be 1, 2 & 3 respectively. + * In the driver the numbering is from 0. Hence the -1. + */ + idx = idx - 1; + conv_ops = &ldo_conv_ops[TPS65224_LDO_CONV_OPS_IDX]; + } else { + conv_ops = &ldo_conv_ops[TPS65941_LDO_CONV_OPS_IDX]; + } uc_pdata = dev_get_uclass_plat(dev); @@ -239,22 +503,37 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) if (ret < 0) return ret; - ret &= TPS65941_LDO_VOLT_MASK; - ret = tps65941_ldo_val2volt(ret); - if (ret < 0) - return ret; + ret &= conv_ops->volt_mask; + ret_volt = conv_ops->val2volt(idx, ret); + if (ret_volt < 0) + return ret_volt; if (op == PMIC_OP_GET) { - *uV = ret; + *uV = ret_volt; return 0; } - hex = tps65941_buck_volt2val(*uV); + /* TPS65224 LDO1 in BYPASS mode only supports 2.2V min to 3.6V max */ + if (chip_id == TPS65224 && idx == 0 && (ret & BIT(TPS65224_LDO_BYP_CONFIG)) && + *uV < TPS65224_LDO1_VOLT_BYP_MIN) + return -EINVAL; + + /* TPS65224 LDO2 & LDO3 in BYPASS mode supports 1.5V min to 5.5V max */ + if (chip_id == TPS65224 && idx > 0 && (ret & BIT(TPS65224_LDO_BYP_CONFIG)) && + *uV < TPS65224_LDO23_VOLT_BYP_MIN) + return -EINVAL; + + hex = conv_ops->volt2val(idx, *uV); if (hex < 0) return hex; - ret &= 0x0; - ret = hex; + if (chip_id == TPS65224) { + hex = hex << TPS65941_LDO_MODE_MASK; + ret &= ~TPS65224_LDO_VOLT_MASK; + ret |= hex; + } else { + ret = hex; + } ret = pmic_reg_write(dev->parent, adr, ret); @@ -265,15 +544,27 @@ static int tps65941_ldo_probe(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; int idx; + ulong chip_id; + + chip_id = tps65941_get_chip_id(dev); uc_pdata = dev_get_uclass_plat(dev); uc_pdata->type = REGULATOR_TYPE_LDO; idx = dev->driver_data; - if (idx == 1 || idx == 2 || idx == 3 || idx == 4) { + switch (idx) { + case TPS65941_LDO_ID_1: + case TPS65941_LDO_ID_2: + case TPS65941_LDO_ID_3: debug("Single phase regulator\n"); - } else { - printf("Wrong ID for regulator\n"); + break; + case TPS65941_LDO_ID_4: + if (chip_id != TPS65224) { + debug("Single phase regulator\n"); + break; + } + default: + pr_err("Wrong ID for regulator\n"); return -EINVAL; } @@ -287,23 +578,51 @@ static int tps65941_buck_probe(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; int idx; + ulong chip_id; + + chip_id = tps65941_get_chip_id(dev); uc_pdata = dev_get_uclass_plat(dev); uc_pdata->type = REGULATOR_TYPE_BUCK; idx = dev->driver_data; - if (idx == 1 || idx == 2 || idx == 3 || idx == 4 || idx == 5) { + switch (idx) { + case TPS65941_BUCK_ID_1: + case TPS65941_BUCK_ID_2: + case TPS65941_BUCK_ID_3: + case TPS65941_BUCK_ID_4: debug("Single phase regulator\n"); - } else if (idx == 12) { - idx = 1; - } else if (idx == 34) { - idx = 3; - } else if (idx == 123) { + break; + case TPS65941_BUCK_ID_5: + if (chip_id != TPS65224) { + debug("Single phase regulator\n"); + } else { + pr_err("Wrong ID for regulator\n"); + return -EINVAL; + } + break; + case TPS65941_BUCK_ID_12: idx = 1; - } else if (idx == 1234) { - idx = 1; - } else { - printf("Wrong ID for regulator\n"); + break; + case TPS65941_BUCK_ID_123: + case TPS65941_BUCK_ID_1234: + if (chip_id != TPS65224) { + idx = 1; + } else { + pr_err("Wrong ID for regulator\n"); + return -EINVAL; + } + break; + case TPS65941_BUCK_ID_34: + if (chip_id != TPS65224) { + idx = 3; + } else { + pr_err("Wrong ID for regulator\n"); + return -EINVAL; + } + break; + default: + pr_err("Wrong ID for regulator\n"); return -EINVAL; } diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c index 10828e80822..264366291cf 100644 --- a/drivers/ram/rockchip/sdram_rk3308.c +++ b/drivers/ram/rockchip/sdram_rk3308.c @@ -7,8 +7,8 @@ #include <dm.h> #include <ram.h> #include <syscon.h> -#include <asm/arch/grf_rk3308.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3308.h> #include <asm/arch-rockchip/sdram.h> struct dram_info { diff --git a/drivers/rng/stm32_rng.c b/drivers/rng/stm32_rng.c index 61d5ed61582..44e8a460752 100644 --- a/drivers/rng/stm32_rng.c +++ b/drivers/rng/stm32_rng.c @@ -74,7 +74,7 @@ struct stm32_rng_plat { * Extracts from the STM32 RNG specification when RNG supports CONDRST. * * When a noise source (or seed) error occurs, the RNG stops generating - * random numbers and sets to “1” both SEIS and SECS bits to indicate + * random numbers and sets to "1" both SEIS and SECS bits to indicate * that a seed error occurred. (...) * * 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield @@ -127,12 +127,12 @@ static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_plat *pdata) * Extracts from the STM32 RNG specification, when CONDRST is not supported * * When a noise source (or seed) error occurs, the RNG stops generating - * random numbers and sets to “1” both SEIS and SECS bits to indicate + * random numbers and sets to "1" both SEIS and SECS bits to indicate * that a seed error occurred. (...) * * The following sequence shall be used to fully recover from a seed * error after the RNG initialization: - * 1. Clear the SEIS bit by writing it to “0”. + * 1. Clear the SEIS bit by writing it to "0". * 2. Read out 12 words from the RNG_DR register, and discard each of * them in order to clean the pipeline. * 3. Confirm that SEIS is still cleared. Random number generation is diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b19e2684e5..1fe4607598e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -321,7 +321,7 @@ config DEBUG_UART_S5P config DEBUG_UART_MSM bool "Qualcomm QUP UART debug" - depends on ARCH_SNAPDRAGON + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX help Select this to enable a debug UART using the serial_msm driver. You will need to provide parameters to make this work. The driver will diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index ac4280c6c4c..a472e0b3683 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -32,6 +32,16 @@ #define UARTDM_RXFS_BUF_MASK 0x7 #define UARTDM_MR1 0x00 #define UARTDM_MR2 0x04 +/* + * This is documented on page 1817 of the apq8016e technical reference manual. + * section 6.2.5.3.26 + * + * The upper nybble contains the bit clock divider for the RX pin, the lower + * nybble defines the TX pin. In almost all cases these should be the same value. + * + * The baud rate is the core clock frequency divided by the fixed divider value + * programmed into this register (defined in calc_csr_bitrate()). + */ #define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ @@ -53,10 +63,10 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_UART_MR1_RX_RDY_CTL BIT(7) DECLARE_GLOBAL_DATA_PTR; @@ -64,7 +74,7 @@ struct msm_serial_data { phys_addr_t base; unsigned chars_cnt; /* number of buffered chars */ uint32_t chars_buf; /* buffered chars */ - uint32_t clk_bit_rate; /* data mover mode bit rate register value */ + uint32_t clk_rate; /* core clock rate */ }; static int msm_serial_fetch(struct udevice *dev) @@ -156,33 +166,63 @@ static const struct dm_serial_ops msm_serial_ops = { .getc = msm_serial_getc, }; -static int msm_uart_clk_init(struct udevice *dev) +static long msm_uart_clk_init(struct udevice *dev) { - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 115200); + struct msm_serial_data *priv = dev_get_priv(dev); struct clk clk; int ret; + long rate; ret = clk_get_by_name(dev, "core", &clk); if (ret < 0) { pr_warn("%s: Failed to get clock: %d\n", __func__, ret); - return ret; + return 0; } - ret = clk_set_rate(&clk, clk_rate); - if (ret < 0) - return ret; + rate = clk_set_rate(&clk, priv->clk_rate); - return 0; + return rate; +} + +static int calc_csr_bitrate(struct msm_serial_data *priv) +{ + /* This table is from the TRE. See the definition of UARTDM_CSR */ + unsigned int csr_div_table[] = {24576, 12288, 6144, 3072, 1536, 768, 512, 384, + 256, 192, 128, 96, 64, 48, 32, 16}; + int i = ARRAY_SIZE(csr_div_table) - 1; + /* Currently we only support one baudrate */ + int baud = 115200; + + for (; i >= 0; i--) { + int x = priv->clk_rate / csr_div_table[i]; + + if (x == baud) + /* Duplicate the configuration for RX + * as the lower nybble only configures TX + */ + return i + (i << 4); + } + + return -EINVAL; } static void uart_dm_init(struct msm_serial_data *priv) { /* Delay initialization for a bit to let pins stabilize if necessary */ mdelay(5); + int bitrate = calc_csr_bitrate(priv); + if (bitrate < 0) { + log_warning("Couldn't calculate bit clock divider! Using default\n"); + /* This happens to be the value used on MSM8916 for the hardcoded clockrate + * in clock-apq8016. It's at least a better guess than a value we *know* + * is wrong... + */ + bitrate = 0xCC; + } - writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); - writel(0x0, priv->base + UARTDM_MR1); + writel(bitrate, priv->base + UARTDM_CSR); + /* Enable RS232 flow control to support RS232 db9 connector */ + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); @@ -192,16 +232,25 @@ static void uart_dm_init(struct msm_serial_data *priv) } static int msm_serial_probe(struct udevice *dev) { - int ret; struct msm_serial_data *priv = dev_get_priv(dev); + long rate; /* No need to reinitialize the UART after relocation */ if (gd->flags & GD_FLG_RELOC) return 0; - ret = msm_uart_clk_init(dev); - if (ret) - return ret; + rate = msm_uart_clk_init(dev); + if (rate < 0) + return rate; + if (!rate) { + log_err("Got core clock rate of 0... Please fix your clock driver\n"); + return -EINVAL; + } + + /* Update the clock rate to the actual programmed rate returned by the + * clock driver + */ + priv->clk_rate = rate; uart_dm_init(priv); @@ -211,13 +260,18 @@ static int msm_serial_probe(struct udevice *dev) static int msm_serial_of_to_plat(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); + int ret; priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE); + ret = dev_read_u32(dev, "clock-frequency", &priv->clk_rate); + if (ret < 0) { + log_debug("No clock frequency specified, using default rate\n"); + /* Default for APQ8016 */ + priv->clk_rate = 7372800; + } return 0; } @@ -242,18 +296,23 @@ U_BOOT_DRIVER(serial_msm) = { static struct msm_serial_data init_serial_data = { .base = CONFIG_VAL(DEBUG_UART_BASE), - .clk_rate = 7372800, + .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK), }; #include <debug_uart.h> /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ -//int apq8016_clk_init_uart(phys_addr_t gcc_base); +//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id); static inline void _debug_uart_init(void) { - /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ - //apq8016_clk_init_uart(0x1800000); + /* + * Uncomment to turn on UART clocks when debugging U-Boot as aboot + * on MSM8916. Supported debug UART clock IDs: + * - db410c: GCC_BLSP1_UART2_APPS_CLK + * - HMIBSC: GCC_BLSP1_UART1_APPS_CLK + */ + //apq8016_clk_init_uart(0x1800000, <uart_clk_id>); uart_dm_init(&init_serial_data); } diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index 7a2fbb0db6e..ed39ff2fa4c 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -418,7 +418,7 @@ void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ) k3_ringacc_ring_reconfig_qmode_sci( ring, K3_NAV_RINGACC_RING_MODE_RING); /* - * 4. Ring the doorbell 2**22 – ringOcc times. + * 4. Ring the doorbell 2**22 - ringOcc times. * This will wrap the internal UDMAP ring state occupancy * counter (which is 21-bits wide) to 0. */ diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index 5fe8a70abca..244de69b359 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -23,13 +23,19 @@ DECLARE_GLOBAL_DATA_PTR; #define PMIC_ARB_VERSION_V2_MIN 0x20010000 #define PMIC_ARB_VERSION_V3_MIN 0x30000000 #define PMIC_ARB_VERSION_V5_MIN 0x50000000 +#define PMIC_ARB_VERSION_V7_MIN 0x70000000 #define APID_MAP_OFFSET_V1_V2_V3 (0x800) #define APID_MAP_OFFSET_V5 (0x900) +#define APID_MAP_OFFSET_V7 (0x2000) #define ARB_CHANNEL_OFFSET(n) (0x4 * (n)) #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000) #define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80) +#define SPMI_V7_OBS_CH_OFFSET(chnl) ((chnl) * 0x20) #define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x10000) +#define SPMI_V7_RW_CH_OFFSET(chnl) ((chnl) * 0x1000) + +#define SPMI_OWNERSHIP_PERIPH2OWNER(x) ((x) & 0x7) #define SPMI_REG_CMD0 0x0 #define SPMI_REG_CONFIG 0x4 @@ -49,14 +55,20 @@ DECLARE_GLOBAL_DATA_PTR; #define SPMI_STATUS_DONE 0x1 #define SPMI_MAX_CHANNELS 128 +#define SPMI_MAX_CHANNELS_V5 512 +#define SPMI_MAX_CHANNELS_V7 1024 #define SPMI_MAX_SLAVES 16 #define SPMI_MAX_PERIPH 256 +#define SPMI_CHANNEL_READ_ONLY BIT(31) +#define SPMI_CHANNEL_MASK 0xffff + enum arb_ver { V1 = 1, V2, V3, - V5 = 5 + V5 = 5, + V7 = 7 }; /* @@ -72,12 +84,25 @@ struct msm_spmi_priv { phys_addr_t arb_chnl; /* ARB channel mapping base */ phys_addr_t spmi_chnls; /* SPMI channels */ phys_addr_t spmi_obs; /* SPMI observer */ + phys_addr_t spmi_cnfg; /* SPMI config */ + u32 owner; /* Current owner */ + unsigned int max_channels; /* Max channels */ /* SPMI channel map */ - uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH]; + uint32_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH]; /* SPMI bus arbiter version */ u32 arb_ver; }; +static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u8 pid, u8 off) +{ + return (opc << 27) | (sid << 20) | (pid << 12) | (off << 4) | 1; +} + +static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 off) +{ + return (opc << 27) | (off << 4) | 1; +} + static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off, uint8_t val) { @@ -90,35 +115,53 @@ static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off, return -EIO; if (pid >= SPMI_MAX_PERIPH) return -EIO; + if (priv->channel_map[usid][pid] & SPMI_CHANNEL_READ_ONLY) + return -EPERM; - channel = priv->channel_map[usid][pid]; + channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK; - /* Disable IRQ mode for the current channel*/ - writel(0x0, - priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG); + dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel); - /* Write single byte */ - writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA); + switch (priv->arb_ver) { + case V1: + ch_offset = SPMI_CH_OFFSET(channel); - /* Prepare write command */ - reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT; - reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT); - reg |= (pid << SPMI_CMD_ADDR_SHIFT); - reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT); - reg |= 1; /* byte count */ + reg = pmic_arb_fmt_cmd_v1(SPMI_CMD_EXT_REG_WRITE_LONG, + usid, pid, off); + break; - if (priv->arb_ver == V5) - ch_offset = SPMI_V5_RW_CH_OFFSET(channel); - else + case V2: ch_offset = SPMI_CH_OFFSET(channel); + reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off); + break; + + case V5: + ch_offset = SPMI_V5_RW_CH_OFFSET(channel); + + reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off); + break; + + case V7: + ch_offset = SPMI_V7_RW_CH_OFFSET(channel); + + reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off); + break; + } + + /* Disable IRQ mode for the current channel*/ + writel(0x0, priv->spmi_chnls + ch_offset + SPMI_REG_CONFIG); + + /* Write single byte */ + writel(val, priv->spmi_chnls + ch_offset + SPMI_REG_WDATA); + /* Send write command */ - writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); + writel(reg, priv->spmi_chnls + ch_offset + SPMI_REG_CMD0); /* Wait till CMD DONE status */ reg = 0; while (!reg) { - reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) + + reg = readl(priv->spmi_chnls + ch_offset + SPMI_REG_STATUS); } @@ -142,23 +185,44 @@ static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off) if (pid >= SPMI_MAX_PERIPH) return -EIO; - channel = priv->channel_map[usid][pid]; + channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK; - if (priv->arb_ver == V5) - ch_offset = SPMI_V5_OBS_CH_OFFSET(channel); - else + dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel); + + switch (priv->arb_ver) { + case V1: ch_offset = SPMI_CH_OFFSET(channel); + /* Prepare read command */ + reg = pmic_arb_fmt_cmd_v1(SPMI_CMD_EXT_REG_READ_LONG, + usid, pid, off); + break; + + case V2: + ch_offset = SPMI_CH_OFFSET(channel); + + /* Prepare read command */ + reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off); + break; + + case V5: + ch_offset = SPMI_V5_OBS_CH_OFFSET(channel); + + /* Prepare read command */ + reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off); + break; + + case V7: + ch_offset = SPMI_V7_OBS_CH_OFFSET(channel); + + /* Prepare read command */ + reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off); + break; + } + /* Disable IRQ mode for the current channel*/ writel(0x0, priv->spmi_obs + ch_offset + SPMI_REG_CONFIG); - /* Prepare read command */ - reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT; - reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT); - reg |= (pid << SPMI_CMD_ADDR_SHIFT); - reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT); - reg |= 1; /* byte count */ - /* Request read */ writel(reg, priv->spmi_obs + ch_offset + SPMI_REG_CMD0); @@ -193,18 +257,29 @@ static int msm_spmi_probe(struct udevice *dev) core_addr = dev_read_addr_name(dev, "core"); priv->spmi_chnls = dev_read_addr_name(dev, "chnls"); priv->spmi_obs = dev_read_addr_name(dev, "obsrvr"); + dev_read_u32(dev, "qcom,ee", &priv->owner); hw_ver = readl(core_addr + PMIC_ARB_VERSION); if (hw_ver < PMIC_ARB_VERSION_V3_MIN) { priv->arb_ver = V2; priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3; + priv->max_channels = SPMI_MAX_CHANNELS; } else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) { priv->arb_ver = V3; priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3; - } else { + priv->max_channels = SPMI_MAX_CHANNELS; + } else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) { priv->arb_ver = V5; priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5; + priv->max_channels = SPMI_MAX_CHANNELS; + priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg"); + } else { + /* TOFIX: handle second bus */ + priv->arb_ver = V7; + priv->arb_chnl = core_addr + APID_MAP_OFFSET_V7; + priv->max_channels = SPMI_MAX_CHANNELS_V7; + priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg"); } dev_dbg(dev, "PMIC Arb Version-%d (%#x)\n", hw_ver >> 28, hw_ver); @@ -218,12 +293,21 @@ static int msm_spmi_probe(struct udevice *dev) dev_dbg(dev, "priv->spmi_chnls address (%#08llx)\n", priv->spmi_chnls); dev_dbg(dev, "priv->spmi_obs address (%#08llx)\n", priv->spmi_obs); /* Scan peripherals connected to each SPMI channel */ - for (i = 0; i < SPMI_MAX_PERIPH; i++) { + for (i = 0; i < priv->max_channels; i++) { uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i)); uint8_t slave_id = (periph & 0xf0000) >> 16; uint8_t pid = (periph & 0xff00) >> 8; priv->channel_map[slave_id][pid] = i; + + /* Mark channels read-only when from different owner */ + if (priv->arb_ver == V5 || priv->arb_ver == V7) { + uint32_t cnfg = readl(priv->spmi_cnfg + ARB_CHANNEL_OFFSET(i)); + uint8_t owner = SPMI_OWNERSHIP_PERIPH2OWNER(cnfg); + + if (owner != priv->owner) + priv->channel_map[slave_id][pid] |= SPMI_CHANNEL_READ_ONLY; + } } return 0; } diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c index 8ad7c09efdd..86b16a3bb8d 100644 --- a/drivers/tee/sandbox.c +++ b/drivers/tee/sandbox.c @@ -174,7 +174,7 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32 func, uint num_params, uint slot; u64 val; char *value; - u32 value_sz; + u32 value_sz, tmp_sz; switch (func) { case TA_AVB_CMD_READ_ROLLBACK_INDEX: @@ -267,8 +267,12 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32 func, uint num_params, if (!ep) return TEE_ERROR_ITEM_NOT_FOUND; - value_sz = strlen(ep->data) + 1; - memcpy(value, ep->data, value_sz); + tmp_sz = strlen(ep->data) + 1; + if (value_sz < tmp_sz) + return TEE_ERROR_SHORT_BUFFER; + + memcpy(value, ep->data, tmp_sz); + params[1].u.memref.size = tmp_sz; return TEE_SUCCESS; case TA_AVB_CMD_WRITE_PERSIST_VALUE: diff --git a/drivers/thermal/thermal_sandbox.c b/drivers/thermal/thermal_sandbox.c index acc364feb03..7dc0d108b8c 100644 --- a/drivers/thermal/thermal_sandbox.c +++ b/drivers/thermal/thermal_sandbox.c @@ -12,7 +12,7 @@ int sandbox_thermal_get_temp(struct udevice *dev, int *temp) { - /* Simply return 100°C */ + /* Simply return 100 deg C */ *temp = 100; return 0; diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 91f082fe05e..778b01b22ea 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -506,6 +506,16 @@ static int musb_usb_remove(struct udevice *dev) return 0; } +/* + * The Linux driver has a config struct, its fields mapping to this driver + * like this: + * .hdrc_config: + * sunxi_musb_hdrc_config_5eps => musb_config + * sunxi_musb_hdrc_config_4eps => musb_config_h3 + * .has_sram: always enabled, ideally no-op on SoCs not using it + * .has_reset: automatically detected from DT + * .no_configdata: handled via Kconfig's CONFIG_USB_MUSB_FIXED_CONFIGDATA + */ static const struct sunxi_musb_config sun4i_a10_cfg = { .config = &musb_config, }; @@ -518,6 +528,10 @@ static const struct sunxi_musb_config sun8i_h3_cfg = { .config = &musb_config_h3, }; +static const struct sunxi_musb_config suniv_f1c100s_cfg = { + .config = &musb_config, +}; + static const struct udevice_id sunxi_musb_ids[] = { { .compatible = "allwinner,sun4i-a10-musb", .data = (ulong)&sun4i_a10_cfg }, @@ -527,6 +541,8 @@ static const struct udevice_id sunxi_musb_ids[] = { .data = (ulong)&sun6i_a31_cfg }, { .compatible = "allwinner,sun8i-h3-musb", .data = (ulong)&sun8i_h3_cfg }, + { .compatible = "allwinner,suniv-f1c100s-musb", + .data = (ulong)&suniv_f1c100s_cfg }, { } }; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 39c82521be1..7808ae7919e 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -522,6 +522,14 @@ config VIDEO_LCD_ORISETECH_OTM8009A Say Y here if you want to enable support for Orise Technology otm8009a 480x800 dsi 2dl panel. +config VIDEO_LCD_LG_LD070WX3 + bool "LD070WX3 DSI LCD panel support" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for LG LD070WX3 + 800x1280 DSI video mode panel. + config VIDEO_LCD_RAYDIUM_RM68200 bool "RM68200 DSI LCD panel support" select VIDEO_MIPI_DSI @@ -547,6 +555,15 @@ config VIDEO_LCD_RENESAS_R69328 IPS-LCD module with Renesas R69328 IC. The panel has a 720x1280 resolution and uses 24 bit RGB per pixel. +config VIDEO_LCD_SAMSUNG_LTL106HL02 + tristate "Samsung LTL106HL02 1920x1080 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for Samsung LTL106HL02 + LCD module found in Microsoft Surface 2. The panel has a FullHD + resolution (1920x1080). + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" ---help--- diff --git a/drivers/video/Makefile b/drivers/video/Makefile index fdc29376324..f3f70cd04a1 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -58,10 +58,12 @@ obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o +obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o +obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index 2311ca2d1a5..ab917273720 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -7,6 +7,16 @@ config VIDEO_BRIDGE requires LVDS, an eDP->LVDS bridge chip can be used to provide the necessary conversion. This option enables support for these devices. +config VIDEO_BRIDGE_PARADE_DP501 + bool "Support Parade DP501 DP & DVI/HDMI dual mode transmitter" + depends on PANEL && DM_GPIO + select DM_I2C + help + The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It + enables an RGB/Parallel SOC output to be converted, packed and + serialized into either DP or TMDS output device. Only DisplayPort + functionality of this transmitter has been implemented and tested. + config VIDEO_BRIDGE_PARADE_PS862X bool "Support Parade PS862X DP->LVDS bridge" depends on VIDEO_BRIDGE @@ -40,3 +50,12 @@ config VIDEO_BRIDGE_SOLOMON_SSD2825 select VIDEO_MIPI_DSI help Solomon SSD2824 SPI RGB-DSI bridge driver wrapped into panel uClass. + +config VIDEO_BRIDGE_TOSHIBA_TC358768 + bool "Support Toshiba TC358768 MIPI DSI bridge" + depends on PANEL && DM_GPIO + select VIDEO_MIPI_DSI + select DM_I2C + help + Toshiba TC358768AXBG/TC358778XBG DSI bridge chip driver. + Found in Asus Transformer Infinity TF700T. diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile index 22625c8bc67..58697e3cbe9 100644 --- a/drivers/video/bridge/Makefile +++ b/drivers/video/bridge/Makefile @@ -4,7 +4,9 @@ # Written by Simon Glass <sjg@chromium.org> obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o +obj-$(CONFIG_VIDEO_BRIDGE_PARADE_DP501) += dp501.o obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o obj-$(CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825) += ssd2825.o +obj-$(CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768) += tc358768.o diff --git a/drivers/video/bridge/dp501.c b/drivers/video/bridge/dp501.c new file mode 100644 index 00000000000..095e3e71fed --- /dev/null +++ b/drivers/video/bridge/dp501.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Jonas Schwöbel <jonasschwoebel@yahoo.de> + * Copyright (C) 2024 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <backlight.h> +#include <panel.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <power/regulator.h> + +#include <asm/gpio.h> + +/* TOP */ +#define TOPCFG0 0x00 +#define ROMI2C_PRESCALE 0x01 +#define HDCPI2C_PRESCALE 0x02 +#define GPIO 0x03 +#define GPIO_OUT_ENB 0x04 +#define TESTI2C_CTL 0x05 +#define I2CMTIMEOUT 0x06 +#define TOPCFG1 0x07 +#define TOPCFG2 0x08 +#define TOPCFG3 0x09 +#define TOPCFG4 0x0A +#define CLKSWRST 0x0B +#define CADETB_CTL 0x0C + +/* Video Attribute */ +#define HTOTAL_L 0x10 +#define HTOTAL_H 0x11 +#define HSTART_L 0x12 +#define HSTART_H 0x13 +#define HWIDTH_L 0x14 +#define HWIDTH_H 0x15 +#define VTOTAL_L 0x16 +#define VTOTAL_H 0x17 +#define VSTART_L 0x18 +#define VSTART_H 0x19 +#define VHEIGHT_L 0x1A +#define VHEIGHT_H 0x1B +#define HSPHSW_L 0x1C +#define HSPHSW_H 0x1D +#define VSPVSW_L 0x1E +#define VSPVSW_H 0x1F +#define MISC0 0x20 +#define MISC1 0x21 + +/* Video Capture */ +#define VCAPCTRL0 0x24 +#define VCAPCTRL1 0x25 +#define VCAPCTRL2 0x26 +#define VCAPCTRL3 0x27 +#define VCAPCTRL4 0x28 +#define VCAP_MEASURE 0x29 + +/* Main Link Control */ +#define NVID_L 0x2C +#define NVID_M 0x2D +#define NVID_H 0x2E +#define LINK_CTRL0 0x2F +#define LINK_CTRL1 0x30 +#define LINK_DEBUG 0x31 +#define ERR_POS 0x32 +#define ERR_PAT 0x33 +#define LINK_DEB_SEL 0x34 +#define IDLE_PATTERN 0x35 +#define TU_SIZE 0x36 +#define CRC_CTRL 0x37 +#define CRC_OUT 0x38 + +/* AVI-2 InfoFrame */ +#define SD_CTRL0 0x3A +#define SD_CTRL1 0x3B +#define SD_HB0 0x3C +#define SD_HB1 0x3D +#define SD_HB2 0x3E +#define SD_HB3 0x3F +#define SD_DB0 0x40 +#define SD_DB1 0x41 +#define SD_DB2 0x42 +#define SD_DB3 0x43 +#define SD_DB4 0x44 +#define SD_DB5 0x45 +#define SD_DB6 0x46 +#define SD_DB7 0x47 +#define SD_DB8 0x48 +#define SD_DB9 0x49 +#define SD_DB10 0x4A +#define SD_DB11 0x4B +#define SD_DB12 0x4C +#define SD_DB13 0x4D +#define SD_DB14 0x4E +#define SD_DB15 0x4F + +/* Aux Channel and PCS */ +#define DPCD_REV 0X50 +#define MAX_LINK_RATE 0x51 +#define MAX_LANE_COUNT 0x52 +#define MAX_DOWNSPREAD 0x53 +#define NORP 0x54 +#define DOWNSTRMPORT_PRE 0x55 +#define MLINK_CH_CODING 0x56 +#define RCV_P0_CAP0 0x58 +#define RCV_P0_CAP1 0x59 +#define RCV_P1_CAP0 0x5A +#define RCV_P1_CAP1 0x5B +#define DOWNSPREAD_CTL 0x5C +#define LINK_BW 0x5D +#define LANE_CNT 0x5E +#define TRAINING_CTL 0x5F +#define QUALTEST_CTL 0x60 +#define SINK_COUNT 0x61 +#define DEV_SERVICE_IRQ 0x62 +#define LANE01_STATUS 0x63 +#define LANE23_STATUS 0x64 +#define LANE_STATUS_UPDATE 0x65 +#define SINK_STATUS 0x66 +#define AUX_NOISE 0x67 +#define TEST_MODE 0x69 +#define TEST_PATTERN0 0x6A +#define TEST_PATTERN1 0x6B +#define TEST_PATTERN2 0x6C +#define SIGNATURE 0x6D +#define PCSCFG 0x6E +#define AUXCTRL0 0x6f +#define AUXCTRL2 0x70 +#define AUXCTRL1 0x71 +#define HPDCTL0 0x72 +#define HPDCTL1 0x73 +#define LINK_STATE_CTRL 0x74 +#define SWRST 0x75 +#define LINK_IRQ 0x76 +#define AUXIRQ_CTRL 0x77 +#define HPD2_IRQ_CTRL 0x78 +#define SW_TRAIN_CTRL 0x79 +#define SW_DRV_SET 0x7A +#define SW_PRE_SET 0x7B +#define DPCD_ADDR_L 0x7D +#define DPCD_ADDR_M 0x7E +#define DPCD_ADDR_H 0x7F +#define DPCD_LENGTH 0x80 +#define DPCD_WDATA 0x81 +#define DPCD_RDATA 0x82 +#define DPCD_CTL 0x83 +#define DPCD_STATUS 0x84 +#define AUX_STATUS 0x85 +#define I2CTOAUX_RELENGTH 0x86 +#define AUX_RETRY_CTRL 0x87 +#define TIMEOUT_CTRL 0x88 +#define I2CCMD_OPT1 0x89 +#define AUXCMD_ERR_IRQ 0x8A +#define AUXCMD_OPT2 0x8B +#define HDCP_Reserved 0x8C + +/* Audio InfoFrame */ +#define TX_MVID0 0x90 +#define TX_MVID1 0x91 +#define TX_MVID2 0x92 +#define TX_MVID_OFF 0x93 +#define TX_MAUD0 0x94 +#define TX_MAUD1 0x95 +#define TX_MAUD2 0x96 +#define TX_MAUD_OFF 0x97 +#define MN_CTRL 0x98 +#define MOUT0 0x99 +#define MOUT1 0x9A +#define MOUT2 0x9B + +/* Audio Control */ +#define NAUD_L 0x9F +#define NAUD_M 0xA0 +#define NAUD_H 0xA1 +#define AUD_CTRL0 0xA2 +#define AUD_CTRL1 0xA3 +#define LANE_POL 0xAA +#define LANE_EN 0xAB +#define LANE_MAP 0xAC +#define SCR_POLY0 0xAD +#define SCR_POLY1 0xAE +#define PRBS7_POLY 0xAF + +/* Video Pre-process */ +#define MISC_SHDOW 0xB0 +#define VCAPCPCTL0 0xB1 +#define VCAPCPCTL1 0xB2 +#define VCAPCPCTL2 0xB3 +#define CSCPAR 0xB4 +#define I2CTODPCDSTATUS2 0xBA +#define AUXCTL_REG 0xBB + +/* Page 2 */ +#define SEL_PIO1 0x24 +#define SEL_PIO2 0x25 +#define SEL_PIO3 0x26 +#define CHIP_VER_L 0x82 + +struct dp501_priv { + struct udevice *panel; + struct display_timing timing; + + struct udevice *chip2; + + struct udevice *vdd; + struct gpio_desc reset_gpio; + struct gpio_desc enable_gpio; +}; + +static int dp501_sw_init(struct udevice *dev) +{ + struct dp501_priv *priv = dev_get_priv(dev); + int i; + u8 val; + + dm_i2c_reg_write(dev, TOPCFG4, 0x30); + udelay(200); + dm_i2c_reg_write(dev, TOPCFG4, 0x0c); + dm_i2c_reg_write(dev, 0x8f, 0x02); + + /* check for connected panel during 1 msec */ + for (i = 0; i < 5; i++) { + val = dm_i2c_reg_read(dev, 0x8d); + val &= BIT(2); + if (val) + break; + + udelay(200); + } + + if (!val) { + log_debug("%s: panel is not connected!\n", __func__); + return -ENODEV; + } + + dm_i2c_reg_write(priv->chip2, SEL_PIO1, 0x02); + dm_i2c_reg_write(priv->chip2, SEL_PIO2, 0x04); + dm_i2c_reg_write(priv->chip2, SEL_PIO3, 0x10); + + dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0xa0); + dm_i2c_reg_write(dev, 0x8f, 0x02); + dm_i2c_reg_write(dev, TOPCFG1, 0x16); + dm_i2c_reg_write(dev, TOPCFG0, 0x24); + dm_i2c_reg_write(dev, HPD2_IRQ_CTRL, 0x30); + dm_i2c_reg_write(dev, AUXIRQ_CTRL, 0xff); + dm_i2c_reg_write(dev, LINK_IRQ, 0xff); + + /* auto detect DVO timing */ + dm_i2c_reg_write(dev, VCAPCTRL3, 0x30); + + /* reset tpfifo at v blank */ + dm_i2c_reg_write(dev, LINK_CTRL0, 0x82); + + dm_i2c_reg_write(dev, VCAPCTRL4, 0x07); + dm_i2c_reg_write(dev, AUX_RETRY_CTRL, 0x7f); + dm_i2c_reg_write(dev, TIMEOUT_CTRL, 0x1e); + dm_i2c_reg_write(dev, AUXCTL_REG, 0x06); + + /* DPCD readable */ + dm_i2c_reg_write(dev, HPDCTL0, 0xa9); + + /* Scramble on */ + dm_i2c_reg_write(dev, QUALTEST_CTL, 0x00); + + dm_i2c_reg_write(dev, 0x8f, 0x02); + + dm_i2c_reg_write(dev, VCAPCTRL0, 0xc4); + + /* set color depth 8bit (0x00: 6bit; 0x20: 8bit; 0x40: 10bit) */ + dm_i2c_reg_write(dev, MISC0, 0x20); + + dm_i2c_reg_write(dev, VCAPCPCTL2, 0x01); + + /* check if bridge returns ready status */ + for (i = 0; i < 5; i++) { + val = dm_i2c_reg_read(dev, LINK_IRQ); + val &= BIT(0); + if (val) + break; + + udelay(200); + } + + if (!val) { + log_debug("%s: bridge is not ready\n", __func__); + return -ENODEV; + } + + return 0; +} + +static void dpcd_configure(struct udevice *dev, u32 config, bool write) +{ + dm_i2c_reg_write(dev, DPCD_ADDR_L, (u8)(config >> 8)); + dm_i2c_reg_write(dev, DPCD_ADDR_M, (u8)(config >> 16)); + dm_i2c_reg_write(dev, DPCD_ADDR_H, (u8)((config >> 24) | BIT(7))); + dm_i2c_reg_write(dev, DPCD_LENGTH, 0x00); + dm_i2c_reg_write(dev, LINK_IRQ, 0x20); + + if (write) + dm_i2c_reg_write(dev, DPCD_WDATA, (u8)(config & 0xff)); + + dm_i2c_reg_write(dev, DPCD_CTL, 0x01); + + udelay(10); +} + +static int dump_dpcd_data(struct udevice *dev, u32 config, u8 *data) +{ + int i; + u8 value; + + dpcd_configure(dev, config, false); + + value = dm_i2c_reg_read(dev, DPCD_CTL); + if (value) + return -ENODATA; + + for (i = 0; i < 5; i++) { + value = dm_i2c_reg_read(dev, LINK_IRQ); + value &= BIT(5); + if (value) + break; + + udelay(100); + } + + if (!value) + return -ENODATA; + + value = dm_i2c_reg_read(dev, DPCD_STATUS); + if (!(value & 0xe0)) + *data = dm_i2c_reg_read(dev, DPCD_RDATA); + else + return -ENODATA; + + return 0; +} + +static int dp501_dpcd_dump(struct udevice *dev, u32 config, u8 *data) +{ + int i, ret; + + for (i = 0; i < 5; i++) { + ret = dump_dpcd_data(dev, config, data); + if (!ret) + break; + + udelay(100); + } + + return ret; +} + +static int dp501_reset_link(struct udevice *dev) +{ + dm_i2c_reg_write(dev, TRAINING_CTL, 0x00); + dm_i2c_reg_write(dev, SWRST, 0xf8); + dm_i2c_reg_write(dev, SWRST, 0x00); + + return -ENODEV; +} + +static int dp501_link_training(struct udevice *dev) +{ + int i, ret; + u8 lane, link, link_out; + u8 lane_cnt, lane01, lane23; + + dpcd_configure(dev, 0x030000, true); + dpcd_configure(dev, 0x03011c, true); + dpcd_configure(dev, 0x0301f8, true); + + ret = dp501_dpcd_dump(dev, 0x90000100, &link); + if (ret) { + log_debug("%s: link dump failed %d\n", __func__, ret); + return dp501_reset_link(dev); + } + + ret = dp501_dpcd_dump(dev, 0x90000200, &lane); + if (ret) { + log_debug("%s: lane dump failed %d\n", __func__, ret); + return dp501_reset_link(dev); + } + + /* Software trainig */ + for (i = 10; i > 0; i--) { + dm_i2c_reg_write(dev, LINK_BW, link); + dm_i2c_reg_write(dev, LANE_CNT, lane | BIT(7)); + + link_out = dm_i2c_reg_read(dev, LINK_BW); + lane_cnt = dm_i2c_reg_read(dev, LANE_CNT); + + if (link_out == link && + (lane_cnt == (lane | BIT(7)))) + break; + + udelay(500); + } + + if (!i) + return dp501_reset_link(dev); + + dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0x00); + dm_i2c_reg_write(dev, TRAINING_CTL, 0x0d); + + /* check if bridge returns link ready status */ + for (i = 0; i < 100; i++) { + link_out = dm_i2c_reg_read(dev, LINK_IRQ); + link_out &= BIT(1); + if (link_out) { + dm_i2c_reg_write(dev, LINK_IRQ, 0xff); + break; + } + + udelay(100); + } + + if (!link_out) { + log_debug("%s: link prepare failed %d\n", + __func__, link_out); + return dp501_reset_link(dev); + } + + lane01 = dm_i2c_reg_read(dev, LANE01_STATUS); + lane23 = dm_i2c_reg_read(dev, LANE23_STATUS); + + switch (lane_cnt & 0xf) { + case 4: + if (lane01 == 0x77 && + lane23 == 0x77) + return 0; + break; + + case 2: + if (lane01 == 0x77) + return 0; + break; + + default: + if ((lane01 & 7) == 7) + return 0; + break; + } + + return dp501_reset_link(dev); +} + +static int dp501_attach(struct udevice *dev) +{ + struct dp501_priv *priv = dev_get_priv(dev); + int ret; + + ret = dp501_sw_init(dev); + if (ret) + return ret; + + mdelay(90); + + ret = dp501_link_training(dev); + if (ret) + return ret; + + /* Perform panel HW setup */ + return panel_enable_backlight(priv->panel); +} + +static int dp501_set_backlight(struct udevice *dev, int percent) +{ + struct dp501_priv *priv = dev_get_priv(dev); + + return panel_set_backlight(priv->panel, percent); +} + +static int dp501_panel_timings(struct udevice *dev, + struct display_timing *timing) +{ + struct dp501_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->timing, sizeof(*timing)); + return 0; +} + +static void dp501_hw_init(struct dp501_priv *priv) +{ + dm_gpio_set_value(&priv->reset_gpio, 1); + + regulator_set_enable_if_allowed(priv->vdd, 1); + dm_gpio_set_value(&priv->enable_gpio, 1); + + udelay(100); + + dm_gpio_set_value(&priv->reset_gpio, 0); + mdelay(80); +} + +static int dp501_setup(struct udevice *dev) +{ + struct dm_i2c_chip *chip = dev_get_parent_plat(dev); + struct dp501_priv *priv = dev_get_priv(dev); + struct udevice *bus = dev_get_parent(dev); + int ret; + + /* get panel */ + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "panel", &priv->panel); + if (ret) { + log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret); + return log_ret(ret); + } + + /* get regulators */ + ret = device_get_supply_regulator(dev, "power-supply", &priv->vdd); + if (ret) { + log_debug("%s: vddc regulator error: %d\n", __func__, ret); + if (ret != -ENOENT) + return log_ret(ret); + } + + /* get gpios */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: Could not decode reset-gpios (%d)\n", + __func__, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "enable-gpios", 0, + &priv->enable_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: Could not decode enable-gpios (%d)\n", + __func__, ret); + return ret; + } + + ret = i2c_get_chip(bus, chip->chip_addr + 2, 1, &priv->chip2); + if (ret) { + log_debug("%s: cannot get second PMIC I2C chip (err %d)\n", + __func__, ret); + return ret; + } + + dp501_hw_init(priv); + + /* get EDID */ + return panel_get_display_timing(priv->panel, &priv->timing); +} + +static int dp501_probe(struct udevice *dev) +{ + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + return dp501_setup(dev); +} + +struct panel_ops dp501_ops = { + .enable_backlight = dp501_attach, + .set_backlight = dp501_set_backlight, + .get_display_timing = dp501_panel_timings, +}; + +static const struct udevice_id dp501_ids[] = { + { .compatible = "parade,dp501" }, + { } +}; + +U_BOOT_DRIVER(dp501) = { + .name = "dp501", + .id = UCLASS_PANEL, + .of_match = dp501_ids, + .ops = &dp501_ops, + .probe = dp501_probe, + .priv_auto = sizeof(struct dp501_priv), +}; diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c index cea20dcffa5..f0ef3dafb93 100644 --- a/drivers/video/bridge/ssd2825.c +++ b/drivers/video/bridge/ssd2825.c @@ -349,39 +349,6 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev) struct ssd2825_bridge_priv *priv = dev_get_priv(dev); struct mipi_dsi_device *device = &priv->device; struct display_timing *dt = &priv->timing; - int ret; - - ret = clk_prepare_enable(priv->tx_clk); - if (ret) { - log_err("error enabling tx_clk (%d)\n", ret); - return ret; - } - - ret = dm_gpio_set_value(&priv->power_gpio, 1); - if (ret) { - log_err("error changing power-gpios (%d)\n", ret); - return ret; - } - mdelay(10); - - ret = dm_gpio_set_value(&priv->reset_gpio, 0); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(10); - - ret = dm_gpio_set_value(&priv->reset_gpio, 1); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(10); - - /* Perform panel HW setup */ - ret = panel_enable_backlight(priv->panel); - if (ret) - return ret; /* Perform SW reset */ ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100); @@ -417,17 +384,15 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev) SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT); ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); - /* Set up SW panel configuration */ - ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT); - if (ret) - return ret; - - return 0; + /* Perform panel setup */ + return panel_enable_backlight(priv->panel); } static int ssd2825_bridge_set_panel(struct udevice *dev, int percent) { - return 0; + struct ssd2825_bridge_priv *priv = dev_get_priv(dev); + + return panel_set_backlight(priv->panel, percent); } static int ssd2825_bridge_panel_timings(struct udevice *dev, @@ -440,6 +405,45 @@ static int ssd2825_bridge_panel_timings(struct udevice *dev, return 0; } +static int ssd2825_bridge_hw_init(struct udevice *dev) +{ + struct ssd2825_bridge_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_prepare_enable(priv->tx_clk); + if (ret) { + log_debug("%s: error enabling tx_clk (%d)\n", + __func__, ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->power_gpio, 1); + if (ret) { + log_debug("%s: error changing power-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(10); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(10); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(10); + + return 0; +} + static int ssd2825_bridge_probe(struct udevice *dev) { struct ssd2825_bridge_priv *priv = dev_get_priv(dev); @@ -496,7 +500,7 @@ static int ssd2825_bridge_probe(struct udevice *dev) return PTR_ERR(priv->tx_clk); } - return 0; + return ssd2825_bridge_hw_init(dev); } static const struct panel_ops ssd2825_bridge_ops = { diff --git a/drivers/video/bridge/tc358768.c b/drivers/video/bridge/tc358768.c new file mode 100644 index 00000000000..19b6ca29d3e --- /dev/null +++ b/drivers/video/bridge/tc358768.c @@ -0,0 +1,985 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <mipi_display.h> +#include <mipi_dsi.h> +#include <backlight.h> +#include <panel.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/math64.h> +#include <power/regulator.h> + +#include <asm/gpio.h> + +/* Global (16-bit addressable) */ +#define TC358768_CHIPID 0x0000 +#define TC358768_SYSCTL 0x0002 +#define TC358768_CONFCTL 0x0004 +#define TC358768_VSDLY 0x0006 +#define TC358768_DATAFMT 0x0008 +#define TC358768_GPIOEN 0x000E +#define TC358768_GPIODIR 0x0010 +#define TC358768_GPIOIN 0x0012 +#define TC358768_GPIOOUT 0x0014 +#define TC358768_PLLCTL0 0x0016 +#define TC358768_PLLCTL1 0x0018 +#define TC358768_CMDBYTE 0x0022 +#define TC358768_PP_MISC 0x0032 +#define TC358768_DSITX_DT 0x0050 +#define TC358768_FIFOSTATUS 0x00F8 + +/* Debug (16-bit addressable) */ +#define TC358768_VBUFCTRL 0x00E0 +#define TC358768_DBG_WIDTH 0x00E2 +#define TC358768_DBG_VBLANK 0x00E4 +#define TC358768_DBG_DATA 0x00E8 + +/* TX PHY (32-bit addressable) */ +#define TC358768_CLW_DPHYCONTTX 0x0100 +#define TC358768_D0W_DPHYCONTTX 0x0104 +#define TC358768_D1W_DPHYCONTTX 0x0108 +#define TC358768_D2W_DPHYCONTTX 0x010C +#define TC358768_D3W_DPHYCONTTX 0x0110 +#define TC358768_CLW_CNTRL 0x0140 +#define TC358768_D0W_CNTRL 0x0144 +#define TC358768_D1W_CNTRL 0x0148 +#define TC358768_D2W_CNTRL 0x014C +#define TC358768_D3W_CNTRL 0x0150 + +/* TX PPI (32-bit addressable) */ +#define TC358768_STARTCNTRL 0x0204 +#define TC358768_DSITXSTATUS 0x0208 +#define TC358768_LINEINITCNT 0x0210 +#define TC358768_LPTXTIMECNT 0x0214 +#define TC358768_TCLK_HEADERCNT 0x0218 +#define TC358768_TCLK_TRAILCNT 0x021C +#define TC358768_THS_HEADERCNT 0x0220 +#define TC358768_TWAKEUP 0x0224 +#define TC358768_TCLK_POSTCNT 0x0228 +#define TC358768_THS_TRAILCNT 0x022C +#define TC358768_HSTXVREGCNT 0x0230 +#define TC358768_HSTXVREGEN 0x0234 +#define TC358768_TXOPTIONCNTRL 0x0238 +#define TC358768_BTACNTRL1 0x023C + +/* TX CTRL (32-bit addressable) */ +#define TC358768_DSI_CONTROL 0x040C +#define TC358768_DSI_STATUS 0x0410 +#define TC358768_DSI_INT 0x0414 +#define TC358768_DSI_INT_ENA 0x0418 +#define TC358768_DSICMD_RDFIFO 0x0430 +#define TC358768_DSI_ACKERR 0x0434 +#define TC358768_DSI_ACKERR_INTENA 0x0438 +#define TC358768_DSI_ACKERR_HALT 0x043c +#define TC358768_DSI_RXERR 0x0440 +#define TC358768_DSI_RXERR_INTENA 0x0444 +#define TC358768_DSI_RXERR_HALT 0x0448 +#define TC358768_DSI_ERR 0x044C +#define TC358768_DSI_ERR_INTENA 0x0450 +#define TC358768_DSI_ERR_HALT 0x0454 +#define TC358768_DSI_CONFW 0x0500 +#define TC358768_DSI_LPCMD 0x0500 +#define TC358768_DSI_RESET 0x0504 +#define TC358768_DSI_INT_CLR 0x050C +#define TC358768_DSI_START 0x0518 + +/* DSITX CTRL (16-bit addressable) */ +#define TC358768_DSICMD_TX 0x0600 +#define TC358768_DSICMD_TYPE 0x0602 +#define TC358768_DSICMD_WC 0x0604 +#define TC358768_DSICMD_WD0 0x0610 +#define TC358768_DSICMD_WD1 0x0612 +#define TC358768_DSICMD_WD2 0x0614 +#define TC358768_DSICMD_WD3 0x0616 +#define TC358768_DSI_EVENT 0x0620 +#define TC358768_DSI_VSW 0x0622 +#define TC358768_DSI_VBPR 0x0624 +#define TC358768_DSI_VACT 0x0626 +#define TC358768_DSI_HSW 0x0628 +#define TC358768_DSI_HBPR 0x062A +#define TC358768_DSI_HACT 0x062C + +/* TC358768_DSI_CONTROL (0x040C) register */ +#define TC358768_DSI_CONTROL_DIS_MODE BIT(15) +#define TC358768_DSI_CONTROL_TXMD BIT(7) +#define TC358768_DSI_CONTROL_HSCKMD BIT(5) +#define TC358768_DSI_CONTROL_EOTDIS BIT(0) + +/* TC358768_DSI_CONFW (0x0500) register */ +#define TC358768_DSI_CONFW_MODE_SET (5 << 29) +#define TC358768_DSI_CONFW_MODE_CLR (6 << 29) +#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (3 << 24) + +#define NANO 1000000000UL +#define PICO 1000000000000ULL + +struct tc358768_priv { + struct mipi_dsi_host host; + struct mipi_dsi_device device; + + struct udevice *panel; + struct display_timing timing; + + struct udevice *vddc; + struct udevice *vddmipi; + struct udevice *vddio; + + struct clk *refclk; + + struct gpio_desc reset_gpio; + + u32 pd_lines; /* number of Parallel Port Input Data Lines */ + u32 dsi_lanes; /* number of DSI Lanes */ + + /* Parameters for PLL programming */ + u32 fbd; /* PLL feedback divider */ + u32 prd; /* PLL input divider */ + u32 frs; /* PLL Freqency range for HSCK (post divider) */ + + u32 dsiclk; /* pll_clk / 2 */ +}; + +static void tc358768_read(struct udevice *dev, u32 reg, u32 *val) +{ + int count; + u8 buf[4] = { 0, 0, 0, 0 }; + + /* 16-bit register? */ + if (reg < 0x100 || reg >= 0x600) + count = 2; + else + count = 4; + + dm_i2c_read(dev, reg, buf, count); + *val = (buf[0] << 8) | (buf[1] & 0xff) | + (buf[2] << 24) | (buf[3] << 16); + + log_debug("%s 0x%04x >> 0x%08x\n", + __func__, reg, *val); +} + +static void tc358768_write(struct udevice *dev, u32 reg, u32 val) +{ + int count; + u8 buf[4]; + + /* 16-bit register? */ + if (reg < 0x100 || reg >= 0x600) + count = 2; + else + count = 4; + + buf[0] = val >> 8; + buf[1] = val & 0xff; + buf[2] = val >> 24; + buf[3] = val >> 16; + + log_debug("%s 0x%04x << 0x%08x\n", + __func__, reg, val); + + dm_i2c_write(dev, reg, buf, count); +} + +static void tc358768_update_bits(struct udevice *dev, u32 reg, u32 mask, + u32 val) +{ + u32 tmp, orig; + + tc358768_read(dev, reg, &orig); + + tmp = orig & ~mask; + tmp |= val & mask; + if (tmp != orig) + tc358768_write(dev, reg, tmp); +} + +static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct udevice *dev = (struct udevice *)host->dev; + struct mipi_dsi_packet packet; + int ret; + + if (msg->rx_len) { + log_debug("%s: MIPI rx is not supported\n", __func__); + return -EOPNOTSUPP; + } + + if (msg->tx_len > 8) { + log_debug("%s: Maximum 8 byte MIPI tx is supported\n", __func__); + return -EOPNOTSUPP; + } + + ret = mipi_dsi_create_packet(&packet, msg); + if (ret) + return ret; + + if (mipi_dsi_packet_format_is_short(msg->type)) { + tc358768_write(dev, TC358768_DSICMD_TYPE, + (0x10 << 8) | (packet.header[0] & 0x3f)); + tc358768_write(dev, TC358768_DSICMD_WC, 0); + tc358768_write(dev, TC358768_DSICMD_WD0, + (packet.header[2] << 8) | packet.header[1]); + } else { + int i; + + tc358768_write(dev, TC358768_DSICMD_TYPE, + (0x40 << 8) | (packet.header[0] & 0x3f)); + tc358768_write(dev, TC358768_DSICMD_WC, packet.payload_length); + for (i = 0; i < packet.payload_length; i += 2) { + u16 val = packet.payload[i]; + + if (i + 1 < packet.payload_length) + val |= packet.payload[i + 1] << 8; + + tc358768_write(dev, TC358768_DSICMD_WD0 + i, val); + } + } + + /* start transfer */ + tc358768_write(dev, TC358768_DSICMD_TX, 1); + + return packet.size; +} + +static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { + .transfer = tc358768_dsi_host_transfer, +}; + +static void tc358768_sw_reset(struct udevice *dev) +{ + /* Assert Reset */ + tc358768_write(dev, TC358768_SYSCTL, 1); + mdelay(5); + + /* Release Reset, Exit Sleep */ + tc358768_write(dev, TC358768_SYSCTL, 0); +} + +static void tc358768_hw_enable(struct tc358768_priv *priv) +{ + int ret; + + ret = clk_prepare_enable(priv->refclk); + if (ret) + log_debug("%s: error enabling refclk (%d)\n", __func__, ret); + + ret = regulator_set_enable_if_allowed(priv->vddc, true); + if (ret) + log_debug("%s: error enabling vddc (%d)\n", __func__, ret); + + ret = regulator_set_enable_if_allowed(priv->vddmipi, true); + if (ret) + log_debug("%s: error enabling vddmipi (%d)\n", __func__, ret); + + mdelay(10); + + ret = regulator_set_enable_if_allowed(priv->vddio, true); + if (ret) + log_debug("%s: error enabling vddio (%d)\n", __func__, ret); + + mdelay(2); + + /* + * The RESX is active low (GPIO_ACTIVE_LOW). + * DEASSERT (value = 0) the reset_gpio to enable the chip + */ + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + log_debug("%s: error changing reset-gpio (%d)\n", __func__, ret); + + /* wait for encoder clocks to stabilize */ + mdelay(2); +} + +static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) +{ + return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes); +} + +static int tc358768_calc_pll(struct tc358768_priv *priv, + struct display_timing *dt) +{ + static const u32 frs_limits[] = { + 1000000000, + 500000000, + 250000000, + 125000000, + 62500000 + }; + unsigned long refclk; + u32 prd, target_pll, i, max_pll, min_pll; + u32 frs, best_diff, best_pll, best_prd, best_fbd; + + target_pll = tc358768_pclk_to_pll(priv, dt->pixelclock.typ); + + /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ + + for (i = 0; i < ARRAY_SIZE(frs_limits); i++) + if (target_pll >= frs_limits[i]) + break; + + if (i == ARRAY_SIZE(frs_limits) || i == 0) + return -EINVAL; + + frs = i - 1; + max_pll = frs_limits[i - 1]; + min_pll = frs_limits[i]; + + refclk = clk_get_rate(priv->refclk); + + best_diff = UINT_MAX; + best_pll = 0; + best_prd = 0; + best_fbd = 0; + + for (prd = 1; prd <= 16; ++prd) { + u32 divisor = prd * (1 << frs); + u32 fbd; + + for (fbd = 1; fbd <= 512; ++fbd) { + u32 pll, diff, pll_in; + + pll = (u32)div_u64((u64)refclk * fbd, divisor); + + if (pll >= max_pll || pll < min_pll) + continue; + + pll_in = (u32)div_u64((u64)refclk, prd); + if (pll_in < 4000000) + continue; + + diff = max(pll, target_pll) - min(pll, target_pll); + + if (diff < best_diff) { + best_diff = diff; + best_pll = pll; + best_prd = prd; + best_fbd = fbd; + + if (best_diff == 0) + goto found; + } + } + } + + if (best_diff == UINT_MAX) { + log_debug("%s: could not find suitable PLL setup\n", __func__); + return -EINVAL; + } + +found: + priv->fbd = best_fbd; + priv->prd = best_prd; + priv->frs = frs; + priv->dsiclk = best_pll / 2; + + return 0; +} + +static void tc358768_setup_pll(struct udevice *dev) +{ + struct tc358768_priv *priv = dev_get_priv(dev); + u32 fbd, prd, frs; + int ret; + + ret = tc358768_calc_pll(priv, &priv->timing); + if (ret) + log_debug("%s: PLL calculation failed: %d\n", __func__, ret); + + fbd = priv->fbd; + prd = priv->prd; + frs = priv->frs; + + log_debug("%s: PLL: refclk %lu, fbd %u, prd %u, frs %u\n", __func__, + clk_get_rate(priv->refclk), fbd, prd, frs); + log_debug("%s: PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", __func__, + priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); + + /* PRD[15:12] FBD[8:0] */ + tc358768_write(dev, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); + + /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ + tc358768_write(dev, TC358768_PLLCTL1, + (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); + + /* wait for lock */ + mdelay(5); + + /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ + tc358768_write(dev, TC358768_PLLCTL1, + (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); +} + +static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) +{ + return DIV_ROUND_UP(ns * 1000, period_ps); +} + +static u32 tc358768_ps_to_ns(u32 ps) +{ + return ps / 1000; +} + +static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) +{ + return (u32)div_u64((u64)val * NANO, pclk); +} + +/* Convert value in DPI pixel clock units to DSI byte count */ +static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) +{ + u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; + u64 n = priv->timing.pixelclock.typ; + + return (u32)div_u64(m + n - 1, n); +} + +static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) +{ + u64 m = (u64)val * NANO; + u64 n = priv->dsiclk / 4 * priv->dsi_lanes; + + return (u32)div_u64(m, n); +} + +static int tc358768_attach(struct udevice *dev) +{ + struct tc358768_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct display_timing *dt = &priv->timing; + u32 val, val2, lptxcnt, hact, data_type; + s32 raw_val; + u32 hsbyteclk_ps, dsiclk_ps, ui_ps; + u32 dsiclk, hsbyteclk; + int i; + /* In pixelclock units */ + u32 dpi_htot, dpi_data_start; + /* In byte units */ + u32 dsi_dpi_htot, dsi_dpi_data_start; + u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; + const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */ + /* In hsbyteclk units */ + u32 dsi_vsdly; + const u32 internal_dly = 40; + + if (device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + debug("%s: Non-continuous mode unimplemented, falling back to continuous\n", __func__); + device->mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; + } + + tc358768_hw_enable(priv); + tc358768_sw_reset(dev); + + tc358768_setup_pll(dev); + + dsiclk = priv->dsiclk; + hsbyteclk = dsiclk / 4; + + /* Data Format Control Register */ + val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ + switch (device->format) { + case MIPI_DSI_FMT_RGB888: + val |= (0x3 << 4); + hact = dt->hactive.typ * 3; + data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; + break; + case MIPI_DSI_FMT_RGB666: + val |= (0x4 << 4); + hact = dt->hactive.typ * 3; + data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + val |= (0x4 << 4) | BIT(3); + hact = dt->hactive.typ * 18 / 8; + data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; + break; + case MIPI_DSI_FMT_RGB565: + val |= (0x5 << 4); + hact = dt->hactive.typ * 2; + data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; + break; + default: + log_debug("%s: Invalid data format (%u)\n", + __func__, device->format); + return -EINVAL; + } + + /* + * There are three important things to make TC358768 work correctly, + * which are not trivial to manage: + * + * 1. Keep the DPI line-time and the DSI line-time as close to each + * other as possible. + * 2. TC358768 goes to LP mode after each line's active area. The DSI + * HFP period has to be long enough for entering and exiting LP mode. + * But it is not clear how to calculate this. + * 3. VSDly (video start delay) has to be long enough to ensure that the + * DSI TX does not start transmitting until we have started receiving + * pixel data from the DPI input. It is not clear how to calculate + * this either. + */ + + dpi_htot = dt->hactive.typ + dt->hfront_porch.typ + + dt->hsync_len.typ + dt->hback_porch.typ; + dpi_data_start = dt->hsync_len.typ + dt->hback_porch.typ; + + log_debug("%s: dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", __func__, + dt->hsync_len.typ, dt->hback_porch.typ, dt->hactive.typ, + dt->hfront_porch.typ, dpi_htot); + + log_debug("%s: dpi horiz timing (ns): %u + %u + %u + %u = %u\n", __func__, + tc358768_dpi_to_ns(dt->hsync_len.typ, dt->pixelclock.typ), + tc358768_dpi_to_ns(dt->hback_porch.typ, dt->pixelclock.typ), + tc358768_dpi_to_ns(dt->hactive.typ, dt->pixelclock.typ), + tc358768_dpi_to_ns(dt->hfront_porch.typ, dt->pixelclock.typ), + tc358768_dpi_to_ns(dpi_htot, dt->pixelclock.typ)); + + log_debug("%s: dpi data start (ns): %u + %u = %u\n", __func__, + tc358768_dpi_to_ns(dt->hsync_len.typ, dt->pixelclock.typ), + tc358768_dpi_to_ns(dt->hback_porch.typ, dt->pixelclock.typ), + tc358768_dpi_to_ns(dpi_data_start, dt->pixelclock.typ)); + + dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot); + dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); + + if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, dt->hsync_len.typ); + dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, dt->hback_porch.typ); + } else { + /* HBP is included in HSW in event mode */ + dsi_hbp = 0; + dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, + dt->hsync_len.typ + + dt->hback_porch.typ); + + /* + * The pixel packet includes the actual pixel data, and: + * DSI packet header = 4 bytes + * DCS code = 1 byte + * DSI packet footer = 2 bytes + */ + dsi_hact = hact + 4 + 1 + 2; + + dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; + + /* + * Here we should check if HFP is long enough for entering LP + * and exiting LP, but it's not clear how to calculate that. + * Instead, this is a naive algorithm that just adjusts the HFP + * and HSW so that HFP is (at least) roughly 2/3 of the total + * blanking time. + */ + if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { + u32 old_hfp = dsi_hfp; + u32 old_hsw = dsi_hsw; + u32 tot = dsi_hfp + dsi_hsw + dsi_hss; + + dsi_hsw = tot / 3; + + /* + * Seems like sometimes HSW has to be divisible by num-lanes, but + * not always... + */ + dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes); + + dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; + + log_debug("%s: hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", + __func__, old_hfp, old_hsw, dsi_hfp, dsi_hsw); + } + + log_debug("%s: dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", __func__, + dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, + dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); + + log_debug("%s: dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", __func__, + tc358768_dsi_bytes_to_ns(priv, dsi_hss), + tc358768_dsi_bytes_to_ns(priv, dsi_hsw), + tc358768_dsi_bytes_to_ns(priv, dsi_hbp), + tc358768_dsi_bytes_to_ns(priv, dsi_hact), + tc358768_dsi_bytes_to_ns(priv, dsi_hfp), + tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + + dsi_hbp + dsi_hact + dsi_hfp)); + } + + /* VSDly calculation */ + + /* Start with the HW internal delay */ + dsi_vsdly = internal_dly; + + /* Convert to byte units as the other variables are in byte units */ + dsi_vsdly *= priv->dsi_lanes; + + /* Do we need more delay, in addition to the internal? */ + if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { + dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; + dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes); + } + + log_debug("%s: dsi data start (bytes) %u + %u + %u + %u = %u\n", __func__, + dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, + dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); + + log_debug("%s: dsi data start (ns) %u + %u + %u + %u = %u\n", __func__, + tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), + tc358768_dsi_bytes_to_ns(priv, dsi_hss), + tc358768_dsi_bytes_to_ns(priv, dsi_hsw), + tc358768_dsi_bytes_to_ns(priv, dsi_hbp), + tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); + + /* Convert back to hsbyteclk */ + dsi_vsdly /= priv->dsi_lanes; + + /* + * The docs say that there is an internal delay of 40 cycles. + * However, we get underflows if we follow that rule. If we + * instead ignore the internal delay, things work. So either + * the docs are wrong or the calculations are wrong. + * + * As a temporary fix, add the internal delay here, to counter + * the subtraction when writing the register. + */ + dsi_vsdly += internal_dly; + + /* Clamp to the register max */ + if (dsi_vsdly - internal_dly > 0x3ff) { + log_warning("%s: VSDly too high, underflows likely\n", __func__); + dsi_vsdly = 0x3ff + internal_dly; + } + + /* VSDly[9:0] */ + tc358768_write(dev, TC358768_VSDLY, dsi_vsdly - internal_dly); + + tc358768_write(dev, TC358768_DATAFMT, val); + tc358768_write(dev, TC358768_DSITX_DT, data_type); + + /* Enable D-PHY (HiZ->LP11) */ + tc358768_write(dev, TC358768_CLW_CNTRL, 0x0000); + /* Enable lanes */ + for (i = 0; i < device->lanes; i++) + tc358768_write(dev, TC358768_D0W_CNTRL + i * 4, 0x0000); + + /* Set up D-PHY CONTTX */ + tc358768_write(dev, TC358768_CLW_DPHYCONTTX, 0x0203); + /* Adjust lanes */ + for (i = 0; i < device->lanes; i++) + tc358768_write(dev, TC358768_D0W_DPHYCONTTX + i * 4, 0x0203); + + /* DSI Timings */ + hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk); + dsiclk_ps = (u32)div_u64(PICO, dsiclk); + ui_ps = dsiclk_ps / 2; + log_debug("%s: dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", + __func__, dsiclk_ps, ui_ps, hsbyteclk_ps); + + /* LP11 > 100us for D-PHY Rx Init */ + val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; + log_debug("%s: LINEINITCNT: 0x%x\n", __func__, val); + tc358768_write(dev, TC358768_LINEINITCNT, val); + + /* LPTimeCnt > 50ns */ + val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; + lptxcnt = val; + log_debug("%s: LPTXTIMECNT: 0x%x\n", __func__, val); + tc358768_write(dev, TC358768_LPTXTIMECNT, val); + + /* 38ns < TCLK_PREPARE < 95ns */ + val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; + log_debug("%s: TCLK_PREPARECNT: 0x%x\n", __func__, val); + /* TCLK_PREPARE + TCLK_ZERO > 300ns */ + val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), + hsbyteclk_ps) - 2; + log_debug("%s: TCLK_ZEROCNT: 0x%x\n", __func__, val2); + val |= val2 << 8; + tc358768_write(dev, TC358768_TCLK_HEADERCNT, val); + + /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ + raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), + hsbyteclk_ps) - 5; + val = clamp(raw_val, 0, 127); + log_debug("%s: TCLK_TRAILCNT: 0x%x\n", __func__, val); + tc358768_write(dev, TC358768_TCLK_TRAILCNT, val); + + /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ + val = 50 + tc358768_ps_to_ns(4 * ui_ps); + val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; + log_debug("%s: THS_PREPARECNT: 0x%x\n", __func__, val); + /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ + raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), + hsbyteclk_ps) - 10; + val2 = clamp(raw_val, 0, 127); + log_debug("%s: THS_ZEROCNT: 0x%x\n", __func__, val2); + val |= val2 << 8; + tc358768_write(dev, TC358768_THS_HEADERCNT, val); + + /* TWAKEUP > 1ms in lptxcnt steps */ + val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps); + val = val / (lptxcnt + 1) - 1; + log_debug("%s: TWAKEUP: 0x%x\n", __func__, val); + tc358768_write(dev, TC358768_TWAKEUP, val); + + /* TCLK_POSTCNT > 60ns + 52*UI */ + val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), + hsbyteclk_ps) - 3; + log_debug("%s: TCLK_POSTCNT: 0x%x\n", __func__, val); + tc358768_write(dev, TC358768_TCLK_POSTCNT, val); + + /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ + raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), + hsbyteclk_ps) - 4; + val = clamp(raw_val, 0, 15); + log_debug("%s: THS_TRAILCNT: 0x%x\n", __func__, val); + tc358768_write(dev, TC358768_THS_TRAILCNT, val); + + val = BIT(0); + for (i = 0; i < device->lanes; i++) + val |= BIT(i + 1); + tc358768_write(dev, TC358768_HSTXVREGEN, val); + + tc358768_write(dev, TC358768_TXOPTIONCNTRL, + (device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); + + /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ + val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); + val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; + log_debug("%s: TXTAGOCNT: 0x%x\n", __func__, val); + val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps), + hsbyteclk_ps) - 2; + log_debug("%s: RXTASURECNT: 0x%x\n", __func__, val2); + val = val << 16 | val2; + tc358768_write(dev, TC358768_BTACNTRL1, val); + + /* START[0] */ + tc358768_write(dev, TC358768_STARTCNTRL, 1); + + if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + /* Set pulse mode */ + tc358768_write(dev, TC358768_DSI_EVENT, 0); + + /* vact */ + tc358768_write(dev, TC358768_DSI_VACT, dt->vactive.typ); + /* vsw */ + tc358768_write(dev, TC358768_DSI_VSW, dt->vsync_len.typ); + /* vbp */ + tc358768_write(dev, TC358768_DSI_VBPR, dt->vback_porch.typ); + } else { + /* Set event mode */ + tc358768_write(dev, TC358768_DSI_EVENT, 1); + + /* vact */ + tc358768_write(dev, TC358768_DSI_VACT, dt->vactive.typ); + + /* vsw (+ vbp) */ + tc358768_write(dev, TC358768_DSI_VSW, + dt->vsync_len.typ + dt->vback_porch.typ); + /* vbp (not used in event mode) */ + tc358768_write(dev, TC358768_DSI_VBPR, 0); + } + + /* hsw (bytes) */ + tc358768_write(dev, TC358768_DSI_HSW, dsi_hsw); + + /* hbp (bytes) */ + tc358768_write(dev, TC358768_DSI_HBPR, dsi_hbp); + + /* hact (bytes) */ + tc358768_write(dev, TC358768_DSI_HACT, hact); + + /* VSYNC polarity */ + tc358768_update_bits(dev, TC358768_CONFCTL, BIT(5), + (dt->flags & DISPLAY_FLAGS_VSYNC_HIGH) ? BIT(5) : 0); + + /* HSYNC polarity */ + tc358768_update_bits(dev, TC358768_PP_MISC, BIT(0), + (dt->flags & DISPLAY_FLAGS_HSYNC_LOW) ? BIT(0) : 0); + + /* Start DSI Tx */ + tc358768_write(dev, TC358768_DSI_START, 0x1); + + /* Configure DSI_Control register */ + val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; + val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | + 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; + tc358768_write(dev, TC358768_DSI_CONFW, val); + + val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; + val |= (device->lanes - 1) << 1; + + val |= TC358768_DSI_CONTROL_TXMD; + + if (!(device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + val |= TC358768_DSI_CONTROL_HSCKMD; + + /* + * TODO: Actually MIPI_DSI_MODE_NO_EOT_PACKET + * + * Many of the DSI flags have names opposite to their + * actual effects, e.g. MIPI_DSI_MODE_EOT_PACKET means + * that EoT packets will actually be disabled. + */ + if (device->mode_flags & MIPI_DSI_MODE_EOT_PACKET) + val |= TC358768_DSI_CONTROL_EOTDIS; + + tc358768_write(dev, TC358768_DSI_CONFW, val); + + val = TC358768_DSI_CONFW_MODE_CLR | + TC358768_DSI_CONFW_ADDR_DSI_CONTROL | + TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ + tc358768_write(dev, TC358768_DSI_CONFW, val); + + /* clear FrmStop and RstPtr */ + tc358768_update_bits(dev, TC358768_PP_MISC, 0x3 << 14, 0); + + /* set PP_en */ + tc358768_update_bits(dev, TC358768_CONFCTL, BIT(6), BIT(6)); + + /* Set up panel configuration */ + return panel_enable_backlight(priv->panel); +} + +static int tc358768_set_backlight(struct udevice *dev, int percent) +{ + struct tc358768_priv *priv = dev_get_priv(dev); + + return panel_set_backlight(priv->panel, percent); +} + +static int tc358768_panel_timings(struct udevice *dev, + struct display_timing *timing) +{ + struct tc358768_priv *priv = dev_get_priv(dev); + + /* Default to positive sync */ + + if (!(priv->timing.flags & + (DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_HSYNC_HIGH))) + priv->timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH; + + if (!(priv->timing.flags & + (DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH))) + priv->timing.flags |= DISPLAY_FLAGS_VSYNC_HIGH; + + memcpy(timing, &priv->timing, sizeof(*timing)); + + return 0; +} + +static int tc358768_setup(struct udevice *dev) +{ + struct tc358768_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct mipi_dsi_panel_plat *mipi_plat; + int ret; + + /* The bridge uses 16 bit registers */ + ret = i2c_set_chip_offset_len(dev, 2); + if (ret) { + log_debug("%s: set_chip_offset_len failed: %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "panel", &priv->panel); + if (ret) { + log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret); + return log_ret(ret); + } + + panel_get_display_timing(priv->panel, &priv->timing); + + mipi_plat = dev_get_plat(priv->panel); + mipi_plat->device = device; + + priv->host.dev = (struct device *)dev; + priv->host.ops = &tc358768_dsi_host_ops; + + device->host = &priv->host; + device->lanes = mipi_plat->lanes; + device->format = mipi_plat->format; + device->mode_flags = mipi_plat->mode_flags; + + priv->pd_lines = mipi_dsi_pixel_format_to_bpp(device->format); + priv->dsi_lanes = device->lanes; + + /* get regulators */ + ret = device_get_supply_regulator(dev, "vddc-supply", &priv->vddc); + if (ret) { + log_debug("%s: vddc regulator error: %d\n", __func__, ret); + if (ret != -ENOENT) + return log_ret(ret); + } + + ret = device_get_supply_regulator(dev, "vddmipi-supply", &priv->vddmipi); + if (ret) { + log_debug("%s: vddmipi regulator error: %d\n", __func__, ret); + if (ret != -ENOENT) + return log_ret(ret); + } + + ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio); + if (ret) { + log_debug("%s: vddio regulator error: %d\n", __func__, ret); + if (ret != -ENOENT) + return log_ret(ret); + } + + /* get clk */ + priv->refclk = devm_clk_get(dev, "refclk"); + if (IS_ERR(priv->refclk)) { + log_debug("%s: Could not get refclk: %ld\n", + __func__, PTR_ERR(priv->refclk)); + return PTR_ERR(priv->refclk); + } + + /* get gpios */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret); + return ret; + } + + dm_gpio_set_value(&priv->reset_gpio, 1); + + return 0; +} + +static int tc358768_probe(struct udevice *dev) +{ + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + return tc358768_setup(dev); +} + +struct panel_ops tc358768_ops = { + .enable_backlight = tc358768_attach, + .set_backlight = tc358768_set_backlight, + .get_display_timing = tc358768_panel_timings, +}; + +static const struct udevice_id tc358768_ids[] = { + { .compatible = "toshiba,tc358768" }, + { .compatible = "toshiba,tc358778" }, + { } +}; + +U_BOOT_DRIVER(tc358768) = { + .name = "tc358768", + .id = UCLASS_PANEL, + .of_match = tc358768_ids, + .ops = &tc358768_ops, + .probe = tc358768_probe, + .priv_auto = sizeof(struct tc358768_priv), +}; diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index c4fbb182944..c217af97878 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -78,10 +78,10 @@ static void dw_hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset) { switch (hdmi->reg_io_width) { case 1: - writeb(val, hdmi->ioaddr + offset); + writeb(val, (void *)(hdmi->ioaddr + offset)); break; case 4: - writel(val, hdmi->ioaddr + (offset << 2)); + writel(val, (void *)(hdmi->ioaddr + (offset << 2))); break; default: debug("reg_io_width has unsupported width!\n"); @@ -93,9 +93,9 @@ static u8 dw_hdmi_read(struct dw_hdmi *hdmi, int offset) { switch (hdmi->reg_io_width) { case 1: - return readb(hdmi->ioaddr + offset); + return readb((void *)(hdmi->ioaddr + offset)); case 4: - return readl(hdmi->ioaddr + (offset << 2)); + return readl((void *)(hdmi->ioaddr + (offset << 2))); default: debug("reg_io_width has unsupported width!\n"); break; @@ -936,6 +936,22 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi) return -1; } +int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi) +{ + int ret; + + ret = dw_hdmi_phy_wait_for_hpd(hdmi); + if (ret < 0) { + debug("hdmi can not get hpd signal\n"); + return -ENODEV; + } + + if (hdmi->ops && hdmi->ops->read_hpd) + hdmi->ops->read_hpd(hdmi, true); + + return 0; +} + void dw_hdmi_phy_init(struct dw_hdmi *hdmi) { /* enable phy i2cm done irq */ @@ -988,7 +1004,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) hdmi_av_composer(hdmi, edid); - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ); if (ret) return ret; @@ -1009,10 +1025,18 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) return 0; } +static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { + .phy_set = dw_hdmi_phy_cfg, +}; + void dw_hdmi_init(struct dw_hdmi *hdmi) { uint ih_mute; + /* hook Synopsys PHYs ops */ + if (!hdmi->ops) + hdmi->ops = &dw_hdmi_synopsys_phy_ops; + /* * boot up defaults are: * hdmi_ih_mute = 0x03 (disabled) @@ -1037,4 +1061,7 @@ void dw_hdmi_init(struct dw_hdmi *hdmi) /* enable i2c client nack % arbitration error irq */ hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT); + + if (hdmi->ops && hdmi->ops->setup_hpd) + hdmi->ops->setup_hpd(hdmi); } diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c index 79a272128b8..1bff641434e 100644 --- a/drivers/video/endeavoru-panel.c +++ b/drivers/video/endeavoru-panel.c @@ -57,61 +57,8 @@ static void dcs_write_one(struct mipi_dsi_device *dsi, u8 cmd, u8 data) static int endeavoru_panel_enable_backlight(struct udevice *dev) { - struct endeavoru_panel_priv *priv = dev_get_priv(dev); - int ret; - - ret = dm_gpio_set_value(&priv->reset_gpio, 1); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(5); - - ret = regulator_set_enable_if_allowed(priv->vddio, 1); - if (ret) { - log_err("error enabling iovcc-supply (%d)\n", ret); - return ret; - } - mdelay(1); - - ret = regulator_set_enable_if_allowed(priv->vdd, 1); - if (ret) { - log_err("error enabling vcc-supply (%d)\n", ret); - return ret; - } - mdelay(20); - - ret = dm_gpio_set_value(&priv->reset_gpio, 0); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(2); - - /* Reset panel */ - ret = dm_gpio_set_value(&priv->reset_gpio, 1); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(1); - - ret = dm_gpio_set_value(&priv->reset_gpio, 0); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(25); - - return 0; -} - -static int endeavoru_panel_set_backlight(struct udevice *dev, int percent) -{ - struct endeavoru_panel_priv *priv = dev_get_priv(dev); struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); struct mipi_dsi_device *dsi = plat->device; - int ret; dcs_write_one(dsi, 0xc2, 0x08); @@ -160,18 +107,22 @@ static int endeavoru_panel_set_backlight(struct udevice *dev, int percent) dcs_write_one(dsi, 0x55, 0x80); dcs_write_one(dsi, 0x5e, 0x06); - ret = backlight_enable(priv->backlight); - if (ret) - return ret; - /* Set backlight */ dcs_write_one(dsi, 0x51, 0x96); - ret = backlight_set_brightness(priv->backlight, percent); + return 0; +} + +static int endeavoru_panel_set_backlight(struct udevice *dev, int percent) +{ + struct endeavoru_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = backlight_enable(priv->backlight); if (ret) return ret; - return 0; + return backlight_set_brightness(priv->backlight, percent); } static int endeavoru_panel_timings(struct udevice *dev, @@ -217,6 +168,63 @@ static int endeavoru_panel_of_to_plat(struct udevice *dev) return 0; } +static int endeavoru_panel_hw_init(struct udevice *dev) +{ + struct endeavoru_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(5); + + ret = regulator_set_enable_if_allowed(priv->vddio, 1); + if (ret) { + log_debug("%s: error enabling iovcc-supply (%d)\n", + __func__, ret); + return ret; + } + mdelay(1); + + ret = regulator_set_enable_if_allowed(priv->vdd, 1); + if (ret) { + log_debug("%s: error enabling vcc-supply (%d)\n", + __func__, ret); + return ret; + } + mdelay(20); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(2); + + /* Reset panel */ + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(1); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(25); + + return 0; +} + static int endeavoru_panel_probe(struct udevice *dev) { struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); @@ -226,7 +234,7 @@ static int endeavoru_panel_probe(struct udevice *dev) plat->format = MIPI_DSI_FMT_RGB888; plat->mode_flags = MIPI_DSI_MODE_VIDEO; - return 0; + return endeavoru_panel_hw_init(dev); } static const struct panel_ops endeavoru_panel_ops = { diff --git a/drivers/video/lg-ld070wx3.c b/drivers/video/lg-ld070wx3.c new file mode 100644 index 00000000000..610a06ffe7b --- /dev/null +++ b/drivers/video/lg-ld070wx3.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * LG LD070WX3-SL01 DSI panel driver + * + * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <mipi_dsi.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct lg_ld070wx3_priv { + struct udevice *vdd; + struct udevice *vcc; + + struct udevice *backlight; +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 70000000, + .hactive.typ = 800, + .hfront_porch.typ = 32, + .hback_porch.typ = 48, + .hsync_len.typ = 8, + .vactive.typ = 1280, + .vfront_porch.typ = 5, + .vback_porch.typ = 3, + .vsync_len.typ = 1, +}; + +static void dcs_write_one(struct mipi_dsi_device *dsi, u8 cmd, u8 data) +{ + mipi_dsi_dcs_write(dsi, cmd, &data, 1); +} + +static int lg_ld070wx3_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + int ret; + + ret = mipi_dsi_dcs_soft_reset(dsi); + if (ret < 0) { + log_debug("%s: failed to soft reset panel: %d\n", + __func__, ret); + return ret; + } + + /* Delay before sending new command after soft reset */ + mdelay(20); + + /* Differential input impedance selection */ + dcs_write_one(dsi, 0xAE, 0x0B); + + /* Enter test mode 1 and 2*/ + dcs_write_one(dsi, 0xEE, 0xEA); + dcs_write_one(dsi, 0xEF, 0x5F); + + /* Increased MIPI CLK driving ability */ + dcs_write_one(dsi, 0xF2, 0x68); + + /* Exit test mode 1 and 2 */ + dcs_write_one(dsi, 0xEE, 0x00); + dcs_write_one(dsi, 0xEF, 0x00); + + return 0; +} + +static int lg_ld070wx3_set_backlight(struct udevice *dev, int percent) +{ + struct lg_ld070wx3_priv *priv = dev_get_priv(dev); + int ret; + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + return backlight_set_brightness(priv->backlight, percent); +} + +static int lg_ld070wx3_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int lg_ld070wx3_of_to_plat(struct udevice *dev) +{ + struct lg_ld070wx3_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_debug("%s: cannot get backlight: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "vdd-supply", &priv->vdd); + if (ret) { + log_debug("%s: cannot get vdd-supply: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "vcc-supply", &priv->vcc); + if (ret) { + log_debug("%s: cannot get vcc-supply: ret = %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int lg_ld070wx3_hw_init(struct udevice *dev) +{ + struct lg_ld070wx3_priv *priv = dev_get_priv(dev); + int ret; + + ret = regulator_set_enable_if_allowed(priv->vcc, 1); + if (ret) { + log_debug("%s: enabling vcc-supply failed (%d)\n", + __func__, ret); + return ret; + } + + ret = regulator_set_enable_if_allowed(priv->vdd, 1); + if (ret) { + log_debug("%s: enabling vdd-supply failed (%d)\n", + __func__, ret); + return ret; + } + + /* + * According to spec delay between enabling supply is 0, + * for regulators to reach required voltage ~5ms needed. + * MIPI interface signal for setup requires additional + * 110ms which in total results in 115ms. + */ + mdelay(115); + + return 0; +} + +static int lg_ld070wx3_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO; + + return lg_ld070wx3_hw_init(dev); +} + +static const struct panel_ops lg_ld070wx3_ops = { + .enable_backlight = lg_ld070wx3_enable_backlight, + .set_backlight = lg_ld070wx3_set_backlight, + .get_display_timing = lg_ld070wx3_timings, +}; + +static const struct udevice_id lg_ld070wx3_ids[] = { + { .compatible = "lg,ld070wx3-sl01" }, + { } +}; + +U_BOOT_DRIVER(lg_ld070wx3) = { + .name = "lg_ld070wx3", + .id = UCLASS_PANEL, + .of_match = lg_ld070wx3_ids, + .ops = &lg_ld070wx3_ops, + .of_to_plat = lg_ld070wx3_of_to_plat, + .probe = lg_ld070wx3_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct lg_ld070wx3_priv), +}; diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 5db01904b53..259af1b4571 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -375,6 +375,10 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi) return -ETIMEDOUT; } +static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = { + .phy_set = meson_dw_hdmi_phy_init, +}; + static int meson_dw_hdmi_probe(struct udevice *dev) { struct meson_dw_hdmi *priv = dev_get_priv(dev); @@ -397,7 +401,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev) priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24; - priv->hdmi.phy_set = meson_dw_hdmi_phy_init; + priv->hdmi.ops = &dw_hdmi_meson_phy_ops; if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) priv->hdmi.reg_io_width = 1; else { diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c index 426fdc6224a..3f5859055c9 100644 --- a/drivers/video/renesas-r61307.c +++ b/drivers/video/renesas-r61307.c @@ -19,7 +19,7 @@ #include <power/regulator.h> /* - * The datasheet is not publicly available, all values are + * The datasheet is not publicly available, all values are * taken from the downstream. If you have access to datasheets, * corrections are welcome. */ @@ -120,42 +120,6 @@ static struct display_timing default_timing = { static int renesas_r61307_enable_backlight(struct udevice *dev) { struct renesas_r61307_priv *priv = dev_get_priv(dev); - int ret; - - ret = regulator_set_enable_if_allowed(priv->vcc, 1); - if (ret) { - log_err("enabling vcc-supply failed (%d)\n", ret); - return ret; - } - mdelay(5); - - ret = regulator_set_enable_if_allowed(priv->iovcc, 1); - if (ret) { - log_err("enabling iovcc-supply failed (%d)\n", ret); - return ret; - } - - ret = dm_gpio_set_value(&priv->reset_gpio, 0); - if (ret) { - log_err("changing reset-gpio failed (%d)\n", ret); - return ret; - } - mdelay(5); - - ret = dm_gpio_set_value(&priv->reset_gpio, 1); - if (ret) { - log_err("changing reset-gpio failed (%d)\n", ret); - return ret; - } - - mdelay(5); - - return 0; -} - -static int renesas_r61307_set_backlight(struct udevice *dev, int percent) -{ - struct renesas_r61307_priv *priv = dev_get_priv(dev); struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); struct mipi_dsi_device *dsi = plat->device; int ret; @@ -205,18 +169,23 @@ static int renesas_r61307_set_backlight(struct udevice *dev, int percent) log_err("failed to set display on: %d\n", ret); return ret; } - mdelay(50); + return 0; +} + +static int renesas_r61307_set_backlight(struct udevice *dev, int percent) +{ + struct renesas_r61307_priv *priv = dev_get_priv(dev); + int ret; + ret = backlight_enable(priv->backlight); if (ret) return ret; - ret = backlight_set_brightness(priv->backlight, percent); - if (ret) - return ret; + mdelay(5); - return 0; + return backlight_set_brightness(priv->backlight, percent); } static int renesas_r61307_timings(struct udevice *dev, @@ -266,6 +235,46 @@ static int renesas_r61307_of_to_plat(struct udevice *dev) return 0; } +static int renesas_r61307_hw_init(struct udevice *dev) +{ + struct renesas_r61307_priv *priv = dev_get_priv(dev); + int ret; + + ret = regulator_set_enable_if_allowed(priv->vcc, 1); + if (ret) { + log_debug("%s: enabling vcc-supply failed (%d)\n", + __func__, ret); + return ret; + } + mdelay(5); + + ret = regulator_set_enable_if_allowed(priv->iovcc, 1); + if (ret) { + log_debug("%s: enabling iovcc-supply failed (%d)\n", + __func__, ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: changing reset-gpio failed (%d)\n", + __func__, ret); + return ret; + } + mdelay(5); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: changing reset-gpio failed (%d)\n", + __func__, ret); + return ret; + } + + mdelay(5); + + return 0; +} + static int renesas_r61307_probe(struct udevice *dev) { struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); @@ -275,7 +284,7 @@ static int renesas_r61307_probe(struct udevice *dev) plat->format = MIPI_DSI_FMT_RGB888; plat->mode_flags = MIPI_DSI_MODE_VIDEO; - return 0; + return renesas_r61307_hw_init(dev); } static const struct panel_ops renesas_r61307_ops = { diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c index d2f71694681..082f5bc3d0a 100644 --- a/drivers/video/renesas-r69328.c +++ b/drivers/video/renesas-r69328.c @@ -19,7 +19,7 @@ #include <power/regulator.h> /* - * The datasheet is not publicly available, all values are + * The datasheet is not publicly available, all values are * taken from the downstream. If you have access to datasheets, * corrections are welcome. */ @@ -65,37 +65,6 @@ static struct display_timing default_timing = { static int renesas_r69328_enable_backlight(struct udevice *dev) { - struct renesas_r69328_priv *priv = dev_get_priv(dev); - int ret; - - ret = dm_gpio_set_value(&priv->enable_gpio, 1); - if (ret) { - log_err("error changing enable-gpios (%d)\n", ret); - return ret; - } - mdelay(5); - - ret = dm_gpio_set_value(&priv->reset_gpio, 0); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - mdelay(5); - - ret = dm_gpio_set_value(&priv->reset_gpio, 1); - if (ret) { - log_err("error changing reset-gpios (%d)\n", ret); - return ret; - } - - mdelay(5); - - return 0; -} - -static int renesas_r69328_set_backlight(struct udevice *dev, int percent) -{ - struct renesas_r69328_priv *priv = dev_get_priv(dev); struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); struct mipi_dsi_device *dsi = plat->device; int ret; @@ -153,18 +122,23 @@ static int renesas_r69328_set_backlight(struct udevice *dev, int percent) log_err("failed to set display on: %d\n", ret); return ret; } - mdelay(50); + return 0; +} + +static int renesas_r69328_set_backlight(struct udevice *dev, int percent) +{ + struct renesas_r69328_priv *priv = dev_get_priv(dev); + int ret; + ret = backlight_enable(priv->backlight); if (ret) return ret; - ret = backlight_set_brightness(priv->backlight, percent); - if (ret) - return ret; + mdelay(5); - return 0; + return backlight_set_brightness(priv->backlight, percent); } static int renesas_r69328_timings(struct udevice *dev, @@ -203,6 +177,39 @@ static int renesas_r69328_of_to_plat(struct udevice *dev) return 0; } +static int renesas_r69328_hw_init(struct udevice *dev) +{ + struct renesas_r69328_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->enable_gpio, 1); + if (ret) { + log_debug("%s: error changing enable-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(5); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + mdelay(5); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error changing reset-gpios (%d)\n", + __func__, ret); + return ret; + } + + mdelay(5); + + return 0; +} + static int renesas_r69328_probe(struct udevice *dev) { struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); @@ -212,7 +219,7 @@ static int renesas_r69328_probe(struct udevice *dev) plat->format = MIPI_DSI_FMT_RGB888; plat->mode_flags = MIPI_DSI_MODE_VIDEO; - return 0; + return renesas_r69328_hw_init(dev); } static const struct panel_ops renesas_r69328_ops = { diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 8128289cc82..f55beceebf1 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -6,10 +6,12 @@ ifdef CONFIG_VIDEO_ROCKCHIP obj-y += rk_vop.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o +obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o +obj-hdmi-$(CONFIG_ROCKCHIP_RK3328) += rk3328_hdmi.o obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y) obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o diff --git a/drivers/video/rockchip/rk3328_hdmi.c b/drivers/video/rockchip/rk3328_hdmi.c new file mode 100644 index 00000000000..763669c09be --- /dev/null +++ b/drivers/video/rockchip/rk3328_hdmi.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <clk.h> +#include <display.h> +#include <dm.h> +#include <dw_hdmi.h> +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include "rk_hdmi.h" + +#define RK3328_IO_3V_DOMAIN (7 << (9 + 16)) +#define RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16))) +#define RK3328_IO_DDC_IN_MSK ((3 << 10) | (3 << (10 + 16))) +#define RK3328_IO_CTRL_BY_HDMI ((1 << 13) | (1 << (13 + 16))) + +static int rk3328_hdmi_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *edid) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + + return dw_hdmi_enable(&priv->hdmi, edid); +} + +static int rk3328_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint pixclock) +{ + struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); + int ret; + + ret = generic_phy_init(&priv->phy); + if (ret) { + printf("failed to init phy (ret=%d)\n", ret); + return ret; + } + + ret = generic_phy_power_on(&priv->phy); + if (ret) { + printf("failed to power on phy (ret=%d)\n", ret); + return ret; + } + + return 0; +} + +static void rk3328_dw_hdmi_setup_hpd(struct dw_hdmi *hdmi) +{ + struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); + struct rk3328_grf_regs *grf = priv->grf; + + writel(RK3328_IO_DDC_IN_MSK, &grf->soc_con[2]); + writel(RK3328_IO_CTRL_BY_HDMI, &grf->soc_con[3]); +} + +static void rk3328_dw_hdmi_read_hpd(struct dw_hdmi *hdmi, bool hpd_status) +{ + struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv, hdmi); + struct rk3328_grf_regs *grf = priv->grf; + + if (hpd_status) + writel(RK3328_IO_5V_DOMAIN, &grf->soc_con[4]); + else + writel(RK3328_IO_3V_DOMAIN, &grf->soc_con[4]); +} + +static const struct dw_hdmi_phy_ops dw_hdmi_rk3328_phy_ops = { + .phy_set = rk3328_dw_hdmi_phy_cfg, + .setup_hpd = rk3328_dw_hdmi_setup_hpd, + .read_hpd = rk3328_dw_hdmi_read_hpd, +}; + +static int rk3328_hdmi_of_to_plat(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; + + hdmi->i2c_clk_high = 0x71; + hdmi->i2c_clk_low = 0x76; + + rk_hdmi_of_to_plat(dev); + + hdmi->ops = &dw_hdmi_rk3328_phy_ops; + + return 0; +} + +static int rk3328_hdmi_probe(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + int ret; + + ret = generic_phy_get_by_name(dev, "hdmi", &priv->phy); + if (ret) { + printf("failed to get hdmi phy\n"); + return ret; + }; + + ret = rk_hdmi_probe(dev); + if (ret) { + printf("failed to probe rk hdmi\n"); + return ret; + } + + return 0; +} + +static const struct dm_display_ops rk3328_hdmi_ops = { + .read_edid = rk_hdmi_read_edid, + .enable = rk3328_hdmi_enable, +}; + +static const struct udevice_id rk3328_hdmi_ids[] = { + { .compatible = "rockchip,rk3328-dw-hdmi" }, + { } +}; + +U_BOOT_DRIVER(rk3328_hdmi_rockchip) = { + .name = "rk3328_hdmi_rockchip", + .id = UCLASS_DISPLAY, + .of_match = rk3328_hdmi_ids, + .ops = &rk3328_hdmi_ops, + .of_to_plat = rk3328_hdmi_of_to_plat, + .probe = rk3328_hdmi_probe, + .priv_auto = sizeof(struct rk_hdmi_priv), +}; diff --git a/drivers/video/rockchip/rk3328_vop.c b/drivers/video/rockchip/rk3328_vop.c new file mode 100644 index 00000000000..55233f19eeb --- /dev/null +++ b/drivers/video/rockchip/rk3328_vop.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <dm.h> +#include <video.h> +#include <asm/io.h> +#include "rk_vop.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void rk3328_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + switch (mode) { + case VOP_MODE_HDMI: + clrsetbits_le32(®s->dsp_ctrl1, + M_RK3399_DSP_HDMI_POL, + V_RK3399_DSP_HDMI_POL(polarity)); + break; + default: + debug("%s: unsupported output mode %x\n", __func__, mode); + } +} + +static int rk3328_vop_probe(struct udevice *dev) +{ + /* Before relocation we don't need to do anything */ + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + return rk_vop_probe(dev); +} + +static int rk3328_vop_remove(struct udevice *dev) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + struct rk3288_vop *win_regs = priv->regs + priv->win_offset; + + /* FIXME: Explicit disabling of WIN0 is needed to avoid iommu + * page-fault in Linux, better handling of iommu-address in + * Linux might drop this. + */ + clrbits_le32(&win_regs->win0_ctrl0, M_WIN0_EN); + writel(0x01, ®s->reg_cfg_done); + + return 0; +} + +struct rkvop_driverdata rk3328_driverdata = { + .dsp_offset = 0x490, + .win_offset = 0xd0, + .features = VOP_FEATURE_OUTPUT_10BIT, + .set_pin_polarity = rk3328_set_pin_polarity, +}; + +static const struct udevice_id rk3328_vop_ids[] = { + { + .compatible = "rockchip,rk3328-vop", + .data = (ulong)&rk3328_driverdata + }, + { /* sentile */ } +}; + +static const struct video_ops rk3328_vop_ops = { +}; + +U_BOOT_DRIVER(rk3328_vop) = { + .name = "rk3328_vop", + .id = UCLASS_VIDEO, + .of_match = rk3328_vop_ids, + .ops = &rk3328_vop_ops, + .bind = rk_vop_bind, + .probe = rk3328_vop_probe, + .remove = rk3328_vop_remove, + .priv_auto = sizeof(struct rk_vop_priv), + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 044a29ee47a..d31f6a4ff81 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -89,7 +89,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev) /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */ hdmi->reg_io_width = 4; - hdmi->phy_set = dw_hdmi_phy_cfg; priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); @@ -111,14 +110,12 @@ int rk_hdmi_probe(struct udevice *dev) struct dw_hdmi *hdmi = &priv->hdmi; int ret; - ret = dw_hdmi_phy_wait_for_hpd(hdmi); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } - dw_hdmi_init(hdmi); dw_hdmi_phy_init(hdmi); + ret = dw_hdmi_detect_hpd(hdmi); + if (ret < 0) + return ret; + return 0; } diff --git a/drivers/video/rockchip/rk_hdmi.h b/drivers/video/rockchip/rk_hdmi.h index 200dbaea740..dcfba3d3d7e 100644 --- a/drivers/video/rockchip/rk_hdmi.h +++ b/drivers/video/rockchip/rk_hdmi.h @@ -6,6 +6,8 @@ #ifndef __RK_HDMI_H__ #define __RK_HDMI_H__ +#include <generic-phy.h> + struct rkhdmi_driverdata { /* configuration */ u8 i2c_clk_high; @@ -19,6 +21,7 @@ struct rkhdmi_driverdata { struct rk_hdmi_priv { struct dw_hdmi hdmi; + struct phy phy; void *grf; }; diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index c514e2a0e44..acc02e5d7c7 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -39,11 +39,14 @@ enum vop_pol { DCLK_INVERT = 3 }; -static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong fbbase, +static void rkvop_enable(struct udevice *dev, ulong fbbase, int fb_bits_per_pixel, const struct display_timing *edid, struct reset_ctl *dclk_rst) { + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + struct rk3288_vop *win_regs = priv->regs + priv->win_offset; u32 lb_mode; u32 rgb_mode; u32 hactive = edid->hactive.typ; @@ -51,32 +54,32 @@ static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong fbb int ret; writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), - ®s->win0_act_info); + &win_regs->win0_act_info); writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), - ®s->win0_dsp_st); + &win_regs->win0_dsp_st); writel(V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1), - ®s->win0_dsp_info); + &win_regs->win0_dsp_info); - clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, + clrsetbits_le32(&win_regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); switch (fb_bits_per_pixel) { case 16: rgb_mode = RGB565; - writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir); + writel(V_RGB565_VIRWIDTH(hactive), &win_regs->win0_vir); break; case 24: rgb_mode = RGB888; - writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir); + writel(V_RGB888_VIRWIDTH(hactive), &win_regs->win0_vir); break; case 32: default: rgb_mode = ARGB8888; - writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir); + writel(V_ARGB888_VIRWIDTH(hactive), &win_regs->win0_vir); break; } @@ -89,12 +92,12 @@ static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong fbb else lb_mode = LB_RGB_1280X8; - clrsetbits_le32(®s->win0_ctrl0, + clrsetbits_le32(&win_regs->win0_ctrl0, M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); - writel(fbbase, ®s->win0_yrgb_mst); + writel(fbbase, &win_regs->win0_yrgb_mst); writel(0x01, ®s->reg_cfg_done); /* enable reg config */ ret = reset_assert(dclk_rst); @@ -162,6 +165,7 @@ static void rkvop_mode_set(struct udevice *dev, { struct rk_vop_priv *priv = dev_get_priv(dev); struct rk3288_vop *regs = priv->regs; + struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset; struct rkvop_driverdata *data = (struct rkvop_driverdata *)dev_get_driver_data(dev); @@ -195,27 +199,27 @@ static void rkvop_mode_set(struct udevice *dev, writel(V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), - ®s->dsp_htotal_hs_end); + &dsp_regs->dsp_htotal_hs_end); writel(V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch), - ®s->dsp_hact_st_end); + &dsp_regs->dsp_hact_st_end); writel(V_VSYNC(vsync_len) | V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), - ®s->dsp_vtotal_vs_end); + &dsp_regs->dsp_vtotal_vs_end); writel(V_VAEP(vsync_len + vback_porch + vactive)| V_VASP(vsync_len + vback_porch), - ®s->dsp_vact_st_end); + &dsp_regs->dsp_vact_st_end); writel(V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch), - ®s->post_dsp_hact_info); + &dsp_regs->post_dsp_hact_info); writel(V_VAEP(vsync_len + vback_porch + vactive)| V_VASP(vsync_len + vback_porch), - ®s->post_dsp_vact_info); + &dsp_regs->post_dsp_vact_info); writel(0x01, ®s->reg_cfg_done); /* enable reg config */ } @@ -243,9 +247,7 @@ static void rkvop_mode_set(struct udevice *dev, static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct rk_vop_priv *priv = dev_get_priv(dev); int vop_id, remote_vop_id; - struct rk3288_vop *regs = priv->regs; struct display_timing timing; struct udevice *disp; int ret; @@ -380,7 +382,7 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) return ret; } - rkvop_enable(dev, regs, fbbase, 1 << l2bpp, &timing, &dclk_rst); + rkvop_enable(dev, fbbase, 1 << l2bpp, &timing, &dclk_rst); ret = display_enable(disp, 1 << l2bpp, &timing); if (ret) @@ -415,6 +417,8 @@ int rk_vop_probe(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct rk_vop_priv *priv = dev_get_priv(dev); + struct rkvop_driverdata *ops = + (struct rkvop_driverdata *)dev_get_driver_data(dev); int ret = 0; ofnode port, node; struct reset_ctl ahb_rst; @@ -448,6 +452,8 @@ int rk_vop_probe(struct udevice *dev) #endif priv->regs = dev_read_addr_ptr(dev); + priv->win_offset = ops->win_offset; + priv->dsp_offset = ops->dsp_offset; /* * Try all the ports until we find one that works. In practice this diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h index 0528fb23f59..eba68d87c4b 100644 --- a/drivers/video/rockchip/rk_vop.h +++ b/drivers/video/rockchip/rk_vop.h @@ -11,6 +11,8 @@ struct rk_vop_priv { void *grf; void *regs; + int win_offset; + int dsp_offset; }; enum vop_features { @@ -18,6 +20,8 @@ enum vop_features { }; struct rkvop_driverdata { + int win_offset; + int dsp_offset; /* configuration */ u32 features; /* block-specific setters/getters */ diff --git a/drivers/video/samsung-ltl106hl02.c b/drivers/video/samsung-ltl106hl02.c new file mode 100644 index 00000000000..5e6c11c4be3 --- /dev/null +++ b/drivers/video/samsung-ltl106hl02.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung LTL106HL02-001 DSI panel driver + * + * Copyright (c) 2020 Anton Bambura <jenneron@protonmail.com> + * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + * Copyright (c) 2024 Jonas Schwöbel <jonasschwoebel@yahoo.de> + */ + +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <mipi_dsi.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct samsung_ltl106hl02_priv { + struct udevice *vdd; + struct udevice *backlight; + + struct gpio_desc reset_gpio; +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 137000000, + .hactive.typ = 1920, + .hfront_porch.typ = 32, + .hback_porch.typ = 64, + .hsync_len.typ = 32, + .vactive.typ = 1080, + .vfront_porch.typ = 2, + .vback_porch.typ = 26, + .vsync_len.typ = 3, +}; + +static int samsung_ltl106hl02_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + int ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + log_debug("%s: failed to exit sleep mode: %d\n", + __func__, ret); + return ret; + } + mdelay(70); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + log_debug("%s: failed to enable display: %d\n", + __func__, ret); + return ret; + } + mdelay(5); + + return 0; +} + +static int samsung_ltl106hl02_set_backlight(struct udevice *dev, int percent) +{ + struct samsung_ltl106hl02_priv *priv = dev_get_priv(dev); + int ret; + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + return backlight_set_brightness(priv->backlight, percent); +} + +static int samsung_ltl106hl02_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int samsung_ltl106hl02_of_to_plat(struct udevice *dev) +{ + struct samsung_ltl106hl02_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_debug("%s: cannot get backlight: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "vdd-supply", &priv->vdd); + if (ret) + log_debug("%s: cannot get vdd-supply: error %d\n", + __func__, ret); + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) + log_debug("%s: cannot get reset-gpios: error %d\n", + __func__, ret); + + return 0; +} + +static int samsung_ltl106hl02_hw_init(struct udevice *dev) +{ + struct samsung_ltl106hl02_priv *priv = dev_get_priv(dev); + + dm_gpio_set_value(&priv->reset_gpio, 1); + regulator_set_enable_if_allowed(priv->vdd, 1); + + /* Dataheets states at least 8.5 msec for vdd stabilization */ + mdelay(10); + + dm_gpio_set_value(&priv->reset_gpio, 0); + + return 0; +} + +static int samsung_ltl106hl02_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO; + + return samsung_ltl106hl02_hw_init(dev); +} + +static const struct panel_ops samsung_ltl106hl02_ops = { + .enable_backlight = samsung_ltl106hl02_enable_backlight, + .set_backlight = samsung_ltl106hl02_set_backlight, + .get_display_timing = samsung_ltl106hl02_timings, +}; + +static const struct udevice_id samsung_ltl106hl02_ids[] = { + { .compatible = "samsung,ltl106hl02-001" }, + { } +}; + +U_BOOT_DRIVER(samsung_ltl106hl02) = { + .name = "samsung_ltl106hl02", + .id = UCLASS_PANEL, + .of_match = samsung_ltl106hl02_ids, + .ops = &samsung_ltl106hl02_ops, + .of_to_plat = samsung_ltl106hl02_of_to_plat, + .probe = samsung_ltl106hl02_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct samsung_ltl106hl02_priv), +}; diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index efb122b534a..76a30427a59 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -7,31 +7,22 @@ #include <common.h> #include <backlight.h> #include <dm.h> +#include <edid.h> +#include <i2c.h> #include <log.h> #include <mipi_dsi.h> #include <panel.h> #include <asm/gpio.h> #include <power/regulator.h> +#define EDID_I2C_ADDR 0x50 + struct simple_panel_priv { struct udevice *reg; struct udevice *backlight; struct gpio_desc enable; }; -/* List of supported DSI panels */ -enum { - PANEL_NON_DSI, - PANASONIC_VVX10F004B00, -}; - -static const struct mipi_dsi_panel_plat panasonic_vvx10f004b00 = { - .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_CLOCK_NON_CONTINUOUS, - .format = MIPI_DSI_FMT_RGB888, - .lanes = 4, -}; - static int simple_panel_enable_backlight(struct udevice *dev) { struct simple_panel_priv *priv = dev_get_priv(dev); @@ -62,13 +53,71 @@ static int simple_panel_set_backlight(struct udevice *dev, int percent) return 0; } +#if CONFIG_IS_ENABLED(I2C_EDID) && CONFIG_IS_ENABLED(DM_I2C) +static int simple_panel_get_edid_timing(struct udevice *dev, + struct display_timing *timings) +{ + struct udevice *panel_ddc, *panel_edid; + struct display_timing edid_timing; + u8 edid_buf[EDID_SIZE] = { 0 }; + int ret, bpc; + /* Check for DDC i2c if no timings are provided */ + ret = uclass_get_device_by_phandle(UCLASS_I2C, dev, + "ddc-i2c-bus", + &panel_ddc); + if (ret) { + log_debug("%s: cannot get DDC i2c bus: error %d\n", + __func__, ret); + return ret; + } + + ret = dm_i2c_probe(panel_ddc, EDID_I2C_ADDR, 0, &panel_edid); + if (ret) { + log_debug("%s: cannot probe EDID: error %d\n", + __func__, ret); + return ret; + } + + ret = dm_i2c_read(panel_edid, 0, edid_buf, sizeof(edid_buf)); + if (ret) { + log_debug("%s: cannot dump EDID buffer: error %d\n", + __func__, ret); + return ret; + } + + ret = edid_get_timing(edid_buf, sizeof(edid_buf), + &edid_timing, &bpc); + if (ret) { + log_debug("%s: cannot decode EDID info: error %d\n", + __func__, ret); + return ret; + } + + memcpy(timings, &edid_timing, sizeof(*timings)); + + return 0; +} +#else +static int simple_panel_get_edid_timing(struct udevice *dev, + struct display_timing *timings) +{ + return -ENOTSUPP; +} +#endif + static int simple_panel_get_display_timing(struct udevice *dev, struct display_timing *timings) { const void *blob = gd->fdt_blob; + int ret; + + /* Check for timing subnode if panel node first */ + ret = fdtdec_decode_display_timing(blob, dev_of_offset(dev), + 0, timings); + if (!ret) + return ret; - return fdtdec_decode_display_timing(blob, dev_of_offset(dev), - 0, timings); + return simple_panel_get_edid_timing(dev, timings); } static int simple_panel_of_to_plat(struct udevice *dev) @@ -111,7 +160,8 @@ static int simple_panel_probe(struct udevice *dev) { struct simple_panel_priv *priv = dev_get_priv(dev); struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); - const u32 dsi_data = dev_get_driver_data(dev); + struct mipi_dsi_panel_plat *dsi_data = + (struct mipi_dsi_panel_plat *)dev_get_driver_data(dev); int ret; ret = regulator_set_enable_if_allowed(priv->reg, true); @@ -121,15 +171,8 @@ static int simple_panel_probe(struct udevice *dev) return ret; } - switch (dsi_data) { - case PANASONIC_VVX10F004B00: - memcpy(plat, &panasonic_vvx10f004b00, - sizeof(panasonic_vvx10f004b00)); - break; - case PANEL_NON_DSI: - default: - break; - } + if (dsi_data) + memcpy(plat, dsi_data, sizeof(struct mipi_dsi_panel_plat)); return 0; } @@ -140,6 +183,13 @@ static const struct panel_ops simple_panel_ops = { .get_display_timing = simple_panel_get_display_timing, }; +static const struct mipi_dsi_panel_plat panasonic_vvx10f004b00 = { + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_CLOCK_NON_CONTINUOUS, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 4, +}; + static const struct udevice_id simple_panel_ids[] = { { .compatible = "simple-panel" }, { .compatible = "auo,b133xtn01" }, @@ -150,7 +200,7 @@ static const struct udevice_id simple_panel_ids[] = { { .compatible = "sharp,lq123p1jx31" }, { .compatible = "boe,nv101wxmn51" }, { .compatible = "panasonic,vvx10f004b00", - .data = PANASONIC_VVX10F004B00 }, + .data = (ulong)&panasonic_vvx10f004b00 }, { } }; diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 235ec761f70..33bb78bc3a3 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -15,14 +15,14 @@ static int simple_video_probe(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); - const void *blob = gd->fdt_blob; - const int node = dev_of_offset(dev); + ofnode node = dev_ofnode(dev); const char *format; + int ret; fdt_addr_t base; fdt_size_t size; + u32 width, height, rot; - base = fdtdec_get_addr_size_auto_parent(blob, dev_of_offset(dev->parent), - node, "reg", 0, &size, false); + base = dev_read_addr_size(dev, &size); if (base == FDT_ADDR_T_NONE) { debug("%s: Failed to decode memory region\n", __func__); return -EINVAL; @@ -41,17 +41,25 @@ static int simple_video_probe(struct udevice *dev) debug("%s: Query resolution...\n", __func__); - uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0); - uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0); - uc_priv->rot = fdtdec_get_uint(blob, node, "rot", 0); - if (uc_priv->rot > 3) { - log_debug("%s: invalid rot\n", __func__); - return log_msg_ret("rot", -EINVAL); + ret = ofnode_read_u32(node, "width", &width); + ret = ret ?: ofnode_read_u32(node, "height", &height); + if (ret || !width || !height) { + log_err("%s: invalid width or height: %d\n", __func__, ret); + return ret ?: -EINVAL; } + ofnode_read_u32(node, "rot", &rot); + uc_priv->rot = rot; + uc_priv->xsize = width; + uc_priv->ysize = height; - format = fdt_getprop(blob, node, "format", NULL); + format = ofnode_read_string(node, "format"); debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format); + if (!format) { + log_err("%s: please add required property \"format\"\n", __func__); + return -EINVAL; + } + if (strcmp(format, "r5g6b5") == 0) { uc_priv->bpix = VIDEO_BPP16; } else if (strcmp(format, "a8b8g8r8") == 0 || @@ -67,7 +75,7 @@ static int simple_video_probe(struct udevice *dev) uc_priv->bpix = VIDEO_BPP32; uc_priv->format = VIDEO_X2R10G10B10; } else { - printf("%s: invalid format: %s\n", __func__, format); + log_err("%s: invalid format: %s\n", __func__, format); return -EINVAL; } diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0324a050d03..a5e8d39e98f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -358,17 +358,19 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) sunxi_dw_hdmi_phy_init(&priv->hdmi); - ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } + ret = dw_hdmi_detect_hpd(&priv->hdmi); + if (ret < 0) + return ret; dw_hdmi_init(&priv->hdmi); return 0; } +static const struct dw_hdmi_phy_ops dw_hdmi_sunxi_phy_ops = { + .phy_set = sunxi_dw_hdmi_phy_cfg, +}; + static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) { struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); @@ -379,7 +381,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) hdmi->i2c_clk_high = 0xd8; hdmi->i2c_clk_low = 0xfe; hdmi->reg_io_width = 1; - hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; + hdmi->ops = &dw_hdmi_sunxi_phy_ops; ret = reset_get_bulk(dev, &priv->resets); if (ret) diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile index f0b534c5794..a75aea2a875 100644 --- a/drivers/video/tegra20/Makefile +++ b/drivers/video/tegra20/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o -obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o mipi-phy.o +obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index f53ad463970..d073da7d7d4 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -3,8 +3,8 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include <common.h> #include <backlight.h> +#include <cpu_func.h> #include <dm.h> #include <fdtdec.h> #include <log.h> @@ -21,12 +21,20 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> +#include <asm/arch/powergate.h> #include <asm/arch/pwm.h> -#include <asm/arch/display.h> -#include <asm/arch-tegra/timer.h> + +#include "tegra-dc.h" DECLARE_GLOBAL_DATA_PTR; +/* Holder of Tegra per-SOC DC differences */ +struct tegra_dc_soc_info { + bool has_timer; + bool has_rgb; + bool has_pgate; +}; + /* Information about the display controller */ struct tegra_lcd_priv { int width; /* width in pixels */ @@ -35,16 +43,19 @@ struct tegra_lcd_priv { struct display_timing timing; struct udevice *panel; struct dc_ctlr *dc; /* Display controller regmap */ + const struct tegra_dc_soc_info *soc; fdt_addr_t frame_buffer; /* Address of frame buffer */ unsigned pixel_clock; /* Pixel clock in Hz */ int dc_clk[2]; /* Contains clk and its parent */ + ulong scdiv; /* Clock divider used by disp_clk_ctrl */ bool rotation; /* 180 degree panel turn */ + bool pipe; /* DC controller: 0 for A, 1 for B */ }; enum { /* Maximum LCD size we support */ - LCD_MAX_WIDTH = 1920, - LCD_MAX_HEIGHT = 1200, + LCD_MAX_WIDTH = 2560, + LCD_MAX_HEIGHT = 1600, LCD_MAX_LOG2_BPP = VIDEO_BPP16, }; @@ -110,13 +121,11 @@ static void update_window(struct tegra_lcd_priv *priv, writel(val, &dc->cmd.state_ctrl); } -static int update_display_mode(struct dc_disp_reg *disp, - struct tegra_lcd_priv *priv) +static int update_display_mode(struct tegra_lcd_priv *priv) { + struct dc_disp_reg *disp = &priv->dc->disp; struct display_timing *dt = &priv->timing; unsigned long val; - unsigned long rate; - unsigned long div; writel(0x0, &disp->disp_timing_opt); @@ -128,29 +137,22 @@ static int update_display_mode(struct dc_disp_reg *disp, &disp->front_porch); writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); - val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; - val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; - writel(val, &disp->data_enable_opt); - - val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; - val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; - val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; - writel(val, &disp->disp_interface_ctrl); + if (priv->soc->has_rgb) { + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; + writel(val, &disp->data_enable_opt); - /* - * The pixel clock divider is in 7.1 format (where the bottom bit - * represents 0.5). Here we calculate the divider needed to get from - * the display clock (typically 600MHz) to the pixel clock. We round - * up or down as requried. - */ - rate = clock_get_periph_rate(priv->dc_clk[0], priv->dc_clk[1]); - div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2; - debug("Display clock %lu, divider %lu\n", rate, div); + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; + writel(val, &disp->disp_interface_ctrl); + } - writel(0x00010001, &disp->shift_clk_opt); + if (priv->soc->has_rgb) + writel(0x00010001, &disp->shift_clk_opt); val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; - val |= div << SHIFT_CLK_DIVIDER_SHIFT; + val |= priv->scdiv << SHIFT_CLK_DIVIDER_SHIFT; writel(val, &disp->disp_clk_ctrl); return 0; @@ -174,6 +176,7 @@ static void basic_init(struct dc_cmd_reg *cmd) writel(val, &cmd->disp_pow_ctrl); val = readl(&cmd->disp_cmd); + val &= ~CTRL_MODE_MASK; val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; writel(val, &cmd->disp_cmd); } @@ -215,8 +218,11 @@ static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { 0x00020000, }; -static void rgb_enable(struct dc_com_reg *com) +static void rgb_enable(struct tegra_lcd_priv *priv) { + struct dc_com_reg *com = &priv->dc->com; + struct display_timing *dt = &priv->timing; + u32 value; int i; for (i = 0; i < PIN_REG_COUNT; i++) { @@ -225,16 +231,31 @@ static void rgb_enable(struct dc_com_reg *com) writel(rgb_data_tab[i], &com->pin_output_data[i]); } + /* configure H- and V-sync signal polarities */ + value = readl(&com->pin_output_polarity[1]); + + if (dt->flags & DISPLAY_FLAGS_HSYNC_LOW) + value |= LHS_OUTPUT_POLARITY_LOW; + else + value &= ~LHS_OUTPUT_POLARITY_LOW; + + if (dt->flags & DISPLAY_FLAGS_VSYNC_LOW) + value |= LVS_OUTPUT_POLARITY_LOW; + else + value &= ~LVS_OUTPUT_POLARITY_LOW; + + writel(value, &com->pin_output_polarity[1]); + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) writel(rgb_sel_tab[i], &com->pin_output_sel[i]); } -static int setup_window(struct disp_ctl_win *win, - struct tegra_lcd_priv *priv) +static int setup_window(struct tegra_lcd_priv *priv, + struct disp_ctl_win *win) { if (priv->rotation) { - win->x = priv->width * 2; - win->y = priv->height; + win->x = priv->width * 2 - 1; + win->y = priv->height - 1; } else { win->x = 0; win->y = 0; @@ -274,12 +295,11 @@ static int setup_window(struct disp_ctl_win *win, * You should pass in the U-Boot address here, and check the contents of * struct tegra_lcd_priv to see what was actually chosen. * - * @param blob Device tree blob * @param priv Driver's private data * @param default_lcd_base Default address of LCD frame buffer * Return: 0 if ok, -1 on error (unsupported bits per pixel) */ -static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, +static int tegra_display_probe(struct tegra_lcd_priv *priv, void *default_lcd_base) { struct disp_ctl_win window; @@ -288,12 +308,29 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, priv->frame_buffer = (u32)default_lcd_base; /* - * We halve the rate if DISP1 paret is PLLD, since actual parent + * We halve the rate if DISP1 parent is PLLD, since actual parent * is plld_out0 which is PLLD divided by 2. */ if (priv->dc_clk[1] == CLOCK_ID_DISPLAY) rate /= 2; +#ifndef CONFIG_TEGRA20 + /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */ + if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2) + rate /= 2; +#endif + + /* + * The pixel clock divider is in 7.1 format (where the bottom bit + * represents 0.5). Here we calculate the divider needed to get from + * the display clock (typically 600MHz) to the pixel clock. We round + * up or down as required. + */ + if (!priv->scdiv) + priv->scdiv = ((rate * 2 + priv->pixel_clock / 2) + / priv->pixel_clock) - 2; + debug("Display clock %lu, divider %lu\n", rate, priv->scdiv); + /* * HOST1X is init by default at 150MHz with PLLC as parent */ @@ -303,13 +340,17 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, rate); basic_init(&priv->dc->cmd); - basic_init_timer(&priv->dc->disp); - rgb_enable(&priv->dc->com); + + if (priv->soc->has_timer) + basic_init_timer(&priv->dc->disp); + + if (priv->soc->has_rgb) + rgb_enable(priv); if (priv->pixel_clock) - update_display_mode(&priv->dc->disp, priv); + update_display_mode(priv); - if (setup_window(&window, priv)) + if (setup_window(priv, &window)) return -1; update_window(priv, &window); @@ -322,7 +363,6 @@ static int tegra_lcd_probe(struct udevice *dev) struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct tegra_lcd_priv *priv = dev_get_priv(dev); - const void *blob = gd->fdt_blob; int ret; /* Initialize the Tegra display controller */ @@ -330,8 +370,42 @@ static int tegra_lcd_probe(struct udevice *dev) funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); #endif - if (tegra_display_probe(blob, priv, (void *)plat->base)) { - printf("%s: Failed to probe display driver\n", __func__); + if (priv->soc->has_pgate) { + uint powergate; + + if (priv->pipe) + powergate = TEGRA_POWERGATE_DISB; + else + powergate = TEGRA_POWERGATE_DIS; + + ret = tegra_powergate_power_off(powergate); + if (ret < 0) { + log_err("failed to power off DISP gate: %d", ret); + return ret; + } + + ret = tegra_powergate_sequence_power_up(powergate, + priv->dc_clk[0]); + if (ret < 0) { + log_err("failed to power up DISP gate: %d", ret); + return ret; + } + } + + /* Get shift clock divider from Tegra DSI if used */ + if (!strcmp(priv->panel->name, TEGRA_DSI_A) || + !strcmp(priv->panel->name, TEGRA_DSI_B)) { + struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel); + + priv->scdiv = dc_plat->scdiv; + } + + /* Clean the framebuffer area */ + memset((u8 *)plat->base, 0, plat->size); + flush_dcache_all(); + + if (tegra_display_probe(priv, (void *)plat->base)) { + debug("%s: Failed to probe display driver\n", __func__); return -1; } @@ -346,12 +420,6 @@ static int tegra_lcd_probe(struct udevice *dev) return ret; } - ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT); - if (ret) { - debug("%s: Cannot set backlight to default, ret=%d\n", __func__, ret); - return ret; - } - mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, DCACHE_WRITETHROUGH); @@ -361,10 +429,10 @@ static int tegra_lcd_probe(struct udevice *dev) uc_priv->xsize = priv->width; uc_priv->ysize = priv->height; uc_priv->bpix = priv->log2_bpp; - debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer, + debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer, plat->size); - return 0; + return panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT); } static int tegra_lcd_of_to_plat(struct udevice *dev) @@ -383,6 +451,8 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) return -EINVAL; } + priv->soc = (struct tegra_dc_soc_info *)dev_get_driver_data(dev); + ret = clock_decode_pair(dev, priv->dc_clk); if (ret < 0) { debug("%s: Cannot decode clocks for '%s' (ret = %d)\n", @@ -392,6 +462,9 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) priv->rotation = dev_read_bool(dev, "nvidia,180-rotation"); + if (!strcmp(dev->name, TEGRA_DC_B)) + priv->pipe = 1; + rgb = fdt_subnode_offset(blob, node, "rgb"); if (rgb < 0) { debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n", @@ -417,12 +490,14 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) return ret; } + /* Fill the platform data for internal devices */ if (!strcmp(priv->panel->name, TEGRA_DSI_A) || !strcmp(priv->panel->name, TEGRA_DSI_B)) { struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel); dc_plat->dev = dev; dc_plat->dc = priv->dc; + dc_plat->pipe = priv->pipe; } ret = panel_get_display_timing(priv->panel, &priv->timing); @@ -464,19 +539,46 @@ static int tegra_lcd_bind(struct udevice *dev) static const struct video_ops tegra_lcd_ops = { }; +static const struct tegra_dc_soc_info tegra20_dc_soc_info = { + .has_timer = true, + .has_rgb = true, + .has_pgate = false, +}; + +static const struct tegra_dc_soc_info tegra30_dc_soc_info = { + .has_timer = false, + .has_rgb = true, + .has_pgate = false, +}; + +static const struct tegra_dc_soc_info tegra114_dc_soc_info = { + .has_timer = false, + .has_rgb = false, + .has_pgate = true, +}; + static const struct udevice_id tegra_lcd_ids[] = { - { .compatible = "nvidia,tegra20-dc" }, - { .compatible = "nvidia,tegra30-dc" }, - { } + { + .compatible = "nvidia,tegra20-dc", + .data = (ulong)&tegra20_dc_soc_info + }, { + .compatible = "nvidia,tegra30-dc", + .data = (ulong)&tegra30_dc_soc_info + }, { + .compatible = "nvidia,tegra114-dc", + .data = (ulong)&tegra114_dc_soc_info + }, { + /* sentinel */ + } }; U_BOOT_DRIVER(tegra_lcd) = { - .name = "tegra_lcd", - .id = UCLASS_VIDEO, - .of_match = tegra_lcd_ids, - .ops = &tegra_lcd_ops, - .bind = tegra_lcd_bind, - .probe = tegra_lcd_probe, + .name = "tegra_lcd", + .id = UCLASS_VIDEO, + .of_match = tegra_lcd_ids, + .ops = &tegra_lcd_ops, + .bind = tegra_lcd_bind, + .probe = tegra_lcd_probe, .of_to_plat = tegra_lcd_of_to_plat, .priv_auto = sizeof(struct tegra_lcd_priv), }; diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h new file mode 100644 index 00000000000..05042dab1c6 --- /dev/null +++ b/drivers/video/tegra20/tegra-dc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * NVIDIA Corporation <www.nvidia.com> + */ + +#ifndef _TEGRA_DC_H +#define _TEGRA_DC_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +/* arch-tegra/dc exists only because T124 uses it */ +#include <asm/arch-tegra/dc.h> + +#define TEGRA_DC_A "dc@54200000" +#define TEGRA_DC_B "dc@54240000" +#define TEGRA_DSI_A "dsi@54300000" +#define TEGRA_DSI_B "dsi@54400000" + +struct tegra_dc_plat { + struct udevice *dev; /* Display controller device */ + struct dc_ctlr *dc; /* Display controller regmap */ + bool pipe; /* DC number: 0 for A, 1 for B */ + ulong scdiv; /* Shift clock divider */ +}; + +/* This holds information about a window which can be displayed */ +struct disp_ctl_win { + enum win_color_depth_id fmt; /* Color depth/format */ + unsigned int bpp; /* Bits per pixel */ + phys_addr_t phys_addr; /* Physical address in memory */ + unsigned int x; /* Horizontal address offset (bytes) */ + unsigned int y; /* Veritical address offset (bytes) */ + unsigned int w; /* Width of source window */ + unsigned int h; /* Height of source window */ + unsigned int stride; /* Number of bytes per line */ + unsigned int out_x; /* Left edge of output window (col) */ + unsigned int out_y; /* Top edge of output window (row) */ + unsigned int out_w; /* Width of output window in pixels */ + unsigned int out_h; /* Height of output window in pixels */ +}; + +#endif /* _TEGRA_DC_H */ diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index a48f9c85d0f..13dae37806f 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -12,6 +12,7 @@ #include <mipi_dsi.h> #include <backlight.h> #include <panel.h> +#include <reset.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/time.h> @@ -20,17 +21,24 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/display.h> -#include <asm/arch-tegra30/dsi.h> +#include "tegra-dc.h" +#include "tegra-dsi.h" #include "mipi-phy.h" +/* List of supported DSI bridges */ +enum { + DSI_V0, + DSI_V1, +}; + struct tegra_dsi_priv { struct mipi_dsi_host host; struct mipi_dsi_device device; struct mipi_dphy_timing dphy_timing; struct udevice *panel; + struct udevice *mipi; struct display_timing timing; struct dsi_ctlr *dsi; @@ -41,6 +49,8 @@ struct tegra_dsi_priv { int dsi_clk; int video_fifo_depth; int host_fifo_depth; + + u32 version; }; static void tegra_dc_enable_controller(struct udevice *dev) @@ -501,6 +511,41 @@ static void tegra_dsi_pad_calibrate(struct dsi_pad_ctrl_reg *pad) writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2)); } +static void tegra_dsi_mipi_calibrate(struct tegra_dsi_priv *priv) +{ + struct dsi_pad_ctrl_reg *pad = &priv->dsi->pad; + u32 value; + int ret; + + ret = misc_set_enabled(priv->mipi, true); + if (ret) + log_debug("%s: failed to enable MIPI calibration: %d\n", + __func__, ret); + + writel(0, &pad->pad_ctrl); + writel(0, &pad->pad_ctrl_1); + writel(0, &pad->pad_ctrl_2); + writel(0, &pad->pad_ctrl_3); + writel(0, &pad->pad_ctrl_4); + + /* DSI pad enable */ + value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); + writel(value, &pad->pad_ctrl); + + value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | + DSI_PAD_OUT_CLK(0x0); + writel(value, &pad->pad_ctrl_2); + + value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | + DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); + writel(value, &pad->pad_ctrl_3); + + ret = misc_write(priv->mipi, 0, NULL, 0); + if (ret) + log_debug("%s: MIPI calibration failed %d\n", __func__, ret); +} + static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout, unsigned long bclk, unsigned int vrefresh) @@ -664,10 +709,25 @@ static int tegra_dsi_encoder_enable(struct udevice *dev) u32 value; int ret; + /* If for some reasone DSI is enabled then it needs to + * be disabled in order for the panel initialization + * commands to be properly sent. + */ + value = readl(&misc->dsi_pwr_ctrl); + + if (value & DSI_POWER_CONTROL_ENABLE) { + value = readl(&misc->dsi_pwr_ctrl); + value &= ~DSI_POWER_CONTROL_ENABLE; + writel(value, &misc->dsi_pwr_ctrl); + } + /* Disable interrupt */ writel(0, &misc->int_enable); - tegra_dsi_pad_calibrate(&priv->dsi->pad); + if (priv->version) + tegra_dsi_mipi_calibrate(priv); + else + tegra_dsi_pad_calibrate(&priv->dsi->pad); tegra_dsi_get_muldiv(device->format, &mul, &div); @@ -706,12 +766,6 @@ static int tegra_dsi_encoder_enable(struct udevice *dev) if (ret) return ret; - tegra_dsi_configure(dev, 0); - - ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT); - if (ret) - return ret; - tegra_dsi_configure(dev, device->mode_flags); tegra_dc_enable_controller(dev); @@ -726,8 +780,10 @@ static int tegra_dsi_encoder_enable(struct udevice *dev) static int tegra_dsi_bridge_set_panel(struct udevice *dev, int percent) { - /* Is not used in tegra dc */ - return 0; + struct tegra_dsi_priv *priv = dev_get_priv(dev); + + /* Turn on/off backlight */ + return panel_set_backlight(priv->panel, percent); } static int tegra_dsi_panel_timings(struct udevice *dev, @@ -743,6 +799,7 @@ static int tegra_dsi_panel_timings(struct udevice *dev, static void tegra_dsi_init_clocks(struct udevice *dev) { struct tegra_dsi_priv *priv = dev_get_priv(dev); + struct tegra_dc_plat *dc_plat = dev_get_plat(dev); struct mipi_dsi_device *device = &priv->device; unsigned int mul, div; unsigned long bclk, plld; @@ -754,6 +811,19 @@ static void tegra_dsi_init_clocks(struct udevice *dev) plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC); + dc_plat->scdiv = ((plld * USEC_PER_SEC + + priv->timing.pixelclock.typ / 2) / + priv->timing.pixelclock.typ) - 2; + + /* + * BUG: If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The + * cause of this is not quite clear. This can be overcomed by + * halving the PLLD/D2 if the target rate is > 800MHz. This way + * DISP1 and DSI clocks will be equal. + */ + if (plld > 800) + plld /= 2; + switch (clock_get_osc_freq()) { case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */ @@ -790,17 +860,27 @@ static int tegra_dsi_bridge_probe(struct udevice *dev) struct tegra_dsi_priv *priv = dev_get_priv(dev); struct mipi_dsi_device *device = &priv->device; struct mipi_dsi_panel_plat *mipi_plat; + struct reset_ctl reset_ctl; int ret; + priv->version = dev_get_driver_data(dev); + priv->dsi = (struct dsi_ctlr *)dev_read_addr_ptr(dev); if (!priv->dsi) { printf("%s: No display controller address\n", __func__); return -EINVAL; } - priv->video_fifo_depth = 480; + priv->video_fifo_depth = 1920; priv->host_fifo_depth = 64; + ret = reset_get_by_name(dev, "dsi", &reset_ctl); + if (ret) { + log_debug("%s: reset_get_by_name() failed: %d\n", + __func__, ret); + return ret; + } + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, "avdd-dsi-csi-supply", &priv->avdd); if (ret) @@ -814,6 +894,16 @@ static int tegra_dsi_bridge_probe(struct udevice *dev) return log_ret(ret); } + if (priv->version) { + ret = uclass_get_device_by_phandle(UCLASS_MISC, dev, + "nvidia,mipi-calibrate", + &priv->mipi); + if (ret) { + log_debug("%s: cannot get MIPI: error %d\n", __func__, ret); + return ret; + } + } + panel_get_display_timing(priv->panel, &priv->timing); mipi_plat = dev_get_plat(priv->panel); @@ -829,12 +919,17 @@ static int tegra_dsi_bridge_probe(struct udevice *dev) tegra_dsi_get_format(device->format, &priv->format); + reset_assert(&reset_ctl); + ret = regulator_set_enable_if_allowed(priv->avdd, true); if (ret && ret != -ENOSYS) return ret; tegra_dsi_init_clocks(dev); + mdelay(2); + reset_deassert(&reset_ctl); + return 0; } @@ -845,7 +940,8 @@ static const struct panel_ops tegra_dsi_bridge_ops = { }; static const struct udevice_id tegra_dsi_bridge_ids[] = { - { .compatible = "nvidia,tegra30-dsi" }, + { .compatible = "nvidia,tegra30-dsi", .data = DSI_V0 }, + { .compatible = "nvidia,tegra114-dsi", .data = DSI_V1 }, { } }; diff --git a/arch/arm/include/asm/arch-tegra30/dsi.h b/drivers/video/tegra20/tegra-dsi.h index 7ade132613f..69dac4bd1b8 100644 --- a/arch/arm/include/asm/arch-tegra30/dsi.h +++ b/drivers/video/tegra20/tegra-dsi.h @@ -4,8 +4,8 @@ * NVIDIA Corporation <www.nvidia.com> */ -#ifndef __ASM_ARCH_TEGRA_DSI_H -#define __ASM_ARCH_TEGRA_DSI_H +#ifndef _TEGRA_DSI_H +#define _TEGRA_DSI_H #ifndef __ASSEMBLY__ #include <linux/bitops.h> @@ -105,6 +105,10 @@ struct dsi_pad_ctrl_reg { uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */ uint pad_cd_status; /* _PAD_CD_STATUS_0 */ uint dsi_vid_mode_control; /* _DSI_VID_MODE_CONTROL_0 */ + uint pad_ctrl_1; /* _PAD_CONTROL_1 */ + uint pad_ctrl_2; /* _PAD_CONTROL_2 */ + uint pad_ctrl_3; /* _PAD_CONTROL_3 */ + uint pad_ctrl_4; /* _PAD_CONTROL_4 */ }; /* Display Serial Interface (DSI_) regs */ @@ -184,6 +188,20 @@ struct dsi_ctlr { #define DSI_PAD_CONTROL_PAD_LPUPADJ(x) (((x) & 0x3) << 14) #define DSI_PAD_CONTROL_PAD_LPDNADJ(x) (((x) & 0x3) << 12) +#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) +#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) + +#define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0) +#define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4) +#define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8) +#define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12) +#define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16) + +#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) +#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) +#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) +#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) + /* * pixel format as used in the DSI_CONTROL_FORMAT field */ @@ -214,4 +232,4 @@ enum tegra_dsi_format { #define PAD_DRIV_DN_REF(x) (((x) & 0x7) << 16) #define PAD_DRIV_UP_REF(x) (((x) & 0x7) << 8) -#endif /* __ASM_ARCH_TEGRA_DSI_H */ +#endif /* _TEGRA_DSI_H */ diff --git a/drivers/video/tegra20/tegra-mipi.c b/drivers/video/tegra20/tegra-mipi.c new file mode 100644 index 00000000000..2df3c1a9942 --- /dev/null +++ b/drivers/video/tegra20/tegra-mipi.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 NVIDIA Corporation + * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <clk.h> +#include <misc.h> +#include <linux/delay.h> +#include <linux/iopoll.h> + +#include <asm/io.h> + +/* MIPI control registers 0x00 ~ 0x60 */ +struct mipi_ctlr { + uint mipi_cal_ctrl; + uint mipi_cal_autocal_ctrl; + uint mipi_cal_status; + + uint unused1[2]; + + uint mipi_cal_config_csia; + uint mipi_cal_config_csib; + uint mipi_cal_config_csic; + uint mipi_cal_config_csid; + uint mipi_cal_config_csie; + + uint unused2[4]; + + uint mipi_cal_config_dsia; + uint mipi_cal_config_dsib; + uint mipi_cal_config_dsic; + uint mipi_cal_config_dsid; + + uint unused3[4]; + + uint mipi_cal_bias_pad_cfg0; + uint mipi_cal_bias_pad_cfg1; + uint mipi_cal_bias_pad_cfg2; +}; + +#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26) +#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24) +#define MIPI_CAL_CTRL_CLKEN_OVR BIT(4) +#define MIPI_CAL_CTRL_START BIT(0) + +#define MIPI_CAL_STATUS_DONE BIT(16) +#define MIPI_CAL_STATUS_ACTIVE BIT(0) + +#define MIPI_CAL_OVERIDE(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SEL(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOS(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOS(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOS(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_BIAS_PAD_PDVCLAMP BIT(1) +#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF BIT(0) + +#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16) +#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8) + +#define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16) +#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4) +#define MIPI_CAL_BIAS_PAD_PDVREG BIT(1) + +struct tegra_mipi_priv { + struct mipi_ctlr *mipi; + struct clk *mipi_cal; +}; + +static int tegra_mipi_calibrate(struct udevice *dev, int offset, const void *buf, + int size) +{ + struct tegra_mipi_priv *priv = dev_get_priv(dev); + u32 value; + + value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(0x2) | + MIPI_CAL_BIAS_PAD_DRV_UP_REF(0x0); + writel(value, &priv->mipi->mipi_cal_bias_pad_cfg1); + + value = readl(&priv->mipi->mipi_cal_bias_pad_cfg2); + value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7); + value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7); + writel(value, &priv->mipi->mipi_cal_bias_pad_cfg2); + + value = MIPI_CAL_OVERIDE(0x0) | MIPI_CAL_SEL(0x1) | + MIPI_CAL_HSPDOS(0x0) | MIPI_CAL_HSPUOS(0x4) | + MIPI_CAL_TERMOS(0x5); + writel(value, &priv->mipi->mipi_cal_config_dsia); + writel(value, &priv->mipi->mipi_cal_config_dsib); + + /* Deselect PAD C */ + value = readl(&priv->mipi->mipi_cal_config_dsic); + value &= ~(MIPI_CAL_SEL(0x1)); + writel(value, &priv->mipi->mipi_cal_config_dsic); + + /* Deselect PAD D */ + value = readl(&priv->mipi->mipi_cal_config_dsid); + value &= ~(MIPI_CAL_SEL(0x1)); + writel(value, &priv->mipi->mipi_cal_config_dsid); + + value = readl(&priv->mipi->mipi_cal_ctrl); + value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf); + value &= ~MIPI_CAL_CTRL_PRESCALE(0x3); + value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa) | + MIPI_CAL_CTRL_PRESCALE(0x2) | + MIPI_CAL_CTRL_CLKEN_OVR; + writel(value, &priv->mipi->mipi_cal_ctrl); + + /* clear any pending status bits */ + value = readl(&priv->mipi->mipi_cal_status); + writel(value, &priv->mipi->mipi_cal_status); + + value = readl(&priv->mipi->mipi_cal_ctrl); + value |= MIPI_CAL_CTRL_START; + writel(value, &priv->mipi->mipi_cal_ctrl); + + /* + * Wait for min 72uS to let calibration logic finish calibration + * sequence codes before waiting for pads idle state to apply the + * results. + */ + udelay(80); + + return readl_poll_sleep_timeout(&priv->mipi->mipi_cal_status, value, + !(value & MIPI_CAL_STATUS_ACTIVE) && + (value & MIPI_CAL_STATUS_DONE), 100, + 250000); +} + +static int tegra_mipi_enable(struct udevice *dev, bool val) +{ + struct tegra_mipi_priv *priv = dev_get_priv(dev); + u32 value; + + clk_enable(priv->mipi_cal); + + value = readl(&priv->mipi->mipi_cal_bias_pad_cfg0); + value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP; + value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; + writel(value, &priv->mipi->mipi_cal_bias_pad_cfg0); + + value = readl(&priv->mipi->mipi_cal_bias_pad_cfg2); + value &= ~MIPI_CAL_BIAS_PAD_PDVREG; + writel(value, &priv->mipi->mipi_cal_bias_pad_cfg2); + + return 0; +} + +static const struct misc_ops tegra_mipi_ops = { + .write = tegra_mipi_calibrate, + .set_enabled = tegra_mipi_enable, +}; + +static int tegra_mipi_probe(struct udevice *dev) +{ + struct tegra_mipi_priv *priv = dev_get_priv(dev); + + priv->mipi = (struct mipi_ctlr *)dev_read_addr_ptr(dev); + if (!priv->mipi) { + log_debug("%s: no MIPI controller address\n", __func__); + return -EINVAL; + } + + priv->mipi_cal = devm_clk_get(dev, NULL); + if (IS_ERR(priv->mipi_cal)) { + log_debug("%s: Could not get MIPI clock: %ld\n", + __func__, PTR_ERR(priv->mipi_cal)); + return PTR_ERR(priv->mipi_cal); + } + + return 0; +} + +static const struct udevice_id tegra_mipi_ids[] = { + { .compatible = "nvidia,tegra114-mipi" }, + { } +}; + +U_BOOT_DRIVER(tegra_mipi) = { + .name = "tegra_mipi", + .id = UCLASS_MISC, + .ops = &tegra_mipi_ops, + .of_match = tegra_mipi_ids, + .probe = tegra_mipi_probe, + .priv_auto = sizeof(struct tegra_mipi_priv), +}; diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c index bb677daa8a1..5f93f57fe90 100644 --- a/drivers/video/tegra20/tegra-pwm-backlight.c +++ b/drivers/video/tegra20/tegra-pwm-backlight.c @@ -15,7 +15,8 @@ #include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/display.h> + +#include "tegra-dc.h" #define TEGRA_DISPLAY_A_BASE 0x54200000 #define TEGRA_DISPLAY_B_BASE 0x54240000 diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 3571e62ba2d..7b5d1dfbb3b 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -404,6 +404,10 @@ bool video_is_active(void) { struct udevice *dev; + /* Assume video to be active if SPL passed video hand-off to U-boot */ + if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) + return true; + for (uclass_find_first_device(UCLASS_VIDEO, &dev); dev; uclass_find_next_device(&dev)) { diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c index 1df04e239ad..9fc51d203e5 100644 --- a/drivers/xen/pvblock.c +++ b/drivers/xen/pvblock.c @@ -79,7 +79,7 @@ struct blkfront_plat { }; /** - * struct blkfront_aiocb - AIO сontrol block + * struct blkfront_aiocb - AIO control block * @aio_dev: Blockfront device * @aio_buf: Memory buffer, which must be sector-aligned for * @aio_dev sector diff --git a/dts/Kconfig b/dts/Kconfig index b9b6367154e..6883a000a05 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -101,6 +101,30 @@ config OF_UPSTREAM the dts/upstream subtree, they can override this option to have the DT build from existing U-Boot tree location instead. +config OF_UPSTREAM_BUILD_VENDOR + bool "Build all devicetree files for a particular vendor" + depends on OF_UPSTREAM + help + Enable building all devicetree files for a particular vendor. This + is useful for generic U-Boot configurations where many boards can + be supported with a single binary. + + This is only available for platforms using upstream devicetree. + +config OF_UPSTREAM_VENDOR + string "Vendor to build all upstream devicetree files for" + depends on OF_UPSTREAM_BUILD_VENDOR + default "qcom" if ARCH_SNAPDRAGON + default "rockchip" if ARCH_ROCKCHIP + default "amlogic" if ARCH_MESON + default "allwinner" if ARCH_SUNXI + default "mediatek" if ARCH_MEDIATEK + default "marvell" if ARCH_MVEBU || ARCH_KIRKWOOD + default "xilinx" if ARCH_VERSAL || ARCH_ZYNQ + default "nvidia" if ARCH_TEGRA + help + Select the vendor to build all devicetree files for. + choice prompt "Provider of DTB for DT control" depends on OF_CONTROL diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index 2c269ed6627..3aa94d70b9c 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -121,7 +121,7 @@ struct acpi_cstate { * * @percent: Percent of the core CPU operating frequency that will be * available when this throttling state is invoked - * @power: Throttling state’s maximum power dissipation (mw) + * @power: Throttling state's maximum power dissipation (mw) * @latency: Worst-case latency (uS) that the CPU is unavailable during a * transition from any throttling state to this throttling state * @control: Value to be written to the Processor Control Register @@ -920,7 +920,7 @@ void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power, * @ctx: ACPI context pointer * @domain: Dependency domain number to which this P state entry belongs * @numprocs: Number of processors belonging to the domain for this logical - * processor’s P-states + * processor's P-states * @coordtype: Coordination type */ void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, @@ -972,7 +972,7 @@ void acpigen_write_tss_package(struct acpi_ctx *ctx, * @ctx: ACPI context pointer * @domain: dependency domain number to which this T state entry belongs * @numprocs: Number of processors belonging to the domain for this logical - * processor’s T-states + * processor's T-states * @coordtype: Coordination type */ void acpigen_write_tsd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 845705c86db..c8ec034fc97 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -46,8 +46,6 @@ "fdt_board=eval\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 8a9f3ef75a7..0df3917e200 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -64,12 +64,9 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off vmalloc=400M\0" \ "fdt_board=eval\0" \ - "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ @@ -80,16 +77,12 @@ "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \ " ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" /* Miscellaneous configurable options */ diff --git a/include/configs/apple.h b/include/configs/apple.h index 0576bc04c94..1e08b114480 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -6,29 +6,13 @@ /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial,usbkbd,spikbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" -#if IS_ENABLED(CONFIG_CMD_NVME) - #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) -#else - #define BOOT_TARGET_NVME(func) -#endif - -#if IS_ENABLED(CONFIG_CMD_USB) - #define BOOT_TARGET_USB(func) func(USB, usb, 0) -#else - #define BOOT_TARGET_USB(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_NVME(func) \ - BOOT_TARGET_USB(func) - -#include <config_distro_bootcmd.h> +#define BOOT_TARGETS "nvme usb" #define CFG_EXTRA_ENV_SETTINGS \ ENV_DEVICE_SETTINGS \ - BOOTENV + "boot_targets=" BOOT_TARGETS "\0" #endif diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 561a61ebc03..8860ceec1a0 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -48,12 +48,12 @@ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ + "setenv bootargs ${ubiargs} " \ + "${setupargs} ${tdxargs}; echo Booting from NAND...; " \ "ubi part ubi &&" \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND) /* Run Distro Boot script if ubiboot fails */ @@ -86,11 +86,7 @@ UBOOT_UPDATE \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=user_debug=30\0" \ "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ - "ip_dyn=yes\0" \ - "kernel_file=zImage\0" \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "${board}/flash_eth.img && source ${loadaddr}\0" \ @@ -99,7 +95,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "setup=setenv setupargs " \ "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \ + ",${baudrate}n8 ${memargs} ${mtdparts}\0" \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb && " \ "fatload ${interface} 0:1 ${loadaddr} " \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 042fcb8757f..2b7fea30116 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -40,8 +40,6 @@ "fdt_board=eval-v3\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 4b2841833b5..79e5b870b81 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -58,12 +58,9 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ @@ -72,16 +69,12 @@ "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "vidargs=fbmem=8M\0" + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" /* Miscellaneous configurable options */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 7a9f4afe7d1..33133a0b96e 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -89,12 +89,12 @@ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ + "setenv bootargs ${ubiargs} " \ + "${setupargs} ${tdxargs}; echo Booting from NAND...; " \ "ubi part ubi && run m4boot && " \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) #define MODULE_EXTRA_ENV_SETTINGS \ @@ -123,15 +123,10 @@ MEM_LAYOUT_ENV_SETTINGS \ MODULE_EXTRA_ENV_SETTINGS \ UBOOT_UPDATE \ - "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=\0" \ "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ "m4boot=;\0" \ - "ip_dyn=yes\0" \ - "kernel_file=zImage\0" \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "${board}/flash_eth.img && source ${loadaddr}\0" \ @@ -140,7 +135,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "setup=setenv setupargs " \ "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \ + ",${baudrate}n8 ${memargs} ${mtdparts}\0" \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb && " \ "fatload ${interface} 0:1 ${loadaddr} " \ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 46c582e963e..348078f9770 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -53,7 +53,8 @@ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "check_button=gpio input 179; test $? -eq 0\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ ENDEAVORU_BOOTMENU diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index d10e5b1d2e0..c985080f7b3 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -6,6 +6,11 @@ #ifndef __EVB_RK3328_H #define __EVB_RK3328_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include <configs/rk3328_common.h> #endif diff --git a/include/configs/grouper.h b/include/configs/grouper.h index 93304ddc6e8..8064b88902e 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -49,7 +49,10 @@ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "check_button=gpio input 131; test $? -eq 0;\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ + "button_cmd_1_name=Lid\0" \ + "button_cmd_1=poweroff\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ GROUPER_BOOTMENU diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h new file mode 100644 index 00000000000..27404c80fdf --- /dev/null +++ b/include/configs/hmibsc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for HMIBSC + * + * (C) Copyright 2024 Sumit Garg <sumit.garg@linaro.org> + */ + +#ifndef __CONFIGS_HMIBSC_H +#define __CONFIGS_HMIBSC_H + +/* PHY needs a longer aneg time */ +#define PHY_ANEG_TIMEOUT 8000 + +#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" + +#endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index e920ec7e5dd..2c40674b224 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -26,6 +26,7 @@ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" #endif diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 0d0965ecce2..fc74980f7ca 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -7,33 +7,7 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H -#if IS_ENABLED(CONFIG_CMD_USB) -#define BOOT_TARGET_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_USB(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) && CONFIG_IS_ENABLED(CMD_PXE) -#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) -#else -#define BOOT_TARGET_PXE(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) -#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) -#else -#define BOOT_TARGET_DHCP(func) -#endif - -#ifndef BOOT_TARGET_DEVICES -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) -#endif -#include <config_distro_bootcmd.h> +#define BOOT_TARGETS "mmc1 mmc0 usb pxe dhcp" #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" @@ -88,7 +62,7 @@ MEM_LAYOUT_ENV_SETTINGS \ "fdt_high=" FDT_HIGH "\0" \ "initrd_high=" INITRD_HIGH "\0" \ - BOOTENV \ + "boot_targets=" BOOT_TARGETS "\0" \ BOARD_EXTRA_ENV_SETTINGS #endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h index 3b7db0ab142..bb6817c8d2b 100644 --- a/include/configs/transformer-common.h +++ b/include/configs/transformer-common.h @@ -71,18 +71,20 @@ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=enter console=usb start; setenv skip_boot 1; exit\0" \ - "bootmenu_5=reboot RCM=enterrcm\0" \ - "bootmenu_6=reboot=reset\0" \ - "bootmenu_7=power off=poweroff\0" \ + "bootmenu_4=reboot RCM=enterrcm\0" \ + "bootmenu_5=reboot=reset\0" \ + "bootmenu_6=power off=poweroff\0" \ "bootmenu_delay=-1\0" #define BOARD_EXTRA_ENV_SETTINGS \ "spi_size=0x400000\0" \ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ - "check_button=gpio input ${gpio_button}; test $? -eq 0;\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ + "button_cmd_1_name=Lid sensor\0" \ + "button_cmd_1=poweroff\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ TRANSFORMER_BOOTMENU diff --git a/include/configs/verdin-am62.h b/include/configs/verdin-am62.h index 9d2e37f2d96..ac44809fdfa 100644 --- a/include/configs/verdin-am62.h +++ b/include/configs/verdin-am62.h @@ -39,12 +39,9 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_scripts=boot.scr\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttyS2\0" \ "fdt_board=dev\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \ "update_tiboot3=askenv confirm Did you load tiboot3.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index a7ea02807dd..34238d3b505 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -37,14 +37,11 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 256bab089ff..0b88e95603d 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -13,7 +13,6 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x184000 @@ -40,15 +39,11 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ - "boot_scripts=boot.scr\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc2\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index 14532542ea6..78a20128611 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -54,7 +54,8 @@ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "check_button=gpio input 116; test $? -eq 0\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ X3_BOOTMENU diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h deleted file mode 100644 index b3f3b7cf9af..00000000000 --- a/include/dt-bindings/ata/ahci.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * This header provides constants for most AHCI bindings. - */ - -#ifndef _DT_BINDINGS_ATA_AHCI_H -#define _DT_BINDINGS_ATA_AHCI_H - -/* Host Bus Adapter generic platform capabilities */ -#define HBA_SSS (1 << 27) -#define HBA_SMPS (1 << 28) - -/* Host Bus Adapter port-specific platform capabilities */ -#define HBA_PORT_HPCP (1 << 18) -#define HBA_PORT_MPSP (1 << 19) -#define HBA_PORT_CPD (1 << 20) -#define HBA_PORT_ESP (1 << 21) -#define HBA_PORT_FBSCP (1 << 22) - -#endif diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 35a1f62053a..787c9e74dc9 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -203,6 +203,7 @@ #define IMX93_CLK_ARM_PLL 198 #define IMX93_CLK_A55_SEL 199 #define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_END 201 +#define IMX93_CLK_PDM_IPG 201 +#define IMX93_CLK_END 202 #endif diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h deleted file mode 100644 index c029467e828..00000000000 --- a/include/dt-bindings/gpio/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most GPIO bindings. - * - * Most GPIO bindings include a flags cell as part of the GPIO specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_GPIO_GPIO_H -#define _DT_BINDINGS_GPIO_GPIO_H - -/* Bit 0 express polarity */ -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/* Bit 1 express single-endedness */ -#define GPIO_PUSH_PULL 0 -#define GPIO_SINGLE_ENDED 2 - -/* Bit 2 express Open drain or open source */ -#define GPIO_LINE_OPEN_SOURCE 0 -#define GPIO_LINE_OPEN_DRAIN 4 - -/* - * Open Drain/Collector is the combination of single-ended open drain interface. - * Open Source/Emitter is the combination of single-ended open source interface. - */ -#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) -#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) - -/* Bit 3 express GPIO suspend/resume and reset persistence */ -#define GPIO_PERSISTENT 0 -#define GPIO_TRANSITORY 8 - -/* Bit 4 express pull up */ -#define GPIO_PULL_UP 16 - -/* Bit 5 express pull down */ -#define GPIO_PULL_DOWN 32 - -#endif diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h deleted file mode 100644 index 8962df79e75..00000000000 --- a/include/dt-bindings/input/gpio-keys.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for gpio keys bindings. - */ - -#ifndef _DT_BINDINGS_GPIO_KEYS_H -#define _DT_BINDINGS_GPIO_KEYS_H - -#define EV_ACT_ANY 0x00 /* asserted or deasserted */ -#define EV_ACT_ASSERTED 0x01 /* asserted */ -#define EV_ACT_DEASSERTED 0x02 /* deasserted */ - -#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h deleted file mode 100644 index a21413324a3..00000000000 --- a/include/dt-bindings/input/input.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This header provides constants for most input bindings. - * - * Most input bindings include key code, matrix key code format. - * In most cases, key code and matrix key code format uses - * the standard values/macro defined in this header. - */ - -#ifndef _DT_BINDINGS_INPUT_INPUT_H -#define _DT_BINDINGS_INPUT_INPUT_H - -#include "linux-event-codes.h" - -#define MATRIX_KEY(row, col, code) \ - ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) - -#endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h deleted file mode 100644 index 331458c0e71..00000000000 --- a/include/dt-bindings/input/linux-event-codes.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Input event codes - * - * *** IMPORTANT *** - * This file is not only included from C-code but also from devicetree source - * files. As such this file MUST only contain comments and defines. - * - * Copyright (c) 1999-2002 Vojtech Pavlik - * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef _UAPI_INPUT_EVENT_CODES_H -#define _UAPI_INPUT_EVENT_CODES_H - -/* - * Device properties and quirks - */ - -#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ -#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ -#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ -#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ -#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ -#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ -#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ - -#define INPUT_PROP_MAX 0x1f -#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) - -/* - * Event types - */ - -#define EV_SYN 0x00 -#define EV_KEY 0x01 -#define EV_REL 0x02 -#define EV_ABS 0x03 -#define EV_MSC 0x04 -#define EV_SW 0x05 -#define EV_LED 0x11 -#define EV_SND 0x12 -#define EV_REP 0x14 -#define EV_FF 0x15 -#define EV_PWR 0x16 -#define EV_FF_STATUS 0x17 -#define EV_MAX 0x1f -#define EV_CNT (EV_MAX+1) - -/* - * Synchronization events. - */ - -#define SYN_REPORT 0 -#define SYN_CONFIG 1 -#define SYN_MT_REPORT 2 -#define SYN_DROPPED 3 -#define SYN_MAX 0xf -#define SYN_CNT (SYN_MAX+1) - -/* - * Keys and buttons - * - * Most of the keys/buttons are modeled after USB HUT 1.12 - * (see http://www.usb.org/developers/hidpage). - * Abbreviations in the comments: - * AC - Application Control - * AL - Application Launch Button - * SC - System Control - */ - -#define KEY_RESERVED 0 -#define KEY_ESC 1 -#define KEY_1 2 -#define KEY_2 3 -#define KEY_3 4 -#define KEY_4 5 -#define KEY_5 6 -#define KEY_6 7 -#define KEY_7 8 -#define KEY_8 9 -#define KEY_9 10 -#define KEY_0 11 -#define KEY_MINUS 12 -#define KEY_EQUAL 13 -#define KEY_BACKSPACE 14 -#define KEY_TAB 15 -#define KEY_Q 16 -#define KEY_W 17 -#define KEY_E 18 -#define KEY_R 19 -#define KEY_T 20 -#define KEY_Y 21 -#define KEY_U 22 -#define KEY_I 23 -#define KEY_O 24 -#define KEY_P 25 -#define KEY_LEFTBRACE 26 -#define KEY_RIGHTBRACE 27 -#define KEY_ENTER 28 -#define KEY_LEFTCTRL 29 -#define KEY_A 30 -#define KEY_S 31 -#define KEY_D 32 -#define KEY_F 33 -#define KEY_G 34 -#define KEY_H 35 -#define KEY_J 36 -#define KEY_K 37 -#define KEY_L 38 -#define KEY_SEMICOLON 39 -#define KEY_APOSTROPHE 40 -#define KEY_GRAVE 41 -#define KEY_LEFTSHIFT 42 -#define KEY_BACKSLASH 43 -#define KEY_Z 44 -#define KEY_X 45 -#define KEY_C 46 -#define KEY_V 47 -#define KEY_B 48 -#define KEY_N 49 -#define KEY_M 50 -#define KEY_COMMA 51 -#define KEY_DOT 52 -#define KEY_SLASH 53 -#define KEY_RIGHTSHIFT 54 -#define KEY_KPASTERISK 55 -#define KEY_LEFTALT 56 -#define KEY_SPACE 57 -#define KEY_CAPSLOCK 58 -#define KEY_F1 59 -#define KEY_F2 60 -#define KEY_F3 61 -#define KEY_F4 62 -#define KEY_F5 63 -#define KEY_F6 64 -#define KEY_F7 65 -#define KEY_F8 66 -#define KEY_F9 67 -#define KEY_F10 68 -#define KEY_NUMLOCK 69 -#define KEY_SCROLLLOCK 70 -#define KEY_KP7 71 -#define KEY_KP8 72 -#define KEY_KP9 73 -#define KEY_KPMINUS 74 -#define KEY_KP4 75 -#define KEY_KP5 76 -#define KEY_KP6 77 -#define KEY_KPPLUS 78 -#define KEY_KP1 79 -#define KEY_KP2 80 -#define KEY_KP3 81 -#define KEY_KP0 82 -#define KEY_KPDOT 83 - -#define KEY_ZENKAKUHANKAKU 85 -#define KEY_102ND 86 -#define KEY_F11 87 -#define KEY_F12 88 -#define KEY_RO 89 -#define KEY_KATAKANA 90 -#define KEY_HIRAGANA 91 -#define KEY_HENKAN 92 -#define KEY_KATAKANAHIRAGANA 93 -#define KEY_MUHENKAN 94 -#define KEY_KPJPCOMMA 95 -#define KEY_KPENTER 96 -#define KEY_RIGHTCTRL 97 -#define KEY_KPSLASH 98 -#define KEY_SYSRQ 99 -#define KEY_RIGHTALT 100 -#define KEY_LINEFEED 101 -#define KEY_HOME 102 -#define KEY_UP 103 -#define KEY_PAGEUP 104 -#define KEY_LEFT 105 -#define KEY_RIGHT 106 -#define KEY_END 107 -#define KEY_DOWN 108 -#define KEY_PAGEDOWN 109 -#define KEY_INSERT 110 -#define KEY_DELETE 111 -#define KEY_MACRO 112 -#define KEY_MUTE 113 -#define KEY_VOLUMEDOWN 114 -#define KEY_VOLUMEUP 115 -#define KEY_POWER 116 /* SC System Power Down */ -#define KEY_KPEQUAL 117 -#define KEY_KPPLUSMINUS 118 -#define KEY_PAUSE 119 -#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ - -#define KEY_KPCOMMA 121 -#define KEY_HANGEUL 122 -#define KEY_HANGUEL KEY_HANGEUL -#define KEY_HANJA 123 -#define KEY_YEN 124 -#define KEY_LEFTMETA 125 -#define KEY_RIGHTMETA 126 -#define KEY_COMPOSE 127 - -#define KEY_STOP 128 /* AC Stop */ -#define KEY_AGAIN 129 -#define KEY_PROPS 130 /* AC Properties */ -#define KEY_UNDO 131 /* AC Undo */ -#define KEY_FRONT 132 -#define KEY_COPY 133 /* AC Copy */ -#define KEY_OPEN 134 /* AC Open */ -#define KEY_PASTE 135 /* AC Paste */ -#define KEY_FIND 136 /* AC Search */ -#define KEY_CUT 137 /* AC Cut */ -#define KEY_HELP 138 /* AL Integrated Help Center */ -#define KEY_MENU 139 /* Menu (show menu) */ -#define KEY_CALC 140 /* AL Calculator */ -#define KEY_SETUP 141 -#define KEY_SLEEP 142 /* SC System Sleep */ -#define KEY_WAKEUP 143 /* System Wake Up */ -#define KEY_FILE 144 /* AL Local Machine Browser */ -#define KEY_SENDFILE 145 -#define KEY_DELETEFILE 146 -#define KEY_XFER 147 -#define KEY_PROG1 148 -#define KEY_PROG2 149 -#define KEY_WWW 150 /* AL Internet Browser */ -#define KEY_MSDOS 151 -#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ -#define KEY_SCREENLOCK KEY_COFFEE -#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ -#define KEY_DIRECTION KEY_ROTATE_DISPLAY -#define KEY_CYCLEWINDOWS 154 -#define KEY_MAIL 155 -#define KEY_BOOKMARKS 156 /* AC Bookmarks */ -#define KEY_COMPUTER 157 -#define KEY_BACK 158 /* AC Back */ -#define KEY_FORWARD 159 /* AC Forward */ -#define KEY_CLOSECD 160 -#define KEY_EJECTCD 161 -#define KEY_EJECTCLOSECD 162 -#define KEY_NEXTSONG 163 -#define KEY_PLAYPAUSE 164 -#define KEY_PREVIOUSSONG 165 -#define KEY_STOPCD 166 -#define KEY_RECORD 167 -#define KEY_REWIND 168 -#define KEY_PHONE 169 /* Media Select Telephone */ -#define KEY_ISO 170 -#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ -#define KEY_HOMEPAGE 172 /* AC Home */ -#define KEY_REFRESH 173 /* AC Refresh */ -#define KEY_EXIT 174 /* AC Exit */ -#define KEY_MOVE 175 -#define KEY_EDIT 176 -#define KEY_SCROLLUP 177 -#define KEY_SCROLLDOWN 178 -#define KEY_KPLEFTPAREN 179 -#define KEY_KPRIGHTPAREN 180 -#define KEY_NEW 181 /* AC New */ -#define KEY_REDO 182 /* AC Redo/Repeat */ - -#define KEY_F13 183 -#define KEY_F14 184 -#define KEY_F15 185 -#define KEY_F16 186 -#define KEY_F17 187 -#define KEY_F18 188 -#define KEY_F19 189 -#define KEY_F20 190 -#define KEY_F21 191 -#define KEY_F22 192 -#define KEY_F23 193 -#define KEY_F24 194 - -#define KEY_PLAYCD 200 -#define KEY_PAUSECD 201 -#define KEY_PROG3 202 -#define KEY_PROG4 203 -#define KEY_DASHBOARD 204 /* AL Dashboard */ -#define KEY_SUSPEND 205 -#define KEY_CLOSE 206 /* AC Close */ -#define KEY_PLAY 207 -#define KEY_FASTFORWARD 208 -#define KEY_BASSBOOST 209 -#define KEY_PRINT 210 /* AC Print */ -#define KEY_HP 211 -#define KEY_CAMERA 212 -#define KEY_SOUND 213 -#define KEY_QUESTION 214 -#define KEY_EMAIL 215 -#define KEY_CHAT 216 -#define KEY_SEARCH 217 -#define KEY_CONNECT 218 -#define KEY_FINANCE 219 /* AL Checkbook/Finance */ -#define KEY_SPORT 220 -#define KEY_SHOP 221 -#define KEY_ALTERASE 222 -#define KEY_CANCEL 223 /* AC Cancel */ -#define KEY_BRIGHTNESSDOWN 224 -#define KEY_BRIGHTNESSUP 225 -#define KEY_MEDIA 226 - -#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video - outputs (Monitor/LCD/TV-out/etc) */ -#define KEY_KBDILLUMTOGGLE 228 -#define KEY_KBDILLUMDOWN 229 -#define KEY_KBDILLUMUP 230 - -#define KEY_SEND 231 /* AC Send */ -#define KEY_REPLY 232 /* AC Reply */ -#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ -#define KEY_SAVE 234 /* AC Save */ -#define KEY_DOCUMENTS 235 - -#define KEY_BATTERY 236 - -#define KEY_BLUETOOTH 237 -#define KEY_WLAN 238 -#define KEY_UWB 239 - -#define KEY_UNKNOWN 240 - -#define KEY_VIDEO_NEXT 241 /* drive next video source */ -#define KEY_VIDEO_PREV 242 /* drive previous video source */ -#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ -#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual - brightness control is off, - rely on ambient */ -#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO -#define KEY_DISPLAY_OFF 245 /* display device to off state */ - -#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ -#define KEY_WIMAX KEY_WWAN -#define KEY_RFKILL 247 /* Key that controls all radios */ - -#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ - -/* Code 255 is reserved for special needs of AT keyboard driver */ - -#define BTN_MISC 0x100 -#define BTN_0 0x100 -#define BTN_1 0x101 -#define BTN_2 0x102 -#define BTN_3 0x103 -#define BTN_4 0x104 -#define BTN_5 0x105 -#define BTN_6 0x106 -#define BTN_7 0x107 -#define BTN_8 0x108 -#define BTN_9 0x109 - -#define BTN_MOUSE 0x110 -#define BTN_LEFT 0x110 -#define BTN_RIGHT 0x111 -#define BTN_MIDDLE 0x112 -#define BTN_SIDE 0x113 -#define BTN_EXTRA 0x114 -#define BTN_FORWARD 0x115 -#define BTN_BACK 0x116 -#define BTN_TASK 0x117 - -#define BTN_JOYSTICK 0x120 -#define BTN_TRIGGER 0x120 -#define BTN_THUMB 0x121 -#define BTN_THUMB2 0x122 -#define BTN_TOP 0x123 -#define BTN_TOP2 0x124 -#define BTN_PINKIE 0x125 -#define BTN_BASE 0x126 -#define BTN_BASE2 0x127 -#define BTN_BASE3 0x128 -#define BTN_BASE4 0x129 -#define BTN_BASE5 0x12a -#define BTN_BASE6 0x12b -#define BTN_DEAD 0x12f - -#define BTN_GAMEPAD 0x130 -#define BTN_SOUTH 0x130 -#define BTN_A BTN_SOUTH -#define BTN_EAST 0x131 -#define BTN_B BTN_EAST -#define BTN_C 0x132 -#define BTN_NORTH 0x133 -#define BTN_X BTN_NORTH -#define BTN_WEST 0x134 -#define BTN_Y BTN_WEST -#define BTN_Z 0x135 -#define BTN_TL 0x136 -#define BTN_TR 0x137 -#define BTN_TL2 0x138 -#define BTN_TR2 0x139 -#define BTN_SELECT 0x13a -#define BTN_START 0x13b -#define BTN_MODE 0x13c -#define BTN_THUMBL 0x13d -#define BTN_THUMBR 0x13e - -#define BTN_DIGI 0x140 -#define BTN_TOOL_PEN 0x140 -#define BTN_TOOL_RUBBER 0x141 -#define BTN_TOOL_BRUSH 0x142 -#define BTN_TOOL_PENCIL 0x143 -#define BTN_TOOL_AIRBRUSH 0x144 -#define BTN_TOOL_FINGER 0x145 -#define BTN_TOOL_MOUSE 0x146 -#define BTN_TOOL_LENS 0x147 -#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ -#define BTN_TOUCH 0x14a -#define BTN_STYLUS 0x14b -#define BTN_STYLUS2 0x14c -#define BTN_TOOL_DOUBLETAP 0x14d -#define BTN_TOOL_TRIPLETAP 0x14e -#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ - -#define BTN_WHEEL 0x150 -#define BTN_GEAR_DOWN 0x150 -#define BTN_GEAR_UP 0x151 - -#define KEY_OK 0x160 -#define KEY_SELECT 0x161 -#define KEY_GOTO 0x162 -#define KEY_CLEAR 0x163 -#define KEY_POWER2 0x164 -#define KEY_OPTION 0x165 -#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ -#define KEY_TIME 0x167 -#define KEY_VENDOR 0x168 -#define KEY_ARCHIVE 0x169 -#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ -#define KEY_CHANNEL 0x16b -#define KEY_FAVORITES 0x16c -#define KEY_EPG 0x16d -#define KEY_PVR 0x16e /* Media Select Home */ -#define KEY_MHP 0x16f -#define KEY_LANGUAGE 0x170 -#define KEY_TITLE 0x171 -#define KEY_SUBTITLE 0x172 -#define KEY_ANGLE 0x173 -#define KEY_ZOOM 0x174 -#define KEY_MODE 0x175 -#define KEY_KEYBOARD 0x176 -#define KEY_SCREEN 0x177 -#define KEY_PC 0x178 /* Media Select Computer */ -#define KEY_TV 0x179 /* Media Select TV */ -#define KEY_TV2 0x17a /* Media Select Cable */ -#define KEY_VCR 0x17b /* Media Select VCR */ -#define KEY_VCR2 0x17c /* VCR Plus */ -#define KEY_SAT 0x17d /* Media Select Satellite */ -#define KEY_SAT2 0x17e -#define KEY_CD 0x17f /* Media Select CD */ -#define KEY_TAPE 0x180 /* Media Select Tape */ -#define KEY_RADIO 0x181 -#define KEY_TUNER 0x182 /* Media Select Tuner */ -#define KEY_PLAYER 0x183 -#define KEY_TEXT 0x184 -#define KEY_DVD 0x185 /* Media Select DVD */ -#define KEY_AUX 0x186 -#define KEY_MP3 0x187 -#define KEY_AUDIO 0x188 /* AL Audio Browser */ -#define KEY_VIDEO 0x189 /* AL Movie Browser */ -#define KEY_DIRECTORY 0x18a -#define KEY_LIST 0x18b -#define KEY_MEMO 0x18c /* Media Select Messages */ -#define KEY_CALENDAR 0x18d -#define KEY_RED 0x18e -#define KEY_GREEN 0x18f -#define KEY_YELLOW 0x190 -#define KEY_BLUE 0x191 -#define KEY_CHANNELUP 0x192 /* Channel Increment */ -#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ -#define KEY_FIRST 0x194 -#define KEY_LAST 0x195 /* Recall Last */ -#define KEY_AB 0x196 -#define KEY_NEXT 0x197 -#define KEY_RESTART 0x198 -#define KEY_SLOW 0x199 -#define KEY_SHUFFLE 0x19a -#define KEY_BREAK 0x19b -#define KEY_PREVIOUS 0x19c -#define KEY_DIGITS 0x19d -#define KEY_TEEN 0x19e -#define KEY_TWEN 0x19f -#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ -#define KEY_GAMES 0x1a1 /* Media Select Games */ -#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ -#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ -#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ -#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ -#define KEY_EDITOR 0x1a6 /* AL Text Editor */ -#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ -#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ -#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ -#define KEY_DATABASE 0x1aa /* AL Database App */ -#define KEY_NEWS 0x1ab /* AL Newsreader */ -#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ -#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ -#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ -#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ -#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE -#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ -#define KEY_LOGOFF 0x1b1 /* AL Logoff */ - -#define KEY_DOLLAR 0x1b2 -#define KEY_EURO 0x1b3 - -#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ -#define KEY_FRAMEFORWARD 0x1b5 -#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ -#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ -#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ -#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ -#define KEY_IMAGES 0x1ba /* AL Image Browser */ - -#define KEY_DEL_EOL 0x1c0 -#define KEY_DEL_EOS 0x1c1 -#define KEY_INS_LINE 0x1c2 -#define KEY_DEL_LINE 0x1c3 - -#define KEY_FN 0x1d0 -#define KEY_FN_ESC 0x1d1 -#define KEY_FN_F1 0x1d2 -#define KEY_FN_F2 0x1d3 -#define KEY_FN_F3 0x1d4 -#define KEY_FN_F4 0x1d5 -#define KEY_FN_F5 0x1d6 -#define KEY_FN_F6 0x1d7 -#define KEY_FN_F7 0x1d8 -#define KEY_FN_F8 0x1d9 -#define KEY_FN_F9 0x1da -#define KEY_FN_F10 0x1db -#define KEY_FN_F11 0x1dc -#define KEY_FN_F12 0x1dd -#define KEY_FN_1 0x1de -#define KEY_FN_2 0x1df -#define KEY_FN_D 0x1e0 -#define KEY_FN_E 0x1e1 -#define KEY_FN_F 0x1e2 -#define KEY_FN_S 0x1e3 -#define KEY_FN_B 0x1e4 - -#define KEY_BRL_DOT1 0x1f1 -#define KEY_BRL_DOT2 0x1f2 -#define KEY_BRL_DOT3 0x1f3 -#define KEY_BRL_DOT4 0x1f4 -#define KEY_BRL_DOT5 0x1f5 -#define KEY_BRL_DOT6 0x1f6 -#define KEY_BRL_DOT7 0x1f7 -#define KEY_BRL_DOT8 0x1f8 -#define KEY_BRL_DOT9 0x1f9 -#define KEY_BRL_DOT10 0x1fa - -#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ -#define KEY_NUMERIC_1 0x201 /* and other keypads */ -#define KEY_NUMERIC_2 0x202 -#define KEY_NUMERIC_3 0x203 -#define KEY_NUMERIC_4 0x204 -#define KEY_NUMERIC_5 0x205 -#define KEY_NUMERIC_6 0x206 -#define KEY_NUMERIC_7 0x207 -#define KEY_NUMERIC_8 0x208 -#define KEY_NUMERIC_9 0x209 -#define KEY_NUMERIC_STAR 0x20a -#define KEY_NUMERIC_POUND 0x20b -#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ -#define KEY_NUMERIC_B 0x20d -#define KEY_NUMERIC_C 0x20e -#define KEY_NUMERIC_D 0x20f - -#define KEY_CAMERA_FOCUS 0x210 -#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ - -#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ -#define KEY_TOUCHPAD_ON 0x213 -#define KEY_TOUCHPAD_OFF 0x214 - -#define KEY_CAMERA_ZOOMIN 0x215 -#define KEY_CAMERA_ZOOMOUT 0x216 -#define KEY_CAMERA_UP 0x217 -#define KEY_CAMERA_DOWN 0x218 -#define KEY_CAMERA_LEFT 0x219 -#define KEY_CAMERA_RIGHT 0x21a - -#define KEY_ATTENDANT_ON 0x21b -#define KEY_ATTENDANT_OFF 0x21c -#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ -#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ - -#define BTN_DPAD_UP 0x220 -#define BTN_DPAD_DOWN 0x221 -#define BTN_DPAD_LEFT 0x222 -#define BTN_DPAD_RIGHT 0x223 - -#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ - -#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ -#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ -#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ -#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ -#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ -#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ -#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ - -#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ -#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ - -#define KEY_KBDINPUTASSIST_PREV 0x260 -#define KEY_KBDINPUTASSIST_NEXT 0x261 -#define KEY_KBDINPUTASSIST_PREVGROUP 0x262 -#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 -#define KEY_KBDINPUTASSIST_ACCEPT 0x264 -#define KEY_KBDINPUTASSIST_CANCEL 0x265 - -#define BTN_TRIGGER_HAPPY 0x2c0 -#define BTN_TRIGGER_HAPPY1 0x2c0 -#define BTN_TRIGGER_HAPPY2 0x2c1 -#define BTN_TRIGGER_HAPPY3 0x2c2 -#define BTN_TRIGGER_HAPPY4 0x2c3 -#define BTN_TRIGGER_HAPPY5 0x2c4 -#define BTN_TRIGGER_HAPPY6 0x2c5 -#define BTN_TRIGGER_HAPPY7 0x2c6 -#define BTN_TRIGGER_HAPPY8 0x2c7 -#define BTN_TRIGGER_HAPPY9 0x2c8 -#define BTN_TRIGGER_HAPPY10 0x2c9 -#define BTN_TRIGGER_HAPPY11 0x2ca -#define BTN_TRIGGER_HAPPY12 0x2cb -#define BTN_TRIGGER_HAPPY13 0x2cc -#define BTN_TRIGGER_HAPPY14 0x2cd -#define BTN_TRIGGER_HAPPY15 0x2ce -#define BTN_TRIGGER_HAPPY16 0x2cf -#define BTN_TRIGGER_HAPPY17 0x2d0 -#define BTN_TRIGGER_HAPPY18 0x2d1 -#define BTN_TRIGGER_HAPPY19 0x2d2 -#define BTN_TRIGGER_HAPPY20 0x2d3 -#define BTN_TRIGGER_HAPPY21 0x2d4 -#define BTN_TRIGGER_HAPPY22 0x2d5 -#define BTN_TRIGGER_HAPPY23 0x2d6 -#define BTN_TRIGGER_HAPPY24 0x2d7 -#define BTN_TRIGGER_HAPPY25 0x2d8 -#define BTN_TRIGGER_HAPPY26 0x2d9 -#define BTN_TRIGGER_HAPPY27 0x2da -#define BTN_TRIGGER_HAPPY28 0x2db -#define BTN_TRIGGER_HAPPY29 0x2dc -#define BTN_TRIGGER_HAPPY30 0x2dd -#define BTN_TRIGGER_HAPPY31 0x2de -#define BTN_TRIGGER_HAPPY32 0x2df -#define BTN_TRIGGER_HAPPY33 0x2e0 -#define BTN_TRIGGER_HAPPY34 0x2e1 -#define BTN_TRIGGER_HAPPY35 0x2e2 -#define BTN_TRIGGER_HAPPY36 0x2e3 -#define BTN_TRIGGER_HAPPY37 0x2e4 -#define BTN_TRIGGER_HAPPY38 0x2e5 -#define BTN_TRIGGER_HAPPY39 0x2e6 -#define BTN_TRIGGER_HAPPY40 0x2e7 - -/* We avoid low common keys in module aliases so they don't get huge. */ -#define KEY_MIN_INTERESTING KEY_MUTE -#define KEY_MAX 0x2ff -#define KEY_CNT (KEY_MAX+1) - -/* - * Relative axes - */ - -#define REL_X 0x00 -#define REL_Y 0x01 -#define REL_Z 0x02 -#define REL_RX 0x03 -#define REL_RY 0x04 -#define REL_RZ 0x05 -#define REL_HWHEEL 0x06 -#define REL_DIAL 0x07 -#define REL_WHEEL 0x08 -#define REL_MISC 0x09 -#define REL_MAX 0x0f -#define REL_CNT (REL_MAX+1) - -/* - * Absolute axes - */ - -#define ABS_X 0x00 -#define ABS_Y 0x01 -#define ABS_Z 0x02 -#define ABS_RX 0x03 -#define ABS_RY 0x04 -#define ABS_RZ 0x05 -#define ABS_THROTTLE 0x06 -#define ABS_RUDDER 0x07 -#define ABS_WHEEL 0x08 -#define ABS_GAS 0x09 -#define ABS_BRAKE 0x0a -#define ABS_HAT0X 0x10 -#define ABS_HAT0Y 0x11 -#define ABS_HAT1X 0x12 -#define ABS_HAT1Y 0x13 -#define ABS_HAT2X 0x14 -#define ABS_HAT2Y 0x15 -#define ABS_HAT3X 0x16 -#define ABS_HAT3Y 0x17 -#define ABS_PRESSURE 0x18 -#define ABS_DISTANCE 0x19 -#define ABS_TILT_X 0x1a -#define ABS_TILT_Y 0x1b -#define ABS_TOOL_WIDTH 0x1c - -#define ABS_VOLUME 0x20 - -#define ABS_MISC 0x28 - -#define ABS_MT_SLOT 0x2f /* MT slot being modified */ -#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ -#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ -#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ -#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ -#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ -#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ -#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ -#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ -#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ -#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ -#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ -#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ -#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ -#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ - - -#define ABS_MAX 0x3f -#define ABS_CNT (ABS_MAX+1) - -/* - * Switch events - */ - -#define SW_LID 0x00 /* set = lid shut */ -#define SW_TABLET_MODE 0x01 /* set = tablet mode */ -#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ -#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" - set = radio enabled */ -#define SW_RADIO SW_RFKILL_ALL /* deprecated */ -#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ -#define SW_DOCK 0x05 /* set = plugged into dock */ -#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ -#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ -#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ -#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ -#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ -#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ -#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ -#define SW_LINEIN_INSERT 0x0d /* set = inserted */ -#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ -#define SW_MAX 0x10 -#define SW_CNT (SW_MAX+1) - -/* - * Misc events - */ - -#define MSC_SERIAL 0x00 -#define MSC_PULSELED 0x01 -#define MSC_GESTURE 0x02 -#define MSC_RAW 0x03 -#define MSC_SCAN 0x04 -#define MSC_TIMESTAMP 0x05 -#define MSC_MAX 0x07 -#define MSC_CNT (MSC_MAX+1) - -/* - * LEDs - */ - -#define LED_NUML 0x00 -#define LED_CAPSL 0x01 -#define LED_SCROLLL 0x02 -#define LED_COMPOSE 0x03 -#define LED_KANA 0x04 -#define LED_SLEEP 0x05 -#define LED_SUSPEND 0x06 -#define LED_MUTE 0x07 -#define LED_MISC 0x08 -#define LED_MAIL 0x09 -#define LED_CHARGING 0x0a -#define LED_MAX 0x0f -#define LED_CNT (LED_MAX+1) - -/* - * Autorepeat values - */ - -#define REP_DELAY 0x00 -#define REP_PERIOD 0x01 -#define REP_MAX 0x01 -#define REP_CNT (REP_MAX+1) - -/* - * Sounds - */ - -#define SND_CLICK 0x00 -#define SND_BELL 0x01 -#define SND_TONE 0x02 -#define SND_MAX 0x07 -#define SND_CNT (SND_MAX+1) - -#endif diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h deleted file mode 100644 index 33a1003c55a..00000000000 --- a/include/dt-bindings/interrupt-controller/irq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This header provides constants for most IRQ bindings. - * - * Most IRQ bindings include a flags cell as part of the IRQ specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H - -#define IRQ_TYPE_NONE 0 -#define IRQ_TYPE_EDGE_RISING 1 -#define IRQ_TYPE_EDGE_FALLING 2 -#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 4 -#define IRQ_TYPE_LEVEL_LOW 8 - -#endif diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h deleted file mode 100644 index 9a0d33d027f..00000000000 --- a/include/dt-bindings/leds/common.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for the common LEDs device tree bindings. - * - * Copyright (C) 2015, Samsung Electronics Co., Ltd. - * Author: Jacek Anaszewski <j.anaszewski@samsung.com> - * - * Copyright (C) 2019 Jacek Anaszewski <jacek.anaszewski@gmail.com> - * Copyright (C) 2020 Pavel Machek <pavel@ucw.cz> - */ - -#ifndef __DT_BINDINGS_LEDS_H -#define __DT_BINDINGS_LEDS_H - -/* External trigger type */ -#define LEDS_TRIG_TYPE_EDGE 0 -#define LEDS_TRIG_TYPE_LEVEL 1 - -/* Boost modes */ -#define LEDS_BOOST_OFF 0 -#define LEDS_BOOST_ADAPTIVE 1 -#define LEDS_BOOST_FIXED 2 - -/* Standard LED colors */ -#define LED_COLOR_ID_WHITE 0 -#define LED_COLOR_ID_RED 1 -#define LED_COLOR_ID_GREEN 2 -#define LED_COLOR_ID_BLUE 3 -#define LED_COLOR_ID_AMBER 4 -#define LED_COLOR_ID_VIOLET 5 -#define LED_COLOR_ID_YELLOW 6 -#define LED_COLOR_ID_IR 7 -#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ -#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, - so this would include RGBW and similar */ -#define LED_COLOR_ID_PURPLE 10 -#define LED_COLOR_ID_ORANGE 11 -#define LED_COLOR_ID_PINK 12 -#define LED_COLOR_ID_CYAN 13 -#define LED_COLOR_ID_LIME 14 -#define LED_COLOR_ID_MAX 15 - -/* Standard LED functions */ -/* Keyboard LEDs, usually it would be input4::capslock etc. */ -/* Obsolete equivalent: "shift-key-light" */ -#define LED_FUNCTION_CAPSLOCK "capslock" -#define LED_FUNCTION_SCROLLLOCK "scrolllock" -#define LED_FUNCTION_NUMLOCK "numlock" -/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), - "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ -#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" - -/* System LEDs, usually found on system body. - platform::mute (etc) is sometimes seen, :mute would be better */ -#define LED_FUNCTION_POWER "power" -#define LED_FUNCTION_DISK "disk" - -/* Obsolete: "platform:*:charging" (allwinner sun50i) */ -#define LED_FUNCTION_CHARGING "charging" -/* Used RGB notification LEDs common on phones. - Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), - "lp5523:{r,g,b}" (Nokia N900) */ -#define LED_FUNCTION_STATUS "status" - -#define LED_FUNCTION_MICMUTE "micmute" -#define LED_FUNCTION_MUTE "mute" - -/* Used for player LEDs as found on game controllers from e.g. Nintendo, Sony. */ -#define LED_FUNCTION_PLAYER1 "player-1" -#define LED_FUNCTION_PLAYER2 "player-2" -#define LED_FUNCTION_PLAYER3 "player-3" -#define LED_FUNCTION_PLAYER4 "player-4" -#define LED_FUNCTION_PLAYER5 "player-5" - -/* Miscelleaus functions. Use functions above if you can. */ -#define LED_FUNCTION_ACTIVITY "activity" -#define LED_FUNCTION_ALARM "alarm" -#define LED_FUNCTION_BACKLIGHT "backlight" -#define LED_FUNCTION_BLUETOOTH "bluetooth" -#define LED_FUNCTION_BOOT "boot" -#define LED_FUNCTION_CPU "cpu" -#define LED_FUNCTION_DEBUG "debug" -#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" -#define LED_FUNCTION_DISK_ERR "disk-err" -#define LED_FUNCTION_DISK_READ "disk-read" -#define LED_FUNCTION_DISK_WRITE "disk-write" -#define LED_FUNCTION_FAULT "fault" -#define LED_FUNCTION_FLASH "flash" -#define LED_FUNCTION_HEARTBEAT "heartbeat" -#define LED_FUNCTION_INDICATOR "indicator" -#define LED_FUNCTION_LAN "lan" -#define LED_FUNCTION_MAIL "mail" -#define LED_FUNCTION_MTD "mtd" -#define LED_FUNCTION_PANIC "panic" -#define LED_FUNCTION_PROGRAMMING "programming" -#define LED_FUNCTION_RX "rx" -#define LED_FUNCTION_SD "sd" -#define LED_FUNCTION_STANDBY "standby" -#define LED_FUNCTION_TORCH "torch" -#define LED_FUNCTION_TX "tx" -#define LED_FUNCTION_USB "usb" -#define LED_FUNCTION_WAN "wan" -#define LED_FUNCTION_WLAN "wlan" -#define LED_FUNCTION_WPS "wps" - -#endif /* __DT_BINDINGS_LEDS_H */ diff --git a/include/dt-bindings/mux/mux.h b/include/dt-bindings/mux/mux.h deleted file mode 100644 index 042719218db..00000000000 --- a/include/dt-bindings/mux/mux.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most Multiplexer bindings. - * - * Most Multiplexer bindings specify an idle state. In most cases, the - * the multiplexer can be left as is when idle, and in some cases it can - * disconnect the input/output and leave the multiplexer in a high - * impedance state. - */ - -#ifndef _DT_BINDINGS_MUX_MUX_H -#define _DT_BINDINGS_MUX_MUX_H - -#define MUX_IDLE_AS_IS (-1) -#define MUX_IDLE_DISCONNECT (-2) - -#endif diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h deleted file mode 100644 index f48c9acf251..00000000000 --- a/include/dt-bindings/phy/phy.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * - * This header provides constants for the phy framework - * - * Copyright (C) 2014 STMicroelectronics - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> - */ - -#ifndef _DT_BINDINGS_PHY -#define _DT_BINDINGS_PHY - -#define PHY_NONE 0 -#define PHY_TYPE_SATA 1 -#define PHY_TYPE_PCIE 2 -#define PHY_TYPE_USB2 3 -#define PHY_TYPE_USB3 4 -#define PHY_TYPE_UFS 5 -#define PHY_TYPE_DP 6 -#define PHY_TYPE_XPCS 7 -#define PHY_TYPE_SGMII 8 -#define PHY_TYPE_QSGMII 9 -#define PHY_TYPE_DPHY 10 -#define PHY_TYPE_CPHY 11 - -#endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h deleted file mode 100644 index 96f49e82253..00000000000 --- a/include/dt-bindings/pwm/pwm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for most PWM bindings. - * - * Most PWM bindings can include a flags cell as part of the PWM specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_PWM_PWM_H -#define _DT_BINDINGS_PWM_PWM_H - -#define PWM_POLARITY_INVERTED (1 << 0) - -#endif diff --git a/include/dt-bindings/spmi/spmi.h b/include/dt-bindings/spmi/spmi.h deleted file mode 100644 index ad4a43481de..00000000000 --- a/include/dt-bindings/spmi/spmi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ -#ifndef __DT_BINDINGS_SPMI_H -#define __DT_BINDINGS_SPMI_H - -#define SPMI_USID 0 -#define SPMI_GSID 1 - -#endif diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h deleted file mode 100644 index 7871e5f52b1..00000000000 --- a/include/dt-bindings/thermal/thermal.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for most thermal bindings. - * - * Copyright (C) 2013 Texas Instruments - * Eduardo Valentin <eduardo.valentin@ti.com> - */ - -#ifndef _DT_BINDINGS_THERMAL_THERMAL_H -#define _DT_BINDINGS_THERMAL_THERMAL_H - -/* On cooling devices upper and lower limits */ -#define THERMAL_NO_LIMIT (~0) - -#endif diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h deleted file mode 100644 index 985f2bbd4d2..00000000000 --- a/include/dt-bindings/usb/pd.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_POWER_DELIVERY_H -#define __DT_POWER_DELIVERY_H - -/* Power delivery Power Data Object definitions */ -#define PDO_TYPE_FIXED 0 -#define PDO_TYPE_BATT 1 -#define PDO_TYPE_VAR 2 -#define PDO_TYPE_APDO 3 - -#define PDO_TYPE_SHIFT 30 -#define PDO_TYPE_MASK 0x3 - -#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) - -#define PDO_VOLT_MASK 0x3ff -#define PDO_CURR_MASK 0x3ff -#define PDO_PWR_MASK 0x3ff - -#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ -#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ -#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ -#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ -#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ -#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ -#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ - -#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) -#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) - -#define PDO_FIXED(mv, ma, flags) \ - (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ - PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) - -#define VSAFE5V 5000 /* mv units */ - -#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ -#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ - -#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) -#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) -#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) - -#define PDO_BATT(min_mv, max_mv, max_mw) \ - (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ - PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) - -#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ -#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ - -#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) -#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) -#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) - -#define PDO_VAR(min_mv, max_mv, max_ma) \ - (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ - PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) - -#define APDO_TYPE_PPS 0 - -#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ -#define PDO_APDO_TYPE_MASK 0x3 - -#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) - -#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ -#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ -#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ - -#define PDO_PPS_APDO_VOLT_MASK 0xff -#define PDO_PPS_APDO_CURR_MASK 0x7f - -#define PDO_PPS_APDO_MIN_VOLT(mv) \ - ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) -#define PDO_PPS_APDO_MAX_VOLT(mv) \ - ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) -#define PDO_PPS_APDO_MAX_CURR(ma) \ - ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) - -#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ - (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ - PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ - PDO_PPS_APDO_MAX_CURR(max_ma)) - - #endif /* __DT_POWER_DELIVERY_H */ diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index 8acae3839fb..f4d66edacee 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -534,6 +534,14 @@ struct hdmi_data_info { struct hdmi_vmode video_mode; }; +struct dw_hdmi; + +struct dw_hdmi_phy_ops { + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); + void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); + void (*setup_hpd)(struct dw_hdmi *hdmi); +}; + struct dw_hdmi { ulong ioaddr; const struct hdmi_mpll_config *mpll_cfg; @@ -543,8 +551,8 @@ struct dw_hdmi { u8 reg_io_width; struct hdmi_data_info hdmi_data; struct udevice *ddc_bus; + const struct dw_hdmi_phy_ops *ops; - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); }; @@ -556,5 +564,6 @@ void dw_hdmi_phy_init(struct dw_hdmi *hdmi); int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); void dw_hdmi_init(struct dw_hdmi *hdmi); +int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi); #endif diff --git a/include/efi_loader.h b/include/efi_loader.h index bb51c028177..69442f4e58d 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -159,6 +159,10 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, #define EFICONFIG_AUTO_GENERATED_ENTRY_GUID \ EFI_GUID(0x8108ac4e, 0x9f11, 0x4d59, \ 0x85, 0x0e, 0xe2, 0x1a, 0x52, 0x2c, 0x59, 0xb2) +#define U_BOOT_EFI_RT_VAR_FILE_GUID \ + EFI_GUID(0xb2ac5fc9, 0x92b7, 0x4acd, \ + 0xae, 0xac, 0x11, 0xe8, 0x18, 0xc3, 0x13, 0x0c) + /* Use internal device tree when starting UEFI application */ #define EFI_FDT_USE_INTERNAL NULL diff --git a/include/efi_variable.h b/include/efi_variable.h index 42a2b7c52be..223bb9a4a5b 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -271,13 +271,16 @@ const efi_guid_t *efi_auth_var_get_guid(const u16 *name); * * @variable_name_size: size of variable_name buffer in bytes * @variable_name: name of uefi variable's name in u16 + * @mask: bitmask with required attributes of variables to be collected. + * variables are only collected if all of the required + * attributes match. Use 0 to skip matching * @vendor: vendor's guid * * Return: status code */ efi_status_t __efi_runtime efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_name, - efi_guid_t *vendor); + efi_guid_t *vendor, u32 mask); /** * efi_get_variable_mem() - Runtime common code across efi variable * implementations for GetVariable() from @@ -289,12 +292,15 @@ efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_na * @data_size: size of the buffer to which the variable value is copied * @data: buffer to which the variable value is copied * @timep: authentication time (seconds since start of epoch) + * @mask: bitmask with required attributes of variables to be collected. + * variables are only collected if all of the required + * attributes match. Use 0 to skip matching * Return: status code */ efi_status_t __efi_runtime efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, efi_uintn_t *data_size, void *data, - u64 *timep); + u64 *timep, u32 mask); /** * efi_get_variable_runtime() - runtime implementation of GetVariable() @@ -334,4 +340,10 @@ efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, */ void efi_var_buf_update(struct efi_var_file *var_buf); +efi_status_t __efi_runtime efi_var_collect_mem(struct efi_var_file *buf, + efi_uintn_t *lenp, + u32 check_attr_mask); + +u32 efi_var_entry_len(struct efi_var_entry *var); + #endif diff --git a/include/fdt_support.h b/include/fdt_support.h index 25600d62f29..4b71b8948d9 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -423,6 +423,8 @@ int arch_fixup_memory_node(void *blob); int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, u32 height, u32 stride, const char *format); +int fdt_add_fb_mem_rsv(void *blob); + int fdt_overlay_apply_verbose(void *fdt, void *fdto); int fdt_valid(struct fdt_header **blobp); diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 7a66c7af749..ee18a63e460 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -153,7 +153,7 @@ struct mtd_info { uint32_t flags; uint64_t size; // Total size of the MTD - /* "Major" erase size for the device. Naïve users may take this + /* "Major" erase size for the device. Naive users may take this * to be the only erase size available, or may use the more detailed * information below if they desire */ diff --git a/include/power/tps65941.h b/include/power/tps65941.h index a2bc6814bad..cec85333f0b 100644 --- a/include/power/tps65941.h +++ b/include/power/tps65941.h @@ -3,11 +3,14 @@ #define TPS659413 0x2 #define TPS659414 0x3 #define LP876441 0x4 +#define TPS65224 0x5 /* I2C device address for pmic tps65941 */ #define TPS65941_I2C_ADDR (0x12 >> 1) #define TPS65941_LDO_NUM 4 #define TPS65941_BUCK_NUM 5 +#define TPS65224_LDO_NUM 3 +#define TPS65224_BUCK_NUM 4 /* Drivers name */ #define TPS65941_LDO_DRIVER "tps65941_ldo" @@ -25,3 +28,30 @@ #define TPS65941_LDO_MODE_MASK 0x1 #define TPS65941_LDO_BYPASS_EN 0x80 #define TP65941_BUCK_CONF_SLEW_MASK 0x7 + +#define TPS65224_BUCK_VOLT_MAX 3300000 +#define TPS65224_BUCK1_VOLT_MAX_HEX 0xFD +#define TPS65224_BUCK234_VOLT_MAX_HEX 0x45 + +#define TPS65224_BUCK_CONF_SLEW_MASK 0x3 +#define TPS65224_LDO_VOLT_MASK (0x3F << 1) + +#define TPS65224_LDO1_VOLT_MIN_HEX 0x0C +#define TPS65224_LDO23_VOLT_MIN_HEX 0x00 +#define TPS65224_LDO1_VOLT_MAX_HEX 0x36 +#define TPS65224_LDO23_VOLT_MAX_HEX 0x38 + +#define TPS65224_LDO1_VOLT_MAX 3300000 +#define TPS65224_LDO23_VOLT_MAX 3400000 +#define TPS65224_LDO1_VOLT_MIN 1200000 +#define TPS65224_LDO23_VOLT_MIN 600000 + +#define TPS65224_LDO_STEP 50000 + +#define TPS65224_LDO_BYP_CONFIG 7 + +#define TPS65224_LDO1_VOLT_BYP_MIN 2200000 +#define TPS65224_LDO1_VOLT_BYP_MAX 3600000 + +#define TPS65224_LDO23_VOLT_BYP_MIN 1500000 +#define TPS65224_LDO23_VOLT_BYP_MAX 5500000 diff --git a/include/sdhci.h b/include/sdhci.h index a1b74e3bd79..78ef0d1c088 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -11,6 +11,7 @@ #include <linux/bitops.h> #include <linux/types.h> +#include <linux/kernel.h> #include <asm/io.h> #include <mmc.h> #include <asm/gpio.h> @@ -291,16 +292,21 @@ struct sdhci_ops { * Return: 0 if successful, -ve on error */ int (*set_enhanced_strobe)(struct sdhci_host *host); + +#ifdef CONFIG_MMC_SDHCI_ADMA_HELPERS + void (*adma_write_desc)(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, bool end); +#endif }; #define ADMA_MAX_LEN 65532 -#ifdef CONFIG_DMA_ADDR_T_64BIT +#ifdef CONFIG_MMC_SDHCI_ADMA_64BIT #define ADMA_DESC_LEN 16 #else #define ADMA_DESC_LEN 8 #endif -#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \ - MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN +#define ADMA_TABLE_NO_ENTRIES DIV_ROUND_UP(CONFIG_SYS_MMC_MAX_BLK_COUNT * \ + MMC_MAX_BLOCK_LEN, ADMA_MAX_LEN) #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN) @@ -319,7 +325,7 @@ struct sdhci_adma_desc { u8 reserved; u16 len; u32 addr_lo; -#ifdef CONFIG_DMA_ADDR_T_64BIT +#ifdef CONFIG_MMC_SDHCI_ADMA_64BIT u32 addr_hi; #endif } __packed; @@ -526,8 +532,11 @@ extern const struct dm_mmc_ops sdhci_ops; #else #endif +void sdhci_adma_write_desc(struct sdhci_host *host, void **next_desc, + dma_addr_t addr, int len, bool end); struct sdhci_adma_desc *sdhci_adma_init(void); -void sdhci_prepare_adma_table(struct sdhci_adma_desc *table, - struct mmc_data *data, dma_addr_t addr); +void sdhci_prepare_adma_table(struct sdhci_host *host, + struct sdhci_adma_desc *table, + struct mmc_data *data, dma_addr_t start_addr); #endif /* __SDHCI_HW_H */ diff --git a/include/soc/qcom/geni-se.h b/include/soc/qcom/geni-se.h new file mode 100644 index 00000000000..698a9256d26 --- /dev/null +++ b/include/soc/qcom/geni-se.h @@ -0,0 +1,265 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _QCOM_GENI_SE +#define _QCOM_GENI_SE + +/* Protocols supported by GENI Serial Engines */ +enum geni_se_protocol_type { + GENI_SE_NONE, + GENI_SE_SPI, + GENI_SE_UART, + GENI_SE_I2C, + GENI_SE_I3C, + GENI_SE_SPI_SLAVE, +}; + +#define QUP_HW_VER_REG 0x4 + +/* Common SE registers */ +#define GENI_INIT_CFG_REVISION 0x0 +#define GENI_S_INIT_CFG_REVISION 0x4 +#define GENI_FORCE_DEFAULT_REG 0x20 +#define GENI_OUTPUT_CTRL 0x24 +#define GENI_CGC_CTRL 0x28 +#define SE_GENI_STATUS 0x40 +#define GENI_SER_M_CLK_CFG 0x48 +#define GENI_SER_S_CLK_CFG 0x4c +#define GENI_IF_DISABLE_RO 0x64 +#define GENI_FW_REVISION_RO 0x68 +#define SE_GENI_CLK_SEL 0x7c +#define SE_GENI_CFG_SEQ_START 0x84 +#define SE_GENI_BYTE_GRAN 0x254 +#define SE_GENI_DMA_MODE_EN 0x258 +#define SE_GENI_TX_PACKING_CFG0 0x260 +#define SE_GENI_TX_PACKING_CFG1 0x264 +#define SE_GENI_RX_PACKING_CFG0 0x284 +#define SE_GENI_RX_PACKING_CFG1 0x288 +#define SE_GENI_M_CMD0 0x600 +#define SE_GENI_M_CMD_CTRL_REG 0x604 +#define SE_GENI_M_IRQ_STATUS 0x610 +#define SE_GENI_M_IRQ_EN 0x614 +#define SE_GENI_M_IRQ_CLEAR 0x618 +#define SE_GENI_S_CMD0 0x630 +#define SE_GENI_S_CMD_CTRL_REG 0x634 +#define SE_GENI_S_IRQ_STATUS 0x640 +#define SE_GENI_S_IRQ_EN 0x644 +#define SE_GENI_S_IRQ_CLEAR 0x648 +#define SE_GENI_TX_FIFOn 0x700 +#define SE_GENI_RX_FIFOn 0x780 +#define SE_GENI_TX_FIFO_STATUS 0x800 +#define SE_GENI_RX_FIFO_STATUS 0x804 +#define SE_GENI_TX_WATERMARK_REG 0x80c +#define SE_GENI_RX_WATERMARK_REG 0x810 +#define SE_GENI_RX_RFR_WATERMARK_REG 0x814 +#define SE_GENI_IOS 0x908 +#define SE_DMA_TX_IRQ_STAT 0xc40 +#define SE_DMA_TX_IRQ_CLR 0xc44 +#define SE_DMA_TX_FSM_RST 0xc58 +#define SE_DMA_RX_IRQ_STAT 0xd40 +#define SE_DMA_RX_IRQ_CLR 0xd44 +#define SE_DMA_RX_LEN_IN 0xd54 +#define SE_DMA_RX_FSM_RST 0xd58 +#define SE_GSI_EVENT_EN 0xe18 +#define SE_IRQ_EN 0xe1c +#define SE_HW_PARAM_0 0xe24 +#define SE_HW_PARAM_1 0xe28 + +/* GENI_FORCE_DEFAULT_REG fields */ +#define FORCE_DEFAULT BIT(0) + +/* GENI_OUTPUT_CTRL fields */ +#define GENI_IO_MUX_0_EN BIT(0) +#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) + +/* GENI_CGC_CTRL fields */ +#define CFG_AHB_CLK_CGC_ON BIT(0) +#define CFG_AHB_WR_ACLK_CGC_ON BIT(1) +#define DATA_AHB_CLK_CGC_ON BIT(2) +#define SCLK_CGC_ON BIT(3) +#define TX_CLK_CGC_ON BIT(4) +#define RX_CLK_CGC_ON BIT(5) +#define EXT_CLK_CGC_ON BIT(6) +#define PROG_RAM_HCLK_OFF BIT(8) +#define PROG_RAM_SCLK_OFF BIT(9) +#define DEFAULT_CGC_EN GENMASK(6, 0) + +/* GENI_STATUS fields */ +#define M_GENI_CMD_ACTIVE BIT(0) +#define S_GENI_CMD_ACTIVE BIT(12) + +/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ +#define SER_CLK_EN BIT(0) +#define CLK_DIV_MSK GENMASK(15, 4) +#define CLK_DIV_SHFT 4 + +/* GENI_IF_DISABLE_RO fields */ +#define FIFO_IF_DISABLE (BIT(0)) + +/* GENI_FW_REVISION_RO fields */ +#define FW_REV_PROTOCOL_MSK GENMASK(15, 8) +#define FW_REV_PROTOCOL_SHFT 8 + +/* GENI_CLK_SEL fields */ +#define CLK_SEL_MSK GENMASK(2, 0) + +/* SE_GENI_CFG_SEQ_START fields */ +#define START_TRIGGER BIT(0) + +/* SE_IRQ_EN fields */ +#define DMA_RX_IRQ_EN BIT(0) +#define DMA_TX_IRQ_EN BIT(1) +#define GENI_M_IRQ_EN BIT(2) +#define GENI_S_IRQ_EN BIT(3) + +/* SE_GENI_DMA_MODE_EN */ +#define GENI_DMA_MODE_EN BIT(0) + +/* GENI_M_CMD0 fields */ +#define M_OPCODE_MSK GENMASK(31, 27) +#define M_OPCODE_SHFT 27 +#define M_PARAMS_MSK GENMASK(26, 0) + +/* GENI_M_CMD_CTRL_REG */ +#define M_GENI_CMD_CANCEL BIT(2) +#define M_GENI_CMD_ABORT BIT(1) +#define M_GENI_DISABLE BIT(0) + +/* GENI_S_CMD0 fields */ +#define S_OPCODE_MSK GENMASK(31, 27) +#define S_OPCODE_SHFT 27 +#define S_PARAMS_MSK GENMASK(26, 0) + +/* GENI_S_CMD_CTRL_REG */ +#define S_GENI_CMD_CANCEL BIT(2) +#define S_GENI_CMD_ABORT BIT(1) +#define S_GENI_DISABLE BIT(0) + +/* GENI_M_IRQ_EN fields */ +#define M_CMD_DONE_EN BIT(0) +#define M_CMD_OVERRUN_EN BIT(1) +#define M_ILLEGAL_CMD_EN BIT(2) +#define M_CMD_FAILURE_EN BIT(3) +#define M_CMD_CANCEL_EN BIT(4) +#define M_CMD_ABORT_EN BIT(5) +#define M_TIMESTAMP_EN BIT(6) +#define M_RX_IRQ_EN BIT(7) +#define M_GP_SYNC_IRQ_0_EN BIT(8) +#define M_GP_IRQ_0_EN BIT(9) +#define M_GP_IRQ_1_EN BIT(10) +#define M_GP_IRQ_2_EN BIT(11) +#define M_GP_IRQ_3_EN BIT(12) +#define M_GP_IRQ_4_EN BIT(13) +#define M_GP_IRQ_5_EN BIT(14) +#define M_TX_FIFO_NOT_EMPTY_EN BIT(21) +#define M_IO_DATA_DEASSERT_EN BIT(22) +#define M_IO_DATA_ASSERT_EN BIT(23) +#define M_RX_FIFO_RD_ERR_EN BIT(24) +#define M_RX_FIFO_WR_ERR_EN BIT(25) +#define M_RX_FIFO_WATERMARK_EN BIT(26) +#define M_RX_FIFO_LAST_EN BIT(27) +#define M_TX_FIFO_RD_ERR_EN BIT(28) +#define M_TX_FIFO_WR_ERR_EN BIT(29) +#define M_TX_FIFO_WATERMARK_EN BIT(30) +#define M_SEC_IRQ_EN BIT(31) +#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ + M_IO_DATA_DEASSERT_EN | \ + M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ + M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ + M_TX_FIFO_WR_ERR_EN) + +/* GENI_S_IRQ_EN fields */ +#define S_CMD_DONE_EN BIT(0) +#define S_CMD_OVERRUN_EN BIT(1) +#define S_ILLEGAL_CMD_EN BIT(2) +#define S_CMD_FAILURE_EN BIT(3) +#define S_CMD_CANCEL_EN BIT(4) +#define S_CMD_ABORT_EN BIT(5) +#define S_GP_SYNC_IRQ_0_EN BIT(8) +#define S_GP_IRQ_0_EN BIT(9) +#define S_GP_IRQ_1_EN BIT(10) +#define S_GP_IRQ_2_EN BIT(11) +#define S_GP_IRQ_3_EN BIT(12) +#define S_GP_IRQ_4_EN BIT(13) +#define S_GP_IRQ_5_EN BIT(14) +#define S_IO_DATA_DEASSERT_EN BIT(22) +#define S_IO_DATA_ASSERT_EN BIT(23) +#define S_RX_FIFO_RD_ERR_EN BIT(24) +#define S_RX_FIFO_WR_ERR_EN BIT(25) +#define S_RX_FIFO_WATERMARK_EN BIT(26) +#define S_RX_FIFO_LAST_EN BIT(27) +#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ + S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) + +/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ +#define WATERMARK_MSK GENMASK(5, 0) + +/* GENI_TX_FIFO_STATUS fields */ +#define TX_FIFO_WC GENMASK(27, 0) + +/* GENI_RX_FIFO_STATUS fields */ +#define RX_LAST BIT(31) +#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) +#define RX_LAST_BYTE_VALID_SHFT 28 +#define RX_FIFO_WC_MSK GENMASK(24, 0) + +/* SE_GENI_IOS fields */ +#define IO2_DATA_IN BIT(1) +#define RX_DATA_IN BIT(0) + +/* SE_DMA_TX_IRQ_STAT Register fields */ +#define TX_DMA_DONE BIT(0) +#define TX_EOT BIT(1) +#define TX_SBE BIT(2) +#define TX_RESET_DONE BIT(3) + +/* SE_DMA_RX_IRQ_STAT Register fields */ +#define RX_DMA_DONE BIT(0) +#define RX_EOT BIT(1) +#define RX_SBE BIT(2) +#define RX_RESET_DONE BIT(3) +#define RX_FLUSH_DONE BIT(4) +#define RX_DMA_PARITY_ERR BIT(5) +#define RX_DMA_BREAK GENMASK(8, 7) +#define RX_GENI_GP_IRQ GENMASK(10, 5) +#define RX_GENI_CANCEL_IRQ BIT(11) +#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) + +/* SE_HW_PARAM_0 fields */ +#define TX_FIFO_WIDTH_MSK GENMASK(29, 24) +#define TX_FIFO_WIDTH_SHFT 24 +/* + * For QUP HW Version >= 3.10 Tx fifo depth support is increased + * to 256bytes and corresponding bits are 16 to 23 + */ +#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) +#define TX_FIFO_DEPTH_MSK GENMASK(21, 16) +#define TX_FIFO_DEPTH_SHFT 16 + +/* SE_HW_PARAM_1 fields */ +#define RX_FIFO_WIDTH_MSK GENMASK(29, 24) +#define RX_FIFO_WIDTH_SHFT 24 +/* + * For QUP HW Version >= 3.10 Rx fifo depth support is increased + * to 256bytes and corresponding bits are 16 to 23 + */ +#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) +#define RX_FIFO_DEPTH_MSK GENMASK(21, 16) +#define RX_FIFO_DEPTH_SHFT 16 + +#define HW_VER_MAJOR_MASK GENMASK(31, 28) +#define HW_VER_MAJOR_SHFT 28 +#define HW_VER_MINOR_MASK GENMASK(27, 16) +#define HW_VER_MINOR_SHFT 16 +#define HW_VER_STEP_MASK GENMASK(15, 0) + +#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) +#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) +#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) + +/* QUP SE VERSION value for major number 2 and minor number 5 */ +#define QUP_SE_VERSION_2_5 0x20050000 + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index efb77978a65..189e6eb31aa 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -416,7 +416,7 @@ config TRACE_EARLY_ADDR config CIRCBUF bool "Enable circular buffer support" -source lib/dhry/Kconfig +source "lib/dhry/Kconfig" menu "Security support" @@ -429,10 +429,10 @@ config AES supported by the algorithm but only a 128-bit key is supported at present. -source lib/ecdsa/Kconfig -source lib/rsa/Kconfig -source lib/crypto/Kconfig -source lib/crypt/Kconfig +source "lib/ecdsa/Kconfig" +source "lib/rsa/Kconfig" +source "lib/crypto/Kconfig" +source "lib/crypt/Kconfig" config TPM bool "Trusted Platform Module (TPM) Support" @@ -1081,9 +1081,9 @@ config SMBIOS_PARSER help A simple parser for SMBIOS data. -source lib/efi/Kconfig -source lib/efi_loader/Kconfig -source lib/optee/Kconfig +source "lib/efi/Kconfig" +source "lib/efi_loader/Kconfig" +source "lib/optee/Kconfig" config TEST_FDTDEC bool "enable fdtdec test" @@ -1148,4 +1148,4 @@ config PHANDLE_CHECK_SEQ endmenu -source lib/fwu_updates/Kconfig +source "lib/fwu_updates/Kconfig" diff --git a/lib/charset.c b/lib/charset.c index df4f0407485..182c92a50c4 100644 --- a/lib/charset.c +++ b/lib/charset.c @@ -387,7 +387,7 @@ int u16_strcasecmp(const u16 *s1, const u16 *s2) * > 0 if the first different u16 in s1 is greater than the * corresponding u16 in s2 */ -int u16_strncmp(const u16 *s1, const u16 *s2, size_t n) +int __efi_runtime u16_strncmp(const u16 *s1, const u16 *s2, size_t n) { int ret = 0; diff --git a/lib/crypto/x509_cert_parser.c b/lib/crypto/x509_cert_parser.c index a0f0689118f..34de75a3ece 100644 --- a/lib/crypto/x509_cert_parser.c +++ b/lib/crypto/x509_cert_parser.c @@ -535,7 +535,7 @@ int x509_process_extension(void *context, size_t hdrlen, * Decode an ASN.1 universal time or generalised time field into a struct the * kernel can handle and check it for validity. The time is decoded thus: * - * [RFC5280 §4.1.2.5] + * [RFC5280 paragraph 74.1.2.5] * CAs conforming to this profile MUST always encode certificate validity * dates through the year 2049 as UTCTime; certificate validity dates in * 2050 or later MUST be encoded as GeneralizedTime. Conforming diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e13a6f9f4c3..430bb7f0f7d 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -62,6 +62,22 @@ config EFI_VARIABLE_FILE_STORE Select this option if you want non-volatile UEFI variables to be stored as file /ubootefi.var on the EFI system partition. +config EFI_RT_VOLATILE_STORE + bool "Allow variable runtime services in volatile storage (e.g RAM)" + depends on EFI_VARIABLE_FILE_STORE + help + When EFI variables are stored on file we don't allow SetVariableRT, + since the OS doesn't know how to write that file. At he same time + we copy runtime variables in DRAM and support GetVariableRT + + Enable this option to allow SetVariableRT on the RAM backend of + the EFI variable storage. The OS will be responsible for syncing + the RAM contents to the file, otherwise any changes made during + runtime won't persist reboots. + Authenticated variables are not supported. Note that this will + violate the EFI spec since writing auth variables will return + EFI_INVALID_PARAMETER + config EFI_MM_COMM_TEE bool "UEFI variables storage service via the trusted world" depends on OPTEE @@ -129,7 +145,7 @@ if EFI_VARIABLES_PRESEED config EFI_VAR_SEED_FILE string "File with initial values of non-volatile UEFI variables" - default ubootefi.var + default "ubootefi.var" help File with initial values of non-volatile UEFI variables. The file must be in the same format as the storage in the EFI system partition. The diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index 58761fae784..6918fd5e48a 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -549,11 +549,6 @@ efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) out: free(load_options); - if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) { - if (efi_initrd_deregister() != EFI_SUCCESS) - log_err("Failed to remove loadfile2 for initrd\n"); - } - /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */ list_for_each_entry(evt, &efi_events, link) { if (evt->group && diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c index 2b467b55481..67d1f75d525 100644 --- a/lib/efi_loader/efi_load_initrd.c +++ b/lib/efi_loader/efi_load_initrd.c @@ -184,6 +184,50 @@ out: } /** + * efi_initrd_deregister() - delete the handle for loading initial RAM disk + * + * This will delete the handle containing the Linux specific vendor device + * path and EFI_LOAD_FILE2_PROTOCOL for loading an initrd + * + * Return: status code + */ +efi_status_t efi_initrd_deregister(void) +{ + efi_status_t ret; + + if (!efi_initrd_handle) + return EFI_SUCCESS; + + ret = efi_uninstall_multiple_protocol_interfaces(efi_initrd_handle, + /* initramfs */ + &efi_guid_device_path, + &dp_lf2_handle, + /* LOAD_FILE2 */ + &efi_guid_load_file2_protocol, + &efi_lf2_protocol, + NULL); + efi_initrd_handle = NULL; + + return ret; +} + +/** + * efi_initrd_return_notify() - return to efibootmgr callback + * + * @event: the event for which this notification function is registered + * @context: event context + */ +static void EFIAPI efi_initrd_return_notify(struct efi_event *event, + void *context) +{ + efi_status_t ret; + + EFI_ENTRY("%p, %p", event, context); + ret = efi_initrd_deregister(); + EFI_EXIT(ret); +} + +/** * efi_initrd_register() - create handle for loading initial RAM disk * * This function creates a new handle and installs a Linux specific vendor @@ -196,6 +240,7 @@ out: efi_status_t efi_initrd_register(void) { efi_status_t ret; + struct efi_event *event; /* * Allow the user to continue if Boot#### file path is not set for @@ -214,34 +259,17 @@ efi_status_t efi_initrd_register(void) &efi_guid_load_file2_protocol, &efi_lf2_protocol, NULL); + if (ret != EFI_SUCCESS) { + log_err("installing EFI_LOAD_FILE2_PROTOCOL failed\n"); + return ret; + } - return ret; -} - -/** - * efi_initrd_deregister() - delete the handle for loading initial RAM disk - * - * This will delete the handle containing the Linux specific vendor device - * path and EFI_LOAD_FILE2_PROTOCOL for loading an initrd - * - * Return: status code - */ -efi_status_t efi_initrd_deregister(void) -{ - efi_status_t ret; - - if (!efi_initrd_handle) - return EFI_SUCCESS; - - ret = efi_uninstall_multiple_protocol_interfaces(efi_initrd_handle, - /* initramfs */ - &efi_guid_device_path, - &dp_lf2_handle, - /* LOAD_FILE2 */ - &efi_guid_load_file2_protocol, - &efi_lf2_protocol, - NULL); - efi_initrd_handle = NULL; + ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, + efi_initrd_return_notify, NULL, + &efi_guid_event_group_return_to_efibootmgr, + &event); + if (ret != EFI_SUCCESS) + log_err("Creating event failed\n"); return ret; } diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index a61c9a77b13..73831c527e0 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -10,6 +10,7 @@ #include <dm.h> #include <elf.h> #include <efi_loader.h> +#include <efi_variable.h> #include <log.h> #include <malloc.h> #include <rtc.h> @@ -110,6 +111,7 @@ static __efi_runtime_data efi_uintn_t efi_descriptor_size; */ efi_status_t efi_init_runtime_supported(void) { + const efi_guid_t efi_guid_efi_rt_var_file = U_BOOT_EFI_RT_VAR_FILE_GUID; efi_status_t ret; struct efi_rt_properties_table *rt_table; @@ -127,6 +129,46 @@ efi_status_t efi_init_runtime_supported(void) EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP | EFI_RT_SUPPORTED_CONVERT_POINTER; + if (IS_ENABLED(CONFIG_EFI_RT_VOLATILE_STORE)) { + u8 s = 0; + + ret = efi_set_variable_int(u"RTStorageVolatile", + &efi_guid_efi_rt_var_file, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_READ_ONLY, + sizeof(EFI_VAR_FILE_NAME), + EFI_VAR_FILE_NAME, false); + if (ret != EFI_SUCCESS) { + log_err("Failed to set RTStorageVolatile\n"); + return ret; + } + /* + * This variable needs to be visible so users can read it, + * but the real contents are going to be filled during + * GetVariable + */ + ret = efi_set_variable_int(u"VarToFile", + &efi_guid_efi_rt_var_file, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_READ_ONLY, + sizeof(s), + &s, false); + if (ret != EFI_SUCCESS) { + log_err("Failed to set VarToFile\n"); + efi_set_variable_int(u"RTStorageVolatile", + &efi_guid_efi_rt_var_file, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_READ_ONLY, + 0, NULL, false); + + return ret; + } + rt_table->runtime_services_supported |= EFI_RT_SUPPORTED_SET_VARIABLE; + } + /* * This value must be synced with efi_runtime_detach_list * as well as efi_runtime_services. diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index aa8feffd3ec..961139f005a 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -182,7 +182,8 @@ efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *guid, { efi_status_t ret; - ret = efi_get_variable_mem(variable_name, guid, attributes, data_size, data, NULL); + ret = efi_get_variable_mem(variable_name, guid, attributes, data_size, + data, NULL, EFI_VARIABLE_RUNTIME_ACCESS); /* Remove EFI_VARIABLE_READ_ONLY flag */ if (attributes) @@ -195,7 +196,8 @@ efi_status_t __efi_runtime EFIAPI efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, u16 *variable_name, efi_guid_t *guid) { - return efi_get_next_variable_name_mem(variable_name_size, variable_name, guid); + return efi_get_next_variable_name_mem(variable_name_size, variable_name, + guid, EFI_VARIABLE_RUNTIME_ACCESS); } /** @@ -419,7 +421,7 @@ void *efi_get_var(const u16 *name, const efi_guid_t *vendor, efi_uintn_t *size) } /** - * efi_var_collect() - Copy EFI variables mstching attributes mask + * efi_var_collect() - Copy EFI variables matching attributes mask * * @bufp: buffer containing variable collection * @lenp: buffer length diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 6c21cec5d45..940ab663882 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -61,6 +61,23 @@ efi_var_mem_compare(struct efi_var_entry *var, const efi_guid_t *guid, return match; } +/** + * efi_var_entry_len() - Get the entry len including headers & name + * + * @var: pointer to variable start + * + * Return: 8-byte aligned variable entry length + */ + +u32 __efi_runtime efi_var_entry_len(struct efi_var_entry *var) +{ + if (!var) + return 0; + + return ALIGN((sizeof(u16) * (u16_strlen(var->name) + 1)) + + var->length + sizeof(*var), 8); +} + struct efi_var_entry __efi_runtime *efi_var_mem_find(const efi_guid_t *guid, const u16 *name, struct efi_var_entry **next) @@ -185,53 +202,6 @@ u64 __efi_runtime efi_var_mem_free(void) } /** - * efi_var_mem_bs_del() - delete boot service only variables - */ -static void efi_var_mem_bs_del(void) -{ - struct efi_var_entry *var = efi_var_buf->var; - - for (;;) { - struct efi_var_entry *last; - - last = (struct efi_var_entry *) - ((uintptr_t)efi_var_buf + efi_var_buf->length); - if (var >= last) - break; - if (var->attr & EFI_VARIABLE_RUNTIME_ACCESS) { - u16 *data; - - /* skip variable */ - for (data = var->name; *data; ++data) - ; - ++data; - var = (struct efi_var_entry *) - ALIGN((uintptr_t)data + var->length, 8); - } else { - /* delete variable */ - efi_var_mem_del(var); - } - } -} - -/** - * efi_var_mem_notify_exit_boot_services() - ExitBootService callback - * - * @event: callback event - * @context: callback context - */ -static void EFIAPI -efi_var_mem_notify_exit_boot_services(struct efi_event *event, void *context) -{ - EFI_ENTRY("%p, %p", event, context); - - /* Delete boot service only variables */ - efi_var_mem_bs_del(); - - EFI_EXIT(EFI_SUCCESS); -} - -/** * efi_var_mem_notify_exit_boot_services() - SetVirtualMemoryMap callback * * @event: callback event @@ -261,11 +231,7 @@ efi_status_t efi_var_mem_init(void) efi_var_buf->magic = EFI_VAR_FILE_MAGIC; efi_var_buf->length = (uintptr_t)efi_var_buf->var - (uintptr_t)efi_var_buf; - /* crc32 for 0 bytes = 0 */ - ret = efi_create_event(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_CALLBACK, - efi_var_mem_notify_exit_boot_services, NULL, - NULL, &event); if (ret != EFI_SUCCESS) return ret; ret = efi_create_event(EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, TPL_CALLBACK, @@ -276,10 +242,71 @@ efi_status_t efi_var_mem_init(void) return ret; } +/** + * efi_var_collect_mem() - Copy EFI variables matching attributes mask from + * efi_var_buf + * + * @buf: buffer containing variable collection + * @lenp: buffer length + * @mask: mask of matched attributes + * + * Return: Status code + */ +efi_status_t __efi_runtime +efi_var_collect_mem(struct efi_var_file *buf, efi_uintn_t *lenp, u32 mask) +{ + static struct efi_var_file __efi_runtime_data hdr = { + .magic = EFI_VAR_FILE_MAGIC, + }; + struct efi_var_entry *last, *var, *var_to; + + hdr.length = sizeof(struct efi_var_file); + + var = efi_var_buf->var; + last = (struct efi_var_entry *) + ((uintptr_t)efi_var_buf + efi_var_buf->length); + if (buf) + var_to = buf->var; + + while (var < last) { + u32 len = efi_var_entry_len(var); + + if ((var->attr & mask) != mask) { + var = (void *)((uintptr_t)var + len); + continue; + } + + hdr.length += len; + + if (buf && hdr.length <= *lenp) { + efi_memcpy_runtime(var_to, var, len); + var_to = (void *)var_to + len; + } + var = (void *)var + len; + } + + if (!buf && hdr.length <= *lenp) { + *lenp = hdr.length; + return EFI_INVALID_PARAMETER; + } + + if (!buf || hdr.length > *lenp) { + *lenp = hdr.length; + return EFI_BUFFER_TOO_SMALL; + } + hdr.crc32 = crc32(0, (u8 *)buf->var, + hdr.length - sizeof(struct efi_var_file)); + + efi_memcpy_runtime(buf, &hdr, sizeof(hdr)); + *lenp = hdr.length; + + return EFI_SUCCESS; +} + efi_status_t __efi_runtime efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, efi_uintn_t *data_size, void *data, - u64 *timep) + u64 *timep, u32 mask) { efi_uintn_t old_size; struct efi_var_entry *var; @@ -291,11 +318,22 @@ efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, if (!var) return EFI_NOT_FOUND; + /* + * This function is used at runtime to dump EFI variables. + * The memory backend we keep around has BS-only variables as + * well. At runtime we filter them here + */ + if (mask && !((var->attr & mask) == mask)) + return EFI_NOT_FOUND; + if (attributes) *attributes = var->attr; if (timep) *timep = var->time; + if (!u16_strcmp(variable_name, u"VarToFile")) + return efi_var_collect_mem(data, data_size, EFI_VARIABLE_NON_VOLATILE); + old_size = *data_size; *data_size = var->length; if (old_size < var->length) @@ -315,7 +353,8 @@ efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, efi_status_t __efi_runtime efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, - u16 *variable_name, efi_guid_t *vendor) + u16 *variable_name, efi_guid_t *vendor, + u32 mask) { struct efi_var_entry *var; efi_uintn_t len, old_size; @@ -324,6 +363,7 @@ efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, if (!variable_name_size || !variable_name || !vendor) return EFI_INVALID_PARAMETER; +skip: len = *variable_name_size >> 1; if (u16_strnlen(variable_name, len) == len) return EFI_INVALID_PARAMETER; @@ -347,6 +387,11 @@ efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, efi_memcpy_runtime(variable_name, var->name, *variable_name_size); efi_memcpy_runtime(vendor, &var->guid, sizeof(efi_guid_t)); + if (mask && !((var->attr & mask) == mask)) { + *variable_name_size = old_size; + goto skip; + } + return EFI_SUCCESS; } diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index e6c1219a11c..0cbed53d1db 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -209,27 +209,32 @@ efi_get_variable_int(const u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, efi_uintn_t *data_size, void *data, u64 *timep) { - return efi_get_variable_mem(variable_name, vendor, attributes, data_size, data, timep); + return efi_get_variable_mem(variable_name, vendor, attributes, data_size, + data, timep, 0); } efi_status_t __efi_runtime efi_get_next_variable_name_int(efi_uintn_t *variable_name_size, u16 *variable_name, efi_guid_t *vendor) { - return efi_get_next_variable_name_mem(variable_name_size, variable_name, vendor); + return efi_get_next_variable_name_mem(variable_name_size, variable_name, + vendor, 0); } -efi_status_t efi_set_variable_int(const u16 *variable_name, - const efi_guid_t *vendor, - u32 attributes, efi_uintn_t data_size, - const void *data, bool ro_check) +/** + * setvariable_allowed() - checks defined by the UEFI spec for setvariable + * + * @variable_name: name of the variable + * @vendor: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer with the variable value + * @data: buffer with the variable value + * Return: status code + */ +static efi_status_t __efi_runtime +setvariable_allowed(const u16 *variable_name, const efi_guid_t *vendor, + u32 attributes, efi_uintn_t data_size, const void *data) { - struct efi_var_entry *var; - efi_uintn_t ret; - bool append, delete; - u64 time = 0; - enum efi_auth_var_type var_type; - if (!variable_name || !*variable_name || !vendor) return EFI_INVALID_PARAMETER; @@ -261,6 +266,25 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, !(attributes & EFI_VARIABLE_BOOTSERVICE_ACCESS))) return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} + +efi_status_t efi_set_variable_int(const u16 *variable_name, + const efi_guid_t *vendor, + u32 attributes, efi_uintn_t data_size, + const void *data, bool ro_check) +{ + struct efi_var_entry *var; + efi_uintn_t ret; + bool append, delete; + u64 time = 0; + enum efi_auth_var_type var_type; + + ret = setvariable_allowed(variable_name, vendor, attributes, data_size, + data); + if (ret != EFI_SUCCESS) + return ret; + /* check if a variable exists */ var = efi_var_mem_find(vendor, variable_name, NULL); append = !!(attributes & EFI_VARIABLE_APPEND_WRITE); @@ -454,7 +478,79 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, u32 attributes, efi_uintn_t data_size, const void *data) { - return EFI_UNSUPPORTED; + struct efi_var_entry *var; + efi_uintn_t ret; + bool append, delete; + u64 time = 0; + + if (!IS_ENABLED(CONFIG_EFI_RT_VOLATILE_STORE)) + return EFI_UNSUPPORTED; + + /* + * Authenticated variables are not supported. The EFI spec + * in §32.3.6 requires keys to be stored in non-volatile storage which + * is tamper and delete resistant. + * The rest of the checks are in setvariable_allowed() + */ + if (attributes & EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS) + return EFI_INVALID_PARAMETER; + + ret = setvariable_allowed(variable_name, vendor, attributes, data_size, + data); + if (ret != EFI_SUCCESS) + return ret; + + /* check if a variable exists */ + var = efi_var_mem_find(vendor, variable_name, NULL); + append = !!(attributes & EFI_VARIABLE_APPEND_WRITE); + attributes &= ~EFI_VARIABLE_APPEND_WRITE; + delete = !append && (!data_size || !attributes); + + /* BS only variables are hidden deny writing them */ + if (!delete && !(attributes & EFI_VARIABLE_RUNTIME_ACCESS)) + return EFI_INVALID_PARAMETER; + + if (var) { + if (var->attr & EFI_VARIABLE_READ_ONLY || + !(var->attr & EFI_VARIABLE_NON_VOLATILE)) + return EFI_WRITE_PROTECTED; + + /* attributes won't be changed */ + if (!delete && (((var->attr & ~EFI_VARIABLE_READ_ONLY) != + (attributes & ~EFI_VARIABLE_READ_ONLY)))) + return EFI_INVALID_PARAMETER; + time = var->time; + } else { + if (!(attributes & EFI_VARIABLE_NON_VOLATILE)) + return EFI_INVALID_PARAMETER; + if (append && !data_size) + return EFI_SUCCESS; + if (delete) + return EFI_NOT_FOUND; + } + + if (delete) { + /* EFI_NOT_FOUND has been handled before */ + attributes = var->attr; + ret = EFI_SUCCESS; + } else if (append && var) { + u16 *old_data = (void *)((uintptr_t)var->name + + sizeof(u16) * (u16_strlen(var->name) + 1)); + + ret = efi_var_mem_ins(variable_name, vendor, attributes, + var->length, old_data, data_size, data, + time); + } else { + ret = efi_var_mem_ins(variable_name, vendor, attributes, + data_size, data, 0, NULL, time); + } + + if (ret != EFI_SUCCESS) + return ret; + /* We are always inserting new variables, get rid of the old copy */ + efi_var_mem_del(var); + + return EFI_SUCCESS; } /** diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index dde135fd9f8..4f1aa298da1 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -959,11 +959,6 @@ void efi_variables_boot_exit_notify(void) log_err("Unable to notify the MM partition for ExitBootServices\n"); free(comm_buf); - /* - * Populate the list for runtime variables. - * asking EFI_VARIABLE_RUNTIME_ACCESS is redundant, since - * efi_var_mem_notify_exit_boot_services will clean those, but that's fine - */ ret = efi_var_collect(&var_buf, &len, EFI_VARIABLE_RUNTIME_ACCESS); if (ret != EFI_SUCCESS) log_err("Can't populate EFI variables. No runtime variables will be available\n"); diff --git a/lib/efi_selftest/efi_selftest_variables_runtime.c b/lib/efi_selftest/efi_selftest_variables_runtime.c index 4700d942410..afa91be62c8 100644 --- a/lib/efi_selftest/efi_selftest_variables_runtime.c +++ b/lib/efi_selftest/efi_selftest_variables_runtime.c @@ -10,6 +10,8 @@ */ #include <efi_selftest.h> +#include <efi_variable.h> +#include <u-boot/crc.h> #define EFI_ST_MAX_DATA_SIZE 16 #define EFI_ST_MAX_VARNAME_SIZE 40 @@ -17,6 +19,8 @@ static struct efi_boot_services *boottime; static struct efi_runtime_services *runtime; static const efi_guid_t guid_vendor0 = EFI_GLOBAL_VARIABLE_GUID; +static const efi_guid_t __efi_runtime_data efi_rt_var_guid = + U_BOOT_EFI_RT_VAR_FILE_GUID; /* * Setup unit test. @@ -41,15 +45,18 @@ static int setup(const efi_handle_t img_handle, static int execute(void) { efi_status_t ret; - efi_uintn_t len; + efi_uintn_t len, avail, append_len = 17; u32 attr; u8 v[16] = {0x5d, 0xd1, 0x5e, 0x51, 0x5a, 0x05, 0xc7, 0x0c, 0x35, 0x4a, 0xae, 0x87, 0xa5, 0xdf, 0x0f, 0x65,}; + u8 v2[CONFIG_EFI_VAR_BUF_SIZE]; u8 data[EFI_ST_MAX_DATA_SIZE]; + u8 data2[CONFIG_EFI_VAR_BUF_SIZE]; u16 varname[EFI_ST_MAX_VARNAME_SIZE]; efi_guid_t guid; u64 max_storage, rem_storage, max_size; + memset(v2, 0x1, sizeof(v2)); ret = runtime->query_variable_info(EFI_VARIABLE_BOOTSERVICE_ACCESS, &max_storage, &rem_storage, &max_size); @@ -62,9 +69,216 @@ static int execute(void) EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, 3, v + 4); - if (ret != EFI_UNSUPPORTED) { - efi_st_error("SetVariable failed\n"); - return EFI_ST_FAILURE; + if (IS_ENABLED(CONFIG_EFI_RT_VOLATILE_STORE)) { + efi_uintn_t prev_len, delta; + struct efi_var_entry *var; + struct efi_var_file *hdr; + + /* At runtime only non-volatile variables may be set. */ + if (ret != EFI_INVALID_PARAMETER) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* runtime atttribute must be set */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + 3, v + 4); + if (ret != EFI_INVALID_PARAMETER) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + len = sizeof(data); + ret = runtime->get_variable(u"RTStorageVolatile", + &efi_rt_var_guid, + &attr, &len, data); + if (ret != EFI_SUCCESS) { + efi_st_error("GetVariable failed\n"); + return EFI_ST_FAILURE; + } + + if (len != sizeof(EFI_VAR_FILE_NAME) || + memcmp(data, EFI_VAR_FILE_NAME, sizeof(EFI_VAR_FILE_NAME))) { + data[len - 1] = 0; + efi_st_error("RTStorageVolatile = %s\n", data); + return EFI_ST_FAILURE; + } + + len = sizeof(data2); + ret = runtime->get_variable(u"VarToFile", &efi_rt_var_guid, + &attr, &len, data2); + if (ret != EFI_SUCCESS) { + efi_st_error("GetVariable failed\n"); + return EFI_ST_FAILURE; + } + /* + * VarToFile size must change once a variable is inserted + * Store it now, we'll use it later + */ + prev_len = len; + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + sizeof(v2), + v2); + /* + * This will try to update VarToFile as well and must fail, + * without changing or deleting VarToFile + */ + if (ret != EFI_OUT_OF_RESOURCES) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + len = sizeof(data2); + ret = runtime->get_variable(u"VarToFile", &efi_rt_var_guid, + &attr, &len, data2); + if (ret != EFI_SUCCESS || prev_len != len) { + efi_st_error("Get/SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* Add an 8byte aligned variable */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + sizeof(v), v); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* Delete it by setting the attrs to 0 */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + 0, sizeof(v), v); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* Add it back */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + sizeof(v), v); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* Delete it again by setting the size to 0 */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + 0, NULL); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* Delete it again and make sure it's not there */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + 0, NULL); + if (ret != EFI_NOT_FOUND) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* + * Add a non-aligned variable + * VarToFile updates must include efi_st_var0 + */ + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + 9, v + 4); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + var = efi_var_mem_find(&guid_vendor0, u"efi_st_var0", NULL); + if (!var) { + efi_st_error("GetVariable failed\n"); + return EFI_ST_FAILURE; + } + delta = efi_var_entry_len(var); + len = sizeof(data2); + ret = runtime->get_variable(u"VarToFile", &efi_rt_var_guid, + &attr, &len, data2); + if (ret != EFI_SUCCESS || prev_len + delta != len) { + efi_st_error("Get/SetVariable failed\n"); + return EFI_ST_FAILURE; + } + + /* + * Append on an existing variable must update VarToFile + * Our variable entries are 8-byte aligned. + * Adding a single byte will fit on the existing space + */ + prev_len = len; + avail = efi_var_entry_len(var) - + (sizeof(u16) * (u16_strlen(var->name) + 1) + sizeof(*var)) - + var->length; + if (avail >= append_len) + delta = 0; + else + delta = ALIGN(append_len - avail, 8); + ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_APPEND_WRITE | + EFI_VARIABLE_NON_VOLATILE, + append_len, v2); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + len = sizeof(data2); + ret = runtime->get_variable(u"VarToFile", &efi_rt_var_guid, + &attr, &len, data2); + if (ret != EFI_SUCCESS) { + efi_st_error("GetVariable failed\n"); + return EFI_ST_FAILURE; + } + if (prev_len + delta != len) { + efi_st_error("Unexpected VarToFile size"); + return EFI_ST_FAILURE; + } + + /* Make sure that variable contains a valid file */ + hdr = (struct efi_var_file *)data2; + if (hdr->magic != EFI_VAR_FILE_MAGIC || + len != hdr->length || + hdr->crc32 != crc32(0, (u8 *)((uintptr_t)data2 + sizeof(struct efi_var_file)), + len - sizeof(struct efi_var_file))) { + efi_st_error("VarToFile invalid header\n"); + return EFI_ST_FAILURE; + } + + /* Variables that are BS, RT and volatile are RO after EBS */ + ret = runtime->set_variable(u"VarToFile", &efi_rt_var_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + sizeof(v), v); + if (ret != EFI_WRITE_PROTECTED) { + efi_st_error("Get/SetVariable failed\n"); + return EFI_ST_FAILURE; + } + } else { + if (ret != EFI_UNSUPPORTED) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } } len = EFI_ST_MAX_DATA_SIZE; ret = runtime->get_variable(u"PlatformLangCodes", &guid_vendor0, diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts index 5e2429c6170..790f3c508f1 100644 --- a/scripts/Makefile.dts +++ b/scripts/Makefile.dts @@ -1,3 +1,16 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST))) + +ifeq ($(CONFIG_OF_UPSTREAM_BUILD_VENDOR),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := $(srctree)/dts/upstream/src/arm64 +else +dt_dir := $(srctree)/dts/upstream/src/$(ARCH) +endif + +dtb-vendor_dts := $(patsubst %.dts,%.dtb,$(wildcard $(dt_dir)/$(subst ",,$(CONFIG_OF_UPSTREAM_VENDOR))/*.dts)) + +dtb-y += $(subst $(dt_dir)/,,$(dtb-vendor_dts)) + +endif diff --git a/tools/binman/etype/nxp_imx8mimage.py b/tools/binman/etype/nxp_imx8mimage.py new file mode 100644 index 00000000000..3585120b79b --- /dev/null +++ b/tools/binman/etype/nxp_imx8mimage.py @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2023-2024 Marek Vasut <marex@denx.de> +# Written with much help from Simon Glass <sjg@chromium.org> +# +# Entry-type module for generating the i.MX8M mkimage -T imx8mimage +# configuration file and invocation of mkimage -T imx8mimage on the +# configuration file and input data. +# + +from collections import OrderedDict + +from binman.entry import Entry +from binman.etype.mkimage import Entry_mkimage +from binman.etype.section import Entry_section +from binman import elf +from dtoc import fdt_util +from u_boot_pylib import tools + +class Entry_nxp_imx8mimage(Entry_mkimage): + """NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker + + Properties / Entry arguments: + - nxp,boot-from - device to boot from (e.g. 'sd') + - nxp,loader-address - loader address (SPL text base) + - nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus) + """ + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.required_props = ['nxp,boot-from', 'nxp,rom-version', 'nxp,loader-address'] + + def ReadNode(self): + super().ReadNode() + self.boot_from = fdt_util.GetString(self._node, 'nxp,boot-from') + self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address') + self.rom_version = fdt_util.GetInt(self._node, 'nxp,rom-version') + self.ReadEntries() + + def BuildSectionData(self, required): + data, input_fname, uniq = self.collect_contents_to_file( + self._entries.values(), 'input') + # Generate mkimage configuration file similar to imx8mimage.cfg + # and pass it to mkimage to generate SPL image for us here. + cfg_fname = tools.get_output_filename('nxp.imx8mimage.cfg.%s' % uniq) + with open(cfg_fname, 'w') as outf: + print('ROM_VERSION v%d' % self.rom_version, file=outf) + print('BOOT_FROM %s' % self.boot_from, file=outf) + print('LOADER %s %#x' % (input_fname, self.loader_address), file=outf) + + output_fname = tools.get_output_filename(f'cfg-out.{uniq}') + args = ['-d', input_fname, '-n', cfg_fname, '-T', 'imx8mimage', + output_fname] + if self.mkimage.run_cmd(*args) is not None: + return tools.read_file(output_fname) + else: + # Bintool is missing; just use the input data as the output + self.record_missing_bintool(self.mkimage) + return data + + def SetImagePos(self, image_pos): + # Customized SoC specific SetImagePos which skips the mkimage etype + # implementation and removes the 0x48 offset introduced there. That + # offset is only used for uImage/fitImage, which is not the case in + # here. + upto = 0x00 + for entry in super().GetEntries().values(): + entry.SetOffsetSize(upto, None) + + # Give up if any entries lack a size + if entry.size is None: + return + upto += entry.size + + Entry_section.SetImagePos(self, image_pos) |